diff --git a/.project b/.project new file mode 100644 index 000000000..4c9adf2ba --- /dev/null +++ b/.project @@ -0,0 +1,11 @@ + + + ChibiOS-RT (whole tree) + + + + + + + + diff --git a/boards/ARDUINO_MEGA/board.c b/boards/ARDUINO_MEGA/board.c new file mode 100644 index 000000000..a33d693ad --- /dev/null +++ b/boards/ARDUINO_MEGA/board.c @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(PORTA) + {VAL_PORTA, VAL_DDRA}, +#endif +#if defined(PORTB) + {VAL_PORTB, VAL_DDRB}, +#endif +#if defined(PORTC) + {VAL_PORTC, VAL_DDRC}, +#endif +#if defined(PORTD) + {VAL_PORTD, VAL_DDRD}, +#endif +#if defined(PORTE) + {VAL_PORTE, VAL_DDRE}, +#endif +#if defined(PORTF) + {VAL_PORTF, VAL_DDRF}, +#endif +#if defined(PORTG) + {VAL_PORTG, VAL_DDRG}, +#endif +#if defined(PORTH) + {VAL_PORTH, VAL_DDRH}, +#endif +#if defined(PORTJ) + {VAL_PORTJ, VAL_DDRJ}, +#endif +#if defined(PORTK) + {VAL_PORTK, VAL_DDRK}, +#endif +#if defined(PORTL) + {VAL_PORTL, VAL_DDRL}, +#endif +}; +#endif /* HAL_USE_PAL */ + +/** + * @brief Timer0 interrupt handler. + */ +CH_IRQ_HANDLER(TIMER0_COMPA_vect) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; + + /* + * Timer 0 setup. + */ + TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ + (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */ + (0 << COM0B1) | (0 << COM0B0); /* OC0B disabled. */ + TCCR0B = (0 << WGM02) | /* CTC mode. */ + (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */ + OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; /* Reset counter. */ + TIFR0 = (1 << OCF0A); /* Reset pending. */ + TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */ +} diff --git a/boards/ARDUINO_MEGA/board.h b/boards/ARDUINO_MEGA/board.h new file mode 100644 index 000000000..9dc3b09e4 --- /dev/null +++ b/boards/ARDUINO_MEGA/board.h @@ -0,0 +1,86 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Arduino Mega board. + */ + +/* + * Board identifier. + */ +#define BOARD_ARDUINO_MEGA +#define BOARD_NAME "Arduino Mega" + +/* All inputs with pull-ups */ +#define VAL_DDRA 0x00 +#define VAL_PORTA 0xFF + +/* All inputs except PB7 which has a LED connected */ +#define VAL_DDRB 0x80 +#define VAL_PORTB 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRC 0x00 +#define VAL_PORTC 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRD 0x00 +#define VAL_PORTD 0xFF + +/* All inputs except PE1 (Serial TX0) */ +#define VAL_DDRE 0x02 +#define VAL_PORTE 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRH 0x00 +#define VAL_PORTH 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRJ 0x00 +#define VAL_PORTJ 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRK 0x00 +#define VAL_PORTK 0xFF + +/* All inputs with pull-ups */ +#define VAL_DDRL 0x00 +#define VAL_PORTL 0xFF + +#define PORTB_LED1 7 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ARDUINO_MEGA/board.mk b/boards/ARDUINO_MEGA/board.mk new file mode 100644 index 000000000..8e7f1117e --- /dev/null +++ b/boards/ARDUINO_MEGA/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ARDUINO_MEGA/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ARDUINO_MEGA diff --git a/boards/EA_LPCXPRESSO_11C24/board.c b/boards/EA_LPCXPRESSO_11C24/board.c new file mode 100644 index 000000000..0e00ff2a3 --- /dev/null +++ b/boards/EA_LPCXPRESSO_11C24/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11C24 EA Board support - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR}, + {VAL_GPIO2DATA, VAL_GPIO2DIR}, + {VAL_GPIO3DATA, VAL_GPIO3DIR}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + lpc111x_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + */ + LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */ +} diff --git a/boards/EA_LPCXPRESSO_11C24/board.h b/boards/EA_LPCXPRESSO_11C24/board.h new file mode 100644 index 000000000..b8de6f790 --- /dev/null +++ b/boards/EA_LPCXPRESSO_11C24/board.h @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11C24 EA Board support - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso LPC11C24 + * board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_BB_LPC11C24 +#define BOARD_NAME "Embedded Artists LPCXpresso LPC11C24" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * SCK0 connection on this board. + */ +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED) +#define VAL_GPIO0DATA 0x00000000 + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR 0x00000000 +#define VAL_GPIO1DATA 0x00000000 + +/* + * GPIO 2 initial setup. + */ +#define VAL_GPIO2DIR 0x00000000 +#define VAL_GPIO2DATA 0x00000000 + +/* + * GPIO 3 initial setup. + */ +#define VAL_GPIO3DIR 0x00000000 +#define VAL_GPIO3DATA 0x00000000 + +/* + * Pin definitions. + */ +#define GPIO0_SW_ISP 1 +#define GPIO0_LED 7 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_11C24/board.mk b/boards/EA_LPCXPRESSO_11C24/board.mk new file mode 100644 index 000000000..d60e6ea6d --- /dev/null +++ b/boards/EA_LPCXPRESSO_11C24/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_11C24/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_11C24 diff --git a/boards/EA_LPCXPRESSO_BB_1114/board.c b/boards/EA_LPCXPRESSO_BB_1114/board.c new file mode 100644 index 000000000..a0af7d697 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1114/board.c @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR}, + {VAL_GPIO2DATA, VAL_GPIO2DIR}, + {VAL_GPIO3DATA, VAL_GPIO3DIR}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + lpc111x_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG + * you must comment that line first. + */ + LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */ + LPC_IOCON->R_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output + and makes it GPIO1_2. */ + LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/ + LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/ +} diff --git a/boards/EA_LPCXPRESSO_BB_1114/board.h b/boards/EA_LPCXPRESSO_BB_1114/board.h new file mode 100644 index 000000000..c27830d28 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1114/board.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter + * board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_BB_LPC1114 +#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1114" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * SCK0 connection on this board. + */ +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_LED2) +#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_LED2) + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \ + PAL_PORT_BIT(GPIO1_LED3R) | \ + PAL_PORT_BIT(GPIO1_LED3G) | \ + PAL_PORT_BIT(GPIO1_SPI0SEL) +#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED3B) | \ + PAL_PORT_BIT(GPIO1_LED3R) | \ + PAL_PORT_BIT(GPIO1_LED3G) | \ + PAL_PORT_BIT(GPIO1_SPI0SEL) + +/* + * GPIO 2 initial setup. + */ +#define VAL_GPIO2DIR 0x00000000 +#define VAL_GPIO2DATA 0x00000000 + +/* + * GPIO 3 initial setup. + */ +#define VAL_GPIO3DIR 0x00000000 +#define VAL_GPIO3DATA 0x00000000 + +/* + * Pin definitions. + */ +#define GPIO0_SW3 1 +#define GPIO0_OLEDSEL 2 +#define GPIO0_LED2 7 + +#define GPIO1_LED3B 2 +#define GPIO1_SW4 4 +#define GPIO1_LED3R 9 +#define GPIO1_LED3G 10 +#define GPIO1_SPI0SEL 11 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_BB_1114/board.mk b/boards/EA_LPCXPRESSO_BB_1114/board.mk new file mode 100644 index 000000000..affca2d05 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1114/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114 diff --git a/boards/EA_LPCXPRESSO_BB_11U14/board.c b/boards/EA_LPCXPRESSO_BB_11U14/board.c new file mode 100644 index 000000000..117e78c0e --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_11U14/board.c @@ -0,0 +1,66 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + lpc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG + * you must comment that line first. + */ + LPC_IOCON->PIO0_7 = 0x80; /* Disables pull-up on LED2 output. */ + LPC_IOCON->TRST_PIO0_14 = 0x81; /* Disables pull-up on LED3B output + and makes it GPIO1_2. */ + LPC_IOCON->PIO0_21 = 0x80; /* Disables pull-up on LED3R output.*/ + LPC_IOCON->PIO0_22 = 0x80; /* Disables pull-up on LED3G output.*/ + + /* SSP0 mapping.*/ + LPC_IOCON->PIO1_29 = 0x81; /* SCK0 without resistors. */ + LPC_IOCON->PIO0_8 = 0x81; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0x81; /* MOSI0 without resistors. */ + + /* USART mapping.*/ + LPC_IOCON->PIO0_18 = 0x81; /* RDX without resistors. */ + LPC_IOCON->PIO0_19 = 0x81; /* TDX without resistors. */ +} diff --git a/boards/EA_LPCXPRESSO_BB_11U14/board.h b/boards/EA_LPCXPRESSO_BB_11U14/board.h new file mode 100644 index 000000000..dac011460 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_11U14/board.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter + * board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_BB_LPC11U14 +#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC11U14" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * SCK0 connection on this board. + */ +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_USB_DPCTL) | \ + PAL_PORT_BIT(GPIO0_LED2) | \ + PAL_PORT_BIT(GPIO0_LED3B) | \ + PAL_PORT_BIT(GPIO0_LED3R) | \ + PAL_PORT_BIT(GPIO0_LED3G) | \ + PAL_PORT_BIT(GPIO0_SPI0SEL) +#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_LED2) | \ + PAL_PORT_BIT(GPIO0_LED3B) | \ + PAL_PORT_BIT(GPIO0_LED3R) | \ + PAL_PORT_BIT(GPIO0_LED3G) | \ + PAL_PORT_BIT(GPIO0_SPI0SEL) + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR 0x00000000 +#define VAL_GPIO1DATA 0x00000000 + +/* + * Pin definitions. + */ +#define GPIO0_SW3 1 +#define GPIO0_OLEDSEL 2 +#define GPIO0_USB_VBUS 3 +#define GPIO0_USB_DPCTL 6 +#define GPIO0_LED2 7 +#define GPIO0_SW4 16 +#define GPIO0_LED3B 14 +#define GPIO0_LED3R 21 +#define GPIO0_LED3G 22 +#define GPIO0_SPI0SEL 23 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_BB_11U14/board.mk b/boards/EA_LPCXPRESSO_BB_11U14/board.mk new file mode 100644 index 000000000..1c5d132d2 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_11U14/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_11U14/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_11U14 diff --git a/boards/EA_LPCXPRESSO_BB_1343/board.c b/boards/EA_LPCXPRESSO_BB_1343/board.c new file mode 100644 index 000000000..d25d93d20 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1343/board.c @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR}, + {VAL_GPIO2DATA, VAL_GPIO2DIR}, + {VAL_GPIO3DATA, VAL_GPIO3DIR}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + LPC13xx_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG + * you must comment that line first. + */ + LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */ + LPC_IOCON->R_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output + and makes it GPIO1_2. */ + LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/ + LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/ +} diff --git a/boards/EA_LPCXPRESSO_BB_1343/board.h b/boards/EA_LPCXPRESSO_BB_1343/board.h new file mode 100644 index 000000000..b5ad73dbd --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1343/board.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso Base Board with LPC1343 daughter + * board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_BB_LPC1343 +#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1343" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_LED2) +#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \ + PAL_PORT_BIT(GPIO0_LED2) + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \ + PAL_PORT_BIT(GPIO1_LED3R) | \ + PAL_PORT_BIT(GPIO1_LED3G) | \ + PAL_PORT_BIT(GPIO1_SPI0SEL) +#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED3B) | \ + PAL_PORT_BIT(GPIO1_LED3R) | \ + PAL_PORT_BIT(GPIO1_LED3G) | \ + PAL_PORT_BIT(GPIO1_SPI0SEL) + +/* + * GPIO 2 initial setup. + */ +#define VAL_GPIO2DIR 0x00000000 +#define VAL_GPIO2DATA 0x00000000 + +/* + * GPIO 3 initial setup. + */ +#define VAL_GPIO3DIR 0x00000000 +#define VAL_GPIO3DATA 0x00000000 + +/* + * Pin definitions. + */ +#define GPIO0_SW3 1 +#define GPIO0_OLEDSEL 2 +#define GPIO0_LED2 7 + +#define GPIO1_LED3B 2 +#define GPIO1_SW4 4 +#define GPIO1_LED3R 9 +#define GPIO1_LED3G 10 +#define GPIO1_SPI0SEL 11 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_BB_1343/board.mk b/boards/EA_LPCXPRESSO_BB_1343/board.mk new file mode 100644 index 000000000..da59e98c4 --- /dev/null +++ b/boards/EA_LPCXPRESSO_BB_1343/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343 diff --git a/boards/EA_LPCXPRESSO_LPC812/board.c b/boards/EA_LPCXPRESSO_LPC812/board.c new file mode 100644 index 000000000..1f1952dbf --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.c @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = {VAL_GPIO0DATA, VAL_GPIO0DIR}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void){ + + lpc8xx_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void){ + + /* Enable clocks to IOCON & SWM */ + LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7)); + +#if defined VAL_PIO0_0 + LPC_IOCON->PIO0_0 = PIN_RSVD|VAL_PIO0_0; +#endif +#if defined VAL_PIO0_1 + LPC_IOCON->PIO0_1 = PIN_RSVD|VAL_PIO0_1; +#endif +#if defined VAL_PIO0_2 + LPC_IOCON->PIO0_2 = PIN_RSVD|VAL_PIO0_2; +#endif +#if defined VAL_PIO0_3 + LPC_IOCON->PIO0_3 = PIN_RSVD|VAL_PIO0_3; +#endif +#if defined VAL_PIO0_4 + LPC_IOCON->PIO0_4 = PIN_RSVD|VAL_PIO0_4; +#endif +#if defined VAL_PIO0_5 + LPC_IOCON->PIO0_5 = PIN_RSVD|VAL_PIO0_5; +#endif +#if defined VAL_PIO0_6 + LPC_IOCON->PIO0_6 = PIN_RSVD|VAL_PIO0_6; +#endif +#if defined VAL_PIO0_7 + LPC_IOCON->PIO0_7 = PIN_RSVD|VAL_PIO0_7; +#endif +#if defined VAL_PIO0_8 + LPC_IOCON->PIO0_8 = PIN_RSVD|VAL_PIO0_8; +#endif +#if defined VAL_PIO0_9 + LPC_IOCON->PIO0_9 = PIN_RSVD|VAL_PIO0_9; +#endif +#if defined VAL_PIO0_10 + LPC_IOCON->PIO0_10 = PIN_RSVD|VAL_PIO0_10; +#endif +#if defined VAL_PIO0_11 + LPC_IOCON->PIO0_11 = PIN_RSVD|VAL_PIO0_11; +#endif +#if defined VAL_PIO0_12 + LPC_IOCON->PIO0_12 = PIN_RSVD|VAL_PIO0_12; +#endif +#if defined VAL_PIO0_13 + LPC_IOCON->PIO0_13 = PIN_RSVD|VAL_PIO0_13; +#endif +#if defined VAL_PIO0_14 + LPC_IOCON->PIO0_14 = PIN_RSVD|VAL_PIO0_14; +#endif +#if defined VAL_PIO0_15 + LPC_IOCON->PIO0_15 = PIN_RSVD|VAL_PIO0_15; +#endif +#if defined VAL_PIO0_16 + LPC_IOCON->PIO0_16 = PIN_RSVD|VAL_PIO0_16; +#endif +#if defined VAL_PIO0_17 + LPC_IOCON->PIO0_17 = PIN_RSVD|VAL_PIO0_17; +#endif + + +#if defined VAL_PINASSIGN0 + LPC_SWM->PINASSIGN0 = VAL_PINASSIGN0; +#endif +#if defined VAL_PINASSIGN1 + LPC_SWM->PINASSIGN1 = VAL_PINASSIGN1; +#endif +#if defined VAL_PINASSIGN2 + LPC_SWM->PINASSIGN2 = VAL_PINASSIGN2; +#endif +#if defined VAL_PINASSIGN3 + LPC_SWM->PINASSIGN3 = VAL_PINASSIGN3; +#endif +#if defined VAL_PINASSIGN4 + LPC_SWM->PINASSIGN4 = VAL_PINASSIGN4; +#endif +#if defined VAL_PINASSIGN5 + LPC_SWM->PINASSIGN5 = VAL_PINASSIGN5; +#endif +#if defined VAL_PINASSIGN6 + LPC_SWM->PINASSIGN6 = VAL_PINASSIGN6; +#endif +#if defined VAL_PINASSIGN7 + LPC_SWM->PINASSIGN7 = VAL_PINASSIGN7; +#endif +#if defined VAL_PINASSIGN8 + LPC_SWM->PINASSIGN8 = VAL_PINASSIGN8; +#endif + + /* Disable clocks to IOCON & SWM */ + LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7)); + +} + + diff --git a/boards/EA_LPCXPRESSO_LPC812/board.h b/boards/EA_LPCXPRESSO_LPC812/board.h new file mode 100644 index 000000000..0a1618292 --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.h @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso LPC812 board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_LPC812 +#define BOARD_NAME "Embedded Artists LPCXpresso LPC812" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the LPC8xx Reference Manual for details. + */ +/* Pull-up/down */ +#define PIN_MODE_NOPULL (0<<3) +#define PIN_MODE_PULLDOWN (1<<3) +#define PIN_MODE_PULLUP (2<<3) +#define PIN_MODE_REPEATER (3<<3) +/* Hysteresis */ +#define PIN_HYS_EN (1<<5) +/* Invert Input */ +#define PIN_INV_INPUT (1<<6) +/* Reserved bits */ +#define PIN_RSVD (1<<7) +/* I2C Mode */ +#define PIN_I2CMODE_STD (0<<8) +#define PIN_I2CMODE_STDIO (1<<8) +#define PIN_I2CMODE_FAST (2<<8) +/* Open Drain */ +#define PIN_OPEN_DRAIN (1<<10) +/* Input Filter Sample Clocks */ +#define PIN_SMODE_FILTER(n) ((n)<<11) +/* Input Filter clock divider */ +#define PIN_CLKDIV_FILTER(n) ((n)<<13) + +/* + * Pin definitions. + */ +#define LED_RED 7 +#define LED_BLUE 16 +#define LED_GREEN 17 + + +/* + * GPIO 0 initial setup. + */ +/*#define VAL_PIO0_0 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_1 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_2 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_3 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_4 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_5 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_6 PIN_MODE_PULLUP*/ +#define VAL_PIO0_7 PIN_MODE_NOPULL +/*#define VAL_PIO0_8 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_9 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_10 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_11 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_12 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_13 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_14 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_15 PIN_MODE_PULLUP*/ +#define VAL_PIO0_16 PIN_MODE_NOPULL +#define VAL_PIO0_17 PIN_MODE_NOPULL + + /* UART0: TXD = P0.4, RXD = P0.0)*/ +#define VAL_PINASSIGN0 ((0xFFFF0000) | (0<<8) | (4)) +/*#define VAL_PINASSIGN1 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN2 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN3 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN4 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN5 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN6 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN7 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN8 0xFFFFFFFF*/ + + +#define VAL_GPIO0DIR (PAL_PORT_BIT(LED_RED) | \ + PAL_PORT_BIT(LED_BLUE) | \ + PAL_PORT_BIT(LED_GREEN)) + +#define VAL_GPIO0DATA (PAL_PORT_BIT(LED_RED) | \ + PAL_PORT_BIT(LED_BLUE) | \ + PAL_PORT_BIT(LED_GREEN)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_LPC812/board.mk b/boards/EA_LPCXPRESSO_LPC812/board.mk new file mode 100644 index 000000000..de80424bb --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812 diff --git a/boards/MAPLEMINI_STM32_F103/board.c b/boards/MAPLEMINI_STM32_F103/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/boards/MAPLEMINI_STM32_F103/board.c @@ -0,0 +1,50 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/MAPLEMINI_STM32_F103/board.h b/boards/MAPLEMINI_STM32_F103/board.h new file mode 100644 index 000000000..977a54bb7 --- /dev/null +++ b/boards/MAPLEMINI_STM32_F103/board.h @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the LeafLabs Maple Mini. + */ + +/* + * Board identifier. + */ +#define BOARD_MAPLEMINI_STM32_F103 +#define BOARD_NAME "LeafLabs Maple Mini" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD + +/* + * IO pins assignments. + */ +/* Missing.*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + * PA9 - Alternate output (USART1 TX). + * PA10 - Normal input (USART1 RX). + */ +#define VAL_GPIOACRL 0x88884B88 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x888884B8 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB1 - Push Pull output (LED). + */ +#define VAL_GPIOBCRL 0x88888838 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +/* + * USB bus activation macro, required by the USB driver. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC) + +/* + * USB bus de-activation macro, required by the USB driver. + */ +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/MAPLEMINI_STM32_F103/board.mk b/boards/MAPLEMINI_STM32_F103/board.mk new file mode 100644 index 000000000..ab4b30cac --- /dev/null +++ b/boards/MAPLEMINI_STM32_F103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/MAPLEMINI_STM32_F103/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/MAPLEMINI_STM32_F103 diff --git a/boards/NGX_BB_LPC11U14/board.c b/boards/NGX_BB_LPC11U14/board.c new file mode 100644 index 000000000..3f3c3d726 --- /dev/null +++ b/boards/NGX_BB_LPC11U14/board.c @@ -0,0 +1,61 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +__inline void __early_init(void) { + + lpc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +__inline void boardInit(void) { + + /* LCD */ + LPC_IOCON->TMS_PIO0_12 = 0x91; /* LCD_EN: GPIO - pull-up */ + LPC_IOCON->TDO_PIO0_13 = 0x81; /* LCD_RW: GPIO - No pull-up */ + LPC_IOCON->TRST_PIO0_14 = 0x81; /* LCD_RS: GPIO - No pull-up */ + + /* USART */ + LPC_IOCON->PIO0_18 = 0x81; /* RDX: RXD - No pull-up */ + LPC_IOCON->PIO0_19 = 0x81; /* TDX: TXD - No pull-up */ + + /* Test LEDs */ + LPC_IOCON->PIO0_22 = 0x80; /* LED_TEST1: GPIO - No pull-up */ + LPC_IOCON->PIO0_23 = 0x80; /* LED_TEST2: GPIO - No pull-up */ + +} + diff --git a/boards/NGX_BB_LPC11U14/board.h b/boards/NGX_BB_LPC11U14/board.h new file mode 100644 index 000000000..9a59a9c44 --- /dev/null +++ b/boards/NGX_BB_LPC11U14/board.h @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for NGX BlueBoard LPC11U14. + */ + +/* + * Board identifiers. + */ +#define BOARD_NGX_BB_LPC11U14 +#define BOARD_NAME "NGX BlueBoard LPC11U14" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * Pin definitions. + */ + +/* GPIO Port0 */ +#define BUTTON_ISP_PORT GPIO0 +#define BUTTON_ISP 1 + +#define LCD_ERD_PORT GPIO0 +#define LCD_ERD 12 + +#define LCD_RWR_PORT GPIO0 +#define LCD_RWR 13 + +#define LCD_RS_PORT GPIO0 +#define LCD_RS 14 + +#define LED_PORT GPIO0 +#define LED_TEST1 22 +#define LED_TEST2 23 + +/* GPIO Port1 */ +#define LCD_RST_PORT GPIO1 +#define LCD_RST 0 + +#define LCD_CS_PORT GPIO1 +#define LCD_CS 13 + +#define LCD_BL_PORT GPIO1 +#define LCD_BL 14 +#define LCD_VCCEN_PORT GPIO1 +#define LCD_VCCEN 14 + +#define WHEEL_SENSOR_PORT GPIO0 +#define WHEEL_SENSOR 21 + +#define LCD_DATA_PORT GPIO1 +#define LCD_D0 19 +#define LCD_D1 20 +#define LCD_D2 21 +#define LCD_D3 22 +#define LCD_D4 26 +#define LCD_D5 27 +#define LCD_D6 28 +#define LCD_D7 31 + +#define LCD_DATA_MASK PAL_PORT_BIT(LCD_D0) | \ + PAL_PORT_BIT(LCD_D1) | \ + PAL_PORT_BIT(LCD_D2) | \ + PAL_PORT_BIT(LCD_D3) | \ + PAL_PORT_BIT(LCD_D4) | \ + PAL_PORT_BIT(LCD_D5) | \ + PAL_PORT_BIT(LCD_D6) | \ + PAL_PORT_BIT(LCD_D7) + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR PAL_PORT_BIT(LCD_ERD) | \ + PAL_PORT_BIT(LCD_RWR) | \ + PAL_PORT_BIT(LCD_RS) | \ + PAL_PORT_BIT(LED_TEST1) | \ + PAL_PORT_BIT(LED_TEST2) + +#define VAL_GPIO0DATA PAL_PORT_BIT(LCD_ERD) | \ + PAL_PORT_BIT(LCD_RWR) | \ + PAL_PORT_BIT(LED_TEST1) | \ + PAL_PORT_BIT(LED_TEST2) + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR PAL_PORT_BIT(LCD_RST) | \ + PAL_PORT_BIT(LCD_CS) | \ + PAL_PORT_BIT(LCD_BL) | \ + LCD_DATA_MASK + +#define VAL_GPIO1DATA 0x00000000 + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif + +#endif diff --git a/boards/NGX_BB_LPC11U14/board.mk b/boards/NGX_BB_LPC11U14/board.mk new file mode 100644 index 000000000..451d160dd --- /dev/null +++ b/boards/NGX_BB_LPC11U14/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/NGX_BB_LPC11U14/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/NGX_BB_LPC11U14 diff --git a/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c new file mode 100644 index 000000000..193217320 --- /dev/null +++ b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} + +#if HAL_USE_SDC +/** + * @brief Insertion monitor function. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadPad(GPIOE, GPIOE_SDIO_DETECT); +} + +/** + * @brief Protection detection. + * @note Not supported, always not protected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return FALSE; +} +#endif /* HAL_USE_SDC */ diff --git a/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h new file mode 100644 index 000000000..78ae3bd0e --- /dev/null +++ b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h @@ -0,0 +1,520 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_NONSTANDARD_STM32F4_BARTHESS1 +#define BOARD_NAME "Hand made STM32F4x board" + +/* + * Board frequencies. + * NOTE: The LSE crystal is not fitted by default on the board. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_USART2_CTS 0 /* xbee */ +#define GPIOA_USART2_RTS 1 /* xbee */ +#define GPIOA_USART2_TX 2 /* xbee */ +#define GPIOA_USART2_RX 3 /* xbee */ +#define GPIOA_SPI1_NSS 4 +#define GPIOA_SPI1_SCK 5 +#define GPIOA_SPI1_MISO 6 +#define GPIOA_SPI1_MOSI 7 +#define GPIOA_5V_DOMAIN_EN 8 +#define GPIOA_USART1_TX 9 /* gps */ +#define GPIOA_USART1_RX 10/* gps */ +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_JTMS 13 +#define GPIOA_JTCK 14 +#define GPIOA_JTDI 15 + +#define GPIOB_RECEIVER_PPM 0 +#define GPIOB_TACHOMETER 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTDO 3 +#define GPIOB_NJTRST 4 +#define GPIOB_LED_R 6 +#define GPIOB_LED_G 7 +#define GPIOB_LED_B 8 +#define GPIOB_I2C2_SCL 10 +#define GPIOB_I2C2_SDA 11 + + +#define GPIOC_AN_CURRENT_SENS 0 +#define GPIOC_AN_SUPPLY_SENS 1 +#define GPIOC_AN_6V_SENS 2 +#define GPIOC_AN33_0 3 +#define GPIOC_AN33_1 4 +#define GPIOC_AN33_2 5 +#define GPIOC_SDIO_D0 8 +#define GPIOC_SDIO_D1 9 +#define GPIOC_SDIO_D2 10 +#define GPIOC_SDIO_D3 11 +#define GPIOC_SDIO_CK 12 +#define GPIOC_TAMPER_RTC 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_SDIO_CMD 2 +#define GPIOD_PWM1 12 +#define GPIOD_PWM2 13 +#define GPIOD_PWM3 14 +#define GPIOD_PWM4 15 + +#define GPIOE_GPS_PPS 0 +#define GPIOE_XBEE_SLEEP 1 +#define GPIOE_XBEE_RESET 2 +#define GPIOE_SDIO_DETECT 3 +#define GPIOE_USB_DISCOVERY 4 +#define GPIOE_GPS_PWR_EN 5 +#define GPIOE_BMP085_EOC 6 +#define GPIOE_MAG_INT 7 +#define GPIOE_MMA8451_INT1 8 +#define GPIOE_PWM5 9 +#define GPIOE_ITG3200_INT 10 +#define GPIOE_PWM6 11 +#define GPIOE_PWM7 13 +#define GPIOE_PWM8 14 +#define GPIOE_MMA8451_INT2 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + * + * 1 for open drain outputs denotes hi-Z state + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * Port A setup. + * All input with pull-up except: +#define GPIOA_USART2_CTS 0 //xbee +#define GPIOA_USART2_RTS 1 //xbee +#define GPIOA_USART2_TX 2 //xbee +#define GPIOA_USART2_Rx 3 //xbee +#define GPIOA_SPI1_NSS 4 +#define GPIOA_SPI1_SCK 5 +#define GPIOA_SPI1_MISO 6 +#define GPIOA_SPI1_MOSI 7 +#define GPIOA_5V_DOMAIN_EN 8 +#define GPIOA_USART1_TX 9 +#define GPIOA_USART1_RX 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_JTMS 13 +#define GPIOA_JTCK 14 +#define GPIOA_JTDI 15 + */ + +/* default after reset 0xA8000000 */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_USART2_CTS) | \ + PIN_MODE_ALTERNATE(GPIOA_USART2_RTS) | \ + PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ + PIN_MODE_OUTPUT(GPIOA_5V_DOMAIN_EN) | \ + PIN_MODE_ALTERNATE(GPIOA_USART1_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_USART1_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTDI)) +/* default 0x00000000 */ +#define VAL_GPIOA_OTYPER 0x00000000 +/* default 0x00000000 */ +#define VAL_GPIOA_OSPEEDR 0x00000000 +/* 0x64000000 */ +#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_USART2_CTS) | \ + PIN_PUDR_FLOATING(GPIOA_USART2_RTS) | \ + PIN_PUDR_FLOATING(GPIOA_USART2_TX) | \ + PIN_PUDR_FLOATING(GPIOA_USART2_RX) | \ + PIN_PUDR_PULLUP(GPIOA_SPI1_NSS) | \ + PIN_PUDR_PULLUP(GPIOA_SPI1_SCK) | \ + PIN_PUDR_PULLUP(GPIOA_SPI1_MISO) | \ + PIN_PUDR_PULLUP(GPIOA_SPI1_MOSI) | \ + PIN_PUDR_FLOATING(GPIOA_5V_DOMAIN_EN) | \ + PIN_PUDR_FLOATING(GPIOA_USART1_TX) | \ + PIN_PUDR_FLOATING(GPIOA_USART1_RX) | \ + PIN_PUDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUDR_PULLUP(GPIOA_JTMS) | \ + PIN_PUDR_PULLDOWN(GPIOA_JTCK) | \ + PIN_PUDR_PULLUP(GPIOA_JTDI)) +/* 0x00000000 */ +#define VAL_GPIOA_ODR 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_USART2_CTS, 7) | \ + PIN_AFIO_AF(GPIOA_USART2_RTS, 7) | \ + PIN_AFIO_AF(GPIOA_USART2_TX, 7) | \ + PIN_AFIO_AF(GPIOA_USART2_RX, 7)| \ + PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5)) +/* 0x00000000 */ +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USART1_TX, 7) | \ + PIN_AFIO_AF(GPIOA_USART1_RX, 7) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_JTMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTCK, 0) | \ + PIN_AFIO_AF(GPIOA_JTDI, 0)) + +/* + * Port B setup. +#define GPIOB_RECEIVER_PPM 0 +#define GPIOB_TACHOMETER 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTDO 3 +#define GPIOB_NJTRST 4 +#define GPIOB_LED_R 6 +#define GPIOB_LED_G 7 +#define GPIOB_LED_B 8 +#define GPIOB_I2C2_SCL 10 +#define GPIOB_I2C2_SDA 11 + */ +/* 0x00000280 */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_RECEIVER_PPM) | \ + PIN_MODE_INPUT(GPIOB_TACHOMETER) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_JTDO) | \ + PIN_MODE_ALTERNATE(GPIOB_NJTRST) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_OUTPUT(GPIOB_LED_R) | \ + PIN_MODE_OUTPUT(GPIOB_LED_G) | \ + PIN_MODE_OUTPUT(GPIOB_LED_B) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +/* 0x00000000 */ +#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_LED_R) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_LED_G) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_LED_B) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA)) +/* 0x000000C0 */ +#define VAL_GPIOB_OSPEEDR 0x000000C0//0xAAAAAAEA +/* 0x00000100 */ +#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLDOWN(GPIOB_RECEIVER_PPM) | \ + PIN_PUDR_PULLDOWN(GPIOB_TACHOMETER) | \ + PIN_PUDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUDR_FLOATING(GPIOB_JTDO) | \ + PIN_PUDR_PULLUP(GPIOB_NJTRST) | \ + PIN_PUDR_FLOATING(5) | \ + PIN_PUDR_FLOATING(GPIOB_LED_R) | \ + PIN_PUDR_FLOATING(GPIOB_LED_G) | \ + PIN_PUDR_FLOATING(GPIOB_LED_B) | \ + PIN_PUDR_FLOATING(9) | \ + PIN_PUDR_FLOATING(GPIOB_I2C2_SCL) | \ + PIN_PUDR_FLOATING(GPIOB_I2C2_SDA) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +/* 0x00000000 */ +#define VAL_GPIOB_ODR 0x000001C0 +/* 0x00000000 */ +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_RECEIVER_PPM, 0) | \ + PIN_AFIO_AF(GPIOB_JTDO, 0)) +/* 0x00000000 */ +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C2_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C2_SDA, 4)) + + +/* + * Port C setup. +#define GPIOC_AN_CURRENT_SENS 0 +#define GPIOC_AN_SUPPLY_SENS 1 +#define GPIOC_AN_6V_SENS 2 +#define GPIOC_AN33_0 3 +#define GPIOC_AN33_1 4 +#define GPIOC_AN33_2 5 + +#define GPIOC_SDIO_D0 8 +#define GPIOC_SDIO_D1 9 +#define GPIOC_SDIO_D2 10 +#define GPIOC_SDIO_D3 11 +#define GPIOC_SDIO_CK 12 + +#define GPIOC_TAMPER_RTC 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + */ +/* 0x00000000 */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_AN_CURRENT_SENS) | \ + PIN_MODE_ANALOG(GPIOC_AN_SUPPLY_SENS) | \ + PIN_MODE_ANALOG(GPIOC_AN_6V_SENS) | \ + PIN_MODE_ANALOG(GPIOC_AN33_0) | \ + PIN_MODE_ANALOG(GPIOC_AN33_1) | \ + PIN_MODE_ANALOG(GPIOC_AN33_2) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \ + PIN_MODE_INPUT(GPIOC_TAMPER_RTC) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) + +/* 0x00000000 */ +#define VAL_GPIOC_OTYPER 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_25M(GPIOC_SDIO_D0) | \ + PIN_OSPEED_25M(GPIOC_SDIO_D1) | \ + PIN_OSPEED_25M(GPIOC_SDIO_D2) | \ + PIN_OSPEED_25M(GPIOC_SDIO_D3) | \ + PIN_OSPEED_25M(GPIOC_SDIO_CK) | \ + PIN_OSPEED_2M(GPIOC_TAMPER_RTC)) +/* 0x00000000 */ +#define VAL_GPIOC_PUPDR (PIN_PUDR_FLOATING(GPIOC_AN_CURRENT_SENS) | \ + PIN_PUDR_FLOATING(GPIOC_AN_SUPPLY_SENS) | \ + PIN_PUDR_FLOATING(GPIOC_AN_6V_SENS) | \ + PIN_PUDR_FLOATING(GPIOC_AN33_0) | \ + PIN_PUDR_FLOATING(GPIOC_AN33_1) | \ + PIN_PUDR_FLOATING(GPIOC_AN33_2) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(GPIOC_SDIO_D0) | \ + PIN_PUDR_PULLUP(GPIOC_SDIO_D1) | \ + PIN_PUDR_PULLUP(GPIOC_SDIO_D2) | \ + PIN_PUDR_PULLUP(GPIOC_SDIO_D3) | \ + PIN_PUDR_PULLUP(GPIOC_SDIO_CK) | \ + PIN_PUDR_FLOATING(GPIOC_TAMPER_RTC) | \ + PIN_PUDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUDR_FLOATING(GPIOC_OSC32_OUT)) +/* 0x00000000 */ +#define VAL_GPIOC_ODR 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOC_AFRL 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12) | \ + PIN_AFIO_AF(GPIOC_SDIO_D1, 12) | \ + PIN_AFIO_AF(GPIOC_SDIO_D2, 12) | \ + PIN_AFIO_AF(GPIOC_SDIO_D3, 12) | \ + PIN_AFIO_AF(GPIOC_SDIO_CK, 12)) + +/* + * Port D setup. +#define GPIOD_SDIO_CMD 2 +#define GPIOD_PWM1 12 +#define GPIOD_PWM2 13 +#define GPIOD_PWM3 14 +#define GPIOD_PWM4 15 + */ +/* 0x00000000 */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM1) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM2) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM3) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM4)) +/* 0x00000000 */ +#define VAL_GPIOD_OTYPER 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_25M(GPIOD_SDIO_CMD)) +/* 0x00000000 */ +#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(GPIOD_SDIO_CMD) | \ + PIN_PUDR_PULLDOWN(GPIOD_PWM1) | \ + PIN_PUDR_PULLDOWN(GPIOD_PWM2) | \ + PIN_PUDR_PULLDOWN(GPIOD_PWM3) | \ + PIN_PUDR_PULLDOWN(GPIOD_PWM4)) +/* 0x00000000 */ +#define VAL_GPIOD_ODR 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_SDIO_CMD, 12)) +/* 0x00000000 */ +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PWM1, 2) | \ + PIN_AFIO_AF(GPIOD_PWM2, 2) | \ + PIN_AFIO_AF(GPIOD_PWM3, 2) | \ + PIN_AFIO_AF(GPIOD_PWM4, 2)) + + +/* + * Port E setup. +#define GPIOE_GPS_PPS 0 +#define GPIOE_XBEE_SLEEP 1 +#define GPIOE_XBEE_RESET 2 +#define GPIOE_SDIO_DETECT 3 +#define GPIOE_USB_DISCOVERY 4 +#define GPIOE_GPS_EN 5 +#define GPIOE_BMP085_EOC 6 +#define GPIOE_MAG_INT 7 +#define GPIOE_MMA8451_INT1 8 +#define GPIOE_PWM5 9 +#define GPIOE_ITG3200_INT 10 +#define GPIOE_PWM6 11 +#define GPIOE_TACHOMETER 12 +#define GPIOE_PWM7 13 +#define GPIOE_PWM8 14 +#define GPIOE_MMA8451_INT2 15 + */ +/* 0x00000000 */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_GPS_PPS) | \ + PIN_MODE_OUTPUT(GPIOE_XBEE_SLEEP) | \ + PIN_MODE_OUTPUT(GPIOE_XBEE_RESET) | \ + PIN_MODE_INPUT(GPIOE_SDIO_DETECT) | \ + PIN_MODE_OUTPUT(GPIOE_USB_DISCOVERY) | \ + PIN_MODE_OUTPUT(GPIOE_GPS_PWR_EN) | \ + PIN_MODE_INPUT(GPIOE_BMP085_EOC) | \ + PIN_MODE_INPUT(GPIOE_MAG_INT) | \ + PIN_MODE_INPUT(GPIOE_MMA8451_INT1) | \ + PIN_MODE_ALTERNATE(GPIOE_PWM5) | \ + PIN_MODE_INPUT(GPIOE_ITG3200_INT) | \ + PIN_MODE_ALTERNATE(GPIOE_PWM6) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_ALTERNATE(GPIOE_PWM7) | \ + PIN_MODE_ALTERNATE(GPIOE_PWM8) | \ + PIN_MODE_INPUT(GPIOE_MMA8451_INT2)) +/* 0x00000000 */ +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_XBEE_SLEEP) | \ + PIN_OTYPE_PUSHPULL(GPIOE_XBEE_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOE_USB_DISCOVERY) | \ + PIN_OTYPE_OPENDRAIN(GPIOE_GPS_PWR_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PWM5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PWM6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PWM7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PWM8)) +/* 0x00000000 */ +#define VAL_GPIOE_OSPEEDR 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLDOWN(GPIOE_GPS_PPS) | \ + PIN_PUDR_PULLUP(GPIOE_XBEE_SLEEP) | \ + PIN_PUDR_FLOATING(GPIOE_XBEE_RESET) | \ + PIN_PUDR_PULLUP(GPIOE_SDIO_DETECT) | \ + PIN_PUDR_FLOATING(GPIOE_USB_DISCOVERY) | \ + PIN_PUDR_FLOATING(GPIOE_GPS_PWR_EN) | \ + PIN_PUDR_PULLDOWN(GPIOE_BMP085_EOC) | \ + PIN_PUDR_PULLDOWN(GPIOE_MAG_INT) | \ + PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT1) | \ + PIN_PUDR_PULLDOWN(GPIOE_PWM5) | \ + PIN_PUDR_PULLDOWN(GPIOE_ITG3200_INT) | \ + PIN_PUDR_PULLDOWN(GPIOE_PWM6) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLDOWN(GPIOE_PWM7) | \ + PIN_PUDR_PULLDOWN(GPIOE_PWM8) | \ + PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT2)) +/* 0x00000000 */ +#define VAL_GPIOE_ODR 0x30 +/* 0x00000000 */ +#define VAL_GPIOE_AFRL 0x00000000 +/* 0x00000000 */ +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PWM5, 1) | \ + PIN_AFIO_AF(GPIOE_PWM6, 1) | \ + PIN_AFIO_AF(GPIOE_PWM7, 1) | \ + PIN_AFIO_AF(GPIOE_PWM8, 1)) + +/* + * Port F setup. + */ +#define VAL_GPIOF_MODER 0x00000000 +#define VAL_GPIOF_OTYPER 0x00000000 +#define VAL_GPIOF_OSPEEDR 0x00000000 +#define VAL_GPIOF_PUPDR 0x00000000 +#define VAL_GPIOF_ODR 0x00000000 +#define VAL_GPIOF_AFRL 0x00000000 +#define VAL_GPIOF_AFRH 0x00000000 + +/* + * Port G setup. + */ +#define VAL_GPIOG_MODER 0x00000000 +#define VAL_GPIOG_OTYPER 0x00000000 +#define VAL_GPIOG_OSPEEDR 0x00000000 +#define VAL_GPIOG_PUPDR 0x00000000 +#define VAL_GPIOG_ODR 0x00000000 +#define VAL_GPIOG_AFRL 0x00000000 +#define VAL_GPIOG_AFRH 0x00000000 + +/* + * Port H setup. + */ +#define VAL_GPIOH_MODER 0x00000000 +#define VAL_GPIOH_OTYPER 0x00000000 +#define VAL_GPIOH_OSPEEDR 0x00000000 +#define VAL_GPIOH_PUPDR 0x00000000 +#define VAL_GPIOH_ODR 0x00000000 +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 + +/* + * Port I setup. + */ +#define VAL_GPIOI_MODER 0x00000000 +#define VAL_GPIOI_OTYPER 0x00000000 +#define VAL_GPIOI_OSPEEDR 0x00000000 +#define VAL_GPIOI_PUPDR 0x00000000 +#define VAL_GPIOI_ODR 0x00000000 +#define VAL_GPIOI_AFRL 0x00000000 +#define VAL_GPIOI_AFRH 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk new file mode 100644 index 000000000..8f50edf14 --- /dev/null +++ b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1 diff --git a/boards/OLIMEX_AVR_CAN/board.c b/boards/OLIMEX_AVR_CAN/board.c new file mode 100644 index 000000000..f7e458d9b --- /dev/null +++ b/boards/OLIMEX_AVR_CAN/board.c @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(PORTA) + {VAL_PORTA, VAL_DDRA}, +#endif +#if defined(PORTB) + {VAL_PORTB, VAL_DDRB}, +#endif +#if defined(PORTC) + {VAL_PORTC, VAL_DDRC}, +#endif +#if defined(PORTD) + {VAL_PORTD, VAL_DDRD}, +#endif +#if defined(PORTE) + {VAL_PORTE, VAL_DDRE}, +#endif +#if defined(PORTF) + {VAL_PORTF, VAL_DDRF}, +#endif +#if defined(PORTG) + {VAL_PORTG, VAL_DDRG}, +#endif +}; +#endif /* HAL_USE_PAL */ + +CH_IRQ_HANDLER(TIMER0_COMP_vect) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; + + /* + * Enables Idle mode for SLEEP instruction. + */ + SMCR = (1 << SE); + + /* + * Timer 0 setup. + */ + TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ + (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */ + (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */ + OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; /* Reset counter. */ + TIFR0 = (1 << OCF0A); /* Reset pending. */ + TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */ +} diff --git a/boards/OLIMEX_AVR_CAN/board.h b/boards/OLIMEX_AVR_CAN/board.h new file mode 100644 index 000000000..4d674756e --- /dev/null +++ b/boards/OLIMEX_AVR_CAN/board.h @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex AVR-CAN proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_AVR_CAN +#define BOARD_NAME "Olimex AVR-CAN" + +/* + * All inputs with pullups. + */ +#define VAL_DDRA 0x00 +#define VAL_PORTA 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRB 0x00 +#define VAL_PORTB 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRC 0x00 +#define VAL_PORTC 0xFF + +/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 + * IN IN OUT IN OUT IN IN IN + * DDRD 0 0 1 0 1 0 0 0 + * PU HiZ VAL PU VAL HiZ HiZ HiZ + * PORTD 1 0 ?1 1 1 0 0 0 + */ +#define VAL_DDRD 0x28 +#define VAL_PORTD 0xB8 + +/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 + * IN IN IN OUT IN IN OUT IN + * DDRE 0 0 0 1 0 0 1 0 + * PU PU HiZ VAL PU PU VAL HiZ + * PORTE 1 1 0 1 1 1 1 0 + */ +#define VAL_DDRE 0x12 +#define VAL_PORTE 0xDE + +/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 + * x x x x IN IN IN IN + * DDRF 0 0 0 0 0 0 0 0 + * x x x x PU PU PU PU + * PORTF 0 0 0 0 1 1 1 1 + * + */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0x0F + +/* x x x x x PG2 PG1 PG0 + * x x x x x IN IN IN + * DDRG 0 0 0 0 0 0 0 0 + * x x x x x PU PU PU + * PORTG 0 0 0 0 0 1 1 1 + * + */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0x07 + +#define PORTE_LED 4 +#define PORTE_BUTTON 5 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_AVR_CAN/board.mk b/boards/OLIMEX_AVR_CAN/board.mk new file mode 100644 index 000000000..4d2d406ad --- /dev/null +++ b/boards/OLIMEX_AVR_CAN/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN diff --git a/boards/OLIMEX_AVR_MT_128/board.c b/boards/OLIMEX_AVR_MT_128/board.c new file mode 100644 index 000000000..ff1ee85e8 --- /dev/null +++ b/boards/OLIMEX_AVR_MT_128/board.c @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(PORTA) + {VAL_PORTA, VAL_DDRA}, +#endif +#if defined(PORTB) + {VAL_PORTB, VAL_DDRB}, +#endif +#if defined(PORTC) + {VAL_PORTC, VAL_DDRC}, +#endif +#if defined(PORTD) + {VAL_PORTD, VAL_DDRD}, +#endif +#if defined(PORTE) + {VAL_PORTE, VAL_DDRE}, +#endif +#if defined(PORTF) + {VAL_PORTF, VAL_DDRF}, +#endif +#if defined(PORTG) + {VAL_PORTG, VAL_DDRG}, +#endif +}; +#endif /* HAL_USE_PAL */ + +/** + * @brief Timer0 interrupt handler. + */ +CH_IRQ_HANDLER(TIMER0_COMP_vect) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; + + /* + * Enables Idle mode for SLEEP instruction. + */ + MCUCR = (1 << SE); + + /* + * Timer 0 setup. + */ + TCCR0 = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ + (0 << COM01) | (0 << COM00) | /* OC0A disabled. */ + (1 << CS02) | (0 << CS01) | (0 << CS00); /* CLK/64 clock. */ + OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; /* Reset counter. */ + TIFR = (1 << OCF0); /* Reset pending. */ + TIMSK = (1 << OCIE0); /* IRQ on compare. */ +} diff --git a/boards/OLIMEX_AVR_MT_128/board.h b/boards/OLIMEX_AVR_MT_128/board.h new file mode 100644 index 000000000..3c99f9d53 --- /dev/null +++ b/boards/OLIMEX_AVR_MT_128/board.h @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex AVR-MT-128 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_AVR_MT_128 +#define BOARD_NAME "Olimex AVR-MT-128" + +/* PA7 RLY DS B5 B4 B3 B2 B1 + * IN OUT IN IN IN IN IN IN + * DDRA 0 1 0 0 0 0 0 0 + * PU VAL HiZ HiZ HiZ HiZ HiZ HiZ + * PORTA 1 0 0 0 0 0 0 0 + */ +#define VAL_DDRA 0x40 +#define VAL_PORTA 0x80 + +/* + * All inputs with pullups. + */ +#define VAL_DDRB 0x00 +#define VAL_PORTB 0xFF + +/* D7 D6 D5 D4 PC3 E R/W RS + * OUT OUT OUT OUT IN OUT OUT OUT + * DDRC 1 1 1 1 0 1 1 1 + * PU PU PU PU PU VAL VAL VAL + * PORTC 0 0 0 0 1 0 0 0 + */ +#define VAL_DDRC 0xF7 +#define VAL_PORTC 0x08 + +/* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0 + * IN IN IN IN OUT IN IN IN + * DDRD 0 0 0 0 1 0 0 0 + * PU PU PU PU VAL HiZ PU PU + * PORTD 1 1 1 1 1 0 1 1 + */ +#define VAL_DDRD 0x08 +#define VAL_PORTD 0xFB + +/* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0 + * IN IN OUT OUT IN IN OUT IN + * DDRE 0 0 1 1 0 0 1 0 + * PU PU VAL VAL PU PU VAL PU + * PORTE 1 1 1 1 1 1 1 1 + */ +#define VAL_DDRE 0x32 +#define VAL_PORTE 0xFF + +/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 + * x x x x IN IN IN IN + * DDRF 0 0 0 0 0 0 0 0 + * x x x x PU PU PU PU + * PORTF 0 0 0 0 1 1 1 1 + * + */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0x0F + +/* x x x x x PG2 PG1 PG0 + * x x x x x IN IN IN + * DDRG 0 0 0 0 0 0 0 0 + * x x x x x PU PU PU + * PORTG 0 0 0 0 0 1 1 1 + * + */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0x07 + + +#define PORTA_BUTTON1 0 +#define PORTA_BUTTON2 1 +#define PORTA_BUTTON3 2 +#define PORTA_BUTTON4 3 +#define PORTA_BUTTON5 4 +#define PORTA_DALLAS 5 +#define PORTA_RELAY 6 + +#define PORTC_44780_RS_MASK (1 << 0) +#define PORTC_44780_RW_MASK (1 << 1) +#define PORTC_44780_E_MASK (1 << 2) +#define PORTC_44780_D4_MASK (1 << 4) +#define PORTC_44780_D5_MASK (1 << 5) +#define PORTC_44780_D6_MASK (1 << 6) +#define PORTC_44780_D7_MASK (1 << 7) +#define PORTC_44780_DATA_MASK (PORTC_44780_D4_MASK | PORTC_44780_D5_MASK | \ + PORTC_44780_D6_MASK | PORTC_44780_D7_MASK) + +#define PORTE_BUZZ1 (1 << 4) +#define PORTE_BUZZ2 (1 << 5) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_AVR_MT_128/board.mk b/boards/OLIMEX_AVR_MT_128/board.mk new file mode 100644 index 000000000..7b903ffec --- /dev/null +++ b/boards/OLIMEX_AVR_MT_128/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128 diff --git a/boards/OLIMEX_LPC-P1227/board.c b/boards/OLIMEX_LPC-P1227/board.c new file mode 100644 index 000000000..09bb82e7b --- /dev/null +++ b/boards/OLIMEX_LPC-P1227/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR}, + {VAL_GPIO2DATA, VAL_GPIO2DIR}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + lpc122x_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + */ + LPC_IOCON->PIO1_4 = 0x80; /* Disables pull-up on LED2 output. */ + LPC_IOCON->PIO1_5 = 0x80; /* Disables pull-up on LED1 output */ + LPC_IOCON->PIO1_6 = 0x80; /* Disables pull-up on Buzzer output */ +} diff --git a/boards/OLIMEX_LPC-P1227/board.h b/boards/OLIMEX_LPC-P1227/board.h new file mode 100644 index 000000000..ae2e879a7 --- /dev/null +++ b/boards/OLIMEX_LPC-P1227/board.h @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Olimex LPC-P1227 board. + * + */ + +/* + * Board identifiers. + */ +#define OLIMEX_LPC_P1227 +#define BOARD_NAME "Olimex LPC-P1227" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR 0x00000000 +#define VAL_GPIO0DATA 0x00000000 + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED1) | \ + PAL_PORT_BIT(GPIO1_LED2) | \ + PAL_PORT_BIT(GPIO1_BUZZER) + +#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED1) + + +/* + * GPIO 2 initial setup. + */ +#define VAL_GPIO2DIR PAL_PORT_BIT(GPIO2_LCD_DC) | \ + PAL_PORT_BIT(GPIO2_LCD_SS) | \ + PAL_PORT_BIT(GPIO2_LCD_RES) +#define VAL_GPIO2DATA PAL_PORT_BIT(GPIO2_LCD_SS) + + +/* + * Pin definitions. + */ + +#define GPIO1_LED1 5 +#define GPIO1_LED2 4 +#define GPIO1_SW_WAKEUP 3 +#define GPIO1_BUZZER 6 + +#define GPIO2_SW_USER1 12 +#define GPIO2_SW_USER2 11 +#define GPIO2_SW_USER3 10 +#define GPIO2_LCD_DC 15 +#define GPIO2_LCD_SS 14 +#define GPIO2_LCD_RES 13 + +/* LCD3310 pins */ +#define LCD3310_RES_PIN GPIO2_LCD_RES +#define LCD3310_RES_PORT GPIO2 +#define LCD3310_DC_PIN GPIO2_LCD_DC +#define LCD3310_DC_PORT GPIO2 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_LPC-P1227/board.mk b/boards/OLIMEX_LPC-P1227/board.mk new file mode 100644 index 000000000..090251880 --- /dev/null +++ b/boards/OLIMEX_LPC-P1227/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC-P1227/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC-P1227 diff --git a/boards/OLIMEX_LPC_P1343/board.c b/boards/OLIMEX_LPC_P1343/board.c new file mode 100644 index 000000000..a0757d587 --- /dev/null +++ b/boards/OLIMEX_LPC_P1343/board.c @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR}, + {VAL_GPIO2DATA, VAL_GPIO2DIR}, + {VAL_GPIO3DATA, VAL_GPIO3DIR}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + LPC13xx_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Extra, board-specific, initializations. + */ +} diff --git a/boards/OLIMEX_LPC_P1343/board.h b/boards/OLIMEX_LPC_P1343/board.h new file mode 100644 index 000000000..ca7934f4d --- /dev/null +++ b/boards/OLIMEX_LPC_P1343/board.h @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex LPC-P1343 proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_OLIMEX_LPC_P1343 +#define BOARD_NAME "Olimex LPC-P1343" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + +/* + * GPIO 0 initial setup. + */ +#define VAL_GPIO0DIR 0x00000000 +#define VAL_GPIO0DATA 0x00000000 + +/* + * GPIO 1 initial setup. + */ +#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_SW2) + +#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_SW2) + +/* + * GPIO 2 initial setup. + */ + +#define VAL_GPIO2DIR PAL_PORT_BIT(GPIO2_SW1) | \ + PAL_PORT_BIT(GPIO2_LED5) | \ + PAL_PORT_BIT(GPIO2_LED6) | \ + PAL_PORT_BIT(GPIO2_LED7) | \ + PAL_PORT_BIT(GPIO2_LED8) + +#define VAL_GPIO2DATA PAL_PORT_BIT(GPIO2_LED5) | \ + PAL_PORT_BIT(GPIO2_LED6) | \ + PAL_PORT_BIT(GPIO2_LED7) | \ + PAL_PORT_BIT(GPIO2_LED8) + +/* + * GPIO 3 initial setup. + */ + +#define VAL_GPIO3DIR PAL_PORT_BIT(GPIO3_LED1) | \ + PAL_PORT_BIT(GPIO3_LED2) | \ + PAL_PORT_BIT(GPIO3_LED3) | \ + PAL_PORT_BIT(GPIO3_LED4) + +#define VAL_GPIO3DATA PAL_PORT_BIT(GPIO3_LED1) | \ + PAL_PORT_BIT(GPIO3_LED2) | \ + PAL_PORT_BIT(GPIO3_LED3) | \ + PAL_PORT_BIT(GPIO3_LED4) + +/* + * Pin definitions. + */ +#define GPIO1_SW2 4 +#define GPIO1_SPI0SEL 11 + +#define GPIO2_SW1 9 + +#define GPIO3_LED1 0 +#define GPIO3_LED2 1 +#define GPIO3_LED3 2 +#define GPIO3_LED4 3 +#define GPIO2_LED5 4 +#define GPIO2_LED6 5 +#define GPIO2_LED7 6 +#define GPIO2_LED8 7 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_LPC_P1343/board.mk b/boards/OLIMEX_LPC_P1343/board.mk new file mode 100644 index 000000000..718cc6e29 --- /dev/null +++ b/boards/OLIMEX_LPC_P1343/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC_P1343/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC_P1343 diff --git a/boards/OLIMEX_LPC_P2148/board.c b/boards/OLIMEX_LPC_P2148/board.c new file mode 100644 index 000000000..1c0a00302 --- /dev/null +++ b/boards/OLIMEX_LPC_P2148/board.c @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define VAL_TC0_PRESCALER 0 + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + VAL_PINSEL0, + VAL_PINSEL1, + VAL_PINSEL2, + {VAL_FIO0PIN, VAL_FIO0DIR}, + {VAL_FIO1PIN, VAL_FIO1DIR} +}; +#endif + +/* + * Timer 0 IRQ handling here. + */ +static CH_IRQ_HANDLER(T0IrqHandler) { + + CH_IRQ_PROLOGUE(); + T0IR = 1; /* Clear interrupt on match MR0. */ + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + VICVectAddr = 0; + CH_IRQ_EPILOGUE(); +} + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + lpc214x_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(IOPORT2, PB_CP1); +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return palReadPad(IOPORT2, PB_WP1); +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * System Timer initialization, 1ms intervals. + */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + VICIntEnable = INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ +} diff --git a/boards/OLIMEX_LPC_P2148/board.h b/boards/OLIMEX_LPC_P2148/board.h new file mode 100644 index 000000000..17651b313 --- /dev/null +++ b/boards/OLIMEX_LPC_P2148/board.h @@ -0,0 +1,92 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex LPC-P2148 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_LPC_P2148 +#define BOARD_NAME "Olimex LPC-P2148" + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * FIO0DIR (15...0) + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * FIO0DIR (31...16) + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 + * + * FIO1DIR (31...16) + * -- -- -- -- -- IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT + * 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100840A8 +#define VAL_PINSEL2 0x00000004 /* Do not modify */ +#define VAL_FIO0DIR 0xB0703C00 +#define VAL_FIO1DIR 0x01FF0000 +#define VAL_FIO0PIN 0xFFFFFFFF +#define VAL_FIO1PIN 0xFFFFFFFF + +#define PA_LED1 10 +#define PA_LED2 11 +#define PA_BUZZ1 12 +#define PA_BUZZ2 13 +#define PA_BSL 14 +#define PA_BUTTON1 15 +#define PA_BUTTON2 16 +#define PA_SSEL1 20 +#define PA_LEDUSB 31 + +#define PB_WP1 24 +#define PB_CP1 25 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_LPC_P2148/board.mk b/boards/OLIMEX_LPC_P2148/board.mk new file mode 100644 index 000000000..5d0937e6d --- /dev/null +++ b/boards/OLIMEX_LPC_P2148/board.mk @@ -0,0 +1,5 @@ +# List of all the mandatory board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148 diff --git a/boards/OLIMEX_LPC_P2148/buzzer.c b/boards/OLIMEX_LPC_P2148/buzzer.c new file mode 100644 index 000000000..cf2182f08 --- /dev/null +++ b/boards/OLIMEX_LPC_P2148/buzzer.c @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * Buzzer driver for Olimex LPC-P2148. + * Uses the timer 1 for wave generation and a Virtual Timer for the sound + * duration. + * The driver also generates an event when the sound is done and the buzzer + * goes silent. + */ + +#include "ch.h" +#include "hal.h" + +#include "buzzer.h" + +EventSource BuzzerSilentEventSource; + +#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) +#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) + +/** + * @brief Buzzer driver initialization. + */ +void buzzInit(void) { + + chEvtInit(&BuzzerSilentEventSource); + + /* + * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. + * Enables Timer1 clock. + */ + PINSEL0 &= 0xF0FFFFFF; + PINSEL0 |= 0x0A000000; + PCONP = (PCONP & PCALL) | PCTIM1; + + /* + * Timer setup. + */ + TC *tc = T1Base; + StopCounter(tc); + tc->TC_CTCR = 0; /* Clock source is PCLK. */ + tc->TC_PR = 0; /* Prescaler disabled. */ + tc->TC_MCR = 2; /* Clear TC on match MR0. */ +} + +/** + * @brief Stops the sound. + * + * @param[in] p pointer to the timer + */ +static void stop(void *p) { + + StopCounter((TC *)p); + chSysLockFromIsr(); + chEvtBroadcastI(&BuzzerSilentEventSource); + chSysUnlockFromIsr(); +} + +/** + * @brief Plays a tone asynchronously. + * + * @param[in] freq approximated tone frequency + * @param[in] duration tone duration in systicks + */ +void buzzPlay(uint32_t freq, systime_t duration) { + static VirtualTimer bvt; + TC *tc = T1Base; + + chSysLock(); + + if (chVTIsArmedI(&bvt)) { /* If a sound is already being */ + chVTResetI(&bvt); /* played then aborts it. */ + StopCounter(tc); + } + + tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); + StartCounter(tc); + chVTSetI(&bvt, duration, stop, tc); + + chSysUnlock(); +} + +/** + * @brief Plays a tone. + * + * @param[in] freq approximated tone frequency + * @param[in] duration tone duration in systicks + */ +void buzzPlayWait(uint32_t freq, systime_t duration) { + TC *tc = T1Base; + + StopCounter(tc); + tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); + StartCounter(tc); + chThdSleep(duration); + StopCounter(tc); +} diff --git a/boards/OLIMEX_LPC_P2148/buzzer.h b/boards/OLIMEX_LPC_P2148/buzzer.h new file mode 100644 index 000000000..82f573902 --- /dev/null +++ b/boards/OLIMEX_LPC_P2148/buzzer.h @@ -0,0 +1,32 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BUZZER_H_ +#define _BUZZER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + void buzzInit(void); + void buzzPlay(uint32_t freq, systime_t duration); + void buzzPlayWait(uint32_t freq, systime_t duration); +#ifdef __cplusplus +} +#endif + +extern EventSource BuzzerSilentEventSource; + +#endif /* _BUZZER_H_ */ diff --git a/boards/OLIMEX_MSP430_P1611/board.c b/boards/OLIMEX_MSP430_P1611/board.c new file mode 100644 index 000000000..bf89db001 --- /dev/null +++ b/boards/OLIMEX_MSP430_P1611/board.c @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) + {VAL_P1OUT, VAL_P1DIR}, +#endif +#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) + {VAL_P2OUT, VAL_P2DIR}, +#endif +#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) + {VAL_P3OUT, VAL_P3DIR}, +#endif +#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) + {VAL_P4OUT, VAL_P4DIR}, +#endif +#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) + {VAL_P5OUT, VAL_P5DIR}, +#endif +#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) + {VAL_P6OUT, VAL_P6DIR}, +#endif +}; +#endif + +CH_IRQ_HANDLER(TIMERA0) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +#if USE_MSP430_USART0 + P3SEL |= (1 << 4) | (1 << 5); +#endif + +#if USE_MSP430_USART1 + P3SEL |= (1 << 6) | (1 << 7); +#endif + + /* + * Timer 0 setup, uses SMCLK as source. + */ + TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */ + TACTL = TACLR; /* Clean start. */ + TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */ + TACCTL0 = CCIE; /* Interrupt on compare. */ +} diff --git a/boards/OLIMEX_MSP430_P1611/board.h b/boards/OLIMEX_MSP430_P1611/board.h new file mode 100644 index 000000000..e28b85bf5 --- /dev/null +++ b/boards/OLIMEX_MSP430_P1611/board.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex MSP430-P1611 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_MSP430_P1611 +#define BOARD_NAME "Olimex MSP430-P1611" + +/* + * Clock constants. + */ +#define LFXT1CLK 32768 +#define XT2CLK 8000000 +#define DCOCLK 750000 + +/* + * Pin definitions for the Olimex MSP430-P1611 board. + */ +#define P3_O_TXD0 4 +#define P3_O_TXD0_MASK (1 << P3_O_TXD0) +#define P3_I_RXD0 5 +#define P3_I_RXD0_MASK (1 << P3_I_RXD0) +#define P6_O_LED 0 +#define P6_O_LED_MASK (1 << P6_O_LED) +#define P6_I_BUTTON 1 +#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON) + +/* + * Initial I/O ports settings. + */ +#define VAL_P1OUT 0x00 +#define VAL_P1DIR 0xFF + +#define VAL_P2OUT 0x00 +#define VAL_P2DIR 0xFF + +#define VAL_P3OUT P3_O_TXD0_MASK +#define VAL_P3DIR ~P3_I_RXD0_MASK + +#define VAL_P4OUT 0x00 +#define VAL_P4DIR 0xFF + +#define VAL_P5OUT 0x00 +#define VAL_P5DIR 0xFF + +#define VAL_P6OUT P6_O_LED_MASK +#define VAL_P6DIR ~P6_I_BUTTON_MASK + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_MSP430_P1611/board.mk b/boards/OLIMEX_MSP430_P1611/board.mk new file mode 100644 index 000000000..84acad8ed --- /dev/null +++ b/boards/OLIMEX_MSP430_P1611/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611 diff --git a/boards/OLIMEX_SAM7_EX256/board.c b/boards/OLIMEX_SAM7_EX256/board.c new file mode 100644 index 000000000..9de1b3ffc --- /dev/null +++ b/boards/OLIMEX_SAM7_EX256/board.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif +}; +#endif + +/* + * SYS IRQ handling here. + */ +static CH_IRQ_HANDLER(SYSIrqHandler) { + + CH_IRQ_PROLOGUE(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + } + +#if USE_SAM7_DBGU_UART + if (AT91C_BASE_DBGU->DBGU_CSR & + (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | + AT91C_US_OVRE | AT91C_US_RXBRK)) { + sd_lld_serve_interrupt(&SDDBG); + } +#endif + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + at91sam7_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(IOPORT2, PIOB_MMC_CP); +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return palReadPad(IOPORT2, PIOB_MMC_WP); +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * LCD pins setup. + */ + palClearPad(IOPORT2, PIOB_LCD_BL); + palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); + + palSetPad(IOPORT1, PIOA_LCD_RESET); + palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * Joystick and buttons setup. + */ + palSetGroupMode(IOPORT1, + PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK, + 0, + PAL_MODE_INPUT); + palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, 0, PAL_MODE_INPUT); + + /* + * MMC/SD slot setup. + */ + palSetGroupMode(IOPORT2, + PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, + 0, + PAL_MODE_INPUT); + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * RTS/CTS pins enabled for USART0 only. + */ + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; +} diff --git a/boards/OLIMEX_SAM7_EX256/board.h b/boards/OLIMEX_SAM7_EX256/board.h new file mode 100644 index 000000000..efe5ead0c --- /dev/null +++ b/boards/OLIMEX_SAM7_EX256/board.h @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex SAM7-EX256 development board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_SAM7_EX256 +#define BOARD_NAME "Olimex SAM7-EX256" + +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7_PLATFORM) +#define SAM7_PLATFORM SAM7X256 +#endif + +#include "at91sam7.h" + +#define CLK 18432000 +#define MCK 48054857 + +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + +/* + * I/O definitions. + */ +#define PIOA_LCD_RESET 2 +#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) +#define PIOA_B1 7 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 8 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_B3 9 +#define PIOA_B3_MASK (1 << PIOA_B3) +#define PIOA_B4 14 +#define PIOA_B4_MASK (1 << PIOA_B4) +#define PIOA_B5 15 +#define PIOA_B5_MASK (1 << PIOA_B5) +#define PIOA_USB_PUP 25 +#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) +#define PIOA_USB_PR 26 +#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) +#define PIOA_CS_MMC 13 + +#define PIOB_PHY_PD 18 +#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) +#define PIOB_AUDIO_OUT 19 +#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) +#define PIOB_LCD_BL 20 +#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) +#define PIOB_MMC_WP 22 +#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) +#define PIOB_MMC_CP 23 +#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) +#define PIOB_SW1 24 +#define PIOB_SW1_MASK (1 << PIOB_SW1) +#define PIOB_SW2 25 +#define PIOB_SW2_MASK (1 << PIOB_SW2) +#define PIOB_PHY_IRQ 26 +#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_SAM7_EX256/board.mk b/boards/OLIMEX_SAM7_EX256/board.mk new file mode 100644 index 000000000..d0a4816f1 --- /dev/null +++ b/boards/OLIMEX_SAM7_EX256/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256 diff --git a/boards/OLIMEX_SAM7_P256/board.c b/boards/OLIMEX_SAM7_P256/board.c new file mode 100644 index 000000000..936019c4d --- /dev/null +++ b/boards/OLIMEX_SAM7_P256/board.c @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif +}; +#endif + +/* + * SYS IRQ handling here. + */ +static CH_IRQ_HANDLER(SYSIrqHandler) { + + CH_IRQ_PROLOGUE(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + } + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + at91sam7_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(IOPORT1, PIOA_MMC_CP); +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return palReadPad(IOPORT1, PIOA_MMC_WP); +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * LED pins setup. + */ + palClearPad(IOPORT1, PIOA_LED1); + palSetPadMode(IOPORT1, PIOA_LED1, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(IOPORT1, PIOA_LED2); + palSetPadMode(IOPORT1, PIOA_LED2, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * buttons setup. + */ + palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK, 0, PAL_MODE_INPUT); + + /* + * MMC/SD slot setup. + */ + palSetGroupMode(IOPORT1, + PIOA_MMC_WP_MASK | PIOA_MMC_CP_MASK, + 0, + PAL_MODE_INPUT); + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; +} diff --git a/boards/OLIMEX_SAM7_P256/board.h b/boards/OLIMEX_SAM7_P256/board.h new file mode 100644 index 000000000..d16c13271 --- /dev/null +++ b/boards/OLIMEX_SAM7_P256/board.h @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex SAM7-P256 development board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_SAM7_P256 + +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7_PLATFORM) +#define SAM7_PLATFORM SAM7S256 +#endif + +#include "at91sam7.h" + +#define CLK 18432000 +#define MCK 48054857 + +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +/* + * I/O definitions. + */ +#define PIOA_LED1 18 +#define PIOA_LED1_MASK (1 << PIOA_LED1_MASK) +#define PIOA_LED2 17 +#define PIOA_LED2_MASK (1 << PIOA_LED2_MASK) +#define PIOA_B1 19 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 20 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_DP_PUP 25 +#define PIOA_DD_PUP_MASK (1 << PIOA_DP_PUP) +#define PIOA_USB_D 26 +#define PIOA_USB_D_MASK (1 << PIOA_USB_D) + +#define PIOA_MMC_WP 25 +#define PIOA_MMC_WP_MASK (1 << PIOA_MMC_WP) +#define PIOA_MMC_CP 15 +#define PIOA_MMC_CP_MASK (1 << PIOA_MMC_CP) +#define PIOA_MMC_NPCS0 11 +#define PIOA_MMC_NPCS0_MASK (1 << PIOA_MMC_NPCS0_MASK) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_SAM7_P256/board.mk b/boards/OLIMEX_SAM7_P256/board.mk new file mode 100644 index 000000000..e9fb6691a --- /dev/null +++ b/boards/OLIMEX_SAM7_P256/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256 diff --git a/boards/OLIMEX_STM32_103STK/board.c b/boards/OLIMEX_STM32_103STK/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.c @@ -0,0 +1,50 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_103STK/board.h b/boards/OLIMEX_STM32_103STK/board.h new file mode 100644 index 000000000..df1b832d2 --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.h @@ -0,0 +1,168 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM32-103STK proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_103STK +#define BOARD_NAME "Olimex STM32-103STK" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_WAKEUP 0 +#define GPIOC_BUTTON_TAMPER 13 +#define GPIOC_JOY 5 +#define GPIOC_JOY_CENTER_BUT 6 + +#define GPIOA_SPI1NSS 4 +#define GPIOB_SPI2NSS 12 + +#define GPIOC_MMCWP 2 +#define GPIOC_MMCCP 1 + +#define GPIOC_USB_P 4 +#define GPIOC_LCD_RES 7 +#define GPIOC_NRF_CE 8 +#define GPIOC_NRF_IRQ 9 +#define GPIOC_LCD_E 10 + +#define GPIOC_USB_DISC 11 +#define GPIOC_LED 12 + +#define GPIOB_ACCEL_IRQ 5 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (BUTTON). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + */ +#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB6,7 - Alternate open drain (I2C1). + * PB10,11 - Alternate open drain (I2C2). + * PB12 - Push Pull output (MMC SPI2 NSS). + * PB13 - Alternate output (MMC SPI2 SCK). + * PB14 - Normal input (MMC SPI2 MISO). + * PB15 - Alternate output (MMC SPI2 MOSI). + */ +#define VAL_GPIOBCRL 0xEE888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0xB4B3EE88 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC4 - Normal input because there is an external resistor. + * PC5 - Analog input (joystick). + * PC6 - Normal input because there is an external resistor. + * PC7 - Normal input because there is an external resistor. + * PC10 - Push Pull output (CAN CNTRL). + * PC11 - Push Pull output (USB DISC). + * PC12 - Open Drain output (LED). + */ +#define VAL_GPIOCCRL 0x44048888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88863388 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +/* + * USB bus activation macro, required by the USB driver. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC) + +/* + * USB bus de-activation macro, required by the USB driver. + */ +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_103STK/board.mk b/boards/OLIMEX_STM32_103STK/board.mk new file mode 100644 index 000000000..383e1c490 --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK diff --git a/boards/OLIMEX_STM32_E407/board.c b/boards/OLIMEX_STM32_E407/board.c new file mode 100644 index 000000000..a4152433a --- /dev/null +++ b/boards/OLIMEX_STM32_E407/board.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + static bool_t last_status = FALSE; + + if (blkIsTransferring(sdcp)) + return last_status; + return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_E407/board.h b/boards/OLIMEX_STM32_E407/board.h new file mode 100644 index 000000000..505f30f7d --- /dev/null +++ b/boards/OLIMEX_STM32_E407/board.h @@ -0,0 +1,1301 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Olimex STM32-E407 board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_E407 +#define BOARD_NAME "Olimex STM32-E407" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_KS8721_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_WKUP 0 +#define GPIOA_ETH_RMII_REF_CLK 1 +#define GPIOA_ETH_RMII_MDIO 2 +#define GPIOA_ETH_RMII_MDINT 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_ETH_RMII_CRS_DV 7 +#define GPIOA_USB_HS_BUSON 8 +#define GPIOA_OTG_FS_VBUS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_JTAG_TMS 13 +#define GPIOA_JTAG_TCK 14 +#define GPIOA_JTAG_TDI 15 + +#define GPIOB_USB_FS_BUSON 0 +#define GPIOB_USB_HS_FAULT 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTAG_TDO 3 +#define GPIOB_JTAG_TRST 4 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 +#define GPIOB_I2C1_SCL 8 +#define GPIOB_I2C1_SDA 9 +#define GPIOB_SPI2_SCK 10 +#define GPIOB_PIN11 11 +#define GPIOB_OTG_HS_ID 12 +#define GPIOB_OTG_HS_VBUS 13 +#define GPIOB_OTG_HS_DM 14 +#define GPIOB_OTG_HS_DP 15 + +#define GPIOC_PIN0 0 +#define GPIOC_ETH_RMII_MDC 1 +#define GPIOC_SPI2_MISO 2 +#define GPIOC_SPI2_MOSI 3 +#define GPIOC_ETH_RMII_RXD0 4 +#define GPIOC_ETH_RMII_RXD1 5 +#define GPIOC_USART6_TX 6 +#define GPIOC_USART6_RX 7 +#define GPIOC_SD_D0 8 +#define GPIOC_SD_D1 9 +#define GPIOC_SD_D2 10 +#define GPIOC_SD_D3 11 +#define GPIOC_SD_CLK 12 +#define GPIOC_LED 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_SD_CMD 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_USB_FS_FAULT 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_SPI2_CS 10 +#define GPIOG_ETH_RMII_TXEN 11 +#define GPIOG_PIN12 12 +#define GPIOG_ETH_RMII_TXD0 13 +#define GPIOG_ETH_RMII_TXD1 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON_WKUP (input floating). + * PA1 - ETH_RMII_REF_CLK (alternate 11). + * PA2 - ETH_RMII_MDIO (alternate 11). + * PA3 - ETH_RMII_MDINT (input floating). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - ETH_RMII_CRS_DV (alternate 11). + * PA8 - USB_HS_BUSON (output pushpull maximum). + * PA9 - OTG_FS_VBUS (input pulldown). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - JTAG_TMS (alternate 0). + * PA14 - JTAG_TCK (alternate 0). + * PA15 - JTAG_TDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\ + PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \ + PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\ + PIN_OSPEED_100M(GPIOA_PIN4) | \ + PIN_OSPEED_100M(GPIOA_PIN5) | \ + PIN_OSPEED_100M(GPIOA_PIN6) | \ + PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TCK) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\ + PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \ + PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\ + PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TDI, 0)) + +/* + * GPIOB setup: + * + * PB0 - USB_FS_BUSON (output pushpull maximum). + * PB1 - USB_HS_FAULT (input floating). + * PB2 - BOOT1 (input floating). + * PB3 - JTAG_TDO (alternate 0). + * PB4 - JTAG_TRST (alternate 0). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - I2C1_SCL (alternate 4). + * PB9 - I2C1_SDA (alternate 4). + * PB10 - SPI2_SCK (alternate 5). + * PB11 - PIN11 (input pullup). + * PB12 - OTG_HS_ID (alternate 12). + * PB13 - OTG_HS_VBUS (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \ + PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \ + PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \ + PIN_OSPEED_100M(GPIOB_BOOT1) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_PIN6) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_100M(GPIOB_SPI2_SCK) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_ID) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_100M(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\ + PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ + PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) | \ + PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - ETH_RMII_MDC (alternate 11). + * PC2 - SPI2_MISO (alternate 5). + * PC3 - SPI2_MOSI (alternate 5). + * PC4 - ETH_RMII_RXD0 (alternate 11). + * PC5 - ETH_RMII_RXD1 (alternate 11). + * PC6 - USART6_TX (alternate 8). + * PC7 - USART6_RX (alternate 8). + * PC8 - SD_D0 (alternate 12). + * PC9 - SD_D1 (alternate 12). + * PC10 - SD_D2 (alternate 12). + * PC11 - SD_D3 (alternate 12). + * PC12 - SD_CLK (alternate 12). + * PC13 - LED (output pushpull maximum). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\ + PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\ + PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \ + PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \ + PIN_MODE_OUTPUT(GPIOC_LED) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\ + PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) | \ + PIN_OSPEED_100M(GPIOC_SPI2_MISO) | \ + PIN_OSPEED_100M(GPIOC_SPI2_MOSI) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \ + PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \ + PIN_OSPEED_100M(GPIOC_USART6_TX) | \ + PIN_OSPEED_100M(GPIOC_USART6_RX) | \ + PIN_OSPEED_100M(GPIOC_SD_D0) | \ + PIN_OSPEED_100M(GPIOC_SD_D1) | \ + PIN_OSPEED_100M(GPIOC_SD_D2) | \ + PIN_OSPEED_100M(GPIOC_SD_D3) | \ + PIN_OSPEED_100M(GPIOC_SD_CLK) | \ + PIN_OSPEED_100M(GPIOC_LED) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\ + PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\ + PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\ + PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \ + PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOC_LED) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_SPI2_MISO) | \ + PIN_ODR_HIGH(GPIOC_SPI2_MOSI) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_USART6_TX) | \ + PIN_ODR_HIGH(GPIOC_USART6_RX) | \ + PIN_ODR_HIGH(GPIOC_SD_D0) | \ + PIN_ODR_HIGH(GPIOC_SD_D1) | \ + PIN_ODR_HIGH(GPIOC_SD_D2) | \ + PIN_ODR_HIGH(GPIOC_SD_D3) | \ + PIN_ODR_HIGH(GPIOC_SD_CLK) | \ + PIN_ODR_HIGH(GPIOC_LED) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \ + PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \ + PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \ + PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \ + PIN_AFIO_AF(GPIOC_USART6_RX, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D1, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D2, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D3, 12) | \ + PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \ + PIN_AFIO_AF(GPIOC_LED, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - SD_CMD (alternate 12). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ + PIN_OSPEED_100M(GPIOD_PIN1) | \ + PIN_OSPEED_100M(GPIOD_SD_CMD) | \ + PIN_OSPEED_100M(GPIOD_PIN3) | \ + PIN_OSPEED_100M(GPIOD_PIN4) | \ + PIN_OSPEED_100M(GPIOD_PIN5) | \ + PIN_OSPEED_100M(GPIOD_PIN6) | \ + PIN_OSPEED_100M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_PIN8) | \ + PIN_OSPEED_100M(GPIOD_PIN9) | \ + PIN_OSPEED_100M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_PIN11) | \ + PIN_OSPEED_100M(GPIOD_PIN12) | \ + PIN_OSPEED_100M(GPIOD_PIN13) | \ + PIN_OSPEED_100M(GPIOD_PIN14) | \ + PIN_OSPEED_100M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \ + PIN_OSPEED_100M(GPIOE_PIN1) | \ + PIN_OSPEED_100M(GPIOE_PIN2) | \ + PIN_OSPEED_100M(GPIOE_PIN3) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_PIN8) | \ + PIN_OSPEED_100M(GPIOE_PIN9) | \ + PIN_OSPEED_100M(GPIOE_PIN10) | \ + PIN_OSPEED_100M(GPIOE_PIN11) | \ + PIN_OSPEED_100M(GPIOE_PIN12) | \ + PIN_OSPEED_100M(GPIOE_PIN13) | \ + PIN_OSPEED_100M(GPIOE_PIN14) | \ + PIN_OSPEED_100M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - USB_FS_FAULT (input floating). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ + PIN_OSPEED_100M(GPIOF_PIN1) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_PIN4) | \ + PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_PIN9) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \ + PIN_OSPEED_100M(GPIOF_PIN12) | \ + PIN_OSPEED_100M(GPIOF_PIN13) | \ + PIN_OSPEED_100M(GPIOF_PIN14) | \ + PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - SPI2_CS (output pushpull maximum). + * PG11 - ETH_RMII_TXEN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - ETH_RMII_TXD0 (alternate 11). + * PG14 - ETH_RMII_TXD1 (alternate 11). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_OUTPUT(GPIOG_SPI2_CS) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\ + PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ + PIN_OSPEED_100M(GPIOG_PIN1) | \ + PIN_OSPEED_100M(GPIOG_PIN2) | \ + PIN_OSPEED_100M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_PIN4) | \ + PIN_OSPEED_100M(GPIOG_PIN5) | \ + PIN_OSPEED_100M(GPIOG_PIN6) | \ + PIN_OSPEED_100M(GPIOG_PIN7) | \ + PIN_OSPEED_100M(GPIOG_PIN8) | \ + PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_SPI2_CS) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \ + PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \ + PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \ + PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) | \ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\ + PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_SPI2_CS) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_SPI2_CS, 0) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_E407/board.mk b/boards/OLIMEX_STM32_E407/board.mk new file mode 100644 index 000000000..0f9c9e4a7 --- /dev/null +++ b/boards/OLIMEX_STM32_E407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_E407/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_E407 diff --git a/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/boards/OLIMEX_STM32_E407/cfg/board.chcfg new file mode 100644 index 000000000..4d4abeb04 --- /dev/null +++ b/boards/OLIMEX_STM32_E407/cfg/board.chcfg @@ -0,0 +1,335 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + Olimex STM32-E407 + OLIMEX_STM32_E407 + + + + + + + MII_KS8721_ID + RMII + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/OLIMEX_STM32_H103/board.c b/boards/OLIMEX_STM32_H103/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/boards/OLIMEX_STM32_H103/board.c @@ -0,0 +1,50 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_H103/board.h b/boards/OLIMEX_STM32_H103/board.h new file mode 100644 index 000000000..76c66099d --- /dev/null +++ b/boards/OLIMEX_STM32_H103/board.h @@ -0,0 +1,132 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM33-H103 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_H103 +#define BOARD_NAME "Olimex STM32-H103" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 + +#define GPIOC_USB_DISC 11 +#define GPIOC_LED 12 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (BUTTON). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + */ +#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC6 - Normal input because there is an external resistor. + * PC7 - Normal input because there is an external resistor. + * PC11 - Open Drain output (USB disconnect). + * PC12 - Push Pull output (LED). + */ +#define VAL_GPIOCCRL 0x44888888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88837888 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_H103/board.mk b/boards/OLIMEX_STM32_H103/board.mk new file mode 100644 index 000000000..040374ffc --- /dev/null +++ b/boards/OLIMEX_STM32_H103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H103/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H103 diff --git a/boards/OLIMEX_STM32_LCD/board.c b/boards/OLIMEX_STM32_LCD/board.c new file mode 100644 index 000000000..397ed99b9 --- /dev/null +++ b/boards/OLIMEX_STM32_LCD/board.c @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, + {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, + {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + (void)sdcp; + + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + (void)sdcp; + + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + (void)mmcp; + + return TRUE; +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + (void)mmcp; + + return FALSE; +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} + diff --git a/boards/OLIMEX_STM32_LCD/board.h b/boards/OLIMEX_STM32_LCD/board.h new file mode 100644 index 000000000..0d510abac --- /dev/null +++ b/boards/OLIMEX_STM32_LCD/board.h @@ -0,0 +1,196 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM32-LCD proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_LCD +#define BOARD_NAME "Olimex STM32-LCD" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_HD + +/* + * IO pins assignments. + */ +#define GPIOA_SPI1NSS 4 + +#define GPIOB_SPI2NSS 12 + +#define GPIOA_USB_P 0 +#define GPIOD_USB_DISC 2 + +#define GPIOE_TFT_RST 2 +#define GPIOD_TFT_LIGHT 13 +#define GPIOC_TFT_YD 0 +#define GPIOC_TFT_YU 1 +#define GPIOC_TFT_XL 2 +#define GPIOC_TFT_XR 3 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (USB P). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + * PA11 - Normal input (USB DM). + * PA12 - Normal input (USB DP). + */ +#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC0 - Analog Input (TP_YD). + * PC1 - Analog Input (TP_YU). + * PC2 - Analog Input (TP_XL). + * PC3 - Analog Input (TP_XR). + * PC8 - Alternate PP 50M (SD_D0). + * PC9 - Alternate PP 50M (SD_D1). + * PC10 - Alternate PP 50M (SD_D2). + * PC11 - Alternate PP 50M (SD_D3). + * PC12 - Alternate PP 50M (SD_CLK). + * PC14 - Normal input (XTAL). + * PC15 - Normal input (XTAL). + */ +#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD2 - Alternate PP 50M (SD_CMD) + * PD0 - Alternate PP 50M (FSMC_D2) + * PD1 - Alternate PP 50M (FSMC_D3) + * PD4 - Alternate PP 50M (TFT_RD) + * PD5 - Alternate PP 50M (TFT_WR) + * PD7 - Alternate PP 50M (TFT_CS) + * PD8 - Alternate PP 50M (FSMC_D13) + * PD9 - Alternate PP 50M (FSMC_D14) + * PD10 - Alternate PP 50M (FSMC_D15) + * PD14 - Alternate PP 50M (FSMC_D0) + * PD15 - Alternate PP 50M (FSMC_D1) + */ +#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */ +#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + * PE2 - Digital Output (TFT_RST) + * PE3 - Alternate PP 50M (TFT_RS) + * PE7 - Alternate PP 50M (FSMC_D4) + * PE8 - Alternate PP 50M (FSMC_D5) + * PE9 - Alternate PP 50M (FSMC_D6) + * PE10 - Alternate PP 50M (FSMC_D7) + * PE11 - Alternate PP 50M (FSMC_D8) + * PE12 - Alternate PP 50M (FSMC_D9) + * PE13 - Alternate PP 50M (FSMC_D10) + * PE14 - Alternate PP 50M (FSMC_D11) + * PE15 - Alternate PP 50M (FSMC_D12) + */ +#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */ +#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +/* + * Port F setup. + * Everything input with pull-up expect: + */ +#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ +#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ +#define VAL_GPIOFODR 0xFFFFFFFF + +/* + * Port G setup. + * Everything input with pull-up expect: + */ +#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ +#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ +#define VAL_GPIOGODR 0xFFFFFFFF + +/* + * USB bus activation macro, required by the USB driver. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC) + +/* + * USB bus de-activation macro, required by the USB driver. + */ +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_LCD/board.mk b/boards/OLIMEX_STM32_LCD/board.mk new file mode 100644 index 000000000..c1cc061de --- /dev/null +++ b/boards/OLIMEX_STM32_LCD/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_LCD/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_LCD diff --git a/boards/OLIMEX_STM32_P103/board.c b/boards/OLIMEX_STM32_P103/board.c new file mode 100644 index 000000000..ab992f116 --- /dev/null +++ b/boards/OLIMEX_STM32_P103/board.c @@ -0,0 +1,65 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return palReadPad(GPIOC, GPIOC_MMCCP); +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(GPIOC, GPIOC_MMCWP); +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_P103/board.h b/boards/OLIMEX_STM32_P103/board.h new file mode 100644 index 000000000..58f020bcc --- /dev/null +++ b/boards/OLIMEX_STM32_P103/board.h @@ -0,0 +1,156 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM32-P103 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_P103 +#define BOARD_NAME "Olimex STM32-P103" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_SPI1NSS 4 + +#define GPIOB_SPI2NSS 12 + +#define GPIOC_USB_P 4 +#define GPIOC_MMCWP 6 +#define GPIOC_MMCCP 7 +#define GPIOC_CAN_CNTL 10 +#define GPIOC_USB_DISC 11 +#define GPIOC_LED 12 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (BUTTON). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + * PA11 - Normal input (USB DM). + * PA12 - Normal input (USB DP). + */ +#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB13 - Alternate output (MMC SPI2 SCK). + * PB14 - Normal input (MMC SPI2 MISO). + * PB15 - Alternate output (MMC SPI2 MOSI). + */ +#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0xB4B88888 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC4 - Normal input because there is an external resistor. + * PC6 - Normal input because there is an external resistor. + * PC7 - Normal input because there is an external resistor. + * PC10 - Push Pull output (CAN CNTRL). + * PC11 - Push Pull output (USB DISC). + * PC12 - Push Pull output (LED). + */ +#define VAL_GPIOCCRL 0x44848888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88833388 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +/* + * USB bus activation macro, required by the USB driver. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC) + +/* + * USB bus de-activation macro, required by the USB driver. + */ +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_P103/board.mk b/boards/OLIMEX_STM32_P103/board.mk new file mode 100644 index 000000000..701970e84 --- /dev/null +++ b/boards/OLIMEX_STM32_P103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P103 diff --git a/boards/OLIMEX_STM32_P107/board.c b/boards/OLIMEX_STM32_P107/board.c new file mode 100644 index 000000000..586c27c13 --- /dev/null +++ b/boards/OLIMEX_STM32_P107/board.c @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* + * Card detection through the card internal pull-up on D3. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + static bool_t last_status = FALSE; + + (void)mmcp; + if ((palReadLatch(GPIOA) & PAL_PORT_BIT(GPIOA_SPI3_CS_MMC)) == 0) + return last_status; + return last_status = (bool_t)palReadPad(GPIOA, GPIOA_SPI3_CS_MMC); +} + +/* + * Card write protection detection is not possible, the card is always + * reported as not protected. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return FALSE; +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Several I/O pins are re-mapped: + * USART3 to the PD8/PD9 pins. + * I2C1 to the PB8/PB9 pins. + * SPI3 to the PC10/PC11/PC12 pins. + */ + AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP | + AFIO_MAPR_I2C1_REMAP | + AFIO_MAPR_SPI3_REMAP; +} diff --git a/boards/OLIMEX_STM32_P107/board.h b/boards/OLIMEX_STM32_P107/board.h new file mode 100644 index 000000000..8bf523d33 --- /dev/null +++ b/boards/OLIMEX_STM32_P107/board.h @@ -0,0 +1,193 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM32-P107 Rev.A evaluation board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_P107_REV_A +#define BOARD_NAME "Olimex STM32-P107 Rev.A" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 25000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_CL + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_STE101P_ID +#define BOARD_PHY_RMII + +/* + * IO pins assignments. + */ +#define GPIOA_SWITCH_WKUP 0 +#define GPIOA_SPI3_CS_MMC 4 +#define GPIOC_LED_STATUS1 6 +#define GPIOC_LED_STATUS2 7 +#define GPIOC_SWITCH_TAMPER 13 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (WKUP BUTTON). + * PA1 - Normal input (ETH_RMII_REF_CLK). + * PA2 - Alternate output (ETH_RMII_MDIO). + * PA3 - Input with PU (unconnected). + * PA4 - Open Drain output (CS_MMC). + * PA5 - Input with PU (unconnected). + * PA6 - Input with PU (unconnected). + * PA7 - Normal input (ETH_RMII_CRS_DV). + * PA8 - Alternate output (MCO). + * PA9 - Normal input (OTG_VBUS). + * PA10 - Normal input (OTG_ID). + * PA11 - Normal input (OTG_DM). + * PA12 - Normal input (OTG_DP). + * PA13 - Normal input (TMS). + * PA14 - Normal input (TCK). + * PA15 - Normal input (TDI). + */ +#define VAL_GPIOACRL 0x48878B44 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x4444444B /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup: + * PB0 - Input with PU (unconnected). + * PB1 - Input with PU (unconnected). + * PB2 - Normal input (BOOT1). + * PB3 - Normal input (TDO). + * PB4 - Normal input (TRST). + * PB5 - Input with PU (unconnected). + * PB6 - Input with PU (unconnected). + * PB7 - Input with PU (unconnected). + * PB8 - Alternate O.D. (I2C1 SCL, remapped). + * PB9 - Alternate O.D. (I2C1 SDA, remapped). + * PB10 - Input with PU (unconnected). + * PB11 - Alternate output (ETH_RMII_TX_EN). + * PB12 - Alternate output (ETH_RMII_TXD0). + * PB13 - Alternate output (ETH_RMII_TXD1). + * PB14 - Input with PU (unconnected). + * PB15 - Push Pull output (CS_UEXT). + */ +#define VAL_GPIOBCRL 0x88844488 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0x38BBB8FF /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup: + * PC0 - Input with PU (unconnected). + * PC1 - Alternate output (ETH_MDC). + * PC2 - Input with PU (unconnected). + * PC3 - Input with PU (unconnected). + * PC4 - Normal input (ETH_RMII_RXD0). + * PC5 - Normal input (ETH_RMII_RXD1). + * PC6 - Push Pull output (STAT1 green LED). + * PC7 - Push Pull output (STAT2 yellow LED). + * PC8 - Input with PU (unconnected). + * PC9 - Input with PU (unconnected). + * PC10 - Alternate output (SPI3 SCK). + * PC11 - Input with PU (SPI3 MISO). + * PC12 - Alternate output (SPI3 MOSI). + * PC13 - Normal input (TAMPER). + * PC14 - Normal input (OSC32 IN). + * PC15 - Normal input (OSC32 OUT). + */ +#define VAL_GPIOCCRL 0x334488B8 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x444B8B88 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFF3F + +/* + * Port D setup: + * PD0 - Input with PU (unconnected). + * PD1 - Input with PU (unconnected). + * PD2 - Input with PU (unconnected). + * PD3 - Input with PU (unconnected). + * PD4 - Input with PU (unconnected). + * PD5 - Alternate output (USART2 TX, UEXT). + * PD6 - Input with PU (USART2 RX, UEXT). + * PD7 - Push Pull output (USB_VBUSON). + * PD8 - Alternate output (USART2 TX, remapped). + * PD9 - Normal input (USART2 RX, remapped). + * PD10 - Input with PU (unconnected). + * PD11 - Normal input (USART2 CTS, remapped). + * PD12 - Alternate output (USART2 RTS, remapped). + * PD13 - Input with PU (unconnected). + * PD14 - Input with PU (unconnected). + * PD15 - Input with PU (unconnected). + */ +#define VAL_GPIODCRL 0x38B88888 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x888B484B /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + * PE14 - Normal input (ETH_RMII_MDINT). + * PE15 - Normal input (USB_FAULT). + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x44888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_P107/board.mk b/boards/OLIMEX_STM32_P107/board.mk new file mode 100644 index 000000000..63f70119a --- /dev/null +++ b/boards/OLIMEX_STM32_P107/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P107/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P107 diff --git a/boards/OLIMEX_STM32_P407/board.c b/boards/OLIMEX_STM32_P407/board.c new file mode 100644 index 000000000..17ef1d54f --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + static bool_t last_status = FALSE; + (void)mmcp; + + if ((palReadLatch(GPIOD) & PAL_PORT_BIT(GPIOD_SPI3_CS)) == 0) + return last_status; + return last_status = (bool_t)palReadPad(GPIOD, GPIOD_SPI3_CS); +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_P407/board.h b/boards/OLIMEX_STM32_P407/board.h new file mode 100644 index 000000000..66279a8f9 --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.h @@ -0,0 +1,651 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Olimex STM32-P407 board. + * NOTE: Part of JTAG signals are used for other functions, this board can be + * used using SWD only. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_P407 +#define BOARD_NAME "Olimex STM32-P407" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_KS8721_ID +#define BOARD_PHY_RMII + +/* + * Board frequencies. + * NOTE: The LSE crystal is not fitted by default on the board. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 25000000 + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_WKUP 0 +#define GPIOA_ETH_RMII_REF_CLK 1 +#define GPIOA_ETH_RMII_MDIO 2 +#define GPIOA_ETH_RMII_MDINT 3 +#define GPIOA_DCMI_HSYNC 4 +#define GPIOA_LCD_SCK 5 +#define GPIOA_DCMI_PIXCLK 6 +#define GPIOA_ETH_RMII_CRS_DV 7 +#define GPIOA_MCO1 8 +#define GPIOA_OTG_FS_VBUS 9 +#define GPIOA_DCMI_D1 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_I2S3_WS 15 + +#define GPIOB_LCD_BL 0 +#define GPIOB_BUZ 1 +#define GPIOB_CAM_ENB 2 +#define GPIOB_I2S3_CK 3 +#define GPIOB_LCD_MISO 4 +#define GPIOB_I2S3_SD 5 +#define GPIOB_DCMI_D5 6 +#define GPIOB_DCMI_VSYNC 7 +#define GPIOB_CAN1_RX 8 +#define GPIOB_CAN1_TX 9 +#define GPIOB_USB_FS_FAULT 10 +#define GPIOB_ETH_RMII_TX_EN 11 +#define GPIOB_OTG_HS_ID 12 +#define GPIOB_OTG_HS_VBUS 13 +#define GPIOB_OTG_HS_DM 14 +#define GPIOB_OTG_HS_DP 15 + +#define GPIOC_TRIM 0 +#define GPIOC_ETH_RMII_MDC 1 +#define GPIOC_USB_FS_VBUSON 2 +#define GPIOC_LCD_MOSI 3 +#define GPIOC_ETH_RMII_RXD0 4 +#define GPIOC_ETH_RMII_RXD1 5 +#define GPIOC_DCMI_D0_US6_TX 6 +#define GPIOC_I2S3_MCK 7 +#define GPIOC_DCMI_D2 8 +#define GPIOC_DCMI_D3 9 +#define GPIOC_SPI3_SCK 10 +#define GPIOC_SPI3_MISO 11 +#define GPIOC_SPI3_MOSI 12 +#define GPIOC_SWITCH_TAMPER 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_USELESS0 0 +#define GPIOD_USELESS1 1 +#define GPIOD_SPI3_CS 2 +#define GPIOD_LCD_RST 3 +#define GPIOD_USELESS4 4 +#define GPIOD_USELESS5 5 +#define GPIOD_LCD_CS 6 +#define GPIOD_USELESS7 7 +#define GPIOD_USART3_TX 8 +#define GPIOD_USART3_RX 9 +#define GPIOD_USELESS10 10 +#define GPIOD_USART3_CTS 11 +#define GPIOD_USART3_RTS 12 +#define GPIOD_USB_HS_FAULT 13 +#define GPIOD_USELESS14 14 +#define GPIOD_USELESS15 15 + +#define GPIOE_0 0 +#define GPIOE_1 1 +#define GPIOE_TEMP_ALERT 2 +#define GPIOE_USB_HS_VBUSON 3 +#define GPIOE_4 4 +#define GPIOE_5 5 +#define GPIOE_6 6 +#define GPIOE_7 7 +#define GPIOE_8 8 +#define GPIOE_9 9 +#define GPIOE_10 10 +#define GPIOE_11 11 +#define GPIOE_12 12 +#define GPIOE_13 13 +#define GPIOE_14 14 +#define GPIOE_15 15 + +#define GPIOF_0 0 +#define GPIOF_1 1 +#define GPIOF_2 2 +#define GPIOF_3 3 +#define GPIOF_4 4 +#define GPIOF_5 5 +#define GPIOF_STAT1 6 +#define GPIOF_STAT2 7 +#define GPIOF_STAT3 8 +#define GPIOF_CAM_PWR 9 +#define GPIOF_10 10 +#define GPIOF_CAM_RS 11 +#define GPIOF_12 12 +#define GPIOF_13 13 +#define GPIOF_14 14 +#define GPIOF_15 15 + +#define GPIOG_0 0 +#define GPIOG_1 1 +#define GPIOG_2 2 +#define GPIOG_3 3 +#define GPIOG_4 4 +#define GPIOG_5 5 +#define GPIOG_RIGHT 6 +#define GPIOG_UP 7 +#define GPIOG_DOWN 8 +#define GPIOG_USART6_RX 9 +#define GPIOG_10 10 +#define GPIOG_LEFT 11 +#define GPIOG_12 12 +#define GPIOG_ETH_RMII_TXD0 13 +#define GPIOG_ETH_RMII_TXD1 14 +#define GPIOG_CENT 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * Port A setup. + * + * PA0 - GPIOA_BUTTON_WKUP (input floating). + * PA1 - GPIOA_ETH_RMII_REF_CLK(alternate 11). + * PA2 - GPIOA_ETH_RMII_MDIO (alternate 11). + * PA3 - GPIOA_ETH_RMII_MDINT (input floating). + * PA4 - GPIOA_DCMI_HSYNC (input pull-up). + * PA5 - GPIOA_LCD_SCK (output push-pull). + * PA6 - GPIOA_DCMI_PIXCLK (input pull-up). + * PA7 - GPIOA_ETH_RMII_CRS_DV (alternate 11). + * PA8 - GPIOA_MCO1 (alternate 0). + * PA9 - GPIOA_OTG_FS_VBUS (input pull-up). + * PA10 - GPIOA_DCMI_D1 (input pull-up). + * PA11 - GPIOA_OTG_FS_DM (alternate 10). + * PA12 - GPIOA_OTG_FS_DP (alternate 10). + * PA13 - GPIOA_SWDIO (alternate 0). + * PA14 - GPIOA_SWCLK (alternate 0, pull-down). + * PA15 - GPIOA_I2S3_WS (alternate 6). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \ + PIN_MODE_INPUT(GPIOA_DCMI_HSYNC) | \ + PIN_MODE_OUTPUT(GPIOA_LCD_SCK) | \ + PIN_MODE_INPUT(GPIOA_DCMI_PIXCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) | \ + PIN_MODE_ALTERNATE(GPIOA_MCO1) | \ + PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \ + PIN_MODE_INPUT(GPIOA_DCMI_D1) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_I2S3_WS)) +#define VAL_GPIOA_OTYPER 0x00000000 +#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOA_PUPDR (PIN_PUDR_PULLUP(GPIOA_DCMI_HSYNC) | \ + PIN_PUDR_PULLUP(GPIOA_DCMI_PIXCLK) | \ + PIN_PUDR_PULLDOWN(GPIOA_OTG_FS_VBUS) | \ + PIN_PUDR_PULLUP(GPIOA_DCMI_D1) | \ + PIN_PUDR_PULLDOWN(GPIOA_SWCLK)) +#define VAL_GPIOA_ODR 0xFFFFFFDF +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \ + PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_MCO1, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_I2S3_WS, 6)) + +/* + * Port B setup. + * + * PB0 - GPIOB_LCD_BL (output push-pull). + * PB1 - GPIOB_BUZ (output push-pull). + * PB2 - GPIOB_CAM_ENB (input floating). + * PB3 - GPIOB_I2S3_CK (alternate 6). + * PB4 - GPIOB_LCD_MISO (input floating). + * PB5 - GPIOB_I2S3_SD (alternate 6). + * PB6 - GPIOB_DCMI_D5 (input pull-up). + * PB7 - GPIOB_DCMI_VSYNC (input pull-up). + * PB8 - GPIOB_CAN1_RX (alternate 9). + * PB9 - GPIOB_CAN1_TX (alternate 9). + * PB10 - GPIOB_USB_FS_FAULT (input floating). + * PB11 - GPIOB_ETH_RMII_TX_EN (alternate 11). + * PB12 - GPIOB_OTG_HS_ID (alternate 12). + * PB13 - GPIOB_OTG_HS_VBUS (input pull-up). + * PB14 - GPIOB_OTG_HS_DM (alternate 12). + * PB15 - GPIOB_OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LCD_BL) | \ + PIN_MODE_OUTPUT(GPIOB_BUZ) | \ + PIN_MODE_INPUT(GPIOB_CAM_ENB) | \ + PIN_MODE_ALTERNATE(GPIOB_I2S3_CK) | \ + PIN_MODE_INPUT(GPIOB_LCD_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_I2S3_SD) | \ + PIN_MODE_INPUT(GPIOB_DCMI_D5) | \ + PIN_MODE_INPUT(GPIOB_DCMI_VSYNC) | \ + PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) | \ + PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) | \ + PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) | \ + PIN_MODE_ALTERNATE(GPIOB_ETH_RMII_TX_EN) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER 0x00000000 +#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(GPIOB_DCMI_D5) | \ + PIN_PUDR_PULLUP(GPIOB_DCMI_VSYNC) | \ + PIN_PUDR_PULLDOWN(GPIOB_OTG_HS_VBUS)) +#define VAL_GPIOB_ODR 0xFFFFFFFC +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_I2S3_CK, 6) | \ + PIN_AFIO_AF(GPIOB_I2S3_SD, 6)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_CAN1_RX, 9) | \ + PIN_AFIO_AF(GPIOB_CAN1_TX, 9) | \ + PIN_AFIO_AF(GPIOB_ETH_RMII_TX_EN, 11) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12)) + +/* + * Port C setup. + * + * PC0 - GPIOC_TRIM (input floating). + * PC1 - GPIOC_ETH_RMII_MDC (alternate 11). + * PC2 - GPIOC_USB_FS_VBUSON (output push-pull). + * PC3 - GPIOC_LCD_MOSI (output push-pull). + * PC4 - GPIOC_ETH_RMII_RXD0 (alternate 11). + * PC5 - GPIOC_ETH_RMII_RXD1 (alternate 11). + * PC6 - GPIOC_DCMI_D0_US6_TX (alternate 8). + * PC7 - GPIOC_I2S3_MCK (alternate 6). + * PC8 - GPIOC_DCMI_D2 (input pull-up). + * PC9 - GPIOC_DCMI_D3 (input pull-up). + * PC10 - GPIOC_SPI3_SCK (alternate 6). + * PC11 - GPIOC_SPI3_MISO (alternate 6). + * PC12 - GPIOC_SPI3_MOSI (alternate 6). + * PC13 - GPIOC_SWITCH_TAMPER (input floating). + * PC14 - GPIOC_OSC32_IN (input floating). + * PC15 - GPIOC_OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_TRIM) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) | \ + PIN_MODE_OUTPUT(GPIOC_USB_FS_VBUSON) | \ + PIN_MODE_OUTPUT(GPIOC_LCD_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) | \ + PIN_MODE_ALTERNATE(GPIOC_DCMI_D0_US6_TX) | \ + PIN_MODE_ALTERNATE(GPIOC_I2S3_MCK) | \ + PIN_MODE_INPUT(GPIOC_DCMI_D2) | \ + PIN_MODE_INPUT(GPIOC_DCMI_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_INPUT(GPIOC_SWITCH_TAMPER) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER 0x00000000 +#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOC_PUPDR (PIN_PUDR_PULLUP(GPIOC_DCMI_D2) | \ + PIN_PUDR_PULLUP(GPIOC_DCMI_D3)) +#define VAL_GPIOC_ODR 0xFFFFFFF3 +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \ + PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \ + PIN_AFIO_AF(GPIOC_DCMI_D0_US6_TX, 8) | \ + PIN_AFIO_AF(GPIOC_I2S3_MCK, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6)) + +/* + * Port D setup. + * + * PD0 - GPIOD_USELESS0 (input pull-up). + * PD1 - GPIOD_USELESS1 (input pull-up). + * PD2 - GPIOD_SPI3_CS (output opendrain). + * PD3 - GPIOD_LCD_RST (output push-pull). + * PD4 - GPIOD_USELESS4 (input pull-up). + * PD5 - GPIOD_USELESS5 (input pull-up). + * PD6 - GPIOD_LCD_CS (output push-pull). + * PD7 - GPIOD_USELESS7 (input pull-up). + * PD8 - GPIOD_USART3_TX (alternate 8). + * PD9 - GPIOD_USART3_RX (alternate 8). + * PD10 - GPIOD_USELESS10 (input pull-up). + * PD11 - GPIOD_USART3_CTS (alternate 8). + * PD12 - GPIOD_USART3_RTS (alternate 8). + * PD13 - GPIOD_USB_HS_FAULT (input floating). + * PD14 - GPIOD_USELESS14 (input pull-up). + * PD15 - GPIOD_USELESS15 (input pull-up). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_USELESS0) | \ + PIN_MODE_INPUT(GPIOD_USELESS1) | \ + PIN_MODE_OUTPUT(GPIOD_SPI3_CS) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_RST) | \ + PIN_MODE_INPUT(GPIOD_USELESS4) | \ + PIN_MODE_INPUT(GPIOD_USELESS5) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_CS) | \ + PIN_MODE_INPUT(GPIOD_USELESS7) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_INPUT(GPIOD_USELESS10) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_CTS) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RTS) | \ + PIN_MODE_INPUT(GPIOD_USB_HS_FAULT) | \ + PIN_MODE_INPUT(GPIOD_USELESS14) | \ + PIN_MODE_INPUT(GPIOD_USELESS15)) +#define VAL_GPIOD_OTYPER PIN_OTYPE_OPENDRAIN(GPIOD_SPI3_CS) +#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(GPIOD_USELESS0) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS1) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS4) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS5) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS7) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS10) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS14) | \ + PIN_PUDR_PULLUP(GPIOD_USELESS15)) +#define VAL_GPIOD_ODR 0xFFFFFFFF +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7) | \ + PIN_AFIO_AF(GPIOD_USART3_RX, 7) | \ + PIN_AFIO_AF(GPIOD_USART3_CTS, 7) | \ + PIN_AFIO_AF(GPIOD_USART3_RTS, 7)) + +/* + * Port E setup. + * + * PE0 - GPIOE_0 (input pull-up). + * PE1 - GPIOE_1 (input pull-up). + * PE2 - GPIOE_TEMP_ALERT (input floating). + * PE3 - GPIOE_USB_HS_VBUSON (output push-pull). + * PE4 - GPIOE_4 (input pull-up). + * PE5 - GPIOE_5 (input pull-up). + * PE6 - GPIOE_6 (input pull-up). + * PE7 - GPIOE_7 (input pull-up). + * PE8 - GPIOE_8 (input pull-up). + * PE9 - GPIOE_9 (input pull-up). + * PE10 - GPIOE_10 (input pull-up). + * PE11 - GPIOE_11 (input pull-up). + * PE12 - GPIOE_12 (input pull-up). + * PE13 - GPIOE_13 (input pull-up). + * PE14 - GPIOE_14 (input pull-up). + * PE15 - GPIOE_15 (input pull-up). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_0) | \ + PIN_MODE_INPUT(GPIOE_1) | \ + PIN_MODE_INPUT(GPIOE_TEMP_ALERT) | \ + PIN_MODE_OUTPUT(GPIOE_USB_HS_VBUSON) | \ + PIN_MODE_INPUT(GPIOE_4) | \ + PIN_MODE_INPUT(GPIOE_5) | \ + PIN_MODE_INPUT(GPIOE_6) | \ + PIN_MODE_INPUT(GPIOE_7) | \ + PIN_MODE_INPUT(GPIOE_8) | \ + PIN_MODE_INPUT(GPIOE_9) | \ + PIN_MODE_INPUT(GPIOE_10) | \ + PIN_MODE_INPUT(GPIOE_11) | \ + PIN_MODE_INPUT(GPIOE_12) | \ + PIN_MODE_INPUT(GPIOE_13) | \ + PIN_MODE_INPUT(GPIOE_14) | \ + PIN_MODE_INPUT(GPIOE_15)) +#define VAL_GPIOE_OTYPER 0x00000000 +#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLUP(GPIOE_0) | \ + PIN_PUDR_PULLUP(GPIOE_1) | \ + PIN_PUDR_PULLUP(GPIOE_4) | \ + PIN_PUDR_PULLUP(GPIOE_5) | \ + PIN_PUDR_PULLUP(GPIOE_6) | \ + PIN_PUDR_PULLUP(GPIOE_7) | \ + PIN_PUDR_PULLUP(GPIOE_8) | \ + PIN_PUDR_PULLUP(GPIOE_9) | \ + PIN_PUDR_PULLUP(GPIOE_10) | \ + PIN_PUDR_PULLUP(GPIOE_11) | \ + PIN_PUDR_PULLUP(GPIOE_12) | \ + PIN_PUDR_PULLUP(GPIOE_13) | \ + PIN_PUDR_PULLUP(GPIOE_14) | \ + PIN_PUDR_PULLUP(GPIOE_15)) +#define VAL_GPIOE_ODR 0xFFFFFFF7 +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 + +/* + * Port F setup. + * + * PF0 - GPIOF_0 (input pull-up). + * PF1 - GPIOF_1 (input pull-up). + * PF2 - GPIOF_2 (input pull-up). + * PF3 - GPIOF_3 (input pull-up). + * PF4 - GPIOF_4 (input pull-up). + * PF5 - GPIOF_5 (input pull-up). + * PF6 - GPIOF_STAT1 (output push-pull). + * PF7 - GPIOF_STAT2 (output push-pull). + * PF8 - GPIOF_STAT3 (output push-pull). + * PF9 - GPIOF_CAM_PWR (output push-pull). + * PF10 - GPIOF_10 (input pull-up). + * PF11 - GPIOF_CAM_RS (output push-pull). + * PF12 - GPIOF_12 (input pull-up). + * PF13 - GPIOF_13 (input pull-up). + * PF14 - GPIOF_14 (input pull-up). + * PF15 - GPIOF_15 (input pull-up). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_0) | \ + PIN_MODE_INPUT(GPIOF_1) | \ + PIN_MODE_INPUT(GPIOF_2) | \ + PIN_MODE_INPUT(GPIOF_3) | \ + PIN_MODE_INPUT(GPIOF_4) | \ + PIN_MODE_INPUT(GPIOF_5) | \ + PIN_MODE_OUTPUT(GPIOF_STAT1) | \ + PIN_MODE_OUTPUT(GPIOF_STAT2) | \ + PIN_MODE_OUTPUT(GPIOF_STAT3) | \ + PIN_MODE_OUTPUT(GPIOF_CAM_PWR) | \ + PIN_MODE_INPUT(GPIOF_10) | \ + PIN_MODE_OUTPUT(GPIOF_CAM_RS) | \ + PIN_MODE_INPUT(GPIOF_12) | \ + PIN_MODE_INPUT(GPIOF_13) | \ + PIN_MODE_INPUT(GPIOF_14) | \ + PIN_MODE_INPUT(GPIOF_15)) +#define VAL_GPIOF_OTYPER 0x00000000 +#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(GPIOF_0) | \ + PIN_PUDR_PULLUP(GPIOF_1) | \ + PIN_PUDR_PULLUP(GPIOF_2) | \ + PIN_PUDR_PULLUP(GPIOF_3) | \ + PIN_PUDR_PULLUP(GPIOF_4) | \ + PIN_PUDR_PULLUP(GPIOF_5) | \ + PIN_PUDR_PULLUP(GPIOF_10) | \ + PIN_PUDR_PULLUP(GPIOF_12) | \ + PIN_PUDR_PULLUP(GPIOF_13) | \ + PIN_PUDR_PULLUP(GPIOF_14) | \ + PIN_PUDR_PULLUP(GPIOF_15)) +#define VAL_GPIOF_ODR 0xFFFFFC3F +#define VAL_GPIOF_AFRL 0x00000000 +#define VAL_GPIOF_AFRH 0x00000000 + +/* + * Port G setup. + * + * PG0 - GPIOG_0 (input pull-up). + * PG1 - GPIOG_1 (input pull-up). + * PG2 - GPIOG_2 (input pull-up). + * PG3 - GPIOG_3 (input pull-up). + * PG4 - GPIOG_4 (input pull-up). + * PG5 - GPIOG_5 (input pull-up). + * PG6 - GPIOG_RIGHT (input floating). + * PG7 - GPIOG_UP (input floating). + * PG8 - GPIOG_DOWN (input floating). + * PG9 - GPIOG_USART6_RX (alternate 8). + * PG10 - GPIOG_10 (input pull-up). + * PG11 - GPIOG_LEFT (input floating). + * PG12 - GPIOG_12 (input pull-up). + * PG13 - GPIOG_ETH_RMII_TXD0 (alternate 11). + * PG14 - GPIOG_ETH_RMII_TXD1 (alternate 11). + * PG15 - GPIOG_CENT (input pull-up). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_0) | \ + PIN_MODE_INPUT(GPIOG_1) | \ + PIN_MODE_INPUT(GPIOG_2) | \ + PIN_MODE_INPUT(GPIOG_3) | \ + PIN_MODE_INPUT(GPIOG_4) | \ + PIN_MODE_INPUT(GPIOG_5) | \ + PIN_MODE_INPUT(GPIOG_RIGHT) | \ + PIN_MODE_INPUT(GPIOG_UP) | \ + PIN_MODE_INPUT(GPIOG_DOWN) | \ + PIN_MODE_ALTERNATE(GPIOG_USART6_RX) | \ + PIN_MODE_INPUT(GPIOG_10) | \ + PIN_MODE_INPUT(GPIOG_LEFT) | \ + PIN_MODE_INPUT(GPIOG_12) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) | \ + PIN_MODE_INPUT(GPIOG_CENT)) +#define VAL_GPIOG_OTYPER 0x00000000 +#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOG_PUPDR (PIN_PUDR_PULLUP(GPIOG_0) | \ + PIN_PUDR_PULLUP(GPIOG_1) | \ + PIN_PUDR_PULLUP(GPIOG_2) | \ + PIN_PUDR_PULLUP(GPIOG_3) | \ + PIN_PUDR_PULLUP(GPIOG_4) | \ + PIN_PUDR_PULLUP(GPIOG_5) | \ + PIN_PUDR_PULLUP(GPIOG_10) | \ + PIN_PUDR_PULLUP(GPIOG_12)) +#define VAL_GPIOG_ODR 0xFFFFFFFF +#define VAL_GPIOG_AFRL 0x00000000 +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_USART6_RX, 8) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \ + PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11)) + +/* + * Port H setup. + * All input with pull-up except: + * PH0 - GPIOH_OSC_IN (input floating). + * PH1 - GPIOH_OSC_OUT (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER 0x00000000 +#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOH_ODR 0xFFFFFFFF +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 + +/* + * Port I setup. + * All input with pull-up. + */ +#define VAL_GPIOI_MODER 0x00000000 +#define VAL_GPIOI_OTYPER 0x00000000 +#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOI_PUPDR (PIN_PUDR_PULLUP(0) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOI_ODR 0xFFFFFFFF +#define VAL_GPIOI_AFRL 0x00000000 +#define VAL_GPIOI_AFRH 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_P407/board.mk b/boards/OLIMEX_STM32_P407/board.mk new file mode 100644 index 000000000..b1e5aafe2 --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P407/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P407 diff --git a/boards/RAISONANCE_REVA_STM8S/board.c b/boards/RAISONANCE_REVA_STM8S/board.c new file mode 100644 index 000000000..33e1fa1e9 --- /dev/null +++ b/boards/RAISONANCE_REVA_STM8S/board.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +ROMCONST PALConfig pal_default_config = +{ + { + {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2}, + {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2}, + {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2}, + {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2}, + {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2}, + {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2}, + {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2}, + } +}; +#endif + +/* + * TIM 2 clock after the prescaler. + */ +#define TIM2_CLOCK (SYSCLK / 16) +#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1) + +/* + * TIM2 interrupt handler. + */ +CH_IRQ_HANDLER(13) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + TIM2->SR1 = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * TIM2 initialization as system tick. + */ + CLK->PCKENR1 |= CLK_PCKENR1_TIM2; + TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/ + TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8); + TIM2->ARRL = (uint8_t)(TIM2_ARR); + TIM2->CNTRH = 0; + TIM2->CNTRL = 0; + TIM2->SR1 = 0; + TIM2->IER = TIM2_IER_UIE; + TIM2->CR1 = TIM2_CR1_CEN; +} diff --git a/boards/RAISONANCE_REVA_STM8S/board.h b/boards/RAISONANCE_REVA_STM8S/board.h new file mode 100644 index 000000000..d61e50513 --- /dev/null +++ b/boards/RAISONANCE_REVA_STM8S/board.h @@ -0,0 +1,184 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Raisonance REva V3 + STM8S208RB daughter board. + */ + +/* + * Board identifiers. + */ +#define BOARD_REVA_V3_STM8S208RB +#define BOARD_NAME "Raisonance REva V3 + STM8S208RB" + +/* + * Board frequencies. + */ +#define HSECLK 0 + +/* + * MCU model used on the board. + */ +#define STM8S208 + +/* + * Pin definitions. + */ +#define PA_OSCIN 1 +#define PA_J2_25 2 /* It is also OSCOUT. */ +#define PA_J2_27 3 +#define PA_RX 4 +#define PA_TX 5 + +#define PB_LED(n) (n) +#define PB_LCD_D0 0 +#define PB_LCD_D1 1 +#define PB_LCD_CSB 2 +#define PB_LCD_RESB 3 + +#define PC_ADC_ETR 0 +#define PC_J2_51 1 +#define PC_J2_53 2 +#define PC_J2_55 3 +#define PC_J2_57 4 +#define PC_SCK 5 +#define PC_MOSI 6 +#define PC_MISO 7 + +#define PD_J2_69 0 +#define PD_J2_21 1 +#define PD_J2_67 2 +#define PD_J2_65 3 +#define PD_PWM 4 +#define PD_J2_63 5 +#define PD_J2_61 6 +#define PD_J2_59 7 + +#define PE_P2_49 0 +#define PE_SCL 1 +#define PE_SDA 2 +#define PE_P2_47 3 +#define PE_P2_45 4 +#define PE_P2_43 5 +#define PE_P2_41 6 +#define PE_P2_39 7 + +#define PF_J2_37 0 +#define PF_J2_35 1 +#define PF_J2_33 2 +#define PF_J2_31 3 +#define PF_ANA_IN1 4 +#define PF_ANA_IN2 5 +#define PF_ANA_TEMP 6 +#define PF_ANA_POT 7 + +#define PG_CAN_TX 0 +#define PG_CAN_RX 1 +#define PG_BT5 2 +#define PG_BT6 3 +#define PG_SW4 4 +#define PG_SW3 5 +#define PG_SW2 6 +#define PG_SW1 7 + +#define PI_J2_71 0 + +/* + * Port A initial setup. + */ +#define VAL_GPIOAODR (1 << PA_TX) /* PA_TX initially to 1. */ +#define VAL_GPIOADDR (1 << PA_TX) /* PA_TX output, others inputs. */ +#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */ +#define VAL_GPIOACR2 0 + +/* + * Port B initial setup. + */ +#define VAL_GPIOBODR 0xFF /* Initially all set to high. */ +#define VAL_GPIOBDDR 0xFF /* All outputs. */ +#define VAL_GPIOBCR1 0xFF /* All push-pull. */ +#define VAL_GPIOBCR2 0 + +/* + * Port C initial setup. + */ +#define VAL_GPIOCODR 0 +#define VAL_GPIOCDDR 0 /* All inputs. */ +#define VAL_GPIOCCR1 0xFF /* All pull-up. */ +#define VAL_GPIOCCR2 0 + +/* + * Port D initial setup. + */ +#define VAL_GPIODODR 0 +#define VAL_GPIODDDR 0 /* All inputs. */ +#define VAL_GPIODCR1 0xFF /* All pull-up. */ +#define VAL_GPIODCR2 0 + +/* + * Port E initial setup. + */ +#define VAL_GPIOEODR 0 +#define VAL_GPIOEDDR 0 /* All inputs. */ +#define VAL_GPIOECR1 0xFF /* All pull-up. */ +#define VAL_GPIOECR2 0 + +/* + * Port F initial setup. + */ +#define VAL_GPIOFODR 0 +#define VAL_GPIOFDDR 0 /* All inputs. */ +#define VAL_GPIOFCR1 0xFF /* All pull-up. */ +#define VAL_GPIOFCR2 0 + +/* + * Port G initial setup. + */ +#define VAL_GPIOGODR (1 << PG_CAN_TX)/* CAN_TX initially to 1. */ +#define VAL_GPIOGDDR (1 << PG_CAN_TX)/* CAN_TX output, others inputs. */ +#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */ +#define VAL_GPIOGCR2 0 + +/* + * Port H initial setup (dummy, not present). + */ +#define VAL_GPIOHODR 0 +#define VAL_GPIOHDDR 0 /* All inputs. */ +#define VAL_GPIOHCR1 0xFF /* All pull-up. */ +#define VAL_GPIOHCR2 0 + +/* + * Port I initial setup. + */ +#define VAL_GPIOIODR 0 +#define VAL_GPIOIDDR 0 /* All inputs. */ +#define VAL_GPIOICR1 0xFF /* All pull-up. */ +#define VAL_GPIOICR2 0 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/STUDIEL_AT91SAM7A3_EK/board.c b/boards/STUDIEL_AT91SAM7A3_EK/board.c new file mode 100644 index 000000000..2a3dc015b --- /dev/null +++ b/boards/STUDIEL_AT91SAM7A3_EK/board.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif +}; +#endif + +/* + * SYS IRQ handling here. + */ +static CH_IRQ_HANDLER(SYSIrqHandler) { + + CH_IRQ_PROLOGUE(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + } + +#if USE_SAM7_DBGU_UART + if (AT91C_BASE_DBGU->DBGU_CSR & + (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) { + sd_lld_serve_interrupt(&SDDBG); + } +#endif + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + at91sam7_clock_init(); +} + +#if HAL_USE_MMC_SPI +/* Board-related functions related to the MMC_SPI driver.*/ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(IOPORT2, PIOB_MMC_CP); +} + +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + return palReadPad(IOPORT2, PIOB_MMC_WP); +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * RTS/CTS pins enabled for USART0 only. + */ + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; +} diff --git a/boards/STUDIEL_AT91SAM7A3_EK/board.h b/boards/STUDIEL_AT91SAM7A3_EK/board.h new file mode 100644 index 000000000..1bb61e40c --- /dev/null +++ b/boards/STUDIEL_AT91SAM7A3_EK/board.h @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Studiel AT91SAM7A3-EK board. + */ + +/* + * Board identifier. + */ +#define BOARD_STUDIEL_AT91SAM7A3_EK +#define BOARD_NAME "Studiel AT91SAM7A3-EK eval. board" + +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7A3_PLATFORM) +#define SAM7_PLATFORM SAM7A3 +#endif + +#include "at91sam7.h" + +#define CLK 18432000 +#define MCK 48054857 + +/* + * I/O definitions. + */ +#define PIOA_RXD0 2 +#define PIOA_RXD0_MASK (1 << PIOA_RXD0) +#define PIOA_TXD0 3 +#define PIOA_TXD0_MASK (1 << PIOA_TXD0) +#define PIOA_LED1 20 +#define PIOA_LED1_MASK (1 << PIOA_LED1) +#define PIOA_LED2 21 +#define PIOA_LED2_MASK (1 << PIOA_LED2) +#define PIOA_LED3 24 +#define PIOA_LED3_MASK (1 << PIOA_LED3) +#define PIOA_LED4 25 +#define PIOA_LED4_MASK (1 << PIOA_LED4) +// mmc-spi +#define PIOA_SPI0_NSS 14 +#define PIOA_SPI0_NSS_MASK (1 << PIOA_SPI0_NSS) +#define PIOA_SPI0_MISO 15 +#define PIOA_SPI0_MISO_MASK (1 << PIOA_SPI0_MISO) +#define PIOA_SPI0_MOSI 16 +#define PIOA_SPI0_MOSI_MASK (1 << PIOA_SPI0_MOSI) +#define PIOA_SPI0_CLK 17 +#define PIOA_SPI0_CLK_MASK (1 << PIOA_SPI0_CLK) + +/* + * Initial I/O setup. + */ +/* Output data. */ +#define VAL_PIOA_ODSR 0x00000000 +/* Direction. */ +#define VAL_PIOA_OSR 0x00000000 | PIOA_LED1_MASK | PIOA_LED2_MASK | \ + PIOA_LED3_MASK | PIOA_LED4_MASK +/* Pull-up. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC560BC/board.c b/boards/ST_EVB_SPC560BC/board.c new file mode 100644 index 000000000..5c067606b --- /dev/null +++ b/boards/ST_EVB_SPC560BC/board.c @@ -0,0 +1,67 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/* Initialization array for the PSMI registers.*/ +static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ + spc_siu_init, + spc_padsels_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC560BC/board.h b/boards/ST_EVB_SPC560BC/board.h new file mode 100644 index 000000000..70e3ee548 --- /dev/null +++ b/boards/ST_EVB_SPC560BC/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC560B/Cxx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC560BC +#define BOARD_NAME "Generic SPC560B/Cxx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 8000000 +#endif + +/* + * I/O definitions. + */ +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 + +#define PE_BUTTON1 0 +#define PE_BUTTON2 1 +#define PE_BUTTON3 2 +#define PE_BUTTON4 3 + +#define PE_LED1 4 +#define PE_LED2 5 +#define PE_LED3 6 +#define PE_LED4 7 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC560BC/board.mk b/boards/ST_EVB_SPC560BC/board.mk new file mode 100644 index 000000000..92aadc984 --- /dev/null +++ b/boards/ST_EVB_SPC560BC/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560BC/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560BC diff --git a/boards/ST_EVB_SPC560D/board.c b/boards/ST_EVB_SPC560D/board.c new file mode 100644 index 000000000..fc5f2c6bc --- /dev/null +++ b/boards/ST_EVB_SPC560D/board.c @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/* Initialization array for the PSMI registers.*/ +static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ + spc_siu_init, + spc_padsels_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC560D/board.h b/boards/ST_EVB_SPC560D/board.h new file mode 100644 index 000000000..bca6f7245 --- /dev/null +++ b/boards/ST_EVB_SPC560D/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC560Dxx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC560D +#define BOARD_NAME "Generic SPC560Dxx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 8000000 +#endif + +/* + * I/O definitions. + */ +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 + +#define PE_BUTTON1 0 +#define PE_BUTTON2 1 +#define PE_BUTTON3 2 +#define PE_BUTTON4 3 + +#define PE_LED1 4 +#define PE_LED2 5 +#define PE_LED3 6 +#define PE_LED4 7 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC560D/board.mk b/boards/ST_EVB_SPC560D/board.mk new file mode 100644 index 000000000..8a18b37df --- /dev/null +++ b/boards/ST_EVB_SPC560D/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560D/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560D diff --git a/boards/ST_EVB_SPC560P/board.c b/boards/ST_EVB_SPC560P/board.c new file mode 100644 index 000000000..5410436bb --- /dev/null +++ b/boards/ST_EVB_SPC560P/board.c @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/* Initialization array for the PSMI registers.*/ +static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ + spc_siu_init, + spc_padsels_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC560P/board.h b/boards/ST_EVB_SPC560P/board.h new file mode 100644 index 000000000..a02225c13 --- /dev/null +++ b/boards/ST_EVB_SPC560P/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC560Pxx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC560P +#define BOARD_NAME "Generic SPC560Pxx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 40000000 +#endif + +/* + * I/O definitions. + */ +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 + +#define PD_BUTTON1 0 +#define PD_BUTTON2 1 +#define PD_BUTTON3 2 +#define PD_BUTTON4 3 + +#define PD_LED1 4 +#define PD_LED2 5 +#define PD_LED3 6 +#define PD_LED4 7 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC560P/board.mk b/boards/ST_EVB_SPC560P/board.mk new file mode 100644 index 000000000..01d5f533b --- /dev/null +++ b/boards/ST_EVB_SPC560P/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560P/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560P diff --git a/boards/ST_EVB_SPC563M/board.c b/boards/ST_EVB_SPC563M/board.c new file mode 100644 index 000000000..523d1d7e5 --- /dev/null +++ b/boards/ST_EVB_SPC563M/board.c @@ -0,0 +1,59 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT5, P5_ESCI_A_TX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT5, P5_ESCI_A_RX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT11, P11_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + spc_siu_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC563M/board.h b/boards/ST_EVB_SPC563M/board.h new file mode 100644 index 000000000..3a258f2f9 --- /dev/null +++ b/boards/ST_EVB_SPC563M/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC563Mxx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC563M +#define BOARD_NAME "Generic SPC563Mxx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 8000000 +#endif + +/* + * I/O definitions. + */ +#define P5_ESCI_A_TX 9 +#define P5_ESCI_A_RX 10 + +#define P11_BUTTON1 3 +#define P11_BUTTON2 5 +#define P11_BUTTON3 7 +#define P11_BUTTON4 9 + +#define P11_LED1 12 +#define P11_LED2 13 +#define P11_LED3 14 +#define P11_LED4 15 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC563M/board.mk b/boards/ST_EVB_SPC563M/board.mk new file mode 100644 index 000000000..63b4368ec --- /dev/null +++ b/boards/ST_EVB_SPC563M/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC563M/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC563M diff --git a/boards/ST_EVB_SPC564A/board.c b/boards/ST_EVB_SPC564A/board.c new file mode 100644 index 000000000..523d1d7e5 --- /dev/null +++ b/boards/ST_EVB_SPC564A/board.c @@ -0,0 +1,59 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT5, P5_ESCI_A_TX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT5, P5_ESCI_A_RX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT11, P11_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT11, P11_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT11, P11_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + spc_siu_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC564A/board.h b/boards/ST_EVB_SPC564A/board.h new file mode 100644 index 000000000..67084dd79 --- /dev/null +++ b/boards/ST_EVB_SPC564A/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC564Axx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC564A +#define BOARD_NAME "Generic SPC564Axx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 8000000 +#endif + +/* + * I/O definitions. + */ +#define P5_ESCI_A_TX 9 +#define P5_ESCI_A_RX 10 + +#define P11_BUTTON1 3 +#define P11_BUTTON2 5 +#define P11_BUTTON3 7 +#define P11_BUTTON4 9 + +#define P11_LED1 12 +#define P11_LED2 13 +#define P11_LED3 14 +#define P11_LED4 15 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC564A/board.mk b/boards/ST_EVB_SPC564A/board.mk new file mode 100644 index 000000000..1dc4a1117 --- /dev/null +++ b/boards/ST_EVB_SPC564A/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC564A/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC564A diff --git a/boards/ST_EVB_SPC56EL/board.c b/boards/ST_EVB_SPC56EL/board.c new file mode 100644 index 000000000..7373f595d --- /dev/null +++ b/boards/ST_EVB_SPC56EL/board.c @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/* Initialization array for the PSMI registers.*/ +static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = { + PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ + spc_siu_init, + spc_padsels_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_early_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_EVB_SPC56EL/board.h b/boards/ST_EVB_SPC56EL/board.h new file mode 100644 index 000000000..5c64e99bb --- /dev/null +++ b/boards/ST_EVB_SPC56EL/board.h @@ -0,0 +1,68 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC560Pxx proto board. + */ + +/* + * Board identifiers. + */ +#define BOARD_GENERIC_SPC56EL +#define BOARD_NAME "Generic SPC56ELxx" + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 40000000 +#endif + +/* + * I/O definitions. + */ +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 + +#define PD_BUTTON1 0 +#define PD_BUTTON2 1 +#define PD_BUTTON3 2 +#define PD_BUTTON4 3 + +#define PD_LED1 4 +#define PD_LED2 5 +#define PD_LED3 6 +#define PD_LED4 7 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_EVB_SPC56EL/board.mk b/boards/ST_EVB_SPC56EL/board.mk new file mode 100644 index 000000000..8e5c03bce --- /dev/null +++ b/boards/ST_EVB_SPC56EL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC56EL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC56EL diff --git a/boards/ST_STM3210C_EVAL/board.c b/boards/ST_STM3210C_EVAL/board.c new file mode 100644 index 000000000..030d2f9ae --- /dev/null +++ b/boards/ST_STM3210C_EVAL/board.c @@ -0,0 +1,55 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * Remap USART2 to the PD5/PD6 pins. + */ + AFIO->MAPR |= AFIO_MAPR_USART2_REMAP; +} diff --git a/boards/ST_STM3210C_EVAL/board.h b/boards/ST_STM3210C_EVAL/board.h new file mode 100644 index 000000000..2193179b8 --- /dev/null +++ b/boards/ST_STM3210C_EVAL/board.h @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the STMicroelectronics STM3210C-EVAL evaluation board. + */ + +#define GPIOD_LED1 7 +#define GPIOD_LED2 13 +#define GPIOD_LED3 3 +#define GPIOD_LED4 4 + +/* + * Board identifier. + */ +#define BOARD_ST_STM3210C_EVAL +#define BOARD_NAME "ST STM3210C-EVAL" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 25000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_CL + +/* + * IO pins assignments. + * *********************TO BE COMPLETED********************* + */ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input except: + */ +#define VAL_GPIOACRL 0x44444444 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x44444444 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input except: + */ +#define VAL_GPIOBCRL 0x44444444 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0x44444444 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input except: + */ +#define VAL_GPIOCCRL 0x44444444 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x44444444 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input except: + * PD5 - USART2TX (remapped) AF PP Output + * PD6 - USART2RX (remapped) Digital Input + * PD7 - LED (LD1) PP Output + */ +#define VAL_GPIODCRL 0x34B33444 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x44344444 /* PD15...PD8 */ +#define VAL_GPIODODR 0x0000DF67 + +/* + * Port E setup. + * Everything input except: + */ +#define VAL_GPIOECRL 0x44444444 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x44344444 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM3210C_EVAL/board.mk b/boards/ST_STM3210C_EVAL/board.mk new file mode 100644 index 000000000..eaa17162b --- /dev/null +++ b/boards/ST_STM3210C_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM3210C_EVAL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM3210C_EVAL diff --git a/boards/ST_STM3210E_EVAL/board.c b/boards/ST_STM3210E_EVAL/board.c new file mode 100644 index 000000000..95f58e3b0 --- /dev/null +++ b/boards/ST_STM3210E_EVAL/board.c @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, + {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, + {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC +/* Board-related functions related to the SDC driver.*/ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadPad(GPIOF, GPIOF_SD_DETECT); +} + +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return FALSE; +} +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/boards/ST_STM3210E_EVAL/board.h b/boards/ST_STM3210E_EVAL/board.h new file mode 100644 index 000000000..739b3e089 --- /dev/null +++ b/boards/ST_STM3210E_EVAL/board.h @@ -0,0 +1,251 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the STMicroelectronics STM3210E-EVAL evaluation board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM3210E_EVAL +#define BOARD_NAME "ST STM3210E-EVAL" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + * Note: Older board revisions should define STM32F10X_HD instead, please + * verify the STM32 model mounted on your board. The change also + * affects your linker script. + */ +#define STM32F10X_XL + +/* + * IO pins assignments. + */ +#define GPIOA_WAKEUP_BUTTON 0 + +#define GPIOB_SC_3V_5V 0 +#define GPIOB_SPI1_CS 2 +#define GPIOB_TEMP_INT 5 +#define GPIOB_USB_DISC 14 + +#define GPIOC_SC_CMDVCC 6 +#define GPIOC_SC_OFF 7 +#define GPIOC_TAMPER_BUTTON 13 + +#define GPIOD_JOY_DOWN 3 + +#define GPIOF_LED1 6 +#define GPIOF_LED2 7 +#define GPIOF_LED3 8 +#define GPIOF_LED4 9 +#define GPIOF_SD_DETECT 11 + +#define GPIOG_JOY_SEL 7 +#define GPIOG_USER_BUTTON 8 +#define GPIOG_JOY_RIGHT 13 +#define GPIOG_JOY_LEFT 14 +#define GPIOG_JOY_UP 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_ANALOG(n) (0 << (((n) & 7) * 4)) +#define PIN_OUTPUT_PP_10(n) (1 << (((n) & 7) * 4)) +#define PIN_OUTPUT_PP_2(n) (2 << (((n) & 7) * 4)) +#define PIN_OUTPUT_PP_50(n) (3 << (((n) & 7) * 4)) +#define PIN_INPUT(n) (4 << (((n) & 7) * 4)) +#define PIN_OUTPUT_OD_10(n) (5 << (((n) & 7) * 4)) +#define PIN_OUTPUT_OD_2(n) (6 << (((n) & 7) * 4)) +#define PIN_OUTPUT_OD_50(n) (7 << (((n) & 7) * 4)) +#define PIN_INPUT_PUD(n) (8 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_PP_10(n) (9 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_PP_2(n) (10 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_PP_50(n) (11 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_OD_10(n) (13 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_OD_2(n) (14 << (((n) & 7) * 4)) +#define PIN_ALTERNATE_OD_50(n) (15 << (((n) & 7) * 4)) +#define PIN_UNDEFINED(n) PIN_INPUT_PUD(n) + +/* + * Port A setup. + */ +#define VAL_GPIOACRL (PIN_INPUT(0) | /* Wakeup Button. */ \ + PIN_OUTPUT_PP_50(1) | /* USART2_RTS. */ \ + PIN_ALTERNATE_PP_50(2) | /* USART2_TX. */ \ + PIN_INPUT(3) | /* USART2_RX. */ \ + PIN_UNDEFINED(4) | \ + PIN_ALTERNATE_PP_50(5) | /* SPI1_SCK. */ \ + PIN_INPUT(6) | /* SPI1_MISO. */ \ + PIN_ALTERNATE_PP_50(7)) /* SPI1_MOSI. */ +#define VAL_GPIOACRH (PIN_ALTERNATE_PP_50(8) | /* MCO. */ \ + PIN_ALTERNATE_PP_50(9) | /* USART1_TX. */ \ + PIN_INPUT(10) | /* USART1_RX. */ \ + PIN_INPUT_PUD(11) | /* USB_DM. */ \ + PIN_INPUT_PUD(12) | /* USB_DP. */ \ + PIN_INPUT(13) | /* TMS. */ \ + PIN_INPUT(14) | /* TCK. */ \ + PIN_INPUT(15)) /* TDI. */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + */ +#define VAL_GPIOBCRL (PIN_OUTPUT_PP_50(0) | /* SmartCard_3/5V. */ \ + PIN_INPUT_PUD(1) | /* Unconnected. */ \ + PIN_OUTPUT_PP_50(2) | /* SPI1_CS. */ \ + PIN_INPUT(3) | /* TDO. */ \ + PIN_INPUT(4) | /* TRST. */ \ + PIN_INPUT_PUD(5) | /* Temp.Sensor INT. */ \ + PIN_ALTERNATE_OD_50(6) | /* I2C1_SCK. */ \ + PIN_ALTERNATE_OD_50(7)) /* I2C1_SDA. */ +#define VAL_GPIOBCRH (PIN_INPUT(8) | /* CAN_RX. */ \ + PIN_ALTERNATE_PP_50(9) | /* CAN_TX. */ \ + PIN_ALTERNATE_OD_50(10)| /* SmartCard IO. */ \ + PIN_OUTPUT_PP_50(11) | /* SmartCard RST. */ \ + PIN_ALTERNATE_PP_50(12)| /* SmartCard CLK. */ \ + PIN_UNDEFINED(13) | \ + PIN_OUTPUT_PP_50(14) | /* USB disconnect. */ \ + PIN_UNDEFINED(15)) +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + */ +#define VAL_GPIOCCRL (PIN_UNDEFINED(0) | \ + PIN_UNDEFINED(1) | \ + PIN_UNDEFINED(2) | \ + PIN_UNDEFINED(3) | \ + PIN_ANALOG(4) | /* Potentiometer. */ \ + PIN_UNDEFINED(5) | \ + PIN_OUTPUT_PP_50(6) | /* SmartCard CMDVCC. */ \ + PIN_INPUT(7)) /* SmartCard OFF. */ +#define VAL_GPIOCCRH (PIN_ALTERNATE_PP_50(8) | /* SDIO D0. */ \ + PIN_ALTERNATE_PP_50(9) | /* SDIO D1. */ \ + PIN_ALTERNATE_PP_50(10)| /* SDIO D2. */ \ + PIN_ALTERNATE_PP_50(11)| /* SDIO D3. */ \ + PIN_ALTERNATE_PP_50(12)| /* SDIO CLK. */ \ + PIN_INPUT(13) | /* Tamper Button. */ \ + PIN_INPUT(14) | /* OSC IN. */ \ + PIN_INPUT(15)) /* OSC OUT. */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup + */ +#define VAL_GPIODCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_D2. */ \ + PIN_ALTERNATE_PP_50(1) | /* FSMC_D3. */ \ + PIN_ALTERNATE_PP_50(2) | /* SDIO CMD. */ \ + PIN_INPUT(3) | /* Joy Down. */ \ + PIN_ALTERNATE_PP_50(4) | /* FSMC_NOE. */ \ + PIN_ALTERNATE_PP_50(5) | /* FSMC_NWE. */ \ + PIN_INPUT(6) | /* FSMC_NWAIT. */ \ + PIN_ALTERNATE_PP_50(7)) /* FSMC_NCE2. */ +#define VAL_GPIODCRH (PIN_ALTERNATE_PP_50(8) | /* FSMC_D13. */ \ + PIN_ALTERNATE_PP_50(9) | /* FSMC_D14. */ \ + PIN_ALTERNATE_PP_50(10)| /* FSMC_D15. */ \ + PIN_ALTERNATE_PP_50(11)| /* FSMC_A16. */ \ + PIN_ALTERNATE_PP_50(12)| /* FSMC_A17. */ \ + PIN_ALTERNATE_PP_50(13)| /* FSMC_A18. */ \ + PIN_ALTERNATE_PP_50(14)| /* FSMC_D0. */ \ + PIN_ALTERNATE_PP_50(15)) /* FSMC_D1. */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + */ +#define VAL_GPIOECRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_NBL0. */ \ + PIN_ALTERNATE_PP_50(1) | /* FSMC_NBL1. */ \ + PIN_ALTERNATE_PP_50(2) | /* FSMC_A23. */ \ + PIN_ALTERNATE_PP_50(3) | /* FSMC_A19. */ \ + PIN_ALTERNATE_PP_50(4) | /* FSMC_A20. */ \ + PIN_ALTERNATE_PP_50(5) | /* FSMC_A21. */ \ + PIN_ALTERNATE_PP_50(6) | /* FSMC_A22. */ \ + PIN_ALTERNATE_PP_50(7)) /* FSMC_D4. */ +#define VAL_GPIOECRH (PIN_ALTERNATE_PP_50(8) | /* FSMC_D5. */ \ + PIN_ALTERNATE_PP_50(9) | /* FSMC_D6. */ \ + PIN_ALTERNATE_PP_50(10)| /* FSMC_D7. */ \ + PIN_ALTERNATE_PP_50(11)| /* FSMC_D8. */ \ + PIN_ALTERNATE_PP_50(12)| /* FSMC_D9. */ \ + PIN_ALTERNATE_PP_50(13)| /* FSMC_D10. */ \ + PIN_ALTERNATE_PP_50(14)| /* FSMC_D11. */ \ + PIN_ALTERNATE_PP_50(15)) /* FSMC_D12. */ +#define VAL_GPIOEODR 0xFFFFFFFF + +/* + * Port F setup. + */ +#define VAL_GPIOFCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_A0. */ \ + PIN_ALTERNATE_PP_50(1) | /* FSMC_A1. */ \ + PIN_ALTERNATE_PP_50(2) | /* FSMC_A2. */ \ + PIN_ALTERNATE_PP_50(3) | /* FSMC_A3. */ \ + PIN_ALTERNATE_PP_50(4) | /* FSMC_A4. */ \ + PIN_ALTERNATE_PP_50(5) | /* FSMC_A5. */ \ + PIN_OUTPUT_PP_50(6) | /* LED1. */ \ + PIN_OUTPUT_PP_50(7)) /* LED2. */ +#define VAL_GPIOFCRH (PIN_OUTPUT_PP_50(8) | /* LED3. */ \ + PIN_OUTPUT_PP_50(9) | /* LED4. */ \ + PIN_UNDEFINED(10) | \ + PIN_INPUT_PUD(11) | /* SDCard detect. */ \ + PIN_ALTERNATE_PP_50(12)| /* FSMC_A6. */ \ + PIN_ALTERNATE_PP_50(13)| /* FSMC_A7. */ \ + PIN_ALTERNATE_PP_50(14)| /* FSMC_A8. */ \ + PIN_ALTERNATE_PP_50(15)) /* FSMC_A9. */ +#define VAL_GPIOFODR 0xFFFFFC3F + +/* + * Port G setup. + */ +#define VAL_GPIOGCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_A10. */ \ + PIN_ALTERNATE_PP_50(1) | /* FSMC_A11. */ \ + PIN_ALTERNATE_PP_50(2) | /* FSMC_A12. */ \ + PIN_ALTERNATE_PP_50(3) | /* FSMC_A13. */ \ + PIN_ALTERNATE_PP_50(4) | /* FSMC_A14. */ \ + PIN_ALTERNATE_PP_50(5) | /* FSMC_A15. */ \ + PIN_INPUT(6) | /* FSMC_INT2. */ \ + PIN_INPUT(7)) /* Joy Select. */ +#define VAL_GPIOGCRH (PIN_INPUT(8) | /* User Button. */ \ + PIN_ALTERNATE_PP_50(9) | /* FSMC_NE2. */ \ + PIN_ALTERNATE_PP_50(10)| /* FSMC_NE3. */ \ + PIN_OUTPUT_PP_50(11) | /* Audio PDN. */ \ + PIN_ALTERNATE_PP_50(12)| /* FSMC_NE4. */ \ + PIN_INPUT(13) | /* Joy Right. */ \ + PIN_INPUT(14) | /* Joy Left. */ \ + PIN_INPUT(15)) /* Joy Up. */ +#define VAL_GPIOGODR 0xFFFFF7FF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM3210E_EVAL/board.mk b/boards/ST_STM3210E_EVAL/board.mk new file mode 100644 index 000000000..edd0baf21 --- /dev/null +++ b/boards/ST_STM3210E_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM3210E_EVAL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM3210E_EVAL diff --git a/boards/ST_STM3220G_EVAL/board.c b/boards/ST_STM3220G_EVAL/board.c new file mode 100644 index 000000000..c78a97b8d --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM3220G_EVAL/board.h b/boards/ST_STM3220G_EVAL/board.h new file mode 100644 index 000000000..07cfc5dea --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.h @@ -0,0 +1,226 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM3220G-EVAL board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM3220G_EVAL +#define BOARD_NAME "ST STM3220G-EVAL" + +/* + * Board frequencies. + * NOTE: The HSE crystal is not fitted by default on the board. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 25000000 + +/* + * MCU type as defined in the ST header file stm32f2xx.h. + */ +#define STM32F2XX + +/* + * IO pins assignments. + */ + +#define GPIOA_WAKEUP_BUTTON 0 + +#define GPIOB_ETHER_INT 14 +#define GPIOB_NAND_INT 15 + +#define GPIOC_TAMPER_BUTTON 0 +#define GPIOC_LED4 7 + +#define GPIOF_POT 9 + +#define GPIOG_LED1 6 +#define GPIOG_LED2 8 +#define GPIOG_USER_BUTTON 15 + +#define GPIOH_EXPANDER_INT 12 +#define GPIOH_SD_DETECT 13 + +#define GPIOI_LED3 9 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0 << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1 << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2 << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3 << ((n) * 2)) +#define PIN_OTYPE_PUSHPULL(n) (0 << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1 << (n)) +#define PIN_OSPEED_2M(n) (0 << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1 << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2 << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3 << ((n) * 2)) +#define PIN_PUDR_FLOATING(n) (0 << ((n) * 2)) +#define PIN_PUDR_PULLUP(n) (1 << ((n) * 2)) +#define PIN_PUDR_PULLDOWN(n) (2 << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * Port A setup. + * All input with pull-up except: + * PA8 - MCO 1 (alternate 0). + * PA13 - JTMS/SWDAT (alternate 0). + * PA14 - JTCK/SWCLK (alternate 0). + * PA15 - JTDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOA_OTYPER 0x00000000 +#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(13) | \ + PIN_PUDR_FLOATING(14) | \ + PIN_PUDR_FLOATING(15)) +#define VAL_GPIOA_ODR 0xFFFFFFFF +#define VAL_GPIOA_AFRL 0x00000000 +#define VAL_GPIOA_AFRH 0x00000000 + +/* + * Port B setup. + * All input with pull-up except: + * PB3 - JTDO (alternate 0). + * PB4 - JNTRST (alternate 0). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_ALTERNATE(4)) +#define VAL_GPIOB_OTYPER 0x00000000 +#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOB_PUPDR (~(PIN_PUDR_FLOATING(3) | \ + PIN_PUDR_FLOATING(4))) +#define VAL_GPIOB_ODR 0xFFFFFFFF +#define VAL_GPIOB_AFRL 0x00000000 +#define VAL_GPIOB_AFRH 0x00000000 + +/* + * Port C setup. + * All input with pull-up except: + * PC9 - MCO2 (alternate 0). + * PC10 - USART3_TX (alternate 7). + * PC11 - USART3_RX (alternate 7). + * PC14 - OSC32_INT (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11)) +#define VAL_GPIOC_OTYPER 0x00000000 +#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOC_PUPDR (~(PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_FLOATING(14) | \ + PIN_PUDR_FLOATING(15))) +#define VAL_GPIOC_ODR 0xFFFFFFFF +#define VAL_GPIOC_AFRL 0x00000000 +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(7, 10) | \ + PIN_AFIO_AF(7, 11)) + +/* + * Port D setup. + * All input with pull-up. + */ +#define VAL_GPIOD_MODER 0x00000000 +#define VAL_GPIOD_OTYPER 0x00000000 +#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOD_PUPDR 0xFFFFFFFF +#define VAL_GPIOD_ODR 0xFFFFFFFF +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH 0x00000000 + +/* + * Port E setup. + * All input with pull-up. + */ +#define VAL_GPIOE_MODER 0x00000000 +#define VAL_GPIOE_OTYPER 0x00000000 +#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOE_PUPDR 0xFFFFFFFF +#define VAL_GPIOE_ODR 0xFFFFFFFF +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 + +/* + * Port F setup. + * All input with pull-up. + */ +#define VAL_GPIOF_MODER 0x00000000 +#define VAL_GPIOF_OTYPER 0x00000000 +#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOF_PUPDR 0xFFFFFFFF +#define VAL_GPIOF_ODR 0xFFFFFFFF +#define VAL_GPIOF_AFRL 0x00000000 +#define VAL_GPIOF_AFRH 0x00000000 + +/* + * Port G setup. + * All input with pull-up. + */ +#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_LED1)) +#define VAL_GPIOG_OTYPER 0x00000000 +#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOG_PUPDR (~(PIN_PUDR_FLOATING(GPIOG_LED1))) +#define VAL_GPIOG_ODR 0xFFFFFFBF +#define VAL_GPIOG_AFRL 0x00000000 +#define VAL_GPIOG_AFRH 0x00000000 + +/* + * Port H setup. + * All input with pull-up. + */ +#define VAL_GPIOH_MODER 0x00000000 +#define VAL_GPIOH_OTYPER 0x00000000 +#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOH_PUPDR 0xFFFFFFFF +#define VAL_GPIOH_ODR 0xFFFFFFFF +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 + +/* + * Port I setup. + * All input with pull-up. + */ +#define VAL_GPIOI_MODER 0x00000000 +#define VAL_GPIOI_OTYPER 0x00000000 +#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOI_PUPDR 0xFFFFFFFF +#define VAL_GPIOI_ODR 0xFFFFFFFF +#define VAL_GPIOI_AFRL 0x00000000 +#define VAL_GPIOI_AFRH 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM3220G_EVAL/board.mk b/boards/ST_STM3220G_EVAL/board.mk new file mode 100644 index 000000000..3121594a6 --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM3220G_EVAL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM3220G_EVAL diff --git a/boards/ST_STM32373C_EVAL/board.c b/boards/ST_STM32373C_EVAL/board.c new file mode 100644 index 000000000..baafd6550 --- /dev/null +++ b/boards/ST_STM32373C_EVAL/board.c @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32373C_EVAL/board.h b/boards/ST_STM32373C_EVAL/board.h new file mode 100644 index 000000000..13676e7e6 --- /dev/null +++ b/boards/ST_STM32373C_EVAL/board.h @@ -0,0 +1,888 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32373C-EVAL board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32373C_EVAL +#define BOARD_NAME "STMicroelectronics STM32373C-EVAL" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#define STM32_LSEDRV (3 << 3) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + +/* + * MCU type as defined in the ST header. + */ +#define STM32F37X + +/* + * IO pins assignments. + */ +#define GPIOA_WKUP_BUTTON 0 +#define GPIOA_LDR_OUT 1 +#define GPIOA_KEY_BUTTON 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_COMP2_OUT 7 +#define GPIOA_I2C2_SMB 8 +#define GPIOA_I2C2_SCL 9 +#define GPIOA_I2C2_SDA 10 +#define GPIOA_USB_DM 11 +#define GPIOA_USB_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_JTDI 15 + +#define GPIOB_MIC_IN 0 +#define GPIOB_ADC_POT_IN 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_JTRST 4 +#define GPIOB_PIN5 5 +#define GPIOB_I2C1_SCL 6 +#define GPIOB_I2C1_SDA 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_LED1 0 +#define GPIOC_LED2 1 +#define GPIOC_LED3 2 +#define GPIOC_LED4 3 +#define GPIOC_PIN4 4 +#define GPIOC_USB_DISCONNECT 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_SPI3_SCK 10 +#define GPIOC_SPI3_MISO 11 +#define GPIOC_SPI3_MOSI 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_CAN_RX 0 +#define GPIOD_CAN_TX 1 +#define GPIOD_LCD_CS 2 +#define GPIOD_USART2_CTS 3 +#define GPIOD_USART2_RST 4 +#define GPIOD_USART2_TX 5 +#define GPIOD_USART2_RX 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_AUDIO_RST 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_SD_CS 2 +#define GPIOE_SD_DETECT 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_JOY_SEL 6 +#define GPIOE_RTD_IN 7 +#define GPIOE_PRESSUREP 8 +#define GPIOE_PRESSUREN 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PRESSURE_TEPM 14 +#define GPIOE_PIN15 15 + +#define GPIOF_OSC_IN 0 +#define GPIOF_OSC_OUT 1 +#define GPIOF_JOY_DOWN 2 +#define GPIOF_PIN3 3 +#define GPIOF_JOY_LEFT 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_JOY_RIGHT 9 +#define GPIOF_JOY_UP 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - WKUP_BUTTON (input floating). + * PA1 - LDR_OUT (analog). + * PA2 - KEY_BUTTON (input floating). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input floating). + * PA6 - PIN6 (input pullup). + * PA7 - COMP2_OUT (output pushpull maximum). + * PA8 - I2C2_SMB (input floating). + * PA9 - I2C2_SCL (alternate 4). + * PA10 - I2C2_SDA (alternate 4). + * PA11 - USB_DM (alternate 14). + * PA12 - USB_DP (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - JTDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP_BUTTON) | \ + PIN_MODE_ANALOG(GPIOA_LDR_OUT) | \ + PIN_MODE_INPUT(GPIOA_KEY_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_OUTPUT(GPIOA_COMP2_OUT) | \ + PIN_MODE_INPUT(GPIOA_I2C2_SMB) | \ + PIN_MODE_ALTERNATE(GPIOA_I2C2_SCL) | \ + PIN_MODE_ALTERNATE(GPIOA_I2C2_SDA) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_WKUP_BUTTON) |\ + PIN_OTYPE_PUSHPULL(GPIOA_LDR_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOA_KEY_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_COMP2_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOA_I2C2_SMB) | \ + PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_WKUP_BUTTON) | \ + PIN_OSPEED_2M(GPIOA_LDR_OUT) | \ + PIN_OSPEED_2M(GPIOA_KEY_BUTTON) | \ + PIN_OSPEED_2M(GPIOA_PIN3) | \ + PIN_OSPEED_2M(GPIOA_PIN4) | \ + PIN_OSPEED_100M(GPIOA_PIN5) | \ + PIN_OSPEED_2M(GPIOA_PIN6) | \ + PIN_OSPEED_100M(GPIOA_COMP2_OUT) | \ + PIN_OSPEED_2M(GPIOA_I2C2_SMB) | \ + PIN_OSPEED_100M(GPIOA_I2C2_SCL) | \ + PIN_OSPEED_100M(GPIOA_I2C2_SDA) | \ + PIN_OSPEED_100M(GPIOA_USB_DM) | \ + PIN_OSPEED_2M(GPIOA_USB_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_100M(GPIOA_JTDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_WKUP_BUTTON) |\ + PIN_PUPDR_FLOATING(GPIOA_LDR_OUT) | \ + PIN_PUPDR_FLOATING(GPIOA_KEY_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOA_COMP2_OUT) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C2_SMB) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C2_SCL) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C2_SDA) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_JTDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_WKUP_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_LDR_OUT) | \ + PIN_ODR_HIGH(GPIOA_KEY_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_LOW(GPIOA_COMP2_OUT) | \ + PIN_ODR_HIGH(GPIOA_I2C2_SMB) | \ + PIN_ODR_HIGH(GPIOA_I2C2_SCL) | \ + PIN_ODR_HIGH(GPIOA_I2C2_SDA) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_JTDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_WKUP_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_LDR_OUT, 0) | \ + PIN_AFIO_AF(GPIOA_KEY_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 5) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_COMP2_OUT, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C2_SMB, 0) | \ + PIN_AFIO_AF(GPIOA_I2C2_SCL, 4) | \ + PIN_AFIO_AF(GPIOA_I2C2_SDA, 4) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 14) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 14) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_JTDI, 0)) + +/* + * GPIOB setup: + * + * PB0 - MIC_IN (analog). + * PB1 - ADC_POT_IN (analog). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - JTRST (input floating). + * PB5 - PIN5 (input pullup). + * PB6 - I2C1_SCL (alternate 4). + * PB7 - I2C1_SDA (alternate 4). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_MIC_IN) | \ + PIN_MODE_ANALOG(GPIOB_ADC_POT_IN) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_JTRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_MIC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ADC_POT_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_MIC_IN) | \ + PIN_OSPEED_2M(GPIOB_ADC_POT_IN) | \ + PIN_OSPEED_2M(GPIOB_PIN2) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_100M(GPIOB_JTRST) | \ + PIN_OSPEED_2M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_2M(GPIOB_PIN8) | \ + PIN_OSPEED_2M(GPIOB_PIN9) | \ + PIN_OSPEED_2M(GPIOB_PIN10) | \ + PIN_OSPEED_2M(GPIOB_PIN11) | \ + PIN_OSPEED_2M(GPIOB_PIN12) | \ + PIN_OSPEED_2M(GPIOB_PIN13) | \ + PIN_OSPEED_2M(GPIOB_PIN14) | \ + PIN_OSPEED_2M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_MIC_IN) | \ + PIN_PUPDR_FLOATING(GPIOB_ADC_POT_IN) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_FLOATING(GPIOB_JTRST) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_MIC_IN) | \ + PIN_ODR_HIGH(GPIOB_ADC_POT_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_JTRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_MIC_IN, 0) | \ + PIN_AFIO_AF(GPIOB_ADC_POT_IN, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_JTRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - LED1 (output opendrain maximum). + * PC1 - LED2 (output opendrain maximum). + * PC2 - LED3 (output opendrain maximum). + * PC3 - LED4 (output opendrain maximum). + * PC4 - PIN4 (input pullup). + * PC5 - USB_DISCONNECT (output pushpull maximum). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SPI3_SCK (alternate 6). + * PC11 - SPI3_MISO (alternate 6). + * PC12 - SPI3_MOSI (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_LED1) | \ + PIN_MODE_OUTPUT(GPIOC_LED2) | \ + PIN_MODE_OUTPUT(GPIOC_LED3) | \ + PIN_MODE_OUTPUT(GPIOC_LED4) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_OUTPUT(GPIOC_USB_DISCONNECT) |\ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOC_LED1) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_LED2) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_LED3) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USB_DISCONNECT) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_LED1) | \ + PIN_OSPEED_100M(GPIOC_LED2) | \ + PIN_OSPEED_100M(GPIOC_LED3) | \ + PIN_OSPEED_100M(GPIOC_LED4) | \ + PIN_OSPEED_2M(GPIOC_PIN4) | \ + PIN_OSPEED_100M(GPIOC_USB_DISCONNECT) |\ + PIN_OSPEED_2M(GPIOC_PIN6) | \ + PIN_OSPEED_2M(GPIOC_PIN7) | \ + PIN_OSPEED_2M(GPIOC_PIN8) | \ + PIN_OSPEED_2M(GPIOC_PIN9) | \ + PIN_OSPEED_100M(GPIOC_SPI3_SCK) | \ + PIN_OSPEED_100M(GPIOC_SPI3_MISO) | \ + PIN_OSPEED_100M(GPIOC_SPI3_MOSI) | \ + PIN_OSPEED_2M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_LED1) | \ + PIN_PUPDR_FLOATING(GPIOC_LED2) | \ + PIN_PUPDR_FLOATING(GPIOC_LED3) | \ + PIN_PUPDR_FLOATING(GPIOC_LED4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOC_USB_DISCONNECT) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) | \ + PIN_PUPDR_PULLUP(GPIOC_SPI3_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_LED1) | \ + PIN_ODR_HIGH(GPIOC_LED2) | \ + PIN_ODR_HIGH(GPIOC_LED3) | \ + PIN_ODR_HIGH(GPIOC_LED4) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_USB_DISCONNECT) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_SPI3_SCK) | \ + PIN_ODR_HIGH(GPIOC_SPI3_MISO) | \ + PIN_ODR_HIGH(GPIOC_SPI3_MOSI) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_LED1, 0) | \ + PIN_AFIO_AF(GPIOC_LED2, 0) | \ + PIN_AFIO_AF(GPIOC_LED3, 0) | \ + PIN_AFIO_AF(GPIOC_LED4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_USB_DISCONNECT, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - CAN_RX (alternate 7). + * PD1 - CAN_TX (alternate 7). + * PD2 - LCD_CS (output pushpull maximum). + * PD3 - USART2_CTS (alternate 7). + * PD4 - USART2_RST (alternate 7). + * PD5 - USART2_TX (alternate 7). + * PD6 - USART2_RX (alternate 7). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - AUDIO_RST (output pushpull maximum). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_CAN_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_CAN_TX) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_CS) | \ + PIN_MODE_ALTERNATE(GPIOD_USART2_CTS) | \ + PIN_MODE_ALTERNATE(GPIOD_USART2_RST) | \ + PIN_MODE_ALTERNATE(GPIOD_USART2_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART2_RX) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_OUTPUT(GPIOD_AUDIO_RST) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_CAN_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CAN_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART2_CTS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART2_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART2_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART2_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_CAN_RX) | \ + PIN_OSPEED_100M(GPIOD_CAN_TX) | \ + PIN_OSPEED_100M(GPIOD_LCD_CS) | \ + PIN_OSPEED_100M(GPIOD_USART2_CTS) | \ + PIN_OSPEED_100M(GPIOD_USART2_RST) | \ + PIN_OSPEED_100M(GPIOD_USART2_TX) | \ + PIN_OSPEED_100M(GPIOD_USART2_RX) | \ + PIN_OSPEED_2M(GPIOD_PIN7) | \ + PIN_OSPEED_2M(GPIOD_PIN8) | \ + PIN_OSPEED_2M(GPIOD_PIN9) | \ + PIN_OSPEED_2M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_AUDIO_RST) | \ + PIN_OSPEED_2M(GPIOD_PIN12) | \ + PIN_OSPEED_2M(GPIOD_PIN13) | \ + PIN_OSPEED_2M(GPIOD_PIN14) | \ + PIN_OSPEED_2M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_CAN_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_CAN_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_CS) | \ + PIN_PUPDR_FLOATING(GPIOD_USART2_CTS) | \ + PIN_PUPDR_FLOATING(GPIOD_USART2_RST) | \ + PIN_PUPDR_FLOATING(GPIOD_USART2_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART2_RX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOD_AUDIO_RST) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_CAN_RX) | \ + PIN_ODR_HIGH(GPIOD_CAN_TX) | \ + PIN_ODR_HIGH(GPIOD_LCD_CS) | \ + PIN_ODR_HIGH(GPIOD_USART2_CTS) | \ + PIN_ODR_HIGH(GPIOD_USART2_RST) | \ + PIN_ODR_HIGH(GPIOD_USART2_TX) | \ + PIN_ODR_HIGH(GPIOD_USART2_RX) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_LOW(GPIOD_AUDIO_RST) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_CAN_RX, 7) | \ + PIN_AFIO_AF(GPIOD_CAN_TX, 7) | \ + PIN_AFIO_AF(GPIOD_LCD_CS, 0) | \ + PIN_AFIO_AF(GPIOD_USART2_CTS, 7) | \ + PIN_AFIO_AF(GPIOD_USART2_RST, 7) | \ + PIN_AFIO_AF(GPIOD_USART2_TX, 7) | \ + PIN_AFIO_AF(GPIOD_USART2_RX, 7) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_AUDIO_RST, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - SD_CS (output opendrain maximum). + * PE3 - SD_DETECT (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - JOY_SEL (input pulldown). + * PE7 - RTD_IN (analog). + * PE8 - PRESSUREP (analog). + * PE9 - PRESSUREN (analog). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PRESSURE_TEPM (input floating). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_OUTPUT(GPIOE_SD_CS) | \ + PIN_MODE_INPUT(GPIOE_SD_DETECT) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_JOY_SEL) | \ + PIN_MODE_ANALOG(GPIOE_RTD_IN) | \ + PIN_MODE_ANALOG(GPIOE_PRESSUREP) | \ + PIN_MODE_ANALOG(GPIOE_PRESSUREN) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PRESSURE_TEPM) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_OPENDRAIN(GPIOE_SD_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SD_DETECT) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_JOY_SEL) | \ + PIN_OTYPE_PUSHPULL(GPIOE_RTD_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREP) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREN) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PRESSURE_TEPM) |\ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_PIN0) | \ + PIN_OSPEED_2M(GPIOE_PIN1) | \ + PIN_OSPEED_100M(GPIOE_SD_CS) | \ + PIN_OSPEED_100M(GPIOE_SD_DETECT) | \ + PIN_OSPEED_2M(GPIOE_PIN4) | \ + PIN_OSPEED_2M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_JOY_SEL) | \ + PIN_OSPEED_2M(GPIOE_RTD_IN) | \ + PIN_OSPEED_100M(GPIOE_PRESSUREP) | \ + PIN_OSPEED_100M(GPIOE_PRESSUREN) | \ + PIN_OSPEED_2M(GPIOE_PIN10) | \ + PIN_OSPEED_2M(GPIOE_PIN11) | \ + PIN_OSPEED_2M(GPIOE_PIN12) | \ + PIN_OSPEED_2M(GPIOE_PIN13) | \ + PIN_OSPEED_2M(GPIOE_PRESSURE_TEPM) | \ + PIN_OSPEED_2M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_SD_CS) | \ + PIN_PUPDR_PULLUP(GPIOE_SD_DETECT) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLDOWN(GPIOE_JOY_SEL) | \ + PIN_PUPDR_FLOATING(GPIOE_RTD_IN) | \ + PIN_PUPDR_FLOATING(GPIOE_PRESSUREP) | \ + PIN_PUPDR_FLOATING(GPIOE_PRESSUREN) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PRESSURE_TEPM) |\ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_SD_CS) | \ + PIN_ODR_HIGH(GPIOE_SD_DETECT) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_JOY_SEL) | \ + PIN_ODR_HIGH(GPIOE_RTD_IN) | \ + PIN_ODR_HIGH(GPIOE_PRESSUREP) | \ + PIN_ODR_HIGH(GPIOE_PRESSUREN) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_LOW(GPIOE_PIN13) | \ + PIN_ODR_LOW(GPIOE_PRESSURE_TEPM) | \ + PIN_ODR_LOW(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0) | \ + PIN_AFIO_AF(GPIOE_SD_CS, 0) | \ + PIN_AFIO_AF(GPIOE_SD_DETECT, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_JOY_SEL, 0) | \ + PIN_AFIO_AF(GPIOE_RTD_IN, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PRESSUREP, 0) | \ + PIN_AFIO_AF(GPIOE_PRESSUREN, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PRESSURE_TEPM, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - OSC_IN (input floating). + * PF1 - OSC_OUT (input floating). + * PF2 - JOY_DOWN (input pulldown). + * PF3 - PIN3 (input pullup). + * PF4 - JOY_LEFT (input pulldown). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - JOY_RIGHT (input pulldown). + * PF10 - JOY_UP (input pulldown). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ + PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOF_JOY_DOWN) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_JOY_LEFT) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_JOY_RIGHT) | \ + PIN_MODE_INPUT(GPIOF_JOY_UP) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_JOY_DOWN) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_JOY_LEFT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_JOY_RIGHT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_JOY_UP) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_OSC_IN) | \ + PIN_OSPEED_100M(GPIOF_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOF_JOY_DOWN) | \ + PIN_OSPEED_2M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_JOY_LEFT) | \ + PIN_OSPEED_2M(GPIOF_PIN5) | \ + PIN_OSPEED_2M(GPIOF_PIN6) | \ + PIN_OSPEED_2M(GPIOF_PIN7) | \ + PIN_OSPEED_2M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_JOY_RIGHT) | \ + PIN_OSPEED_100M(GPIOF_JOY_UP) | \ + PIN_OSPEED_2M(GPIOF_PIN11) | \ + PIN_OSPEED_2M(GPIOF_PIN12) | \ + PIN_OSPEED_2M(GPIOF_PIN13) | \ + PIN_OSPEED_2M(GPIOF_PIN14) | \ + PIN_OSPEED_2M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ + PIN_PUPDR_PULLDOWN(GPIOF_JOY_DOWN) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLDOWN(GPIOF_JOY_LEFT) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLDOWN(GPIOF_JOY_RIGHT) | \ + PIN_PUPDR_PULLDOWN(GPIOF_JOY_UP) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ + PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOF_JOY_DOWN) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_JOY_LEFT) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_JOY_RIGHT) | \ + PIN_ODR_HIGH(GPIOF_JOY_UP) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOF_JOY_DOWN, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_JOY_LEFT, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_JOY_RIGHT, 0) | \ + PIN_AFIO_AF(GPIOF_JOY_UP, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32373C_EVAL/board.mk b/boards/ST_STM32373C_EVAL/board.mk new file mode 100644 index 000000000..98a37d006 --- /dev/null +++ b/boards/ST_STM32373C_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32373C_EVAL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32373C_EVAL diff --git a/boards/ST_STM32373C_EVAL/cfg/board.chcfg b/boards/ST_STM32373C_EVAL/cfg/board.chcfg new file mode 100644 index 000000000..85f428ef8 --- /dev/null +++ b/boards/ST_STM32373C_EVAL/cfg/board.chcfg @@ -0,0 +1,798 @@ + + + + + resources/gencfg/processors/boards/stm32f3xx/templates + .. + + STMicroelectronics STM32373C-EVAL + ST_STM32373C_EVAL + + STM32F37X + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ST_STM32F0_DISCOVERY/board.c b/boards/ST_STM32F0_DISCOVERY/board.c new file mode 100644 index 000000000..0393835ad --- /dev/null +++ b/boards/ST_STM32F0_DISCOVERY/board.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32F0_DISCOVERY/board.h b/boards/ST_STM32F0_DISCOVERY/board.h new file mode 100644 index 000000000..088cf38e3 --- /dev/null +++ b/boards/ST_STM32F0_DISCOVERY/board.h @@ -0,0 +1,757 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for ST STM32F0-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F0_DISCOVERY +#define BOARD_NAME "ST STM32F0-Discovery" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + * NOTE: HSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#define STM32_LSEDRV (3 << 3) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 0 +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header file stm32f0xx.h. + */ +#define STM32F0XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_PIN7 7 +#define GPIOA_PIN8 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_PIN11 11 +#define GPIOA_PIN12 12 +#define GPIOA_SWDAT 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_PIN3 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_PIN0 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_LED4 8 +#define GPIOC_LED3 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOF_OSC_IN 0 +#define GPIOF_OSC_OUT 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_10M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_40M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - PIN11 (input pullup). + * PA12 - PIN12 (input pullup). + * PA13 - SWDAT (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDAT) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \ + PIN_OSPEED_2M(GPIOA_PIN1) | \ + PIN_OSPEED_2M(GPIOA_PIN2) | \ + PIN_OSPEED_2M(GPIOA_PIN3) | \ + PIN_OSPEED_2M(GPIOA_PIN4) | \ + PIN_OSPEED_2M(GPIOA_PIN5) | \ + PIN_OSPEED_2M(GPIOA_PIN6) | \ + PIN_OSPEED_2M(GPIOA_PIN7) | \ + PIN_OSPEED_2M(GPIOA_PIN8) | \ + PIN_OSPEED_2M(GPIOA_PIN9) | \ + PIN_OSPEED_2M(GPIOA_PIN10) | \ + PIN_OSPEED_2M(GPIOA_PIN11) | \ + PIN_OSPEED_2M(GPIOA_PIN12) | \ + PIN_OSPEED_40M(GPIOA_SWDAT) | \ + PIN_OSPEED_40M(GPIOA_SWCLK) | \ + PIN_OSPEED_40M(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDAT) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_SWDAT) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0) | \ + PIN_AFIO_AF(GPIOA_SWDAT, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - PIN3 (input pullup). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \ + PIN_OSPEED_2M(GPIOB_PIN1) | \ + PIN_OSPEED_40M(GPIOB_PIN2) | \ + PIN_OSPEED_40M(GPIOB_PIN3) | \ + PIN_OSPEED_40M(GPIOB_PIN4) | \ + PIN_OSPEED_2M(GPIOB_PIN5) | \ + PIN_OSPEED_2M(GPIOB_PIN6) | \ + PIN_OSPEED_2M(GPIOB_PIN7) | \ + PIN_OSPEED_2M(GPIOB_PIN8) | \ + PIN_OSPEED_2M(GPIOB_PIN9) | \ + PIN_OSPEED_2M(GPIOB_PIN10) | \ + PIN_OSPEED_2M(GPIOB_PIN11) | \ + PIN_OSPEED_2M(GPIOB_PIN12) | \ + PIN_OSPEED_2M(GPIOB_PIN13) | \ + PIN_OSPEED_2M(GPIOB_PIN14) | \ + PIN_OSPEED_2M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_PIN3) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_PIN3, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - LED4 (output pushpull maximum). + * PC9 - LED3 (output pushpull maximum). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_OUTPUT(GPIOC_LED4) | \ + PIN_MODE_OUTPUT(GPIOC_LED3) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \ + PIN_OSPEED_2M(GPIOC_PIN1) | \ + PIN_OSPEED_2M(GPIOC_PIN2) | \ + PIN_OSPEED_2M(GPIOC_PIN3) | \ + PIN_OSPEED_2M(GPIOC_PIN4) | \ + PIN_OSPEED_2M(GPIOC_PIN5) | \ + PIN_OSPEED_2M(GPIOC_PIN6) | \ + PIN_OSPEED_2M(GPIOC_PIN7) | \ + PIN_OSPEED_40M(GPIOC_LED4) | \ + PIN_OSPEED_40M(GPIOC_LED3) | \ + PIN_OSPEED_2M(GPIOC_PIN10) | \ + PIN_OSPEED_2M(GPIOC_PIN11) | \ + PIN_OSPEED_2M(GPIOC_PIN12) | \ + PIN_OSPEED_2M(GPIOC_PIN13) | \ + PIN_OSPEED_40M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_40M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOC_LED4) | \ + PIN_PUPDR_FLOATING(GPIOC_LED3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_LOW(GPIOC_LED4) | \ + PIN_ODR_LOW(GPIOC_LED3) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED4, 0) | \ + PIN_AFIO_AF(GPIOC_LED3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \ + PIN_OSPEED_2M(GPIOD_PIN1) | \ + PIN_OSPEED_2M(GPIOD_PIN2) | \ + PIN_OSPEED_2M(GPIOD_PIN3) | \ + PIN_OSPEED_2M(GPIOD_PIN4) | \ + PIN_OSPEED_2M(GPIOD_PIN5) | \ + PIN_OSPEED_2M(GPIOD_PIN6) | \ + PIN_OSPEED_2M(GPIOD_PIN7) | \ + PIN_OSPEED_2M(GPIOD_PIN8) | \ + PIN_OSPEED_2M(GPIOD_PIN9) | \ + PIN_OSPEED_2M(GPIOD_PIN10) | \ + PIN_OSPEED_2M(GPIOD_PIN11) | \ + PIN_OSPEED_2M(GPIOD_PIN12) | \ + PIN_OSPEED_2M(GPIOD_PIN13) | \ + PIN_OSPEED_2M(GPIOD_PIN14) | \ + PIN_OSPEED_2M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - OSC_IN (input floating). + * PF1 - OSC_OUT (input floating). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ + PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_2M(GPIOF_OSC_IN) | \ + PIN_OSPEED_2M(GPIOF_OSC_OUT) | \ + PIN_OSPEED_2M(GPIOF_PIN2) | \ + PIN_OSPEED_2M(GPIOF_PIN3) | \ + PIN_OSPEED_2M(GPIOF_PIN4) | \ + PIN_OSPEED_2M(GPIOF_PIN5) | \ + PIN_OSPEED_2M(GPIOF_PIN6) | \ + PIN_OSPEED_2M(GPIOF_PIN7) | \ + PIN_OSPEED_2M(GPIOF_PIN8) | \ + PIN_OSPEED_2M(GPIOF_PIN9) | \ + PIN_OSPEED_2M(GPIOF_PIN10) | \ + PIN_OSPEED_2M(GPIOF_PIN11) | \ + PIN_OSPEED_2M(GPIOF_PIN12) | \ + PIN_OSPEED_2M(GPIOF_PIN13) | \ + PIN_OSPEED_2M(GPIOF_PIN14) | \ + PIN_OSPEED_2M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ + PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32F0_DISCOVERY/board.mk b/boards/ST_STM32F0_DISCOVERY/board.mk new file mode 100644 index 000000000..144ae4963 --- /dev/null +++ b/boards/ST_STM32F0_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY diff --git a/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..3773f03d1 --- /dev/null +++ b/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,667 @@ + + + + + resources/gencfg/processors/boards/stm32f0xx/templates + .. + + ST STM32F0-Discovery + ST_STM32F0_DISCOVERY + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ST_STM32F3_DISCOVERY/board.c b/boards/ST_STM32F3_DISCOVERY/board.c new file mode 100644 index 000000000..baafd6550 --- /dev/null +++ b/boards/ST_STM32F3_DISCOVERY/board.c @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32F3_DISCOVERY/board.h b/boards/ST_STM32F3_DISCOVERY/board.h new file mode 100644 index 000000000..147dfb9b1 --- /dev/null +++ b/boards/ST_STM32F3_DISCOVERY/board.h @@ -0,0 +1,891 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F3-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F3_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F3-Discovery" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#define STM32_LSEDRV (3 << 3) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header. + */ +#define STM32F30X + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_SPI1_SCK 5 +#define GPIOA_SPI1_MISO 6 +#define GPIOA_SPI1_MOSI 7 +#define GPIOA_PIN8 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_USB_DM 11 +#define GPIOA_USB_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_I2C1_SCL 6 +#define GPIOB_I2C1_SDA 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_PIN0 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_L3GD20_INT1 0 +#define GPIOE_L3GD20_INT2 1 +#define GPIOE_LSM303_DRDY 2 +#define GPIOE_SPI1_CS 3 +#define GPIOE_LSM303_INT1 4 +#define GPIOE_LSM303_INT2 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_LED4_BLUE 8 +#define GPIOE_LED3_RED 9 +#define GPIOE_LED5_ORANGE 10 +#define GPIOE_LED7_GREEN 11 +#define GPIOE_LED9_BLUE 12 +#define GPIOE_LED10_RED 13 +#define GPIOE_LED8_ORANGE 14 +#define GPIOE_LED6_GREEN 15 + +#define GPIOF_OSC_IN 0 +#define GPIOF_OSC_OUT 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - SPI1_SCK (alternate 5). + * PA6 - SPI1_MISO (alternate 5). + * PA7 - SPI1_MOSI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - USB_DM (alternate 14). + * PA12 - USB_DP (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \ + PIN_OSPEED_2M(GPIOA_PIN1) | \ + PIN_OSPEED_2M(GPIOA_PIN2) | \ + PIN_OSPEED_2M(GPIOA_PIN3) | \ + PIN_OSPEED_2M(GPIOA_PIN4) | \ + PIN_OSPEED_100M(GPIOA_SPI1_SCK) | \ + PIN_OSPEED_100M(GPIOA_SPI1_MISO) | \ + PIN_OSPEED_100M(GPIOA_SPI1_MOSI) | \ + PIN_OSPEED_2M(GPIOA_PIN8) | \ + PIN_OSPEED_2M(GPIOA_PIN9) | \ + PIN_OSPEED_2M(GPIOA_PIN10) | \ + PIN_OSPEED_100M(GPIOA_USB_DM) | \ + PIN_OSPEED_2M(GPIOA_USB_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_2M(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ + PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ + PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ + PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 14) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 14) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - I2C1_SCL (alternate 4). + * PB7 - I2C1_SDA (alternate 4). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \ + PIN_OSPEED_2M(GPIOB_PIN1) | \ + PIN_OSPEED_2M(GPIOB_PIN2) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_2M(GPIOB_PIN4) | \ + PIN_OSPEED_2M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_2M(GPIOB_PIN8) | \ + PIN_OSPEED_2M(GPIOB_PIN9) | \ + PIN_OSPEED_2M(GPIOB_PIN10) | \ + PIN_OSPEED_2M(GPIOB_PIN11) | \ + PIN_OSPEED_2M(GPIOB_PIN12) | \ + PIN_OSPEED_2M(GPIOB_PIN13) | \ + PIN_OSPEED_2M(GPIOB_PIN14) | \ + PIN_OSPEED_2M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \ + PIN_OSPEED_2M(GPIOC_PIN1) | \ + PIN_OSPEED_2M(GPIOC_PIN2) | \ + PIN_OSPEED_2M(GPIOC_PIN3) | \ + PIN_OSPEED_2M(GPIOC_PIN4) | \ + PIN_OSPEED_2M(GPIOC_PIN5) | \ + PIN_OSPEED_2M(GPIOC_PIN6) | \ + PIN_OSPEED_2M(GPIOC_PIN7) | \ + PIN_OSPEED_2M(GPIOC_PIN8) | \ + PIN_OSPEED_2M(GPIOC_PIN9) | \ + PIN_OSPEED_2M(GPIOC_PIN10) | \ + PIN_OSPEED_2M(GPIOC_PIN11) | \ + PIN_OSPEED_2M(GPIOC_PIN12) | \ + PIN_OSPEED_2M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \ + PIN_OSPEED_2M(GPIOD_PIN1) | \ + PIN_OSPEED_2M(GPIOD_PIN2) | \ + PIN_OSPEED_2M(GPIOD_PIN3) | \ + PIN_OSPEED_2M(GPIOD_PIN4) | \ + PIN_OSPEED_2M(GPIOD_PIN5) | \ + PIN_OSPEED_2M(GPIOD_PIN6) | \ + PIN_OSPEED_2M(GPIOD_PIN7) | \ + PIN_OSPEED_2M(GPIOD_PIN8) | \ + PIN_OSPEED_2M(GPIOD_PIN9) | \ + PIN_OSPEED_2M(GPIOD_PIN10) | \ + PIN_OSPEED_2M(GPIOD_PIN11) | \ + PIN_OSPEED_2M(GPIOD_PIN12) | \ + PIN_OSPEED_2M(GPIOD_PIN13) | \ + PIN_OSPEED_2M(GPIOD_PIN14) | \ + PIN_OSPEED_2M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - L3GD20_INT1 (input pullup). + * PE1 - L3GD20_INT2 (input pullup). + * PE2 - LSM303_DRDY (input pullup). + * PE3 - SPI1_CS (output pushpull maximum). + * PE4 - LSM303_INT1 (input pullup). + * PE5 - LSM303_INT2 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - LED4_BLUE (output pushpull maximum). + * PE9 - LED3_RED (output pushpull maximum). + * PE10 - LED5_ORANGE (output pushpull maximum). + * PE11 - LED7_GREEN (output pushpull maximum). + * PE12 - LED9_BLUE (output pushpull maximum). + * PE13 - LED10_RED (output pushpull maximum). + * PE14 - LED8_ORANGE (output pushpull maximum). + * PE15 - LED6_GREEN (output pushpull maximum). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) | \ + PIN_MODE_INPUT(GPIOE_L3GD20_INT2) | \ + PIN_MODE_INPUT(GPIOE_LSM303_DRDY) | \ + PIN_MODE_OUTPUT(GPIOE_SPI1_CS) | \ + PIN_MODE_INPUT(GPIOE_LSM303_INT1) | \ + PIN_MODE_INPUT(GPIOE_LSM303_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_OUTPUT(GPIOE_LED4_BLUE) | \ + PIN_MODE_OUTPUT(GPIOE_LED3_RED) | \ + PIN_MODE_OUTPUT(GPIOE_LED5_ORANGE) | \ + PIN_MODE_OUTPUT(GPIOE_LED7_GREEN) | \ + PIN_MODE_OUTPUT(GPIOE_LED9_BLUE) | \ + PIN_MODE_OUTPUT(GPIOE_LED10_RED) | \ + PIN_MODE_OUTPUT(GPIOE_LED8_ORANGE) | \ + PIN_MODE_OUTPUT(GPIOE_LED6_GREEN)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) |\ + PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303_DRDY) |\ + PIN_OTYPE_PUSHPULL(GPIOE_SPI1_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT1) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT2) |\ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED4_BLUE) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED3_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED5_ORANGE) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LED7_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED9_BLUE) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED10_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED8_ORANGE) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LED6_GREEN)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_L3GD20_INT1) | \ + PIN_OSPEED_2M(GPIOE_L3GD20_INT2) | \ + PIN_OSPEED_2M(GPIOE_LSM303_DRDY) | \ + PIN_OSPEED_100M(GPIOE_SPI1_CS) | \ + PIN_OSPEED_2M(GPIOE_LSM303_INT1) | \ + PIN_OSPEED_2M(GPIOE_LSM303_INT2) | \ + PIN_OSPEED_2M(GPIOE_PIN6) | \ + PIN_OSPEED_2M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_LED4_BLUE) | \ + PIN_OSPEED_100M(GPIOE_LED3_RED) | \ + PIN_OSPEED_100M(GPIOE_LED5_ORANGE) | \ + PIN_OSPEED_100M(GPIOE_LED7_GREEN) | \ + PIN_OSPEED_100M(GPIOE_LED9_BLUE) | \ + PIN_OSPEED_100M(GPIOE_LED10_RED) | \ + PIN_OSPEED_100M(GPIOE_LED8_ORANGE) | \ + PIN_OSPEED_100M(GPIOE_LED6_GREEN)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) | \ + PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) | \ + PIN_PUPDR_PULLUP(GPIOE_LSM303_DRDY) | \ + PIN_PUPDR_FLOATING(GPIOE_SPI1_CS) | \ + PIN_PUPDR_PULLUP(GPIOE_LSM303_INT1) | \ + PIN_PUPDR_PULLUP(GPIOE_LSM303_INT2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_LED4_BLUE) | \ + PIN_PUPDR_PULLUP(GPIOE_LED3_RED) | \ + PIN_PUPDR_PULLUP(GPIOE_LED5_ORANGE) | \ + PIN_PUPDR_FLOATING(GPIOE_LED7_GREEN) | \ + PIN_PUPDR_PULLUP(GPIOE_LED9_BLUE) | \ + PIN_PUPDR_FLOATING(GPIOE_LED10_RED) | \ + PIN_PUPDR_FLOATING(GPIOE_LED8_ORANGE) |\ + PIN_PUPDR_FLOATING(GPIOE_LED6_GREEN)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) | \ + PIN_ODR_HIGH(GPIOE_L3GD20_INT2) | \ + PIN_ODR_HIGH(GPIOE_LSM303_DRDY) | \ + PIN_ODR_HIGH(GPIOE_SPI1_CS) | \ + PIN_ODR_HIGH(GPIOE_LSM303_INT1) | \ + PIN_ODR_HIGH(GPIOE_LSM303_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_LOW(GPIOE_LED4_BLUE) | \ + PIN_ODR_LOW(GPIOE_LED3_RED) | \ + PIN_ODR_LOW(GPIOE_LED5_ORANGE) | \ + PIN_ODR_LOW(GPIOE_LED7_GREEN) | \ + PIN_ODR_LOW(GPIOE_LED9_BLUE) | \ + PIN_ODR_LOW(GPIOE_LED10_RED) | \ + PIN_ODR_LOW(GPIOE_LED8_ORANGE) | \ + PIN_ODR_LOW(GPIOE_LED6_GREEN)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_LSM303_DRDY, 0) | \ + PIN_AFIO_AF(GPIOE_SPI1_CS, 0) | \ + PIN_AFIO_AF(GPIOE_LSM303_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_LSM303_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_LED4_BLUE, 0) | \ + PIN_AFIO_AF(GPIOE_LED3_RED, 0) | \ + PIN_AFIO_AF(GPIOE_LED5_ORANGE, 0) | \ + PIN_AFIO_AF(GPIOE_LED7_GREEN, 0) | \ + PIN_AFIO_AF(GPIOE_LED9_BLUE, 0) | \ + PIN_AFIO_AF(GPIOE_LED10_RED, 0) | \ + PIN_AFIO_AF(GPIOE_LED8_ORANGE, 0) | \ + PIN_AFIO_AF(GPIOE_LED6_GREEN, 0)) + +/* + * GPIOF setup: + * + * PF0 - OSC_IN (input floating). + * PF1 - OSC_OUT (input floating). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ + PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_OSC_IN) | \ + PIN_OSPEED_100M(GPIOF_OSC_OUT) | \ + PIN_OSPEED_2M(GPIOF_PIN2) | \ + PIN_OSPEED_2M(GPIOF_PIN3) | \ + PIN_OSPEED_2M(GPIOF_PIN4) | \ + PIN_OSPEED_2M(GPIOF_PIN5) | \ + PIN_OSPEED_2M(GPIOF_PIN6) | \ + PIN_OSPEED_2M(GPIOF_PIN7) | \ + PIN_OSPEED_2M(GPIOF_PIN8) | \ + PIN_OSPEED_2M(GPIOF_PIN9) | \ + PIN_OSPEED_2M(GPIOF_PIN10) | \ + PIN_OSPEED_2M(GPIOF_PIN11) | \ + PIN_OSPEED_2M(GPIOF_PIN12) | \ + PIN_OSPEED_2M(GPIOF_PIN13) | \ + PIN_OSPEED_2M(GPIOF_PIN14) | \ + PIN_OSPEED_2M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ + PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32F3_DISCOVERY/board.mk b/boards/ST_STM32F3_DISCOVERY/board.mk new file mode 100644 index 000000000..522082fe9 --- /dev/null +++ b/boards/ST_STM32F3_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY diff --git a/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..cbd264d03 --- /dev/null +++ b/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,798 @@ + + + + + resources/gencfg/processors/boards/stm32f3xx/templates + .. + + STMicroelectronics STM32F3-Discovery + ST_STM32F3_DISCOVERY + + STM32F30X + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ST_STM32F4_DISCOVERY/board.c b/boards/ST_STM32F4_DISCOVERY/board.c new file mode 100644 index 000000000..99569f695 --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h new file mode 100644 index 000000000..6e636db9e --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -0,0 +1,1297 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F4-Discovery" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_LRCK 4 +#define GPIOA_SPC 5 +#define GPIOA_SDO 6 +#define GPIOA_SDI 7 +#define GPIOA_PIN8 8 +#define GPIOA_VBUS_FS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_SCL 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_SDA 9 +#define GPIOB_CLK_IN 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_OTG_FS_POWER_ON 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PDM_OUT 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_MCLK 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_SCLK 10 +#define GPIOC_PIN11 11 +#define GPIOC_SDIN 12 +#define GPIOC_PIN13 13 +#define GPIOC_PIN14 14 +#define GPIOC_PIN15 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_RESET 4 +#define GPIOD_OVER_CURRENT 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_LED4 12 +#define GPIOD_LED3 13 +#define GPIOD_LED5 14 +#define GPIOD_LED6 15 + +#define GPIOE_INT1 0 +#define GPIOE_INT2 1 +#define GPIOE_PIN2 2 +#define GPIOE_CS_SPI 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_PIN10 10 +#define GPIOG_PIN11 11 +#define GPIOG_PIN12 12 +#define GPIOG_PIN13 13 +#define GPIOG_PIN14 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - LRCK (alternate 6). + * PA5 - SPC (alternate 5). + * PA6 - SDO (alternate 5). + * PA7 - SDI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \ + PIN_OSPEED_100M(GPIOA_PIN1) | \ + PIN_OSPEED_100M(GPIOA_PIN2) | \ + PIN_OSPEED_100M(GPIOA_PIN3) | \ + PIN_OSPEED_100M(GPIOA_LRCK) | \ + PIN_OSPEED_50M(GPIOA_SPC) | \ + PIN_OSPEED_50M(GPIOA_SDO) | \ + PIN_OSPEED_50M(GPIOA_SDI) | \ + PIN_OSPEED_100M(GPIOA_PIN8) | \ + PIN_OSPEED_100M(GPIOA_VBUS_FS) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_100M(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPC) | \ + PIN_PUPDR_FLOATING(GPIOA_SDO) | \ + PIN_PUPDR_FLOATING(GPIOA_SDI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_LRCK) | \ + PIN_ODR_HIGH(GPIOA_SPC) | \ + PIN_ODR_HIGH(GPIOA_SDO) | \ + PIN_ODR_HIGH(GPIOA_SDI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_LRCK, 6) | \ + PIN_AFIO_AF(GPIOA_SPC, 5) | \ + PIN_AFIO_AF(GPIOA_SDO, 5) | \ + PIN_AFIO_AF(GPIOA_SDI, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - SDA (alternate 4). + * PB10 - CLK_IN (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_SCL) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOB_SDA) | \ + PIN_MODE_INPUT(GPIOB_CLK_IN) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ + PIN_OSPEED_100M(GPIOB_PIN1) | \ + PIN_OSPEED_100M(GPIOB_PIN2) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_100M(GPIOB_PIN4) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_SCL) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_PIN8) | \ + PIN_OSPEED_100M(GPIOB_SDA) | \ + PIN_OSPEED_100M(GPIOB_CLK_IN) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ + PIN_OSPEED_100M(GPIOB_PIN12) | \ + PIN_OSPEED_100M(GPIOB_PIN13) | \ + PIN_OSPEED_100M(GPIOB_PIN14) | \ + PIN_OSPEED_100M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_SCL) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_SDA) | \ + PIN_ODR_HIGH(GPIOB_CLK_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PDM_OUT (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - MCLK (alternate 6). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SCLK (alternate 6). + * PC11 - PIN11 (input pullup). + * PC12 - SDIN (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PDM_OUT) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOC_MCLK) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_SCLK) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIN) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_100M(GPIOC_PIN1) | \ + PIN_OSPEED_100M(GPIOC_PIN2) | \ + PIN_OSPEED_100M(GPIOC_PDM_OUT) | \ + PIN_OSPEED_100M(GPIOC_PIN4) | \ + PIN_OSPEED_100M(GPIOC_PIN5) | \ + PIN_OSPEED_100M(GPIOC_PIN6) | \ + PIN_OSPEED_100M(GPIOC_MCLK) | \ + PIN_OSPEED_100M(GPIOC_PIN8) | \ + PIN_OSPEED_100M(GPIOC_PIN9) | \ + PIN_OSPEED_100M(GPIOC_SCLK) | \ + PIN_OSPEED_100M(GPIOC_PIN11) | \ + PIN_OSPEED_100M(GPIOC_SDIN) | \ + PIN_OSPEED_100M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_PIN14) | \ + PIN_OSPEED_100M(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_MCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_SCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIN) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PDM_OUT) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_MCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_SCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_SDIN) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_MCLK, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_SCLK, 6) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_SDIN, 6) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - RESET (output pushpull maximum). + * PD5 - OVER_CURRENT (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_OUTPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ + PIN_OSPEED_100M(GPIOD_PIN1) | \ + PIN_OSPEED_100M(GPIOD_PIN2) | \ + PIN_OSPEED_100M(GPIOD_PIN3) | \ + PIN_OSPEED_100M(GPIOD_RESET) | \ + PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_100M(GPIOD_PIN6) | \ + PIN_OSPEED_100M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_PIN8) | \ + PIN_OSPEED_100M(GPIOD_PIN9) | \ + PIN_OSPEED_100M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_PIN11) | \ + PIN_OSPEED_100M(GPIOD_LED4) | \ + PIN_OSPEED_100M(GPIOD_LED3) | \ + PIN_OSPEED_100M(GPIOD_LED5) | \ + PIN_OSPEED_100M(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_RESET) | \ + PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_LED4) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_LED5) | \ + PIN_PUPDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_RESET) | \ + PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_LOW(GPIOD_LED4) | \ + PIN_ODR_LOW(GPIOD_LED3) | \ + PIN_ODR_LOW(GPIOD_LED5) | \ + PIN_ODR_LOW(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_RESET, 0) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_LED4, 0) | \ + PIN_AFIO_AF(GPIOD_LED3, 0) | \ + PIN_AFIO_AF(GPIOD_LED5, 0) | \ + PIN_AFIO_AF(GPIOD_LED6, 0)) + +/* + * GPIOE setup: + * + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). + * PE2 - PIN2 (input floating). + * PE3 - CS_SPI (output pushpull maximum). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ + PIN_MODE_INPUT(GPIOE_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \ + PIN_OSPEED_100M(GPIOE_INT2) | \ + PIN_OSPEED_100M(GPIOE_PIN2) | \ + PIN_OSPEED_100M(GPIOE_CS_SPI) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_PIN8) | \ + PIN_OSPEED_100M(GPIOE_PIN9) | \ + PIN_OSPEED_100M(GPIOE_PIN10) | \ + PIN_OSPEED_100M(GPIOE_PIN11) | \ + PIN_OSPEED_100M(GPIOE_PIN12) | \ + PIN_OSPEED_100M(GPIOE_PIN13) | \ + PIN_OSPEED_100M(GPIOE_PIN14) | \ + PIN_OSPEED_100M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \ + PIN_PUPDR_FLOATING(GPIOE_INT2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \ + PIN_ODR_HIGH(GPIOE_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_CS_SPI) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input floating). + * PF1 - PIN1 (input floating). + * PF2 - PIN2 (input floating). + * PF3 - PIN3 (input floating). + * PF4 - PIN4 (input floating). + * PF5 - PIN5 (input floating). + * PF6 - PIN6 (input floating). + * PF7 - PIN7 (input floating). + * PF8 - PIN8 (input floating). + * PF9 - PIN9 (input floating). + * PF10 - PIN10 (input floating). + * PF11 - PIN11 (input floating). + * PF12 - PIN12 (input floating). + * PF13 - PIN13 (input floating). + * PF14 - PIN14 (input floating). + * PF15 - PIN15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ + PIN_OSPEED_100M(GPIOF_PIN1) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_PIN4) | \ + PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_PIN9) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_PIN11) | \ + PIN_OSPEED_100M(GPIOF_PIN12) | \ + PIN_OSPEED_100M(GPIOF_PIN13) | \ + PIN_OSPEED_100M(GPIOF_PIN14) | \ + PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input floating). + * PG1 - PIN1 (input floating). + * PG2 - PIN2 (input floating). + * PG3 - PIN3 (input floating). + * PG4 - PIN4 (input floating). + * PG5 - PIN5 (input floating). + * PG6 - PIN6 (input floating). + * PG7 - PIN7 (input floating). + * PG8 - PIN8 (input floating). + * PG9 - PIN9 (input floating). + * PG10 - PIN10 (input floating). + * PG11 - PIN11 (input floating). + * PG12 - PIN12 (input floating). + * PG13 - PIN13 (input floating). + * PG14 - PIN14 (input floating). + * PG15 - PIN15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ + PIN_OSPEED_100M(GPIOG_PIN1) | \ + PIN_OSPEED_100M(GPIOG_PIN2) | \ + PIN_OSPEED_100M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_PIN4) | \ + PIN_OSPEED_100M(GPIOG_PIN5) | \ + PIN_OSPEED_100M(GPIOG_PIN6) | \ + PIN_OSPEED_100M(GPIOG_PIN7) | \ + PIN_OSPEED_100M(GPIOG_PIN8) | \ + PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_PIN10) | \ + PIN_OSPEED_100M(GPIOG_PIN11) | \ + PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_PIN13) | \ + PIN_OSPEED_100M(GPIOG_PIN14) | \ + PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32F4_DISCOVERY/board.mk b/boards/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 000000000..eb47aa2af --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY diff --git a/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..e30de70e6 --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1186 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + STMicroelectronics STM32F4-Discovery + ST_STM32F4_DISCOVERY + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ST_STM32L_DISCOVERY/board.c b/boards/ST_STM32L_DISCOVERY/board.c new file mode 100644 index 000000000..3d5ff42d9 --- /dev/null +++ b/boards/ST_STM32L_DISCOVERY/board.c @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h new file mode 100644 index 000000000..efbd86dae --- /dev/null +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -0,0 +1,890 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for ST STM32L-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32L_DISCOVERY +#define BOARD_NAME "ST STM32L-Discovery" + + +/* + * Board oscillators-related settings. + * NOTE: HSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 0 +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header file stm32l1xx.h. + */ +#define STM32L1XX_MD + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_PIN7 7 +#define GPIOA_PIN8 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_PIN11 11 +#define GPIOA_PIN12 12 +#define GPIOA_JTAG_TMS 13 +#define GPIOA_JTAG_TCK 14 +#define GPIOA_JTAG_TDI 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTAG_TDO 3 +#define GPIOB_JTAG_TRST 4 +#define GPIOB_PIN5 5 +#define GPIOB_LED4 6 +#define GPIOB_LED3 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_PIN0 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_400K(n) (0U << ((n) * 2)) +#define PIN_OSPEED_2M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_10M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_40M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - PIN11 (input pullup). + * PA12 - PIN12 (input pullup). + * PA13 - JTAG_TMS (alternate 0). + * PA14 - JTAG_TCK (alternate 0). + * PA15 - JTAG_TDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_400K(GPIOA_BUTTON) | \ + PIN_OSPEED_400K(GPIOA_PIN1) | \ + PIN_OSPEED_400K(GPIOA_PIN2) | \ + PIN_OSPEED_400K(GPIOA_PIN3) | \ + PIN_OSPEED_400K(GPIOA_PIN4) | \ + PIN_OSPEED_400K(GPIOA_PIN5) | \ + PIN_OSPEED_400K(GPIOA_PIN6) | \ + PIN_OSPEED_400K(GPIOA_PIN7) | \ + PIN_OSPEED_400K(GPIOA_PIN8) | \ + PIN_OSPEED_400K(GPIOA_PIN9) | \ + PIN_OSPEED_400K(GPIOA_PIN10) | \ + PIN_OSPEED_400K(GPIOA_PIN11) | \ + PIN_OSPEED_400K(GPIOA_PIN12) | \ + PIN_OSPEED_40M(GPIOA_JTAG_TMS) | \ + PIN_OSPEED_40M(GPIOA_JTAG_TCK) | \ + PIN_OSPEED_40M(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOA_JTAG_TMS) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \ + PIN_PUPDR_PULLUP(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TDI, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - BOOT1 (input floating). + * PB3 - JTAG_TDO (alternate 0). + * PB4 - JTAG_TRST (alternate 0). + * PB5 - PIN5 (input pullup). + * PB6 - LED4 (output pushpull maximum). + * PB7 - LED3 (output pushpull maximum). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_OUTPUT(GPIOB_LED4) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_400K(GPIOB_PIN0) | \ + PIN_OSPEED_400K(GPIOB_PIN1) | \ + PIN_OSPEED_40M(GPIOB_BOOT1) | \ + PIN_OSPEED_40M(GPIOB_JTAG_TDO) | \ + PIN_OSPEED_40M(GPIOB_JTAG_TRST) | \ + PIN_OSPEED_400K(GPIOB_PIN5) | \ + PIN_OSPEED_40M(GPIOB_LED4) | \ + PIN_OSPEED_40M(GPIOB_LED3) | \ + PIN_OSPEED_400K(GPIOB_PIN8) | \ + PIN_OSPEED_400K(GPIOB_PIN9) | \ + PIN_OSPEED_400K(GPIOB_PIN10) | \ + PIN_OSPEED_400K(GPIOB_PIN11) | \ + PIN_OSPEED_400K(GPIOB_PIN12) | \ + PIN_OSPEED_400K(GPIOB_PIN13) | \ + PIN_OSPEED_400K(GPIOB_PIN14) | \ + PIN_OSPEED_400K(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ + PIN_PUPDR_PULLUP(GPIOB_JTAG_TRST) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_LED4) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_LOW(GPIOB_LED4) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_LED4, 0) | \ + PIN_AFIO_AF(GPIOB_LED3, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_400K(GPIOC_PIN0) | \ + PIN_OSPEED_400K(GPIOC_PIN1) | \ + PIN_OSPEED_400K(GPIOC_PIN2) | \ + PIN_OSPEED_400K(GPIOC_PIN3) | \ + PIN_OSPEED_400K(GPIOC_PIN4) | \ + PIN_OSPEED_400K(GPIOC_PIN5) | \ + PIN_OSPEED_400K(GPIOC_PIN6) | \ + PIN_OSPEED_400K(GPIOC_PIN7) | \ + PIN_OSPEED_400K(GPIOC_PIN8) | \ + PIN_OSPEED_400K(GPIOC_PIN9) | \ + PIN_OSPEED_400K(GPIOC_PIN10) | \ + PIN_OSPEED_400K(GPIOC_PIN11) | \ + PIN_OSPEED_400K(GPIOC_PIN12) | \ + PIN_OSPEED_400K(GPIOC_PIN13) | \ + PIN_OSPEED_40M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_40M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_400K(GPIOD_PIN0) | \ + PIN_OSPEED_400K(GPIOD_PIN1) | \ + PIN_OSPEED_400K(GPIOD_PIN2) | \ + PIN_OSPEED_400K(GPIOD_PIN3) | \ + PIN_OSPEED_400K(GPIOD_PIN4) | \ + PIN_OSPEED_400K(GPIOD_PIN5) | \ + PIN_OSPEED_400K(GPIOD_PIN6) | \ + PIN_OSPEED_400K(GPIOD_PIN7) | \ + PIN_OSPEED_400K(GPIOD_PIN8) | \ + PIN_OSPEED_400K(GPIOD_PIN9) | \ + PIN_OSPEED_400K(GPIOD_PIN10) | \ + PIN_OSPEED_400K(GPIOD_PIN11) | \ + PIN_OSPEED_400K(GPIOD_PIN12) | \ + PIN_OSPEED_400K(GPIOD_PIN13) | \ + PIN_OSPEED_400K(GPIOD_PIN14) | \ + PIN_OSPEED_400K(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_400K(GPIOE_PIN0) | \ + PIN_OSPEED_400K(GPIOE_PIN1) | \ + PIN_OSPEED_400K(GPIOE_PIN2) | \ + PIN_OSPEED_400K(GPIOE_PIN3) | \ + PIN_OSPEED_400K(GPIOE_PIN4) | \ + PIN_OSPEED_400K(GPIOE_PIN5) | \ + PIN_OSPEED_400K(GPIOE_PIN6) | \ + PIN_OSPEED_400K(GPIOE_PIN7) | \ + PIN_OSPEED_400K(GPIOE_PIN8) | \ + PIN_OSPEED_400K(GPIOE_PIN9) | \ + PIN_OSPEED_400K(GPIOE_PIN10) | \ + PIN_OSPEED_400K(GPIOE_PIN11) | \ + PIN_OSPEED_400K(GPIOE_PIN12) | \ + PIN_OSPEED_400K(GPIOE_PIN13) | \ + PIN_OSPEED_400K(GPIOE_PIN14) | \ + PIN_OSPEED_400K(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_40M(GPIOH_OSC_IN) | \ + PIN_OSPEED_40M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_400K(GPIOH_PIN2) | \ + PIN_OSPEED_400K(GPIOH_PIN3) | \ + PIN_OSPEED_400K(GPIOH_PIN4) | \ + PIN_OSPEED_400K(GPIOH_PIN5) | \ + PIN_OSPEED_400K(GPIOH_PIN6) | \ + PIN_OSPEED_400K(GPIOH_PIN7) | \ + PIN_OSPEED_400K(GPIOH_PIN8) | \ + PIN_OSPEED_400K(GPIOH_PIN9) | \ + PIN_OSPEED_400K(GPIOH_PIN10) | \ + PIN_OSPEED_400K(GPIOH_PIN11) | \ + PIN_OSPEED_400K(GPIOH_PIN12) | \ + PIN_OSPEED_400K(GPIOH_PIN13) | \ + PIN_OSPEED_400K(GPIOH_PIN14) | \ + PIN_OSPEED_400K(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32L_DISCOVERY/board.mk b/boards/ST_STM32L_DISCOVERY/board.mk new file mode 100644 index 000000000..7e3fdd8e3 --- /dev/null +++ b/boards/ST_STM32L_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32L_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32L_DISCOVERY diff --git a/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..b42e09289 --- /dev/null +++ b/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,799 @@ + + + + + resources/gencfg/processors/boards/stm32l1xx/templates + .. + + ST STM32L-Discovery + ST_STM32L_DISCOVERY + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ST_STM32VL_DISCOVERY/board.c b/boards/ST_STM32VL_DISCOVERY/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/boards/ST_STM32VL_DISCOVERY/board.c @@ -0,0 +1,50 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32VL_DISCOVERY/board.h b/boards/ST_STM32VL_DISCOVERY/board.h new file mode 100644 index 000000000..36e157d48 --- /dev/null +++ b/boards/ST_STM32VL_DISCOVERY/board.h @@ -0,0 +1,143 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32VL-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32VL_DISCOVERY +#define BOARD_NAME "ST STM32VL-Discovery" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD_VL + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_SPI1NSS 4 + +#define GPIOB_SPI2NSS 12 + +#define GPIOC_LED4 8 +#define GPIOC_LED3 9 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (BUTTON). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + * PA4 - Push pull output (SPI1 NSS), initially high state. + * PA5 - Alternate output (SPI1 SCK). + * PA6 - Normal input (SPI1 MISO). + * PA7 - Alternate output (SPI1 MOSI). + * PA9 - Alternate output (USART1 TX). + * PA10 - Normal input (USART1 RX). + */ +#define VAL_GPIOACRL 0xB4B34B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x888884B8 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB12 - Push pull output (SPI2 NSS), initially high state. + * PB13 - Alternate output (SPI2 SCK). + * PB14 - Normal input (SPI2 MISO). + * PB15 - Alternate output (SPI2 MOSI). + */ +#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0xB4B38888 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC8 - Push-pull output (LED4), initially low state. + * PC9 - Push-pull output (LED3), initially low state. + */ +#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88888833 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFCFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32VL_DISCOVERY/board.mk b/boards/ST_STM32VL_DISCOVERY/board.mk new file mode 100644 index 000000000..36467943c --- /dev/null +++ b/boards/ST_STM32VL_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32VL_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32VL_DISCOVERY diff --git a/boards/ST_STM8L_DISCOVERY/board.c b/boards/ST_STM8L_DISCOVERY/board.c new file mode 100644 index 000000000..d530c295c --- /dev/null +++ b/boards/ST_STM8L_DISCOVERY/board.c @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +ROMCONST PALConfig pal_default_config = +{ + { + {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2}, + {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2}, + {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2}, + {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2}, + {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2}, + {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2}, + } +}; +#endif + +/* + * TIM 2 clock after the prescaler. + */ +#define TIM2_CLOCK (SYSCLK / 16) +#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1) + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * TIM2 initialization as system tick. + */ + CLK->PCKENR1 |= CLK_PCKENR1_TIM2; + TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/ + TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8); + TIM2->ARRL = (uint8_t)(TIM2_ARR); + TIM2->CNTRH = 0; + TIM2->CNTRL = 0; + TIM2->SR1 = 0; + TIM2->IER = TIM_IER_UIE; + TIM2->CR1 = TIM_CR1_CEN; +} diff --git a/boards/ST_STM8L_DISCOVERY/board.h b/boards/ST_STM8L_DISCOVERY/board.h new file mode 100644 index 000000000..907279ee7 --- /dev/null +++ b/boards/ST_STM8L_DISCOVERY/board.h @@ -0,0 +1,167 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM8L-Discovery board. + */ + +/* + * Board identifiers. + */ +#define BOARD_ST_STM8L_DISCOVERY +#define BOARD_NAME "ST STM8L-Discovery" + +/* + * Board frequencies and bypass modes. + * + * The bypass must be set to TRUE if the chip is driven by an external + * oscillator rather than a crystal. Frequency must be set to zero if + * the clock source is not used at all. + * The following constants are used by the HAL low level driver for + * correct clock initialization. + */ +#define HSECLK 0 +#define HSEBYPASS FALSE +#define LSECLK 32768 +#define LSEBYPASS FALSE + +/* + * MCU model used on the board. + */ +#define STM8L152C6 +#define STM8L15X_MD + +/* + * Pin definitions. + */ +#define PA_OSC_IN 2 +#define PA_OSC_OUT 3 +#define PA_LCD_COM0 4 +#define PA_LCD_COM1 5 +#define PA_LCD_COM2 6 +#define PA_LCD_SEG0 7 + +#define PB_LCD_SEG10 0 +#define PB_LCD_SEG11 1 +#define PB_LCD_SEG12 2 +#define PB_LCD_SEG13 3 +#define PB_LCD_SEG14 4 +#define PB_LCD_SEG15 5 +#define PB_LCD_SEG16 6 +#define PB_LCD_SEG17 7 + +#define PC_UNUSED 0 +#define PC_BUTTON 1 +#define PC_LCD_SEG22 2 +#define PC_LCD_SEG23 3 +#define PC_IDD_CNT_EN 4 +#define PC_LED4 7 + +#define PD_LCD_SEG7 0 +#define PD_LCD_COM3 1 +#define PD_LCD_SEG8 2 +#define PD_LCD_SEG9 3 +#define PD_LCD_SEG18 4 +#define PD_LCD_SEG19 5 +#define PD_LCD_SEG20 6 +#define PD_LCD_SEG21 7 + +#define PE_LCD_SEG1 0 +#define PE_LCD_SEG2 1 +#define PE_LCD_SEG3 2 +#define PE_LCD_SEG4 3 +#define PE_LCD_SEG5 4 +#define PE_LCD_SEG6 5 +#define PE_IDD_WAKEUP 6 +#define PE_LED3 7 + +#define PF0_IDD_MEASUREMENT 0 + +/* + * Port A initial setup. + */ +#define VAL_GPIOAODR 0 +#define VAL_GPIOADDR 0 /* All inputs. */ +#define VAL_GPIOACR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIOACR2 0 + +/* + * Port B initial setup. + */ +#define VAL_GPIOBODR 0 +#define VAL_GPIOBDDR 0 /* All inputs. */ +#define VAL_GPIOBCR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIOBCR2 0 + +/* + * Port C initial setup. + */ +#define VAL_GPIOCODR 0 +#define VAL_GPIOCDDR (1 << PC_LED4) +#define VAL_GPIOCCR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIOCCR2 0 + +/* + * Port D initial setup. + */ +#define VAL_GPIODODR 0 +#define VAL_GPIODDDR 0 /* All inputs. */ +#define VAL_GPIODCR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIODCR2 0 + +/* + * Port E initial setup. + */ +#define VAL_GPIOEODR 0 +#define VAL_GPIOEDDR (1 << PE_LED3) +#define VAL_GPIOECR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIOECR2 0 + +/* + * Port F initial setup. + */ +#define VAL_GPIOFODR 0 +#define VAL_GPIOFDDR 0 /* All inputs. */ +#define VAL_GPIOFCR1 0xFF /* All pull-up/push-pull. */ +#define VAL_GPIOFCR2 0 + +/* + * TIM2-update ISR segment code. This code is injected into the appropriate + * ISR by the HAL. + */ +#define _TIM2_UPDATE_ISR() { \ + if (TIM2->SR1 & TIM_SR1_UIF) { \ + chSysLockFromIsr(); \ + chSysTimerHandlerI(); \ + chSysUnlockFromIsr(); \ + TIM2->SR1 = 0; \ + } \ +} + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM8S_DISCOVERY/board.c b/boards/ST_STM8S_DISCOVERY/board.c new file mode 100644 index 000000000..33e1fa1e9 --- /dev/null +++ b/boards/ST_STM8S_DISCOVERY/board.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +ROMCONST PALConfig pal_default_config = +{ + { + {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2}, + {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2}, + {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2}, + {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2}, + {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2}, + {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2}, + {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2}, + } +}; +#endif + +/* + * TIM 2 clock after the prescaler. + */ +#define TIM2_CLOCK (SYSCLK / 16) +#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1) + +/* + * TIM2 interrupt handler. + */ +CH_IRQ_HANDLER(13) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + TIM2->SR1 = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + + /* + * TIM2 initialization as system tick. + */ + CLK->PCKENR1 |= CLK_PCKENR1_TIM2; + TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/ + TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8); + TIM2->ARRL = (uint8_t)(TIM2_ARR); + TIM2->CNTRH = 0; + TIM2->CNTRL = 0; + TIM2->SR1 = 0; + TIM2->IER = TIM2_IER_UIE; + TIM2->CR1 = TIM2_CR1_CEN; +} diff --git a/boards/ST_STM8S_DISCOVERY/board.h b/boards/ST_STM8S_DISCOVERY/board.h new file mode 100644 index 000000000..70e8682da --- /dev/null +++ b/boards/ST_STM8S_DISCOVERY/board.h @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM8S-Discovery board. + */ + +/* + * Board identifiers. + */ +#define BOARD_ST_STM8S_DISCOVERY +#define BOARD_NAME "ST STM8S-Discovery" + +/* + * Board frequencies. + */ +#define HSECLK 16000000 + +/* + * MCU model used on the board. + */ +#define STM8S105 + +/* + * Pin definitions. + */ +#define PA_OSCIN 1 +#define PA_OSCOUT 2 + +#define PC_TS_KEY 1 +#define PC_TS_LOADREF 2 +#define PC_TS_SHIELD 3 + +#define PD_LD10 0 +#define PD_SWIM 1 +#define PD_TX 5 +#define PD_RX 6 + +/* + * Port A initial setup. + */ +#define VAL_GPIOAODR 0 +#define VAL_GPIOADDR 0 /* All inputs. */ +#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */ +#define VAL_GPIOACR2 0 + +/* + * Port B initial setup. + */ +#define VAL_GPIOBODR 0 +#define VAL_GPIOBDDR 0 /* All inputs. */ +#define VAL_GPIOBCR1 0xFF /* All push-pull. */ +#define VAL_GPIOBCR2 0 + +/* + * Port C initial setup. + */ +#define VAL_GPIOCODR 0 +#define VAL_GPIOCDDR 0 /* All inputs. */ +#define VAL_GPIOCCR1 0xFF /* All pull-up. */ +#define VAL_GPIOCCR2 0 + +/* + * Port D initial setup. + */ +#define VAL_GPIODODR (1 << PD_LD10) | (1 << PD_TX) +#define VAL_GPIODDDR (1 << PD_LD10) | (1 << PD_TX) +#define VAL_GPIODCR1 0xFF /* All pull-up. */ +#define VAL_GPIODCR2 0 + +/* + * Port E initial setup. + */ +#define VAL_GPIOEODR 0 +#define VAL_GPIOEDDR 0 /* All inputs. */ +#define VAL_GPIOECR1 0xFF /* All pull-up. */ +#define VAL_GPIOECR2 0 + +/* + * Port F initial setup. + */ +#define VAL_GPIOFODR 0 +#define VAL_GPIOFDDR 0 /* All inputs. */ +#define VAL_GPIOFCR1 0xFF /* All pull-up. */ +#define VAL_GPIOFCR2 0 + +/* + * Port G initial setup. + */ +#define VAL_GPIOGODR 0 +#define VAL_GPIOGDDR 0 /* All inputs. */ +#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */ +#define VAL_GPIOGCR2 0 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/readme.txt b/boards/readme.txt new file mode 100644 index 000000000..b08a21bfb --- /dev/null +++ b/boards/readme.txt @@ -0,0 +1,6 @@ +This directory contains the support files for various board models. If you +want to support a new board: +- Create a new directory under ./boards, give it the name of your board. +- Copy inside the new directory the files from a similar board. +- Customize board.c, board.h and board.mk in order to correctly initialize + your board. diff --git a/boards/simulator/board.c b/boards/simulator/board.c new file mode 100644 index 000000000..6912c20ad --- /dev/null +++ b/boards/simulator/board.c @@ -0,0 +1,35 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + {0, 0, 0}, + {0, 0, 0} +}; +#endif + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/simulator/board.h b/boards/simulator/board.h new file mode 100644 index 000000000..ee9b14e73 --- /dev/null +++ b/boards/simulator/board.h @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/simulator/board.mk b/boards/simulator/board.mk new file mode 100644 index 000000000..a48747c66 --- /dev/null +++ b/boards/simulator/board.mk @@ -0,0 +1,5 @@ +# List of all the simulator board related files. +BOARDSRC = ${CHIBIOS}/boards/simulator/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/simulator diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile new file mode 100644 index 000000000..0389049bf --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -0,0 +1,192 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/AT91SAM7X256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/ffconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h new file mode 100644 index 000000000..4614abe14 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c new file mode 100644 index 000000000..85edb9ed1 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -0,0 +1,399 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" +#include "evtimer.h" +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + /* The presence check is performed only while the driver is not in a + transfer state because it is often performed by changing the mode of + the pin connected to the CS/D3 contact of the card, this could disturb + the transfer.*/ + blkstate_t state = blkGetDriverState(bbdp); + chSysLockFromIsr(); + if ((state != BLK_READING) && (state != BLK_WRITING)) { + /* Safe to perform the check.*/ + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +#define MAX_SPI_BITRATE 100 +#define MIN_SPI_BITRATE 250 + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (__MHz, NCPHA=1, CPOL=0).*/ +static SPIConfig hs_spicfg = { + NULL, + IOPORT1, + PIOA_CS_MMC, + (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* Low speed SPI configuration (192kHz, NCPHA=1, CPOL=0).*/ +static SPIConfig ls_spicfg = { + NULL, + IOPORT1, + PIOA_CS_MMC, + (MIN_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* MMC/SD over SPI driver configuration.*/ +static MMCConfig mmccfg = {&SPID1, &ls_spicfg, &hs_spicfg}; + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: tree\r\n"); + return; + } + if (!fs_ready) { + chprintf(chp, "File System not mounted\r\n"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf(chp, "FS: f_getfree() failed\r\n"); + return; + } + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files(chp, (char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * LCD blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *p) { + + (void)p; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) { + return; + } + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + mmcDisconnect(&MMCD1); + fs_ready = FALSE; +} + +/* + * Application entry point. + */ +int main(void) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the MMC driver to work with SPI. + */ + palSetPadMode(IOPORT1, PIOA_CS_MMC, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, PIOA_CS_MMC); + mmcObjectInit(&MMCD1); + mmcStart(&MMCD1, &mmccfg); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&MMCD1); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&inserted_event, &el0, 0); + chEvtRegister(&removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500))); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..25cfbfc57 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI TRUE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 TRUE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt b/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt new file mode 100644 index 000000000..4430e8b41 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for SAM7. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM-EX256 board. The port on other boards or other +members of the SAM7 family should be an easy task. + +** The Demo ** + +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LCD background using a thread and monitors the MMC +slot for a card insertion. When a card is inserted then the file system is +mounted and the LCD background flashes faster. +A command line shell is spawned on SD1, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile new file mode 100644 index 000000000..02da69ba2 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -0,0 +1,187 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/AT91SAM7X256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c new file mode 100644 index 000000000..88ded5d19 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *p) { + + (void)p; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h new file mode 100644 index 000000000..5221d02df --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-GCC/readme.txt b/demos/ARM7-AT91SAM7X-GCC/readme.txt new file mode 100644 index 000000000..1b5240c97 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo currently just flashes the LCD background using a thread. +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile new file mode 100644 index 000000000..e9ac17116 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -0,0 +1,190 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/AT91SAM7X256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LWSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + ./web/web.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h new file mode 100644 index 000000000..63751bbdf --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h new file mode 100644 index 000000000..5a8e51970 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -0,0 +1,2127 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c new file mode 100644 index 000000000..96401164e --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "lwipthread.h" +#include "web/web.h" + +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *p) { + + (void)p; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Creates the LWIP threads (it changes priority internally). + */ + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, + lwip_thread, NULL); + + /* + * Creates the HTTP thread (it changes priority internally). + */ + chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, + http_server, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h new file mode 100644 index 000000000..5221d02df --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt new file mode 100644 index 000000000..14495cc0c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt @@ -0,0 +1,34 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo currently just flashes the LCD background using a thread and serves +HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP +address into web.c in order to adapt it to your network settings). +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. +The demo requires the lwIP 1.3.1 stack, included in ./ext + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com + +The lwIP stack also has its own license, please read the info into the included +lwIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c new file mode 100644 index 000000000..c4f16852e --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file is a modified version of the lwIP web server demo. The original + * author is unknown because the file didn't contain any license information. + */ + +/** + * @file web.c + * @brief HTTP server wrapper thread code. + * @addtogroup WEB_THREAD + * @{ + */ + +#include "ch.h" + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" + +#include "web.h" + +#if LWIP_NETCONN + +static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; + +static void http_server_serve(struct netconn *conn) { + struct netbuf *inbuf; + char *buf; + u16_t buflen; + err_t err; + + /* Read the data from the port, blocking if nothing yet there. + We assume the request (the part we care about) is in one netbuf */ + err = netconn_recv(conn, &inbuf); + + if (err == ERR_OK) { + netbuf_data(inbuf, (void **)&buf, &buflen); + + /* Is this an HTTP GET command? (only check the first 5 chars, since + there are other formats for GET, and we're keeping it very simple )*/ + if (buflen>=5 && + buf[0]=='G' && + buf[1]=='E' && + buf[2]=='T' && + buf[3]==' ' && + buf[4]=='/' ) { + + /* Send the HTML header + * subtract 1 from the size, since we dont send the \0 in the string + * NETCONN_NOCOPY: our data is const static, so no need to copy it + */ + netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); + + /* Send our HTML page */ + netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); + } + } + /* Close the connection (server closes in HTTP) */ + netconn_close(conn); + + /* Delete the buffer (netconn_recv gives us ownership, + so we have to make sure to deallocate the buffer) */ + netbuf_delete(inbuf); +} + +/** + * Stack area for the http thread. + */ +WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +/** + * HTTP server thread. + */ +msg_t http_server(void *p) { + struct netconn *conn, *newconn; + err_t err; + + (void)p; + + /* Create a new TCP connection handle */ + conn = netconn_new(NETCONN_TCP); + LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); + + /* Bind to port 80 (HTTP) with default IP address */ + netconn_bind(conn, NULL, WEB_THREAD_PORT); + + /* Put the connection into LISTEN state */ + netconn_listen(conn); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(WEB_THREAD_PRIORITY); + + while(1) { + err = netconn_accept(conn, &newconn); + if (err != ERR_OK) + continue; + http_server_serve(newconn); + netconn_delete(newconn); + } + return RDY_OK; +} + +#endif /* LWIP_NETCONN */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h new file mode 100644 index 000000000..1dc8b6675 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file web.h + * @brief HTTP server wrapper thread macros and structures. + * @addtogroup WEB_THREAD + * @{ + */ + +#ifndef _WEB_H_ +#define _WEB_H_ + +#ifndef WEB_THREAD_STACK_SIZE +#define WEB_THREAD_STACK_SIZE 1024 +#endif + +#ifndef WEB_THREAD_PORT +#define WEB_THREAD_PORT 80 +#endif + +#ifndef WEB_THREAD_PRIORITY +#define WEB_THREAD_PRIORITY (LOWPRIO + 2) +#endif + +extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t http_server(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _WEB_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile new file mode 100644 index 000000000..09d89a9aa --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -0,0 +1,203 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/AT91SAM7X256.ld + +# List of the required uIP source files. +USRC = $(CHIBIOS)/ext/uip-1.0/uip/uip_arp.c \ + $(CHIBIOS)/ext/uip-1.0/uip/psock.c \ + $(CHIBIOS)/ext/uip-1.0/uip/uip.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/http-strings.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-fs.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-cgi.c + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(USRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/evtimer.c \ + web/webthread.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/ext/uip-1.0/uip \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver \ + ./web + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h new file mode 100644 index 000000000..63751bbdf --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c new file mode 100644 index 000000000..2a96a4f9b --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "web/webthread.h" + +static WORKING_AREA(waWebThread, 1024); + +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *p) { + + (void)p; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker and web server threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waWebThread, sizeof(waWebThread), LOWPRIO, WebThread, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h new file mode 100644 index 000000000..5221d02df --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt new file mode 100644 index 000000000..9d3b84e97 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt @@ -0,0 +1,34 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo currently just flashes the LCD background using a thread and serves +HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP +address into webthread.c in order to adapt it to your network settings). +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. +The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com + +The uIP stack also has its own license, please read the info into the included +uIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h new file mode 100644 index 000000000..744cf56ef --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h @@ -0,0 +1,9 @@ +#ifndef __CC_ARCH_H__ +#define __CC_ARCH_H__ + +#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END + +#endif /* __CC_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h new file mode 100644 index 000000000..e205f9c8d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include + +typedef systime_t clock_time_t; +#define CLOCK_CONF_SECOND CH_FREQUENCY + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h new file mode 100644 index 000000000..b6a17c970 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +#include /* patched */ + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1518 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c new file mode 100644 index 000000000..ac4f8779b --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -0,0 +1,183 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "evtimer.h" + +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "clock-arch.h" + +#define IPADDR0 192 +#define IPADDR1 168 +#define IPADDR2 1 +#define IPADDR3 20 + +#define SEND_TIMEOUT 50 + +static const struct uip_eth_addr macaddr = { + {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} +}; + +static const MACConfig mac_config = {macaddr.addr}; + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + +/* + * uIP send function wrapping the EMAC functions. + */ +static void network_device_send(void) { + MACTransmitDescriptor td; + + if (macWaitTransmitDescriptor(ÐD1, &td, MS2ST(SEND_TIMEOUT)) == RDY_OK) { + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) + macWriteTransmitDescriptor(&td, uip_buf, uip_len); + else { + macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); + macWriteTransmitDescriptor(&td, uip_appdata, + uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); + } + macReleaseTransmitDescriptor(&td); + } + /* Dropped... */ +} + +/* + * uIP receive function wrapping the EMAC function. + */ +static size_t network_device_read(void) { + MACReceiveDescriptor rd; + size_t size; + + if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) != RDY_OK) + return 0; + size = rd.size; + macReadReceiveDescriptor(&rd, uip_buf, size); + macReleaseReceiveDescriptor(&rd); + return size; +} + +void clock_init(void) {} + +clock_time_t clock_time( void ) +{ + return chTimeNow(); +} + +/* + * TCP/IP periodic timer. + */ +static void PeriodicTimerHandler(eventid_t id) { + int i; + + (void)id; + for (i = 0; i < UIP_CONNS; i++) { + uip_periodic(i); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } +} + +/* + * ARP periodic timer. + */ +static void ARPTimerHandler(eventid_t id) { + + (void)id; + (void)macPollLinkStatus(ÐD1); + uip_arp_timer(); +} + +/* + * Ethernet frame received. + */ +static void FrameReceivedHandler(eventid_t id) { + + (void)id; + while ((uip_len = network_device_read()) > 0) { + if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } + else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if (uip_len > 0) + network_device_send(); + } + } +} + +#define FRAME_RECEIVED_ID 0 +#define PERIODIC_TIMER_ID 1 +#define ARP_TIMER_ID 2 + +static const evhandler_t evhndl[] = { + FrameReceivedHandler, + PeriodicTimerHandler, + ARPTimerHandler +}; + +msg_t WebThread(void *p) { + EvTimer evt1, evt2; + EventListener el0, el1, el2; + uip_ipaddr_t ipaddr; + + (void)p; + + /* + * Event sources setup. + */ + chEvtRegister(macGetReceiveEventSource(ÐD1), &el0, FRAME_RECEIVED_ID); + chEvtAddEvents(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ + + evtInit(&evt1, MS2ST(500)); + evtStart(&evt1); + chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); + + evtInit(&evt2, S2ST(10)); + evtStart(&evt2); + chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); + + /* + * EMAC driver start. + */ + macStart(ÐD1, &mac_config); + (void)macPollLinkStatus(ÐD1); + + /* + * uIP initialization. + */ + uip_init(); + uip_setethaddr(macaddr); + uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); + uip_sethostaddr(ipaddr); + httpd_init(); + + while (TRUE) { + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h new file mode 100644 index 000000000..e0c6338fc --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _WEBTHREAD_H_ +#define _WEBTHREAD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + msg_t WebThread(void *p); + #ifdef __cplusplus +} +#endif + +#endif /* _WEBTHREAD_H_ */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile new file mode 100644 index 000000000..a0eaaffb7 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -0,0 +1,193 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC2148.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(TESTSRC) \ + ${BOARDPATH}/buzzer.c \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/ffconf.h b/demos/ARM7-LPC214x-FATFS-GCC/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h new file mode 100644 index 000000000..4614abe14 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c new file mode 100644 index 000000000..7b9edc9b6 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -0,0 +1,364 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "chprintf.h" +#include "evtimer.h" +#include "buzzer.h" + +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + /* The presence check is performed only while the driver is not in a + transfer state because it is often performed by changing the mode of + the pin connected to the CS/D3 contact of the card, this could disturb + the transfer.*/ + blkstate_t state = blkGetDriverState(bbdp); + chSysLockFromIsr(); + if ((state != BLK_READING) && (state != BLK_WRITING)) { + /* Safe to perform the check.*/ + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ +static SPIConfig hs_spicfg = { + NULL, + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 2 +}; + +/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0).*/ +static SPIConfig ls_spicfg = { + NULL, + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 254 +}; + +/* MMC/SD over SPI driver configuration.*/ +static MMCConfig mmccfg = {&SPID1, &ls_spicfg, &hs_spicfg}; + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + } + return 0; +} + +/* + * Yellow LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(200); + palSetPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(300); + } + return 0; +} + +/* + * Executed as event handler at 500mS intervals. + */ +static void TimerHandler(eventid_t id) { + + (void)id; + if (!palReadPad(IOPORT1, PA_BUTTON1)) { + if (fs_ready) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf((BaseSequentialStream *)&SD1, "FS: f_getfree() failed\r\n"); + return; + } + chprintf((BaseSequentialStream *)&SD1, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files((BaseSequentialStream *)&SD1, (char *)fbuff); + } + } + else if (!palReadPad(IOPORT1, PA_BUTTON2)) { + static WORKING_AREA(waTestThread, 256); + Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), + NORMALPRIO, TestThread, &SD1); + chThdWait(tp); + buzzPlay(500, MS2ST(100)); + } +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + buzzPlayWait(1000, MS2ST(100)); + buzzPlayWait(2000, MS2ST(100)); + chprintf((BaseSequentialStream *)&SD1, "MMC: inserted\r\n"); + /* + * On insertion MMC initialization and FS mount. + */ + chprintf((BaseSequentialStream *)&SD1, "MMC: initialization "); + if (mmcConnect(&MMCD1)) { + chprintf((BaseSequentialStream *)&SD1, "failed\r\n"); + return; + } + chprintf((BaseSequentialStream *)&SD1, "ok\r\n"); + chprintf((BaseSequentialStream *)&SD1, "FS: mount "); + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + chprintf((BaseSequentialStream *)&SD1, "failed\r\n"); + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; + chprintf((BaseSequentialStream *)&SD1, "ok\r\n"); + buzzPlay(440, MS2ST(200)); +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + chprintf((BaseSequentialStream *)&SD1, "MMC: removed\r\n"); + mmcDisconnect(&MMCD1); + fs_ready = FALSE; + buzzPlayWait(2000, MS2ST(100)); + buzzPlayWait(1000, MS2ST(100)); +} + +/* + * Application entry point. + */ +int main(void) { + static const evhandler_t evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler + }; + static EvTimer evt; + struct EventListener el0, el1, el2; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Buzzer driver initialization. + */ + buzzInit(); + + /* + * Initializes the MMC driver to work with SPI2. + */ + mmcObjectInit(&MMCD1); + mmcStart(&MMCD1, &mmccfg); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&MMCD1); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + chEvtRegister(&inserted_event, &el1, 1); + chEvtRegister(&removed_event, &el2, 2); + while (TRUE) + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + return 0; +} diff --git a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..62c9c28f0 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/ARM7-LPC214x-FATFS-GCC/readme.txt b/demos/ARM7-LPC214x-FATFS-GCC/readme.txt new file mode 100644 index 000000000..83abee7c6 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/readme.txt @@ -0,0 +1,19 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for LPC214x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. +By pressing button 1 a directory scan on the MMC slot is performed, by +pressing the button 2 the test suite is activated on serial port 1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile new file mode 100644 index 000000000..95a64eb8c --- /dev/null +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -0,0 +1,190 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti -fno-exceptions +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/cpp_wrappers/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC2148.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(CHCPPSRC) \ + main.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHCPPINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp new file mode 100644 index 000000000..ec6a323f7 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -0,0 +1,174 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.hpp" +#include "hal.h" +#include "test.h" + +#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) + +using namespace chibios_rt; + +/* + * LED blink sequences. + * NOTE: Sequences must always be terminated by a GOTO instruction. + * NOTE: The sequencer language could be easily improved but this is outside + * the scope of this demo. + */ +#define SLEEP 0 +#define GOTO 1 +#define STOP 2 +#define BITCLEAR 3 +#define BITSET 4 + +typedef struct { + uint8_t action; + uint32_t value; +} seqop_t; + +// Flashing sequence for LED1. +static const seqop_t LED1_sequence[] = +{ + {BITCLEAR, PAL_PORT_BIT(PA_LED1)}, + {SLEEP, 200}, + {BITSET, PAL_PORT_BIT(PA_LED1)}, + {SLEEP, 1800}, + {GOTO, 0} +}; + +// Flashing sequence for LED2. +static const seqop_t LED2_sequence[] = +{ + {SLEEP, 1000}, + {BITCLEAR, PAL_PORT_BIT(PA_LED2)}, + {SLEEP, 200}, + {BITSET, PAL_PORT_BIT(PA_LED2)}, + {SLEEP, 1800}, + {GOTO, 1} +}; + +// Flashing sequence for LED3. +static const seqop_t LED3_sequence[] = +{ + {BITCLEAR, PAL_PORT_BIT(PA_LEDUSB)}, + {SLEEP, 200}, + {BITSET, PAL_PORT_BIT(PA_LEDUSB)}, + {SLEEP, 300}, + {GOTO, 0} +}; + +/* + * Sequencer thread class. It can drive LEDs or other output pins. + * Any sequencer is just an instance of this class, all the details are + * totally encapsulated and hidden to the application level. + */ +class SequencerThread : public BaseStaticThread<128> { +private: + const seqop_t *base, *curr; // Thread local variables. + +protected: + virtual msg_t main(void) { + while (true) { + switch(curr->action) { + case SLEEP: + sleep(curr->value); + break; + case GOTO: + curr = &base[curr->value]; + continue; + case STOP: + return 0; + case BITCLEAR: + palClearPort(IOPORT1, curr->value); + break; + case BITSET: + palSetPort(IOPORT1, curr->value); + break; + } + curr++; + } + } + +public: + SequencerThread(const seqop_t *sequence) : BaseStaticThread<128>() { + + base = curr = sequence; + } +}; + +/* + * Tester thread class. This thread executes the test suite. + */ +class TesterThread : public BaseStaticThread<256> { + +protected: + virtual msg_t main(void) { + + setName("tester"); + + return TestThread(&SD2); + } + +public: + TesterThread(void) : BaseStaticThread<256>() { + } +}; + +static TesterThread tester; +static SequencerThread blinker1(LED1_sequence); +static SequencerThread blinker2(LED2_sequence); +static SequencerThread blinker3(LED3_sequence); + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + System::init(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Starts several instances of the SequencerThread class, each one operating + * on a different LED. + */ + blinker1.start(NORMALPRIO + 10); + blinker2.start(NORMALPRIO + 10); + blinker3.start(NORMALPRIO + 10); + + /* + * Serves timer events. + */ + while (true) { + if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { + tester.start(NORMALPRIO); + tester.wait(); + }; + BaseThread::sleep(MS2ST(500)); + } + return 0; +} diff --git a/demos/ARM7-LPC214x-G++/mcuconf.h b/demos/ARM7-LPC214x-G++/mcuconf.h new file mode 100644 index 000000000..62c9c28f0 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/ARM7-LPC214x-G++/readme.txt b/demos/ARM7-LPC214x-G++/readme.txt new file mode 100644 index 000000000..8f99ee1d7 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X using G++. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads implemented +as C++ classes. Pressing both buttons activates the test procedure on the +serial port 1. + +NOTE: the C++ GNU compiler can produce code sizes comparable to C if you + don't use RTTI and standard libraries, those are disabled by default + in the makefile. You can enable them if you have a lot of program space + available. It is possible to use a lot of C++ features without using + runtimes, just see the demo. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile new file mode 100644 index 000000000..6be46ea25 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -0,0 +1,187 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC2148.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c new file mode 100644 index 000000000..629b8e6a7 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + } + return 0; +} + +/* + * Yellow LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(200); + palSetPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(300); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * If a button is pressed during the reset then the blinking leds threads + * are not started in order to make accurate benchmarks. + */ + if ((palReadPort(IOPORT1) & BOTH_BUTTONS) == BOTH_BUTTONS) { + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + } + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the buttons state and run test procedure + * or print "Hello World!" on serial driver 1. + */ + while (TRUE) { + if (!palReadPad(IOPORT1, PA_BUTTON1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT1, PA_BUTTON2)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARM7-LPC214x-GCC/mcuconf.h b/demos/ARM7-LPC214x-GCC/mcuconf.h new file mode 100644 index 000000000..62c9c28f0 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/ARM7-LPC214x-GCC/readme.txt b/demos/ARM7-LPC214x-GCC/readme.txt new file mode 100644 index 000000000..32d036043 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. By pressing +the buttons on the board it is possible to send a message over the serial +port or activate the test procedure. +See main.c for details. Buzzer.c contains an interesting device driver +example that uses a physical timer for the waveform generation and a virtual +timer for the sound duration. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/.cproject b/demos/ARMCM0-LPC1114-LPCXPRESSO/.cproject new file mode 100644 index 000000000..66264587b --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/.cproject @@ -0,0 +1,257 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1114/301" property_count="5" version="1"/> +<infoList vendor="NXP"> +<info chip="LPC1114/301" match_id="0x0444102b" name="LPC1114/301" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC1114/301</name> +<family>LPC11xx</family> +<vendor>NXP</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash32" location="0" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x400" progwithcode="TRUE" size="0x8000"/> +<peripheralInstance derived_from="LPC11_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="CM0_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP0" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/.project b/demos/ARMCM0-LPC1114-LPCXPRESSO/.project new file mode 100644 index 000000000..5db67c6d2 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/.project @@ -0,0 +1,90 @@ + + + ARMCM0-LPC1114-LPCXPRESSO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + D:/Progetti/ChibiOS-RT/os + + + test + 2 + D:/Progetti/ChibiOS-RT/test + + + diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile new file mode 100644 index 000000000..9919f1519 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1114.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..87ff35a37 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.ewp b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.ewp new file mode 100644 index 000000000..b757f4985 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.ewp @@ -0,0 +1,2219 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.c + + + $PROJ_DIR$\..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\core_cm0.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\LPC11xx.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC11xx\system_LPC11xx.h + + + + port + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v6m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v6m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v6m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\LPC11xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\LPC11xx\vectors.s + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.eww b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.icf b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.icf new file mode 100644 index 000000000..a31967680 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x200; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj new file mode 100644 index 000000000..8b14cacee --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj @@ -0,0 +1,1010 @@ + + + + 1.1 + +

### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + LPC1114x301 + NXP (founded by Philips) + IRAM(0x10000000-0x10001FFF) IROM(0-0x7FFF) CLOCK(12000000) CPUTYPE("Cortex-M0") + + "STARTUP\NXP\LPC11xx\startup_LPC11xx.s" ("NXP LPC11xx Startup Code") + UL2CM3(-UV1742AOE -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) + 5063 + LPC11xx.h + + + + + + + + + + + 0 + + + + NXP\LPC11xx\ + NXP\LPC11xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMP1.DLL + -pLPC1114 + SARMCM3.DLL + + TARMP1.DLL + -pLPC1114 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 0 + 0x10002000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\LPC11xx;..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.c + + + board.h + 5 + ..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + chcore_v6m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v6m.c + + + chcore_v6m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v6m.h + + + chcoreasm_v6m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v6m.s + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\LPC11xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\LPC11xx\vectors.s + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + + + platform + + + core_cm0.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\core_cm0.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\hal_lld.h + + + LPC11xx.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\LPC11xx.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\pal_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\serial_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\serial_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\spi_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\spi_lld.h + + + system_LPC11xx.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\system_LPC11xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + mcuconf.h + 5 + ..\mcuconf.h + + + + + + + + diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/main.c b/demos/ARMCM0-LPC1114-LPCXPRESSO/main.c new file mode 100644 index 000000000..460fe8775 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/main.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ +static SPIConfig spicfg = { + NULL, + GPIO1, + GPIO1_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 48 +}; + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + } +} + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + uint8_t i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the SD1 and SPI1 drivers. + */ + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ + spiStart(&SPID1, &spicfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. + */ + i = 0; + while (TRUE) { + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + i = (i + 1) & 15; + } +} diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/mcuconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..425791688 --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/mcuconf.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC11xx_SYSPLL_MUL 4 +#define LPC11xx_SYSPLL_DIV 4 +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC11xx_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC11xx_GPT_USE_CT16B0 TRUE +#define LPC11xx_GPT_USE_CT16B1 TRUE +#define LPC11xx_GPT_USE_CT32B0 TRUE +#define LPC11xx_GPT_USE_CT32B1 TRUE +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC11xx_SERIAL_USE_UART0 TRUE +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC11xx_SPI_USE_SSP0 TRUE +#define LPC11xx_SPI_USE_SSP1 FALSE +#define LPC11xx_SPI_SSP0CLKDIV 1 +#define LPC11xx_SPI_SSP1CLKDIV 1 +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/.cproject b/demos/ARMCM0-LPC11U14-LPCXPRESSO/.cproject new file mode 100644 index 000000000..aa773f4d6 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/.cproject @@ -0,0 +1,272 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/.project b/demos/ARMCM0-LPC11U14-LPCXPRESSO/.project new file mode 100644 index 000000000..716dba200 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/.project @@ -0,0 +1,94 @@ + + + ARMCM0-LPC11U14-LPCXPRESSO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + D:/Progetti/ChibiOS-RT/boards/EA_LPCXPRESSO_BB_11U14 + + + os + 2 + D:/Progetti/ChibiOS-RT/os + + + test + 2 + D:/Progetti/ChibiOS-RT/test + + + diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile b/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile new file mode 100644 index 000000000..dc2aa318f --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_11U14/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11Uxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC11U14.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..87ff35a37 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c b/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c new file mode 100644 index 000000000..5ee1371b4 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ +static SPIConfig spicfg = { + NULL, + GPIO0, + GPIO0_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 48 +}; + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + } +} + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3G)); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + uint8_t i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the SD1 and SPI1 drivers. + */ + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ + spiStart(&SPID1, &spicfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. + */ + i = 0; + while (TRUE) { + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + i = (i + 1) & 15; + } +} diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..e35aadf7e --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h @@ -0,0 +1,66 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC11U14 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC_SYSPLL_MUL 4 +#define LPC_SYSPLL_DIV 4 +#define LPC_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC_GPT_USE_CT16B0 TRUE +#define LPC_GPT_USE_CT16B1 TRUE +#define LPC_GPT_USE_CT32B0 TRUE +#define LPC_GPT_USE_CT32B1 TRUE +#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC_SERIAL_USE_UART0 TRUE +#define LPC_SERIAL_FIFO_PRELOAD 16 +#define LPC_SERIAL_UART0CLKDIV 1 +#define LPC_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC_SPI_USE_SSP0 TRUE +#define LPC_SPI_USE_SSP1 FALSE +#define LPC_SPI_SSP0CLKDIV 1 +#define LPC_SPI_SSP1CLKDIV 1 +#define LPC_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/.cproject b/demos/ARMCM0-STM32F051-DISCOVERY/.cproject new file mode 100644 index 000000000..a5d58c50a --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/.project b/demos/ARMCM0-STM32F051-DISCOVERY/.project new file mode 100644 index 000000000..0a02ef68b --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/.project @@ -0,0 +1,43 @@ + + + ARMCM0-STM32F051-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/Makefile b/demos/ARMCM0-STM32F051-DISCOVERY/Makefile new file mode 100644 index 000000000..808327ae4 --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/chconf.h b/demos/ARMCM0-STM32F051-DISCOVERY/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/halconf.h b/demos/ARMCM0-STM32F051-DISCOVERY/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/main.c b/demos/ARMCM0-STM32F051-DISCOVERY/main.c new file mode 100644 index 000000000..c20ca0429 --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/main.c @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Blue LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(500); + } +} + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA9 and PA10 are routed to USART1. + */ + sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */ + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h b/demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..11c71ebc8 --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/demos/ARMCM0-STM32F051-DISCOVERY/readme.txt b/demos/ARMCM0-STM32F051-DISCOVERY/readme.txt new file mode 100644 index 000000000..4672d786c --- /dev/null +++ b/demos/ARMCM0-STM32F051-DISCOVERY/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M0 STM32F051. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F0-Discovery board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile b/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile new file mode 100644 index 000000000..37d897ddf --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Os -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_LPC812/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC8xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC8xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC812.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC812 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..d91a792b4 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py b/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py new file mode 100755 index 000000000..13f976bf9 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py @@ -0,0 +1,141 @@ +#!/usr/bin/env python +import serial +import array + +#========================================================= +PORT = '/dev/ttyUSB1' +FILE = 'build/ch.bin' + +RAM_ADDR = 0x10000300 +PAGE_SIZE = 0x40 +SECTOR_SIZE = 0x400 +FLASH_SIZE = 0x4000 + +#========================================================= +ser = serial.Serial( PORT, 115200, timeout=1) + +data = array.array('B') +f = file( FILE, 'rb') +try: + data.fromfile(f, FLASH_SIZE) +except: + pass +f.close() + +## pad out to next whole page +data.fromstring( chr(0xff)*(PAGE_SIZE - (data.buffer_info()[1]%PAGE_SIZE)) ) + +#========================================================= +## fix-up LPC boot checksum +csum = 0; +for i in range(7): + csum = csum + \ + (data[(i*4)] ) + \ + (data[(i*4)+1]<<8 ) + \ + (data[(i*4)+2]<<16) + \ + (data[(i*4)+3]<<24); \ + +csum = -csum +data[28] = csum & 0xff +data[29] = csum>>8 & 0xff +data[30] = csum>>16 & 0xff +data[31] = csum>>24 & 0xff + +#========================================================= +## +ser.write('?') +resp = ser.readline() +if resp.strip() <> 'Synchronized': + print 'No Response "?"' + exit(1) + +ser.write('Synchronized\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> 'OK': + print 'Not Synchronized' + exit(1) + +ser.write('12000\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> 'OK': + print 'No Response "12000"' + exit(1) + +ser.write('A 0\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "A"', resp + exit(1) + +ser.write('J\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "J"', resp + exit(1) +resp = ser.readline() +print 'Device ID: ', hex(int(resp)) + +ser.write('U 23130\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "U"', resp + exit(1) + + +## Erase whole device +ser.write('P 0 7\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + +ser.write('E 0 7\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + + +#========================================================= +address = 0 + +while data.buffer_info()[1]: + + ser.write( "W %d %d\r\n"%(RAM_ADDR, PAGE_SIZE) ) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "W"', resp + exit(1) + + for i in range(PAGE_SIZE): + ser.write( chr(data.pop(0)) ) + + #print('P %x %x\r\n'%( address/SECTOR_SIZE, address/SECTOR_SIZE )) + #print('C %x %x 0xff\r\n'%( address, RAM_ADDR )) + + ## Program page + ser.write('P %d %d\r\n'%( address/SECTOR_SIZE, address/SECTOR_SIZE )) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + + ser.write( 'C %d %d %d\r\n'%(address, RAM_ADDR, PAGE_SIZE) ) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "C"', resp + exit(1) + + print '.', + address = address + PAGE_SIZE + if (address%SECTOR_SIZE) == 0: + print '' + +#========================================================= +#========================================================= + + + diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c b/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c new file mode 100644 index 000000000..49d657d78 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); + +static msg_t Thread1(void *arg) { + (void)arg; + chRegSetThreadName("blinker"); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + + while (TRUE) { + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_RED)); + chThdSleepMilliseconds(500); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_RED)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_BLUE)); + chThdSleepMilliseconds(500); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_BLUE)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + chThdSleepMilliseconds(500); + } + + return 0; +} + +int main(void){ + + halInit(); + chSysInit(); + + sdStart(&SD1, NULL); /* Default: 9600,8,N,1. */ + + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO, Thread1, NULL); + + chnWrite( &SD1, (const uint8_t *)"\nhello\n", 8 ); + + do { + chThdSleepMilliseconds(500); + } while (TRUE); + + return 0; +} + diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..d5b1abe95 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC812 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ + +/* Default: Run PLL @24MHz from 12MHz IRC + #define LPC8xx_PLLCLK_SOURCE SYSPLLCLKSEL_IRCOSC + #define LPC8xx_SYSPLL_MUL 4 + #define LPC8xx_SYSPLL_DIV 4 + #define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT + #define LPC8xx_SYSABHCLK_DIV 1 +*/ + +/*run directly from internal 12M osc...*/ +#define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_IRCOSC + +/* + * GPT driver system settings. + */ +/* Defaults: + #define LPC8xx_GPT_USE_MRT0 TRUE + #define LPC8xx_GPT_USE_MRT1 FALSE + #define LPC8xx_GPT_USE_MRT2 FALSE + #define LPC8xx_GPT_USE_MRT3 FALSE + #define LPC8xx_GPT_MRT_IRQ_PRIORITY 2 +*/ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +/* Defaults: + #define LPC8xx_SERIAL_USE_UART0 TRUE + #define LPC8xx_SERIAL_USE_UART1 FALSE + #define LPC8xx_SERIAL_USE_UART2 FALSE + #define LPC8xx_SERIAL_UART0_IRQ_PRIORITY 3 + #define LPC8xx_SERIAL_UART1_IRQ_PRIORITY 3 + #define LPC8xx_SERIAL_UART2_IRQ_PRIORITY 3 + + #define LPC8xx_SERIAL_U_PCLK 11059200 + #define LPC8xx_SERIAL_UARTCLKDIV !!Calculated!! + #define LPC8xx_SERIAL_UARTFRGMUL !!Calculated!! + #define LPC8xx_SERIAL_UARTFRGDIV !!Calculated!! +*/ + +/* change default baudrate to 9600 */ +#define SERIAL_DEFAULT_BITRATE 9600 + + diff --git a/demos/ARMCM3-GENERIC-KERNEL/Makefile b/demos/ARMCM3-GENERIC-KERNEL/Makefile new file mode 100644 index 000000000..01f24f597 --- /dev/null +++ b/demos/ARMCM3-GENERIC-KERNEL/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTM32F10X_MD + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-GENERIC-KERNEL/chconf.h b/demos/ARMCM3-GENERIC-KERNEL/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-GENERIC-KERNEL/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-GENERIC-KERNEL/main.c b/demos/ARMCM3-GENERIC-KERNEL/main.c new file mode 100644 index 000000000..f5b6cd6ff --- /dev/null +++ b/demos/ARMCM3-GENERIC-KERNEL/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" + +#if !defined(SYSTEM_CLOCK) +#define SYSTEM_CLOCK 8000000 +#endif + +static uint32_t seconds_counter; +static uint32_t minutes_counter; + +/* + * This is a periodic thread that does absolutely nothing except increasing + * the seconds counter. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(1000); + seconds_counter++; + } +} + +/* + * Application entry point. + */ +int main(void) { + + /** + * Hardware initialization, in this simple demo just the systick timer is + * initialized. + */ + STBase->RVR = SYSTEM_CLOCK / CH_FREQUENCY - 1; + STBase->CVR = 0; + STBase->CSR = CLKSOURCE_CORE_BITS | ENABLE_ON_BITS | TICKINT_ENABLED_BITS; + + /* + * System initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + chSysInit(); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * increasing the minutes counter. + */ + while (TRUE) { + chThdSleepSeconds(60); + minutes_counter++; + } +} diff --git a/demos/ARMCM3-GENERIC-KERNEL/readme.txt b/demos/ARMCM3-GENERIC-KERNEL/readme.txt new file mode 100644 index 000000000..0c13627af --- /dev/null +++ b/demos/ARMCM3-GENERIC-KERNEL/readme.txt @@ -0,0 +1,14 @@ +***************************************************************************** +** ChibiOS/RT demo for generict ARM Cortex-M3 processor, kernel only. ** +***************************************************************************** + +** TARGET ** + +The demo runs on any ARM Cortex-M3 processor after changing few constants +in main.c, the defaults are setup for an STM32F1xx. + +** Build Procedure ** + +The demo has been tested by using the free CodeSourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject b/demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject new file mode 100644 index 000000000..a3ce652f0 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject @@ -0,0 +1,258 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1343" property_count="5" version="1"/> +<infoList vendor="NXP"> +<info chip="LPC1343" match_id="0x3d00002b" name="LPC1343" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC1343</name> +<family>LPC13xx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash32" location="0x00000000" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x8000"/> +<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> +<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_USBDEV" determined="infoFile" id="USB" location="0x40020000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +</chip> +<processor> +<name gcc_name="cortex-m3">Cortex-M3</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/.project b/demos/ARMCM3-LPC1343-LPCXPRESSO/.project new file mode 100644 index 000000000..824ecbf3a --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/.project @@ -0,0 +1,90 @@ + + + ARMCM3-LPC1343-LPCXPRESSO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + D:/Progetti/ChibiOS-RT/os + + + test + 2 + D:/Progetti/ChibiOS-RT/test + + + diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile new file mode 100644 index 000000000..9b6daf3c0 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1343/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC13xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1343.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1348 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..87ff35a37 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.ewp b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.ewp new file mode 100644 index 000000000..34617d457 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.ewp @@ -0,0 +1,2222 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\EA_LPCXPRESSO_BB_1343\board.c + + + $PROJ_DIR$\..\..\..\boards\EA_LPCXPRESSO_BB_1343\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\core_cm3.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\LPC13xx.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\LPC13xx\system_LPC13xx.h + + + + port + + LPC13xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\LPC13xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\LPC13xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.eww b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.icf b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.icf new file mode 100644 index 000000000..a31967680 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x200; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/keil/ch.uvproj b/demos/ARMCM3-LPC1343-LPCXPRESSO/keil/ch.uvproj new file mode 100644 index 000000000..175779e8e --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/keil/ch.uvproj @@ -0,0 +1,1005 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + LPC1343 + NXP (founded by Philips) + IRAM(0x10000000-0x10001FFF) IROM(0-0x7FFF) CLOCK(12000000) CPUTYPE("Cortex-M3") + + "STARTUP\NXP\LPC13xx\startup_LPC13xx.s" ("NXP LPC13xx Startup Code") + UL2CM3(-UV0446D8E -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) + 4919 + LPC13xx.h + + + + + + + + + + + 0 + + + + NXP\LPC13xx\ + NXP\LPC13xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMP1.DLL + -pLPC1343 + SARMCM3.DLL + + TARMP1.DLL + -pLPC1343 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 0 + 0x10002000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\LPC13xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\LPC13xx;..\..\..\boards\EA_LPCXPRESSO_BB_1343;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\EA_LPCXPRESSO_BB_1343;..\..\..\os\ports\RVCT\ARMCMx\LPC13xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\EA_LPCXPRESSO_BB_1343\board.c + + + board.h + 5 + ..\..\..\boards\EA_LPCXPRESSO_BB_1343\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\LPC13xx\vectors.s + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + + + platform + + + core_cm3.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\core_cm3.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC13xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\hal_lld.h + + + LPC13xx.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\LPC13xx.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC13xx\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\pal_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\LPC13xx\serial_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\serial_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\LPC13xx\spi_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\spi_lld.h + + + system_LPC13xx.h + 5 + ..\..\..\os\hal\platforms\LPC13xx\system_LPC13xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + mcuconf.h + 5 + ..\mcuconf.h + + + + + + + + diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/main.c b/demos/ARMCM3-LPC1343-LPCXPRESSO/main.c new file mode 100644 index 000000000..cf5d3b96a --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/main.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ +static SPIConfig spicfg = { + NULL, + GPIO1, + GPIO1_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 72 +}; + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + } +} + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + uint8_t i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the SD1 and SPI1 drivers. + */ + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ + spiStart(&SPID1, &spicfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. + */ + i = 0; + while (TRUE) { + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + i = (i + 1) & 15; + } +} diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/mcuconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..e0c8ee453 --- /dev/null +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/mcuconf.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC13xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC13xx_SYSPLL_MUL 6 +#define LPC13xx_SYSPLL_DIV 4 +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC13xx_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC13xx_GPT_USE_CT16B0 TRUE +#define LPC13xx_GPT_USE_CT16B1 TRUE +#define LPC13xx_GPT_USE_CT32B0 TRUE +#define LPC13xx_GPT_USE_CT32B1 TRUE +#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC13xx_SERIAL_USE_UART0 TRUE +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC13xx_SPI_USE_SSP0 TRUE +#define LPC13xx_SPI_USE_SSP1 FALSE +#define LPC13xx_SPI_SSP0CLKDIV 1 +#define LPC13xx_SPI_SSP1CLKDIV 1 +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#define LPC13xx_SPI_SSP1_IRQ_PRIORITY 5 +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 diff --git a/demos/ARMCM3-LPC1343-OLIMEX/.cproject b/demos/ARMCM3-LPC1343-OLIMEX/.cproject new file mode 100644 index 000000000..03577398b --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-LPC1343-OLIMEX/.project b/demos/ARMCM3-LPC1343-OLIMEX/.project new file mode 100644 index 000000000..c75cadaae --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/.project @@ -0,0 +1,85 @@ + + + ARMCM3-LPC1343-OLIMEX + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + D:/Progetti/ChibiOS-RT/os + + + diff --git a/demos/ARMCM3-LPC1343-OLIMEX/Makefile b/demos/ARMCM3-LPC1343-OLIMEX/Makefile new file mode 100644 index 000000000..c87f797bd --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P1343/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC13xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1343.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1348 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-LPC1343-OLIMEX/chconf.h b/demos/ARMCM3-LPC1343-OLIMEX/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-OLIMEX/halconf.h b/demos/ARMCM3-LPC1343-OLIMEX/halconf.h new file mode 100644 index 000000000..41ccd60f5 --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-OLIMEX/main.c b/demos/ARMCM3-LPC1343-OLIMEX/main.c new file mode 100644 index 000000000..6cdaf6dcf --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/main.c @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * LED blinker1 thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIO3, GPIO3_LED1); + chThdSleepMilliseconds(500); + palSetPad(GPIO3, GPIO3_LED1); + chThdSleepMilliseconds(500); + } +} + +/* + * LED blinker2 thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPad(GPIO3, GPIO3_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO3, GPIO3_LED2); + chThdSleepMilliseconds(480); + } +} + +/* + * LED scanlight thread, times are in milliseconds. + */ +static WORKING_AREA(waThread3, 128); +static msg_t Thread3(void *arg) { + + (void)arg; + chRegSetThreadName("scanner1"); + palSetPort(GPIO2, PAL_PORT_BIT(GPIO2_LED5) | + PAL_PORT_BIT(GPIO2_LED6) | + PAL_PORT_BIT(GPIO2_LED7) | + PAL_PORT_BIT(GPIO2_LED8)); + while (TRUE) { + palClearPort( GPIO2, PAL_PORT_BIT(GPIO2_LED5)); + chThdSleepMilliseconds(50); + palSetPort( GPIO2, PAL_PORT_BIT(GPIO2_LED8)); + chThdSleepMilliseconds(150); + palClearPort( GPIO2, PAL_PORT_BIT(GPIO2_LED6)); + chThdSleepMilliseconds(50); + palSetPort( GPIO2, PAL_PORT_BIT(GPIO2_LED5)); + chThdSleepMilliseconds(150); + palClearPort( GPIO2, PAL_PORT_BIT(GPIO2_LED7)); + chThdSleepMilliseconds(50); + palSetPort( GPIO2, PAL_PORT_BIT(GPIO2_LED6)); + chThdSleepMilliseconds(150); + palClearPort( GPIO2, PAL_PORT_BIT(GPIO2_LED8)); + chThdSleepMilliseconds(50); + palSetPort( GPIO2, PAL_PORT_BIT(GPIO2_LED7)); + chThdSleepMilliseconds(150); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Creates the LED threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + chThdCreateStatic(waThread3, sizeof(waThread3), NORMALPRIO, Thread3, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-LPC1343-OLIMEX/mcuconf.h b/demos/ARMCM3-LPC1343-OLIMEX/mcuconf.h new file mode 100644 index 000000000..0ebe52258 --- /dev/null +++ b/demos/ARMCM3-LPC1343-OLIMEX/mcuconf.h @@ -0,0 +1,76 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC13xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC13xx_SYSPLL_MUL 6 +#define LPC13xx_SYSPLL_DIV 4 +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC13xx_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC13xx_GPT_USE_CT16B0 TRUE +#define LPC13xx_GPT_USE_CT16B1 TRUE +#define LPC13xx_GPT_USE_CT32B0 TRUE +#define LPC13xx_GPT_USE_CT32B1 TRUE +#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC13xx_SERIAL_USE_UART0 TRUE +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC13xx_SPI_USE_SSP0 TRUE +#define LPC13xx_SPI_SSP0CLKDIV 1 +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/.cproject b/demos/ARMCM3-STM32F100-DISCOVERY/.cproject new file mode 100644 index 000000000..4398edd6e --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/.project b/demos/ARMCM3-STM32F100-DISCOVERY/.project new file mode 100644 index 000000000..778be5cc4 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/.project @@ -0,0 +1,43 @@ + + + ARMCM3-STM32F100-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32VL_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile new file mode 100644 index 000000000..a9a5aa9ef --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32VL_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F100xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h new file mode 100644 index 000000000..7cbe2994a --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp new file mode 100644 index 000000000..ee3c8c26f --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp @@ -0,0 +1,2309 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32VL_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32VL_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\adc_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h + + + + port + + STM32F1xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.eww b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf new file mode 100644 index 000000000..fe1ac2c14 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..b544d5410 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,1135 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F100RB + STMicroelectronics + IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x\startup_stm32f10x_md_vl.s" ("STM32 Medium density Value Line Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + 5086 + stm32f10x.h + + + + + + + + + + SFD\ST\STM32F100x\STM32F100.sfr + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x20002000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\hal\platforms\STM32\USBv1;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32VL_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32VL_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + vectors.s + 2 + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + usb.c + 1 + ..\..\..\os\hal\src\usb.c + + + ext.c + 1 + ..\..\..\os\hal\src\ext.c + + + gpt.c + 1 + ..\..\..\os\hal\src\gpt.c + + + icu.c + 1 + ..\..\..\os\hal\src\icu.c + + + rtc.c + 1 + ..\..\..\os\hal\src\rtc.c + + + sdc.c + 1 + ..\..\..\os\hal\src\sdc.c + + + serial_usb.c + 1 + ..\..\..\os\hal\src\serial_usb.c + + + tm.c + 1 + ..\..\..\os\hal\src\tm.c + + + usb_cdc.h + 5 + ..\..\..\os\hal\include\usb_cdc.h + + + ext.h + 5 + ..\..\..\os\hal\include\ext.h + + + gpt.h + 5 + ..\..\..\os\hal\include\gpt.h + + + icu.h + 5 + ..\..\..\os\hal\include\icu.h + + + rtc.h + 5 + ..\..\..\os\hal\include\rtc.h + + + sdc.h + 5 + ..\..\..\os\hal\include\sdc.h + + + serial_usb.h + 5 + ..\..\..\os\hal\include\serial_usb.h + + + tm.h + 5 + ..\..\..\os\hal\include\tm.h + + + usb.h + 5 + ..\..\..\os\hal\include\usb.h + + + + + platform + + + adc_lld.c + 1 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\adc_lld.c + + + can_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\can_lld.c + + + hal_lld.c + 1 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.c + + + pal_lld.c + 1 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + uart_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\uart_lld.c + + + adc_lld.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\adc_lld.h + + + can_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\can_lld.h + + + hal_lld.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.h + + + hal_lld_f103.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + pal_lld.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + stm32f10x.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\stm32f10x.h + + + uart_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\uart_lld.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/main.c b/demos/ARMCM3-STM32F100-DISCOVERY/main.c new file mode 100644 index 000000000..2fe5596a9 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/main.c @@ -0,0 +1,235 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10 (41.5 cycles sample time) + * Sensor (239.5 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, + ADC_CR2_TSVREFE, + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + /* HW dependent part.*/ + 0, +#if STM32_PWM_USE_ADVANCED + 0 +#endif +}; + +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + /* HW dependent part.*/ + GPIOA, + GPIOA_SPI1NSS, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD3, 2, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD3, 3, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID1); + spiStartSendI(&SPID1, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} + +/* + * This is a periodic thread that does absolutely nothing except increasing + * a seconds counter. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; + + (void)arg; + chRegSetThreadName("counter"); + while (TRUE) { + chThdSleepMilliseconds(1000); + seconds_counter++; + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + + /* + * Initializes the SPI driver 1. + */ + spiStart(&SPID1, &spicfg); + + /* + * Initializes the ADC driver 1. + * The pin PC0 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, NULL); + palSetGroupMode(GPIOC, PAL_PORT_BIT(0), 0, PAL_MODE_INPUT_ANALOG); + + /* + * Initializes the PWM driver 3, re-routes the TIM3 outputs, programs the + * pins as alternate functions. + * Note, the AFIO access routes the TIM3 output pins on the PC6...PC9 + * where the LEDs are connected. + */ + pwmStart(&PWMD3, &pwmcfg); + AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_0 | AFIO_MAPR_TIM3_REMAP_1; + palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4), + 0, + PAL_MODE_STM32_ALTERNATE_PUSHPULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..f122b8625 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h @@ -0,0 +1,176 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F100_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_ADCPRE STM32_ADCPRE_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/readme.txt b/demos/ARMCM3-STM32F100-DISCOVERY/readme.txt new file mode 100644 index 000000000..acd92f66a --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32VL-Discovery board. + +** The Demo ** + +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +the PWM using the sampled values. The sample data is also transmitted using +the SPI port 1. +By pressing the button located on the board the test procedure is activated +with output on the serial port COM1 (USART1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103-FATFS/.cproject b/demos/ARMCM3-STM32F103-FATFS/.cproject new file mode 100644 index 000000000..e1326e7be --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103-FATFS/.project b/demos/ARMCM3-STM32F103-FATFS/.project new file mode 100644 index 000000000..b02fd30a2 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/.project @@ -0,0 +1,48 @@ + + + ARMCM3-STM32F103-FATFS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P103 + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F103-FATFS/Makefile b/demos/ARMCM3-STM32F103-FATFS/Makefile new file mode 100644 index 000000000..7c23eee44 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/Makefile @@ -0,0 +1,213 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103-FATFS/chconf.h b/demos/ARMCM3-STM32F103-FATFS/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS/ffconf.h b/demos/ARMCM3-STM32F103-FATFS/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARMCM3-STM32F103-FATFS/halconf.h b/demos/ARMCM3-STM32F103-FATFS/halconf.h new file mode 100644 index 000000000..cfe71717e --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS/main.c b/demos/ARMCM3-STM32F103-FATFS/main.c new file mode 100644 index 000000000..0ee436218 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/main.c @@ -0,0 +1,388 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "evtimer.h" +#include "chprintf.h" + +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + /* The presence check is performed only while the driver is not in a + transfer state because it is often performed by changing the mode of + the pin connected to the CS/D3 contact of the card, this could disturb + the transfer.*/ + blkstate_t state = blkGetDriverState(bbdp); + chSysLockFromIsr(); + if ((state != BLK_READING) && (state != BLK_WRITING)) { + /* Safe to perform the check.*/ + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0}; + +/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, + SPI_CR1_BR_2 | SPI_CR1_BR_1}; + +/* MMC/SD over SPI driver configuration.*/ +static MMCConfig mmccfg = {&SPID2, &ls_spicfg, &hs_spicfg}; + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: tree\r\n"); + return; + } + if (!fs_ready) { + chprintf(chp, "File System not mounted\r\n"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf(chp, "FS: f_getfree() failed\r\n"); + return; + } + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files(chp, (char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palTogglePad(IOPORT3, GPIOC_LED); + if (fs_ready) + chThdSleepMilliseconds(200); + else + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) { + return; + } + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + mmcDisconnect(&MMCD1); + fs_ready = FALSE; +} + +/* + * Application entry point. + */ +int main(void) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the MMC driver to work with SPI2. + */ + palSetPadMode(IOPORT2, GPIOB_SPI2NSS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT2, GPIOB_SPI2NSS); + mmcObjectInit(&MMCD1); + mmcStart(&MMCD1, &mmccfg); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&MMCD1); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&inserted_event, &el0, 0); + chEvtRegister(&removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500))); + } + return 0; +} diff --git a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h new file mode 100644 index 000000000..c4619422d --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/demos/ARMCM3-STM32F103-FATFS/readme.txt b/demos/ARMCM3-STM32F103-FATFS/readme.txt new file mode 100644 index 000000000..4178478bb --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/readme.txt @@ -0,0 +1,33 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LED using a thread and monitors the MMC slot for +a card insertion. When a card is inserted then the file system is mounted +and the LED flashes faster. +A command line shell is spawned on SD2, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103-G++/.cproject b/demos/ARMCM3-STM32F103-G++/.cproject new file mode 100644 index 000000000..bbb50b1d8 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103-G++/.project b/demos/ARMCM3-STM32F103-G++/.project new file mode 100644 index 000000000..252cbf296 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/.project @@ -0,0 +1,44 @@ + + + ARMCM3-STM32F103-G++ + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P103 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F103-G++/Makefile b/demos/ARMCM3-STM32F103-G++/Makefile new file mode 100644 index 000000000..f7a72b5d6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/Makefile @@ -0,0 +1,211 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti -fno-exceptions +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/cpp_wrappers/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(CHCPPSRC) \ + main.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHCPPINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +#LD = $(TRGT)gcc +LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103-G++/chconf.h b/demos/ARMCM3-STM32F103-G++/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-G++/halconf.h b/demos/ARMCM3-STM32F103-G++/halconf.h new file mode 100644 index 000000000..dce372010 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-G++/main.cpp b/demos/ARMCM3-STM32F103-G++/main.cpp new file mode 100644 index 000000000..59ff88986 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/main.cpp @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.hpp" +#include "hal.h" +#include "test.h" + +using namespace chibios_rt; + +/* + * LED blink sequences. + * NOTE: Sequences must always be terminated by a GOTO instruction. + * NOTE: The sequencer language could be easily improved but this is outside + * the scope of this demo. + */ +#define SLEEP 0 +#define GOTO 1 +#define STOP 2 +#define BITCLEAR 3 +#define BITSET 4 + +typedef struct { + uint8_t action; + uint32_t value; +} seqop_t; + +// Flashing sequence for LED1. +static const seqop_t LED1_sequence[] = +{ + {BITCLEAR, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 200}, + {BITSET, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 800}, + {BITCLEAR, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 400}, + {BITSET, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 600}, + {BITCLEAR, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 600}, + {BITSET, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 400}, + {BITCLEAR, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 800}, + {BITSET, PAL_PORT_BIT(GPIOC_LED)}, + {SLEEP, 200}, + {GOTO, 0} +}; + +/* + * Sequencer thread class. It can drive LEDs or other output pins. + * Any sequencer is just an instance of this class, all the details are + * totally encapsulated and hidden to the application level. + */ +class SequencerThread : public BaseStaticThread<128> { +private: + const seqop_t *base, *curr; // Thread local variables. + +protected: + virtual msg_t main(void) { + while (true) { + switch(curr->action) { + case SLEEP: + sleep(curr->value); + break; + case GOTO: + curr = &base[curr->value]; + continue; + case STOP: + return 0; + case BITCLEAR: + palClearPort(GPIOC, curr->value); + break; + case BITSET: + palSetPort(GPIOC, curr->value); + break; + } + curr++; + } + } + +public: + SequencerThread(const seqop_t *sequence) : BaseStaticThread<128>() { + + base = curr = sequence; + } +}; + +/* + * Tester thread class. This thread executes the test suite. + */ +class TesterThread : public BaseStaticThread<256> { + +protected: + virtual msg_t main(void) { + + setName("tester"); + + return TestThread(&SD2); + } + +public: + TesterThread(void) : BaseStaticThread<256>() { + } +}; + +/* Static threads instances.*/ +static TesterThread tester; +static SequencerThread blinker1(LED1_sequence); + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + System::init(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Starts several instances of the SequencerThread class, each one operating + * on a different LED. + */ + blinker1.start(NORMALPRIO + 10); + + /* + * Serves timer events. + */ + while (true) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + tester.start(NORMALPRIO); + tester.wait(); + }; + BaseThread::sleep(MS2ST(500)); + } + + return 0; +} diff --git a/demos/ARMCM3-STM32F103-G++/mcuconf.h b/demos/ARMCM3-STM32F103-G++/mcuconf.h new file mode 100644 index 000000000..b506af317 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/demos/ARMCM3-STM32F103-G++/readme.txt b/demos/ARMCM3-STM32F103-G++/readme.txt new file mode 100644 index 000000000..e4ff86156 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +SD2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103/.cproject b/demos/ARMCM3-STM32F103/.cproject new file mode 100644 index 000000000..3eb8aa88c --- /dev/null +++ b/demos/ARMCM3-STM32F103/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103/.project b/demos/ARMCM3-STM32F103/.project new file mode 100644 index 000000000..35116e95f --- /dev/null +++ b/demos/ARMCM3-STM32F103/.project @@ -0,0 +1,95 @@ + + + ARMCM3-STM32F103 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P103 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F103/Makefile b/demos/ARMCM3-STM32F103/Makefile new file mode 100644 index 000000000..854a84a03 --- /dev/null +++ b/demos/ARMCM3-STM32F103/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103/chconf.h b/demos/ARMCM3-STM32F103/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F103/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103/codeblocks/ch.cbp b/demos/ARMCM3-STM32F103/codeblocks/ch.cbp new file mode 100644 index 000000000..3de4549fb --- /dev/null +++ b/demos/ARMCM3-STM32F103/codeblocks/ch.cbp @@ -0,0 +1,387 @@ + + + + + + diff --git a/demos/ARMCM3-STM32F103/codeblocks/ch.workspace b/demos/ARMCM3-STM32F103/codeblocks/ch.workspace new file mode 100644 index 000000000..bee5a82f6 --- /dev/null +++ b/demos/ARMCM3-STM32F103/codeblocks/ch.workspace @@ -0,0 +1,6 @@ + + + + + + diff --git a/demos/ARMCM3-STM32F103/halconf.h b/demos/ARMCM3-STM32F103/halconf.h new file mode 100644 index 000000000..dce372010 --- /dev/null +++ b/demos/ARMCM3-STM32F103/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103/iar/ch.ewp b/demos/ARMCM3-STM32F103/iar/ch.ewp new file mode 100644 index 000000000..e7749ed75 --- /dev/null +++ b/demos/ARMCM3-STM32F103/iar/ch.ewp @@ -0,0 +1,2291 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\OLIMEX_STM32_P103\board.c + + + $PROJ_DIR$\..\..\..\boards\OLIMEX_STM32_P103\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h + + + + port + + STM32F1xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F103/iar/ch.eww b/demos/ARMCM3-STM32F103/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F103/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F103/iar/ch.icf b/demos/ARMCM3-STM32F103/iar/ch.icf new file mode 100644 index 000000000..67ef6e73a --- /dev/null +++ b/demos/ARMCM3-STM32F103/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-STM32F103/keil/ch.uvproj b/demos/ARMCM3-STM32F103/keil/ch.uvproj new file mode 100644 index 000000000..cb2f755e0 --- /dev/null +++ b/demos/ARMCM3-STM32F103/keil/ch.uvproj @@ -0,0 +1,1075 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F103RB + STMicroelectronics + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + 4231 + stm32f10x_lib.h + + + + + + + + + + + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x20005000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\hal\platforms\STM32\USBv1;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\OLIMEX_STM32_P103\board.c + + + board.h + 5 + ..\..\..\boards\OLIMEX_STM32_P103\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + vectors.s + 2 + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + ext.c + 1 + ..\..\..\os\hal\src\ext.c + + + gpt.c + 1 + ..\..\..\os\hal\src\gpt.c + + + icu.c + 1 + ..\..\..\os\hal\src\icu.c + + + rtc.c + 1 + ..\..\..\os\hal\src\rtc.c + + + sdc.c + 1 + ..\..\..\os\hal\src\sdc.c + + + serial_usb.c + 1 + ..\..\..\os\hal\src\serial_usb.c + + + usb.c + 1 + ..\..\..\os\hal\src\usb.c + + + ext.h + 5 + ..\..\..\os\hal\include\ext.h + + + gpt.h + 5 + ..\..\..\os\hal\include\gpt.h + + + icu.h + 5 + ..\..\..\os\hal\include\icu.h + + + rtc.h + 5 + ..\..\..\os\hal\include\rtc.h + + + sdc.h + 5 + ..\..\..\os\hal\include\sdc.h + + + serial_usb.h + 5 + ..\..\..\os\hal\include\serial_usb.h + + + usb.h + 5 + ..\..\..\os\hal\include\usb.h + + + usb_cdc.h + 5 + ..\..\..\os\hal\include\usb_cdc.h + + + tm.h + 5 + ..\..\..\os\hal\include\tm.h + + + tm.c + 1 + ..\..\..\os\hal\src\tm.c + + + + + platform + + + hal_lld.c + 1 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.c + + + pal_lld.c + 1 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + hal_lld.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.h + + + hal_lld_f103.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + pal_lld.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + stm32f10x.h + 5 + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\stm32f10x.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + mcuconf.h + 5 + ..\mcuconf.h + + + + + + + + diff --git a/demos/ARMCM3-STM32F103/main.c b/demos/ARMCM3-STM32F103/main.c new file mode 100644 index 000000000..e77256713 --- /dev/null +++ b/demos/ARMCM3-STM32F103/main.c @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F103/mcuconf.h b/demos/ARMCM3-STM32F103/mcuconf.h new file mode 100644 index 000000000..b506af317 --- /dev/null +++ b/demos/ARMCM3-STM32F103/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/demos/ARMCM3-STM32F103/readme.txt b/demos/ARMCM3-STM32F103/readme.txt new file mode 100644 index 000000000..e4ff86156 --- /dev/null +++ b/demos/ARMCM3-STM32F103/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +SD2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103/ride7/ch.rapp b/demos/ARMCM3-STM32F103/ride7/ch.rapp new file mode 100644 index 000000000..f0aec5e6d --- /dev/null +++ b/demos/ARMCM3-STM32F103/ride7/ch.rapp @@ -0,0 +1,172 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + \ No newline at end of file diff --git a/demos/ARMCM3-STM32F103/ride7/ch.rprj b/demos/ARMCM3-STM32F103/ride7/ch.rprj new file mode 100644 index 000000000..d9f866c84 --- /dev/null +++ b/demos/ARMCM3-STM32F103/ride7/ch.rprj @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/.cproject b/demos/ARMCM3-STM32F103ZG-FATFS/.cproject new file mode 100644 index 000000000..09c606434 --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/.project b/demos/ARMCM3-STM32F103ZG-FATFS/.project new file mode 100644 index 000000000..00c982681 --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/.project @@ -0,0 +1,48 @@ + + + ARMCM3-STM32F103ZG-FATFS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM3210E_EVAL + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/Makefile b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile new file mode 100644 index 000000000..f258f4faf --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile @@ -0,0 +1,214 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM3210E_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/ffconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h new file mode 100644 index 000000000..3f22f8d9c --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/main.c b/demos/ARMCM3-STM32F103ZG-FATFS/main.c new file mode 100644 index 000000000..ee8420dd9 --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/main.c @@ -0,0 +1,365 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "evtimer.h" +#include "chprintf.h" + +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + chSysLockFromIsr(); + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +/** + * @brief FS object. + */ +FATFS SDC_FS; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: tree\r\n"); + return; + } + if (!fs_ready) { + chprintf(chp, "File System not mounted\r\n"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf(chp, "FS: f_getfree() failed\r\n"); + return; + } + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)SDC_FS.csize, + clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files(chp, (char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * SD card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion SDC initialization and FS mount. + */ + if (sdcConnect(&SDCD1)) + return; + + err = f_mount(0, &SDC_FS); + if (err != FR_OK) { + sdcDisconnect(&SDCD1); + return; + } + fs_ready = TRUE; +} + +/* + * SD card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + sdcDisconnect(&SDCD1); + fs_ready = FALSE; +} + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOF, GPIOF_LED4); + palSetPad(GPIOF, GPIOF_LED1); + chThdSleepMilliseconds(250); + palClearPad(GPIOF, GPIOF_LED1); + palSetPad(GPIOF, GPIOF_LED2); + chThdSleepMilliseconds(250); + palClearPad(GPIOF, GPIOF_LED2); + palSetPad(GPIOF, GPIOF_LED3); + chThdSleepMilliseconds(250); + palClearPad(GPIOF, GPIOF_LED3); + palSetPad(GPIOF, GPIOF_LED4); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 and SDC driver 1 using default + * configuration. + */ + sdStart(&SD1, NULL); + sdcStart(&SDCD1, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&SDCD1); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&inserted_event, &el0, 0); + chEvtRegister(&removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500))); + } +} diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h new file mode 100644 index 000000000..e5f050b7d --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/readme.txt b/demos/ARMCM3-STM32F103ZG-FATFS/readme.txt new file mode 100644 index 000000000..188810c72 --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103ZG. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STM3210E-EVAL board. + +** The Demo ** + +The demo flashes the board LEDs using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +SD1 (USART1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F107-FATFS/.cproject b/demos/ARMCM3-STM32F107-FATFS/.cproject new file mode 100644 index 000000000..5e99ce93d --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F107-FATFS/.project b/demos/ARMCM3-STM32F107-FATFS/.project new file mode 100644 index 000000000..684f00f8b --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/.project @@ -0,0 +1,48 @@ + + + ARMCM3-STM32F107-FATFS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P107 + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F107-FATFS/Makefile b/demos/ARMCM3-STM32F107-FATFS/Makefile new file mode 100644 index 000000000..79a34326c --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/Makefile @@ -0,0 +1,212 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform_f105_f107.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F107xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F107-FATFS/chconf.h b/demos/ARMCM3-STM32F107-FATFS/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-FATFS/ffconf.h b/demos/ARMCM3-STM32F107-FATFS/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARMCM3-STM32F107-FATFS/halconf.h b/demos/ARMCM3-STM32F107-FATFS/halconf.h new file mode 100644 index 000000000..cfe71717e --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-FATFS/main.c b/demos/ARMCM3-STM32F107-FATFS/main.c new file mode 100644 index 000000000..15e51c4a0 --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/main.c @@ -0,0 +1,375 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "evtimer.h" +#include "chprintf.h" + +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + chSysLockFromIsr(); + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig hs_spicfg = {NULL, GPIOA, GPIOA_SPI3_CS_MMC, 0}; + +/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig ls_spicfg = {NULL, GPIOA, GPIOA_SPI3_CS_MMC, + SPI_CR1_BR_2 | SPI_CR1_BR_1}; + +/* MMC/SD over SPI driver configuration.*/ +static MMCConfig mmccfg = {&SPID3, &ls_spicfg, &hs_spicfg}; + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: tree\r\n"); + return; + } + if (!fs_ready) { + chprintf(chp, "File System not mounted\r\n"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf(chp, "FS: f_getfree() failed\r\n"); + return; + } + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files(chp, (char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD3, + commands +}; + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palTogglePad(IOPORT3, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(fs_ready ? 125 : 500); + } + return 0; +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) { + return; + } + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + mmcDisconnect(&MMCD1); + fs_ready = FALSE; +} + +/* + * Application entry point. + */ +int main(void) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 3 using the driver default configuration. + */ + sdStart(&SD3, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the MMC driver to work with SPI2. + */ + mmcObjectInit(&MMCD1); + mmcStart(&MMCD1, &mmccfg); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&MMCD1); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&inserted_event, &el0, 0); + chEvtRegister(&removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } + return 0; +} diff --git a/demos/ARMCM3-STM32F107-FATFS/mcuconf.h b/demos/ARMCM3-STM32F107-FATFS/mcuconf.h new file mode 100644 index 000000000..90d9e43dd --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/mcuconf.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F107 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F107_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_PLL3MUL_VALUE 10 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_OTG_CLOCK_REQUIRED TRUE +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#define STM32_I2S_CLOCK_REQUIRED FALSE +#define STM32_MCOSEL STM32_MCOSEL_PLL3 +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM3-STM32F107-FATFS/readme.txt b/demos/ARMCM3-STM32F107-FATFS/readme.txt new file mode 100644 index 000000000..bf9d03077 --- /dev/null +++ b/demos/ARMCM3-STM32F107-FATFS/readme.txt @@ -0,0 +1,33 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P107 board. + +** The Demo ** + +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LED using a thread and monitors the MMC slot for +a card insertion. When a card is inserted then the file system is mounted +and the LED flashes faster. +A command line shell is spawned on SD3, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F107-LWIP/.cproject b/demos/ARMCM3-STM32F107-LWIP/.cproject new file mode 100644 index 000000000..e04c80ba4 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F107-LWIP/.project b/demos/ARMCM3-STM32F107-LWIP/.project new file mode 100644 index 000000000..c73c5f2f4 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/.project @@ -0,0 +1,48 @@ + + + ARMCM3-STM32F107-LWIP + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P107 + + + lwip + 2 + CHIBIOS/ext/lwip + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F107-LWIP/Makefile b/demos/ARMCM3-STM32F107-LWIP/Makefile new file mode 100644 index 000000000..1f2572313 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/Makefile @@ -0,0 +1,210 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform_f105_f107.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F107xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LWSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + web/web.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F107-LWIP/chconf.h b/demos/ARMCM3-STM32F107-LWIP/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-LWIP/halconf.h b/demos/ARMCM3-STM32F107-LWIP/halconf.h new file mode 100644 index 000000000..43fddb60e --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-LWIP/lwipopts.h b/demos/ARMCM3-STM32F107-LWIP/lwipopts.h new file mode 100644 index 000000000..5a8e51970 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/lwipopts.h @@ -0,0 +1,2127 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/ARMCM3-STM32F107-LWIP/main.c b/demos/ARMCM3-STM32F107-LWIP/main.c new file mode 100644 index 000000000..3f34554a1 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/main.c @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "lwipthread.h" + +#include "web/web.h" + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 3 using the driver default configuration. + */ + sdStart(&SD3, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Creates the LWIP threads (it changes priority internally). + */ + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, + lwip_thread, NULL); + + /* + * Creates the HTTP thread (it changes priority internally). + */ + chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, + http_server, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0) + TestThread(&SD3); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F107-LWIP/mcuconf.h b/demos/ARMCM3-STM32F107-LWIP/mcuconf.h new file mode 100644 index 000000000..c2ae45d14 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/mcuconf.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F107 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F107_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_PLL3MUL_VALUE 10 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_OTG_CLOCK_REQUIRED TRUE +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#define STM32_I2S_CLOCK_REQUIRED FALSE +#define STM32_MCOSEL STM32_MCOSEL_PLL3 +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM3-STM32F107-LWIP/readme.txt b/demos/ARMCM3-STM32F107-LWIP/readme.txt new file mode 100644 index 000000000..25d6c13f6 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P107 board. + +** The Demo ** + +The demo currently just flashes a LED using a thread and serves HTTP requests +at address 192.168.1.20 on port 80. +The button activates che ChibiOS/RT test suite, output on SD3. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F107-LWIP/web/web.c b/demos/ARMCM3-STM32F107-LWIP/web/web.c new file mode 100644 index 000000000..c4f16852e --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/web/web.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file is a modified version of the lwIP web server demo. The original + * author is unknown because the file didn't contain any license information. + */ + +/** + * @file web.c + * @brief HTTP server wrapper thread code. + * @addtogroup WEB_THREAD + * @{ + */ + +#include "ch.h" + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" + +#include "web.h" + +#if LWIP_NETCONN + +static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; + +static void http_server_serve(struct netconn *conn) { + struct netbuf *inbuf; + char *buf; + u16_t buflen; + err_t err; + + /* Read the data from the port, blocking if nothing yet there. + We assume the request (the part we care about) is in one netbuf */ + err = netconn_recv(conn, &inbuf); + + if (err == ERR_OK) { + netbuf_data(inbuf, (void **)&buf, &buflen); + + /* Is this an HTTP GET command? (only check the first 5 chars, since + there are other formats for GET, and we're keeping it very simple )*/ + if (buflen>=5 && + buf[0]=='G' && + buf[1]=='E' && + buf[2]=='T' && + buf[3]==' ' && + buf[4]=='/' ) { + + /* Send the HTML header + * subtract 1 from the size, since we dont send the \0 in the string + * NETCONN_NOCOPY: our data is const static, so no need to copy it + */ + netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); + + /* Send our HTML page */ + netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); + } + } + /* Close the connection (server closes in HTTP) */ + netconn_close(conn); + + /* Delete the buffer (netconn_recv gives us ownership, + so we have to make sure to deallocate the buffer) */ + netbuf_delete(inbuf); +} + +/** + * Stack area for the http thread. + */ +WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +/** + * HTTP server thread. + */ +msg_t http_server(void *p) { + struct netconn *conn, *newconn; + err_t err; + + (void)p; + + /* Create a new TCP connection handle */ + conn = netconn_new(NETCONN_TCP); + LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); + + /* Bind to port 80 (HTTP) with default IP address */ + netconn_bind(conn, NULL, WEB_THREAD_PORT); + + /* Put the connection into LISTEN state */ + netconn_listen(conn); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(WEB_THREAD_PRIORITY); + + while(1) { + err = netconn_accept(conn, &newconn); + if (err != ERR_OK) + continue; + http_server_serve(newconn); + netconn_delete(newconn); + } + return RDY_OK; +} + +#endif /* LWIP_NETCONN */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-LWIP/web/web.h b/demos/ARMCM3-STM32F107-LWIP/web/web.h new file mode 100644 index 000000000..1dc8b6675 --- /dev/null +++ b/demos/ARMCM3-STM32F107-LWIP/web/web.h @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file web.h + * @brief HTTP server wrapper thread macros and structures. + * @addtogroup WEB_THREAD + * @{ + */ + +#ifndef _WEB_H_ +#define _WEB_H_ + +#ifndef WEB_THREAD_STACK_SIZE +#define WEB_THREAD_STACK_SIZE 1024 +#endif + +#ifndef WEB_THREAD_PORT +#define WEB_THREAD_PORT 80 +#endif + +#ifndef WEB_THREAD_PRIORITY +#define WEB_THREAD_PRIORITY (LOWPRIO + 2) +#endif + +extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t http_server(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _WEB_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107/.cproject b/demos/ARMCM3-STM32F107/.cproject new file mode 100644 index 000000000..447f8acf4 --- /dev/null +++ b/demos/ARMCM3-STM32F107/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F107/.project b/demos/ARMCM3-STM32F107/.project new file mode 100644 index 000000000..e0d22eca8 --- /dev/null +++ b/demos/ARMCM3-STM32F107/.project @@ -0,0 +1,43 @@ + + + ARMCM3-STM32F107 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P107 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32F107/Makefile b/demos/ARMCM3-STM32F107/Makefile new file mode 100644 index 000000000..4d5d48b63 --- /dev/null +++ b/demos/ARMCM3-STM32F107/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform_f105_f107.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F107xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F107/chconf.h b/demos/ARMCM3-STM32F107/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32F107/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107/halconf.h b/demos/ARMCM3-STM32F107/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARMCM3-STM32F107/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107/iar/ch.ewp b/demos/ARMCM3-STM32F107/iar/ch.ewp new file mode 100644 index 000000000..1f528f08a --- /dev/null +++ b/demos/ARMCM3-STM32F107/iar/ch.ewp @@ -0,0 +1,2309 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\OLIMEX_STM32_P107\board.c + + + $PROJ_DIR$\..\..\..\boards\OLIMEX_STM32_P107\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2s.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\io_block.h + + + $PROJ_DIR$\..\..\..\os\hal\include\io_channel.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmcsd.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2s.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmcsd.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h + + + + port + + STM32F1xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F107/iar/ch.eww b/demos/ARMCM3-STM32F107/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F107/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F107/iar/ch.icf b/demos/ARMCM3-STM32F107/iar/ch.icf new file mode 100644 index 000000000..44efbcba3 --- /dev/null +++ b/demos/ARMCM3-STM32F107/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0802FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-STM32F107/keil/ch.uvproj b/demos/ARMCM3-STM32F107/keil/ch.uvproj new file mode 100644 index 000000000..999e635d2 --- /dev/null +++ b/demos/ARMCM3-STM32F107/keil/ch.uvproj @@ -0,0 +1,1090 @@ + + + + 1.1 + +

### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F107VC + STMicroelectronics + IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000) + 4889 + stm32f10x_lib.h + + + + + + + + + + SFD\ST\STM32F107x\STM32F107.sfr + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F107VC + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F107VC + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x20010000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\various;..\..\..\boards\OLIMEX_STM32_P107;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\OLIMEX_STM32_P107;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\OLIMEX_STM32_P107\board.c + + + board.h + 5 + ..\..\..\boards\OLIMEX_STM32_P107\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + vectors.s + 2 + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + gpt.c + 1 + ..\..\..\os\hal\src\gpt.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + serial_usb.c + 1 + ..\..\..\os\hal\src\serial_usb.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + usb.c + 1 + ..\..\..\os\hal\src\usb.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + gpt.h + 5 + ..\..\..\os\hal\include\gpt.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + serial_usb.h + 5 + ..\..\..\os\hal\include\serial_usb.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + usb.h + 5 + ..\..\..\os\hal\include\usb.h + + + ext.h + 5 + ..\..\..\os\hal\include\ext.h + + + icu.h + 5 + ..\..\..\os\hal\include\icu.h + + + rtc.h + 5 + ..\..\..\os\hal\include\rtc.h + + + sdc.h + 5 + ..\..\..\os\hal\include\sdc.h + + + usb_cdc.h + 5 + ..\..\..\os\hal\include\usb_cdc.h + + + ext.c + 1 + ..\..\..\os\hal\src\ext.c + + + icu.c + 1 + ..\..\..\os\hal\src\icu.c + + + rtc.c + 1 + ..\..\..\os\hal\src\rtc.c + + + sdc.c + 1 + ..\..\..\os\hal\src\sdc.c + + + + + platform + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c + + + stm32f10x.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h + + + hal_lld_f100.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h + + + hal_lld_f103.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h + + + hal_lld_f105_f107.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h + + + stm32_rcc.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + mcuconf.h + 5 + ..\mcuconf.h + + + + + + + + diff --git a/demos/ARMCM3-STM32F107/main.c b/demos/ARMCM3-STM32F107/main.c new file mode 100644 index 000000000..84e2e95b7 --- /dev/null +++ b/demos/ARMCM3-STM32F107/main.c @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 3 using the driver default configuration. + */ + sdStart(&SD3, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0) + TestThread(&SD3); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F107/mcuconf.h b/demos/ARMCM3-STM32F107/mcuconf.h new file mode 100644 index 000000000..c2ae45d14 --- /dev/null +++ b/demos/ARMCM3-STM32F107/mcuconf.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F107 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F107_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_PLL3MUL_VALUE 10 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_OTG_CLOCK_REQUIRED TRUE +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#define STM32_I2S_CLOCK_REQUIRED FALSE +#define STM32_MCOSEL STM32_MCOSEL_PLL3 +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM3-STM32F107/readme.txt b/demos/ARMCM3-STM32F107/readme.txt new file mode 100644 index 000000000..cce940bd6 --- /dev/null +++ b/demos/ARMCM3-STM32F107/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P107 board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +SD3 (USART3). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/.cproject b/demos/ARMCM3-STM32L152-DISCOVERY/.cproject new file mode 100644 index 000000000..30af73e1e --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/.project b/demos/ARMCM3-STM32L152-DISCOVERY/.project new file mode 100644 index 000000000..a1f6875a8 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/.project @@ -0,0 +1,43 @@ + + + ARMCM3-STM32L152-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/Makefile b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile new file mode 100644 index 000000000..dc82a2f04 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h new file mode 100644 index 000000000..7cbe2994a --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp new file mode 100644 index 000000000..f97a68345 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp @@ -0,0 +1,2297 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32L_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32L_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\adc_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h + + + + port + + STM32Lxx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32L1xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32L1xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.eww b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.icf b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.icf new file mode 100644 index 000000000..376fd3e5d --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj b/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..7f2ef1bf9 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,975 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32L152RB + STMicroelectronics + IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code") + ULP2CM3(-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000) + 5248 + stm32l1xx.h + + + + + + + + + + SFD\ST\STM32L15x\STM32L15x.sfr + 0 + + + + ST\STM32L1xx\ + ST\STM32L1xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x20004000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\hal\platforms\STM32L1xx;..\..\..\boards\ST_STM32L_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32L_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\vectors.s + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + usb.c + 1 + ..\..\..\os\hal\src\usb.c + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + ext.c + 1 + ..\..\..\os\hal\src\ext.c + + + gpt.c + 1 + ..\..\..\os\hal\src\gpt.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + icu.c + 1 + ..\..\..\os\hal\src\icu.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + rtc.c + 1 + ..\..\..\os\hal\src\rtc.c + + + sdc.c + 1 + ..\..\..\os\hal\src\sdc.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + serial_usb.c + 1 + ..\..\..\os\hal\src\serial_usb.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + tm.c + 1 + ..\..\..\os\hal\src\tm.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + + + platform + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + mac_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\mac_lld.c + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c new file mode 100644 index 000000000..12e810a22 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -0,0 +1,246 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10 (48 cycles sample time) + * Sensor (192 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + 0, + 0, + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 1 and 2 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + /* HW dependent part.*/ + GPIOB, + 12, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} + +/* + * This is a periodic thread that does absolutely nothing except increasing + * a seconds counter. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; + + (void)arg; + chRegSetThreadName("counter"); + while (TRUE) { + chThdSleepMilliseconds(1000); + seconds_counter++; + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA9 and PA10 are routed to USART1. + */ + sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ + spiStart(&SPID2, &spicfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the ADC driver 1 and enable the thermal sensor. + * The pin PC0 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); + palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..188b543eb --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -0,0 +1,170 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt new file mode 100644 index 000000000..7d8d1b0ac --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32L152. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32L-Discovery board. + +** The Demo ** + +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +the PWM using the sampled values. The sample data is also transmitted using +the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15). +By pressing the button located on the board the test procedure is activated +with output on the serial port COM1 (USART1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-SAM4L/ARMCM4-SAM4L.7z b/demos/ARMCM4-SAM4L/ARMCM4-SAM4L.7z new file mode 100644 index 000000000..e52980390 Binary files /dev/null and b/demos/ARMCM4-SAM4L/ARMCM4-SAM4L.7z differ diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/.cproject b/demos/ARMCM4-STM32F303-DISCOVERY/.cproject new file mode 100644 index 000000000..22d0ba952 --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/.project b/demos/ARMCM4-STM32F303-DISCOVERY/.project new file mode 100644 index 000000000..5e8664b65 --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/.project @@ -0,0 +1,43 @@ + + + ARMCM4-STM32F303-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/Makefile b/demos/ARMCM4-STM32F303-DISCOVERY/Makefile new file mode 100644 index 000000000..0a5b2300e --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/chconf.h b/demos/ARMCM4-STM32F303-DISCOVERY/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/main.c b/demos/ARMCM4-STM32F303-DISCOVERY/main.c new file mode 100644 index 000000000..a72c1a72c --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/main.c @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing LEDs. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED3_RED); + palSetPad(GPIOE, GPIOE_LED5_ORANGE); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED5_ORANGE); + palSetPad(GPIOE, GPIOE_LED7_GREEN); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED7_GREEN); + palSetPad(GPIOE, GPIOE_LED9_BLUE); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED9_BLUE); + palSetPad(GPIOE, GPIOE_LED10_RED); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED10_RED); + palSetPad(GPIOE, GPIOE_LED8_ORANGE); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED8_ORANGE); + palSetPad(GPIOE, GPIOE_LED6_GREEN); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED6_GREEN); + palSetPad(GPIOE, GPIOE_LED4_BLUE); + chThdSleepMilliseconds(125); + palClearPad(GPIOE, GPIOE_LED4_BLUE); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA9(TX) and PA10(RX) are routed to USART1. + */ + sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..b661ca71e --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/readme.txt b/demos/ARMCM4-STM32F303-DISCOVERY/readme.txt new file mode 100644 index 000000000..0bad189d3 --- /dev/null +++ b/demos/ARMCM4-STM32F303-DISCOVERY/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F303. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F3-Discovery board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/.cproject b/demos/ARMCM4-STM32F373-STM32373C_EVAL/.cproject new file mode 100644 index 000000000..062591261 --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/.project b/demos/ARMCM4-STM32F373-STM32373C_EVAL/.project new file mode 100644 index 000000000..d2d67cf3e --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/.project @@ -0,0 +1,43 @@ + + + ARMCM4-STM32F373-STM32373C_EVAL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/Makefile b/demos/ARMCM4-STM32F373-STM32373C_EVAL/Makefile new file mode 100644 index 000000000..3d26f0169 --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/chconf.h b/demos/ARMCM4-STM32F373-STM32373C_EVAL/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/halconf.h b/demos/ARMCM4-STM32F373-STM32373C_EVAL/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/main.c b/demos/ARMCM4-STM32F373-STM32373C_EVAL/main.c new file mode 100644 index 000000000..71df36c02 --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/main.c @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing LEDs. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED1); + palClearPad(GPIOC, GPIOC_LED2); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED2); + palClearPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED3); + palClearPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED4); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the default configuration, pins + * are pre-configured in board.h. + */ + sdStart(&SD2, NULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/mcuconf.h b/demos/ARMCM4-STM32F373-STM32373C_EVAL/mcuconf.h new file mode 100644 index 000000000..1434b2fae --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM4-STM32F373-STM32373C_EVAL/readme.txt b/demos/ARMCM4-STM32F373-STM32373C_EVAL/readme.txt new file mode 100644 index 000000000..b46265e30 --- /dev/null +++ b/demos/ARMCM4-STM32F373-STM32373C_EVAL/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F373. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/.cproject b/demos/ARMCM4-STM32F407-DISCOVERY-G++/.cproject new file mode 100644 index 000000000..c01cf00c2 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/.project b/demos/ARMCM4-STM32F407-DISCOVERY-G++/.project new file mode 100644 index 000000000..7b9854ea9 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/.project @@ -0,0 +1,100 @@ + + + ARMCM4-STM32F407-DISCOVERY-G++ + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/Makefile b/demos/ARMCM4-STM32F407-DISCOVERY-G++/Makefile new file mode 100644 index 000000000..cd5388514 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/Makefile @@ -0,0 +1,224 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti -fno-exceptions +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/cpp_wrappers/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(CHCPPSRC) \ + $(CHIBIOS)/os/fs/fatfs/fatfs_fsimpl.cpp \ + main.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHCPPINC) \ + $(CHIBIOS)/os/various $(CHIBIOS)/os/fs $(CHIBIOS)/os/fs/fatfs + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/chconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-G++/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-G++/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/main.cpp b/demos/ARMCM4-STM32F407-DISCOVERY-G++/main.cpp new file mode 100644 index 000000000..53825dbdb --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/main.cpp @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.hpp" +#include "hal.h" +#include "fs.hpp" +#include "fatfs_fsimpl.hpp" +#include "test.h" + +using namespace chibios_rt; +using namespace chibios_fatfs; + +/* + * LED blink sequences. + * NOTE: Sequences must always be terminated by a GOTO instruction. + * NOTE: The sequencer language could be easily improved but this is outside + * the scope of this demo. + */ +#define SLEEP 0 +#define GOTO 1 +#define STOP 2 +#define BITCLEAR 3 +#define BITSET 4 + +typedef struct { + uint8_t action; + uint32_t value; +} seqop_t; + +// Flashing sequence for LED3. +static const seqop_t LED3_sequence[] = +{ + {BITSET, PAL_PORT_BIT(GPIOD_LED3)}, + {SLEEP, 800}, + {BITCLEAR, PAL_PORT_BIT(GPIOD_LED3)}, + {SLEEP, 200}, + {GOTO, 0} +}; + +// Flashing sequence for LED4. +static const seqop_t LED4_sequence[] = +{ + {BITSET, PAL_PORT_BIT(GPIOD_LED4)}, + {SLEEP, 600}, + {BITCLEAR, PAL_PORT_BIT(GPIOD_LED4)}, + {SLEEP, 400}, + {GOTO, 0} +}; + +// Flashing sequence for LED5. +static const seqop_t LED5_sequence[] = +{ + {BITSET, PAL_PORT_BIT(GPIOD_LED5)}, + {SLEEP, 400}, + {BITCLEAR, PAL_PORT_BIT(GPIOD_LED5)}, + {SLEEP, 600}, + {GOTO, 0} +}; + +// Flashing sequence for LED6. +static const seqop_t LED6_sequence[] = +{ + {BITSET, PAL_PORT_BIT(GPIOD_LED6)}, + {SLEEP, 200}, + {BITCLEAR, PAL_PORT_BIT(GPIOD_LED6)}, + {SLEEP, 800}, + {GOTO, 0} +}; + +/* + * Sequencer thread class. It can drive LEDs or other output pins. + * Any sequencer is just an instance of this class, all the details are + * totally encapsulated and hidden to the application level. + */ +class SequencerThread : public BaseStaticThread<128> { +private: + const seqop_t *base, *curr; // Thread local variables. + +protected: + virtual msg_t main(void) { + + setName("sequencer"); + + while (true) { + switch(curr->action) { + case SLEEP: + sleep(curr->value); + break; + case GOTO: + curr = &base[curr->value]; + continue; + case STOP: + return 0; + case BITCLEAR: + palClearPort(GPIOD, curr->value); + break; + case BITSET: + palSetPort(GPIOD, curr->value); + break; + } + curr++; + } + } + +public: + SequencerThread(const seqop_t *sequence) : BaseStaticThread<128>() { + + base = curr = sequence; + } +}; + +/* + * Tester thread class. This thread executes the test suite. + */ +class TesterThread : public BaseStaticThread<256> { + +protected: + virtual msg_t main(void) { + + setName("tester"); + + return TestThread(&SD2); + } + +public: + TesterThread(void) : BaseStaticThread<256>() { + } +}; + +/* Static threads instances.*/ +static TesterThread tester; +static SequencerThread blinker1(LED3_sequence); +static SequencerThread blinker2(LED4_sequence); +static SequencerThread blinker3(LED5_sequence); +static SequencerThread blinker4(LED6_sequence); + +static FatFSWrapper fs; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + System::init(); + + fs.mount(); + fs.unmount(); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART2. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * Starts several instances of the SequencerThread class, each one operating + * on a different LED. + */ + blinker1.start(NORMALPRIO + 10); + blinker2.start(NORMALPRIO + 10); + blinker3.start(NORMALPRIO + 10); + blinker4.start(NORMALPRIO + 10); + + /* + * Serves timer events. + */ + while (true) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + tester.start(NORMALPRIO); + tester.wait(); + }; + BaseThread::sleep(MS2ST(500)); + } + + return 0; +} diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-G++/mcuconf.h new file mode 100644 index 000000000..a8d51babe --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-G++/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY-G++/readme.txt new file mode 100644 index 000000000..940e07382 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-G++/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use PWM and SPI drivers using synchronous APIs. The PWM +driver the four board LEDs with the data read from the LIS320DL accelerometer. +The data is also transmitted on the SPI2 port. +A simple command shell is activated on virtual serial port SD2 via USB-CDC +driver (use micro-USB plug on STM32F4-Discovery board). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.cproject b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.cproject new file mode 100644 index 000000000..4c0ec4132 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.project b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.project new file mode 100644 index 000000000..20074f5a7 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/.project @@ -0,0 +1,95 @@ + + + ARMCM4-STM32F407-DISCOVERY-MEMS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/Makefile b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/Makefile new file mode 100644 index 000000000..1ed33ade1 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/Makefile @@ -0,0 +1,225 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/devices_lib/accel/lis302dl.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + usbcfg.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/chconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/halconf.h new file mode 100644 index 000000000..5351803c1 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/main.c b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/main.c new file mode 100644 index 000000000..77bf7196b --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/main.c @@ -0,0 +1,325 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "chprintf.h" +#include "shell.h" +#include "lis302dl.h" + +#include "usbcfg.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Accelerometer related. */ +/*===========================================================================*/ + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 1 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static const PWMConfig pwmcfg = { + 100000, /* 100kHz PWM clock frequency. */ + 128, /* PWM period is 128 cycles. */ + NULL, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI1 configuration structure. + * Speed 5.25MHz, CPHA=1, CPOL=1, 8bits frames, MSb transmitted first. + * The slave select line is the pin GPIOE_CS_SPI on the port GPIOE. + */ +static const SPIConfig spi1cfg = { + NULL, + /* HW dependent part.*/ + GPIOE, + GPIOE_CS_SPI, + SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_CPOL | SPI_CR1_CPHA +}; + +/* + * SPI2 configuration structure. + * Speed 21MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first. + * The slave select line is the pin 12 on the port GPIOA. + */ +static const SPIConfig spi2cfg = { + NULL, + /* HW dependent part.*/ + GPIOB, + 12, + 0 +}; + +/* + * This is a periodic thread that reads accelerometer and outputs + * result to SPI2 and PWM. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + static int8_t xbuf[4], ybuf[4]; /* Last accelerometer data.*/ + systime_t time; /* Next deadline.*/ + + (void)arg; + chRegSetThreadName("reader"); + + /* LIS302DL initialization.*/ + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG1, 0x43); + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG2, 0x00); + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG3, 0x00); + + /* Reader thread loop.*/ + time = chTimeNow(); + while (TRUE) { + int32_t x, y; + unsigned i; + + /* Keeping an history of the latest four accelerometer readings.*/ + for (i = 3; i > 0; i--) { + xbuf[i] = xbuf[i - 1]; + ybuf[i] = ybuf[i - 1]; + } + + /* Reading MEMS accelerometer X and Y registers.*/ + xbuf[0] = (int8_t)lis302dlReadRegister(&SPID1, LIS302DL_OUTX); + ybuf[0] = (int8_t)lis302dlReadRegister(&SPID1, LIS302DL_OUTY); + + /* Transmitting accelerometer the data over SPI2.*/ + spiSelect(&SPID2); + spiSend(&SPID2, 4, xbuf); + spiSend(&SPID2, 4, ybuf); + spiUnselect(&SPID2); + + /* Calculating average of the latest four accelerometer readings.*/ + x = ((int32_t)xbuf[0] + (int32_t)xbuf[1] + + (int32_t)xbuf[2] + (int32_t)xbuf[3]) / 4; + y = ((int32_t)ybuf[0] + (int32_t)ybuf[1] + + (int32_t)ybuf[2] + (int32_t)ybuf[3]) / 4; + + /* Reprogramming the four PWM channels using the accelerometer data.*/ + if (y < 0) { + pwmEnableChannel(&PWMD4, 0, (pwmcnt_t)-y); + pwmEnableChannel(&PWMD4, 2, (pwmcnt_t)0); + } + else { + pwmEnableChannel(&PWMD4, 2, (pwmcnt_t)y); + pwmEnableChannel(&PWMD4, 0, (pwmcnt_t)0); + } + if (x < 0) { + pwmEnableChannel(&PWMD4, 1, (pwmcnt_t)-x); + pwmEnableChannel(&PWMD4, 3, (pwmcnt_t)0); + } + else { + pwmEnableChannel(&PWMD4, 3, (pwmcnt_t)x); + pwmEnableChannel(&PWMD4, 1, (pwmcnt_t)0); + } + + /* Waiting until the next 250 milliseconds time interval.*/ + chThdSleepUntil(time += MS2ST(100)); + } +} + +/*===========================================================================*/ +/* Initialization and main thread. */ +/*===========================================================================*/ + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART2. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * Initializes the SPI driver 1 in order to access the MEMS. The signals + * are already initialized in the board file. + */ + spiStart(&SPID1, &spi1cfg); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ + spiStart(&SPID2, &spi2cfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOD, GPIOD_LED4, PAL_MODE_ALTERNATE(2)); /* Green. */ + palSetPadMode(GPIOD, GPIOD_LED3, PAL_MODE_ALTERNATE(2)); /* Orange. */ + palSetPadMode(GPIOD, GPIOD_LED5, PAL_MODE_ALTERNATE(2)); /* Red. */ + palSetPadMode(GPIOD, GPIOD_LED6, PAL_MODE_ALTERNATE(2)); /* Blue. */ + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO + 10, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it just performs + * a shell respawn upon its termination. + */ + while (TRUE) { + if (!shelltp) { + if (SDU1.config->usbp->state == USB_ACTIVE) { + /* Spawns a new shell.*/ + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + } + } + else { + /* If the previous shell exited.*/ + if (chThdTerminated(shelltp)) { + /* Recovers memory of the previous shell.*/ + chThdRelease(shelltp); + shelltp = NULL; + } + } + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h new file mode 100644 index 000000000..dc6e2b241 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/readme.txt new file mode 100644 index 000000000..940e07382 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use PWM and SPI drivers using synchronous APIs. The PWM +driver the four board LEDs with the data read from the LIS320DL accelerometer. +The data is also transmitted on the SPI2 port. +A simple command shell is activated on virtual serial port SD2 via USB-CDC +driver (use micro-USB plug on STM32F4-Discovery board). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.c b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.c new file mode 100644 index 000000000..24955b881 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.c @@ -0,0 +1,314 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.h b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.h new file mode 100644 index 000000000..63015738c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/usbcfg.h @@ -0,0 +1,25 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _USBCFG_H_ +#define _USBCFG_H_ + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; + +#endif /* _USBCFG_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/.cproject b/demos/ARMCM4-STM32F407-DISCOVERY/.cproject new file mode 100644 index 000000000..8f117a33f --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/.cproject @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/.project b/demos/ARMCM4-STM32F407-DISCOVERY/.project new file mode 100644 index 000000000..910df5683 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/.project @@ -0,0 +1,95 @@ + + + ARMCM4-STM32F407-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/Makefile b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile new file mode 100644 index 000000000..95fe53ba6 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile @@ -0,0 +1,224 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/devices_lib/accel/lis302dl.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h new file mode 100644 index 000000000..8d3f4a793 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp new file mode 100644 index 000000000..55e090426 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp @@ -0,0 +1,2318 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + various + + devices_lib + + accel + + $PROJ_DIR$\..\..\..\os\various\devices_lib\accel\lis302dl.c + + + $PROJ_DIR$\..\..\..\os\various\devices_lib\accel\lis302dl.h + + + + + $PROJ_DIR$\..\..\..\os\various\chprintf.c + + + $PROJ_DIR$\..\..\..\os\various\chprintf.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj b/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..ef926a349 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,980 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\hal\platforms\STM32F4xx;..\..\..\os\various;..\..\..\os\various\devices_lib\accel;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + stm32f4xx.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c new file mode 100644 index 000000000..1bd9e6b0c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -0,0 +1,244 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN11 (48 cycles sample time) + * Sensor (192 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, + ADC_CR2_SWSTART, + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 1 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI2 configuration structure. + * Speed 21MHz, CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin 12 on the port GPIOA. + */ +static const SPIConfig spi2cfg = { + spicb, + /* HW dependent part.*/ + GPIOB, + 12, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED3); /* Orange. */ + chThdSleepMilliseconds(500); + palClearPad(GPIOD, GPIOD_LED3); /* Orange. */ + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART2. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ + spiStart(&SPID2, &spi2cfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the ADC driver 1 and enable the thermal sensor. + * The pin PC1 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG); + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOD, GPIOD_LED4, PAL_MODE_ALTERNATE(2)); /* Green. */ + palSetPadMode(GPIOD, GPIOD_LED6, PAL_MODE_ALTERNATE(2)); /* Blue. */ + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 2. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..1030482df --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt new file mode 100644 index 000000000..653db79ab --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels (temperature sensor and PC1) and modulates +the PWM using the sampled values. The sample data is also transmitted using +the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15). +By pressing the button located on the board the test procedure is activated +with output on the serial port SD2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.cproject b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.cproject new file mode 100644 index 000000000..a5d3f27fe --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.project b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.project new file mode 100644 index 000000000..f8e5d5b3e --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/.project @@ -0,0 +1,105 @@ + + + ARMCM4-STM32F407-LWIP-FATFS-USB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_E407 + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + lwip + 2 + CHIBIOS/ext/lwip + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/Makefile b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/Makefile new file mode 100644 index 000000000..89cd7d532 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/Makefile @@ -0,0 +1,229 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_E407/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LWSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + web/web.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/chconf.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/ffconf.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/ffconf.h new file mode 100644 index 000000000..e6a13cea3 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/halconf.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/halconf.h new file mode 100644 index 000000000..b5fd15079 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/lwipopts.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/lwipopts.h new file mode 100644 index 000000000..5a8e51970 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/lwipopts.h @@ -0,0 +1,2127 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/main.c b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/main.c new file mode 100644 index 000000000..c1d2cfea5 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/main.c @@ -0,0 +1,692 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "chprintf.h" +#include "shell.h" + +#include "lwipthread.h" +#include "web/web.h" + +#include "ff.h" + +/*===========================================================================*/ +/* Card insertion monitor. */ +/*===========================================================================*/ + +#define POLLING_INTERVAL 10 +#define POLLING_DELAY 10 + +/** + * @brief Card monitor timer. + */ +static VirtualTimer tmr; + +/** + * @brief Debounce counter. + */ +static unsigned cnt; + +/** + * @brief Card event sources. + */ +static EventSource inserted_event, removed_event; + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p BaseBlockDevice object + * + * @notapi + */ +static void tmrfunc(void *p) { + BaseBlockDevice *bbdp = p; + + chSysLockFromIsr(); + if (cnt > 0) { + if (blkIsInserted(bbdp)) { + if (--cnt == 0) { + chEvtBroadcastI(&inserted_event); + } + } + else + cnt = POLLING_INTERVAL; + } + else { + if (!blkIsInserted(bbdp)) { + cnt = POLLING_INTERVAL; + chEvtBroadcastI(&removed_event); + } + } + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp); + chSysUnlockFromIsr(); +} + +/** + * @brief Polling monitor start. + * + * @param[in] p pointer to an object implementing @p BaseBlockDevice + * + * @notapi + */ +static void tmr_init(void *p) { + + chEvtInit(&inserted_event); + chEvtInit(&removed_event); + chSysLock(); + cnt = POLLING_INTERVAL; + chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p); + chSysUnlock(); +} + +/*===========================================================================*/ +/* FatFs related. */ +/*===========================================================================*/ + +/** + * @brief FS object. + */ +static FATFS SDC_FS; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Generic large buffer.*/ +static uint8_t fbuff[1024]; + +static FRESULT scan_files(BaseSequentialStream *chp, char *path) { + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + +#if _USE_LFN + fno.lfname = 0; + fno.lfsize = 0; +#endif + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + path[i++] = '/'; + strcpy(&path[i], fn); + res = scan_files(chp, path); + if (res != FR_OK) + break; + path[--i] = 0; + } + else { + chprintf(chp, "%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: tree\r\n"); + return; + } + if (!fs_ready) { + chprintf(chp, "File System not mounted\r\n"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chprintf(chp, "FS: f_getfree() failed\r\n"); + return; + } + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)SDC_FS.csize, + clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + fbuff[0] = 0; + scan_files(chp, (char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Main and generic code. */ +/*===========================================================================*/ + +/* + * Card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion SDC initialization and FS mount. + */ + if (sdcConnect(&SDCD1)) + return; + + err = f_mount(0, &SDC_FS); + if (err != FR_OK) { + sdcDisconnect(&SDCD1); + return; + } + fs_ready = TRUE; +} + +/* + * Card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + sdcDisconnect(&SDCD1); + fs_ready = FALSE; +} + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palTogglePad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(fs_ready ? 125 : 500); + } +} + +/* + * Application entry point. + */ +int main(void) { + static Thread *shelltp = NULL; + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + struct EventListener el0, el1; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 6 and SDC driver 1 using default + * configuration. + */ + sdStart(&SD6, NULL); + sdcStart(&SDCD1, NULL); + + /* + * Activates the card insertion monitor. + */ + tmr_init(&SDCD1); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Creates the LWIP threads (it changes priority internally). + */ + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 2, + lwip_thread, NULL); + + /* + * Creates the HTTP thread (it changes priority internally). + */ + chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, + http_server, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&inserted_event, &el0, 0); + chEvtRegister(&removed_event, &el1, 1); + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + if (palReadPad(GPIOA, GPIOA_BUTTON_WKUP) != 0) { + } + chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500))); + } +} diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h new file mode 100644 index 000000000..06bac1a3e --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h @@ -0,0 +1,289 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 TRUE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/readme.txt b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/readme.txt new file mode 100644 index 000000000..f7cc4c942 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-E407 board. + +** The Demo ** + +The demo currently just flashes a LED using a thread and serves HTTP requests +at address 192.168.1.20 on port 80. +FatFs integrated using SDIO. +The USB-FS port is used as USB-CDC and a command shell is ready to accepts +commands there. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.c b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.c new file mode 100644 index 000000000..d651b6e2f --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.c @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file is a modified version of the lwIP web server demo. The original + * author is unknown because the file didn't contain any license information. + */ + +/** + * @file web.c + * @brief HTTP server wrapper thread code. + * @addtogroup WEB_THREAD + * @{ + */ + +#include "ch.h" + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" + +#include "web.h" + +#if LWIP_NETCONN + +static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; + +static void http_server_serve(struct netconn *conn) { + struct netbuf *inbuf; + char *buf; + u16_t buflen; + err_t err; + + /* Read the data from the port, blocking if nothing yet there. + We assume the request (the part we care about) is in one netbuf */ + err = netconn_recv(conn, &inbuf); + + if (err == ERR_OK) { + netbuf_data(inbuf, (void **)&buf, &buflen); + + /* Is this an HTTP GET command? (only check the first 5 chars, since + there are other formats for GET, and we're keeping it very simple )*/ + if (buflen>=5 && + buf[0]=='G' && + buf[1]=='E' && + buf[2]=='T' && + buf[3]==' ' && + buf[4]=='/' ) { + + /* Send the HTML header + * subtract 1 from the size, since we dont send the \0 in the string + * NETCONN_NOCOPY: our data is const static, so no need to copy it + */ + netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); + + /* Send our HTML page */ + netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); + } + } + /* Close the connection (server closes in HTTP) */ + netconn_close(conn); + + /* Delete the buffer (netconn_recv gives us ownership, + so we have to make sure to deallocate the buffer) */ + netbuf_delete(inbuf); +} + +/** + * Stack area for the http thread. + */ +WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +/** + * HTTP server thread. + */ +msg_t http_server(void *p) { + struct netconn *conn, *newconn; + err_t err; + + (void)p; + chRegSetThreadName("http"); + + /* Create a new TCP connection handle */ + conn = netconn_new(NETCONN_TCP); + LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); + + /* Bind to port 80 (HTTP) with default IP address */ + netconn_bind(conn, NULL, WEB_THREAD_PORT); + + /* Put the connection into LISTEN state */ + netconn_listen(conn); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(WEB_THREAD_PRIORITY); + + while(1) { + err = netconn_accept(conn, &newconn); + if (err != ERR_OK) + continue; + http_server_serve(newconn); + netconn_delete(newconn); + } + return RDY_OK; +} + +#endif /* LWIP_NETCONN */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.h b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.h new file mode 100644 index 000000000..1dc8b6675 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/web/web.h @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file web.h + * @brief HTTP server wrapper thread macros and structures. + * @addtogroup WEB_THREAD + * @{ + */ + +#ifndef _WEB_H_ +#define _WEB_H_ + +#ifndef WEB_THREAD_STACK_SIZE +#define WEB_THREAD_STACK_SIZE 1024 +#endif + +#ifndef WEB_THREAD_PORT +#define WEB_THREAD_PORT 80 +#endif + +#ifndef WEB_THREAD_PRIORITY +#define WEB_THREAD_PRIORITY (LOWPRIO + 2) +#endif + +extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t http_server(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _WEB_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP/.cproject b/demos/ARMCM4-STM32F407-LWIP/.cproject new file mode 100644 index 000000000..07ed16b19 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM4-STM32F407-LWIP/.project b/demos/ARMCM4-STM32F407-LWIP/.project new file mode 100644 index 000000000..f11f3e6fc --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/.project @@ -0,0 +1,53 @@ + + + ARMCM4-STM32F407-LWIP + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P407 + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + lwip + 2 + CHIBIOS/ext/lwip + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/ARMCM4-STM32F407-LWIP/Makefile b/demos/ARMCM4-STM32F407-LWIP/Makefile new file mode 100644 index 000000000..e8aec516a --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/Makefile @@ -0,0 +1,224 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P407/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LWSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + web/web.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-LWIP/chconf.h b/demos/ARMCM4-STM32F407-LWIP/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP/halconf.h b/demos/ARMCM4-STM32F407-LWIP/halconf.h new file mode 100644 index 000000000..43fddb60e --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP/lwipopts.h b/demos/ARMCM4-STM32F407-LWIP/lwipopts.h new file mode 100644 index 000000000..5a8e51970 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/lwipopts.h @@ -0,0 +1,2127 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/ARMCM4-STM32F407-LWIP/main.c b/demos/ARMCM4-STM32F407-LWIP/main.c new file mode 100644 index 000000000..1db088b00 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/main.c @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "lwipthread.h" + +#include "web/web.h" + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOF, GPIOF_STAT1); + chThdSleepMilliseconds(500); + palSetPad(GPIOF, GPIOF_STAT1); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 6 using the driver default configuration. + */ + sdStart(&SD6, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Creates the LWIP threads (it changes priority internally). + */ + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, + lwip_thread, NULL); + + /* + * Creates the HTTP thread (it changes priority internally). + */ + chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, + http_server, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0) + TestThread(&SD6); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F407-LWIP/mcuconf.h b/demos/ARMCM4-STM32F407-LWIP/mcuconf.h new file mode 100644 index 000000000..0837acde0 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 TRUE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/demos/ARMCM4-STM32F407-LWIP/readme.txt b/demos/ARMCM4-STM32F407-LWIP/readme.txt new file mode 100644 index 000000000..57a2526ca --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P407 board. + +** The Demo ** + +The demo currently just flashes a LED using a thread and serves HTTP requests +at address 192.168.1.20 on port 80. +The button activates che ChibiOS/RT test suite, output on SD6. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM4-STM32F407-LWIP/web/web.c b/demos/ARMCM4-STM32F407-LWIP/web/web.c new file mode 100644 index 000000000..c4f16852e --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/web/web.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file is a modified version of the lwIP web server demo. The original + * author is unknown because the file didn't contain any license information. + */ + +/** + * @file web.c + * @brief HTTP server wrapper thread code. + * @addtogroup WEB_THREAD + * @{ + */ + +#include "ch.h" + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" + +#include "web.h" + +#if LWIP_NETCONN + +static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; + +static void http_server_serve(struct netconn *conn) { + struct netbuf *inbuf; + char *buf; + u16_t buflen; + err_t err; + + /* Read the data from the port, blocking if nothing yet there. + We assume the request (the part we care about) is in one netbuf */ + err = netconn_recv(conn, &inbuf); + + if (err == ERR_OK) { + netbuf_data(inbuf, (void **)&buf, &buflen); + + /* Is this an HTTP GET command? (only check the first 5 chars, since + there are other formats for GET, and we're keeping it very simple )*/ + if (buflen>=5 && + buf[0]=='G' && + buf[1]=='E' && + buf[2]=='T' && + buf[3]==' ' && + buf[4]=='/' ) { + + /* Send the HTML header + * subtract 1 from the size, since we dont send the \0 in the string + * NETCONN_NOCOPY: our data is const static, so no need to copy it + */ + netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); + + /* Send our HTML page */ + netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); + } + } + /* Close the connection (server closes in HTTP) */ + netconn_close(conn); + + /* Delete the buffer (netconn_recv gives us ownership, + so we have to make sure to deallocate the buffer) */ + netbuf_delete(inbuf); +} + +/** + * Stack area for the http thread. + */ +WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +/** + * HTTP server thread. + */ +msg_t http_server(void *p) { + struct netconn *conn, *newconn; + err_t err; + + (void)p; + + /* Create a new TCP connection handle */ + conn = netconn_new(NETCONN_TCP); + LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); + + /* Bind to port 80 (HTTP) with default IP address */ + netconn_bind(conn, NULL, WEB_THREAD_PORT); + + /* Put the connection into LISTEN state */ + netconn_listen(conn); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(WEB_THREAD_PRIORITY); + + while(1) { + err = netconn_accept(conn, &newconn); + if (err != ERR_OK) + continue; + http_server_serve(newconn); + netconn_delete(newconn); + } + return RDY_OK; +} + +#endif /* LWIP_NETCONN */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-LWIP/web/web.h b/demos/ARMCM4-STM32F407-LWIP/web/web.h new file mode 100644 index 000000000..1dc8b6675 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/web/web.h @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file web.h + * @brief HTTP server wrapper thread macros and structures. + * @addtogroup WEB_THREAD + * @{ + */ + +#ifndef _WEB_H_ +#define _WEB_H_ + +#ifndef WEB_THREAD_STACK_SIZE +#define WEB_THREAD_STACK_SIZE 1024 +#endif + +#ifndef WEB_THREAD_PORT +#define WEB_THREAD_PORT 80 +#endif + +#ifndef WEB_THREAD_PRIORITY +#define WEB_THREAD_PRIORITY (LOWPRIO + 2) +#endif + +extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t http_server(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _WEB_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile new file mode 100644 index 000000000..fa9309e2f --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -0,0 +1,652 @@ +# Hey Emacs, this is a -*- makefile -*- +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +#---------------------------------------------------------------------------- +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF. +# +# make extcoff = Convert ELF to AVR Extended COFF. +# +# make program = Download the hex file to the device, using avrdude. +# Please customize the avrdude settings below first! +# +# make debug = Start either simulavr or avarice as specified for debugging, +# with avr-gdb or avr-insight as the front end for debugging. +# +# make filename.s = Just compile filename.c into the assembler code only. +# +# make filename.i = Create a preprocessed source file for use in submitting +# bug reports to the GCC project. +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + + +# MCU name +MCU = at90can128 + + +# Processor frequency. +# This will define a symbol, F_CPU, in all source code files equal to the +# processor frequency. You can then use this symbol in your source code to +# calculate timings. Do NOT tack on a 'UL' at the end, this will be done +# automatically to create a 32-bit value in your source code. +# Typical values are: +# F_CPU = 1000000 +# F_CPU = 1843200 +# F_CPU = 2000000 +# F_CPU = 3686400 +# F_CPU = 4000000 +# F_CPU = 7372800 +# F_CPU = 8000000 +# F_CPU = 11059200 +# F_CPU = 14745600 +# F_CPU = 16000000 +# F_CPU = 18432000 +# F_CPU = 20000000 +F_CPU = 16000000 + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = ch + + +# Object files directory +# To put object files in current directory, use a dot (.), do NOT make +# this an empty or blank macro! +OBJDIR = . + + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_AVR_CAN/board.mk +include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/AVR/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c + + +# List C++ source files here. (C dependencies are automatically generated.) +CPPSRC = + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s + + +# Debugging format. +# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. +# AVR Studio 4.10 requires dwarf-2. +# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be separated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here for C sources +CDEFS = -DF_CPU=$(F_CPU)UL + + +# Place -D or -U options here for ASM sources +ADEFS = -DF_CPU=$(F_CPU) + + +# Place -D or -U options here for C++ sources +CPPDEFS = -DF_CPU=$(F_CPU)UL +#CPPDEFS += -D__STDC_LIMIT_MACROS +#CPPDEFS += -D__STDC_CONSTANT_MACROS + + + +#---------------- Compiler Options C ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) +CFLAGS += -O$(OPT) +CFLAGS += -funsigned-char +CFLAGS += -funsigned-bitfields +CFLAGS += -fpack-struct +CFLAGS += -fshort-enums +#CFLAGS += -fno-strict-aliasing +CFLAGS += -Wall +CFLAGS += -Wstrict-prototypes +#CFLAGS += -mshort-calls +#CFLAGS += -fno-unit-at-a-time +#CFLAGS += -Wundef +#CFLAGS += -Wunreachable-code +#CFLAGS += -Wsign-compare +CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) + + +#---------------- Compiler Options C++ ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CPPFLAGS = -g$(DEBUG) +CPPFLAGS += $(CPPDEFS) +CPPFLAGS += -O$(OPT) +CPPFLAGS += -funsigned-char +CPPFLAGS += -funsigned-bitfields +CPPFLAGS += -fpack-struct +CPPFLAGS += -fshort-enums +CPPFLAGS += -fno-exceptions +CPPFLAGS += -Wall +CFLAGS += -Wundef +#CPPFLAGS += -mshort-calls +#CPPFLAGS += -fno-unit-at-a-time +#CPPFLAGS += -Wstrict-prototypes +#CPPFLAGS += -Wunreachable-code +#CPPFLAGS += -Wsign-compare +CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +#CPPFLAGS += $(CSTANDARD) + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +# -listing-cont-lines: Sets the maximum number of continuation lines of hex +# dump that will be displayed for a given single line of source input. +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 + + +#---------------- Library Options ---------------- +# Minimalistic printf version +PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires MATH_LIB = -lm below) +PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt + +# If this is left blank, then it will use the Standard printf version. +PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_FLOAT) + + +# Minimalistic scanf version +SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min + +# Floating point + %[ scanf version (requires MATH_LIB = -lm below) +SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt + +# If this is left blank, then it will use the Standard scanf version. +SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_FLOAT) + + +MATH_LIB = -lm + + +# List any extra directories to look for libraries here. +# Each directory must be separated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRALIBDIRS = + + + +#---------------- External Memory Options ---------------- + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# used for variables (.data/.bss) and heap (malloc()). +#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# only used for heap (malloc()). +#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff + +EXTMEMOPTS = + + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += $(EXTMEMOPTS) +LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) +LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) +#LDFLAGS += -T linker_script.x + + + +#---------------- Programming Options (avrdude) ---------------- + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + +# com1 = serial port. Use lpt1 to connect to parallel port. +AVRDUDE_PORT = com1 # programmer connected to serial device + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) +AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) +AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) + + + +#---------------- Debugging Options ---------------- + +# For simulavr only - target MCU frequency. +DEBUG_MFREQ = $(F_CPU) + +# Set the DEBUG_UI to either gdb or insight. +# DEBUG_UI = gdb +DEBUG_UI = insight + +# Set the debugging back-end to either avarice, simulavr. +DEBUG_BACKEND = avarice +#DEBUG_BACKEND = simulavr + +# GDB Init Filename. +GDBINIT_FILE = __avr_gdbinit + +# When using avarice settings for the JTAG +JTAG_DEV = /dev/com1 + +# Debugging port used to communicate between GDB / avarice / simulavr. +DEBUG_PORT = 4242 + +# Debugging host used to communicate between GDB / avarice / simulavr, normally +# just set to localhost unless doing some sort of crazy debugging when +# avarice is running on a different computer. +DEBUG_HOST = localhost + + + +#============================================================================ + + +# Define programs and commands. +SHELL = sh +CC = avr-gcc +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +AR = avr-ar rcs +NM = avr-nm +AVRDUDE = avrdude +REMOVE = rm -f +REMOVEDIR = rm -rf +COPY = cp +WINSHELL = cmd + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_CPP = Compiling C++: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_CREATING_LIBRARY = Creating library: + + + + +# Define all object files. +OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) + +# Define all listing files. +LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + + + +# Default target. +all: begin gccversion sizebefore build sizeafter end + +# Change the build target to build a HEX file or a library. +build: elf hex bin eep lss sym +#build: lib + + +elf: $(TARGET).elf +hex: $(TARGET).hex +bin: $(TARGET).bin +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym +LIBNAME=lib$(TARGET).a +lib: $(LIBNAME) + + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf + +sizebefore: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ + 2>/dev/null; echo; fi + +sizeafter: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ + 2>/dev/null; echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + +# Generate avr-gdb config/init file which does the following: +# define the reset signal, load the target file, connect to target, and set +# a breakpoint at main(). +gdb-config: + @$(REMOVE) $(GDBINIT_FILE) + @echo define reset >> $(GDBINIT_FILE) + @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) + @echo end >> $(GDBINIT_FILE) + @echo file $(TARGET).elf >> $(GDBINIT_FILE) + @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) +ifeq ($(DEBUG_BACKEND),simulavr) + @echo load >> $(GDBINIT_FILE) +endif + @echo break main >> $(GDBINIT_FILE) + +debug: gdb-config $(TARGET).elf +ifeq ($(DEBUG_BACKEND), avarice) + @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. + @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ + $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) + @$(WINSHELL) /c pause + +else + @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ + $(DEBUG_MFREQ) --port $(DEBUG_PORT) +endif + @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) + + + + +# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. +COFFCONVERT = $(OBJCOPY) --debugging +COFFCONVERT += --change-section-address .data-0x800000 +COFFCONVERT += --change-section-address .bss-0x800000 +COFFCONVERT += --change-section-address .noinit-0x800000 +COFFCONVERT += --change-section-address .eeprom-0x810000 + + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + + +# Create library from object files. +.SECONDARY : $(TARGET).a +.PRECIOUS : $(OBJ) +%.a: $(OBJ) + @echo + @echo $(MSG_CREATING_LIBRARY) $@ + $(AR) $@ $(OBJ) + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create object files from C++ source files. +$(OBJDIR)/%.o : %.cpp + @echo + @echo $(MSG_COMPILING_CPP) $< + $(CC) -c $(ALL_CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C++ source files. +%.s : %.cpp + $(CC) -S $(ALL_CPPFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Create preprocessed source for use in sending a bug report. +%.i : %.c + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lss + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRC:.c=.i) + $(REMOVEDIR) .dep + + +# Create object files directory +$(shell mkdir $(OBJDIR) 2>/dev/null) + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin eep lss sym coff extcoff \ +clean clean_list program debug gdb-config + + + + + + diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h new file mode 100644 index 000000000..253eadaa5 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c new file mode 100644 index 000000000..6b2871b78 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -0,0 +1,63 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static WORKING_AREA(waThread1, 32); +static msg_t Thread1(void *arg) { + + while (TRUE) { + palTogglePad(IOPORT5, PORTE_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Starts the LED blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + while(TRUE) { + if (!palReadPad(IOPORT5, PORTE_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } + + return 0; +} diff --git a/demos/AVR-AT90CANx-GCC/mcuconf.h b/demos/AVR-AT90CANx-GCC/mcuconf.h new file mode 100644 index 000000000..d3c05d25b --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/mcuconf.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AVR drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_AVR_USART0 FALSE +#define USE_AVR_USART1 TRUE + +/* + * SPI driver system settings. + */ diff --git a/demos/AVR-AT90CANx-GCC/readme.txt b/demos/AVR-AT90CANx-GCC/readme.txt new file mode 100644 index 000000000..3102bcf15 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for Atmel AVR AT90CAN128. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex AVR-CAN board. + +** The Demo ** + +The demo currently just flashes the board LED using a thread. It will be +expanded in next releases. +By pressing the board button the test suite is activated, output on serial +port 2. + +** Build Procedure ** + +The demo was built using the WinAVR toolchain. + +** Notes ** + +The demo requires include files from WinAVR that are not part of the ChibiOS/RT +distribution, please install WinAVR. + + http://winavr.sourceforge.net/ diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile new file mode 100644 index 000000000..0ea8e8cff --- /dev/null +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -0,0 +1,652 @@ +# Hey Emacs, this is a -*- makefile -*- +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +#---------------------------------------------------------------------------- +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF. +# +# make extcoff = Convert ELF to AVR Extended COFF. +# +# make program = Download the hex file to the device, using avrdude. +# Please customize the avrdude settings below first! +# +# make debug = Start either simulavr or avarice as specified for debugging, +# with avr-gdb or avr-insight as the front end for debugging. +# +# make filename.s = Just compile filename.c into the assembler code only. +# +# make filename.i = Create a preprocessed source file for use in submitting +# bug reports to the GCC project. +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + + +# MCU name +MCU = atmega128 + + +# Processor frequency. +# This will define a symbol, F_CPU, in all source code files equal to the +# processor frequency. You can then use this symbol in your source code to +# calculate timings. Do NOT tack on a 'UL' at the end, this will be done +# automatically to create a 32-bit value in your source code. +# Typical values are: +# F_CPU = 1000000 +# F_CPU = 1843200 +# F_CPU = 2000000 +# F_CPU = 3686400 +# F_CPU = 4000000 +# F_CPU = 7372800 +# F_CPU = 8000000 +# F_CPU = 11059200 +# F_CPU = 14745600 +# F_CPU = 16000000 +# F_CPU = 18432000 +# F_CPU = 20000000 +F_CPU = 16000000 + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = ch + + +# Object files directory +# To put object files in current directory, use a dot (.), do NOT make +# this an empty or blank macro! +OBJDIR = . + + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_AVR_MT_128/board.mk +include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/AVR/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + lcd.c main.c + + +# List C++ source files here. (C dependencies are automatically generated.) +CPPSRC = + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = 2 + + +# Debugging format. +# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. +# AVR Studio 4.10 requires dwarf-2. +# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be separated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here for C sources +CDEFS = -DF_CPU=$(F_CPU)UL + + +# Place -D or -U options here for ASM sources +ADEFS = -DF_CPU=$(F_CPU) + + +# Place -D or -U options here for C++ sources +CPPDEFS = -DF_CPU=$(F_CPU)UL +#CPPDEFS += -D__STDC_LIMIT_MACROS +#CPPDEFS += -D__STDC_CONSTANT_MACROS + + + +#---------------- Compiler Options C ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) +CFLAGS += -O$(OPT) +CFLAGS += -funsigned-char +CFLAGS += -funsigned-bitfields +CFLAGS += -fpack-struct +CFLAGS += -fshort-enums +#CFLAGS += -fno-strict-aliasing +CFLAGS += -Wall +CFLAGS += -Wstrict-prototypes +#CFLAGS += -mshort-calls +#CFLAGS += -fno-unit-at-a-time +#CFLAGS += -Wundef +#CFLAGS += -Wunreachable-code +#CFLAGS += -Wsign-compare +CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) + + +#---------------- Compiler Options C++ ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CPPFLAGS = -g$(DEBUG) +CPPFLAGS += $(CPPDEFS) +CPPFLAGS += -O$(OPT) +CPPFLAGS += -funsigned-char +CPPFLAGS += -funsigned-bitfields +CPPFLAGS += -fpack-struct +CPPFLAGS += -fshort-enums +CPPFLAGS += -fno-exceptions +CPPFLAGS += -Wall +CFLAGS += -Wundef +#CPPFLAGS += -mshort-calls +#CPPFLAGS += -fno-unit-at-a-time +#CPPFLAGS += -Wstrict-prototypes +#CPPFLAGS += -Wunreachable-code +#CPPFLAGS += -Wsign-compare +CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +#CPPFLAGS += $(CSTANDARD) + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +# -listing-cont-lines: Sets the maximum number of continuation lines of hex +# dump that will be displayed for a given single line of source input. +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 + + +#---------------- Library Options ---------------- +# Minimalistic printf version +PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires MATH_LIB = -lm below) +PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt + +# If this is left blank, then it will use the Standard printf version. +PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_FLOAT) + + +# Minimalistic scanf version +SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min + +# Floating point + %[ scanf version (requires MATH_LIB = -lm below) +SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt + +# If this is left blank, then it will use the Standard scanf version. +SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_FLOAT) + + +MATH_LIB = -lm + + +# List any extra directories to look for libraries here. +# Each directory must be separated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRALIBDIRS = + + + +#---------------- External Memory Options ---------------- + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# used for variables (.data/.bss) and heap (malloc()). +#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# only used for heap (malloc()). +#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff + +EXTMEMOPTS = + + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += $(EXTMEMOPTS) +LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) +LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) +#LDFLAGS += -T linker_script.x + + + +#---------------- Programming Options (avrdude) ---------------- + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + +# com1 = serial port. Use lpt1 to connect to parallel port. +AVRDUDE_PORT = com1 # programmer connected to serial device + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) +AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) +AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) + + + +#---------------- Debugging Options ---------------- + +# For simulavr only - target MCU frequency. +DEBUG_MFREQ = $(F_CPU) + +# Set the DEBUG_UI to either gdb or insight. +# DEBUG_UI = gdb +DEBUG_UI = insight + +# Set the debugging back-end to either avarice, simulavr. +DEBUG_BACKEND = avarice +#DEBUG_BACKEND = simulavr + +# GDB Init Filename. +GDBINIT_FILE = __avr_gdbinit + +# When using avarice settings for the JTAG +JTAG_DEV = /dev/com1 + +# Debugging port used to communicate between GDB / avarice / simulavr. +DEBUG_PORT = 4242 + +# Debugging host used to communicate between GDB / avarice / simulavr, normally +# just set to localhost unless doing some sort of crazy debugging when +# avarice is running on a different computer. +DEBUG_HOST = localhost + + + +#============================================================================ + + +# Define programs and commands. +SHELL = sh +CC = avr-gcc +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +AR = avr-ar rcs +NM = avr-nm +AVRDUDE = avrdude +REMOVE = rm -f +REMOVEDIR = rm -rf +COPY = cp +WINSHELL = cmd + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_CPP = Compiling C++: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_CREATING_LIBRARY = Creating library: + + + + +# Define all object files. +OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) + +# Define all listing files. +LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + + + +# Default target. +all: begin gccversion sizebefore build sizeafter end + +# Change the build target to build a HEX file or a library. +build: elf hex bin eep lss sym +#build: lib + + +elf: $(TARGET).elf +hex: $(TARGET).hex +bin: $(TARGET).bin +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym +LIBNAME=lib$(TARGET).a +lib: $(LIBNAME) + + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf + +sizebefore: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ + 2>/dev/null; echo; fi + +sizeafter: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ + 2>/dev/null; echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + +# Generate avr-gdb config/init file which does the following: +# define the reset signal, load the target file, connect to target, and set +# a breakpoint at main(). +gdb-config: + @$(REMOVE) $(GDBINIT_FILE) + @echo define reset >> $(GDBINIT_FILE) + @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) + @echo end >> $(GDBINIT_FILE) + @echo file $(TARGET).elf >> $(GDBINIT_FILE) + @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) +ifeq ($(DEBUG_BACKEND),simulavr) + @echo load >> $(GDBINIT_FILE) +endif + @echo break main >> $(GDBINIT_FILE) + +debug: gdb-config $(TARGET).elf +ifeq ($(DEBUG_BACKEND), avarice) + @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. + @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ + $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) + @$(WINSHELL) /c pause + +else + @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ + $(DEBUG_MFREQ) --port $(DEBUG_PORT) +endif + @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) + + + + +# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. +COFFCONVERT = $(OBJCOPY) --debugging +COFFCONVERT += --change-section-address .data-0x800000 +COFFCONVERT += --change-section-address .bss-0x800000 +COFFCONVERT += --change-section-address .noinit-0x800000 +COFFCONVERT += --change-section-address .eeprom-0x810000 + + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + + +# Create library from object files. +.SECONDARY : $(TARGET).a +.PRECIOUS : $(OBJ) +%.a: $(OBJ) + @echo + @echo $(MSG_CREATING_LIBRARY) $@ + $(AR) $@ $(OBJ) + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create object files from C++ source files. +$(OBJDIR)/%.o : %.cpp + @echo + @echo $(MSG_COMPILING_CPP) $< + $(CC) -c $(ALL_CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C++ source files. +%.s : %.cpp + $(CC) -S $(ALL_CPPFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Create preprocessed source for use in sending a bug report. +%.i : %.c + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lss + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRC:.c=.i) + $(REMOVEDIR) .dep + + +# Create object files directory +$(shell mkdir $(OBJDIR) 2>/dev/null) + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin eep lss sym coff extcoff \ +clean clean_list program debug gdb-config + + + + + + diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h new file mode 100644 index 000000000..253eadaa5 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ATmega128-GCC/lcd.c b/demos/AVR-ATmega128-GCC/lcd.c new file mode 100644 index 000000000..d0415b83f --- /dev/null +++ b/demos/AVR-ATmega128-GCC/lcd.c @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "lcd.h" + +static void e_pulse(void) { + volatile uint8_t i; + + PORTC |= PORTC_44780_E_MASK; + for (i = 0; i < ELOOPVALUE; i++); + ; + PORTC &= ~PORTC_44780_E_MASK; +} + +static void wait_not_busy(void) { + + chThdSleep(2); +} + +/* + * 44780 soft reset procedure. + */ +void lcdInit(void) { + + PORTC = (PORTC & ~(PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK | + PORTC_44780_E_MASK | PORTC_44780_RW_MASK)) | + (LCD_CMD_INIT8 & PORTC_44780_DATA_MASK); + chThdSleep(50); + e_pulse(); + chThdSleep(10); + e_pulse(); + chThdSleep(2); + e_pulse(); + wait_not_busy(); + PORTC = (PORTC & ~(PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK | + PORTC_44780_E_MASK | PORTC_44780_RW_MASK)) | + (LCD_CMD_INIT4 & PORTC_44780_DATA_MASK); + e_pulse(); + lcdCmd(LCD_CMD_INIT4); + lcdCmd(LCD_SET_DM | LCD_DM_DISPLAY_ON); + lcdCmd(LCD_SET_INCREMENT_MODE); +} + +/* + * Sends a command byte to the 44780. + */ +void lcdCmd(uint8_t cmd) { + + wait_not_busy(); + PORTC = (PORTC | PORTC_44780_DATA_MASK) & (cmd | + (0x0F & ~PORTC_44780_RS_MASK)); + e_pulse(); + PORTC = (PORTC | PORTC_44780_DATA_MASK) & ((cmd << 4) | + (0x0F & ~PORTC_44780_RS_MASK)); + e_pulse(); +} + +/* + * Writes a char on the LCD at the current position. + */ +void lcdPutc(char c) { + uint8_t b; + + wait_not_busy(); + b = c | 0x0F; + PORTC = (PORTC | PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK) & + (c | 0x0F); + e_pulse(); + PORTC = (PORTC | PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK) & + ((c << 4) | 0x0F); + e_pulse(); +} + +/* + * Writes a string on the LCD at an absolute address. + */ +void lcdPuts(uint8_t pos, char *p) { + + lcdCmd(LCD_SET_DDRAM_ADDRESS | pos); + while (*p) + lcdPutc(*p++); +} diff --git a/demos/AVR-ATmega128-GCC/lcd.h b/demos/AVR-ATmega128-GCC/lcd.h new file mode 100644 index 000000000..c86d90dc1 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/lcd.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _LCD_H_ +#define _LCD_H_ + +#define ELOOPVALUE 10 + +#define LCD_CLEAR 0x01 + +#define LCD_RETURN_HOME 0x02 + +#define LCD_SET_INCREMENT_MODE 0x06 + +#define LCD_SET_DM 0x08 +#define LCD_DM_DISPLAY_ON 4 +#define LCD_DM_DISPLAY_OFF 0 +#define LCD_DM_CURSOR_ON 2 +#define LCD_DM_CURSOR_OFF 0 +#define LCD_DM_BLINK_ON 1 +#define LCD_DM_BLINK_OFF 0 + +#define LCD_CMD_INIT4 0x28 +#define LCD_CMD_INIT8 0x38 + +#define LCD_SET_DDRAM_ADDRESS 0x80 + +#define LCD_LINE1 0 +#define LCD_LINE2 40 + +void lcdInit(void); +void lcdCmd(uint8_t cmd); +void lcdPutc(char c); +void lcdPuts(uint8_t pos, char *p); + +#endif /* _LCD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c new file mode 100644 index 000000000..756e7fe6a --- /dev/null +++ b/demos/AVR-ATmega128-GCC/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "lcd.h" + +static WORKING_AREA(waThread1, 32); +static msg_t Thread1(void *arg) { + + while (TRUE) { + if (!palReadPad(IOPORT1, PORTA_BUTTON2)) + palTogglePad(IOPORT1, PORTA_RELAY); + chThdSleepMilliseconds(1000); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * This initialization requires the OS already active because it uses delay + * APIs inside. + */ + lcdInit(); + lcdCmd(LCD_CLEAR); + lcdPuts(LCD_LINE1, " ChibiOS/RT "); + lcdPuts(LCD_LINE2, " Hello World! "); + + /* + * Starts the LED blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + while(TRUE) { + if (!palReadPad(IOPORT1, PORTA_BUTTON1)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/AVR-ATmega128-GCC/mcuconf.h b/demos/AVR-ATmega128-GCC/mcuconf.h new file mode 100644 index 000000000..d3c05d25b --- /dev/null +++ b/demos/AVR-ATmega128-GCC/mcuconf.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AVR drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_AVR_USART0 FALSE +#define USE_AVR_USART1 TRUE + +/* + * SPI driver system settings. + */ diff --git a/demos/AVR-ATmega128-GCC/readme.txt b/demos/AVR-ATmega128-GCC/readme.txt new file mode 100644 index 000000000..7158463fb --- /dev/null +++ b/demos/AVR-ATmega128-GCC/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT port for Atmel AVR ATmega128. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex AVR-MT-128 board. + +** The Demo ** + +The demo currently just writes a hello world on the LCD and toggles the relay +using a thread while button 2 is pressed. +By pressing the button 1 the test suite is activated, output on serial port 2. + +** Build Procedure ** + +The demo was built using the WinAVR toolchain. + +** Notes ** + +The demo requires include files from WinAVR that are not part of the ChibiOS/RT +distribution, please install WinAVR. + + http://winavr.sourceforge.net/ diff --git a/demos/AVR-ArduinoMega-GCC/Makefile b/demos/AVR-ArduinoMega-GCC/Makefile new file mode 100644 index 000000000..9113e88fc --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/Makefile @@ -0,0 +1,630 @@ +# Hey Emacs, this is a -*- makefile -*- +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +#---------------------------------------------------------------------------- +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF. +# +# make extcoff = Convert ELF to AVR Extended COFF. +# +# make program = Download the hex file to the device, using avrdude. +# Please customize the avrdude settings below first! +# +# make debug = Start either simulavr or avarice as specified for debugging, +# with avr-gdb or avr-insight as the front end for debugging. +# +# make filename.s = Just compile filename.c into the assembler code only. +# +# make filename.i = Create a preprocessed source file for use in submitting +# bug reports to the GCC project. +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + + +# MCU name +MCU = atmega1280 + + +# Processor frequency. +F_CPU = 16000000 + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = ch + + +# Object files directory +# To put object files in current directory, use a dot (.), do NOT make +# this an empty or blank macro! +OBJDIR = . + + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ARDUINO_MEGA/board.mk +include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/AVR/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c + + +# List C++ source files here. (C dependencies are automatically generated.) +CPPSRC = + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = 2 + + +# Debugging format. +# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. +# AVR Studio 4.10 requires dwarf-2. +# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here for C sources +CDEFS = -DF_CPU=$(F_CPU)UL + + +# Place -D or -U options here for ASM sources +ADEFS = -DF_CPU=$(F_CPU) + + +# Place -D or -U options here for C++ sources +CPPDEFS = -DF_CPU=$(F_CPU)UL +#CPPDEFS += -D__STDC_LIMIT_MACROS +#CPPDEFS += -D__STDC_CONSTANT_MACROS + + + +#---------------- Compiler Options C ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) +CFLAGS += -O$(OPT) +CFLAGS += -funsigned-char +CFLAGS += -funsigned-bitfields +CFLAGS += -fpack-struct +CFLAGS += -fshort-enums +#CFLAGS += -fno-strict-aliasing +CFLAGS += -Wall +CFLAGS += -Wstrict-prototypes +#CFLAGS += -mshort-calls +#CFLAGS += -fno-unit-at-a-time +#CFLAGS += -Wundef +#CFLAGS += -Wunreachable-code +#CFLAGS += -Wsign-compare +CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) + + +#---------------- Compiler Options C++ ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CPPFLAGS = -g$(DEBUG) +CPPFLAGS += $(CPPDEFS) +CPPFLAGS += -O$(OPT) +CPPFLAGS += -funsigned-char +CPPFLAGS += -funsigned-bitfields +CPPFLAGS += -fpack-struct +CPPFLAGS += -fshort-enums +CPPFLAGS += -fno-exceptions +CPPFLAGS += -Wall +CFLAGS += -Wundef +#CPPFLAGS += -mshort-calls +#CPPFLAGS += -fno-unit-at-a-time +#CPPFLAGS += -Wstrict-prototypes +#CPPFLAGS += -Wunreachable-code +#CPPFLAGS += -Wsign-compare +CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +#CPPFLAGS += $(CSTANDARD) + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +# -listing-cont-lines: Sets the maximum number of continuation lines of hex +# dump that will be displayed for a given single line of source input. +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 + + +#---------------- Library Options ---------------- +# Minimalistic printf version +PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires MATH_LIB = -lm below) +PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt + +# If this is left blank, then it will use the Standard printf version. +PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_FLOAT) + + +# Minimalistic scanf version +SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min + +# Floating point + %[ scanf version (requires MATH_LIB = -lm below) +SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt + +# If this is left blank, then it will use the Standard scanf version. +SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_FLOAT) + + +MATH_LIB = -lm + + +# List any extra directories to look for libraries here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRALIBDIRS = + + + +#---------------- External Memory Options ---------------- + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# used for variables (.data/.bss) and heap (malloc()). +#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# only used for heap (malloc()). +#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff + +EXTMEMOPTS = + + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += $(EXTMEMOPTS) +LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) +LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) +#LDFLAGS += -T linker_script.x + + + +#---------------- Programming Options (avrdude) ---------------- + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + +# com1 = serial port. Use lpt1 to connect to parallel port. +AVRDUDE_PORT = com1 # programmer connected to serial device + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) +AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) +AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) + + + +#---------------- Debugging Options ---------------- + +# For simulavr only - target MCU frequency. +DEBUG_MFREQ = $(F_CPU) + +# Set the DEBUG_UI to either gdb or insight. +# DEBUG_UI = gdb +DEBUG_UI = insight + +# Set the debugging back-end to either avarice, simulavr. +DEBUG_BACKEND = avarice +#DEBUG_BACKEND = simulavr + +# GDB Init Filename. +GDBINIT_FILE = __avr_gdbinit + +# When using avarice settings for the JTAG +JTAG_DEV = /dev/com1 + +# Debugging port used to communicate between GDB / avarice / simulavr. +DEBUG_PORT = 4242 + +# Debugging host used to communicate between GDB / avarice / simulavr, normally +# just set to localhost unless doing some sort of crazy debugging when +# avarice is running on a different computer. +DEBUG_HOST = localhost + + + +#============================================================================ + + +# Define programs and commands. +SHELL = sh +CC = avr-gcc +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +AR = avr-ar rcs +NM = avr-nm +AVRDUDE = avrdude +REMOVE = rm -f +REMOVEDIR = rm -rf +COPY = cp +WINSHELL = cmd + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_CPP = Compiling C++: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_CREATING_LIBRARY = Creating library: + + + + +# Define all object files. +OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) + +# Define all listing files. +LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + + + +# Default target. +all: begin gccversion sizebefore build sizeafter end + +# Change the build target to build a HEX file or a library. +build: elf hex bin eep lss sym +#build: lib + + +elf: $(TARGET).elf +hex: $(TARGET).hex +bin: $(TARGET).bin +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym +LIBNAME=lib$(TARGET).a +lib: $(LIBNAME) + + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf + +sizebefore: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ + 2>/dev/null; echo; fi + +sizeafter: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ + 2>/dev/null; echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + +# Generate avr-gdb config/init file which does the following: +# define the reset signal, load the target file, connect to target, and set +# a breakpoint at main(). +gdb-config: + @$(REMOVE) $(GDBINIT_FILE) + @echo define reset >> $(GDBINIT_FILE) + @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) + @echo end >> $(GDBINIT_FILE) + @echo file $(TARGET).elf >> $(GDBINIT_FILE) + @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) +ifeq ($(DEBUG_BACKEND),simulavr) + @echo load >> $(GDBINIT_FILE) +endif + @echo break main >> $(GDBINIT_FILE) + +debug: gdb-config $(TARGET).elf +ifeq ($(DEBUG_BACKEND), avarice) + @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. + @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ + $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) + @$(WINSHELL) /c pause + +else + @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ + $(DEBUG_MFREQ) --port $(DEBUG_PORT) +endif + @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) + + + + +# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. +COFFCONVERT = $(OBJCOPY) --debugging +COFFCONVERT += --change-section-address .data-0x800000 +COFFCONVERT += --change-section-address .bss-0x800000 +COFFCONVERT += --change-section-address .noinit-0x800000 +COFFCONVERT += --change-section-address .eeprom-0x810000 + + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + + +# Create library from object files. +.SECONDARY : $(TARGET).a +.PRECIOUS : $(OBJ) +%.a: $(OBJ) + @echo + @echo $(MSG_CREATING_LIBRARY) $@ + $(AR) $@ $(OBJ) + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create object files from C++ source files. +$(OBJDIR)/%.o : %.cpp + @echo + @echo $(MSG_COMPILING_CPP) $< + $(CC) -c $(ALL_CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C++ source files. +%.s : %.cpp + $(CC) -S $(ALL_CPPFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Create preprocessed source for use in sending a bug report. +%.i : %.c + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lss + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRC:.c=.i) + $(REMOVEDIR) .dep + + +# Create object files directory +$(shell mkdir $(OBJDIR) 2>/dev/null) + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin eep lss sym coff extcoff \ +clean clean_list program debug gdb-config + diff --git a/demos/AVR-ArduinoMega-GCC/chconf.h b/demos/AVR-ArduinoMega-GCC/chconf.h new file mode 100644 index 000000000..b5b5383fd --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE FALSE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ArduinoMega-GCC/halconf.h b/demos/AVR-ArduinoMega-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ArduinoMega-GCC/main.c b/demos/AVR-ArduinoMega-GCC/main.c new file mode 100644 index 000000000..4ee520dd0 --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/main.c @@ -0,0 +1,61 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static WORKING_AREA(waThread1, 32); +static msg_t Thread1(void *arg) { + + while (TRUE) { + palTogglePad(IOPORT2, PORTB_LED1); + chThdSleepMilliseconds(1000); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + palClearPad(IOPORT2, PORTB_LED1); + sdStart(&SD1, NULL); + + /* + * Starts the LED blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + TestThread(&SD1); + while(TRUE) { + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/AVR-ArduinoMega-GCC/mcuconf.h b/demos/AVR-ArduinoMega-GCC/mcuconf.h new file mode 100644 index 000000000..66f346fc0 --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/mcuconf.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AVR drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_AVR_USART0 TRUE +#define USE_AVR_USART1 FALSE + +/* + * SPI driver system settings. + */ diff --git a/demos/AVR-ArduinoMega-GCC/readme.txt b/demos/AVR-ArduinoMega-GCC/readme.txt new file mode 100644 index 000000000..2a1524da7 --- /dev/null +++ b/demos/AVR-ArduinoMega-GCC/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for Atmel AVR ATmega1280. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Arduino Mega board. + +** The Demo ** + +The demo currently just prints the TestThread output on Serial0, which is +available on the board USB connector (FT232 converter), and toggles the LED +on PB7 (pin 13 on Arduino IDE) every second. + +** Build Procedure ** + +The demo was built using the GCC AVR toolchain. It should build with WinAVR too! + +** Notes ** + +This demo runs natively so the Arduino bootloader must be removed and the FUSEs +reprogrammed. The values used for fuses are LFUSE=0xe7 and HFUSE=0x99. diff --git a/demos/MSP430-MSP430F5437/Makefile b/demos/MSP430-MSP430F5437/Makefile new file mode 100644 index 000000000..555794276 --- /dev/null +++ b/demos/MSP430-MSP430F5437/Makefile @@ -0,0 +1,157 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = no +endif + +# Enable register caching optimization (read documentation). +# Option not tested on MSP430, DO NOT USE. +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = msp430.x + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/NONSTANDARD_MSP430_F5437/board.mk +include $(CHIBIOS)/os/hal/platforms/MSP430X/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/common/MSP430X/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = msp430x5437 + +TRGT = msp430- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -D__MSP430F5437__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/common/MSP430X/rules.mk diff --git a/demos/MSP430-MSP430F5437/chconf.h b/demos/MSP430-MSP430F5437/chconf.h new file mode 100644 index 000000000..43dadd686 --- /dev/null +++ b/demos/MSP430-MSP430F5437/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 250 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 /* 2048 byte RAM seems to be ok in case of not providing @p __heap_base__ and @p __heap_end__ symbols */ +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/MSP430-MSP430F5437/halconf.h b/demos/MSP430-MSP430F5437/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/MSP430-MSP430F5437/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/MSP430-MSP430F5437/iar/asmdefines.s43 b/demos/MSP430-MSP430F5437/iar/asmdefines.s43 new file mode 100644 index 000000000..b5f5eb428 --- /dev/null +++ b/demos/MSP430-MSP430F5437/iar/asmdefines.s43 @@ -0,0 +1,38 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#define _FROM_ASM_ + +PUBLIC __heap_base__ +PUBLIC __heap_end__ + +#if defined(__MSP430F5437__) +// Read/write memory (RAM) on MSP430F5437: 0x01C00-0x05BFF + +ORG 0x01C00 +__heap_base__: + +ORG 0x05BFF +__heap_end__: +#else +#error "Unspecified __heap_base__ and __heap_end__ symbols." +#endif + +END diff --git a/demos/MSP430-MSP430F5437/iar/ch.ewp b/demos/MSP430-MSP430F5437/iar/ch.ewp new file mode 100644 index 000000000..ad77cd6ec --- /dev/null +++ b/demos/MSP430-MSP430F5437/iar/ch.ewp @@ -0,0 +1,2229 @@ + + + + 2 + + Debug + + MSP430 + + 1 + + General + 7 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICC430 + 4 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A430 + 4 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 4 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 4 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + MSP430 + + 0 + + General + 7 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICC430 + 4 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A430 + 4 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 4 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 4 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\NONSTANDARD_MSP430_F5437\board.c + + + $PROJ_DIR$\..\..\..\boards\NONSTANDARD_MSP430_F5437\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + platform + + F5XX_F6XX_CORE_LIB + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_FLASH.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_FLASH.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_MACROS.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_PMAP.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_PMAP.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_PMM.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5XX_F6XX_CORE_LIB\HAL_PMM.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_TLV.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_TLV.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5xx_F6xx_Core_Lib\HAL_UCS.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\F5XX_F6XX_CORE_LIB\HAL_UCS.h + + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\MSP430X\serial_lld.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + ports + + $PROJ_DIR$\..\..\..\os\ports\common\MSP430X\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\common\MSP430X\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\common\MSP430X\chtypes.h + + + + various + + $PROJ_DIR$\..\..\..\os\various\chprintf.c + + + $PROJ_DIR$\..\..\..\os\various\chprintf.h + + + $PROJ_DIR$\..\..\..\os\various\evtimer.c + + + $PROJ_DIR$\..\..\..\os\various\evtimer.h + + + $PROJ_DIR$\..\..\..\os\various\shell.c + + + $PROJ_DIR$\..\..\..\os\various\shell.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\asmdefines.s43 + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + $PROJ_DIR$\..\readme.txt + + + + diff --git a/demos/MSP430-MSP430F5437/iar/ch.eww b/demos/MSP430-MSP430F5437/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/MSP430-MSP430F5437/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/MSP430-MSP430F5437/main.c b/demos/MSP430-MSP430F5437/main.c new file mode 100644 index 000000000..1b2d3c98a --- /dev/null +++ b/demos/MSP430-MSP430F5437/main.c @@ -0,0 +1,184 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "chprintf.h" +#include "shell.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("red blinker"); + + while (TRUE) { + palSetPad(IOPORT6, P6_O_RED_LED); + chThdSleepMilliseconds(500); + palClearPad(IOPORT6, P6_O_RED_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Green LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 64); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("green blinker"); + + while (TRUE) { + palSetPad(IOPORT6, P6_O_GREEN_LED); + chThdSleepMilliseconds(1500); + palClearPad(IOPORT6, P6_O_GREEN_LED); + chThdSleepMilliseconds(1500); + } + return 0; +} + +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + + TestThread(chp); +} + +static void cmd_reboot(BaseChannel *chp, int argc, char *argv[]){ + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: rboot\r\n"); + return; + } + chprintf(chp, "rebooting...\r\n"); + chThdSleepMilliseconds(100); + + WDTCTL = 0; /* Giving invalid value to watchdog cause reboot. */ +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"reboot", cmd_reboot}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg[] = { + {(BaseChannel *)&SD1, commands}, + {(BaseChannel *)&SD2, commands}, +}; + +/* + * Application entry point. + */ +int main(void) { + + /* RTC initially stopped.*/ + WDTCTL = WDTPW | WDTHOLD; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); + + /* Shell manager initialization.*/ + shellInit(); + static WORKING_AREA(waShell1, 512); + shellCreateStatic(&shell_cfg[0], waShell1, sizeof(waShell1), NORMALPRIO); + static WORKING_AREA(waShell2, 512); + shellCreateStatic(&shell_cfg[1], waShell2, sizeof(waShell2), NORMALPRIO); + + /* Creates the blinker thread. */ + Thread *th[] = { + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO+1, Thread1, NULL), + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO+2, Thread2, NULL), + }; + + cnt_t idx; + for( idx = 0; idx < sizeof(th)/sizeof(th[0]); ++idx ) { + msg_t msg = chThdWait(th[idx]); + } + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/MSP430-MSP430F5437/mcuconf.h b/demos/MSP430-MSP430F5437/mcuconf.h new file mode 100644 index 000000000..1435b9986 --- /dev/null +++ b/demos/MSP430-MSP430F5437/mcuconf.h @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * MSP430 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL driver system settings. + */ +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_DCOCLK + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_MSP430_USART0 TRUE +#define USE_MSP430_USART1 TRUE + +/* + * SPI driver system settings. + */ diff --git a/demos/MSP430-MSP430F5437/memory.x b/demos/MSP430-MSP430F5437/memory.x new file mode 100644 index 000000000..63d41777c --- /dev/null +++ b/demos/MSP430-MSP430F5437/memory.x @@ -0,0 +1,29 @@ +MEMORY { + sfr : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0 /* END=0x0100, size 240 */ + peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100 /* END=0x0200, size 256 */ + bsl : ORIGIN = 0x1000, LENGTH = 0x0800 /* END=0x1800, size 2K as 4 512-byte segments */ + infomem : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x1a00, size 512 as 4 128-byte segments */ + infod : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x1880, size 128 */ + infoc : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x1900, size 128 */ + infob : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x1980, size 128 */ + infoa : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x1a00, size 128 */ + ram (wx) : ORIGIN = 0x1c00, LENGTH = 0x4000 /* END=0x5c00, size 16K */ + rom (rx) : ORIGIN = 0x5c00, LENGTH = 0xa380 /* END=0xff80, size 41856 */ + vectors : ORIGIN = 0xff80, LENGTH = 0x0080 /* END=0x10000, size 128 as 64 2-byte segments */ + far_rom : ORIGIN = 0x00010000, LENGTH = 0x00035c00 /* END=0x00045c00, size 215K */ + /* Remaining banks are absent */ + ram2 (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + ram_mirror (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + usbram (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 +} +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_FAR_ROM", far_rom); +PROVIDE (__info_segment_size = 0x80); +PROVIDE (__infod = 0x1800); +PROVIDE (__infoc = 0x1880); +PROVIDE (__infob = 0x1900); +PROVIDE (__infoa = 0x1980); +PROVIDE (__heap_base__ = 0x01C00); +PROVIDE (__heap_end__ = 0x05BFF); diff --git a/demos/MSP430-MSP430F5437/msp430.x b/demos/MSP430-MSP430F5437/msp430.x new file mode 100644 index 000000000..f314f76c3 --- /dev/null +++ b/demos/MSP430-MSP430F5437/msp430.x @@ -0,0 +1,184 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430") +OUTPUT_ARCH("msp430") +INCLUDE memory.x +INCLUDE periph.x +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .text : + { + . = ALIGN(2); + KEEP(*(.init .init.*)) + KEEP(*(.init0)) /* Start here after reset. */ + KEEP(*(.init1)) /* User definable. */ + KEEP(*(.init2)) /* Initialize stack. */ + KEEP(*(.init3)) /* Initialize hardware, user definable. */ + KEEP(*(.init4)) /* Copy data to .data, clear bss. */ + KEEP(*(.init5)) /* User definable. */ + KEEP(*(.init6)) /* C++ constructors. */ + KEEP(*(.init7)) /* User definable. */ + KEEP(*(.init8)) /* User definable. */ + KEEP(*(.init9)) /* Call main(). */ + KEEP(*(.fini9)) /* Falls into here after main(). User definable. */ + KEEP(*(.fini8)) /* User definable. */ + KEEP(*(.fini7)) /* User definable. */ + KEEP(*(.fini6)) /* C++ destructors. */ + KEEP(*(.fini5)) /* User definable. */ + KEEP(*(.fini4)) /* User definable. */ + KEEP(*(.fini3)) /* User definable. */ + KEEP(*(.fini2)) /* User definable. */ + KEEP(*(.fini1)) /* User definable. */ + KEEP(*(.fini0)) /* Infinite loop after program termination. */ + KEEP(*(.fini .fini.*)) + . = ALIGN(2); + __ctors_start = . ; + KEEP(*(.ctors)) + __ctors_end = . ; + __dtors_start = . ; + KEEP(*(.dtors)) + __dtors_end = . ; + . = ALIGN(2); + *(.text .text.* .gnu.linkonce.t.*) + . = ALIGN(2); + } > REGION_TEXT + .rodata : + { + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.*) + . = ALIGN(2); + } > REGION_TEXT + _etext = .; /* Past last read-only (loadable) segment */ + .data : + { + . = ALIGN(2); + PROVIDE (__data_start = .) ; + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN(2); + _edata = . ; /* Past last read-write (loadable) segment */ + } > REGION_DATA AT > REGION_TEXT + PROVIDE (__data_load_start = LOADADDR(.data) ); + PROVIDE (__data_size = SIZEOF(.data) ); + .bss : + { + PROVIDE (__bss_start = .) ; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(2); + PROVIDE (__bss_end = .) ; + } > REGION_DATA + PROVIDE (__bss_size = SIZEOF(.bss) ); + .noinit : + { + PROVIDE (__noinit_start = .) ; + *(.noinit .noinit.*) + . = ALIGN(2); + PROVIDE (__noinit_end = .) ; + } > REGION_DATA + . = ALIGN(2); + _end = . ; /* Past last write (loadable) segment */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + .infomemnobits : + { + *(.infomemnobits) + . = ALIGN(2); + *(.infomemnobits.*) + } > infomem + .infoa : + { + *(.infoa .infoa.*) + } > infoa + .infob : + { + *(.infob .infob.*) + } > infob + .infoc : + { + *(.infoc .infoc.*) + } > infoc + .infod : + { + *(.infod .infod.*) + } > infod + .vectors : + { + PROVIDE (__vectors_start = .) ; + KEEP(*(.vectors*)) + _vectors_end = . ; + } > vectors + .fartext : + { + . = ALIGN(2); + *(.fartext) + . = ALIGN(2); + *(.fartext.*) + _efartext = .; + } > REGION_FAR_ROM + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram)); + PROVIDE (__data_start_rom = _etext); + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)); +} diff --git a/demos/MSP430-MSP430F5437/periph.x b/demos/MSP430-MSP430F5437/periph.x new file mode 100644 index 000000000..6df73045c --- /dev/null +++ b/demos/MSP430-MSP430F5437/periph.x @@ -0,0 +1,579 @@ +__ADC12CTL0_L = 0x0700; +__ADC12CTL0_H = 0x0701; +__ADC12CTL0 = 0x0700; +__ADC12CTL1_L = 0x0702; +__ADC12CTL1_H = 0x0703; +__ADC12CTL1 = 0x0702; +__ADC12CTL2_L = 0x0704; +__ADC12CTL2_H = 0x0705; +__ADC12CTL2 = 0x0704; +__ADC12IFG_L = 0x070A; +__ADC12IFG_H = 0x070B; +__ADC12IFG = 0x070A; +__ADC12IE_L = 0x070C; +__ADC12IE_H = 0x070D; +__ADC12IE = 0x070C; +__ADC12IV_L = 0x070E; +__ADC12IV_H = 0x070F; +__ADC12IV = 0x070E; +__ADC12MEM0_L = 0x0720; +__ADC12MEM0_H = 0x0721; +__ADC12MEM0 = 0x0720; +__ADC12MEM1_L = 0x0722; +__ADC12MEM1_H = 0x0723; +__ADC12MEM1 = 0x0722; +__ADC12MEM2_L = 0x0724; +__ADC12MEM2_H = 0x0725; +__ADC12MEM2 = 0x0724; +__ADC12MEM3_L = 0x0726; +__ADC12MEM3_H = 0x0727; +__ADC12MEM3 = 0x0726; +__ADC12MEM4_L = 0x0728; +__ADC12MEM4_H = 0x0729; +__ADC12MEM4 = 0x0728; +__ADC12MEM5_L = 0x072A; +__ADC12MEM5_H = 0x072B; +__ADC12MEM5 = 0x072A; +__ADC12MEM6_L = 0x072C; +__ADC12MEM6_H = 0x072D; +__ADC12MEM6 = 0x072C; +__ADC12MEM7_L = 0x072E; +__ADC12MEM7_H = 0x072F; +__ADC12MEM7 = 0x072E; +__ADC12MEM8_L = 0x0730; +__ADC12MEM8_H = 0x0731; +__ADC12MEM8 = 0x0730; +__ADC12MEM9_L = 0x0732; +__ADC12MEM9_H = 0x0733; +__ADC12MEM9 = 0x0732; +__ADC12MEM10_L = 0x0734; +__ADC12MEM10_H = 0x0735; +__ADC12MEM10 = 0x0734; +__ADC12MEM11_L = 0x0736; +__ADC12MEM11_H = 0x0737; +__ADC12MEM11 = 0x0736; +__ADC12MEM12_L = 0x0738; +__ADC12MEM12_H = 0x0739; +__ADC12MEM12 = 0x0738; +__ADC12MEM13_L = 0x073A; +__ADC12MEM13_H = 0x073B; +__ADC12MEM13 = 0x073A; +__ADC12MEM14_L = 0x073C; +__ADC12MEM14_H = 0x073D; +__ADC12MEM14 = 0x073C; +__ADC12MEM15_L = 0x073E; +__ADC12MEM15_H = 0x073F; +__ADC12MEM15 = 0x073E; +__ADC12MCTL0 = 0x0710; +__ADC12MCTL1 = 0x0711; +__ADC12MCTL2 = 0x0712; +__ADC12MCTL3 = 0x0713; +__ADC12MCTL4 = 0x0714; +__ADC12MCTL5 = 0x0715; +__ADC12MCTL6 = 0x0716; +__ADC12MCTL7 = 0x0717; +__ADC12MCTL8 = 0x0718; +__ADC12MCTL9 = 0x0719; +__ADC12MCTL10 = 0x071A; +__ADC12MCTL11 = 0x071B; +__ADC12MCTL12 = 0x071C; +__ADC12MCTL13 = 0x071D; +__ADC12MCTL14 = 0x071E; +__ADC12MCTL15 = 0x071F; +__CRCDI_L = 0x0150; +__CRCDI_H = 0x0151; +__CRCDI = 0x0150; +__CRCINIRES_L = 0x0154; +__CRCINIRES_H = 0x0155; +__CRCINIRES = 0x0154; +__DMACTL0_L = 0x0500; +__DMACTL0_H = 0x0501; +__DMACTL0 = 0x0500; +__DMACTL1_L = 0x0502; +__DMACTL1_H = 0x0503; +__DMACTL1 = 0x0502; +__DMACTL2_L = 0x0504; +__DMACTL2_H = 0x0505; +__DMACTL2 = 0x0504; +__DMACTL3_L = 0x0506; +__DMACTL3_H = 0x0507; +__DMACTL3 = 0x0506; +__DMACTL4_L = 0x0508; +__DMACTL4_H = 0x0509; +__DMACTL4 = 0x0508; +__DMAIV_L = 0x050E; +__DMAIV_H = 0x050F; +__DMAIV = 0x050E; +__DMA0CTL_L = 0x0510; +__DMA0CTL_H = 0x0511; +__DMA0CTL = 0x0510; +__DMA0SA = 0x0512; +__DMA0DA = 0x0516; +__DMA0SZ = 0x051A; +__DMA1CTL_L = 0x0520; +__DMA1CTL_H = 0x0521; +__DMA1CTL = 0x0520; +__DMA1SA = 0x0522; +__DMA1DA = 0x0526; +__DMA1SZ = 0x052A; +__DMA2CTL_L = 0x0530; +__DMA2CTL_H = 0x0531; +__DMA2CTL = 0x0530; +__DMA2SA = 0x0532; +__DMA2DA = 0x0536; +__DMA2SZ = 0x053A; +__FCTL1_L = 0x0140; +__FCTL1_H = 0x0141; +__FCTL1 = 0x0140; +__FCTL3_L = 0x0144; +__FCTL3_H = 0x0145; +__FCTL3 = 0x0144; +__FCTL4_L = 0x0146; +__FCTL4_H = 0x0147; +__FCTL4 = 0x0146; +__MPY_L = 0x04C0; +__MPY_H = 0x04C1; +__MPY = 0x04C0; +__MPYS_L = 0x04C2; +__MPYS_H = 0x04C3; +__MPYS = 0x04C2; +__MAC_L = 0x04C4; +__MAC_H = 0x04C5; +__MAC = 0x04C4; +__MACS_L = 0x04C6; +__MACS_H = 0x04C7; +__MACS = 0x04C6; +__OP2_L = 0x04C8; +__OP2_H = 0x04C9; +__OP2 = 0x04C8; +__RESLO_L = 0x04CA; +__RESLO_H = 0x04CB; +__RESLO = 0x04CA; +__RESHI_L = 0x04CC; +__RESHI_H = 0x04CD; +__RESHI = 0x04CC; +__SUMEXT_L = 0x04CE; +__SUMEXT_H = 0x04CF; +__SUMEXT = 0x04CE; +__MPY32L_L = 0x04D0; +__MPY32L_H = 0x04D1; +__MPY32L = 0x04D0; +__MPY32H_L = 0x04D2; +__MPY32H_H = 0x04D3; +__MPY32H = 0x04D2; +__MPYS32L_L = 0x04D4; +__MPYS32L_H = 0x04D5; +__MPYS32L = 0x04D4; +__MPYS32H_L = 0x04D6; +__MPYS32H_H = 0x04D7; +__MPYS32H = 0x04D6; +__MAC32L_L = 0x04D8; +__MAC32L_H = 0x04D9; +__MAC32L = 0x04D8; +__MAC32H_L = 0x04DA; +__MAC32H_H = 0x04DB; +__MAC32H = 0x04DA; +__MACS32L_L = 0x04DC; +__MACS32L_H = 0x04DD; +__MACS32L = 0x04DC; +__MACS32H_L = 0x04DE; +__MACS32H_H = 0x04DF; +__MACS32H = 0x04DE; +__OP2L_L = 0x04E0; +__OP2L_H = 0x04E1; +__OP2L = 0x04E0; +__OP2H_L = 0x04E2; +__OP2H_H = 0x04E3; +__OP2H = 0x04E2; +__RES0_L = 0x04E4; +__RES0_H = 0x04E5; +__RES0 = 0x04E4; +__RES1_L = 0x04E6; +__RES1_H = 0x04E7; +__RES1 = 0x04E6; +__RES2_L = 0x04E8; +__RES2_H = 0x04E9; +__RES2 = 0x04E8; +__RES3_L = 0x04EA; +__RES3_H = 0x04EB; +__RES3 = 0x04EA; +__MPY32CTL0_L = 0x04EC; +__MPY32CTL0_H = 0x04ED; +__MPY32CTL0 = 0x04EC; +__PAIN_L = 0x0200; +__PAIN_H = 0x0201; +__PAIN = 0x0200; +__PAOUT_L = 0x0202; +__PAOUT_H = 0x0203; +__PAOUT = 0x0202; +__PADIR_L = 0x0204; +__PADIR_H = 0x0205; +__PADIR = 0x0204; +__PAREN_L = 0x0206; +__PAREN_H = 0x0207; +__PAREN = 0x0206; +__PADS_L = 0x0208; +__PADS_H = 0x0209; +__PADS = 0x0208; +__PASEL_L = 0x020A; +__PASEL_H = 0x020B; +__PASEL = 0x020A; +__PAIES_L = 0x0218; +__PAIES_H = 0x0219; +__PAIES = 0x0218; +__PAIE_L = 0x021A; +__PAIE_H = 0x021B; +__PAIE = 0x021A; +__PAIFG_L = 0x021C; +__PAIFG_H = 0x021D; +__PAIFG = 0x021C; +__P1IV = 0x020E; +__P2IV = 0x021E; +__PBIN_L = 0x0220; +__PBIN_H = 0x0221; +__PBIN = 0x0220; +__PBOUT_L = 0x0222; +__PBOUT_H = 0x0223; +__PBOUT = 0x0222; +__PBDIR_L = 0x0224; +__PBDIR_H = 0x0225; +__PBDIR = 0x0224; +__PBREN_L = 0x0226; +__PBREN_H = 0x0227; +__PBREN = 0x0226; +__PBDS_L = 0x0228; +__PBDS_H = 0x0229; +__PBDS = 0x0228; +__PBSEL_L = 0x022A; +__PBSEL_H = 0x022B; +__PBSEL = 0x022A; +__PCIN_L = 0x0240; +__PCIN_H = 0x0241; +__PCIN = 0x0240; +__PCOUT_L = 0x0242; +__PCOUT_H = 0x0243; +__PCOUT = 0x0242; +__PCDIR_L = 0x0244; +__PCDIR_H = 0x0245; +__PCDIR = 0x0244; +__PCREN_L = 0x0246; +__PCREN_H = 0x0247; +__PCREN = 0x0246; +__PCDS_L = 0x0248; +__PCDS_H = 0x0249; +__PCDS = 0x0248; +__PCSEL_L = 0x024A; +__PCSEL_H = 0x024B; +__PCSEL = 0x024A; +__PDIN_L = 0x0260; +__PDIN_H = 0x0261; +__PDIN = 0x0260; +__PDOUT_L = 0x0262; +__PDOUT_H = 0x0263; +__PDOUT = 0x0262; +__PDDIR_L = 0x0264; +__PDDIR_H = 0x0265; +__PDDIR = 0x0264; +__PDREN_L = 0x0266; +__PDREN_H = 0x0267; +__PDREN = 0x0266; +__PDDS_L = 0x0268; +__PDDS_H = 0x0269; +__PDDS = 0x0268; +__PDSEL_L = 0x026A; +__PDSEL_H = 0x026B; +__PDSEL = 0x026A; +__PEIN_L = 0x0280; +__PEIN_H = 0x0281; +__PEIN = 0x0280; +__PEOUT_L = 0x0282; +__PEOUT_H = 0x0283; +__PEOUT = 0x0282; +__PEDIR_L = 0x0284; +__PEDIR_H = 0x0285; +__PEDIR = 0x0284; +__PEREN_L = 0x0286; +__PEREN_H = 0x0287; +__PEREN = 0x0286; +__PEDS_L = 0x0288; +__PEDS_H = 0x0289; +__PEDS = 0x0288; +__PESEL_L = 0x028A; +__PESEL_H = 0x028B; +__PESEL = 0x028A; +__PFIN_L = 0x02A0; +__PFIN_H = 0x02A1; +__PFIN = 0x02A0; +__PFOUT_L = 0x02A2; +__PFOUT_H = 0x02A3; +__PFOUT = 0x02A2; +__PFDIR_L = 0x02A4; +__PFDIR_H = 0x02A5; +__PFDIR = 0x02A4; +__PFREN_L = 0x02A6; +__PFREN_H = 0x02A7; +__PFREN = 0x02A6; +__PFDS_L = 0x02A8; +__PFDS_H = 0x02A9; +__PFDS = 0x02A8; +__PFSEL_L = 0x02AA; +__PFSEL_H = 0x02AB; +__PFSEL = 0x02AA; +__PJIN_L = 0x0320; +__PJIN_H = 0x0321; +__PJIN = 0x0320; +__PJOUT_L = 0x0322; +__PJOUT_H = 0x0323; +__PJOUT = 0x0322; +__PJDIR_L = 0x0324; +__PJDIR_H = 0x0325; +__PJDIR = 0x0324; +__PJREN_L = 0x0326; +__PJREN_H = 0x0327; +__PJREN = 0x0326; +__PJDS_L = 0x0328; +__PJDS_H = 0x0329; +__PJDS = 0x0328; +__PMMCTL0_L = 0x0120; +__PMMCTL0_H = 0x0121; +__PMMCTL0 = 0x0120; +__PMMCTL1_L = 0x0122; +__PMMCTL1_H = 0x0123; +__PMMCTL1 = 0x0122; +__SVSMHCTL_L = 0x0124; +__SVSMHCTL_H = 0x0125; +__SVSMHCTL = 0x0124; +__SVSMLCTL_L = 0x0126; +__SVSMLCTL_H = 0x0127; +__SVSMLCTL = 0x0126; +__SVSMIO_L = 0x0128; +__SVSMIO_H = 0x0129; +__SVSMIO = 0x0128; +__PMMIFG_L = 0x012C; +__PMMIFG_H = 0x012D; +__PMMIFG = 0x012C; +__PMMRIE_L = 0x012E; +__PMMRIE_H = 0x012F; +__PMMRIE = 0x012E; +__RCCTL0_L = 0x0158; +__RCCTL0_H = 0x0159; +__RCCTL0 = 0x0158; +__RTCCTL01_L = 0x04A0; +__RTCCTL01_H = 0x04A1; +__RTCCTL01 = 0x04A0; +__RTCCTL23_L = 0x04A2; +__RTCCTL23_H = 0x04A3; +__RTCCTL23 = 0x04A2; +__RTCPS0CTL_L = 0x04A8; +__RTCPS0CTL_H = 0x04A9; +__RTCPS0CTL = 0x04A8; +__RTCPS1CTL_L = 0x04AA; +__RTCPS1CTL_H = 0x04AB; +__RTCPS1CTL = 0x04AA; +__RTCPS_L = 0x04AC; +__RTCPS_H = 0x04AD; +__RTCPS = 0x04AC; +__RTCIV = 0x04AE; +__RTCTIM0_L = 0x04B0; +__RTCTIM0_H = 0x04B1; +__RTCTIM0 = 0x04B0; +__RTCTIM1_L = 0x04B2; +__RTCTIM1_H = 0x04B3; +__RTCTIM1 = 0x04B2; +__RTCDATE_L = 0x04B4; +__RTCDATE_H = 0x04B5; +__RTCDATE = 0x04B4; +__RTCYEAR_L = 0x04B6; +__RTCYEAR_H = 0x04B7; +__RTCYEAR = 0x04B6; +__RTCAMINHR_L = 0x04B8; +__RTCAMINHR_H = 0x04B9; +__RTCAMINHR = 0x04B8; +__RTCADOWDAY_L = 0x04BA; +__RTCADOWDAY_H = 0x04BB; +__RTCADOWDAY = 0x04BA; +__SFRIE1_L = 0x0100; +__SFRIE1_H = 0x0101; +__SFRIE1 = 0x0100; +__SFRIFG1_L = 0x0102; +__SFRIFG1_H = 0x0103; +__SFRIFG1 = 0x0102; +__SFRRPCR_L = 0x0104; +__SFRRPCR_H = 0x0105; +__SFRRPCR = 0x0104; +__SYSCTL_L = 0x0180; +__SYSCTL_H = 0x0181; +__SYSCTL = 0x0180; +__SYSBSLC_L = 0x0182; +__SYSBSLC_H = 0x0183; +__SYSBSLC = 0x0182; +__SYSJMBC_L = 0x0186; +__SYSJMBC_H = 0x0187; +__SYSJMBC = 0x0186; +__SYSJMBI0_L = 0x0188; +__SYSJMBI0_H = 0x0189; +__SYSJMBI0 = 0x0188; +__SYSJMBI1_L = 0x018A; +__SYSJMBI1_H = 0x018B; +__SYSJMBI1 = 0x018A; +__SYSJMBO0_L = 0x018C; +__SYSJMBO0_H = 0x018D; +__SYSJMBO0 = 0x018C; +__SYSJMBO1_L = 0x018E; +__SYSJMBO1_H = 0x018F; +__SYSJMBO1 = 0x018E; +__SYSUNIV_L = 0x019A; +__SYSUNIV_H = 0x019B; +__SYSUNIV = 0x019A; +__SYSSNIV_L = 0x019C; +__SYSSNIV_H = 0x019D; +__SYSSNIV = 0x019C; +__SYSRSTIV_L = 0x019E; +__SYSRSTIV_H = 0x019F; +__SYSRSTIV = 0x019E; +__TA0CTL = 0x0340; +__TA0CCTL0 = 0x0342; +__TA0CCTL1 = 0x0344; +__TA0CCTL2 = 0x0346; +__TA0CCTL3 = 0x0348; +__TA0CCTL4 = 0x034A; +__TA0R = 0x0350; +__TA0CCR0 = 0x0352; +__TA0CCR1 = 0x0354; +__TA0CCR2 = 0x0356; +__TA0CCR3 = 0x0358; +__TA0CCR4 = 0x035A; +__TA0IV = 0x036E; +__TA0EX0 = 0x0360; +__TA1CTL = 0x0380; +__TA1CCTL0 = 0x0382; +__TA1CCTL1 = 0x0384; +__TA1CCTL2 = 0x0386; +__TA1R = 0x0390; +__TA1CCR0 = 0x0392; +__TA1CCR1 = 0x0394; +__TA1CCR2 = 0x0396; +__TA1IV = 0x03AE; +__TA1EX0 = 0x03A0; +__TB0CTL = 0x03C0; +__TB0CCTL0 = 0x03C2; +__TB0CCTL1 = 0x03C4; +__TB0CCTL2 = 0x03C6; +__TB0CCTL3 = 0x03C8; +__TB0CCTL4 = 0x03CA; +__TB0CCTL5 = 0x03CC; +__TB0CCTL6 = 0x03CE; +__TB0R = 0x03D0; +__TB0CCR0 = 0x03D2; +__TB0CCR1 = 0x03D4; +__TB0CCR2 = 0x03D6; +__TB0CCR3 = 0x03D8; +__TB0CCR4 = 0x03DA; +__TB0CCR5 = 0x03DC; +__TB0CCR6 = 0x03DE; +__TB0EX0 = 0x03E0; +__TB0IV = 0x03EE; +__UCSCTL0_L = 0x0160; +__UCSCTL0_H = 0x0161; +__UCSCTL0 = 0x0160; +__UCSCTL1_L = 0x0162; +__UCSCTL1_H = 0x0163; +__UCSCTL1 = 0x0162; +__UCSCTL2_L = 0x0164; +__UCSCTL2_H = 0x0165; +__UCSCTL2 = 0x0164; +__UCSCTL3_L = 0x0166; +__UCSCTL3_H = 0x0167; +__UCSCTL3 = 0x0166; +__UCSCTL4_L = 0x0168; +__UCSCTL4_H = 0x0169; +__UCSCTL4 = 0x0168; +__UCSCTL5_L = 0x016A; +__UCSCTL5_H = 0x016B; +__UCSCTL5 = 0x016A; +__UCSCTL6_L = 0x016C; +__UCSCTL6_H = 0x016D; +__UCSCTL6 = 0x016C; +__UCSCTL7_L = 0x016E; +__UCSCTL7_H = 0x016F; +__UCSCTL7 = 0x016E; +__UCSCTL8_L = 0x0170; +__UCSCTL8_H = 0x0171; +__UCSCTL8 = 0x0170; +__UCA0CTLW0_L = 0x05C0; +__UCA0CTLW0_H = 0x05C1; +__UCA0CTLW0 = 0x05C0; +__UCA0BRW_L = 0x05C6; +__UCA0BRW_H = 0x05C7; +__UCA0BRW = 0x05C6; +__UCA0MCTL = 0x05C8; +__UCA0STAT = 0x05CA; +__UCA0RXBUF = 0x05CC; +__UCA0TXBUF = 0x05CE; +__UCA0ABCTL = 0x05D0; +__UCA0IRCTL_L = 0x05D2; +__UCA0IRCTL_H = 0x05D3; +__UCA0IRCTL = 0x05D2; +__UCA0ICTL_L = 0x05DC; +__UCA0ICTL_H = 0x05DD; +__UCA0ICTL = 0x05DC; +__UCA0IV = 0x05DE; +__UCB0CTLW0_L = 0x05E0; +__UCB0CTLW0_H = 0x05E1; +__UCB0CTLW0 = 0x05E0; +__UCB0BRW_L = 0x05E6; +__UCB0BRW_H = 0x05E7; +__UCB0BRW = 0x05E6; +__UCB0STAT = 0x05EA; +__UCB0RXBUF = 0x05EC; +__UCB0TXBUF = 0x05EE; +__UCB0I2COA_L = 0x05F0; +__UCB0I2COA_H = 0x05F1; +__UCB0I2COA = 0x05F0; +__UCB0I2CSA_L = 0x05F2; +__UCB0I2CSA_H = 0x05F3; +__UCB0I2CSA = 0x05F2; +__UCB0ICTL_L = 0x05FC; +__UCB0ICTL_H = 0x05FD; +__UCB0ICTL = 0x05FC; +__UCB0IV = 0x05FE; +__UCA1CTLW0_L = 0x0600; +__UCA1CTLW0_H = 0x0601; +__UCA1CTLW0 = 0x0600; +__UCA1BRW_L = 0x0606; +__UCA1BRW_H = 0x0607; +__UCA1BRW = 0x0606; +__UCA1MCTL = 0x0608; +__UCA1STAT = 0x060A; +__UCA1RXBUF = 0x060C; +__UCA1TXBUF = 0x060E; +__UCA1ABCTL = 0x0610; +__UCA1IRCTL_L = 0x0612; +__UCA1IRCTL_H = 0x0613; +__UCA1IRCTL = 0x0612; +__UCA1ICTL_L = 0x061C; +__UCA1ICTL_H = 0x061D; +__UCA1ICTL = 0x061C; +__UCA1IV = 0x061E; +__UCB1CTLW0_L = 0x0620; +__UCB1CTLW0_H = 0x0621; +__UCB1CTLW0 = 0x0620; +__UCB1BRW_L = 0x0626; +__UCB1BRW_H = 0x0627; +__UCB1BRW = 0x0626; +__UCB1STAT = 0x062A; +__UCB1RXBUF = 0x062C; +__UCB1TXBUF = 0x062E; +__UCB1I2COA_L = 0x0630; +__UCB1I2COA_H = 0x0631; +__UCB1I2COA = 0x0630; +__UCB1I2CSA_L = 0x0632; +__UCB1I2CSA_H = 0x0633; +__UCB1I2CSA = 0x0632; +__UCB1ICTL_L = 0x063C; +__UCB1ICTL_H = 0x063D; +__UCB1ICTL = 0x063C; +__UCB1IV = 0x063E; +__WDTCTL_L = 0x015C; +__WDTCTL_H = 0x015D; +__WDTCTL = 0x015C; diff --git a/demos/MSP430-MSP430F5437/readme.txt b/demos/MSP430-MSP430F5437/readme.txt new file mode 100644 index 000000000..164002431 --- /dev/null +++ b/demos/MSP430-MSP430F5437/readme.txt @@ -0,0 +1,29 @@ +***************************************************************************** +** ChibiOS/RT port for Texas Instruments MSP430X. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an customized MSP430-F5437 board with a 32768kHz XTAL1 +installed. DCOCLK (=MCLK, =SMCLK) is set up to 20Mhz. From mcuconf.h: +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_DCOCLK + +UART0 (38400/8N1) ist used for printing some board information. + +** The Demo ** + +The demo runs first some tests, just to check port correctness. Meanwhile, +green led light. After that the board red and green leds will flash in the +cycle of ~0.5 and ~1.5 seconds respectively. + +** Build Procedure ** + +The demo was built using the +a) IAR for MSP430 5.10.1 (5.10.1.50144) toolchain; +b) GCC version 4.6.3 20120301 (mspgcc LTS 20120406 unpatched). + +*** Notes *** + +On porting to an another MSP430X-MCU remember to check your linker settings +for __heap_base__ and __heap_end__ symbols (or redefine these in +asmdefines.s43). diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile new file mode 100644 index 000000000..f454a4500 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -0,0 +1,155 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = no +endif + +# Enable register caching optimization (read documentation). +# Option not tested on MSP430, DO NOT USE. +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = msp430.x + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_MSP430_P1611/board.mk +include $(CHIBIOS)/os/hal/platforms/MSP430/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/MSP430/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = msp430x1611 + +TRGT = msp430- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -D__MSP430F1611__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/MSP430/rules.mk diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h new file mode 100644 index 000000000..ef57bcf1e --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 512 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c new file mode 100644 index 000000000..e38c1c12a --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(IOPORT6, P6_O_LED); + chThdSleepMilliseconds(500); + palClearPad(IOPORT6, P6_O_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * checking a button and run a test suite if button was pressed. + */ + while (TRUE) { + if (!palReadPad(IOPORT6, P6_I_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/demos/MSP430-MSP430x1611-GCC/mcuconf.h new file mode 100644 index 000000000..7a3ad5f85 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/mcuconf.h @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * MSP430 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL driver system settings. + */ +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_MSP430_USART0 TRUE +#define USE_MSP430_USART1 FALSE + +/* + * SPI driver system settings. + */ diff --git a/demos/MSP430-MSP430x1611-GCC/memory.x b/demos/MSP430-MSP430x1611-GCC/memory.x new file mode 100644 index 000000000..78164e000 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/memory.x @@ -0,0 +1,25 @@ +MEMORY { + sfr : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0 /* END=0x0100, size 240 */ + peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100 /* END=0x0200, size 256 */ + ram_mirror (wx) : ORIGIN = 0x0200, LENGTH = 0x0800 /* END=0x0a00, size 2K */ + infomem : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x1100, size 256 as 2 128-byte segments */ + infob : ORIGIN = 0x1000, LENGTH = 0x0080 /* END=0x1080, size 128 */ + infoa : ORIGIN = 0x1080, LENGTH = 0x0080 /* END=0x1100, size 128 */ + ram (wx) : ORIGIN = 0x1100, LENGTH = 0x2800 /* END=0x3900, size 10K */ + rom (rx) : ORIGIN = 0x4000, LENGTH = 0xbfe0 /* END=0xffe0, size 49120 */ + vectors : ORIGIN = 0xffe0, LENGTH = 0x0020 /* END=0x10000, size 32 as 16 2-byte segments */ + /* Remaining banks are absent */ + bsl : ORIGIN = 0x0000, LENGTH = 0x0000 + infoc : ORIGIN = 0x0000, LENGTH = 0x0000 + infod : ORIGIN = 0x0000, LENGTH = 0x0000 + ram2 (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + usbram (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + far_rom : ORIGIN = 0x00000000, LENGTH = 0x00000000 +} +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_FAR_ROM", far_rom); +PROVIDE (__info_segment_size = 0x80); +PROVIDE (__infob = 0x1000); +PROVIDE (__infoa = 0x1080); diff --git a/demos/MSP430-MSP430x1611-GCC/msp430.x b/demos/MSP430-MSP430x1611-GCC/msp430.x new file mode 100644 index 000000000..c66c3a1a1 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/msp430.x @@ -0,0 +1,184 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430") +OUTPUT_ARCH("msp430") +INCLUDE memory.x +INCLUDE periph.x +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .text : + { + . = ALIGN(2); + KEEP(*(.init .init.*)) + KEEP(*(.init0)) /* Start here after reset. */ + KEEP(*(.init1)) /* User definable. */ + KEEP(*(.init2)) /* Initialize stack. */ + KEEP(*(.init3)) /* Initialize hardware, user definable. */ + KEEP(*(.init4)) /* Copy data to .data, clear bss. */ + KEEP(*(.init5)) /* User definable. */ + KEEP(*(.init6)) /* C++ constructors. */ + KEEP(*(.init7)) /* User definable. */ + KEEP(*(.init8)) /* User definable. */ + KEEP(*(.init9)) /* Call main(). */ + KEEP(*(.fini9)) /* Falls into here after main(). User definable. */ + KEEP(*(.fini8)) /* User definable. */ + KEEP(*(.fini7)) /* User definable. */ + KEEP(*(.fini6)) /* C++ destructors. */ + KEEP(*(.fini5)) /* User definable. */ + KEEP(*(.fini4)) /* User definable. */ + KEEP(*(.fini3)) /* User definable. */ + KEEP(*(.fini2)) /* User definable. */ + KEEP(*(.fini1)) /* User definable. */ + KEEP(*(.fini0)) /* Infinite loop after program termination. */ + KEEP(*(.fini .fini.*)) + . = ALIGN(2); + __ctors_start = . ; + KEEP(*(.ctors)) + __ctors_end = . ; + __dtors_start = . ; + KEEP(*(.dtors)) + __dtors_end = . ; + . = ALIGN(2); + *(.text .text.* .gnu.linkonce.t.*) + . = ALIGN(2); + } > REGION_TEXT + .rodata : + { + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.*) + . = ALIGN(2); + } > REGION_TEXT + _etext = .; /* Past last read-only (loadable) segment */ + .data : + { + . = ALIGN(2); + PROVIDE (__data_start = .) ; + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN(2); + _edata = . ; /* Past last read-write (loadable) segment */ + } > REGION_DATA AT > REGION_TEXT + PROVIDE (__data_load_start = LOADADDR(.data) ); + PROVIDE (__data_size = SIZEOF(.data) ); + .bss : + { + PROVIDE (__bss_start = .) ; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(2); + PROVIDE (__bss_end = .) ; + } > REGION_DATA + PROVIDE (__bss_size = SIZEOF(.bss) ); + .noinit : + { + PROVIDE (__noinit_start = .) ; + *(.noinit .noinit.*) + . = ALIGN(2); + PROVIDE (__noinit_end = .) ; + } > REGION_DATA + . = ALIGN(2); + _end = . ; /* Past last write (loadable) segment */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + .infomemnobits : + { + *(.infomemnobits) + . = ALIGN(2); + *(.infomemnobits.*) + } > infomem + .infoa : + { + *(.infoa .infoa.*) + } > infoa + .infob : + { + *(.infob .infob.*) + } > infob + .infoc : + { + *(.infoc .infoc.*) + } > infoc + .infod : + { + *(.infod .infod.*) + } > infod + .vectors : + { + PROVIDE (__vectors_start = .) ; + KEEP(*(.vectors*)) + _vectors_end = . ; + } > vectors + .fartext : + { + . = ALIGN(2); + *(.fartext) + . = ALIGN(2); + *(.fartext.*) + _efartext = .; + } > REGION_FAR_ROM + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram)); + PROVIDE (__data_start_rom = _etext); + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)); +} diff --git a/demos/MSP430-MSP430x1611-GCC/periph.x b/demos/MSP430-MSP430x1611-GCC/periph.x new file mode 100644 index 000000000..525d0692b --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/periph.x @@ -0,0 +1,165 @@ +__IE1 = 0x0000; +__IFG1 = 0x0002; +__ME1 = 0x0004; +__IE2 = 0x0001; +__IFG2 = 0x0003; +__ME2 = 0x0005; +__WDTCTL = 0x0120; +__MPY = 0x0130; +__MPYS = 0x0132; +__MAC = 0x0134; +__MACS = 0x0136; +__OP2 = 0x0138; +__RESLO = 0x013A; +__RESHI = 0x013C; +__SUMEXT = 0x013E; +__P1IN = 0x0020; +__P1OUT = 0x0021; +__P1DIR = 0x0022; +__P1IFG = 0x0023; +__P1IES = 0x0024; +__P1IE = 0x0025; +__P1SEL = 0x0026; +__P2IN = 0x0028; +__P2OUT = 0x0029; +__P2DIR = 0x002A; +__P2IFG = 0x002B; +__P2IES = 0x002C; +__P2IE = 0x002D; +__P2SEL = 0x002E; +__P3IN = 0x0018; +__P3OUT = 0x0019; +__P3DIR = 0x001A; +__P3SEL = 0x001B; +__P4IN = 0x001C; +__P4OUT = 0x001D; +__P4DIR = 0x001E; +__P4SEL = 0x001F; +__P5IN = 0x0030; +__P5OUT = 0x0031; +__P5DIR = 0x0032; +__P5SEL = 0x0033; +__P6IN = 0x0034; +__P6OUT = 0x0035; +__P6DIR = 0x0036; +__P6SEL = 0x0037; +__U0CTL = 0x0070; +__U0TCTL = 0x0071; +__U0RCTL = 0x0072; +__U0MCTL = 0x0073; +__U0BR0 = 0x0074; +__U0BR1 = 0x0075; +__U0RXBUF = 0x0076; +__U0TXBUF = 0x0077; +__U1CTL = 0x0078; +__U1TCTL = 0x0079; +__U1RCTL = 0x007A; +__U1MCTL = 0x007B; +__U1BR0 = 0x007C; +__U1BR1 = 0x007D; +__U1RXBUF = 0x007E; +__U1TXBUF = 0x007F; +__I2CIE = 0x0050; +__I2CIFG = 0x0051; +__I2CNDAT = 0x0052; +__I2CTCTL = 0x0071; +__I2CDCTL = 0x0072; +__I2CPSC = 0x0073; +__I2CSCLH = 0x0074; +__I2CSCLL = 0x0075; +__I2CDRB = 0x0076; +__I2CDRW = 0x0076; +__I2COA = 0x0118; +__I2CSA = 0x011A; +__I2CIV = 0x011C; +__TAIV = 0x012E; +__TACTL = 0x0160; +__TACCTL0 = 0x0162; +__TACCTL1 = 0x0164; +__TACCTL2 = 0x0166; +__TAR = 0x0170; +__TACCR0 = 0x0172; +__TACCR1 = 0x0174; +__TACCR2 = 0x0176; +__TBIV = 0x011E; +__TBCTL = 0x0180; +__TBCCTL0 = 0x0182; +__TBCCTL1 = 0x0184; +__TBCCTL2 = 0x0186; +__TBCCTL3 = 0x0188; +__TBCCTL4 = 0x018A; +__TBCCTL5 = 0x018C; +__TBCCTL6 = 0x018E; +__TBR = 0x0190; +__TBCCR0 = 0x0192; +__TBCCR1 = 0x0194; +__TBCCR2 = 0x0196; +__TBCCR3 = 0x0198; +__TBCCR4 = 0x019A; +__TBCCR5 = 0x019C; +__TBCCR6 = 0x019E; +__DCOCTL = 0x0056; +__BCSCTL1 = 0x0057; +__BCSCTL2 = 0x0058; +__SVSCTL = 0x0055; +__FCTL1 = 0x0128; +__FCTL2 = 0x012A; +__FCTL3 = 0x012C; +__CACTL1 = 0x0059; +__CACTL2 = 0x005A; +__CAPD = 0x005B; +__ADC12CTL0 = 0x01A0; +__ADC12CTL1 = 0x01A2; +__ADC12IFG = 0x01A4; +__ADC12IE = 0x01A6; +__ADC12IV = 0x01A8; +__ADC12MEM0 = 0x0140; +__ADC12MEM1 = 0x0142; +__ADC12MEM2 = 0x0144; +__ADC12MEM3 = 0x0146; +__ADC12MEM4 = 0x0148; +__ADC12MEM5 = 0x014A; +__ADC12MEM6 = 0x014C; +__ADC12MEM7 = 0x014E; +__ADC12MEM8 = 0x0150; +__ADC12MEM9 = 0x0152; +__ADC12MEM10 = 0x0154; +__ADC12MEM11 = 0x0156; +__ADC12MEM12 = 0x0158; +__ADC12MEM13 = 0x015A; +__ADC12MEM14 = 0x015C; +__ADC12MEM15 = 0x015E; +__ADC12MCTL0 = 0x0080; +__ADC12MCTL1 = 0x0081; +__ADC12MCTL2 = 0x0082; +__ADC12MCTL3 = 0x0083; +__ADC12MCTL4 = 0x0084; +__ADC12MCTL5 = 0x0085; +__ADC12MCTL6 = 0x0086; +__ADC12MCTL7 = 0x0087; +__ADC12MCTL8 = 0x0088; +__ADC12MCTL9 = 0x0089; +__ADC12MCTL10 = 0x008A; +__ADC12MCTL11 = 0x008B; +__ADC12MCTL12 = 0x008C; +__ADC12MCTL13 = 0x008D; +__ADC12MCTL14 = 0x008E; +__ADC12MCTL15 = 0x008F; +__DAC12_0CTL = 0x01c0; +__DAC12_1CTL = 0x01c2; +__DAC12_0DAT = 0x01c8; +__DAC12_1DAT = 0x01ca; +__DMACTL0 = 0x0122; +__DMACTL1 = 0x0124; +__DMA0CTL = 0x01e0; +__DMA1CTL = 0x01e8; +__DMA2CTL = 0x01f0; +__DMA0SA = 0x01e2; +__DMA0DA = 0x01e4; +__DMA0SZ = 0x01e6; +__DMA1SA = 0x01ea; +__DMA1DA = 0x01ec; +__DMA1SZ = 0x01ee; +__DMA2SA = 0x01f2; +__DMA2DA = 0x01f4; +__DMA2SZ = 0x01f6; diff --git a/demos/MSP430-MSP430x1611-GCC/readme.txt b/demos/MSP430-MSP430x1611-GCC/readme.txt new file mode 100644 index 000000000..90dc78ff9 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/readme.txt @@ -0,0 +1,29 @@ +***************************************************************************** +** ChibiOS/RT port for Texas Instruments MSP430. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex MSP430-P1611 board with a 8MHz xtal installed. In +order to execute the demo without an crystal you need to edit mcuconf.h +and change: +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK +in: +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_DCOCLK + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM1 (USART0). + +** Build Procedure ** + +The demo was built using the MSPGCC toolchain. + +** Notes ** + +The demo requires include files from MSPGCC that are not part of the ChibiOS/RT +distribution, please install MSPGCC. + + http://mspgcc.sourceforge.net/ diff --git a/demos/PPC-SPC560B-GCC/.cproject b/demos/PPC-SPC560B-GCC/.cproject new file mode 100644 index 000000000..9b5a16b5c --- /dev/null +++ b/demos/PPC-SPC560B-GCC/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC560B-GCC/.project b/demos/PPC-SPC560B-GCC/.project new file mode 100644 index 000000000..4b773c630 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC560B-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560BC + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC560B-GCC/Makefile b/demos/PPC-SPC560B-GCC/Makefile new file mode 100644 index 000000000..1a594e5e6 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560BC/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560BCxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560BCxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560B50.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC560B-GCC/chconf.h b/demos/PPC-SPC560B-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC560B-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560B-GCC/halconf.h b/demos/PPC-SPC560B-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560B-GCC/main.c b/demos/PPC-SPC560B-GCC/main.c new file mode 100644 index 000000000..afbc87b61 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/main.c @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + unsigned i; + + for (i = 0; i < 4; i++) { + palClearPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(300); + } + + for (i = 0; i < 4; i++) { + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + } + + for (i = 0; i < 4; i++) { + palTogglePad(PORT_E, PE_LED1); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED1); + palTogglePad(PORT_E, PE_LED2); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED2); + palTogglePad(PORT_E, PE_LED3); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED3); + palTogglePad(PORT_E, PE_LED4); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED4); + } + + for (i = 0; i < 4; i++) { + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + chThdSleepMilliseconds(500); + } + + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC560B-GCC/mcuconf.h b/demos/PPC-SPC560B-GCC/mcuconf.h new file mode 100644 index 000000000..b93c9d562 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/mcuconf.h @@ -0,0 +1,178 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560BCxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/PPC-SPC560D-GCC/.cproject b/demos/PPC-SPC560D-GCC/.cproject new file mode 100644 index 000000000..9b5a16b5c --- /dev/null +++ b/demos/PPC-SPC560D-GCC/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC560D-GCC/.project b/demos/PPC-SPC560D-GCC/.project new file mode 100644 index 000000000..5b23694a7 --- /dev/null +++ b/demos/PPC-SPC560D-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC560D-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560D + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC560D-GCC/Makefile b/demos/PPC-SPC560D-GCC/Makefile new file mode 100644 index 000000000..04251c605 --- /dev/null +++ b/demos/PPC-SPC560D-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560D/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Dxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Dxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560D40.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC560D-GCC/chconf.h b/demos/PPC-SPC560D-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC560D-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560D-GCC/halconf.h b/demos/PPC-SPC560D-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC560D-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560D-GCC/main.c b/demos/PPC-SPC560D-GCC/main.c new file mode 100644 index 000000000..afbc87b61 --- /dev/null +++ b/demos/PPC-SPC560D-GCC/main.c @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + unsigned i; + + for (i = 0; i < 4; i++) { + palClearPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(300); + } + + for (i = 0; i < 4; i++) { + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + } + + for (i = 0; i < 4; i++) { + palTogglePad(PORT_E, PE_LED1); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED1); + palTogglePad(PORT_E, PE_LED2); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED2); + palTogglePad(PORT_E, PE_LED3); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED3); + palTogglePad(PORT_E, PE_LED4); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED4); + } + + for (i = 0; i < 4; i++) { + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + chThdSleepMilliseconds(500); + } + + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC560D-GCC/mcuconf.h b/demos/PPC-SPC560D-GCC/mcuconf.h new file mode 100644 index 000000000..a62a73496 --- /dev/null +++ b/demos/PPC-SPC560D-GCC/mcuconf.h @@ -0,0 +1,230 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Dxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 48 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_USE_LINFLEX2 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX2_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/PPC-SPC560P-GCC/.cproject b/demos/PPC-SPC560P-GCC/.cproject new file mode 100644 index 000000000..031774c3b --- /dev/null +++ b/demos/PPC-SPC560P-GCC/.cproject @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC560P-GCC/.project b/demos/PPC-SPC560P-GCC/.project new file mode 100644 index 000000000..8f550f87d --- /dev/null +++ b/demos/PPC-SPC560P-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC560P-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560P + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC560P-GCC/Makefile b/demos/PPC-SPC560P-GCC/Makefile new file mode 100644 index 000000000..6423b2caa --- /dev/null +++ b/demos/PPC-SPC560P-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560P/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Pxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Pxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560P50.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC560P-GCC/chconf.h b/demos/PPC-SPC560P-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC560P-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560P-GCC/halconf.h b/demos/PPC-SPC560P-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC560P-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC560P-GCC/main.c b/demos/PPC-SPC560P-GCC/main.c new file mode 100644 index 000000000..b83d452ae --- /dev/null +++ b/demos/PPC-SPC560P-GCC/main.c @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + unsigned i; + + for (i = 0; i < 4; i++) { + palClearPad(PORT_D, PD_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED4); + chThdSleepMilliseconds(300); + } + + for (i = 0; i < 4; i++) { + palTogglePort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + palTogglePort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + } + + for (i = 0; i < 4; i++) { + palTogglePad(PORT_D, PD_LED1); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED1); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED2); + palTogglePad(PORT_D, PD_LED3); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED3); + palTogglePad(PORT_D, PD_LED4); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED4); + } + + for (i = 0; i < 4; i++) { + palClearPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3)); + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + palClearPort(PORT_D, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4)); + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3)); + chThdSleepMilliseconds(500); + } + + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h new file mode 100644 index 000000000..f30b63d8a --- /dev/null +++ b/demos/PPC-SPC560P-GCC/mcuconf.h @@ -0,0 +1,255 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/PPC-SPC563M-GCC/.cproject b/demos/PPC-SPC563M-GCC/.cproject new file mode 100644 index 000000000..8b7306136 --- /dev/null +++ b/demos/PPC-SPC563M-GCC/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC563M-GCC/.project b/demos/PPC-SPC563M-GCC/.project new file mode 100644 index 000000000..28c9b4382 --- /dev/null +++ b/demos/PPC-SPC563M-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC563M-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC563M + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC563M-GCC/Makefile b/demos/PPC-SPC563M-GCC/Makefile new file mode 100644 index 000000000..e6098bcab --- /dev/null +++ b/demos/PPC-SPC563M-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC563M64.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC563M-GCC/chconf.h b/demos/PPC-SPC563M-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC563M-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC563M-GCC/halconf.h b/demos/PPC-SPC563M-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC563M-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC563M-GCC/main.c b/demos/PPC-SPC563M-GCC/main.c new file mode 100644 index 000000000..d24db076c --- /dev/null +++ b/demos/PPC-SPC563M-GCC/main.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + palClearPad(PORT11, P11_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED4); + chThdSleepMilliseconds(300); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC563M-GCC/mcuconf.h b/demos/PPC-SPC563M-GCC/mcuconf.h new file mode 100644 index 000000000..76898ad35 --- /dev/null +++ b/demos/PPC-SPC563M-GCC/mcuconf.h @@ -0,0 +1,122 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC563Mxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 80 +#define SPC5_CLK_RFD SPC5_RFD_DIV4 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB TRUE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/PPC-SPC564A-GCC/.cproject b/demos/PPC-SPC564A-GCC/.cproject new file mode 100644 index 000000000..ef4704a06 --- /dev/null +++ b/demos/PPC-SPC564A-GCC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC564A-GCC/.project b/demos/PPC-SPC564A-GCC/.project new file mode 100644 index 000000000..8f16b43f8 --- /dev/null +++ b/demos/PPC-SPC564A-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC564A-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC564A + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC564A-GCC/Makefile b/demos/PPC-SPC564A-GCC/Makefile new file mode 100644 index 000000000..9b51a6845 --- /dev/null +++ b/demos/PPC-SPC564A-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC564A/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC564Axx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC564Axx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC564A70.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC564A70L7_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC564A-GCC/chconf.h b/demos/PPC-SPC564A-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC564A-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC564A-GCC/halconf.h b/demos/PPC-SPC564A-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC564A-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC564A-GCC/main.c b/demos/PPC-SPC564A-GCC/main.c new file mode 100644 index 000000000..d24db076c --- /dev/null +++ b/demos/PPC-SPC564A-GCC/main.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + palClearPad(PORT11, P11_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT11, P11_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT11, P11_LED4); + chThdSleepMilliseconds(300); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h new file mode 100644 index 000000000..dc54d3d88 --- /dev/null +++ b/demos/PPC-SPC564A-GCC/mcuconf.h @@ -0,0 +1,139 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC564Axx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 75 +#define SPC5_CLK_RFD SPC5_RFD_DIV2 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(10) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB TRUE +#define SPC5_USE_ESCIC TRUE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 +#define SPC5_ESCIC_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_USE_DSPI3 FALSE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/PPC-SPC56EL-GCC/.cproject b/demos/PPC-SPC56EL-GCC/.cproject new file mode 100644 index 000000000..ac5bc86e0 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC56EL-GCC/.project b/demos/PPC-SPC56EL-GCC/.project new file mode 100644 index 000000000..d8776f952 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/.project @@ -0,0 +1,43 @@ + + + PPC-SPC56EL-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC56EL + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/PPC-SPC56EL-GCC/Makefile b/demos/PPC-SPC56EL-GCC/Makefile new file mode 100644 index 000000000..6ff36c810 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_EVB_SPC56EL/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC56EL-GCC/chconf.h b/demos/PPC-SPC56EL-GCC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC56EL-GCC/halconf.h b/demos/PPC-SPC56EL-GCC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC56EL-GCC/main.c b/demos/PPC-SPC56EL-GCC/main.c new file mode 100644 index 000000000..19e37c641 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/main.c @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + unsigned i; + + for (i = 0; i < 4; i++) { + palClearPad(PORT_D, PD_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT_D, PD_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT_D, PD_LED4); + chThdSleepMilliseconds(300); + } + + for (i = 0; i < 4; i++) { + palTogglePort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + palTogglePort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + } + + for (i = 0; i < 4; i++) { + palTogglePad(PORT_D, PD_LED1); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED1); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED2); + palTogglePad(PORT_D, PD_LED3); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED3); + palTogglePad(PORT_D, PD_LED4); + chThdSleepMilliseconds(250); + palTogglePad(PORT_D, PD_LED4); + } + + for (i = 0; i < 4; i++) { + palClearPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3)); + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4)); + chThdSleepMilliseconds(500); + palClearPort(PORT_D, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4)); + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3)); + chThdSleepMilliseconds(500); + } + + palSetPort(PORT_D, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) | + PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4)); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/PPC-SPC56EL-GCC/mcuconf.h b/demos/PPC-SPC56EL-GCC/mcuconf.h new file mode 100644 index 000000000..f90a80578 --- /dev/null +++ b/demos/PPC-SPC56EL-GCC/mcuconf.h @@ -0,0 +1,280 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC56ELxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC56ELxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 60 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 15 +#define SPC5_SWG_DIVIDER_VALUE 2 +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 FALSE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 FALSE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 FALSE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/Posix-GCC/Makefile b/demos/Posix-GCC/Makefile new file mode 100644 index 000000000..5d77f6a8e --- /dev/null +++ b/demos/Posix-GCC/Makefile @@ -0,0 +1,164 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/simulator/board.mk +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/Posix/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# List C source files here +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + $(BOARDSRC) \ + ${CHIBIOS}/os/various/shell.c \ + ${CHIBIOS}/os/various/chprintf.c \ + main.c + +# List ASM source files here +ASRC = + +# List all user directories here +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + ${CHIBIOS}/os/various + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -ggdb -O2 -fomit-frame-pointer + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) + +ifeq ($(HOST_OSX),yes) + ifeq ($(OSX_SDK),) + OSX_SDK = /Developer/SDKs/MacOSX10.7.sdk + endif + ifeq ($(OSX_ARCH),) + OSX_ARCH = -mmacosx-version-min=10.3 -arch i386 + endif + + CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH) + LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR) + LIBS += $(OSX_ARCH) +else + # Linux, or other + CPFLAGS += -m32 -Wa,-alms=$(<:.c=.lst) + LDFLAGS = -m32 -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT) + +%.o : %.c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%.o : %.s + $(AS) -c $(ASFLAGS) $< -o $@ + +$(PROJECT): $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(SRC)) + -mv *.gcov ./gcov + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT) + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h new file mode 100644 index 000000000..88fc072c1 --- /dev/null +++ b/demos/Posix-GCC/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h new file mode 100644 index 000000000..d406bacc1 --- /dev/null +++ b/demos/Posix-GCC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/*#include "mcuconf.h"*/ + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/Posix-GCC/main.c b/demos/Posix-GCC/main.c new file mode 100644 index 000000000..4aa18837d --- /dev/null +++ b/demos/Posix-GCC/main.c @@ -0,0 +1,255 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define TEST_WA_SIZE THD_WA_SIZE(4096) + +#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) + +static Thread *cdtp; +static Thread *shelltp1; +static Thread *shelltp2; + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.esp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +static const ShellConfig shell_cfg2 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero terminated string itself. + */ +static msg_t console_thread(void *arg) { + + (void)arg; + while (!chThdShouldTerminate()) { + Thread *tp = chMsgWait(); + puts((char *)chMsgGet(tp)); + fflush(stdout); + chMsgRelease(tp, RDY_OK); + } + return 0; +} + +/** + * @brief Shell termination handler. + * + * @param[in] id event id. + */ +static void termination_handler(eventid_t id) { + + (void)id; + if (shelltp1 && chThdTerminated(shelltp1)) { + chThdWait(shelltp1); + shelltp1 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD1 terminated"); + chSysLock(); + chOQResetI(&SD1.oqueue); + chSysUnlock(); + } + if (shelltp2 && chThdTerminated(shelltp2)) { + chThdWait(shelltp2); + shelltp2 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD2 terminated"); + chSysLock(); + chOQResetI(&SD2.oqueue); + chSysUnlock(); + } +} + +static EventListener sd1fel, sd2fel; + +/** + * @brief SD1 status change handler. + * + * @param[in] id event id. + */ +static void sd1_handler(eventid_t id) { + flagsmask_t flags; + + (void)id; + flags = chEvtGetAndClearFlags(&sd1fel); + if ((flags & CHN_CONNECTED) && (shelltp1 == NULL)) { + cputs("Init: connection on SD1"); + shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); + } + if (flags & CHN_DISCONNECTED) { + cputs("Init: disconnection on SD1"); + chSysLock(); + chIQResetI(&SD1.iqueue); + chSysUnlock(); + } +} + +/** + * @brief SD2 status change handler. + * + * @param[in] id event id. + */ +static void sd2_handler(eventid_t id) { + flagsmask_t flags; + + (void)id; + flags = chEvtGetAndClearFlags(&sd2fel); + if ((flags & CHN_CONNECTED) && (shelltp2 == NULL)) { + cputs("Init: connection on SD2"); + shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); + } + if (flags & CHN_DISCONNECTED) { + cputs("Init: disconnection on SD2"); + chSysLock(); + chIQResetI(&SD2.iqueue); + chSysUnlock(); + } +} + +static evhandler_t fhandlers[] = { + termination_handler, + sd1_handler, + sd2_handler +}; + +/*------------------------------------------------------------------------* + * Simulator main. * + *------------------------------------------------------------------------*/ +int main(void) { + EventListener tel; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Serial ports (simulated) initialization. + */ + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + chEvtRegister(&shell_terminated, &tel, 0); + + /* + * Console thread started. + */ + cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, + console_thread, NULL); + + /* + * Initializing connection/disconnection events. + */ + cputs("Shell service started on SD1, SD2"); + cputs(" - Listening for connections on SD1"); + chEvtRegister(chnGetEventSource(&SD1), &sd1fel, 1); + cputs(" - Listening for connections on SD2"); + chEvtRegister(chnGetEventSource(&SD2), &sd2fel, 2); + + /* + * Events servicing loop. + */ + while (!chThdShouldTerminate()) + chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); + + /* + * Clean simulator exit. + */ + chEvtUnregister(chnGetEventSource(&SD1), &sd1fel); + chEvtUnregister(chnGetEventSource(&SD2), &sd2fel); + return 0; +} diff --git a/demos/Posix-GCC/readme.txt b/demos/Posix-GCC/readme.txt new file mode 100644 index 000000000..883659d18 --- /dev/null +++ b/demos/Posix-GCC/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Linux process ** +***************************************************************************** + +** TARGET ** + +The demo runs under x86 Linux as an application program. The serial +I/O is simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how to create/terminate threads at runtime, how to listen to +events, how to work with serial ports, how to use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +GCC required. The Makefile defaults to building for a Linux host. +To build on OS X, use the following command: `make HOST_OSX=yes` + +** Connect to the demo ** + +In order to connect to the demo use telnet on the listening ports. diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw new file mode 100644 index 000000000..a6630271a --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw @@ -0,0 +1,16 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=cosmic\cosmic.stp +Dependencies= + +[Project1] +Filename=raisonance\raisonance.stp +Dependencies= +[Options] +ActiveProject=cosmic +ActiveConfig=Release +AddSortedElements=0 diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp new file mode 100644 index 000000000..20fd5c578 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -0,0 +1,2302 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=cosmic +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8l_discovery;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo;..\..\..\os\hal\platforms\stm8l; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,11,12,20,31,15 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,11,13,11,54,55 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg 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+String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8l_discovery;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo;..\..\..\os\hal\platforms\stm8l; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -customC-pp -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2012,1,23,18,22,6 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile 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+String.104.0=0x7ff +String.105.0=libisl0.sm8;libm0.sm8 +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8 +String.6.0=2010,5,25,14,45,56 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,5,25,14,45,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,11,12,20,31,15 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,5,25,14,45,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -customC-pp -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2012,1,23,18,22,6 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Source Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files...\demo\main.c] +ElemType=File +PathName=..\demo\main.c +Next=Root.Source Files.vectors.c +Config.0=Root.Source Files...\demo\main.c.Config.0 +Config.1=Root.Source Files...\demo\main.c.Config.1 + +[Root.Source Files...\demo\main.c.Config.0] +Settings.0.0=Root.Source Files...\demo\main.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files...\demo\main.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files...\demo\main.c.Config.0.Settings.2 + +[Root.Source Files...\demo\main.c.Config.1] +Settings.1.0=Root.Source Files...\demo\main.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 + 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Files.vectors.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.vectors.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.vectors.c.Config.0.Settings.2 + +[Root.Source Files.vectors.c.Config.1] +Settings.1.0=Root.Source Files.vectors.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.vectors.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.vectors.c.Config.1.Settings.2 + +[Root.Source Files.vectors.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.vectors.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.vectors.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.vectors.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.vectors.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.vectors.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +modsl0 -customC-pp -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) 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+PathName=..\..\..\test\testqueues.h +Next=Root.Include Files.Include Files\test...\..\..\test\testsem.h + +[Root.Include Files.Include Files\test...\..\..\test\testsem.h] +ElemType=File +PathName=..\..\..\test\testsem.h +Next=Root.Include Files.Include Files\test...\..\..\test\testthd.h + +[Root.Include Files.Include Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c new file mode 100644 index 000000000..68bb4c208 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -0,0 +1,276 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* This inclusion allows user ISR to be added to the HAL.*/ +#if defined(_USER_ISR_) +#include "user_isr.h" +#endif + +/** + * @brief Exception handler type. + */ +typedef void @far @interrupt (*interrupt_handler_t)(void); + +/* + * Various external symbols. + */ +void _stext(void); +@far @interrupt void vector_trap(void); +@far @interrupt void vector0(void); +@far @interrupt void vector1(void); +@far @interrupt void vector2(void); +@far @interrupt void vector3(void); +@far @interrupt void vector4(void); +@far @interrupt void vector5(void); +@far @interrupt void vector6(void); +@far @interrupt void vector7(void); +@far @interrupt void vector8(void); +@far @interrupt void vector9(void); +@far @interrupt void vector10(void); +@far @interrupt void vector11(void); +@far @interrupt void vector12(void); +@far @interrupt void vector13(void); +@far @interrupt void vector14(void); +@far @interrupt void vector15(void); +@far @interrupt void vector16(void); +@far @interrupt void vector17(void); +@far @interrupt void vector18(void); +@far @interrupt void vector19(void); +@far @interrupt void vector20(void); +@far @interrupt void vector21(void); +@far @interrupt void vector22(void); +@far @interrupt void vector23(void); +@far @interrupt void vector24(void); +@far @interrupt void vector25(void); +@far @interrupt void vector26(void); +@far @interrupt void vector27(void); +@far @interrupt void vector28(void); +@far @interrupt void vector29(void); + +/** + * @brief Exception vector type. + */ +typedef struct { + uint8_t ev_instruction; + interrupt_handler_t ev_handler; +} exception_vector_t; + +/** + * @brief Unhandled exception handler. + * @default This function is the default handler for all unused entries + * in the vector table. + */ +@far @interrupt void _unhandled_exception (void) +{ + while (TRUE) + ; +} + +/** + * @brief Exceptions table. + */ +exception_vector_t const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + +#if defined(_TRAP_ISR) + {0x82, vector_trap}, +#else + {0x82, _unhandled_exception}, /* trap */ +#endif + +#if defined(_TLI_ISR) + {0x82, vector0}, +#else + {0x82, _unhandled_exception}, /* vector0 */ +#endif + +#if defined(_FLASH_ISR) + {0x82, vector1}, +#else + {0x82, _unhandled_exception}, /* vector1 */ +#endif + +#if defined(_DMA10_ISR) || defined(_DMA11_ISR) + {0x82, vector2}, +#else + {0x82, _unhandled_exception}, /* vector2 */ +#endif + +#if defined(_DMA12_ISR) || defined(_DMA13_ISR) + {0x82, vector3}, +#else + {0x82, _unhandled_exception}, /* vector3 */ +#endif + +#if defined(_RTC_ISR) || defined(_LSE_CSS_ISR) + {0x82, vector4}, +#else + {0x82, _unhandled_exception}, /* vector4 */ +#endif + +#if defined(_EXTIE_ISR) || defined(_EXTIF_ISR) || defined(_PVD_ISR) + {0x82, vector5}, +#else + {0x82, _unhandled_exception}, /* vector5 */ +#endif + +#if defined(_EXTIB_ISR) || defined(_EXTIG_ISR) + {0x82, vector6}, +#else + {0x82, _unhandled_exception}, /* vector6 */ +#endif + +#if defined(_EXTID_ISR) || defined(_EXTIH_ISR) + {0x82, vector7}, +#else + {0x82, _unhandled_exception}, /* vector7 */ +#endif + +#if defined(_EXTI0_ISR) + {0x82, vector8}, +#else + {0x82, _unhandled_exception}, /* vector8 */ +#endif + +#if defined(_EXTI1_ISR) + {0x82, vector9}, +#else + {0x82, _unhandled_exception}, /* vector9 */ +#endif + +#if defined(_EXTI2_ISR) + {0x82, vector10}, +#else + {0x82, _unhandled_exception}, /* vector10 */ +#endif + +#if defined(_EXTI3_ISR) + {0x82, vector11}, +#else + {0x82, _unhandled_exception}, /* vector11 */ +#endif + +#if defined(_EXTI4_ISR) + {0x82, vector12}, +#else + {0x82, _unhandled_exception}, /* vector12 */ +#endif + +#if defined(_EXTI5_ISR) + {0x82, vector13}, +#else + {0x82, _unhandled_exception}, /* vector13 */ +#endif + +#if defined(_EXTI6_ISR) + {0x82, vector14}, +#else + {0x82, _unhandled_exception}, /* vector14 */ +#endif + +#if defined(_EXTI7_ISR) + {0x82, vector15}, +#else + {0x82, _unhandled_exception}, /* vector15 */ +#endif + +#if defined(_LCD_ISR) || defined(_AES_ISR) + {0x82, vector16}, +#else + {0x82, _unhandled_exception}, /* vector16 */ +#endif + +#if defined(_CLK_ISR) || defined(_TIM1_BREAK_ISR) || defined(_DAC_ISR) + {0x82, vector17}, +#else + {0x82, _unhandled_exception}, /* vector17 */ +#endif + +#if defined(_COMP1_ISR) || defined(_COMP2_ISR) || defined(_ADC1_ISR) + {0x82, vector18}, +#else + {0x82, _unhandled_exception}, /* vector18 */ +#endif + +#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) + {0x82, vector19}, +#else + {0x82, _unhandled_exception}, /* vector19 */ +#endif + +#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) + {0x82, vector20}, +#else + {0x82, _unhandled_exception}, /* vector20 */ +#endif + +#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) + {0x82, vector21}, +#else + {0x82, _unhandled_exception}, /* vector21 */ +#endif + +#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) + {0x82, vector22}, +#else + {0x82, _unhandled_exception}, /* vector22 */ +#endif + +#if defined(_TIM1_UPDATE_ISR) + {0x82, vector23}, +#else + {0x82, _unhandled_exception}, /* vector23 */ +#endif + +#if defined(_TIM1_COMPARE_ISR) + {0x82, vector24}, +#else + {0x82, _unhandled_exception}, /* vector24 */ +#endif + +#if defined(_TIM4_UPDATE_ISR) + {0x82, vector25}, +#else + {0x82, _unhandled_exception}, /* vector25 */ +#endif + +#if defined(_SPI1_ISR) + {0x82, vector26}, +#else + {0x82, _unhandled_exception}, /* vector26 */ +#endif + +#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) + {0x82, vector27}, +#else + {0x82, _unhandled_exception}, /* vector27 */ +#endif + +#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) + {0x82, vector28}, +#else + {0x82, _unhandled_exception}, /* vector28 */ +#endif + +#if defined(_SPI2_ISR) || defined(_I2C1_ISR) + {0x82, vector29}, +#else + {0x82, _unhandled_exception}, /* vector29 */ +#endif +}; diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h new file mode 100644 index 000000000..4e460e488 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c new file mode 100644 index 000000000..5362e1361 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, PC_LED4); + chThdSleepMilliseconds(250); + palClearPad(GPIOC, PC_LED4); + chThdSleepMilliseconds(250); + palSetPad(GPIOE, PE_LED3); + chThdSleepMilliseconds(250); + palClearPad(GPIOE, PE_LED3); + chThdSleepMilliseconds(250); + } + return 0; +} + +/* + * Application entry point. + */ +void main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * The STM8L-Discovery requires USART1 pins remapping on PA2 and PA3. + */ + SYSCFG->RMPCR1 = 0x1C; + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) + TestThread(&SD1); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h new file mode 100644 index 000000000..b44b87ec8 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -0,0 +1,43 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8L_NO_CLOCK_INIT FALSE +#define STM8L_HSI_ENABLED TRUE +#define STM8L_LSI_ENABLED TRUE +#define STM8L_HSE_ENABLED FALSE +#define STM8L_LSE_ENABLED TRUE +#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 +#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_LSE +#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8L_SERIAL_USE_USART1 TRUE +#define STM8L_SERIAL_USE_USART2 FALSE +#define STM8L_SERIAL_USE_USART3 FALSE diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp new file mode 100644 index 000000000..508b7693d --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -0,0 +1,2215 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=raisonance +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,4,10,30,46 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\STM8;INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,32,28 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0= +String.6.0=2010,11,13,16,33,31 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x101) EEPROMSTART(0x1000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,4,11,25,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\STM8;INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,11,13,17,40,20 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l;..\..\..\test; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Config.1.Settings.4] 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+String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,32,28 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c] +ElemType=File +PathName=..\demo\main.c +Next=Root.Source Files.Source Files\board +Config.0=Root.Source Files...\demo\main.c.Config.0 +Config.1=Root.Source Files...\demo\main.c.Config.1 + +[Root.Source Files...\demo\main.c.Config.0] +Settings.0.0=Root.Source Files...\demo\main.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files...\demo\main.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files...\demo\main.c.Config.0.Settings.2 + +[Root.Source Files...\demo\main.c.Config.1] +Settings.1.0=Root.Source Files...\demo\main.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 + +[Root.Source Files...\demo\main.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files...\demo\main.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + +[Root.Source Files.Source Files\board] +ElemType=Folder +PathName=Source Files\board +Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c +Next=Root.Source Files.Source Files\os +Config.0=Root.Source Files.Source Files\board.Config.0 +Config.1=Root.Source Files.Source Files\board.Config.1 + +[Root.Source Files.Source Files\board.Config.0] +Settings.0.0=Root.Source Files.Source Files\board.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\board.Config.0.Settings.3 + +[Root.Source Files.Source Files\board.Config.1] +Settings.1.0=Root.Source Files.Source Files\board.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 + +[Root.Source Files.Source Files\board.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] +ElemType=File +PathName=..\..\..\boards\st_stm8l_discovery\board.c + +[Root.Source Files.Source Files\os] +ElemType=Folder +PathName=Source Files\os +Child=Root.Source Files.Source Files\os.Source Files\os\hal +Next=Root.Source Files.Source Files\test + +[Root.Source Files.Source Files\os.Source Files\os\hal] +ElemType=Folder +PathName=Source Files\os\hal +Child=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] +ElemType=File +PathName=..\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] +ElemType=File +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c + +[Root.Source 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+String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.c + +[Root.Source Files.Source Files\test] +ElemType=Folder +PathName=Source Files\test +Child=Root.Source Files.Source Files\test...\..\..\test\testthd.c +Config.0=Root.Source Files.Source Files\test.Config.0 +Config.1=Root.Source Files.Source Files\test.Config.1 + +[Root.Source Files.Source Files\test.Config.0] +Settings.0.0=Root.Source Files.Source Files\test.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\test.Config.0.Settings.3 + +[Root.Source Files.Source Files\test.Config.1] +Settings.1.0=Root.Source Files.Source Files\test.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\test.Config.1.Settings.3 + +[Root.Source Files.Source Files\test.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 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Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.ewp b/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.ewp new file mode 100644 index 000000000..7b9761816 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.ewp @@ -0,0 +1,1770 @@ + + + + 2 + + Debug + + STM8 + + 1 + + General + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ICCSTM8 + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ASTM8 + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + 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$PROJ_DIR$\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\os\hal\src\spi.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\os\kernel\include\chbsem.h + + + $PROJ_DIR$\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\os\kernel\include\chfiles.h + + + $PROJ_DIR$\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\hal_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\hal_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\pal_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\pal_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\serial_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\serial_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\spi_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\spi_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\stm8s.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM8S\stm8s_type.h + + + + port + + $PROJ_DIR$\..\..\os\ports\IAR\STM8\chcore.c + + + $PROJ_DIR$\..\..\os\ports\IAR\STM8\chcore.h + + + $PROJ_DIR$\..\..\os\ports\IAR\STM8\chcore_stm8.s + + + $PROJ_DIR$\..\..\os\ports\IAR\STM8\chtypes.h + + + + + $PROJ_DIR$\chconf.h + + + $PROJ_DIR$\halconf.h + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\mcuconf.h + + + + diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.eww b/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-IAR/chconf.h new file mode 100644 index 000000000..758632eec --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT FALSE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES FALSE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-IAR/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/main.c b/demos/STM8S-STM8S105-DISCOVERY-IAR/main.c new file mode 100644 index 000000000..794e72da8 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/main.c @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + palSetPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +void main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(GPIOG, 0) == PAL_LOW) + /*TestThread(&SD2)*/; + if (palReadPad(GPIOG, 1) == PAL_LOW) + sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8S-STM8S105-DISCOVERY-IAR/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-IAR/mcuconf.h new file mode 100644 index 000000000..c09874c9b --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-IAR/mcuconf.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED FALSE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED TRUE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8S_SERIAL_USE_UART1 FALSE +#define STM8S_SERIAL_USE_UART2 TRUE +#define STM8S_SERIAL_USE_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw new file mode 100644 index 000000000..a6630271a --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw @@ -0,0 +1,16 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=cosmic\cosmic.stp +Dependencies= + +[Project1] +Filename=raisonance\raisonance.stp +Dependencies= +[Options] +ActiveProject=cosmic +ActiveConfig=Release +AddSortedElements=0 diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp new file mode 100644 index 000000000..209036cb6 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -0,0 +1,2067 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=cosmic +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug 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+PathName=..\..\..\test\testbmk.h +Next=Root.Include Files.Include Files\test...\..\..\test\test.h + +[Root.Include Files.Include Files\test...\..\..\test\test.h] +ElemType=File +PathName=..\..\..\test\test.h \ No newline at end of file diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c new file mode 100644 index 000000000..b6b57dc1d --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Exception handler type. + */ +typedef void @far @interrupt (*interrupt_handler_t)(void); + +/* + * Various external symbols. + */ +void _stext(void); +@far @interrupt void vector10(void); +@far @interrupt void vector13(void); +@far @interrupt void vector17(void); +@far @interrupt void vector18(void); +@far @interrupt void vector20(void); +@far @interrupt void vector21(void); + +/** + * @brief Exception vector type. + */ +typedef struct { + uint8_t ev_instruction; + interrupt_handler_t ev_handler; +} exception_vector_t; + +/** + * @brief Undefined interrupt handler. + * @note It should never be invoked. + */ +@far @interrupt static void vector (void) +{ + return; +} + +/** + * @brief Exceptions table. + */ +exception_vector_t const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, vector}, /* trap */ + {0x82, vector}, /* vector0 */ + {0x82, vector}, /* vector1 */ + {0x82, vector}, /* vector2 */ + {0x82, vector}, /* vector3 */ + {0x82, vector}, /* vector4 */ + {0x82, vector}, /* vector5 */ + {0x82, vector}, /* vector6 */ + {0x82, vector}, /* vector7 */ + {0x82, vector}, /* vector8 */ + {0x82, vector}, /* vector9 */ +#if HAL_USE_SPI && STM8S_SPI_USE_SPI + {0x82, vector10}, +#else + {0x82, vector}, /* vector10 */ +#endif + {0x82, vector}, /* vector11 */ + {0x82, vector}, /* vector12 */ + {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector14 */ + {0x82, vector}, /* vector15 */ + {0x82, vector}, /* vector16 */ +#if HAL_USE_SERIAL && STM8S_SERIAL_USE_UART1 + {0x82, vector17}, /* vector17 */ + {0x82, vector18}, /* vector18 */ +#else + {0x82, vector}, /* vector17 */ + {0x82, vector}, /* vector18 */ +#endif + {0x82, vector}, /* vector19 */ +#if HAL_USE_SERIAL && (STM8S_SERIAL_USE_UART2 || STM8S_SERIAL_USE_UART3) + {0x82, vector20}, /* vector20 */ + {0x82, vector21}, /* vector21 */ +#else + {0x82, vector}, /* vector20 */ + {0x82, vector}, /* vector21 */ +#endif + {0x82, vector}, /* vector22 */ + {0x82, vector}, /* vector23 */ + {0x82, vector}, /* vector24 */ + {0x82, vector}, /* vector25 */ + {0x82, vector}, /* vector26 */ + {0x82, vector}, /* vector27 */ + {0x82, vector}, /* vector28 */ + {0x82, vector}, /* vector29 */ +}; diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h new file mode 100644 index 000000000..4e460e488 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c new file mode 100644 index 000000000..13df3736d --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + palSetPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +void main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(GPIOG, 0) == PAL_LOW) + TestThread(&SD2); + if (palReadPad(GPIOG, 1) == PAL_LOW) + sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h new file mode 100644 index 000000000..c09874c9b --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED FALSE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED TRUE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8S_SERIAL_USE_UART1 FALSE +#define STM8S_SERIAL_USE_UART2 TRUE +#define STM8S_SERIAL_USE_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp new file mode 100644 index 000000000..092074d51 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -0,0 +1,2156 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=raisonance +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,4,10,30,46 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\STM8;INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,4,11,25,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\STM8;INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] NODEBUGLINES NODEBUGPUBLICS NODEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c] +ElemType=File +PathName=..\demo\main.c +Next=Root.Source Files.Source Files\board +Config.0=Root.Source Files...\demo\main.c.Config.0 +Config.1=Root.Source Files...\demo\main.c.Config.1 + +[Root.Source Files...\demo\main.c.Config.0] +Settings.0.0=Root.Source Files...\demo\main.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files...\demo\main.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files...\demo\main.c.Config.0.Settings.2 + +[Root.Source Files...\demo\main.c.Config.1] +Settings.1.0=Root.Source Files...\demo\main.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 + +[Root.Source Files...\demo\main.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,12,31 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files...\demo\main.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,12,31 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\board] +ElemType=Folder +PathName=Source Files\board +Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c +Next=Root.Source Files.Source Files\os +Config.0=Root.Source Files.Source Files\board.Config.0 +Config.1=Root.Source Files.Source Files\board.Config.1 + +[Root.Source Files.Source Files\board.Config.0] +Settings.0.0=Root.Source Files.Source Files\board.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\board.Config.0.Settings.3 + +[Root.Source Files.Source Files\board.Config.1] +Settings.1.0=Root.Source Files.Source Files\board.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 + +[Root.Source Files.Source Files\board.Config.0.Settings.0] +String.6.0=2010,6,4,10,11,42 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board.Config.1.Settings.0] +String.6.0=2010,6,4,10,11,42 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c] +ElemType=File +PathName=..\..\..\boards\st_stm8s_discovery\board.c + +[Root.Source Files.Source Files\os] +ElemType=Folder +PathName=Source Files\os +Child=Root.Source Files.Source Files\os.Source Files\os\hal +Next=Root.Source Files.Source Files\test + +[Root.Source Files.Source Files\os.Source Files\os\hal] +ElemType=Folder +PathName=Source Files\os\hal +Child=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,32 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,32 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] +ElemType=File +PathName=..\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] +ElemType=File +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] +ElemType=File +PathName=..\..\..\os\hal\src\pwm.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] 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PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmsg.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 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Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) 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PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] 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+ +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.c + +[Root.Source Files.Source Files\test] +ElemType=Folder +PathName=Source Files\test +Child=Root.Source Files.Source Files\test...\..\..\test\testthd.c +Config.0=Root.Source Files.Source Files\test.Config.0 +Config.1=Root.Source Files.Source Files\test.Config.1 + +[Root.Source Files.Source Files\test.Config.0] +Settings.0.0=Root.Source Files.Source Files\test.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\test.Config.0.Settings.3 + +[Root.Source Files.Source Files\test.Config.1] +Settings.1.0=Root.Source Files.Source Files\test.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\test.Config.1.Settings.3 + +[Root.Source Files.Source Files\test.Config.0.Settings.0] +String.6.0=2010,6,4,10,11,52 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\test.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test.Config.1.Settings.0] +String.6.0=2010,6,4,10,11,52 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +ElemType=File +PathName=..\..\..\test\testthd.c +Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +ElemType=File +PathName=..\..\..\test\testsem.c +Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +ElemType=File +PathName=..\..\..\test\testqueues.c +Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +ElemType=File +PathName=..\..\..\test\testpools.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +ElemType=File +PathName=..\..\..\test\testmtx.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +ElemType=File +PathName=..\..\..\test\testmsg.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +ElemType=File +PathName=..\..\..\test\testmbox.c +Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c + +[Root.Source Files.Source Files\test...\..\..\test\testheap.c] +ElemType=File +PathName=..\..\..\test\testheap.c +Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c] +ElemType=File +PathName=..\..\..\test\testevt.c +Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c] +ElemType=File +PathName=..\..\..\test\testdyn.c +Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c] +ElemType=File +PathName=..\..\..\test\testbmk.c +Next=Root.Source Files.Source Files\test...\..\..\test\test.c + +[Root.Source Files.Source Files\test...\..\..\test\test.c] +ElemType=File +PathName=..\..\..\test\test.c + +[Root.Include Files] +ElemType=Folder +PathName=Include Files +Child=Root.Include Files...\demo\halconf.h +Config.0=Root.Include Files.Config.0 +Config.1=Root.Include Files.Config.1 + +[Root.Include Files.Config.0] +Settings.0.0=Root.Include Files.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Config.0.Settings.3 + +[Root.Include Files.Config.1] +Settings.1.0=Root.Include Files.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Config.1.Settings.3 + +[Root.Include Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files...\demo\halconf.h] +ElemType=File +PathName=..\demo\halconf.h +Next=Root.Include Files...\demo\chconf.h + +[Root.Include Files...\demo\chconf.h] +ElemType=File +PathName=..\demo\chconf.h +Next=Root.Include Files...\demo\mcuconf.h + +[Root.Include Files...\demo\mcuconf.h] +ElemType=File +PathName=..\demo\mcuconf.h +Next=Root.Include Files.Include Files\board + +[Root.Include Files.Include Files\board] +ElemType=Folder +PathName=Include Files\board +Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h +Next=Root.Include Files.Include Files\os + +[Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h] +ElemType=File +PathName=..\..\..\boards\st_stm8s_discovery\board.h + +[Root.Include Files.Include Files\os] +ElemType=Folder +PathName=Include Files\os +Child=Root.Include Files.Include Files\os.Include Files\os\hal +Next=Root.Include Files.Include Files\test + +[Root.Include Files.Include Files\os.Include Files\os\hal] +ElemType=Folder +PathName=Include Files\os\hal +Child=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\spi.h] +ElemType=File +PathName=..\..\..\os\hal\include\spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\serial.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\serial.h] +ElemType=File +PathName=..\..\..\os\hal\include\serial.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\pwm.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\pwm.h] +ElemType=File +PathName=..\..\..\os\hal\include\pwm.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\pal.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\pal.h] +ElemType=File +PathName=..\..\..\os\hal\include\pal.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mmc_spi.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mmc_spi.h] +ElemType=File +PathName=..\..\..\os\hal\include\mmc_spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mii.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mii.h] +ElemType=File +PathName=..\..\..\os\hal\include\mii.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mac.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\mac.h] +ElemType=File +PathName=..\..\..\os\hal\include\mac.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\hal.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\hal.h] +ElemType=File +PathName=..\..\..\os\hal\include\hal.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\can.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\can.h] +ElemType=File +PathName=..\..\..\os\hal\include\can.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\adc.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\adc.h] +ElemType=File +PathName=..\..\..\os\hal\include\adc.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s] +ElemType=Folder +PathName=Include Files\os\hal\stm8s +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\stm8s_type.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel] +ElemType=Folder +PathName=Include Files\os\kernel +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\port + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chthreads.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsys.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsys.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chsys.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chstreams.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chstreams.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chstreams.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsem.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsem.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chsem.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chschd.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chschd.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chschd.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chregistry.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chregistry.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chregistry.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chqueues.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chqueues.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chqueues.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmtx.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmtx.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmtx.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmsg.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmsg.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmsg.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmempools.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmempools.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmempools.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmemcore.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmemcore.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmemcore.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmboxes.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmboxes.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmboxes.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chlists.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chlists.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chlists.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chinline.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chheap.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdebug.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chcond.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] +ElemType=File +PathName=..\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\port] +ElemType=Folder +PathName=Include Files\os\port +Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chtypes.h +Next=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\test] +ElemType=Folder +PathName=Include Files\test +Child=Root.Include Files.Include Files\test...\..\..\test\testsem.h + +[Root.Include Files.Include Files\test...\..\..\test\testsem.h] +ElemType=File +PathName=..\..\..\test\testsem.h +Next=Root.Include Files.Include Files\test...\..\..\test\testqueues.h + +[Root.Include Files.Include Files\test...\..\..\test\testqueues.h] +ElemType=File +PathName=..\..\..\test\testqueues.h +Next=Root.Include Files.Include Files\test...\..\..\test\testpools.h + +[Root.Include Files.Include Files\test...\..\..\test\testpools.h] +ElemType=File +PathName=..\..\..\test\testpools.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmtx.h + +[Root.Include Files.Include Files\test...\..\..\test\testmtx.h] +ElemType=File +PathName=..\..\..\test\testmtx.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmsg.h + +[Root.Include Files.Include Files\test...\..\..\test\testmsg.h] +ElemType=File +PathName=..\..\..\test\testmsg.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmbox.h + +[Root.Include Files.Include Files\test...\..\..\test\testmbox.h] +ElemType=File +PathName=..\..\..\test\testmbox.h +Next=Root.Include Files.Include Files\test...\..\..\test\testheap.h + +[Root.Include Files.Include Files\test...\..\..\test\testheap.h] +ElemType=File +PathName=..\..\..\test\testheap.h +Next=Root.Include Files.Include Files\test...\..\..\test\testevt.h + +[Root.Include Files.Include Files\test...\..\..\test\testevt.h] +ElemType=File +PathName=..\..\..\test\testevt.h +Next=Root.Include Files.Include Files\test...\..\..\test\testdyn.h + +[Root.Include Files.Include Files\test...\..\..\test\testdyn.h] +ElemType=File +PathName=..\..\..\test\testdyn.h +Next=Root.Include Files.Include Files\test...\..\..\test\testbmk.h + +[Root.Include Files.Include Files\test...\..\..\test\testbmk.h] +ElemType=File +PathName=..\..\..\test\testbmk.h +Next=Root.Include Files.Include Files\test...\..\..\test\test.h + +[Root.Include Files.Include Files\test...\..\..\test\test.h] +ElemType=File +PathName=..\..\..\test\test.h +Next=Root.Include Files.Include Files\test...\..\..\test\testthd.h + +[Root.Include Files.Include Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp new file mode 100644 index 000000000..095ec0874 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -0,0 +1,160 @@ + + + + + + + + + + + +

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+ + + + + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj new file mode 100644 index 000000000..90c037168 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h new file mode 100644 index 000000000..4e460e488 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S208-RC/main.c b/demos/STM8S-STM8S208-RC/main.c new file mode 100644 index 000000000..f9b18dc71 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(IOPORT2, PB_LED(7)); + chThdSleepMilliseconds(500); + palSetPad(IOPORT2, PB_LED(7)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +void main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(IOPORT7, PG_BT5) == PAL_LOW) + TestThread(&SD1); + if (palReadPad(IOPORT7, PG_BT6) == PAL_LOW) + sdWriteTimeout(&SD1, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h new file mode 100644 index 000000000..375b1b35f --- /dev/null +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED TRUE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED FALSE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8S_SERIAL_USE_UART1 TRUE +#define STM8S_SERIAL_USE_UART2 FALSE +#define STM8S_SERIAL_USE_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/STM8S-STM8S208-RC/readme.txt b/demos/STM8S-STM8S208-RC/readme.txt new file mode 100644 index 000000000..011f75c56 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/readme.txt @@ -0,0 +1,16 @@ +***************************************************************************** +** ChibiOS/RT demo for STM8S208RB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on a Raisonance REva+STM8S208RB board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port. + +** Build Procedure ** + +From withing the Ride7 IDE open the project, compile and run it. diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile new file mode 100644 index 000000000..1b77c241c --- /dev/null +++ b/demos/Win32-MinGW/Makefile @@ -0,0 +1,149 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = mingw32- +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lws2_32 + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/simulator/board.mk +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# List C source files here +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + $(BOARDSRC) \ + ${CHIBIOS}/os/various/shell.c \ + ${CHIBIOS}/os/various/chprintf.c \ + main.c + +# List ASM source files here +ASRC = + +# List all user directories here +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + ${CHIBIOS}/os/various + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -ggdb -O2 -fomit-frame-pointer + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%.o : %.c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%.o : %.s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(SRC)) + -mv *.gcov ./gcov + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h new file mode 100644 index 000000000..88fc072c1 --- /dev/null +++ b/demos/Win32-MinGW/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h new file mode 100644 index 000000000..d406bacc1 --- /dev/null +++ b/demos/Win32-MinGW/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/*#include "mcuconf.h"*/ + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c new file mode 100644 index 000000000..0d5dab844 --- /dev/null +++ b/demos/Win32-MinGW/main.c @@ -0,0 +1,253 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define TEST_WA_SIZE THD_WA_SIZE(4096) + +#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) + +static Thread *cdtp; +static Thread *shelltp1; +static Thread *shelltp2; + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.esp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +static const ShellConfig shell_cfg2 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero terminated string itself. + */ +static msg_t console_thread(void *arg) { + + (void)arg; + while (!chThdShouldTerminate()) { + Thread *tp = chMsgWait(); + puts((char *)chMsgGet(tp)); + fflush(stdout); + chMsgRelease(tp, RDY_OK); + } + return 0; +} + +/** + * @brief Shell termination handler. + * + * @param[in] id event id. + */ +static void termination_handler(eventid_t id) { + + (void)id; + if (shelltp1 && chThdTerminated(shelltp1)) { + chThdWait(shelltp1); + shelltp1 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD1 terminated"); + chSysLock(); + chOQResetI(&SD1.oqueue); + chSysUnlock(); + } + if (shelltp2 && chThdTerminated(shelltp2)) { + chThdWait(shelltp2); + shelltp2 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD2 terminated"); + chSysLock(); + chOQResetI(&SD2.oqueue); + chSysUnlock(); + } +} + +static EventListener sd1fel, sd2fel; + +/** + * @brief SD1 status change handler. + * + * @param[in] id event id. + */ +static void sd1_handler(eventid_t id) { + flagsmask_t flags; + + (void)id; + flags = chEvtGetAndClearFlags(&sd1fel); + if ((flags & CHN_CONNECTED) && (shelltp1 == NULL)) { + cputs("Init: connection on SD1"); + shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); + } + if (flags & CHN_DISCONNECTED) { + cputs("Init: disconnection on SD1"); + chSysLock(); + chIQResetI(&SD1.iqueue); + chSysUnlock(); + } +} + +/** + * @brief SD2 status change handler. + * + * @param[in] id event id. + */ +static void sd2_handler(eventid_t id) { + flagsmask_t flags; + + (void)id; + flags = chEvtGetAndClearFlags(&sd2fel); + if ((flags & CHN_CONNECTED) && (shelltp2 == NULL)) { + cputs("Init: connection on SD2"); + shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); + } + if (flags & CHN_DISCONNECTED) { + cputs("Init: disconnection on SD2"); + chSysLock(); + chIQResetI(&SD2.iqueue); + chSysUnlock(); + } +} + +static evhandler_t fhandlers[] = { + termination_handler, + sd1_handler, + sd2_handler +}; + +/*------------------------------------------------------------------------* + * Simulator main. * + *------------------------------------------------------------------------*/ +int main(void) { + EventListener tel; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Serial ports (simulated) initialization. + */ + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + chEvtRegister(&shell_terminated, &tel, 0); + + /* + * Console thread started. + */ + cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, + console_thread, NULL); + + /* + * Initializing connection/disconnection events. + */ + cputs("Shell service started on SD1, SD2"); + cputs(" - Listening for connections on SD1"); + chEvtRegister(chnGetEventSource(&SD1), &sd1fel, 1); + cputs(" - Listening for connections on SD2"); + chEvtRegister(chnGetEventSource(&SD2), &sd2fel, 2); + + /* + * Events servicing loop. + */ + while (!chThdShouldTerminate()) + chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); + + /* + * Clean simulator exit. + */ + chEvtUnregister(chnGetEventSource(&SD1), &sd1fel); + chEvtUnregister(chnGetEventSource(&SD2), &sd2fel); + return 0; +} diff --git a/demos/Win32-MinGW/readme.txt b/demos/Win32-MinGW/readme.txt new file mode 100644 index 000000000..e72e2e0a3 --- /dev/null +++ b/demos/Win32-MinGW/readme.txt @@ -0,0 +1,33 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Win32 process ** +***************************************************************************** + +** TARGET ** + +The demo runs under any Windows version as an application program. The serial +I/O is simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how to create/terminate threads at runtime, how to listen to +events, how to work with serial ports, how to use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +The demo was built using the MinGW toolchain. + +** Connect to the demo ** + +In order to connect to the demo a telnet client is required. A good choice +is PuTTY: + +http://www.putty.org/ + +Host Name: 127.0.0.1 +Port: 29001 and/or 29002 +Connection Type: Raw diff --git a/docs/Doxyfile_chm b/docs/Doxyfile_chm new file mode 100644 index 000000000..8b2f242f9 --- /dev/null +++ b/docs/Doxyfile_chm @@ -0,0 +1,1787 @@ +# Doxyfile 1.7.4 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" "). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = ChibiOS/RT + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = 2.7.0 + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. 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If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = NO + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to +# determine which symbols to keep in memory and which to flush to disk. +# When the cache is full, less often used symbols will be written to disk. +# For small to medium size projects (<1000 input files) the default value is +# probably good enough. For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penalty. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will roughly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols + +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = NO + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespaces are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = YES + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = YES + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = NO + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or macro consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and macros in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = NO + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. The create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = ./rsc/layout.xml + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = YES + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_NO_PARAMDOC option can be enabled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ../docs/src \ + ../os/kernel \ + ../os/ports \ + ../os/hal \ + ../os/various \ + ../test \ + ../ext/ext.dox + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.ddf \ + *.s + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = ../os/ports/common/ARMCMx/CMSIS \ + ../os/ports/GCC/SIMIA32 \ + ../os/hal/platforms \ + ../os/hal/templates/meta \ + ../os/various\devices_lib \ + ../os/various\fatfs_bindings \ + ../os/various\lwip_bindings \ + ../test/coverage + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = ./rsc + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = NO + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = NO + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is adviced to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when changing the value of configuration settings such as GENERATE_TREEVIEW! + +HTML_HEADER = ./rsc/header_chm.html + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = ./rsc/footer_chm.html + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the stylesheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = YES + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = ../ChibiOS_RT.chm + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = "\"C:/Program Files/HTML Help Workshop/hhc.exe\"" + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. + +ENUM_VALUES_PER_LINE = 4 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the +# mathjax.org site, so you can quickly see the result without installing +# MathJax, but it is strongly recommended to install a local copy of MathJax +# before deployment. + +MATHJAX_RELPATH = http://www.mathjax.org/mathjax + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = NO + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a PHP enabled web server instead of at the web client +# using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server +# based approach is that it scales better to large projects and allows +# full text search. The disadvantages are that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = YES + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = YES + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# pointed to by INCLUDE_PATH will be searched when a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = __DOXYGEN__ + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. + +SKIP_FUNCTION_MACROS = NO + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = NO + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = YES + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will write a font called Helvetica to the output +# directory and reference it in all dot files that doxygen generates. +# When you want a differently looking font you can specify the font name +# using DOT_FONTNAME. You need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 8 + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = YES + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = NO + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = YES + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will generate a graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = NO + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 20 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 3 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = YES + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = YES + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/docs/Doxyfile_html b/docs/Doxyfile_html new file mode 100644 index 000000000..d18b5eb97 --- /dev/null +++ b/docs/Doxyfile_html @@ -0,0 +1,1787 @@ +# Doxyfile 1.7.4 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" "). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = ChibiOS/RT + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = 2.7.0 + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = . + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, +# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English +# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, +# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = YES + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = NO + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = "C:/Documents and Settings/Administrator/" + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful if your file system +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = NO + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 2 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = "iclass=@par Function Class:\n This is an \ + I-Class API, this function can be \ + invoked from within a system lock zone by both \ + threads and interrupt handlers." \ + "sclass=@par Function Class:\n This is an \ + S-Class API, this function can be \ + invoked from within a system lock zone by threads \ + only." \ + "api=@par Function Class:\n Normal API, this \ + function can be invoked by regular system threads \ + but not from within a lock zone." \ + "notapi=@par Function Class:\n Not an API, this \ + function is for internal use only." \ + "isr=@par Function Class:\n Interrupt handler, \ + this function should not be directly invoked." \ + "init=@par Function Class:\n Initializer, this \ + function just initializes an object and can be \ + invoked before the kernel is initialized." \ + "special=@par Function Class:\n Special function, \ + this function has special requirements see the \ + notes." + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given extension. +# Doxygen has a built-in mapping, but you can override or extend it using this +# tag. The format is ext=language, where ext is a file extension, and language +# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, +# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make +# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C +# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions +# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also makes the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate getter +# and setter methods for a property. Setting this option to YES (the default) +# will make doxygen replace the get and set methods by a property in the +# documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = NO + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to +# determine which symbols to keep in memory and which to flush to disk. +# When the cache is full, less often used symbols will be written to disk. +# For small to medium size projects (<1000 input files) the default value is +# probably good enough. For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penalty. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will roughly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols + +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = NO + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespaces are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = YES + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = YES + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = NO + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or macro consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and macros in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = NO + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. The create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = ./rsc/layout.xml + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = YES + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_NO_PARAMDOC option can be enabled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ../docs/src \ + ../os/kernel \ + ../os/ports \ + ../os/hal \ + ../os/various \ + ../test \ + ../ext/ext.dox + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.ddf \ + *.s + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = ../os/ports/common/ARMCMx/CMSIS \ + ../os/ports/GCC/SIMIA32 \ + ../os/hal/platforms \ + ../os/hal/templates/meta \ + ../os/various\devices_lib \ + ../os/various\fatfs_bindings \ + ../os/various\lwip_bindings \ + ../test/coverage + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = ./rsc + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = NO + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = NO + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is adviced to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when changing the value of configuration settings such as GENERATE_TREEVIEW! + +HTML_HEADER = ./rsc/header_html.html + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = ./rsc/footer_html.html + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the stylesheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = ../ChibiOS_RT.chm + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = "\"C:/Program Files/HTML Help Workshop/hhc.exe\"" + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. + +ENUM_VALUES_PER_LINE = 4 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. + +GENERATE_TREEVIEW = YES + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the +# mathjax.org site, so you can quickly see the result without installing +# MathJax, but it is strongly recommended to install a local copy of MathJax +# before deployment. + +MATHJAX_RELPATH = http://www.mathjax.org/mathjax + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = NO + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a PHP enabled web server instead of at the web client +# using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server +# based approach is that it scales better to large projects and allows +# full text search. The disadvantages are that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = YES + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = YES + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# pointed to by INCLUDE_PATH will be searched when a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = __DOXYGEN__ + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. + +SKIP_FUNCTION_MACROS = NO + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = NO + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = YES + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will write a font called Helvetica to the output +# directory and reference it in all dot files that doxygen generates. +# When you want a differently looking font you can specify the font name +# using DOT_FONTNAME. You need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 8 + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = YES + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = NO + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = YES + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will generate a graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = NO + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 20 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 3 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = YES + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = YES + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/docs/html/logo_small.png b/docs/html/logo_small.png new file mode 100644 index 000000000..c53451bba Binary files /dev/null and b/docs/html/logo_small.png differ diff --git a/docs/index.html b/docs/index.html new file mode 100644 index 000000000..bf4fe4e3f --- /dev/null +++ b/docs/index.html @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/docs/readme.txt b/docs/readme.txt new file mode 100644 index 000000000..9924d779f --- /dev/null +++ b/docs/readme.txt @@ -0,0 +1,11 @@ +*** Documentation build procedure *** + +The following software must be installed: +- Doxygen 1.7.4 or later. +- Graphviz 2.26.3 or later. The ./bin directory must be specified in the path + in order to make Graphviz accessible by Doxygen. + +Build procedure: +- Run Doxywizard. +- Load ./docs/Doxyfile_html or ./docs/Doxyfile_chm from Doxywizard. +- Start. diff --git a/docs/reports/AT91SAM7X-48-ARM.txt b/docs/reports/AT91SAM7X-48-ARM.txt new file mode 100644 index 000000000..3198727f3 --- /dev/null +++ b/docs/reports/AT91SAM7X-48-ARM.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu +Settings: MCK=48.054857, MC_FMR = AT91C_MC_FWS_1FWS (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 12:28:19 +*** Compiler: GCC 4.6.2 +*** Architecture: ARM7 +*** Core Variant: ARM7TDMI +*** Port Info: Pure ARM mode +*** Platform: AT91SAM7x +*** Test Board: Olimex SAM7-EX256 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 116919 msgs/S, 233838 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 89887 msgs/S, 179774 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 89887 msgs/S, 179774 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 380288 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 64709 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 93398 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 26941 reschedules/S, 161646 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 203272 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 272700 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 263496 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 449056 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 322048 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 364 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/AT91SAM7X-48-THUMB.txt b/docs/reports/AT91SAM7X-48-THUMB.txt new file mode 100644 index 000000000..21a3632e5 --- /dev/null +++ b/docs/reports/AT91SAM7X-48-THUMB.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu +Settings: MCK=48.054857, MC_FMR = AT91C_MC_FWS_1FWS (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 13:03:08 +*** Compiler: GCC 4.6.2 +*** Architecture: ARM7 +*** Core Variant: ARM7TDMI +*** Port Info: Pure THUMB mode +*** Platform: AT91SAM7x +*** Test Board: Olimex SAM7-EX256 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 107489 msgs/S, 214978 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 88253 msgs/S, 176506 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 88253 msgs/S, 176506 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 402392 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 67753 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 101772 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 28388 reschedules/S, 170328 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 199720 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 289356 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 323198 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 364448 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 256824 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 364 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/ATmega128-16.txt b/docs/reports/ATmega128-16.txt new file mode 100644 index 000000000..a171ab108 --- /dev/null +++ b/docs/reports/ATmega128-16.txt @@ -0,0 +1,149 @@ +*************************************************************************** +Options: -O2 +Settings: F_CPU=16000000 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 21:11:04 +*** Compiler: GCC 4.3.0 +*** Architecture: AVR +*** Core Variant: MegaAVR +*** Port Info: None +*** Platform: ATmega128 +*** Test Board: Olimex AVR-MT-128 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 31561 msgs/S, 63122 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 24980 msgs/S, 49960 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 24980 msgs/S, 49960 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 88896 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 19766 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 25179 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 7891 reschedules/S, 47346 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 60760 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 91888 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 85722 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 227568 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 116724 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 234 bytes +--- Thread: 31 bytes +--- Timer : 10 bytes +--- Semaph: 5 bytes +--- EventS: 2 bytes +--- EventL: 5 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 18 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC1114-48-GCC.txt b/docs/reports/LPC1114-48-GCC.txt new file mode 100644 index 000000000..4e0118f00 --- /dev/null +++ b/docs/reports/LPC1114-48-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer +Settings: CLK=48, (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 19:34:26 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv6-M +*** Core Variant: Cortex-M0 +*** Port Info: Preemption through NMI +*** Platform: LPC11xx +*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1114 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 127622 msgs/S, 255244 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 101340 msgs/S, 202680 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 101340 msgs/S, 202680 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 384536 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 79026 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 111784 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 30914 reschedules/S, 185484 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 245084 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 377384 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 351018 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 591196 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 354276 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC1114-48-RVCT.txt b/docs/reports/LPC1114-48-RVCT.txt new file mode 100644 index 000000000..06c95d3e3 --- /dev/null +++ b/docs/reports/LPC1114-48-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: CLK=48, (2 wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 19:37:26 +*** Compiler: RVCT +*** Architecture: ARMv6-M +*** Core Variant: Cortex-M0 +*** Port Info: Preemption through NMI +*** Platform: LPC11xx +*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1114 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 122129 msgs/S, 244258 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 102916 msgs/S, 205832 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 103361 msgs/S, 206722 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 380136 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 79326 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 113161 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 33700 reschedules/S, 202200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 232092 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 341100 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 307102 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 618184 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 382800 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC1343-72-GCC.txt b/docs/reports/LPC1343-72-GCC.txt new file mode 100644 index 000000000..4e8c8d7fc --- /dev/null +++ b/docs/reports/LPC1343-72-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu +Settings: CLK=72, (3 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 19:42:36 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: LPC13xx +*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1343 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 268027 msgs/S, 536054 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 217012 msgs/S, 434024 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 217012 msgs/S, 434024 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 974024 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 161791 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 237078 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 67574 reschedules/S, 405444 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 512180 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 623284 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 665126 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 860284 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 635676 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC1343-72-IAR.txt b/docs/reports/LPC1343-72-IAR.txt new file mode 100644 index 000000000..f106ef9d3 --- /dev/null +++ b/docs/reports/LPC1343-72-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: CLK=72, (3 wait states) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 20:09:51 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: LPC13xx +*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1343 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 252028 msgs/S, 504056 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 220329 msgs/S, 440658 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 219661 msgs/S, 439322 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 856376 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 159269 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 223772 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 72334 reschedules/S, 434004 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 469472 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 646692 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 665016 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 1026020 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 661984 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC1343-72-RVCT.txt b/docs/reports/LPC1343-72-RVCT.txt new file mode 100644 index 000000000..f135a267a --- /dev/null +++ b/docs/reports/LPC1343-72-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: CLK=72, (3 wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 19:48:24 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: LPC13xx +*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1343 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 250294 msgs/S, 500588 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 219004 msgs/S, 438008 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 217021 msgs/S, 434042 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 885512 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 164008 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 233236 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 71977 reschedules/S, 431862 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 498840 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 613984 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 647154 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 984024 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 653036 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC2148-48-ARM.txt b/docs/reports/LPC2148-48-ARM.txt new file mode 100644 index 000000000..0d0e430df --- /dev/null +++ b/docs/reports/LPC2148-48-ARM.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 16:47:23 +*** Compiler: GCC 4.6.2 +*** Architecture: ARM7 +*** Core Variant: ARM7TDMI +*** Port Info: Pure ARM mode +*** Platform: LPC214x +*** Test Board: Olimex LPC-P2148 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 148529 msgs/S, 297058 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 113332 msgs/S, 226664 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 113332 msgs/S, 226664 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 493680 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 86173 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 122631 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 34987 reschedules/S, 209922 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 268312 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 388444 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 325360 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 607348 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 380356 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 364 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/LPC2148-48-THUMB.txt b/docs/reports/LPC2148-48-THUMB.txt new file mode 100644 index 000000000..c70f4276f --- /dev/null +++ b/docs/reports/LPC2148-48-THUMB.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 16:28:18 +*** Compiler: GCC 4.6.2 +*** Architecture: ARM7 +*** Core Variant: ARM7TDMI +*** Port Info: Pure THUMB mode +*** Platform: LPC214x +*** Test Board: Olimex LPC-P2148 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 107903 msgs/S, 215806 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 89018 msgs/S, 178036 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 89018 msgs/S, 178036 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 410760 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 69081 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 105994 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 29094 reschedules/S, 174564 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 210820 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 292036 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 326310 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 350856 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 244212 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 364 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/MSP430F1611-0.75.txt b/docs/reports/MSP430F1611-0.75.txt new file mode 100644 index 000000000..802d60e69 --- /dev/null +++ b/docs/reports/MSP430F1611-0.75.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer +Settings: MCLK=DCOCLK 750kHz +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 22 2012 - 20:51:54 +*** Compiler: GCC 3.2.3 +*** Architecture: MSP430 +*** Core Variant: MSP430 +*** Port Info: None +*** Platform: MSP430x16x +*** Test Board: Olimex MSP430-P1611 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 1880 msgs/S, 3760 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 1549 msgs/S, 3098 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 1549 msgs/S, 3098 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 5456 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 1065 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 1434 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 489 reschedules/S, 2934 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 3520 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 6340 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 5626 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 13908 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 7520 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 224 bytes +--- Thread: 38 bytes +--- Timer : 10 bytes +--- Semaph: 6 bytes +--- EventS: 2 bytes +--- EventL: 6 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 20 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/MSP430F1611-8.txt b/docs/reports/MSP430F1611-8.txt new file mode 100644 index 000000000..fd2ac8942 --- /dev/null +++ b/docs/reports/MSP430F1611-8.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer +Settings: MCLK=XT2CLK 8MHz +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.0 +*** Compiled: Apr 25 2012 - 11:28:57 +*** Compiler: GCC 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +*** Architecture: MSP430 +*** Core Variant: MSP430 +*** Port Info: None +*** Platform: MSP430 +*** Test Board: Olimex MSP430-P1611 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 22756 msgs/S, 45512 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 17949 msgs/S, 35898 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 17949 msgs/S, 35898 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 67552 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 12780 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 18071 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 5449 reschedules/S, 32694 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 42200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 73280 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 69456 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 140132 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 76804 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 222 bytes +--- Thread: 38 bytes +--- Timer : 10 bytes +--- Semaph: 6 bytes +--- EventS: 2 bytes +--- EventL: 6 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 20 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/SPC560B50-64.txt b/docs/reports/SPC560B50-64.txt new file mode 100644 index 000000000..d2c22581f --- /dev/null +++ b/docs/reports/SPC560B50-64.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=64 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Apr 26 2013 - 13:25:43 +*** Compiler: GCC 4.6.3 build on 2013-01-07 +*** Architecture: Power Architecture +*** Core Variant: e200z0 +*** Port Info: VLE mode +*** Platform: SPC560B/Cxx Car Body and Convenience +*** Test Board: Generic SPC560B/Cxx + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 200700 msgs/S, 401400 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 167515 msgs/S, 335030 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 167518 msgs/S, 335036 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 590288 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 132691 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 189383 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 52143 reschedules/S, 312858 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 392160 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 619272 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 792852 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 850984 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 649608 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 1052 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/SPC560P50-64.txt b/docs/reports/SPC560P50-64.txt new file mode 100644 index 000000000..34fdae5d9 --- /dev/null +++ b/docs/reports/SPC560P50-64.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=64 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Apr 26 2013 - 13:30:12 +*** Compiler: GCC 4.6.3 build on 2013-01-07 +*** Architecture: Power Architecture +*** Core Variant: e200z0 +*** Port Info: VLE mode +*** Platform: SPC560Pxx Chassis and Safety +*** Test Board: Generic SPC560Pxx + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 200703 msgs/S, 401406 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 167519 msgs/S, 335038 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 167519 msgs/S, 335038 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 590288 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 132689 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 189383 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 52143 reschedules/S, 312858 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 392160 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 619280 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 792852 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 850964 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 649584 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 1052 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/SPC563M64-80.txt b/docs/reports/SPC563M64-80.txt new file mode 100644 index 000000000..6d17cd808 --- /dev/null +++ b/docs/reports/SPC563M64-80.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=80 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Apr 26 2013 - 13:36:25 +*** Compiler: GCC 4.6.3 build on 2013-01-07 +*** Architecture: Power Architecture +*** Core Variant: e200z3 +*** Port Info: VLE mode +*** Platform: SPC563Mxx Powertrain +*** Test Board: Generic SPC563Mxx + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 267100 msgs/S, 534200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 214686 msgs/S, 429372 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 214686 msgs/S, 429372 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 880072 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 172117 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 251932 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 73531 reschedules/S, 441186 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 556476 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 803124 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 897800 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 948060 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 808692 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 1052 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/SPC564A64-150.txt b/docs/reports/SPC564A64-150.txt new file mode 100644 index 000000000..ad2d80d84 --- /dev/null +++ b/docs/reports/SPC564A64-150.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=150 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Apr 29 2013 - 11:08:09 +*** Compiler: GCC 4.6.3 build on 2013-01-07 +*** Architecture: Power Architecture +*** Core Variant: e200z4 +*** Port Info: VLE mode +*** Platform: SPC564Axx Powertrain +*** Test Board: Generic SPC564Axx + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 543008 msgs/S, 1086016 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 448711 msgs/S, 897422 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 448712 msgs/S, 897424 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 1547056 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 358539 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 518581 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 137368 reschedules/S, 824208 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 915500 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1624592 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 1897166 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 2688244 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1855960 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 1052 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/SPC56EL60-120.txt b/docs/reports/SPC56EL60-120.txt new file mode 100644 index 000000000..50a7ad9fe --- /dev/null +++ b/docs/reports/SPC56EL60-120.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=120 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Apr 29 2013 - 11:20:37 +*** Compiler: GCC 4.6.3 build on 2013-01-07 +*** Architecture: Power Architecture +*** Core Variant: e200z4 +*** Port Info: VLE mode +*** Platform: SPC56ELxx Chassis and Safety +*** Test Board: Generic SPC56ELxx + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 379277 msgs/S, 758554 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 312927 msgs/S, 625854 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 312931 msgs/S, 625862 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 1099584 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 250737 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 369918 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 94594 reschedules/S, 567564 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 633460 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1107176 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 1309908 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 1762548 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1239856 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 1052 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F051-48-GCC.txt b/docs/reports/STM32F051-48-GCC.txt new file mode 100644 index 000000000..1d2b671f5 --- /dev/null +++ b/docs/reports/STM32F051-48-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=48, ACR=0x11 (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.0 +*** Compiled: May 19 2012 - 17:24:06 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv6-M +*** Core Variant: Cortex-M0 +*** Port Info: Preemption through NMI +*** Platform: STM32F0 Entry Level +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 151223 msgs/S, 302446 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 119158 msgs/S, 238316 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 119158 msgs/S, 238316 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 456240 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 92602 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 132740 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 36254 reschedules/S, 217524 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 273820 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 427652 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 417370 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 682712 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 422920 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 404 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F100-24-GCC.txt b/docs/reports/STM32F100-24-GCC.txt new file mode 100644 index 000000000..7d22dd1ad --- /dev/null +++ b/docs/reports/STM32F100-24-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=24, ACR=0x10 (no wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 14:51:29 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Value Line Medium Density +*** Test Board: ST STM32VL-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 107466 msgs/S, 214932 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 88361 msgs/S, 176722 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 88361 msgs/S, 176722 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 364984 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 64312 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 91069 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 27423 reschedules/S, 164538 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 194360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 262192 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 305910 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 381748 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 268084 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F100-24-IAR.txt b/docs/reports/STM32F100-24-IAR.txt new file mode 100644 index 000000000..5c5d3512b --- /dev/null +++ b/docs/reports/STM32F100-24-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=24, ACR=0x10 (no wait states) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 14:57:36 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Value Line Medium Density +*** Test Board: ST STM32VL-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 99411 msgs/S, 198822 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 86444 msgs/S, 172888 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 86444 msgs/S, 172888 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 336632 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 62625 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 88700 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 28919 reschedules/S, 173514 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 183540 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 252964 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 309832 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 472444 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 271112 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F100-24-RVCT.txt b/docs/reports/STM32F100-24-RVCT.txt new file mode 100644 index 000000000..b747c1afe --- /dev/null +++ b/docs/reports/STM32F100-24-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=24, ACR=0x10 (no wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 15:04:43 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Value Line Medium Density +*** Test Board: ST STM32VL-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 101100 msgs/S, 202200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 86761 msgs/S, 173522 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 86761 msgs/S, 173522 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 340272 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 63800 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 91072 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 29203 reschedules/S, 175218 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 203920 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 242700 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 311922 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 454500 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 274248 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-48-GCC.txt b/docs/reports/STM32F103-48-GCC.txt new file mode 100644 index 000000000..a9e91a259 --- /dev/null +++ b/docs/reports/STM32F103-48-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=48, ACR=0x11 (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 11:54:27 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 197697 msgs/S, 395394 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 162180 msgs/S, 324360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 162180 msgs/S, 324360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 683520 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 118726 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 170879 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 49070 reschedules/S, 294420 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 347320 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 466776 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 490722 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 640048 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 461148 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-GCC-compact.txt b/docs/reports/STM32F103-72-GCC-compact.txt new file mode 100644 index 000000000..7cd8594e8 --- /dev/null +++ b/docs/reports/STM32F103-72-GCC-compact.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 11:58:05 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Compact kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 275197 msgs/S, 550394 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 221680 msgs/S, 443360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 221680 msgs/S, 443360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 952928 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 163998 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 240229 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 66137 reschedules/S, 396822 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 471772 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 623236 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 641326 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 842560 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 632848 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-GCC.txt b/docs/reports/STM32F103-72-GCC.txt new file mode 100644 index 000000000..d9345d56d --- /dev/null +++ b/docs/reports/STM32F103-72-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.0 +*** Compiled: Apr 25 2012 - 12:56:39 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 268998 msgs/S, 537996 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 213760 msgs/S, 427520 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 213760 msgs/S, 427520 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 975576 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 158908 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 236273 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 64647 reschedules/S, 387882 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 478040 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 623212 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 647076 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 787132 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 596056 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 404 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-IAR-compact.txt b/docs/reports/STM32F103-72-IAR-compact.txt new file mode 100644 index 000000000..cf318340a --- /dev/null +++ b/docs/reports/STM32F103-72-IAR-compact.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 12:04:29 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Compact kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 250283 msgs/S, 500566 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 216355 msgs/S, 432710 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 215059 msgs/S, 430118 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 850064 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 154479 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 228038 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 70146 reschedules/S, 420876 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 474140 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 664692 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 707650 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 1122300 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 650024 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-IAR.txt b/docs/reports/STM32F103-72-IAR.txt new file mode 100644 index 000000000..13b904158 --- /dev/null +++ b/docs/reports/STM32F103-72-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 12:19:46 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 241831 msgs/S, 483662 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 211248 msgs/S, 422496 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 210000 msgs/S, 420000 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 841272 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 149324 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 217650 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 69192 reschedules/S, 415152 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 467900 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 661520 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 690526 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 1071880 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 632748 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-RVCT-compact.txt b/docs/reports/STM32F103-72-RVCT-compact.txt new file mode 100644 index 000000000..21982a672 --- /dev/null +++ b/docs/reports/STM32F103-72-RVCT-compact.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 12:14:42 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Compact kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 245998 msgs/S, 491996 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 210638 msgs/S, 421276 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 210638 msgs/S, 421276 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 852568 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 157180 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 231712 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 67698 reschedules/S, 406188 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 504052 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 608404 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 598586 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 957740 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 669744 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F103-72-RVCT.txt b/docs/reports/STM32F103-72-RVCT.txt new file mode 100644 index 000000000..8b1192283 --- /dev/null +++ b/docs/reports/STM32F103-72-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 12:17:39 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Performance Line Medium Density +*** Test Board: Olimex STM32-P103 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 244331 msgs/S, 488662 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 212523 msgs/S, 425046 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 212523 msgs/S, 425046 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 860304 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 153165 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 224497 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 68542 reschedules/S, 411252 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 493700 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 574396 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 598628 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 855192 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 617932 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F107-72-GCC.txt b/docs/reports/STM32F107-72-GCC.txt new file mode 100644 index 000000000..a8290110c --- /dev/null +++ b/docs/reports/STM32F107-72-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 11:49:01 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Connectivity Line +*** Test Board: Olimex STM32-P107 + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 266998 msgs/S, 533996 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 213748 msgs/S, 427496 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 213748 msgs/S, 427496 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 962456 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 159254 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 236261 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 64820 reschedules/S, 388920 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 474856 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 608060 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 644192 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 787148 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 596068 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F303-72-GCC.txt b/docs/reports/STM32F303-72-GCC.txt new file mode 100644 index 000000000..5bff12cf5 --- /dev/null +++ b/docs/reports/STM32F303-72-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.1unstable +*** Compiled: Dec 5 2012 - 09:02:24 +*** Compiler: GCC 4.6.2 20120613 (release) [ARM/embedded-4_6-branch revision 188521] +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F30x Analog & DSP +*** Test Board: STMicroelectronics STM32F3-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 269999 msgs/S, 539998 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 214388 msgs/S, 428776 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 214388 msgs/S, 428776 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 975520 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 156477 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 235488 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 65113 reschedules/S, 390678 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 478800 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 621156 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 655900 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 787080 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 601008 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 404 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F373-72-GCC.txt b/docs/reports/STM32F373-72-GCC.txt new file mode 100644 index 000000000..fb4cb2f73 --- /dev/null +++ b/docs/reports/STM32F373-72-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=72, ACR=0x12 (2 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.2unstable +*** Compiled: Mar 3 2013 - 09:55:54 +*** Compiler: GCC 4.7.3 20121207 (release) [ARM/embedded-4_7-branch revision 194305] +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F37x Analog & DSP +*** Test Board: STMicroelectronics STM32373C-EVAL + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 263081 msgs/S, 526162 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 212496 msgs/S, 424992 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 212496 msgs/S, 424992 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 931272 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 157855 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 233196 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 64413 reschedules/S, 386478 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 475640 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 629324 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 655914 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 778572 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 576896 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 404 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 16 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 36 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F407-168-GCC-FPU.txt b/docs/reports/STM32F407-168-GCC-FPU.txt new file mode 100644 index 000000000..9b37d76f0 --- /dev/null +++ b/docs/reports/STM32F407-168-GCC-FPU.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.0 +*** Compiled: Apr 1 2012 - 14:19:33 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4F +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 576749 msgs/S, 1153498 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 493633 msgs/S, 987266 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 493631 msgs/S, 987262 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 1672112 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 382319 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 510144 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 156526 reschedules/S, 939156 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1063936 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1804680 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2124518 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 2685364 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1885792 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 644 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F407-168-GCC.txt b/docs/reports/STM32F407-168-GCC.txt new file mode 100644 index 000000000..e28a0a1f9 --- /dev/null +++ b/docs/reports/STM32F407-168-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.5.0 +*** Compiled: Apr 9 2012 - 15:07:48 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 752723 msgs/S, 1505446 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 617124 msgs/S, 1234248 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 617119 msgs/S, 1234238 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2528968 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 448823 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 635833 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 193383 reschedules/S, 1160298 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1356420 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1804932 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2124810 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 2685732 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1886044 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 372 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F407-168-IAR.txt b/docs/reports/STM32F407-168-IAR.txt new file mode 100644 index 000000000..c05a4d60e --- /dev/null +++ b/docs/reports/STM32F407-168-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 15 2012 - 20:30:59 +*** Compiler: IAR +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 682340 msgs/S, 1364680 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 593133 msgs/S, 1186266 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 593132 msgs/S, 1186264 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2315264 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 424953 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 603812 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 203217 reschedules/S, 1219302 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1370264 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1669144 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2098174 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 3010820 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1780940 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32F407-168-RVCT.txt b/docs/reports/STM32F407-168-RVCT.txt new file mode 100644 index 000000000..60ed4ab1c --- /dev/null +++ b/docs/reports/STM32F407-168-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=32, ACR=0x11 (1 wait state) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 15 2012 - 20:25:03 +*** Compiler: RVCT +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 711269 msgs/S, 1422538 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 610399 msgs/S, 1220798 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 610399 msgs/S, 1220798 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2393744 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 448826 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 640691 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 205457 reschedules/S, 1232742 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1434680 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1724960 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2223332 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 3197328 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1951860 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32L152-32-GCC.txt b/docs/reports/STM32L152-32-GCC.txt new file mode 100644 index 000000000..5218cd1ef --- /dev/null +++ b/docs/reports/STM32L152-32-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=32, ACR=0x11 (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 13:25:45 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32L1 Ultra Low Power Medium Density +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 131606 msgs/S, 263212 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 107961 msgs/S, 215922 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 107961 msgs/S, 215922 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 454200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 79829 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 114163 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 33107 reschedules/S, 198642 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 229120 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 329000 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 364000 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 468364 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 309232 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32L152-32-IAR.txt b/docs/reports/STM32L152-32-IAR.txt new file mode 100644 index 000000000..ce8093bf4 --- /dev/null +++ b/docs/reports/STM32L152-32-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=32, ACR=0x11 (1 wait state) +Compiler: IAR C/C++ Compiler for ARM 6.30.3.3241 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 13:30:39 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32L1 Ultra Low Power Medium Density +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 121100 msgs/S, 242200 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 106517 msgs/S, 213034 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 106517 msgs/S, 213034 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 418376 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 77689 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 110214 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 35153 reschedules/S, 210918 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 221188 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 312040 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 383674 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 522068 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 320060 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32L152-32-RVCT.txt b/docs/reports/STM32L152-32-RVCT.txt new file mode 100644 index 000000000..38e3f6ed7 --- /dev/null +++ b/docs/reports/STM32L152-32-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=32, ACR=0x11 (1 wait state) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 21 2012 - 13:38:29 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32L1 Ultra Low Power Medium Density +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 122507 msgs/S, 245014 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 106169 msgs/S, 212338 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 106525 msgs/S, 213050 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 427528 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 78454 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 112558 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 35469 reschedules/S, 212814 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 241292 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 307556 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 359934 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 530856 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 321748 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM8L152-16-Cosmic.txt b/docs/reports/STM8L152-16-Cosmic.txt new file mode 100644 index 000000000..a2d306326 --- /dev/null +++ b/docs/reports/STM8L152-16-Cosmic.txt @@ -0,0 +1,7 @@ +*************************************************************************** +Options: Optimized for speed +Settings: CPUCLK=16MHz (HSI) +Compiler: Cosmic STM8 compiler 4.3.6. +*************************************************************************** + +FAILED (compiler regression) \ No newline at end of file diff --git a/docs/reports/STM8L152-16-Raisonance.txt b/docs/reports/STM8L152-16-Raisonance.txt new file mode 100644 index 000000000..508866149 --- /dev/null +++ b/docs/reports/STM8L152-16-Raisonance.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: Optimized for speed +Settings: CPUCLK=16MHz (HSI) +Compiler: Raisonance RKit-STM8_2.32.10.0307 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 23 2012 - 19:04:23 +*** Compiler: Raisonance +*** Architecture: STM8 +*** Port Info: None +*** Platform: STM8L +*** Test Board: ST STM8L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 30270 msgs/S, 60540 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 23197 msgs/S, 46394 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 23197 msgs/S, 46394 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 107360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 17468 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 27274 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 6268 reschedules/S, 37608 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 53228 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 76448 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 57698 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 125104 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 123176 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 218 bytes +--- Thread: 34 bytes +--- Timer : 10 bytes +--- Semaph: 5 bytes +--- EventS: 2 bytes +--- EventL: 5 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 18 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM8S105-16-Cosmic.txt b/docs/reports/STM8S105-16-Cosmic.txt new file mode 100644 index 000000000..a2d306326 --- /dev/null +++ b/docs/reports/STM8S105-16-Cosmic.txt @@ -0,0 +1,7 @@ +*************************************************************************** +Options: Optimized for speed +Settings: CPUCLK=16MHz (HSI) +Compiler: Cosmic STM8 compiler 4.3.6. +*************************************************************************** + +FAILED (compiler regression) \ No newline at end of file diff --git a/docs/reports/STM8S105-16-Raisonance.txt b/docs/reports/STM8S105-16-Raisonance.txt new file mode 100644 index 000000000..ab926e136 --- /dev/null +++ b/docs/reports/STM8S105-16-Raisonance.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: Optimized for speed +Settings: CPUCLK=16MHz (HSE) +Compiler: Raisonance RKit-STM8_2.32.10.0307 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 23 2012 - 19:17:23 +*** Compiler: Raisonance +*** Architecture: STM8 +*** Port Info: None +*** Platform: STM8S +*** Test Board: ST STM8S-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 30272 msgs/S, 60544 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 23199 msgs/S, 46398 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 23199 msgs/S, 46398 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 107368 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 17469 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 27276 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 6269 reschedules/S, 37614 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 53236 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 76456 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 57702 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 125116 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 123188 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 218 bytes +--- Thread: 34 bytes +--- Timer : 10 bytes +--- Semaph: 5 bytes +--- EventS: 2 bytes +--- EventL: 5 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 18 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM8S208-16-Raisonance.txt b/docs/reports/STM8S208-16-Raisonance.txt new file mode 100644 index 000000000..f57609eac --- /dev/null +++ b/docs/reports/STM8S208-16-Raisonance.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: Optimized for speed (3) +Settings: CPUCLK=16MHz (HSI) +Compiler: Raisonance RKit-STM8_2.32.10.0307 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.4.0 +*** Compiled: Jan 25 2012 - 19:04:12 +*** Compiler: Raisonance +*** Architecture: STM8 +*** Port Info: None +*** Platform: STM8S +*** Test Board: Raisonance REva V3 + STM8S208RB + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 30272 msgs/S, 60544 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 23199 msgs/S, 46398 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 23199 msgs/S, 46398 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 107368 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 17469 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 27276 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 6269 reschedules/S, 37614 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 53236 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 76456 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 57702 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 125116 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 123188 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 218 bytes +--- Thread: 34 bytes +--- Timer : 10 bytes +--- Semaph: 5 bytes +--- EventS: 2 bytes +--- EventL: 5 bytes +--- Mutex : 8 bytes +--- CondV.: 4 bytes +--- Queue : 16 bytes +--- MailB.: 18 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/build.txt b/docs/reports/build.txt new file mode 100644 index 000000000..e05b19da9 --- /dev/null +++ b/docs/reports/build.txt @@ -0,0 +1,45 @@ +Default maximum settings + * Building...OK + * Testing...OK +CH_OPTIMIZE_SPEED=FALSE + * Building...OK + * Testing...OK +CH_TIME_QUANTUM=0 + * Building...OK + * Testing...OK +CH_USE_REGISTRY=FALSE + * Building...OK + * Testing...OK +CH_USE_SEMAPHORES_PRIORITY=TRUE + * Building...OK + * Testing...OK +CH_USE_CONDVARS_TIMEOUT=FALSE + * Building...OK + * Testing...OK +CH_USE_EVENTS_TIMEOUT=FALSE + * Building...OK + * Testing...OK +CH_USE_MESSAGES_PRIORITY=TRUE + * Building...OK + * Testing...OK +CH_USE_DYNAMIC=FALSE + * Building...OK + * Testing...OK +CH_DBG_SYSTEM_STATE_CHECK=TRUE + * Building...OK + * Testing...OK +CH_DBG_ENABLE_CHECKS=TRUE + * Building...OK + * Testing...OK +CH_DBG_ENABLE_ASSERTS=TRUE + * Building...OK + * Testing...OK +CH_DBG_ENABLE_TRACE=TRUE + * Building...OK + * Testing...OK +CH_DBG_FILL_THREADS=TRUE + * Building...OK + * Testing...OK +CH_DBG_THREADS_PROFILING=FALSE + * Building...OK + * Testing...OK diff --git a/docs/reports/coverage.txt b/docs/reports/coverage.txt new file mode 100644 index 000000000..a1ec85669 --- /dev/null +++ b/docs/reports/coverage.txt @@ -0,0 +1,75 @@ +mkdir gcov +gcov -u ..\..\os\kernel\src\chsys.c ..\..\os\kernel\src\chdebug.c ..\..\os\kernel\src\chlists.c ..\..\os\kernel\src\chvt.c ..\..\os\kernel\src\chschd.c ..\..\os\kernel\src\chthreads.c ..\..\os\kernel\src\chdynamic.c ..\..\os\kernel\src\chregistry.c ..\..\os\kernel\src\chsem.c ..\..\os\kernel\src\chmtx.c ..\..\os\kernel\src\chcond.c ..\..\os\kernel\src\chevents.c ..\..\os\kernel\src\chmsg.c ..\..\os\kernel\src\chmboxes.c ..\..\os\kernel\src\chqueues.c ..\..\os\kernel\src\chmemcore.c ..\..\os\kernel\src\chheap.c ..\..\os\kernel\src\chmempools.c +File `../../os/kernel/src/chsys.c' +Lines executed:100.00% of 21 +../../os/kernel/src/chsys.c:creating `chsys.c.gcov' + +File `../../os/kernel/src/chdebug.c' +Lines executed:100.00% of 10 +../../os/kernel/src/chdebug.c:creating `chdebug.c.gcov' + +File `../../os/kernel/src/chlists.c' +Lines executed:100.00% of 31 +../../os/kernel/src/chlists.c:creating `chlists.c.gcov' + +File `../../os/kernel/src/chvt.c' +Lines executed:100.00% of 29 +../../os/kernel/src/chvt.c:creating `chvt.c.gcov' + +File `../../os/kernel/src/chschd.c' +Lines executed:100.00% of 65 +../../os/kernel/src/chschd.c:creating `chschd.c.gcov' + +File `../../os/kernel/src/chthreads.c' +Lines executed:100.00% of 89 +../../os/kernel/src/chthreads.c:creating `chthreads.c.gcov' + +File `../../os/kernel/src/chdynamic.c' +Lines executed:100.00% of 50 +../../os/kernel/src/chdynamic.c:creating `chdynamic.c.gcov' + +File `../../os/kernel/src/chregistry.c' +Lines executed:100.00% of 18 +../../os/kernel/src/chregistry.c:creating `chregistry.c.gcov' + +File `../../os/kernel/src/chsem.c' +Lines executed:100.00% of 88 +../../os/kernel/src/chsem.c:creating `chsem.c.gcov' + +File `../../os/kernel/src/chmtx.c' +Lines executed:100.00% of 112 +../../os/kernel/src/chmtx.c:creating `chmtx.c.gcov' + +File `../../os/kernel/src/chcond.c' +Lines executed:100.00% of 59 +../../os/kernel/src/chcond.c:creating `chcond.c.gcov' + +File `../../os/kernel/src/chevents.c' +Lines executed:100.00% of 111 +../../os/kernel/src/chevents.c:creating `chevents.c.gcov' + +File `../../os/kernel/src/chmsg.c' +Lines executed:100.00% of 27 +../../os/kernel/src/chmsg.c:creating `chmsg.c.gcov' + +File `../../os/kernel/src/chmboxes.c' +Lines executed:100.00% of 94 +../../os/kernel/src/chmboxes.c:creating `chmboxes.c.gcov' + +File `../../os/kernel/src/chqueues.c' +Lines executed:96.72% of 122 +../../os/kernel/src/chqueues.c:creating `chqueues.c.gcov' + +File `../../os/kernel/src/chmemcore.c' +Lines executed:100.00% of 20 +../../os/kernel/src/chmemcore.c:creating `chmemcore.c.gcov' + +File `../../os/kernel/src/chheap.c' +Lines executed:100.00% of 79 +../../os/kernel/src/chheap.c:creating `chheap.c.gcov' + +File `../../os/kernel/src/chmempools.c' +Lines executed:100.00% of 28 +../../os/kernel/src/chmempools.c:creating `chmempools.c.gcov' + +mv -f *.gcov ./gcov diff --git a/docs/reports/kernel.txt b/docs/reports/kernel.txt new file mode 100644 index 000000000..42b5bfe35 --- /dev/null +++ b/docs/reports/kernel.txt @@ -0,0 +1,216 @@ +Platform : PowerPC +OS Setup : Full kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 12136 + +Platform : PowerPC +OS Setup : Full kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 11660 + +Platform : PowerPC +OS Setup : Minimal kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -O2 +Kernel Size = 2196 + +Platform : PowerPC +OS Setup : Full kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -Os -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 10664 + +Platform : PowerPC +OS Setup : Full kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -Os -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 10124 + +Platform : PowerPC +OS Setup : Minimal kernel +Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 +Options : -Os +Kernel Size = 2220 + +Platform : ARM Cortex-M3 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 6312 + +Platform : ARM Cortex-M3 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 5892 + +Platform : ARM Cortex-M3 +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb +Kernel Size = 1496 + +Platform : ARM Cortex-M3 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 5672 + +Platform : ARM Cortex-M3 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 5344 + +Platform : ARM Cortex-M3 +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb +Kernel Size = 1332 + +Platform : ARM Cortex-M0 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 5628 + +Platform : ARM Cortex-M0 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 5408 + +Platform : ARM Cortex-M0 +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb +Kernel Size = 1356 + +Platform : ARM Cortex-M0 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 5120 + +Platform : ARM Cortex-M0 +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 4968 + +Platform : ARM Cortex-M0 +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb +Kernel Size = 1220 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 9424 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 8876 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 +Kernel Size = 1932 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 8616 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 8240 + +Platform : ARM7TDMI (ARM mode) +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os +Kernel Size = 1676 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 6184 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 5948 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -O2 -mthumb -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 1384 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 5700 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Full kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 5512 + +Platform : ARM7TDMI (THUMB mode) +OS Setup : Minimal kernel +Compiler : arm-none-eabi-gcc (GCC) 4.6.2 +Options : -Os -mthumb -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING +Kernel Size = 1256 + +Platform : MSP430 +OS Setup : Full kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 6592 + +Platform : MSP430 +OS Setup : Full kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 6164 + +Platform : MSP430 +OS Setup : Minimal kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -O2 +Kernel Size = 1164 + +Platform : MSP430 +OS Setup : Full kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -Os -DCH_OPTIMIZE_SPEED=TRUE +Kernel Size = 5888 + +Platform : MSP430 +OS Setup : Full kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -Os -DCH_OPTIMIZE_SPEED=FALSE +Kernel Size = 5584 + +Platform : MSP430 +OS Setup : Minimal kernel +Compiler : msp430-gcc (GCC) 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) +Options : -Os +Kernel Size = 988 + diff --git a/docs/rsc/custom.css b/docs/rsc/custom.css new file mode 100644 index 000000000..4ac73ab1a --- /dev/null +++ b/docs/rsc/custom.css @@ -0,0 +1,800 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 12px; +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + padding: 2px; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code { + color: #4665A2; +} + +a.codeRef { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +.fragment { + font-family: monospace, fixed; + font-size: 105%; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 10px; + margin-right: 10px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C4CFE5; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.memitem { + padding: 0; + margin-bottom: 10px; +} + +.memname { + white-space: nowrap; + font-weight: bold; + margin-left: 6px; +} + +.memproto { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 8px; + border-top-left-radius: 8px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug +{ + border-left:4px solid; + padding: 0 0 0 6px; +} + +dl.note +{ + border-color: #D0D000; +} + +dl.warning, dl.attention +{ + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + border-color: #00D000; +} + +dl.deprecated +{ + border-color: #505050; +} + +dl.todo +{ + border-color: #00C0E0; +} + +dl.test +{ + border-color: #3030E0; +} + +dl.bug +{ + border-color: #C08050; +} + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectbrief +{ + font: 120% arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + diff --git a/docs/rsc/footer_chm.html b/docs/rsc/footer_chm.html new file mode 100644 index 000000000..6f8038e4f --- /dev/null +++ b/docs/rsc/footer_chm.html @@ -0,0 +1,4 @@ +
+Generated on $datetime for $projectname by doxygen $doxygenversion
+ + diff --git a/docs/rsc/footer_html.html b/docs/rsc/footer_html.html new file mode 100644 index 000000000..d6f2fa429 --- /dev/null +++ b/docs/rsc/footer_html.html @@ -0,0 +1,24 @@ +
  • + + Get ChibiOS/RT embedded RTOS at SourceForge.net. Fast, + secure and Free Open Source software downloads + +
    • + + + + + + + + diff --git a/docs/rsc/header_chm.html b/docs/rsc/header_chm.html new file mode 100644 index 000000000..4d3d6a90f --- /dev/null +++ b/docs/rsc/header_chm.html @@ -0,0 +1,21 @@ + + + + +$title + + + + +
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    ChibiOS/RT
    2.5.2
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000000000..acc5de238 --- /dev/null +++ b/docs/rsc/workspace.svg @@ -0,0 +1,280 @@ + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Workspace base Workspace top + + + Thread Structure intctx Structure Thread Stack Stack Pointer + + + + Thread Local Storage + chThdLS() Stack Limit + + + extctx Structure INT_REQUIRED_STACK + diff --git a/docs/src/concepts.dox b/docs/src/concepts.dox new file mode 100644 index 000000000..f46f8b06b --- /dev/null +++ b/docs/src/concepts.dox @@ -0,0 +1,410 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @page concepts Kernel Concepts + * @brief ChibiOS/RT Kernel Concepts + * - @ref naming + * - @ref api_suffixes + * - @ref interrupt_classes + * - @ref system_states + * - @ref scheduling + * - @ref thread_states + * - @ref priority + * - @ref warea + * . + * @section naming Naming Conventions + * ChibiOS/RT APIs are all named following this convention: + * @a ch\\\(). + * The possible groups are: @a Sys, @a Sch, @a Time, @a VT, @a Thd, @a Sem, + * @a Mtx, @a Cond, @a Evt, @a Msg, @a Reg, @a SequentialStream, @a IO, @a IQ, + * @a OQ, @a Dbg, @a Core, @a Heap, @a Pool. + * + * @section api_suffixes API Name Suffixes + * The suffix can be one of the following: + * - None, APIs without any suffix can be invoked only from the user + * code in the Normal state unless differently specified. See + * @ref system_states. + * - @anchor I-Class "I", I-Class APIs are invokable only from the + * I-Locked or S-Locked states. See @ref system_states. + * - @anchor S-Class "S", S-Class APIs are invokable only from the + * S-Locked state. See @ref system_states. + * . + * Examples: @p chThdCreateStatic(), @p chSemSignalI(), @p chIQGetTimeout(). + * + * @section interrupt_classes Interrupt Classes + * In ChibiOS/RT there are three logical interrupt classes: + * - Regular Interrupts. Maskable interrupt sources that cannot + * preempt (small parts of) the kernel code and are thus able to invoke + * operating system APIs from within their handlers. The interrupt handlers + * belonging to this class must be written following some rules. See the + * system APIs group and the web article + * + * How to write interrupt handlers. + * - Fast Interrupts. Maskable interrupt sources with the ability + * to preempt the kernel code and thus have a lower latency and are less + * subject to jitter, see the web article + * + * Response Time and Jitter. + * Such sources are not supported on all the architectures.
    + * Fast interrupts are not allowed to invoke any operating system API from + * within their handlers. Fast interrupt sources may, however, pend a lower + * priority regular interrupt where access to the operating system is + * possible. + * - Non Maskable Interrupts. Non maskable interrupt sources are + * totally out of the operating system control and have the lowest latency. + * Such sources are not supported on all the architectures. + * . + * The mapping of the above logical classes into physical interrupts priorities + * is, of course, port dependent. See the documentation of the various ports + * for details. + * + * @section system_states System States + * When using ChibiOS/RT the system can be in one of the following logical + * operating states: + * - Init. When the system is in this state all the maskable + * interrupt sources are disabled. In this state it is not possible to use + * any system API except @p chSysInit(). This state is entered after a + * physical reset. + * - Normal. All the interrupt sources are enabled and the system APIs + * are accessible, threads are running. + * - Suspended. In this state the fast interrupt sources are enabled but + * the regular interrupt sources are not. In this state it is not possible + * to use any system API except @p chSysDisable() or @p chSysEnable() in + * order to change state. + * - Disabled. When the system is in this state both the maskable + * regular and fast interrupt sources are disabled. In this state it is not + * possible to use any system API except @p chSysSuspend() or + * @p chSysEnable() in order to change state. + * - Sleep. Architecture-dependent low power mode, the idle thread + * goes in this state and waits for interrupts, after servicing the interrupt + * the Normal state is restored and the scheduler has a chance to reschedule. + * - S-Locked. Kernel locked and regular interrupt sources disabled. + * Fast interrupt sources are enabled. @ref S-Class and @ref I-Class APIs are + * invokable in this state. + * - I-Locked. Kernel locked and regular interrupt sources disabled. + * @ref I-Class APIs are invokable from this state. + * - Serving Regular Interrupt. No system APIs are accessible but it is + * possible to switch to the I-Locked state using @p chSysLockFromIsr() and + * then invoke any @ref I-Class API. Interrupt handlers can be preemptable on + * some architectures thus is important to switch to I-Locked state before + * invoking system APIs. + * - Serving Fast Interrupt. System APIs are not accessible. + * - Serving Non-Maskable Interrupt. System APIs are not accessible. + * - Halted. All interrupt sources are disabled and system stopped into + * an infinite loop. This state can be reached if the debug mode is activated + * and an error is detected or after explicitly invoking + * @p chSysHalt(). + * . + * Note that the above states are just Logical States that may have no + * real associated machine state on some architectures. The following diagram + * shows the possible transitions between the states: + * + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + edge [fontname=Helvetica, fontsize=8]; + init [label="Init", style="bold"]; + norm [label="Normal", shape=doublecircle]; + susp [label="Suspended"]; + disab [label="Disabled"]; + slock [label="S-Locked"]; + ilock [label="I-Locked"]; + slock [label="S-Locked"]; + sleep [label="Sleep"]; + sri [label="SRI"]; + init -> norm [label="chSysInit()"]; + norm -> slock [label="chSysLock()", constraint=false]; + slock -> norm [label="chSysUnlock()"]; + norm -> susp [label="chSysSuspend()"]; + susp -> disab [label="chSysDisable()"]; + norm -> disab [label="chSysDisable()"]; + susp -> norm [label="chSysEnable()"]; + disab -> norm [label="chSysEnable()"]; + disab -> susp [label="chSysSuspend()"]; + slock -> ilock [label="Context Switch", dir="both"]; + norm -> sri [label="Regular IRQ", style="dotted"]; + sri -> norm [label="Regular IRQ return", fontname=Helvetica, fontsize=8]; + sri -> ilock [label="chSysLockFromIsr()", constraint=false]; + ilock -> sri [label="chSysUnlockFromIsr()", fontsize=8]; + norm -> sleep [label="Idle Thread"]; + sleep -> sri [label="Regular IRQ", style="dotted"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + edge [fontname=Helvetica, fontsize=8]; + init [label="Init", style="bold"]; + norm [label="Normal", shape=doublecircle]; + susp [label="Suspended"]; + disab [label="Disabled"]; + slock [label="S-Locked"]; + ilock [label="I-Locked"]; + slock [label="S-Locked"]; + sleep [label="Sleep"]; + sri [label="SRI"]; + init -> norm [label="chSysInit()"]; + norm -> slock [label="chSysLock()", constraint=false]; + slock -> norm [label="chSysUnlock()"]; + norm -> susp [label="chSysSuspend()"]; + susp -> disab [label="chSysDisable()"]; + norm -> disab [label="chSysDisable()"]; + susp -> norm [label="chSysEnable()"]; + disab -> norm [label="chSysEnable()"]; + disab -> susp [label="chSysSuspend()"]; + slock -> ilock [label="Context Switch", dir="both"]; + norm -> sri [label="Regular IRQ", style="dotted"]; + sri -> norm [label="Regular IRQ return", fontname=Helvetica, fontsize=8]; + sri -> ilock [label="chSysLockFromIsr()", constraint=false]; + ilock -> sri [label="chSysUnlockFromIsr()", fontsize=8]; + norm -> sleep [label="Idle Thread"]; + sleep -> sri [label="Regular IRQ", style="dotted"]; + } + * @enddot + * @endif + * Note, the SFI, Halted and SNMI states were not shown + * because those are reachable from most states: + * + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + edge [fontname=Helvetica, fontsize=8]; + any1 [label="Any State\nexcept *"]; + sfi [label="SFI"]; + any1 -> sfi [style="dotted", label="Fast IRQ"]; + sfi -> any1 [label="Fast IRQ return"]; + } + * @enddot + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + edge [fontname=Helvetica, fontsize=8]; + any2 [label="Any State"]; + halt [label="Halted"]; + SNMI [label="SNMI"]; + any2 -> halt [label="chSysHalt()"]; + any2 -> SNMI [label="Synchronous NMI"]; + any2 -> SNMI [label="Asynchronous NMI", style="dotted"]; + SNMI -> any2 [label="NMI return"]; + halt -> SNMI [label="Asynchronous NMI", style="dotted"]; + SNMI -> halt [label="NMI return"]; + } + * @enddot + * @attention * except: Init, Halt, SNMI, Disabled. + * + * @section scheduling Scheduling + * The strategy is very simple the currently ready thread with the highest + * priority is executed. If more than one thread with equal priority are + * eligible for execution then they are executed in a round-robin way, the + * CPU time slice constant is configurable. The ready list is a double linked + * list of threads ordered by priority.

    + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + edge [fontname=Helvetica, fontsize=8]; + + subgraph cluster_running { + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + currp [label="'currp'\npointer", style="bold"]; + T4 [label="Tuser(4)\nprio=100"]; + label = "Currently Running Thread"; + penwidth = 0; + } + + subgraph cluster_rlist { + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + rh [label="ready list\nheader\nprio=0", style="bold"]; + Ti [label="Tidle\nprio=1"]; + Tm [label="Tmain\nprio=64"]; + T1 [label="Tuser(1)\nprio=32"]; + T2 [label="Tuser(2)\nprio=32"]; + T3 [label="Tuser(3)\nprio=80"]; + label = "Threads Ready for Execution"; + penwidth = 0; + } + + currp -> T4 + rh -> Ti -> T1 -> T2 -> Tm -> T3 -> rh [label="p_next"]; + rh -> T3 -> Tm -> T2 -> T1 -> Ti -> rh [label="p_prev"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + edge [fontname=Helvetica, fontsize=8]; + + subgraph cluster_running { + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + currp [label="'currp'\npointer", style="bold"]; + T4 [label="Tuser(4)\nprio=100"]; + label = "Currently Running Thread"; + penwidth = 0; + } + + subgraph cluster_rlist { + node [shape=square, fontname=Helvetica, fontsize=8, + fixedsize="true", width="0.6", height="0.5"]; + rh [label="ready list\nheader\nprio=0", style="bold"]; + Ti [label="Tidle\nprio=1"]; + Tm [label="Tmain\nprio=64"]; + T1 [label="Tuser(1)\nprio=32"]; + T2 [label="Tuser(2)\nprio=32"]; + T3 [label="Tuser(3)\nprio=80"]; + label = "Threads Ready for Execution"; + penwidth = 0; + } + + currp -> T4 + rh -> Ti -> T1 -> T2 -> Tm -> T3 -> rh [label="p_next"]; + rh -> T3 -> Tm -> T2 -> T1 -> Ti -> rh [label="p_prev"]; + } + * @enddot + * @endif + *
    + * Note that the currently running thread is not in the ready list, the list + * only contains the threads ready to be executed but still actually waiting. + * + * @section thread_states Thread States + * The image shows how threads can change their state in ChibiOS/RT.
    + * @if LATEX_PDF + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + size="5, 7"; + + edge [fontname=Helvetica, fontsize=8]; + start [label="Start", style="bold"]; + + run [label="Running"]; + ready [label="Ready"]; + suspend [label="Suspended"]; + sleep [label="Sleeping"]; + stop [label="Stop", style="bold"]; + + start -> suspend [label="\n chThdCreateI()", constraint=false, dir=back]; + start -> run [label="chThdCreate()"]; + start -> ready [label="chThdCreate()"]; + run -> ready [label="Reschedule", dir="both"]; + suspend -> run [label="chThdResume()"]; + suspend -> ready [label="chThdResume()"]; + run -> sleep [label="chSchGoSleepS()"]; + sleep -> run [label="chSchWakepuS()"]; + sleep -> ready [label="chSchWakepuS()"]; + run -> stop [label="chThdExit()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + + edge [fontname=Helvetica, fontsize=8]; + start [label="Start", style="bold"]; + + run [label="Running"]; + ready [label="Ready"]; + suspend [label="Suspended"]; + sleep [label="Sleeping"]; + stop [label="Stop", style="bold"]; + + start -> suspend [label="\n chThdCreateI()", constraint=false, dir=back]; + start -> run [label="chThdCreate()"]; + start -> ready [label="chThdCreate()"]; + run -> ready [label="Reschedule", dir="both"]; + suspend -> run [label="chThdResume()"]; + suspend -> ready [label="chThdResume()"]; + run -> sleep [label="chSchGoSleepS()"]; + sleep -> run [label="chSchWakepuS()"]; + sleep -> ready [label="chSchWakepuS()"]; + run -> stop [label="chThdExit()"]; + } + * @enddot + * @endif + * + * @section priority Priority Levels + * Priorities in ChibiOS/RT are a contiguous numerical range but the initial + * and final values are not enforced.
    + * The following table describes the various priority boundaries (from lowest + * to highest): + * - @p IDLEPRIO, this is the lowest priority level and is reserved for the + * idle thread, no other threads should share this priority level. This is + * the lowest numerical value of the priorities space. + * - @p LOWPRIO, the lowest priority level that can be assigned to an user + * thread. + * - @p NORMALPRIO, this is the central priority level for user threads. It is + * advisable to assign priorities to threads as values relative to + * @p NORMALPRIO, as example NORMALPRIO-1 or NORMALPRIO+4, this ensures the + * portability of code should the numerical range change in future + * implementations. + * - @p HIGHPRIO, the highest priority level that can be assigned to an user + * thread. + * - @p ABSPRO, absolute maximum software priority level, it can be higher than + * @p HIGHPRIO but the numerical values above @p HIGHPRIO up to @p ABSPRIO + * (inclusive) are reserved. This is the highest numerical value of the + * priorities space. + * . + * @section warea Thread Working Area + * Each thread has its own stack, a Thread structure and some preemption + * areas. All the structures are allocated into a "Thread Working Area", + * a thread private heap, usually statically declared in your code. + * Threads do not use any memory outside the allocated working area + * except when accessing static shared data.

    + * @if LATEX_PDF + * @image latex workspace.eps + * @else + * @image html workspace.png + * @endif + *
    + * Note that the preemption area is only present when the thread is not + * running (switched out), the context switching is done by pushing the + * registers on the stack of the switched-out thread and popping the registers + * of the switched-in thread from its stack. + * The preemption area can be divided in up to three structures: + * - External Context. + * - Interrupt Stack. + * - Internal Context. + * . + * See the port documentation for details, the area may change on + * the various ports and some structures may not be present (or be zero-sized). + */ diff --git a/docs/src/main.dox b/docs/src/main.dox new file mode 100644 index 000000000..535689d22 --- /dev/null +++ b/docs/src/main.dox @@ -0,0 +1,65 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @mainpage ChibiOS/RT + * @author Giovanni Di Sirio (gdisirio@users.sourceforge.net). + * + *

    Chibi ?

    + * I didn't want a serious name for this project. It is the Japanese word for + * small as in small child. So ChibiOS/RT + * @htmlonly (ちびOS/RT) @endhtmlonly + * means small Real Time Operating System. + * Source Wikipedia. + * + *

    Features

    + * - Free software, GPL3 licensed. Stable releases include a exception clause + * to the GPL. + * - Designed for realtime applications. + * - Easily portable. + * - Preemptive scheduling. + * - 128 priority levels. Multiple threads at the same priority level allowed. + * - Round robin scheduling for threads at the same priority level. + * - Offers threads, virtual timers, semaphores, mutexes, condvars, + * event flags, messages, mailboxes, I/O queues. + * - No static setup at compile time, there is no need to configure a maximum + * number of all the above objects. + * - PC simulator target included, the development can be done on a PC + * under Linux or Windows.
    + * Timers, I/O channels and other HW resources are simulated in a guest OS + * process and the application code does not need to be aware of it. + * - No *need* for a memory allocator, all the kernel structures are static + * and declaratively allocated. + * - Optional, thread safe, Heap Allocator subsystem. + * - Optional, thread safe, Memory Pools Allocator subsystem. + * - Blocking and non blocking I/O channels with timeout and events generation + * capability. + * - Minimal system requirements: about 6KiB ROM with all options enabled and + * speed optimizations on. The size can shrink under 2KiB by disabling the + * the unused subsystems and optimizing for size. + * - Almost totally written in C with little ASM code required for ports. + * - Optional Hardware Abstraction Layer (HAL) with support for many device + * driver models and device driver implementations. + * . + *

    Related pages

    + * - @subpage concepts + * - @subpage testsuite + * . + */ diff --git a/documentation.html b/documentation.html new file mode 100644 index 000000000..d9a44933d --- /dev/null +++ b/documentation.html @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/ext/ext.dox b/ext/ext.dox new file mode 100644 index 000000000..4f217a9d6 --- /dev/null +++ b/ext/ext.dox @@ -0,0 +1,39 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup external External Components + * ChibiOS/RT supports several external libraries through support interfaces + * and/or demos. Credit should be given to the original authors for making + * available such useful code.
    + * The current list of supported component is: + * - uIP, by Adam Dunkels at the Swedish Institute of Computer Science, + * link. + * - lwIP, many authors, + * link. + * - FatFs, by "ChaN", + * link. + * . + * External components and libraries are not directly supported and are used + * "as is" or with minor integration patching. + */ diff --git a/ext/fatfs-0.9-patched.zip b/ext/fatfs-0.9-patched.zip new file mode 100644 index 000000000..1c4fe889d Binary files /dev/null and b/ext/fatfs-0.9-patched.zip differ diff --git a/ext/lwip-1.4.1_patched.zip b/ext/lwip-1.4.1_patched.zip new file mode 100644 index 000000000..d236a40af Binary files /dev/null and b/ext/lwip-1.4.1_patched.zip differ diff --git a/ext/readme.txt b/ext/readme.txt new file mode 100644 index 000000000..04b45625d --- /dev/null +++ b/ext/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** External Libraries. ** +***************************************************************************** + +The libraries under this directory are not part of ChibiOS/RT but are used by +some of the demo applications. +Please note that each item is covered by its own license, please read the +instructions contained in the various distributions. + +The currently included items are: + +1. uip-1.0, a minimal TCP/IP implementation: http://www.sics.se/~adam/uip/ +2. lwip-1.4.0, lightweight TCP/IP stack: http://savannah.nongnu.org/projects/lwip/ +3. FatFS 0.9 (patched), the original version is available from + http://elm-chan.org/fsw/ff/00index_e.html + +The above files are included packed as downloaded from the original repository +and without any modification, in order to use the libraries unpack them +under ./ext as: + +./ext/uip-1.0 +./ext/lwip +./ext/fatfs +./ext/stm32lib (you also need to copy stm32f10x_conf.h in your project) + +Some patches are also present: + +1. uip-1.0 patches, small fixes to the uIP required to make it work with + ChibiOS/RT, unpack the archive over the uIP distribution and replace the + files. diff --git a/ext/uip-1.0.patches.zip b/ext/uip-1.0.patches.zip new file mode 100644 index 000000000..bdff1db6b Binary files /dev/null and b/ext/uip-1.0.patches.zip differ diff --git a/ext/uip-1.0.tar.gz b/ext/uip-1.0.tar.gz new file mode 100644 index 000000000..d5530ec3d Binary files /dev/null and b/ext/uip-1.0.tar.gz differ diff --git a/license.txt b/license.txt new file mode 100644 index 000000000..94a9ed024 --- /dev/null +++ b/license.txt @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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But first, please read +. diff --git a/os/fs/fatfs/fatfs_fsimpl.cpp b/os/fs/fatfs/fatfs_fsimpl.cpp new file mode 100644 index 000000000..567c7544a --- /dev/null +++ b/os/fs/fatfs/fatfs_fsimpl.cpp @@ -0,0 +1,210 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/** + * @file fs_fatfs_impl.cpp + * @brief FatFS file system wrapper. + * + * @addtogroup fs_fatfs_wrapper + * @{ + */ + +#include "ch.hpp" +#include "fs.hpp" +#include "fatfs_fsimpl.hpp" +#include "hal.h" + +#define MSG_TERMINATE (msg_t)0 + +#define ERR_OK (msg_t)0 +#define ERR_TERMINATING (msg_t)1 +#define ERR_UNKNOWN_MSG (msg_t)2 + +using namespace chibios_rt; +using namespace chibios_fs; + +/** + * @brief FatFS wrapper-related classes and interfaces. + */ +namespace chibios_fatfs { + + typedef struct { + uint32_t msg_code; + union { + struct { + + }; + } op; + } wmsg_t; + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSFileWrapper * + *------------------------------------------------------------------------*/ + FatFSFileWrapper::FatFSFileWrapper(void) : fs(NULL) { + + } + + FatFSFileWrapper::FatFSFileWrapper(FatFSWrapper *fsref) : fs(fsref) { + + } + + size_t FatFSFileWrapper::write(const uint8_t *bp, size_t n) { + + return 0; + } + + size_t FatFSFileWrapper::read(uint8_t *bp, size_t n) { + + return 0; + } + + msg_t FatFSFileWrapper::put(uint8_t b) { + + return 0; + } + + msg_t FatFSFileWrapper::get(void) { + + return 0; + } + + uint32_t FatFSFileWrapper::getAndClearLastError(void) { + + return 0; + } + + fileoffset_t FatFSFileWrapper::getSize(void) { + + return 0; + } + + fileoffset_t FatFSFileWrapper::getPosition(void) { + + return 0; + } + + uint32_t FatFSFileWrapper::setPosition(fileoffset_t offset) { + + return 0; + } + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSFilesPool * + *------------------------------------------------------------------------*/ + FatFSFilesPool::FatFSFilesPool(void) : ObjectsPool() { + + } + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSServerThread * + *------------------------------------------------------------------------*/ + FatFSServerThread::FatFSServerThread(void) : + BaseStaticThread() { + } + + msg_t FatFSServerThread::main() { + msg_t sts; + + setName("fatfs"); + + /* Synchronous messages processing loop.*/ + while (true) { + ThreadReference tr = waitMessage(); + msg_t msg = tr.getMessage(); + switch (msg) { + case MSG_TERMINATE: + /* The server object is being destroyed, terminating.*/ + tr.releaseMessage(ERR_TERMINATING); + return 0; + default: + sts = ERR_UNKNOWN_MSG; + } + tr.releaseMessage(sts); + } + } + + void FatFSServerThread::stop(void) { + + sendMessage(MSG_TERMINATE); + wait(); + } + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSWrapper * + *------------------------------------------------------------------------*/ + FatFSWrapper::FatFSWrapper(void) { + + } + + void FatFSWrapper::mount(void) { + + server.start(FATFS_THREAD_PRIORITY); + } + + void FatFSWrapper::unmount(void) { + + server.stop(); + } + + uint32_t FatFSWrapper::getAndClearLastError(void) { + + return 0; + } + + void FatFSWrapper::synchronize(void) { + + } + + void FatFSWrapper::remove(const char *fname) { + + (void)fname; + } + + BaseFileStreamInterface *FatFSWrapper::open(const char *fname) { + + (void)fname; + return NULL; + } + + BaseFileStreamInterface *FatFSWrapper::openForRead(const char *fname) { + + (void)fname; + return NULL; + } + + BaseFileStreamInterface *FatFSWrapper::openForWrite(const char *fname) { + + (void)fname; + return NULL; + } + + BaseFileStreamInterface *FatFSWrapper::create(const char *fname) { + + (void)fname; + return NULL; + } + + void FatFSWrapper::close(BaseFileStreamInterface *file) { + + (void)file; + } +} + +/** @} */ diff --git a/os/fs/fatfs/fatfs_fsimpl.hpp b/os/fs/fatfs/fatfs_fsimpl.hpp new file mode 100644 index 000000000..0993a7917 --- /dev/null +++ b/os/fs/fatfs/fatfs_fsimpl.hpp @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file fs_fatfs_impl.hpp + * @brief FatFS file system wrapper header. + * + * @addtogroup cpp_library + * @{ + */ + +#include "ch.hpp" +#include "fs.hpp" + +#ifndef _FS_FATFS_IMPL_HPP_ +#define _FS_FATFS_IMPL_HPP_ + +/** + * @brief Stack size for the internal server thread. + */ +#if !defined(FATFS_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define FATFS_THREAD_STACK_SIZE 1024 +#endif + +/** + * @brief Priority for the internal server thread. + */ +#if !defined(FATFS_THREAD_PRIORITY) || defined(__DOXYGEN__) +#define FATFS_THREAD_PRIORITY NORMALPRIO +#endif + +/** + * @brief Maximum number of open files. + */ +#if !defined(FATFS_MAX_FILES) || defined(__DOXYGEN__) +#define FATFS_MAX_FILES 16 +#endif + +using namespace chibios_rt; +using namespace chibios_fs; + +/** + * @brief FatFS wrapper-related classes and interfaces. + */ +namespace chibios_fatfs { + + class FatFSWrapper; + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSFileWrapper * + *------------------------------------------------------------------------*/ + class FatFSFileWrapper : public BaseFileStreamInterface { + friend class FatFSWrapper; + + protected: + FatFSWrapper *fs; + + public: + FatFSFileWrapper(void); + FatFSFileWrapper(FatFSWrapper *fsref); + + virtual size_t write(const uint8_t *bp, size_t n); + virtual size_t read(uint8_t *bp, size_t n); + virtual msg_t put(uint8_t b); + virtual msg_t get(void); + virtual uint32_t getAndClearLastError(void); + virtual fileoffset_t getSize(void); + virtual fileoffset_t getPosition(void); + virtual uint32_t setPosition(fileoffset_t offset); + }; + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSFilesPool * + *------------------------------------------------------------------------*/ + /** + * @brief Class of memory pool of @p FatFSFileWrapper objects. + */ + class FatFSFilesPool : public ObjectsPool { + public: + FatFSFilesPool(void); + }; + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSServerThread * + *------------------------------------------------------------------------*/ + /** + * @brief Class of the internal server thread. + */ + class FatFSServerThread : public BaseStaticThread { + private: + FatFSFilesPool files; + protected: + virtual msg_t main(void); + public: + FatFSServerThread(void); + virtual void stop(void); + }; + + /*------------------------------------------------------------------------* + * chibios_fatfs::FatFSWrapper * + *------------------------------------------------------------------------*/ + /** + * @brief Class of the FatFS wrapper. + */ + class FatFSWrapper : public chibios_fs::BaseFileSystemInterface { + friend class FatFSFileWrapper; + + protected: + FatFSServerThread server; + + public: + FatFSWrapper(void); + virtual uint32_t getAndClearLastError(void); + virtual void synchronize(void); + virtual void remove(const char *fname); + virtual BaseFileStreamInterface *open(const char *fname); + virtual BaseFileStreamInterface *openForRead(const char *fname); + virtual BaseFileStreamInterface *openForWrite(const char *fname); + virtual BaseFileStreamInterface *create(const char *fname); + virtual void close(BaseFileStreamInterface *file); + + /** + * @brief Mounts the file system. + */ + void mount(void); + + /** + * @brief Unmounts the file system. + */ + void unmount(void); + }; +} + +#endif /* _FS_FATFS_IMPL_HPP_ */ + +/** @} */ diff --git a/os/fs/fs.hpp b/os/fs/fs.hpp new file mode 100644 index 000000000..6a9bd6a5b --- /dev/null +++ b/os/fs/fs.hpp @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file fs.hpp + * @brief File System interfaces header. + * + * @addtogroup fs_interface + * @{ + */ + +#ifndef _FS_HPP_ +#define _FS_HPP_ + +#include "ch.hpp" + +/** + * @name Error codes + * @{ + */ +/** + * @brief No error return code. + */ +#define FILE_OK 0 + +/** + * @brief Error code from the file stream methods. + */ +#define FILE_ERROR 0xFFFFFFFFUL +/** @} */ + +/** + * @brief ChibiOS FS-related interfaces. + */ +namespace chibios_fs { + + /** + * @brief File offset type. + */ + typedef uint32_t fileoffset_t; + + /*------------------------------------------------------------------------* + * chibios_fs::BaseFileStreamInterface * + *------------------------------------------------------------------------*/ + /** + * @brief Interface of an abstract file object. + */ + class BaseFileStreamInterface : public chibios_rt::BaseSequentialStreamInterface { + public: + /** + * @brief Returns an implementation dependent error code. + * + * @return An implementation-dependent error code. + * + * @api + */ + virtual uint32_t getAndClearLastError(void) = 0; + + /** + * @brief Returns the current file size. + * + * @return The file size. + * @retval FILE_ERROR if the operation failed. + * + * @api + */ + virtual fileoffset_t getSize(void) = 0; + + /** + * @brief Returns the current file pointer position. + * + * @return The current position inside the file. + * @retval FILE_ERROR if the operation failed. + * + * @api + */ + virtual fileoffset_t getPosition(void) = 0; + + /** + * @brief sets the current file pointer position. + * + * @param[in] offset new absolute position + * @return The operation status. + * @retval FILE_OK if no error. + * @retval FILE_ERROR if the operation failed. + * + * @api + */ + virtual uint32_t setPosition(fileoffset_t offset) = 0; + }; + + /*------------------------------------------------------------------------* + * chibios_fs::BaseFileSystemInterface * + *------------------------------------------------------------------------*/ + /** + * @brief Interface of an abstract file system object. + * @note The interface only exposes common features, the implementing + * classes can offer an extended interface. + */ + class BaseFileSystemInterface { + public: + /** + * @brief Returns an implementation dependent error code. + * + * @return An implementation-dependent error code. + * + * @api + */ + virtual uint32_t getAndClearLastError(void) = 0; + + /** + * @brief Synchronizes caches with media device. + */ + virtual void synchronize(void) = 0; + + /** + * @brief Removes a file. + * + * @param[in] fname file name + * + * @api + */ + virtual void remove(const char *fname) = 0; + + /** + * @brief Opens a file for read and write. + * + * @param[in] fname file name + * @return An interface of a file object. + * @retval NULL if the operation failed. + * + * @api + */ + virtual BaseFileStreamInterface *open(const char *fname) = 0; + + /** + * @brief Opens a file for read only. + * + * @param[in] fname file name + * @return An interface of a file object. + * @retval NULL if the operation failed. + * + * @api + */ + virtual BaseFileStreamInterface *openForRead(const char *fname) = 0; + + /** + * @brief Opens a file for write only. + * + * @param[in] fname file name + * @return An interface of a file object. + * @retval NULL if the operation failed. + * + * @api + */ + virtual BaseFileStreamInterface *openForWrite(const char *fname) = 0; + + /** + * @brief Creates a file and opens it for write only. + * @details If a file with the same name already exists then it is + * overwritten. + * + * @param[in] fname file name + * @return An interface of a file object. + * @retval NULL if the operation failed. + * + * @api + */ + virtual BaseFileStreamInterface *create(const char *fname) = 0; + + /** + * @brief Closes a file. + * + * @api + */ + virtual void close(BaseFileStreamInterface *file) = 0; + }; +} +#endif /* _FS_HPP_ */ + +/** @} */ diff --git a/os/hal/dox/adc.dox b/os/hal/dox/adc.dox new file mode 100644 index 000000000..02bb24ac6 --- /dev/null +++ b/os/hal/dox/adc.dox @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup ADC ADC Driver + * @brief Generic ADC Driver. + * @details This module implements a generic ADC (Analog to Digital Converter) + * driver supporting a variety of buffer and conversion modes. + * @pre In order to use the ADC driver the @p HAL_USE_ADC option + * must be enabled in @p halconf.h. + * + * @section adc_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + rankdir="LR"; + size="5, 7"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="ADC_STOP\nLow Power"]; + uninit [label="ADC_UNINIT", style="bold"]; + ready [label="ADC_READY\nClock Enabled"]; + active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; + complete [label="ADC_COMPLETE\nComplete"]; + + uninit -> stop [label="\n adcInit()", constraint=false]; + stop -> ready [label="\nadcStart()"]; + ready -> ready [label="\nadcStart()\nadcStopConversion()"]; + ready -> stop [label="\nadcStop()"]; + stop -> stop [label="\nadcStop()"]; + ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; + active -> ready [label="\nadcStopConversion()\nsync return"]; + active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; + complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="ADC_STOP\nLow Power"]; + uninit [label="ADC_UNINIT", style="bold"]; + ready [label="ADC_READY\nClock Enabled"]; + active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; + complete [label="ADC_COMPLETE\nComplete"]; + + uninit -> stop [label="\n adcInit()", constraint=false]; + stop -> ready [label="\nadcStart()"]; + ready -> ready [label="\nadcStart()\nadcStopConversion()"]; + ready -> stop [label="\nadcStop()"]; + stop -> stop [label="\nadcStop()"]; + ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; + active -> ready [label="\nadcStopConversion()\nsync return"]; + active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; + complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; + } + * @enddot + * @endif + * + * @section adc_2 ADC Operations + * The ADC driver is quite complex, an explanation of the terminology and of + * the operational details follows. + * + * @subsection adc_2_1 ADC Conversion Groups + * The @p ADCConversionGroup is the objects that specifies a physical + * conversion operation. This structure contains some standard fields and + * several implementation-dependent fields.
    + * The standard fields define the CG mode, the number of channels belonging + * to the CG and the optional callbacks.
    + * The implementation-dependent fields specify the physical ADC operation + * mode, the analog channels belonging to the group and any other + * implementation-specific setting. Usually the extra fields just mirror + * the physical ADC registers, please refer to the vendor's MCU Reference + * Manual for details about the available settings. Details are also available + * into the documentation of the ADC low level drivers and in the various + * sample applications. + * + * @subsection adc_2_2 ADC Conversion Modes + * The driver supports several conversion modes: + * - One Shot, the driver performs a single group conversion then stops. + * - Linear Buffer, the driver performs a series of group conversions + * then stops. This mode is like a one shot conversion repeated N times, + * the buffer pointer increases after each conversion. The buffer is + * organized as an S(CG)*N samples matrix, when S(CG) is the conversion + * group size (number of channels) and N is the buffer depth (number of + * repeated conversions). + * - Circular Buffer, much like the linear mode but the operation does + * not stop when the buffer is filled, it is automatically restarted + * with the buffer pointer wrapping back to the buffer base. + * . + * @subsection adc_2_3 ADC Callbacks + * The driver is able to invoke callbacks during the conversion process. A + * callback is invoked when the operation has been completed or, in circular + * mode, when the buffer has been filled and the operation is restarted. In + * linear and circular modes a callback is also invoked when the buffer is + * half filled.
    + * The "half filled" and "filled" callbacks in circular mode allow to + * implement "streaming processing" of the sampled data, while the driver is + * busy filling one half of the buffer the application can process the + * other half, this allows for continuous interleaved operations. + * + * The driver is not thread safe for performance reasons, if you need to access + * the ADC bus from multiple threads then use the @p adcAcquireBus() and + * @p adcReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/os/hal/dox/can.dox b/os/hal/dox/can.dox new file mode 100644 index 000000000..e4a0d47a3 --- /dev/null +++ b/os/hal/dox/can.dox @@ -0,0 +1,92 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup CAN CAN Driver + * @brief Generic CAN Driver. + * @details This module implements a generic CAN (Controller Area Network) + * driver allowing the exchange of information at frame level. + * @pre In order to use the CAN driver the @p HAL_USE_CAN option + * must be enabled in @p halconf.h. + * + * @section can_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="CAN_STOP\nLow Power"]; + uninit [label="CAN_UNINIT", style="bold"]; + starting [label="CAN_STARTING\nInitializing"]; + ready [label="CAN_READY\nClock Enabled"]; + sleep [label="CAN_SLEEP\nLow Power"]; + + uninit -> stop [label=" canInit()", constraint=false]; + stop -> stop [label="\ncanStop()"]; + stop -> ready [label="\ncanStart()\n(fast implementation)"]; + stop -> starting [label="\ncanStart()\n(slow implementation)"]; + starting -> starting [label="\ncanStart()\n(other thread)"]; + starting -> ready [label="\ninitialization complete\n(all threads)"]; + ready -> stop [label="\ncanStop()"]; + ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"]; + ready -> sleep [label="\ncanSleep()"]; + sleep -> sleep [label="\ncanSleep()"]; + sleep -> ready [label="\ncanWakeup()"]; + sleep -> ready [label="\nhardware\nwakeup event"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="CAN_STOP\nLow Power"]; + uninit [label="CAN_UNINIT", style="bold"]; + starting [label="CAN_STARTING\nInitializing"]; + ready [label="CAN_READY\nClock Enabled"]; + sleep [label="CAN_SLEEP\nLow Power"]; + + uninit -> stop [label=" canInit()", constraint=false]; + stop -> stop [label="\ncanStop()"]; + stop -> ready [label="\ncanStart()\n(fast implementation)"]; + stop -> starting [label="\ncanStart()\n(slow implementation)"]; + starting -> starting [label="\ncanStart()\n(other thread)"]; + starting -> ready [label="\ninitialization complete\n(all threads)"]; + ready -> stop [label="\ncanStop()"]; + ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"]; + ready -> sleep [label="\ncanSleep()"]; + sleep -> sleep [label="\ncanSleep()"]; + sleep -> ready [label="\ncanWakeup()"]; + sleep -> ready [label="\nhardware\nwakeup event"]; + } + * @enddot + * @endif + * + * @ingroup IO + */ diff --git a/os/hal/dox/ext.dox b/os/hal/dox/ext.dox new file mode 100644 index 000000000..904c63f08 --- /dev/null +++ b/os/hal/dox/ext.dox @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup EXT EXT Driver + * @brief Generic EXT Driver. + * @details This module implements a generic EXT (EXTernal) driver. + * @pre In order to use the EXT driver the @p HAL_USE_EXT option + * must be enabled in @p halconf.h. + * + * @section ext_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @endif + * + * @section ext_2 EXT Operations. + * This driver abstracts generic external interrupt sources, a callback + * is invoked when a programmable transition is detected on one of the + * configured channels. Several channel modes are possible. + * - EXT_CH_MODE_DISABLED, channel not used. + * - EXT_CH_MODE_RISING_EDGE, callback on a rising edge. + * - EXT_CH_MODE_FALLING_EDGE, callback on a falling edge. + * - EXT_CH_MODE_BOTH_EDGES, callback on a both edges. + * . + * @ingroup IO + */ diff --git a/os/hal/dox/gpt.dox b/os/hal/dox/gpt.dox new file mode 100644 index 000000000..50a3ffd1e --- /dev/null +++ b/os/hal/dox/gpt.dox @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup GPT GPT Driver + * @brief Generic GPT Driver. + * @details This module implements a generic GPT (General Purpose Timer) + * driver. The timer can be programmed in order to trigger callbacks + * after a specified time period or continuously with a specified + * interval. + * @pre In order to use the GPT driver the @p HAL_USE_GPT option + * must be enabled in @p halconf.h. + * + * @section gpt_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="GPT_STOP\nLow Power"]; + uninit [label="GPT_UNINIT", style="bold"]; + ready [label="GPT_READY\nClock Enabled"]; + continuous [label="GPT_CONT..S\nContinuous\nMode"]; + oneshot [label="GPT_ONESHOT\nOne Shot\nMode"]; + + uninit -> stop [label=" gptInit()", constraint=false]; + stop -> stop [label="\ngptStop()"]; + stop -> ready [label="\ngptStart()"]; + ready -> stop [label="\ngptStop()"]; + ready -> ready [label="\ngptStart()"]; + ready -> continuous [label="\ngptStartContinuous()"]; + continuous -> ready [label="\ngptStopTimer()"]; + continuous -> continuous [label=">callback<"]; + ready -> oneshot [label="\ngptStartOneShot()\ngptPolledDelay()"]; + oneshot -> ready [label="\n>callback<\nor\nDelay Over"]; + } + * @enddot + * + * @section gpt_2 GPT Operations. + * This driver abstracts a generic timer composed of: + * - A clock prescaler. + * - A main up counter. + * - A comparator register that resets the main counter to zero when the limit + * is reached. A callback is invoked when this happens. + * . + * The timer can operate in three different modes: + * - Continuous Mode, a periodic callback is invoked until the driver + * is explicitly stopped. + * - One Shot Mode, a callback is invoked after the programmed period + * and then the timer automatically stops. + * - Delay Mode, the timer is used for inserting a brief delay into + * the execution flow, no callback is invoked in this mode. + * . + * @ingroup IO + */ diff --git a/os/hal/dox/hal.dox b/os/hal/dox/hal.dox new file mode 100644 index 000000000..1c449e7e3 --- /dev/null +++ b/os/hal/dox/hal.dox @@ -0,0 +1,36 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup HAL HAL Driver + * @brief Hardware Abstraction Layer. + * @details The HAL (Hardware Abstraction Layer) driver performs the system + * initialization and includes the platform support code shared by + * the other drivers. This driver does contain any API function + * except for a general initialization function @p halInit() that + * must be invoked before any HAL service can be used, usually the + * HAL initialization should be performed immediately before the + * kernel initialization.
    + * Some HAL driver implementations also offer a custom early clock + * setup function that can be invoked before the C runtime + * initialization in order to accelerate the startup time. + * + * @ingroup IO + */ diff --git a/os/hal/dox/i2c.dox b/os/hal/dox/i2c.dox new file mode 100644 index 000000000..4b2342e5d --- /dev/null +++ b/os/hal/dox/i2c.dox @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup I2C I2C Driver + * @brief Generic I2C Driver. + * @details This module implements a generic I2C (Inter-Integrated Circuit) + * driver. + * @pre In order to use the I2C driver the @p HAL_USE_I2C option + * must be enabled in @p halconf.h. + * + * @section i2c_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="I2C_STOP\nLow Power"]; + uninit [label="I2C_UNINIT", style="bold"]; + ready [label="I2C_READY\nClock Enabled"]; + active_tx [label="I2C_ACTIVE_TX\nBus TX Active"]; + active_rx [label="I2C_ACTIVE_RX\nBus RX Active"]; + locked [label="I2C_LOCKED\nBus Locked"]; + + uninit -> stop [label="i2cInit()", constraint=false]; + stop -> stop [label="i2cStop()"]; + stop -> ready [label="i2cStart()"]; + ready -> ready [label="i2cStart()"]; + ready -> stop [label="i2cStop()"]; + ready -> active_tx [label="i2cMasterTransmit()"]; + ready -> active_rx [label="i2cMasterReceive()"]; + active_tx -> ready [label="completed"]; + active_rx -> ready [label="completed"]; + active_tx -> locked [label="RDY_TIMEOUT"]; + active_rx -> locked [label="RDY_TIMEOUT"]; + locked -> stop [label="i2cStop()"]; + locked -> ready [label="i2cStart()"]; + } + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="I2C_STOP\nLow Power"]; + uninit [label="I2C_UNINIT", style="bold"]; + ready [label="I2C_READY\nClock Enabled"]; + active_tx [label="I2C_ACTIVE_TX\nBus TX Active"]; + active_rx [label="I2C_ACTIVE_RX\nBus RX Active"]; + locked [label="I2C_LOCKED\nBus Locked"]; + + uninit -> stop [label="i2cInit()", constraint=false]; + stop -> stop [label="i2cStop()"]; + stop -> ready [label="i2cStart()"]; + ready -> ready [label="i2cStart()"]; + ready -> stop [label="i2cStop()"]; + ready -> active_tx [label="i2cMasterTransmit()"]; + ready -> active_rx [label="i2cMasterReceive()"]; + active_tx -> ready [label="completed"]; + active_rx -> ready [label="completed"]; + active_tx -> locked [label="RDY_TIMEOUT"]; + active_rx -> locked [label="RDY_TIMEOUT"]; + locked -> stop [label="i2cStop()"]; + locked -> ready [label="i2cStart()"]; + } + * @enddot + * @endif + * The driver is not thread safe for performance reasons, if you need to access + * the I2C bus from multiple threads then use the @p i2cAcquireBus() and + * @p i2cReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/os/hal/dox/i2s.dox b/os/hal/dox/i2s.dox new file mode 100644 index 000000000..1dffb75d4 --- /dev/null +++ b/os/hal/dox/i2s.dox @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup I2S I2S Driver + * @brief Generic I2S Driver. + * @details This module implements a generic I2S driver. + * @pre In order to use the I2S driver the @p HAL_USE_I2S option + * must be enabled in @p halconf.h. + * + * @section i2s_1 Driver State Machine + * + * @ingroup IO + */ diff --git a/os/hal/dox/icu.dox b/os/hal/dox/icu.dox new file mode 100644 index 000000000..1d3fe092e --- /dev/null +++ b/os/hal/dox/icu.dox @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup ICU ICU Driver + * @brief Generic ICU Driver. + * @details This module implements a generic ICU (Input Capture Unit) driver. + * @pre In order to use the ICU driver the @p HAL_USE_ICU option + * must be enabled in @p halconf.h. + * + * @section icu_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="ICU_STOP\nLow Power"]; + uninit [label="ICU_UNINIT", style="bold"]; + ready [label="ICU_READY\nClock Enabled"]; + waiting [label="ICU_WAITING"]; + active [label="ICU_ACTIVE"]; + idle [label="ICU_IDLE"]; + + uninit -> stop [label=" icuInit()", constraint=false]; + stop -> stop [label="\nicuStop()"]; + stop -> ready [label="\nicuStart()"]; + ready -> stop [label="\nicuStop()"]; + ready -> ready [label="\nicuStart()\nicuDisable()"]; + ready -> waiting [label="\nicuEnable()"]; + waiting -> active [label="\nStart Front"]; + waiting -> ready [label="\nicuDisable()"]; + active -> idle [label="\nStop Front\n>width_cb<"]; + active -> ready [label="\nicuDisable()\nicuDisableI()"]; + idle -> active [label="\nStart Front\n>period_cb<"]; + idle -> ready [label="\nicuDisable()\nicuDisableI()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="ICU_STOP\nLow Power"]; + uninit [label="ICU_UNINIT", style="bold"]; + ready [label="ICU_READY\nClock Enabled"]; + waiting [label="ICU_WAITING"]; + active [label="ICU_ACTIVE"]; + idle [label="ICU_IDLE"]; + + uninit -> stop [label=" icuInit()", constraint=false]; + stop -> stop [label="\nicuStop()"]; + stop -> ready [label="\nicuStart()"]; + ready -> stop [label="\nicuStop()"]; + ready -> ready [label="\nicuStart()\nicuDisable()"]; + ready -> waiting [label="\nicuEnable()"]; + waiting -> active [label="\nStart Front"]; + waiting -> ready [label="\nicuDisable()"]; + active -> idle [label="\nStop Front\n>width_cb<"]; + active -> ready [label="\nicuDisable()\nicuDisableI()"]; + idle -> active [label="\nStart Front\n>period_cb<"]; + idle -> ready [label="\nicuDisable()\nicuDisableI()"]; + } + * @enddot + * @endif + * + * @section icu_2 ICU Operations. + * This driver abstracts a generic Input Capture Unit composed of: + * - A clock prescaler. + * - A main up counter. + * - Two capture registers triggered by the rising and falling edges on + * the sampled input. + * . + * The ICU unit can be programmed to synchronize on the rising or falling + * edge of the sample input: + * - ICU_INPUT_ACTIVE_HIGH, a rising edge is the start signal. + * - ICU_INPUT_ACTIVE_LOW, a falling edge is the start signal. + * . + * After the activation the ICU unit can be in one of the following + * states at any time: + * - ICU_WAITING, waiting the first start signal. + * - ICU_ACTIVE, after a start signal. + * - ICU_IDLE, after a stop signal. + * . + * Callbacks are invoked when start or stop signals occur. + * + * @ingroup IO + */ diff --git a/os/hal/dox/io_block.dox b/os/hal/dox/io_block.dox new file mode 100644 index 000000000..bc709f11e --- /dev/null +++ b/os/hal/dox/io_block.dox @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup IO_BLOCK Abstract I/O Block Device + * @ingroup IO + * + * @section io_block_1 Driver State Machine + * The drivers implementing this interface shall implement the following + * state machine internally. Not all the driver functionalities can be used + * in any moment, any transition not explicitly shown in the following + * diagram has to be considered an error and shall be captured by an + * assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="BLK_STOP\nLow Power"]; + uninit [label="BLK_UNINIT", style="bold"]; + active [label="BLK_ACTIVE\nClock Enabled"]; + connecting [label="BLK_CONN.ING\nConnecting"]; + disconnecting [label="BLK_DISC.ING\nDisconnecting"]; + ready [label="BLK_READY\nCard Ready"]; + reading [label="BLK_READING\nReading"]; + writing [label="BLK_WRITING\nWriting"]; + + uninit -> stop [label=" blkInit()", constraint=false]; + stop -> stop [label="\nblkStop()"]; + stop -> active [label="\nblkStart()"]; + active -> stop [label="\nblkStop()"]; + active -> active [label="\nblkStart()\nblkDisconnect()"]; + active -> connecting [label="\nblkConnect()"]; + connecting -> ready [label="\nconnection\nsuccessful"]; + connecting -> ready [label="\nblkConnect()", dir="back"]; + connecting -> active [label="\nconnection\nfailed"]; + disconnecting -> ready [label="\nblkDisconnect()", dir="back"]; + active -> disconnecting [label="\ndisconnection\nfinished", dir="back"]; + ready -> reading [label="\nblkRead()"]; + reading -> ready [label="\nread finished\nread error"]; + ready -> writing [label="\nblkWrite()"]; + writing -> ready [label="\nwrite finished\nwrite error"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="BLK_STOP\nLow Power"]; + uninit [label="BLK_UNINIT", style="bold"]; + active [label="BLK_ACTIVE\nClock Enabled"]; + connecting [label="BLK_CONN.ING\nConnecting"]; + disconnecting [label="BLK_DISC.ING\nDisconnecting"]; + ready [label="BLK_READY\nCard Ready"]; + reading [label="BLK_READING\nReading"]; + writing [label="BLK_WRITING\nWriting"]; + syncing [label="BLK_SYNCING\nSynchronizing"]; + + uninit -> stop [label=" blkInit()", constraint=false]; + stop -> stop [label="\nblkStop()"]; + stop -> active [label="\nblkStart()"]; + active -> stop [label="\nblkStop()"]; + active -> active [label="\nblkStart()\nblkDisconnect()"]; + active -> connecting [label="\nblkConnect()"]; + connecting -> ready [label="\nconnection\nsuccessful"]; + connecting -> ready [label="\nblkConnect()", dir="back"]; + connecting -> active [label="\nconnection\nfailed"]; + disconnecting -> ready [label="\nblkDisconnect()", dir="back"]; + active -> disconnecting [label="\ndisconnection\nfinished", dir="back"]; + ready -> reading [label="\nblkRead()"]; + reading -> ready [label="\nread finished\nread error"]; + ready -> writing [label="\nblkWrite()"]; + writing -> ready [label="\nwrite finished\nwrite error"]; + ready -> syncing [label="\nblkSync()"]; + syncing -> ready [label="\nsynchronization finished"]; + } + * @enddot + * @endif + */ diff --git a/os/hal/dox/io_channel.dox b/os/hal/dox/io_channel.dox new file mode 100644 index 000000000..66c6bae2c --- /dev/null +++ b/os/hal/dox/io_channel.dox @@ -0,0 +1,24 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup IO_CHANNEL Abstract I/O Channel + * @ingroup IO + */ diff --git a/os/hal/dox/mac.dox b/os/hal/dox/mac.dox new file mode 100644 index 000000000..f73185268 --- /dev/null +++ b/os/hal/dox/mac.dox @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup MAC MAC Driver + * @brief Generic MAC driver. + * @details This module implements a generic MAC (Media Access Control) + * driver for Ethernet controllers. + * @pre In order to use the MAC driver the @p HAL_USE_MAC option + * must be enabled in @p halconf.h. + * + * @ingroup IO + */ diff --git a/os/hal/dox/mmc_spi.dox b/os/hal/dox/mmc_spi.dox new file mode 100644 index 000000000..55dcaafd8 --- /dev/null +++ b/os/hal/dox/mmc_spi.dox @@ -0,0 +1,39 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup MMC_SPI MMC over SPI Driver + * @brief Generic MMC driver. + * @details This module implements a portable MMC/SD driver that uses a SPI + * driver as physical layer. Hot plugging and removal are supported + * through kernel events. + * @pre In order to use the MMC_SPI driver the @p HAL_USE_MMC_SPI and + * @p HAL_USE_SPI options must be enabled in @p halconf.h. + * + * @section mmc_spi_1 Driver State Machine + * This driver implements a state machine internally, see the @ref IO_BLOCK + * module documentation for details. + * + * @section mmc_spi_2 Driver Operations + * This driver allows to read or write single or multiple 512 bytes blocks + * on a SD Card. + * + * @ingroup IO + */ diff --git a/os/hal/dox/mmcsd.dox b/os/hal/dox/mmcsd.dox new file mode 100644 index 000000000..c7551b975 --- /dev/null +++ b/os/hal/dox/mmcsd.dox @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup MMCSD MMC/SD Block Device + * @details This module implements a common ancestor for all device drivers + * accessing MMC or SD cards. This interface inherits the state + * machine and the interface from the @ref IO_BLOCK module. + * + * @ingroup IO + */ diff --git a/os/hal/dox/pal.dox b/os/hal/dox/pal.dox new file mode 100644 index 000000000..d917545a7 --- /dev/null +++ b/os/hal/dox/pal.dox @@ -0,0 +1,74 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup PAL PAL Driver + * @brief I/O Ports Abstraction Layer + * @details This module defines an abstract interface for digital I/O ports. + * Note that most I/O ports functions are just macros. The macros + * have default software implementations that can be redefined in a + * PAL Low Level Driver if the target hardware supports special + * features like, for example, atomic bit set/reset/masking. Please + * refer to the ports specific documentation for details.
    + * The @ref PAL has the advantage to make the access to the I/O + * ports platform independent and still be optimized for the specific + * architectures.
    + * Note that the PAL Low Level Driver may also offer non standard + * macro and functions in order to support specific features but, + * of course, the use of such interfaces would not be portable. + * Such interfaces shall be marked with the architecture name inside + * the function names. + * @pre In order to use the PAL driver the @p HAL_USE_PAL option + * must be enabled in @p halconf.h. + * + * @section pal_1 Implementation Rules + * In implementing a PAL Low Level Driver there are some rules/behaviors that + * should be respected. + * + * @subsection pal_1_1 Writing on input pads + * The behavior is not specified but there are implementations better than + * others, this is the list of possible implementations, preferred options + * are on top: + * -# The written value is not actually output but latched, should the pads + * be reprogrammed as outputs the value would be in effect. + * -# The write operation is ignored. + * -# The write operation has side effects, as example disabling/enabling + * pull up/down resistors or changing the pad direction. This scenario is + * discouraged, please try to avoid this scenario. + * . + * @subsection pal_1_2 Reading from output pads + * The behavior is not specified but there are implementations better than + * others, this is the list of possible implementations, preferred options + * are on top: + * -# The actual pads states are read (not the output latch). + * -# The output latch value is read (regardless of the actual pads states). + * -# Unspecified, please try to avoid this scenario. + * . + * @subsection pal_1_3 Writing unused or unimplemented port bits + * The behavior is not specified. + * + * @subsection pal_1_4 Reading from unused or unimplemented port bits + * The behavior is not specified. + * + * @subsection pal_1_5 Reading or writing on pins associated to other functionalities + * The behavior is not specified. + * + * @ingroup IO + */ diff --git a/os/hal/dox/pwm.dox b/os/hal/dox/pwm.dox new file mode 100644 index 000000000..f990502a4 --- /dev/null +++ b/os/hal/dox/pwm.dox @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup PWM PWM Driver + * @brief Generic PWM Driver. + * @details This module implements a generic PWM (Pulse Width Modulation) + * driver. + * @pre In order to use the PWM driver the @p HAL_USE_PWM option + * must be enabled in @p halconf.h. + * + * @section pwm_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + uninit [label="PWM_UNINIT", style="bold"]; + stop [label="PWM_STOP\nLow Power"]; + ready [label="PWM_READY\nClock Enabled"]; + uninit -> stop [label="pwmInit()"]; + stop -> stop [label="pwmStop()"]; + stop -> ready [label="pwmStart()"]; + ready -> stop [label="pwmStop()"]; + ready -> ready [label="pwmEnableChannel()\npwmDisableChannel()"]; + } + * @enddot + * + * @section pwm_2 PWM Operations. + * This driver abstracts a generic PWM timer composed of: + * - A clock prescaler. + * - A main up counter. + * - A comparator register that resets the main counter to zero when the limit + * is reached. An optional callback can be generated when this happens. + * - An array of @p PWM_CHANNELS PWM channels, each channel has an output, + * a comparator and is able to invoke an optional callback when a comparator + * match with the main counter happens. + * . + * A PWM channel output can be in two different states: + * - IDLE, when the channel is disabled or after a match occurred. + * - ACTIVE, when the channel is enabled and a match didn't occur yet + * in the current PWM cycle. + * . + * Note that the two states can be associated to both logical zero or one in + * the @p PWMChannelConfig structure. + * + * @ingroup IO + */ diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox new file mode 100644 index 000000000..d80b6e837 --- /dev/null +++ b/os/hal/dox/rtc.dox @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup RTC RTC Driver + * @brief Real Time Clock Abstraction Layer + * @details This module defines an abstract interface for a Real Time Clock + * Peripheral. + * @pre In order to use the RTC driver the @p HAL_USE_RTC option + * must be enabled in @p halconf.h. + * + * @ingroup IO + */ diff --git a/os/hal/dox/sdc.dox b/os/hal/dox/sdc.dox new file mode 100644 index 000000000..073629457 --- /dev/null +++ b/os/hal/dox/sdc.dox @@ -0,0 +1,37 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup SDC SDC Driver + * @brief Generic SD Card Driver. + * @details This module implements a generic SDC (Secure Digital Card) driver. + * @pre In order to use the SDC driver the @p HAL_USE_SDC option + * must be enabled in @p halconf.h. + * + * @section sdc_1 Driver State Machine + * This driver implements a state machine internally, see the @ref IO_BLOCK + * module documentation for details. + * + * @section sdc_2 Driver Operations + * This driver allows to read or write single or multiple 512 bytes blocks + * on a SD Card. + * + * @ingroup IO + */ diff --git a/os/hal/dox/serial.dox b/os/hal/dox/serial.dox new file mode 100644 index 000000000..304955216 --- /dev/null +++ b/os/hal/dox/serial.dox @@ -0,0 +1,61 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup SERIAL Serial Driver + * @brief Generic Serial Driver. + * @details This module implements a generic full duplex serial driver. The + * driver implements a @p SerialDriver interface and uses I/O Queues + * for communication between the upper and the lower driver. Event + * flags are used to notify the application about incoming data, + * outgoing data and other I/O events.
    + * The module also contains functions that make the implementation + * of the interrupt service routines much easier. + * @pre In order to use the SERIAL driver the @p HAL_USE_SERIAL option + * must be enabled in @p halconf.h. + * + * + * @section serial_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="SD_UNINIT", style="bold"]; + stop [label="SD_STOP\nLow Power"]; + ready [label="SD_READY\nClock Enabled"]; + + uninit -> stop [label=" sdInit()"]; + stop -> stop [label="\nsdStop()"]; + stop -> ready [label="\nsdStart()"]; + ready -> stop [label="\nsdStop()"]; + ready -> ready [label="\nsdStart()"]; + ready -> ready [label="\nAny I/O operation"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/os/hal/dox/serial_usb.dox b/os/hal/dox/serial_usb.dox new file mode 100644 index 000000000..9377878ee --- /dev/null +++ b/os/hal/dox/serial_usb.dox @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup SERIAL_USB Serial over USB Driver + * @brief Serial over USB Driver. + * @details This module implements an USB Communication Device Class + * (CDC) as a normal serial communication port accessible from + * the device application. + * @pre In order to use the USB over Serial driver the + * @p HAL_USE_SERIAL_USB option must be enabled in @p halconf.h. + * + * @section usb_serial_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="SDU_UNINIT", style="bold"]; + stop [label="SDU_STOP\nLow Power"]; + ready [label="SDU_READY\nClock Enabled"]; + + uninit -> stop [label=" sduInit()"]; + stop -> stop [label="\nsduStop()"]; + stop -> ready [label="\nsduStart()"]; + ready -> stop [label="\nsduStop()"]; + ready -> ready [label="\nsduStart()"]; + ready -> ready [label="\nAny I/O operation"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/os/hal/dox/spi.dox b/os/hal/dox/spi.dox new file mode 100644 index 000000000..2143f9590 --- /dev/null +++ b/os/hal/dox/spi.dox @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup SPI SPI Driver + * @brief Generic SPI Driver. + * @details This module implements a generic SPI (Serial Peripheral Interface) + * driver allowing bidirectional and monodirectional transfers, + * complex atomic transactions are supported as well. + * @pre In order to use the SPI driver the @p HAL_USE_SPI option + * must be enabled in @p halconf.h. + * + * @section spi_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="SPI_STOP\nLow Power"]; + uninit [label="SPI_UNINIT", style="bold"]; + ready [label="SPI_READY\nClock Enabled"]; + active [label="SPI_ACTIVE\nBus Active"]; + complete [label="SPI_COMPLETE\nComplete"]; + + uninit -> stop [label="\n spiInit()", constraint=false]; + stop -> ready [label="\nspiStart()"]; + ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"]; + ready -> stop [label="\nspiStop()"]; + stop -> stop [label="\nspiStop()"]; + ready -> active [label="\nspiStartXXXI() (async)\nspiXXX() (sync)"]; + active -> ready [label="\nsync return"]; + active -> complete [label="\nasync callback\n>spc_endcb<"]; + complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="SPI_STOP\nLow Power"]; + uninit [label="SPI_UNINIT", style="bold"]; + ready [label="SPI_READY\nClock Enabled"]; + active [label="SPI_ACTIVE\nBus Active"]; + complete [label="SPI_COMPLETE\nComplete"]; + + uninit -> stop [label="\n spiInit()", constraint=false]; + stop -> ready [label="\nspiStart()"]; + ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"]; + ready -> stop [label="\nspiStop()"]; + stop -> stop [label="\nspiStop()"]; + ready -> active [label="\nspiStartXXX() (async)\nspiXXX() (sync)"]; + active -> ready [label="\nsync return"]; + active -> complete [label="\nasync callback\n>spc_endcb<"]; + complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + } + * @enddot + * @endif + * + * The driver is not thread safe for performance reasons, if you need to access + * the SPI bus from multiple threads then use the @p spiAcquireBus() and + * @p spiReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/os/hal/dox/tm.dox b/os/hal/dox/tm.dox new file mode 100644 index 000000000..939066bda --- /dev/null +++ b/os/hal/dox/tm.dox @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup TM Time Measurement Driver + * + * @brief Time Measurement unit. + * @details This module implements a time measurement mechanism able to + * monitor a portion of code and store the best/worst/last + * measurement. The measurement is performed using the realtime + * counter mechanism abstracted in the HAL driver. + * + * @ingroup IO + */ diff --git a/os/hal/dox/uart.dox b/os/hal/dox/uart.dox new file mode 100644 index 000000000..57ff5fbb6 --- /dev/null +++ b/os/hal/dox/uart.dox @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup UART UART Driver + * @brief Generic UART Driver. + * @details This driver abstracts a generic UART (Universal Asynchronous + * Receiver Transmitter) peripheral, the API is designed to be: + * - Unbuffered and copy-less, transfers are always directly performed + * from/to the application-level buffers without extra copy + * operations. + * - Asynchronous, the API is always non blocking. + * - Callbacks capable, operations completion and other events are + * notified using callbacks. + * . + * Special hardware features like deep hardware buffers, DMA transfers + * are hidden to the user but fully supportable by the low level + * implementations.
    + * This driver model is best used where communication events are + * meant to drive an higher level state machine, as example: + * - RS485 drivers. + * - Multipoint network drivers. + * - Serial protocol decoders. + * . + * If your application requires a synchronous buffered driver then + * the @ref SERIAL should be used instead. + * @pre In order to use the UART driver the @p HAL_USE_UART option + * must be enabled in @p halconf.h. + * + * @section uart_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="UART_UNINIT", style="bold"]; + stop [label="UART_STOP\nLow Power"]; + ready [label="UART_READY\nClock Enabled"]; + + uninit -> stop [label="\nuartInit()"]; + stop -> ready [label="\nuartStart()"]; + ready -> ready [label="\nuartStart()"]; + ready -> stop [label="\nuartStop()"]; + stop -> stop [label="\nuartStop()"]; + } + * @enddot + * + * @subsection uart_1_1 Transmitter sub State Machine + * The follow diagram describes the transmitter state machine, this diagram + * is valid while the driver is in the @p UART_READY state. This state + * machine is automatically reset to the @p TX_IDLE state each time the + * driver enters the @p UART_READY state. + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + tx_idle [label="TX_IDLE", style="bold"]; + tx_active [label="TX_ACTIVE"]; + tx_complete [label="TX_COMPLETE"]; + tx_fatal [label="Fatal Error", style="bold"]; + + tx_idle -> tx_active [label="\nuartStartSend()"]; + tx_idle -> tx_idle [label="\nuartStopSend()\n>uc_txend2<"]; + tx_active -> tx_complete [label="\nbuffer transmitted\n>uc_txend1<"]; + tx_active -> tx_idle [label="\nuartStopSend()"]; + tx_active -> tx_fatal [label="\nuartStartSend()"]; + tx_complete -> tx_active [label="\nuartStartSendI()\nthen\ncallback return"]; + tx_complete -> tx_idle [label="\ncallback return"]; + } + * @enddot + * + * @subsection uart_1_2 Receiver sub State Machine + * The follow diagram describes the receiver state machine, this diagram + * is valid while the driver is in the @p UART_READY state. This state + * machine is automatically reset to the @p RX_IDLE state each time the + * driver enters the @p UART_READY state. + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + rx_idle [label="RX_IDLE", style="bold"]; + rx_active [label="RX_ACTIVE"]; + rx_complete [label="RX_COMPLETE"]; + rx_fatal [label="Fatal Error", style="bold"]; + + rx_idle -> rx_idle [label="\nuartStopReceive()\n>uc_rxchar<\n>uc_rxerr<"]; + rx_idle -> rx_active [label="\nuartStartReceive()"]; + + rx_active -> rx_complete [label="\nbuffer filled\n>uc_rxend<"]; + rx_active -> rx_idle [label="\nuartStopReceive()"]; + rx_active -> rx_active [label="\nreceive error\n>uc_rxerr<"]; + rx_active -> rx_fatal [label="\nuartStartReceive()"]; + rx_complete -> rx_active [label="\nuartStartReceiveI()\nthen\ncallback return"]; + rx_complete -> rx_idle [label="\ncallback return"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/os/hal/dox/usb.dox b/os/hal/dox/usb.dox new file mode 100644 index 000000000..b71a75186 --- /dev/null +++ b/os/hal/dox/usb.dox @@ -0,0 +1,184 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup USB USB Driver + * @brief Generic USB Driver. + * @details This module implements a generic USB (Universal Serial Bus) driver + * supporting device-mode operations. + * @pre In order to use the USB driver the @p HAL_USE_USB option + * must be enabled in @p halconf.h. + * + * @section usb_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="USB_STOP\nLow Power"]; + uninit [label="USB_UNINIT", style="bold"]; + ready [label="USB_READY\nClock Enabled"]; + selected [label="\nUSB_SELECTED\naddress\nassigned"]; + active [label="\nUSB_ACTIVE\nconfiguration\nselected"]; + + uninit -> stop [label=" usbInit()", constraint=false]; + stop -> stop [label="\nusbStop()"]; + stop -> ready [label="\nusbStart()"]; + ready -> stop [label="\nusbStop()"]; + ready -> ready [label="\n\nusbStart()"]; + ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"]; + ready -> selected [label="\nSET_ADDRESS\n>event_cb<"]; + selected -> stop [label="\nusbStop()"]; + selected -> ready [label="\nUSB RESET\n>event_cb<"]; + selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"]; + selected -> active [label="\nSET_CONF(n)\n>event_cb<"]; + active -> stop [label="\nusbStop()"]; + active -> selected [label="\nSET_CONF(0)\n>event_cb<"]; + active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"]; + active -> ready [label="\nUSB RESET\n>event_cb<"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="USB_STOP\nLow Power"]; + uninit [label="USB_UNINIT", style="bold"]; + ready [label="USB_READY\nClock Enabled"]; + selected [label="\nUSB_SELECTED\naddress\nassigned"]; + active [label="\nUSB_ACTIVE\nconfiguration\nselected"]; + + uninit -> stop [label=" usbInit()", constraint=false]; + stop -> stop [label="\nusbStop()"]; + stop -> ready [label="\nusbStart()"]; + ready -> stop [label="\nusbStop()"]; + ready -> ready [label="\n\nusbStart()"]; + ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"]; + ready -> selected [label="\nSET_ADDRESS\n>event_cb<"]; + selected -> stop [label="\nusbStop()"]; + selected -> ready [label="\nUSB RESET\n>event_cb<"]; + selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"]; + selected -> active [label="\nSET_CONF(n)\n>event_cb<"]; + active -> stop [label="\nusbStop()"]; + active -> selected [label="\nSET_CONF(0)\n>event_cb<"]; + active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"]; + active -> ready [label="\nUSB RESET\n>event_cb<"]; + } + * @enddot + * @endif + * + * @section usb_2 USB Operations + * The USB driver is quite complex and USB is complex in itself, it is + * recommended to study the USB specification before trying to use the + * driver. + * + * @subsection usb_2_1 USB Implementation + * The USB driver abstracts the inner details of the underlying USB hardware. + * The driver works asynchronously and communicates with the application + * using callbacks. The application is responsible of the descriptors and + * strings required by the USB device class to be implemented and of the + * handling of the specific messages sent over the endpoint zero. Standard + * messages are handled internally to the driver. The application can use + * hooks in order to handle custom messages or override the handling of the + * default handling of standard messages. + * + * @subsection usb_2_2 USB Endpoints + * USB endpoints are the objects that the application uses to exchange + * data with the host. There are two kind of endpoints: + * - IN endpoints are used by the application to transmit data to + * the host.
    + * - OUT endpoints are used by the application to receive data from + * the host. + * . + * The driver invokes a callback after finishing an IN or OUT transaction. + * States diagram for OUT endpoints in transaction mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + receiving [label="EP_BUSY\nReceiving"]; + idle [label="EP_IDLE\nReady"]; + + disabled -> idle [label="\nusbInitEndpointI()"]; + idle -> receiving [label="\nusbPrepareReceive()\nusbStartReceiveI()"]; + receiving -> receiving [label="\nmore packets"]; + receiving -> idle [label="\nreception end\n>out_cb<"]; + receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

    + * States diagram for IN endpoints in transaction mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + transmitting [label="EP_BUSY\nTransmitting"]; + idle [label="EP_IDLE\nReady"]; + + disabled -> idle [label="\usbInitEndpointI()"]; + idle -> transmitting [label="\nusbPrepareTransmit()\nusbStartTransmitI()"]; + transmitting -> transmitting [label="\nmore packets"]; + transmitting -> idle [label="\ntransmission end\n>in_cb<"]; + transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

    + * + * @subsection usb_2_4 USB Callbacks + * The USB driver uses callbacks in order to interact with the application. + * There are several kinds of callbacks to be handled: + * - Driver events callback. As example errors, suspend event, reset event + * etc. + * - Messages Hook callback. This hook allows the application to implement + * handling of custom messages or to override the default handling of + * standard messages on endpoint zero. + * - Descriptor Requested callback. When the driver endpoint zero handler + * receives a GET DESCRIPTOR message and needs to send a descriptor to + * the host it queries the application using this callback. + * - Start of Frame callback. This callback is invoked each time a SOF + * packet is received. + * - Endpoint callbacks. Each endpoint informs the application about I/O + * conditions using those callbacks. + * . + * + * @ingroup IO + */ diff --git a/os/hal/hal.dox b/os/hal/hal.dox new file mode 100644 index 000000000..3e747a4ad --- /dev/null +++ b/os/hal/hal.dox @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup IO HAL + * @brief Hardware Abstraction Layer. + * @details Under ChibiOS/RT the set of the various device driver interfaces + * is called the HAL subsystem: Hardware Abstraction Layer. The HAL is the + * abstract interface between ChibiOS/RT application and hardware. + * + * @section hal_device_driver_arch HAL Device Drivers Architecture + * A device driver is usually split in two layers: + * - High Level Device Driver (HLD). This layer contains the definitions + * of the driver's APIs and the platform independent part of the driver.
    + * An HLD is composed by two files: + * - @p @.c, the HLD implementation file. This file must be + * included in the Makefile in order to use the driver. + * - @p @.h, the HLD header file. This file is implicitly + * included by the HAL header file @p hal.h. + * . + * - Low Level Device Driver (LLD). This layer contains the platform + * dependent part of the driver.
    + * A LLD is composed by two files: + * - @p @_lld.c, the LLD implementation file. This file must be + * included in the Makefile in order to use the driver. + * - @p @_lld.h, the LLD header file. This file is implicitly + * included by the HLD header file. + * . + * The LLD may be not present in those drivers that do not access the + * hardware directly but through other device drivers, as example the + * MMC_SPI driver uses the SPI and PAL drivers in order to implement + * its functionalities. + * . + * @subsection hal_device_driver_diagram Diagram + * @dot + digraph example { + graph [size="5, 7", pad="1.5, 0"]; + node [shape=rectangle, fontname=Helvetica, fontsize=8, + fixedsize="true", width="2.0", height="0.4"]; + edge [fontname=Helvetica, fontsize=8]; + + app [label="Application"]; + hld [label="High Level Driver"]; + lld [label="Low Level Driver"]; + hw [label="Microcontroller Hardware"]; + hal_lld [label="HAL shared low level code"]; + + app->hld; + hld->lld; + lld-> hw; + lld->hal_lld; + hal_lld->hw; + } + * @enddot + */ + +/** + * @defgroup HAL_CONF Configuration + * @brief HAL Configuration. + * @details The file @p halconf.h contains the high level settings for all + * the drivers supported by the HAL. The low level, platform dependent, + * settings are contained in the @p mcuconf.h file instead and are describe + * in the various platforms reference manuals. + * + * @ingroup IO + */ diff --git a/os/hal/hal.mk b/os/hal/hal.mk new file mode 100644 index 000000000..b2eed900e --- /dev/null +++ b/os/hal/hal.mk @@ -0,0 +1,25 @@ +# List of all the ChibiOS/RT HAL files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing halconf.h. +HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ + ${CHIBIOS}/os/hal/src/adc.c \ + ${CHIBIOS}/os/hal/src/can.c \ + ${CHIBIOS}/os/hal/src/ext.c \ + ${CHIBIOS}/os/hal/src/gpt.c \ + ${CHIBIOS}/os/hal/src/i2c.c \ + ${CHIBIOS}/os/hal/src/icu.c \ + ${CHIBIOS}/os/hal/src/mac.c \ + ${CHIBIOS}/os/hal/src/mmc_spi.c \ + ${CHIBIOS}/os/hal/src/mmcsd.c \ + ${CHIBIOS}/os/hal/src/pal.c \ + ${CHIBIOS}/os/hal/src/pwm.c \ + ${CHIBIOS}/os/hal/src/rtc.c \ + ${CHIBIOS}/os/hal/src/sdc.c \ + ${CHIBIOS}/os/hal/src/serial.c \ + ${CHIBIOS}/os/hal/src/serial_usb.c \ + ${CHIBIOS}/os/hal/src/spi.c \ + ${CHIBIOS}/os/hal/src/tm.c \ + ${CHIBIOS}/os/hal/src/uart.c \ + ${CHIBIOS}/os/hal/src/usb.c + +# Required include directories +HALINC = ${CHIBIOS}/os/hal/include diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h new file mode 100644 index 000000000..c41435452 --- /dev/null +++ b/os/hal/include/adc.h @@ -0,0 +1,317 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file adc.h + * @brief ADC Driver macros and structures. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_H_ +#define _ADC_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name ADC configuration options + * @{ + */ +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if ADC_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "ADC_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ADC_UNINIT = 0, /**< Not initialized. */ + ADC_STOP = 1, /**< Stopped. */ + ADC_READY = 2, /**< Ready. */ + ADC_ACTIVE = 3, /**< Converting. */ + ADC_COMPLETE = 4, /**< Conversion complete. */ + ADC_ERROR = 5 /**< Conversion complete. */ +} adcstate_t; + +#include "adc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Low Level driver helper macros + * @{ + */ +#if ADC_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Resumes a thread waiting for a conversion completion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_reset_i(adcp) { \ + if ((adcp)->thread != NULL) { \ + Thread *tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_RESET; \ + chSchReadyI(tp); \ + } \ +} + +/** + * @brief Resumes a thread waiting for a conversion completion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_reset_s(adcp) { \ + if ((adcp)->thread != NULL) { \ + Thread *tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + chSchWakeupS(tp, RDY_RESET); \ + } \ +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_wakeup_isr(adcp) { \ + chSysLockFromIsr(); \ + if ((adcp)->thread != NULL) { \ + Thread *tp; \ + tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_OK; \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Wakes up the waiting thread with a timeout message. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_timeout_isr(adcp) { \ + chSysLockFromIsr(); \ + if ((adcp)->thread != NULL) { \ + Thread *tp; \ + tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_TIMEOUT; \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +#else /* !ADC_USE_WAIT */ +#define _adc_reset_i(adcp) +#define _adc_reset_s(adcp) +#define _adc_wakeup_isr(adcp) +#define _adc_timeout_isr(adcp) +#endif /* !ADC_USE_WAIT */ + +/** + * @brief Common ISR code, half buffer event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_isr_half_code(adcp) { \ + if ((adcp)->grpp->end_cb != NULL) { \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth / 2); \ + } \ +} + +/** + * @brief Common ISR code, full buffer event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread wakeup, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_isr_full_code(adcp) { \ + if ((adcp)->grpp->circular) { \ + /* Callback handling.*/ \ + if ((adcp)->grpp->end_cb != NULL) { \ + if ((adcp)->depth > 1) { \ + /* Invokes the callback passing the 2nd half of the buffer.*/ \ + size_t half = (adcp)->depth / 2; \ + size_t half_index = half * (adcp)->grpp->num_channels; \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ + } \ + else { \ + /* Invokes the callback passing the whole buffer.*/ \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ + } \ + } \ + } \ + else { \ + /* End conversion.*/ \ + adc_lld_stop_conversion(adcp); \ + if ((adcp)->grpp->end_cb != NULL) { \ + (adcp)->state = ADC_COMPLETE; \ + if ((adcp)->depth > 1) { \ + /* Invokes the callback passing the 2nd half of the buffer.*/ \ + size_t half = (adcp)->depth / 2; \ + size_t half_index = half * (adcp)->grpp->num_channels; \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ + } \ + else { \ + /* Invokes the callback passing the whole buffer.*/ \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ + } \ + if ((adcp)->state == ADC_COMPLETE) { \ + (adcp)->state = ADC_READY; \ + (adcp)->grpp = NULL; \ + } \ + } \ + else { \ + (adcp)->state = ADC_READY; \ + (adcp)->grpp = NULL; \ + } \ + _adc_wakeup_isr(adcp); \ + } \ +} + +/** + * @brief Common ISR code, error event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread timeout signaling, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] err platform dependent error code + * + * @notapi + */ +#define _adc_isr_error_code(adcp, err) { \ + adc_lld_stop_conversion(adcp); \ + if ((adcp)->grpp->error_cb != NULL) { \ + (adcp)->state = ADC_ERROR; \ + (adcp)->grpp->error_cb(adcp, err); \ + if ((adcp)->state == ADC_ERROR) \ + (adcp)->state = ADC_READY; \ + } \ + (adcp)->grpp = NULL; \ + _adc_timeout_isr(adcp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void adcInit(void); + void adcObjectInit(ADCDriver *adcp); + void adcStart(ADCDriver *adcp, const ADCConfig *config); + void adcStop(ADCDriver *adcp); + void adcStartConversion(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); + void adcStartConversionI(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); + void adcStopConversion(ADCDriver *adcp); + void adcStopConversionI(ADCDriver *adcp); +#if ADC_USE_WAIT + msg_t adcConvert(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + void adcAcquireBus(ADCDriver *adcp); + void adcReleaseBus(ADCDriver *adcp); +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_H_ */ + +/** @} */ diff --git a/os/hal/include/can.h b/os/hal/include/can.h new file mode 100644 index 000000000..6cd2f55c1 --- /dev/null +++ b/os/hal/include/can.h @@ -0,0 +1,168 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file can.h + * @brief CAN Driver macros and structures. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_H_ +#define _CAN_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CAN status flags + * @{ + */ +/** + * @brief Errors rate warning. + */ +#define CAN_LIMIT_WARNING 1 +/** + * @brief Errors rate error. + */ +#define CAN_LIMIT_ERROR 2 +/** + * @brief Bus off condition reached. + */ +#define CAN_BUS_OFF_ERROR 4 +/** + * @brief Framing error of some kind on the CAN bus. + */ +#define CAN_FRAMING_ERROR 8 +/** + * @brief Overflow in receive queue. + */ +#define CAN_OVERFLOW_ERROR 16 +/** @} */ + +/** + * @brief Special mailbox identifier. + */ +#define CAN_ANY_MAILBOX 0 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name CAN configuration options + * @{ + */ +/** + * @brief Sleep mode related APIs inclusion switch. + * @details This option can only be enabled if the CAN implementation supports + * the sleep mode, see the macro @p CAN_SUPPORTS_SLEEP exported by + * the underlying implementation. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS +#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + CAN_UNINIT = 0, /**< Not initialized. */ + CAN_STOP = 1, /**< Stopped. */ + CAN_STARTING = 2, /**< Starting. */ + CAN_READY = 3, /**< Ready. */ + CAN_SLEEP = 4 /**< Sleep state. */ +} canstate_t; + +#include "can_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Converts a mailbox index to a bit mask. + */ +#define CAN_MAILBOX_TO_MASK(mbx) (1 << ((mbx) - 1)) + +/** + * @brief Adds some flags to the CAN status mask. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mask flags to be added to the status mask + * + * @iclass + */ +#define canAddFlagsI(canp, mask) ((canp)->status |= (mask)) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void canInit(void); + void canObjectInit(CANDriver *canp); + void canStart(CANDriver *canp, const CANConfig *config); + void canStop(CANDriver *canp); + msg_t canTransmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp, + systime_t timeout); + msg_t canReceive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp, + systime_t timeout); +#if CAN_USE_SLEEP_MODE + void canSleep(CANDriver *canp); + void canWakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_H_ */ + +/** @} */ diff --git a/os/hal/include/ext.h b/os/hal/include/ext.h new file mode 100644 index 000000000..7f32c5f1f --- /dev/null +++ b/os/hal/include/ext.h @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ext.h + * @brief EXT Driver macros and structures. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_H_ +#define _EXT_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name EXT channel modes + * @{ + */ +#define EXT_CH_MODE_EDGES_MASK 3 /**< @brief Mask of edges field. */ +#define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */ +#define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */ +#define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */ +#define EXT_CH_MODE_BOTH_EDGES 3 /**< @brief Both edges callback. */ + +#define EXT_CH_MODE_AUTOSTART 4 /**< @brief Channel started + automatically on driver start. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + EXT_UNINIT = 0, /**< Not initialized. */ + EXT_STOP = 1, /**< Stopped. */ + EXT_ACTIVE = 2, /**< Active. */ +} extstate_t; + +/** + * @brief Type of a structure representing a EXT driver. + */ +typedef struct EXTDriver EXTDriver; + +#include "ext_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @iclass + */ +#define extChannelEnableI(extp, channel) ext_lld_channel_enable(extp, channel) + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @iclass + */ +#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) + +/** + * @brief Changes the operation mode of a channel. + * @note This function attempts to write over the current configuration + * structure that must have been not declared constant. This + * violates the @p const qualifier in @p extStart() but it is + * intentional. This function cannot be used if the configuration + * structure is declared @p const. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be changed + * @param[in] extcp new configuration for the channel + * + * @api + */ +#define extSetChannelMode(extp, channel, extcp) { \ + chSysLock(); \ + extSetChannelModeI(extp, channel, extcp); \ + chSysUnlock(); \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void extInit(void); + void extObjectInit(EXTDriver *extp); + void extStart(EXTDriver *extp, const EXTConfig *config); + void extStop(EXTDriver *extp); + void extChannelEnable(EXTDriver *extp, expchannel_t channel); + void extChannelDisable(EXTDriver *extp, expchannel_t channel); + void extSetChannelModeI(EXTDriver *extp, + expchannel_t channel, + const EXTChannelConfig *extcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_H_ */ + +/** @} */ diff --git a/os/hal/include/gpt.h b/os/hal/include/gpt.h new file mode 100644 index 000000000..3b474cb14 --- /dev/null +++ b/os/hal/include/gpt.h @@ -0,0 +1,123 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file gpt.h + * @brief GPT Driver macros and structures. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_H_ +#define _GPT_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + GPT_UNINIT = 0, /**< Not initialized. */ + GPT_STOP = 1, /**< Stopped. */ + GPT_READY = 2, /**< Ready. */ + GPT_CONTINUOUS = 3, /**< Active in continuous mode. */ + GPT_ONESHOT = 4 /**< Active in one shot mode. */ +} gptstate_t; + +/** + * @brief Type of a structure representing a GPT driver. + */ +typedef struct GPTDriver GPTDriver; + +/** + * @brief GPT notification callback type. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +typedef void (*gptcallback_t)(GPTDriver *gptp); + +#include "gpt_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * + * @iclass + */ +#define gptChangeIntervalI(gptp, interval) { \ + gpt_lld_change_interval(gptp, interval); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void gptInit(void); + void gptObjectInit(GPTDriver *gptp); + void gptStart(GPTDriver *gptp, const GPTConfig *config); + void gptStop(GPTDriver *gptp); + void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval); + void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval); + void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval); + void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval); + void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval); + void gptStopTimer(GPTDriver *gptp); + void gptStopTimerI(GPTDriver *gptp); + void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_H_ */ + +/** @} */ diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h new file mode 100644 index 000000000..8bf648a8c --- /dev/null +++ b/os/hal/include/hal.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file hal.h + * @brief HAL subsystem header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_H_ +#define _HAL_H_ + +#include "ch.h" +#include "board.h" +#include "halconf.h" + +#include "hal_lld.h" + +/* Abstract interfaces.*/ +#include "io_channel.h" +#include "io_block.h" + +/* Shared headers.*/ +#include "mmcsd.h" + +/* Layered drivers.*/ +#include "tm.h" +#include "pal.h" +#include "adc.h" +#include "can.h" +#include "ext.h" +#include "gpt.h" +#include "i2c.h" +#include "icu.h" +#include "mac.h" +#include "pwm.h" +#include "rtc.h" +#include "serial.h" +#include "sdc.h" +#include "spi.h" +#include "uart.h" +#include "usb.h" + +/* Complex drivers.*/ +#include "mmc_spi.h" +#include "serial_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) +/** + * @name Time conversion utilities for the realtime counter + * @{ + */ +/** + * @brief Seconds to realtime ticks. + * @details Converts from seconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] sec number of seconds + * @return The number of ticks. + * + * @api + */ +#define S2RTT(sec) (halGetCounterFrequency() * (sec)) + +/** + * @brief Milliseconds to realtime ticks. + * @details Converts from milliseconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] msec number of milliseconds + * @return The number of ticks. + * + * @api + */ +#define MS2RTT(msec) (((halGetCounterFrequency() + 999UL) / 1000UL) * (msec)) + +/** + * @brief Microseconds to realtime ticks. + * @details Converts from microseconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] usec number of microseconds + * @return The number of ticks. + * + * @api + */ +#define US2RTT(usec) (((halGetCounterFrequency() + 999999UL) / 1000000UL) * \ + (usec)) + +/** + * @brief Realtime ticks to seconds to. + * @details Converts from realtime ticks number to seconds. + * + * @param[in] ticks number of ticks + * @return The number of seconds. + * + * @api + */ +#define RTT2S(ticks) ((ticks) / halGetCounterFrequency()) + +/** + * @brief Realtime ticks to milliseconds. + * @details Converts from realtime ticks number to milliseconds. + * + * @param[in] ticks number of ticks + * @return The number of milliseconds. + * + * @api + */ +#define RTT2MS(ticks) ((ticks) / (halGetCounterFrequency() / 1000UL)) + +/** + * @brief Realtime ticks to microseconds. + * @details Converts from realtime ticks number to microseconds. + * + * @param[in] ticks number of ticks + * @return The number of microseconds. + * + * @api + */ +#define RTT2US(ticks) ((ticks) / (halGetCounterFrequency() / 1000000UL)) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the current value of the system free running counter. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @special + */ +#define halGetCounterValue() hal_lld_get_counter_value() + +/** + * @brief Realtime counter frequency. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @return The realtime counter frequency of type halclock_t. + * + * @special + */ +#define halGetCounterFrequency() hal_lld_get_counter_frequency() +/** @} */ +#endif /* HAL_IMPLEMENTS_COUNTERS */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void halInit(void); +#if HAL_IMPLEMENTS_COUNTERS + bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end); + void halPolledDelay(halrtcnt_t ticks); +#endif /* HAL_IMPLEMENTS_COUNTERS */ +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_H_ */ + +/** @} */ diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h new file mode 100644 index 000000000..2e45450ee --- /dev/null +++ b/os/hal/include/i2c.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file i2c.h + * @brief I2C Driver macros and structures. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name I2C bus error conditions + * @{ + */ +#define I2CD_NO_ERROR 0x00 /**< @brief No error. */ +#define I2CD_BUS_ERROR 0x01 /**< @brief Bus Error. */ +#define I2CD_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost. */ +#define I2CD_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */ +#define I2CD_OVERRUN 0x08 /**< @brief Overrun/Underrun. */ +#define I2CD_PEC_ERROR 0x10 /**< @brief PEC Error in + reception. */ +#define I2CD_TIMEOUT 0x20 /**< @brief Hardware timeout. */ +#define I2CD_SMB_ALERT 0x40 /**< @brief SMBus Alert. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + I2C_UNINIT = 0, /**< Not initialized. */ + I2C_STOP = 1, /**< Stopped. */ + I2C_READY = 2, /**< Ready. */ + I2C_ACTIVE_TX = 3, /**< Transmitting. */ + I2C_ACTIVE_RX = 4, /**< Receiving. */ + I2C_LOCKED = 5 /**> Bus or driver locked. */ +} i2cstate_t; + +#include "i2c_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout. + * @api + */ +#define i2cMasterTransmit(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes) \ + (i2cMasterTransmitTimeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, \ + TIME_INFINITE)) + +/** + * @brief Wrap i2cMasterReceiveTimeout function with TIME_INFINITE timeout. + * @api + */ +#define i2cMasterReceive(i2cp, addr, rxbuf, rxbytes) \ + (i2cMasterReceiveTimeout(i2cp, addr, rxbuf, rxbytes, TIME_INFINITE)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void i2cInit(void); + void i2cObjectInit(I2CDriver *i2cp); + void i2cStart(I2CDriver *i2cp, const I2CConfig *config); + void i2cStop(I2CDriver *i2cp); + i2cflags_t i2cGetErrors(I2CDriver *i2cp); + msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, + i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, + i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#if I2C_USE_MUTUAL_EXCLUSION + void i2cAcquireBus(I2CDriver *i2cp); + void i2cReleaseBus(I2CDriver *i2cp); +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_H_ */ + +/** @} */ diff --git a/os/hal/include/i2s.h b/os/hal/include/i2s.h new file mode 100644 index 000000000..b2dacbb49 --- /dev/null +++ b/os/hal/include/i2s.h @@ -0,0 +1,148 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file i2s.h + * @brief I2S Driver macros and structures. + * + * @addtogroup I2S + * @{ + */ + +#ifndef _I2S_H_ +#define _I2S_H_ + +#if HAL_USE_I2S || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name I2S modes + * @{ + */ +#define I2S_MODE_SLAVE 0 +#define I2S_MODE_MASTER 1 +#define I2S_MODE_TX 2 +#define I2S_MODE_RX 4 +#define I2S_MODE_TXRX (I2S_MODE_TX | I2S_MODE_RX) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + I2S_UNINIT = 0, /**< Not initialized. */ + I2S_STOP = 1, /**< Stopped. */ + I2S_READY = 2, /**< Ready. */ + I2S_ACTIVE = 3, /**< Active. */ + I2S_COMPLETE = 4 /**< Transmission complete. */ +} i2sstate_t; + +/** + * @brief Type of a structure representing a I2S driver. + */ +typedef struct I2SDriver I2SDriver; + +#include "i2s_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Starts a I2S data exchange. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @iclass + */ +#define i2sStartExchangeI(i2sp) { \ + i2s_lld_start_exchange(i2sp); \ + (i2sp)->state = I2S_ACTIVE; \ +} + +/** + * @brief Starts a I2S data exchange in continuous mode. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @iclass + */ +#define i2sStartExchangeContinuousI(i2sp) { \ + i2s_lld_start_exchange_continuous(i2sp); \ + (i2sp)->state = I2S_ACTIVE; \ +} + +/** + * @brief Stops the ongoing data exchange. + * @details The ongoing data exchange, if any, is stopped, if the driver + * was not active the function does nothing. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @iclass + */ +#define i2sStopExchangeI(i2sp) { \ + i2s_lld_stop_exchange(i2sp); \ + (i2sp)->state = I2S_READY; \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void i2sInit(void); + void i2sObjectInit(I2SDriver *i2sp); + void i2sStart(I2SDriver *i2sp, const I2SConfig *config); + void i2sStop(I2SDriver *i2sp); + void i2sStartExchange(I2SDriver *i2sp); + void i2sStopExchange(I2SDriver *i2sp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2S */ + +#endif /* _I2S_H_ */ + +/** @} */ diff --git a/os/hal/include/icu.h b/os/hal/include/icu.h new file mode 100644 index 000000000..ef42470cb --- /dev/null +++ b/os/hal/include/icu.h @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file icu.h + * @brief ICU Driver macros and structures. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_H_ +#define _ICU_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ICU_UNINIT = 0, /**< Not initialized. */ + ICU_STOP = 1, /**< Stopped. */ + ICU_READY = 2, /**< Ready. */ + ICU_WAITING = 3, /**< Waiting first edge. */ + ICU_ACTIVE = 4, /**< Active cycle phase. */ + ICU_IDLE = 5, /**< Idle cycle phase. */ +} icustate_t; + +/** + * @brief Type of a structure representing an ICU driver. + */ +typedef struct ICUDriver ICUDriver; + +/** + * @brief ICU notification callback type. + * + * @param[in] icup pointer to a @p ICUDriver object + */ +typedef void (*icucallback_t)(ICUDriver *icup); + +#include "icu_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @iclass + */ +#define icuEnableI(icup) icu_lld_enable(icup) + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @iclass + */ +#define icuDisableI(icup) icu_lld_disable(icup) + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * @note This function is meant to be invoked from the width capture + * callback only. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @special + */ +#define icuGetWidth(icup) icu_lld_get_width(icup) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * @note This function is meant to be invoked from the width capture + * callback only. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @special + */ +#define icuGetPeriod(icup) icu_lld_get_period(icup) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +/** + * @brief Common ISR code, ICU width event. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +#define _icu_isr_invoke_width_cb(icup) { \ + (icup)->state = ICU_IDLE; \ + (icup)->config->width_cb(icup); \ +} + +/** + * @brief Common ISR code, ICU period event. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +#define _icu_isr_invoke_period_cb(icup) { \ + icustate_t previous_state = (icup)->state; \ + (icup)->state = ICU_ACTIVE; \ + if (previous_state != ICU_WAITING) \ + (icup)->config->period_cb(icup); \ +} + +/** + * @brief Common ISR code, ICU timer overflow event. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +#define _icu_isr_invoke_overflow_cb(icup) { \ + (icup)->config->overflow_cb(icup); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void icuInit(void); + void icuObjectInit(ICUDriver *icup); + void icuStart(ICUDriver *icup, const ICUConfig *config); + void icuStop(ICUDriver *icup); + void icuEnable(ICUDriver *icup); + void icuDisable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_H_ */ + +/** @} */ diff --git a/os/hal/include/io_block.h b/os/hal/include/io_block.h new file mode 100644 index 000000000..7a2970f9f --- /dev/null +++ b/os/hal/include/io_block.h @@ -0,0 +1,269 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file io_block.h + * @brief I/O block devices access. + * @details This header defines an abstract interface useful to access generic + * I/O block devices in a standardized way. + * + * @addtogroup IO_BLOCK + * @details This module defines an abstract interface for accessing generic + * block devices.
    + * Note that no code is present, just abstract interfaces-like + * structures, you should look at the system as to a set of + * abstract C++ classes (even if written in C). This system + * has then advantage to make the access to block devices + * independent from the implementation logic. + * @{ + */ + +#ifndef _IO_BLOCK_H_ +#define _IO_BLOCK_H_ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + BLK_UNINIT = 0, /**< Not initialized. */ + BLK_STOP = 1, /**< Stopped. */ + BLK_ACTIVE = 2, /**< Interface active. */ + BLK_CONNECTING = 3, /**< Connection in progress. */ + BLK_DISCONNECTING = 4, /**< Disconnection in progress. */ + BLK_READY = 5, /**< Device ready. */ + BLK_READING = 6, /**< Read operation in progress. */ + BLK_WRITING = 7, /**< Write operation in progress. */ + BLK_SYNCING = 8 /**< Sync. operation in progress. */ +} blkstate_t; + +/** + * @brief Block device info. + */ +typedef struct { + uint32_t blk_size; /**< @brief Block size in bytes. */ + uint32_t blk_num; /**< @brief Total number of blocks. */ +} BlockDeviceInfo; + +/** + * @brief @p BaseBlockDevice specific methods. + */ +#define _base_block_device_methods \ + /* Removable media detection.*/ \ + bool_t (*is_inserted)(void *instance); \ + /* Removable write protection detection.*/ \ + bool_t (*is_protected)(void *instance); \ + /* Connection to the block device.*/ \ + bool_t (*connect)(void *instance); \ + /* Disconnection from the block device.*/ \ + bool_t (*disconnect)(void *instance); \ + /* Reads one or more blocks.*/ \ + bool_t (*read)(void *instance, uint32_t startblk, \ + uint8_t *buffer, uint32_t n); \ + /* Writes one or more blocks.*/ \ + bool_t (*write)(void *instance, uint32_t startblk, \ + const uint8_t *buffer, uint32_t n); \ + /* Write operations synchronization.*/ \ + bool_t (*sync)(void *instance); \ + /* Obtains info about the media.*/ \ + bool_t (*get_info)(void *instance, BlockDeviceInfo *bdip); + +/** + * @brief @p BaseBlockDevice specific data. + */ +#define _base_block_device_data \ + /* Driver state.*/ \ + blkstate_t state; + +/** + * @brief @p BaseBlockDevice virtual methods table. + */ +struct BaseBlockDeviceVMT { + _base_block_device_methods +}; + +/** + * @brief Base block device class. + * @details This class represents a generic, block-accessible, device. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseBlockDeviceVMT *vmt; + _base_block_device_data +} BaseBlockDevice; + +/** + * @name Macro Functions (BaseBlockDevice) + * @{ + */ +/** + * @brief Returns the driver state. + * @note Can be called in ISR context. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The driver state. + * + * @special + */ +#define blkGetDriverState(ip) ((ip)->state) + +/** + * @brief Determines if the device is transferring data. + * @note Can be called in ISR context. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The driver state. + * @retval FALSE the device is not transferring data. + * @retval TRUE the device not transferring data. + * + * @special + */ +#define blkIsTransferring(ip) ((((ip)->state) == BLK_CONNECTING) || \ + (((ip)->state) == BLK_DISCONNECTING) || \ + (((ip)->state) == BLK_READING) || \ + (((ip)->state) == BLK_WRITING)) + +/** + * @brief Returns the media insertion status. + * @note On some implementations this function can only be called if the + * device is not transferring data. + * The function @p blkIsTransferring() should be used before calling + * this function. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The media state. + * @retval FALSE media not inserted. + * @retval TRUE media inserted. + * + * @api + */ +#define blkIsInserted(ip) ((ip)->vmt->is_inserted(ip)) + +/** + * @brief Returns the media write protection status. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The media state. + * @retval FALSE writable media. + * @retval TRUE non writable media. + * + * @api + */ +#define blkIsWriteProtected(ip) ((ip)->vmt->is_protected(ip)) + +/** + * @brief Performs the initialization procedure on the block device. + * @details This function should be performed before I/O operations can be + * attempted on the block device and after insertion has been + * confirmed using @p blkIsInserted(). + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkConnect(ip) ((ip)->vmt->connect(ip)) + +/** + * @brief Terminates operations on the block device. + * @details This operation safely terminates operations on the block device. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkDisconnect(ip) ((ip)->vmt->disconnect(ip)) + +/** + * @brief Reads one or more blocks. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkRead(ip, startblk, buf, n) \ + ((ip)->vmt->read(ip, startblk, buf, n)) + +/** + * @brief Writes one or more blocks. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkWrite(ip, startblk, buf, n) \ + ((ip)->vmt->write(ip, startblk, buf, n)) + +/** + * @brief Ensures write synchronization. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkSync(ip) ((ip)->vmt->sync(ip)) + +/** + * @brief Returns a media information structure. + * + * @param[in] ip pointer to a @p BaseBlockDevice or derived class + * @param[out] bdip pointer to a @p BlockDeviceInfo structure + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +#define blkGetInfo(ip, bdip) ((ip)->vmt->get_info(ip, bdip)) + +/** @} */ + +#endif /* _IO_BLOCK_H_ */ + +/** @} */ diff --git a/os/hal/include/io_channel.h b/os/hal/include/io_channel.h new file mode 100644 index 000000000..af90b431e --- /dev/null +++ b/os/hal/include/io_channel.h @@ -0,0 +1,294 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file io_channel.h + * @brief I/O channels access. + * @details This header defines an abstract interface useful to access generic + * I/O serial devices in a standardized way. + * + * @addtogroup IO_CHANNEL + * @details This module defines an abstract interface for I/O channels by + * extending the @p BaseSequentialStream interface.
    + * Note that no code is present, I/O channels are just abstract + * interface like structures, you should look at the systems as + * to a set of abstract C++ classes (even if written in C). + * Specific device drivers can use/extend the interface and + * implement them.
    + * This system has the advantage to make the access to channels + * independent from the implementation logic. + * @{ + */ + +#ifndef _IO_CHANNEL_H_ +#define _IO_CHANNEL_H_ + +/** + * @brief @p BaseChannel specific methods. + */ +#define _base_channel_methods \ + _base_sequential_stream_methods \ + /* Channel put method with timeout specification.*/ \ + msg_t (*putt)(void *instance, uint8_t b, systime_t time); \ + /* Channel get method with timeout specification.*/ \ + msg_t (*gett)(void *instance, systime_t time); \ + /* Channel write method with timeout specification.*/ \ + size_t (*writet)(void *instance, const uint8_t *bp, \ + size_t n, systime_t time); \ + /* Channel read method with timeout specification.*/ \ + size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time); + +/** + * @brief @p BaseChannel specific data. + * @note It is empty because @p BaseChannel is only an interface without + * implementation. + */ +#define _base_channel_data \ + _base_sequential_stream_data + +/** + * @extends BaseSequentialStreamVMT + * + * @brief @p BaseChannel virtual methods table. + */ +struct BaseChannelVMT { + _base_channel_methods +}; + +/** + * @extends BaseSequentialStream + * + * @brief Base channel class. + * @details This class represents a generic, byte-wide, I/O channel. This class + * introduces generic I/O primitives with timeout specification. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseChannelVMT *vmt; + _base_channel_data +} BaseChannel; + +/** + * @name Macro Functions (BaseChannel) + * @{ + */ +/** + * @brief Channel blocking byte write with timeout. + * @details This function writes a byte value to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] b the byte value to be written to the channel + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the channel associated queue (if any) was reset. + * + * @api + */ +#define chnPutTimeout(ip, b, time) ((ip)->vmt->putt(ip, b, time)) + +/** + * @brief Channel blocking byte read with timeout. + * @details This function reads a byte value from a channel. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A byte value from the queue. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the channel associated queue (if any) has been + * reset. + * + * @api + */ +#define chnGetTimeout(ip, time) ((ip)->vmt->gett(ip, time)) + +/** + * @brief Channel blocking write. + * @details The function writes data from a buffer to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * + * @return The number of bytes transferred. + * + * @api + */ +#define chnWrite(ip, bp, n) chSequentialStreamWrite(ip, bp, n) + +/** + * @brief Channel blocking write with timeout. + * @details The function writes data from a buffer to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes transferred. + * + * @api + */ +#define chnWriteTimeout(ip, bp, n, time) ((ip)->vmt->writet(ip, bp, n, time)) + +/** + * @brief Channel blocking read. + * @details The function reads data from a channel into a buffer. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * + * @return The number of bytes transferred. + * + * @api + */ +#define chnRead(ip, bp, n) chSequentialStreamRead(ip, bp, n) + +/** + * @brief Channel blocking read with timeout. + * @details The function reads data from a channel into a buffer. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes transferred. + * + * @api + */ +#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time)) +/** @} */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) +/** + * @name I/O status flags added to the event listener + * @{ + */ +/** @brief No pending conditions.*/ +#define CHN_NO_ERROR 0 +/** @brief Connection happened.*/ +#define CHN_CONNECTED 1 +/** @brief Disconnection happened.*/ +#define CHN_DISCONNECTED 2 +/** @brief Data available in the input queue.*/ +#define CHN_INPUT_AVAILABLE 4 +/** @brief Output queue empty.*/ +#define CHN_OUTPUT_EMPTY 8 +/** @brief Transmission end.*/ +#define CHN_TRANSMISSION_END 16 +/** @} */ + +/** + * @brief @p BaseAsynchronousChannel specific methods. + */ +#define _base_asynchronous_channel_methods \ + _base_channel_methods \ + +/** + * @brief @p BaseAsynchronousChannel specific data. + */ +#define _base_asynchronous_channel_data \ + _base_channel_data \ + /* I/O condition event source.*/ \ + EventSource event; + +/** + * @extends BaseChannelVMT + * + * @brief @p BaseAsynchronousChannel virtual methods table. + */ +struct BaseAsynchronousChannelVMT { + _base_asynchronous_channel_methods +}; + +/** + * @extends BaseChannel + * + * @brief Base asynchronous channel class. + * @details This class extends @p BaseChannel by adding event sources fields + * for asynchronous I/O for use in an event-driven environment. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseAsynchronousChannelVMT *vmt; + _base_asynchronous_channel_data +} BaseAsynchronousChannel; + +/** + * @name Macro Functions (BaseAsynchronousChannel) + * @{ + */ +/** + * @brief Returns the I/O condition event source. + * @details The event source is broadcasted when an I/O condition happens. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @return A pointer to an @p EventSource object. + * + * @api + */ +#define chnGetEventSource(ip) (&((ip)->event)) + +/** + * @brief Adds status flags to the listeners's flags mask. + * @details This function is usually called from the I/O ISRs in order to + * notify I/O conditions such as data events, errors, signal + * changes etc. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @param[in] flags condition flags to be added to the listener flags mask + * + * @iclass + */ +#define chnAddFlagsI(ip, flags) { \ + chEvtBroadcastFlagsI(&(ip)->event, flags); \ +} +/** @} */ + +#endif /* CH_USE_EVENTS */ + +#endif /* _IO_CHANNEL_H_ */ + +/** @} */ diff --git a/os/hal/include/mac.h b/os/hal/include/mac.h new file mode 100644 index 000000000..868460ad5 --- /dev/null +++ b/os/hal/include/mac.h @@ -0,0 +1,214 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file mac.h + * @brief MAC Driver macros and structures. + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_H_ +#define _MAC_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name MAC configuration options + * @{ + */ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS +#error "the MAC driver requires CH_USE_SEMAPHORES" +#endif + +#if MAC_USE_EVENTS && !CH_USE_EVENTS +#error "the MAC driver requires CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + MAC_UNINIT = 0, /**< Not initialized. */ + MAC_STOP = 1, /**< Stopped. */ + MAC_ACTIVE = 2 /**< Active. */ +} macstate_t; + +/** + * @brief Type of a structure representing a MAC driver. + */ +typedef struct MACDriver MACDriver; + +#include "mac_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the received frames event source. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The pointer to the @p EventSource structure. + * + * @api + */ +#if MAC_USE_EVENTS || defined(__DOXYGEN__) +#define macGetReceiveEventSource(macp) (&(macp)->rdevent) +#endif + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum frame + * size is reached. + * + * @api + */ +#define macWriteTransmitDescriptor(tdp, buf, size) \ + mac_lld_write_transmit_descriptor(tdp, buf, size) + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's stream, + * this value can be less than the amount specified in the + * parameter @p size if there are no more bytes to read. + * + * @api + */ +#define macReadReceiveDescriptor(rdp, buf, size) \ + mac_lld_read_receive_descriptor(rdp, buf, size) + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the real buffer size. + * The returned value can be less than the amount + * requested, this means that more buffers must be + * requested in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * + * @api + */ +#define macGetNextTransmitBuffer(tdp, size, sizep) \ + mac_lld_get_next_transmit_buffer(tdp, size, sizep) + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @api + */ +#define macGetNextReceiveBuffer(rdp, sizep) \ + mac_lld_get_next_receive_buffer(rdp, sizep) +#endif /* MAC_USE_ZERO_COPY */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void macInit(void); + void macObjectInit(MACDriver *macp); + void macStart(MACDriver *macp, const MACConfig *config); + void macStop(MACDriver *macp); + void macSetAddress(MACDriver *macp, const uint8_t *p); + msg_t macWaitTransmitDescriptor(MACDriver *macp, + MACTransmitDescriptor *tdp, + systime_t time); + void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp); + msg_t macWaitReceiveDescriptor(MACDriver *macp, + MACReceiveDescriptor *rdp, + systime_t time); + void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp); + bool_t macPollLinkStatus(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_H_ */ + +/** @} */ diff --git a/os/hal/include/mii.h b/os/hal/include/mii.h new file mode 100644 index 000000000..4c9e7a03a --- /dev/null +++ b/os/hal/include/mii.h @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/*-* + * @file mii.h + * @brief MII Driver macros and structures. + * + * @addtogroup MII + * @{ + */ + +#ifndef _MII_H_ +#define _MII_H_ + +/* + * Generic MII registers. Note, not all registers are present on all PHY + * devices and some extra registers may be present. + */ +#define MII_BMCR 0x00 /**< Basic mode control register. */ +#define MII_BMSR 0x01 /**< Basic mode status register. */ +#define MII_PHYSID1 0x02 /**< PHYS ID 1. */ +#define MII_PHYSID2 0x03 /**< PHYS ID 2. */ +#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ +#define MII_LPA 0x05 /**< Link partner ability reg. */ +#define MII_EXPANSION 0x06 /**< Expansion register. */ +#define MII_ANNPTR 0x07 /**< 1000BASE-T control. */ +#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ +#define MII_STAT1000 0x0a /**< 1000BASE-T status. */ +#define MII_ESTATUS 0x0f /**< Extended Status. */ +#define MII_PHYSTS 0x10 /**< PHY Status register. */ +#define MII_MICR 0x11 /**< MII Interrupt ctrl register. */ +#define MII_DCOUNTER 0x12 /**< Disconnect counter. */ +#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ +#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ +#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ +#define MII_SREVISION 0x16 /**< Silicon revision. */ +#define MII_RESV1 0x17 /**< Reserved. */ +#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ +#define MII_PHYADDR 0x19 /**< PHY address. */ +#define MII_RESV2 0x1a /**< Reserved. */ +#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */ +#define MII_NCONFIG 0x1c /**< Network interface config. */ + +/* + * Basic mode control register. + */ +#define BMCR_RESV 0x007f /**< Unused. */ +#define BMCR_CTST 0x0080 /**< Collision test. */ +#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ +#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ +#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ +#define BMCR_PDOWN 0x0800 /**< Powerdown. */ +#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ +#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ +#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */ +#define BMCR_RESET 0x8000 /**< Reset. */ + +/* + * Basic mode status register. + */ +#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ +#define BMSR_JCD 0x0002 /**< Jabber detected. */ +#define BMSR_LSTATUS 0x0004 /**< Link status. */ +#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ +#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ +#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ +#define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */ +#define BMSR_RESV 0x0780 /**< Unused. */ +#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ +#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ +#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ +#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ +#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ + +/* + * Advertisement control register. + */ +#define ADVERTISE_SLCT 0x001f /**< Selector bits. */ +#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ +#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ +#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ +#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ +#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ +#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ +#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ +#define ADVERTISE_RESV 0x1000 /**< Unused. */ +#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ +#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ +#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* + * Link partner ability register. + */ +#define LPA_SLCT 0x001f /**< Same as advertise selector. */ +#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ +#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ +#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ +#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ +#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ +#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ +#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ +#define LPA_RESV 0x1000 /**< Unused. */ +#define LPA_RFAULT 0x2000 /**< Link partner faulted. */ +#define LPA_LPACK 0x4000 /**< Link partner acked us. */ +#define LPA_NPAGE 0x8000 /**< Next page bit. */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* + * Expansion register for auto-negotiation. + */ +#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ +#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ +#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ +#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ +#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ +#define EXPANSION_RESV 0xffe0 /**< Unused. */ + +/* + * N-way test register. + */ +#define NWAYTEST_RESV1 0x00ff /**< Unused. */ +#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ +#define NWAYTEST_RESV2 0xfe00 /**< Unused. */ + +/* + * PHY identifiers. + */ +#define MII_DM9161_ID 0x0181b8a0 +#define MII_AM79C875_ID 0x00225540 +#define MII_KS8721_ID 0x00221610 +#define MII_STE101P_ID 0x00061C50 +#define MII_DP83848I_ID 0x20005C90 + +#endif /* _MII_H_ */ + +/** @} */ diff --git a/os/hal/include/mmc_spi.h b/os/hal/include/mmc_spi.h new file mode 100644 index 000000000..5732570b6 --- /dev/null +++ b/os/hal/include/mmc_spi.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file mmc_spi.h + * @brief MMC over SPI driver header. + * + * @addtogroup MMC_SPI + * @{ + */ + +#ifndef _MMC_SPI_H_ +#define _MMC_SPI_H_ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define MMC_CMD0_RETRY 10 +#define MMC_CMD1_RETRY 100 +#define MMC_ACMD41_RETRY 100 +#define MMC_WAIT_DATA 10000 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name MMC_SPI configuration options + * @{ + */ +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_SPI || !SPI_USE_WAIT || !CH_USE_EVENTS +#error "MMC_SPI driver requires HAL_USE_SPI, SPI_USE_WAIT and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief MMC/SD over SPI driver configuration structure. + */ +typedef struct { + /** + * @brief SPI driver associated to this MMC driver. + */ + SPIDriver *spip; + /** + * @brief SPI low speed configuration used during initialization. + */ + const SPIConfig *lscfg; + /** + * @brief SPI high speed configuration used during transfers. + */ + const SPIConfig *hscfg; +} MMCConfig; + +/** + * @brief @p MMCDriver specific methods. + */ +#define _mmc_driver_methods \ + _mmcsd_block_device_methods + +/** + * @extends MMCSDBlockDeviceVMT + * + * @brief @p MMCDriver virtual methods table. + */ +struct MMCDriverVMT { + _mmc_driver_methods +}; + +/** + * @extends MMCSDBlockDevice + * + * @brief Structure representing a MMC/SD over SPI driver. + */ +typedef struct { + /** + * @brief Virtual Methods Table. + */ + const struct MMCDriverVMT *vmt; + _mmcsd_block_device_data + /** + * @brief Current configuration data. + */ + const MMCConfig *config; + /*** + * @brief Addresses use blocks instead of bytes. + */ + bool_t block_addresses; +} MMCDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the card insertion status. + * @note This macro wraps a low level function named + * @p sdc_lld_is_card_inserted(), this function must be + * provided by the application because it is not part of the + * SDC driver. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define mmcIsCardInserted(mmcp) mmc_lld_is_card_inserted(mmcp) + +/** + * @brief Returns the write protect status. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define mmcIsWriteProtected(mmcp) mmc_lld_is_write_protected(mmcp) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void mmcInit(void); + void mmcObjectInit(MMCDriver *mmcp); + void mmcStart(MMCDriver *mmcp, const MMCConfig *config); + void mmcStop(MMCDriver *mmcp); + bool_t mmcConnect(MMCDriver *mmcp); + bool_t mmcDisconnect(MMCDriver *mmcp); + bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk); + bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer); + bool_t mmcStopSequentialRead(MMCDriver *mmcp); + bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk); + bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer); + bool_t mmcStopSequentialWrite(MMCDriver *mmcp); + bool_t mmcSync(MMCDriver *mmcp); + bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip); + bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk); + bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp); + bool_t mmc_lld_is_write_protected(MMCDriver *mmcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MMC_SPI */ + +#endif /* _MMC_SPI_H_ */ + +/** @} */ diff --git a/os/hal/include/mmcsd.h b/os/hal/include/mmcsd.h new file mode 100644 index 000000000..5ff3082c7 --- /dev/null +++ b/os/hal/include/mmcsd.h @@ -0,0 +1,279 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file mmcsd.h + * @brief MMC/SD cards common header. + * @details This header defines an abstract interface useful to access MMC/SD + * I/O block devices in a standardized way. + * + * @addtogroup MMCSD + * @{ + */ + +#ifndef _MMCSD_H_ +#define _MMCSD_H_ + +#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Fixed block size for MMC/SD block devices. + */ +#define MMCSD_BLOCK_SIZE 512 + +/** + * @brief Mask of error bits in R1 responses. + */ +#define MMCSD_R1_ERROR_MASK 0xFDFFE008 + +/** + * @brief Fixed pattern for CMD8. + */ +#define MMCSD_CMD8_PATTERN 0x000001AA + +/** + * @name SD/MMC status conditions + * @{ + */ +#define MMCSD_STS_IDLE 0 +#define MMCSD_STS_READY 1 +#define MMCSD_STS_IDENT 2 +#define MMCSD_STS_STBY 3 +#define MMCSD_STS_TRAN 4 +#define MMCSD_STS_DATA 5 +#define MMCSD_STS_RCV 6 +#define MMCSD_STS_PRG 7 +#define MMCSD_STS_DIS 8 +/** @} */ + +/** + * @name SD/MMC commands + * @{ + */ +#define MMCSD_CMD_GO_IDLE_STATE 0 +#define MMCSD_CMD_INIT 1 +#define MMCSD_CMD_ALL_SEND_CID 2 +#define MMCSD_CMD_SEND_RELATIVE_ADDR 3 +#define MMCSD_CMD_SET_BUS_WIDTH 6 +#define MMCSD_CMD_SEL_DESEL_CARD 7 +#define MMCSD_CMD_SEND_IF_COND 8 +#define MMCSD_CMD_SEND_CSD 9 +#define MMCSD_CMD_SEND_CID 10 +#define MMCSD_CMD_STOP_TRANSMISSION 12 +#define MMCSD_CMD_SEND_STATUS 13 +#define MMCSD_CMD_SET_BLOCKLEN 16 +#define MMCSD_CMD_READ_SINGLE_BLOCK 17 +#define MMCSD_CMD_READ_MULTIPLE_BLOCK 18 +#define MMCSD_CMD_SET_BLOCK_COUNT 23 +#define MMCSD_CMD_WRITE_BLOCK 24 +#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMCSD_CMD_ERASE_RW_BLK_START 32 +#define MMCSD_CMD_ERASE_RW_BLK_END 33 +#define MMCSD_CMD_ERASE 38 +#define MMCSD_CMD_APP_OP_COND 41 +#define MMCSD_CMD_LOCK_UNLOCK 42 +#define MMCSD_CMD_APP_CMD 55 +#define MMCSD_CMD_READ_OCR 58 +/** @} */ + +/** + * @name CSD record offsets + */ +/** + * @brief Slice position of values in CSD register. + */ +/* CSD version 2.0 */ +#define MMCSD_CSD_20_CRC_SLICE 7,1 +#define MMCSD_CSD_20_FILE_FORMAT_SLICE 11,10 +#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE 12,12 +#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE 13,13 +#define MMCSD_CSD_20_COPY_SLICE 14,14 +#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE 15,15 +#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE 21,21 +#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE 25,12 +#define MMCSD_CSD_20_R2W_FACTOR_SLICE 28,26 +#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE 31,31 +#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE 38,32 +#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE 45,39 +#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE 46,46 +#define MMCSD_CSD_20_C_SIZE_SLICE 69,48 +#define MMCSD_CSD_20_DSR_IMP_SLICE 76,76 +#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE 77,77 +#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE 78,78 +#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE 79,79 +#define MMCSD_CSD_20_READ_BL_LEN_SLICE 83,80 +#define MMCSD_CSD_20_CCC_SLICE 95,84 +#define MMCSD_CSD_20_TRANS_SPEED_SLICE 103,96 +#define MMCSD_CSD_20_NSAC_SLICE 111,104 +#define MMCSD_CSD_20_TAAC_SLICE 119,112 +#define MMCSD_CSD_20_STRUCTURE_SLICE 127,126 + +/* CSD version 1.0 */ +#define MMCSD_CSD_10_CRC_SLICE MMCSD_CSD_20_CRC_SLICE +#define MMCSD_CSD_10_FILE_FORMAT_SLICE MMCSD_CSD_20_FILE_FORMAT_SLICE +#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE +#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE +#define MMCSD_CSD_10_COPY_SLICE MMCSD_CSD_20_COPY_SLICE +#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE +#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE +#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE MMCSD_CSD_20_WRITE_BL_LEN_SLICE +#define MMCSD_CSD_10_R2W_FACTOR_SLICE MMCSD_CSD_20_R2W_FACTOR_SLICE +#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE MMCSD_CSD_20_WP_GRP_ENABLE_SLICE +#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE MMCSD_CSD_20_WP_GRP_SIZE_SLICE +#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE +#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE MMCSD_CSD_20_ERASE_BLK_EN_SLICE +#define MMCSD_CSD_10_C_SIZE_MULT_SLICE 49,47 +#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE 52,50 +#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE 55,53 +#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE 58,56 +#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE 61,59 +#define MMCSD_CSD_10_C_SIZE_SLICE 73,62 +#define MMCSD_CSD_10_DSR_IMP_SLICE MMCSD_CSD_20_DSR_IMP_SLICE +#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE +#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE +#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE MMCSD_CSD_20_READ_BL_PARTIAL_SLICE +#define MMCSD_CSD_10_READ_BL_LEN_SLICE 83, 80 +#define MMCSD_CSD_10_CCC_SLICE MMCSD_CSD_20_CCC_SLICE +#define MMCSD_CSD_10_TRANS_SPEED_SLICE MMCSD_CSD_20_TRANS_SPEED_SLICE +#define MMCSD_CSD_10_NSAC_SLICE MMCSD_CSD_20_NSAC_SLICE +#define MMCSD_CSD_10_TAAC_SLICE MMCSD_CSD_20_TAAC_SLICE +#define MMCSD_CSD_10_STRUCTURE_SLICE MMCSD_CSD_20_STRUCTURE_SLICE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief @p MMCSDBlockDevice specific methods. + */ +#define _mmcsd_block_device_methods \ + _base_block_device_methods + +/** + * @brief @p MMCSDBlockDevice specific data. + * @note It is empty because @p MMCSDBlockDevice is only an interface + * without implementation. + */ +#define _mmcsd_block_device_data \ + _base_block_device_data \ + /* Card CID.*/ \ + uint32_t cid[4]; \ + /* Card CSD.*/ \ + uint32_t csd[4]; \ + /* Total number of blocks in card.*/ \ + uint32_t capacity; + +/** + * @extends BaseBlockDeviceVMT + * + * @brief @p MMCSDBlockDevice virtual methods table. + */ +struct MMCSDBlockDeviceVMT { + _base_block_device_methods +}; + +/** + * @extends BaseBlockDevice + * + * @brief MCC/SD block device class. + * @details This class represents a, block-accessible, MMC/SD device. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct MMCSDBlockDeviceVMT *vmt; + _mmcsd_block_device_data +} MMCSDBlockDevice; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name R1 response utilities + * @{ + */ +/** + * @brief Evaluates to @p TRUE if the R1 response contains error flags. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0) + +/** + * @brief Returns the status field of an R1 response. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15) + +/** + * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the card capacity in blocks. + * + * @param[in] ip pointer to a @p MMCSDBlockDevice or derived class + * + * @return The card capacity. + * + * @api + */ +#define mmcsdGetCardCapacity(ip) ((ip)->capacity) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + uint32_t mmcsdGetCapacity(uint32_t csd[4]); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MMC_SPI || HAL_USE_MMC_SDC*/ + +#endif /* _MMCSD_H_ */ + +/** @} */ diff --git a/os/hal/include/pal.h b/os/hal/include/pal.h new file mode 100644 index 000000000..694da12ae --- /dev/null +++ b/os/hal/include/pal.h @@ -0,0 +1,540 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file pal.h + * @brief I/O Ports Abstraction Layer macros, types and structures. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_H_ +#define _PAL_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Pads mode constants + * @{ + */ +/** + * @brief After reset state. + * @details The state itself is not specified and is architecture dependent, + * it is guaranteed to be equal to the after-reset state. It is + * usually an input state. + */ +#define PAL_MODE_RESET 0 + +/** + * @brief Safe state for unconnected pads. + * @details The state itself is not specified and is architecture dependent, + * it may be mapped on @p PAL_MODE_INPUT_PULLUP, + * @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL for + * example. + */ +#define PAL_MODE_UNCONNECTED 1 + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT 2 + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP 3 + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN 4 + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG 5 + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL 6 + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN 7 +/** @} */ + +/** + * @name Logic level constants + * @{ + */ +/** + * @brief Logical low state. + */ +#define PAL_LOW 0 + +/** + * @brief Logical high state. + */ +#define PAL_HIGH 1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#include "pal_lld.h" + +/** + * @brief I/O bus descriptor. + * @details This structure describes a group of contiguous digital I/O lines + * that have to be handled as bus. + * @note I/O operations on a bus do not affect I/O lines on the same port but + * not belonging to the bus. + */ +typedef struct { + /** + * @brief Port identifier. + */ + ioportid_t portid; + /** + * @brief Bus mask aligned to port bit 0. + * @note The bus mask implicitly define the bus width. A logical AND is + * performed on the bus data. + */ + ioportmask_t mask; + /** + * @brief Offset, within the port, of the least significant bit of the bus. + */ + uint_fast8_t offset; +} IOBus; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Port bit helper macro. + * @details This macro calculates the mask of a bit within a port. + * + * @param[in] n bit position within the port + * @return The bit mask. + */ +#if !defined(PAL_PORT_BIT) || defined(__DOXYGEN__) +#define PAL_PORT_BIT(n) ((ioportmask_t)(1 << (n))) +#endif + +/** + * @brief Bits group mask helper. + * @details This macro calculates the mask of a bits group. + * + * @param[in] width group width + * @return The group mask. + */ +#if !defined(PAL_GROUP_MASK) || defined(__DOXYGEN__) +#define PAL_GROUP_MASK(width) ((ioportmask_t)(1 << (width)) - 1) +#endif + +/** + * @brief Data part of a static I/O bus initializer. + * @details This macro should be used when statically initializing an I/O bus + * that is part of a bigger structure. + * + * @param[in] name name of the IOBus variable + * @param[in] port I/O port descriptor + * @param[in] width bus width in bits + * @param[in] offset bus bit offset within the port + */ +#define _IOBUS_DATA(name, port, width, offset) \ + {port, PAL_GROUP_MASK(width), offset} + +/** + * @brief Static I/O bus initializer. + * + * @param[in] name name of the IOBus variable + * @param[in] port I/O port descriptor + * @param[in] width bus width in bits + * @param[in] offset bus bit offset within the port + */ +#define IOBUS_DECL(name, port, width, offset) \ + IOBus name = _IOBUS_DATA(name, port, width, offset) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief PAL subsystem initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @param[in] config pointer to an architecture specific configuration + * structure. This structure is defined in the low level driver + * header. + * + * @init + */ +#define palInit(config) pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @note The default implementation always return zero and computes the + * parameter eventual side effects. + * + * @param[in] port port identifier + * @return The port logical states. + * + * @api + */ +#if !defined(pal_lld_readport) || defined(__DOXYGEN__) +#define palReadPort(port) ((void)(port), 0) +#else +#define palReadPort(port) pal_lld_readport(port) +#endif + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * @note The default implementation always return zero and computes the + * parameter eventual side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @api + */ +#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__) +#define palReadLatch(port) ((void)(port), 0) +#else +#define palReadLatch(port) pal_lld_readlatch(port) +#endif + +/** + * @brief Writes a bits mask on a I/O port. + * @note The default implementation does nothing except computing the + * parameters eventual side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @api + */ +#if !defined(pal_lld_writeport) || defined(__DOXYGEN__) +#define palWritePort(port, bits) ((void)(port), (void)(bits)) +#else +#define palWritePort(port, bits) pal_lld_writeport(port, bits) +#endif + +/** + * @brief Sets a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @api + */ +#if !defined(pal_lld_setport) || defined(__DOXYGEN__) +#define palSetPort(port, bits) \ + palWritePort(port, palReadLatch(port) | (bits)) +#else +#define palSetPort(port, bits) pal_lld_setport(port, bits) +#endif + +/** + * @brief Clears a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @api + */ +#if !defined(pal_lld_clearport) || defined(__DOXYGEN__) +#define palClearPort(port, bits) \ + palWritePort(port, palReadLatch(port) & ~(bits)) +#else +#define palClearPort(port, bits) pal_lld_clearport(port, bits) +#endif + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @api + */ +#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__) +#define palTogglePort(port, bits) \ + palWritePort(port, palReadLatch(port) ^ (bits)) +#else +#define palTogglePort(port, bits) pal_lld_toggleport(port, bits) +#endif + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the input + * data + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @api + */ +#if !defined(pal_lld_readgroup) || defined(__DOXYGEN__) +#define palReadGroup(port, mask, offset) \ + ((palReadPort(port) >> (offset)) & (mask)) +#else +#define palReadGroup(port, mask, offset) pal_lld_readgroup(port, mask, offset) +#endif + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the + * output data + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @api + */ +#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__) +#define palWriteGroup(port, mask, offset, bits) \ + palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \ + (((bits) & (mask)) << (offset))) +#else +#define palWriteGroup(port, mask, offset, bits) \ + pal_lld_writegroup(port, mask, offset, bits) +#endif + + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @api + */ +#if !defined(pal_lld_setgroupmode) || defined(__DOXYGEN__) +#define palSetGroupMode(port, mask, offset, mode) +#else +#define palSetGroupMode(port, mask, offset, mode) \ + pal_lld_setgroupmode(port, mask, offset, mode) +#endif + +/** + * @brief Reads an input pad logical state. + * @note The default implementation not necessarily optimal. Low level + * drivers may optimize the function by using specific hardware + * or coding. + * @note The default implementation internally uses the @p palReadPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @api + */ +#if !defined(pal_lld_readpad) || defined(__DOXYGEN__) +#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1) +#else +#define palReadPad(port, pad) pal_lld_readpad(port, pad) +#endif + +/** + * @brief Writes a logical state on an output pad. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palReadLatch() + * and @p palWritePort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @api + */ +#if !defined(pal_lld_writepad) || defined(__DOXYGEN__) +#define palWritePad(port, pad, bit) \ + palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \ + (((bit) & 1) << pad)) +#else +#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit) +#endif + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palSetPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_setpad) || defined(__DOXYGEN__) +#define palSetPad(port, pad) palSetPort(port, PAL_PORT_BIT(pad)) +#else +#define palSetPad(port, pad) pal_lld_setpad(port, pad) +#endif + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palClearPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_clearpad) || defined(__DOXYGEN__) +#define palClearPad(port, pad) palClearPort(port, PAL_PORT_BIT(pad)) +#else +#define palClearPad(port, pad) pal_lld_clearpad(port, pad) +#endif + +/** + * @brief Toggles a pad logical state. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palTogglePort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_togglepad) || defined(__DOXYGEN__) +#define palTogglePad(port, pad) palTogglePort(port, PAL_PORT_BIT(pad)) +#else +#define palTogglePad(port, pad) pal_lld_togglepad(port, pad) +#endif + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The default implementation not necessarily optimal. Low level + * drivers may optimize the function by using specific hardware + * or coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @api + */ +#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__) +#define palSetPadMode(port, pad, mode) \ + palSetGroupMode(port, PAL_PORT_BIT(pad), 0, mode) +#else +#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode) +#endif +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + ioportmask_t palReadBus(IOBus *bus); + void palWriteBus(IOBus *bus, ioportmask_t bits); + void palSetBusMode(IOBus *bus, iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* _PAL_H_ */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/include/pwm.h b/os/hal/include/pwm.h new file mode 100644 index 000000000..e943df382 --- /dev/null +++ b/os/hal/include/pwm.h @@ -0,0 +1,252 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file pwm.h + * @brief PWM Driver macros and structures. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_H_ +#define _PWM_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name PWM output mode macros + * @{ + */ +/** + * @brief Standard output modes mask. + */ +#define PWM_OUTPUT_MASK 0x0F + +/** + * @brief Output not driven, callback only. + */ +#define PWM_OUTPUT_DISABLED 0x00 + +/** + * @brief Positive PWM logic, active is logic level one. + */ +#define PWM_OUTPUT_ACTIVE_HIGH 0x01 + +/** + * @brief Inverse PWM logic, active is logic level zero. + */ +#define PWM_OUTPUT_ACTIVE_LOW 0x02 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + PWM_UNINIT = 0, /**< Not initialized. */ + PWM_STOP = 1, /**< Stopped. */ + PWM_READY = 2, /**< Ready. */ +} pwmstate_t; + +/** + * @brief Type of a structure representing a PWM driver. + */ +typedef struct PWMDriver PWMDriver; + +/** + * @brief PWM notification callback type. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +typedef void (*pwmcallback_t)(PWMDriver *pwmp); + +#include "pwm_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name PWM duty cycle conversion + * @{ + */ +/** + * @brief Converts from fraction to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify tenths of thousandth but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] denominator denominator of the fraction + * @param[in] numerator numerator of the fraction + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_FRACTION_TO_WIDTH(pwmp, denominator, numerator) \ + ((uint16_t)((((uint32_t)(pwmp)->period) * \ + (uint32_t)(numerator)) / (uint32_t)(denominator))) + +/** + * @brief Converts from degrees to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify hundredths of degrees but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] degrees degrees as an integer between 0 and 36000 + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ + PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) + +/** + * @brief Converts from percentage to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify tenths of thousandth but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] percentage percentage as an integer between 0 and 10000 + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ + PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] value new cycle time in ticks + * + * @iclass + */ +#define pwmChangePeriodI(pwmp, value) { \ + (pwmp)->period = (value); \ + pwm_lld_change_period(pwmp, value); \ +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @iclass + */ +#define pwmEnableChannelI(pwmp, channel, width) \ + pwm_lld_enable_channel(pwmp, channel, width) + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @iclass + */ +#define pwmDisableChannelI(pwmp, channel) \ + pwm_lld_disable_channel(pwmp, channel) + +/** + * @brief Returns a PWM channel status. + * @pre The PWM unit must have been activated using @p pwmStart(). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @iclass + */ +#define pwmIsChannelEnabledI(pwmp, channel) \ + pwm_lld_is_channel_enabled(pwmp, channel) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void pwmInit(void); + void pwmObjectInit(PWMDriver *pwmp); + void pwmStart(PWMDriver *pwmp, const PWMConfig *config); + void pwmStop(PWMDriver *pwmp); + void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period); + void pwmEnableChannel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_H_ */ + +/** @} */ diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h new file mode 100644 index 000000000..b510df907 --- /dev/null +++ b/os/hal/include/rtc.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file rtc.h + * @brief RTC Driver macros and structures. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_H_ +#define _RTC_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Date/Time bit masks + * @{ + */ +#define RTC_TIME_SECONDS_MASK 0x0000001F /* @brief Seconds mask. */ +#define RTC_TIME_MINUTES_MASK 0x000007E0 /* @brief Minutes mask. */ +#define RTC_TIME_HOURS_MASK 0x0000F800 /* @brief Hours mask. */ +#define RTC_DATE_DAYS_MASK 0x001F0000 /* @brief Days mask. */ +#define RTC_DATE_MONTHS_MASK 0x01E00000 /* @brief Months mask. */ +#define RTC_DATE_YEARS_MASK 0xFE000000 /* @brief Years mask. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC driver. + */ +typedef struct RTCDriver RTCDriver; + +/** + * @brief Type of a structure representing an RTC time stamp. + */ +typedef struct RTCTime RTCTime; + +#include "rtc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Set current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @iclass + */ +#define rtcSetTimeI(rtcp, timespec) rtc_lld_set_time(rtcp, timespec) + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @iclass + */ +#define rtcGetTimeI(rtcp, timespec) rtc_lld_get_time(rtcp, timespec) + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL + * + * @iclass + */ +#define rtcSetAlarmI(rtcp, alarm, alarmspec) \ + rtc_lld_set_alarm(rtcp, alarm, alarmspec) + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @iclass + */ +#define rtcGetAlarmI(rtcp, alarm, alarmspec) \ + rtc_lld_get_alarm(rtcp, alarm, alarmspec) +#endif /* RTC_ALARMS > 0 */ + +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables the callback, use a @p NULL + * pointer in order to disable it. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @iclass + */ +#define rtcSetCallbackI(rtcp, callback) rtc_lld_set_callback(rtcp, callback) +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtcInit(void); + void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec); + void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec); +#if RTC_ALARMS > 0 + void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec); +#endif + uint32_t rtcGetTimeFat(RTCDriver *rtcp); +#if RTC_SUPPORTS_CALLBACKS + void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ +#endif /* _RTC_H_ */ + +/** @} */ diff --git a/os/hal/include/sdc.h b/os/hal/include/sdc.h new file mode 100644 index 000000000..0975ed167 --- /dev/null +++ b/os/hal/include/sdc.h @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file sdc.h + * @brief SDC Driver macros and structures. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_H_ +#define _SDC_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name SD cart types + * @{ + */ +#define SDC_MODE_CARDTYPE_MASK 0xF /**< @brief Card type mask. */ +#define SDC_MODE_CARDTYPE_SDV11 0 /**< @brief Card is SD V1.1.*/ +#define SDC_MODE_CARDTYPE_SDV20 1 /**< @brief Card is SD V2.0.*/ +#define SDC_MODE_CARDTYPE_MMC 2 /**< @brief Card is MMC. */ +#define SDC_MODE_HIGH_CAPACITY 0x10 /**< @brief High cap.card. */ +/** @} */ + +/** + * @name SDC bus error conditions + * @{ + */ +#define SDC_NO_ERROR 0 /**< @brief No error. */ +#define SDC_CMD_CRC_ERROR 1 /**< @brief Command CRC error. */ +#define SDC_DATA_CRC_ERROR 2 /**< @brief Data CRC error. */ +#define SDC_DATA_TIMEOUT 4 /**< @brief HW write timeout. */ +#define SDC_COMMAND_TIMEOUT 8 /**< @brief HW read timeout. */ +#define SDC_TX_UNDERRUN 16 /**< @brief TX buffer underrun. */ +#define SDC_RX_OVERRUN 32 /**< @brief RX buffer overrun. */ +#define SDC_STARTBIT_ERROR 64 /**< @brief Start bit missing. */ +#define SDC_OVERFLOW_ERROR 128 /**< @brief Card overflow error. */ +#define SDC_UNHANDLED_ERROR 0xFFFFFFFF +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SDC configuration options + * @{ + */ +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#include "sdc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the card insertion status. + * @note This macro wraps a low level function named + * @p sdc_lld_is_card_inserted(), this function must be + * provided by the application because it is not part of the + * SDC driver. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define sdcIsCardInserted(sdcp) (sdc_lld_is_card_inserted(sdcp)) + +/** + * @brief Returns the write protect status. + * @note This macro wraps a low level function named + * @p sdc_lld_is_write_protected(), this function must be + * provided by the application because it is not part of the + * SDC driver. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The card state. + * @retval FALSE not write protected. + * @retval TRUE write protected. + * + * @api + */ +#define sdcIsWriteProtected(sdcp) (sdc_lld_is_write_protected(sdcp)) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sdcInit(void); + void sdcObjectInit(SDCDriver *sdcp); + void sdcStart(SDCDriver *sdcp, const SDCConfig *config); + void sdcStop(SDCDriver *sdcp); + bool_t sdcConnect(SDCDriver *sdcp); + bool_t sdcDisconnect(SDCDriver *sdcp); + bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buffer, uint32_t n); + bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buffer, uint32_t n); + sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp); + bool_t sdcSync(SDCDriver *sdcp); + bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip); + bool_t sdcErase(SDCDriver *mmcp, uint32_t startblk, uint32_t endblk); + bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_H_ */ + +/** @} */ diff --git a/os/hal/include/serial.h b/os/hal/include/serial.h new file mode 100644 index 000000000..a44e10cac --- /dev/null +++ b/os/hal/include/serial.h @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file serial.h + * @brief Serial Driver macros and structures. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_H_ +#define _SERIAL_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Serial status flags + * @{ + */ +#define SD_PARITY_ERROR 32 /**< @brief Parity error happened. */ +#define SD_FRAMING_ERROR 64 /**< @brief Framing error happened. */ +#define SD_OVERRUN_ERROR 128 /**< @brief Overflow happened. */ +#define SD_NOISE_ERROR 256 /**< @brief Noise on the line. */ +#define SD_BREAK_DETECTED 512 /**< @brief Break detected. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Serial configuration options + * @{ + */ +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_QUEUES && !CH_USE_EVENTS +#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SD_UNINIT = 0, /**< Not initialized. */ + SD_STOP = 1, /**< Stopped. */ + SD_READY = 2 /**< Ready. */ +} sdstate_t; + +/** + * @brief Structure representing a serial driver. + */ +typedef struct SerialDriver SerialDriver; + +#include "serial_lld.h" + +/** + * @brief @p SerialDriver specific methods. + */ +#define _serial_driver_methods \ + _base_asynchronous_channel_methods + +/** + * @extends BaseAsynchronousChannelVMT + * + * @brief @p SerialDriver virtual methods table. + */ +struct SerialDriverVMT { + _serial_driver_methods +}; + +/** + * @extends BaseAsynchronousChannel + * + * @brief Full duplex serial driver class. + * @details This class extends @p BaseAsynchronousChannel by adding physical + * I/O queues. + */ +struct SerialDriver { + /** @brief Virtual Methods Table.*/ + const struct SerialDriverVMT *vmt; + _serial_driver_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Direct output check on a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * checks directly the output queue. This is faster but cannot + * be used to check different channels implementations. + * + * @see chIOPutWouldBlock() + * @deprecated + * + * @api + */ +#define sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue) + +/** + * @brief Direct input check on a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * checks directly the input queue. This is faster but cannot + * be used to check different channels implementations. + * + * @see chIOGetWouldBlock() + * @deprecated + * + * @api + */ +#define sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue) + +/** + * @brief Direct write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly on the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOPut() + * + * @api + */ +#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b) + +/** + * @brief Direct write to a @p SerialDriver with timeout specification. + * @note This function bypasses the indirect access to the channel and + * writes directly on the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOPutTimeout() + * + * @api + */ +#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->oqueue, b, t) + +/** + * @brief Direct read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOGet() + * + * @api + */ +#define sdGet(sdp) chIQGet(&(sdp)->iqueue) + +/** + * @brief Direct read from a @p SerialDriver with timeout specification. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOGetTimeout() + * + * @api + */ +#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t) + +/** + * @brief Direct blocking write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write from different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdWrite(sdp, b, n) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) + +/** + * @brief Direct blocking write to a @p SerialDriver with timeout + * specification. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdWriteTimeout(sdp, b, n, t) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, t) + +/** + * @brief Direct non-blocking write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdAsynchronousWrite(sdp, b, n) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) + +/** + * @brief Direct blocking read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdRead(sdp, b, n) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) + +/** + * @brief Direct blocking read from a @p SerialDriver with timeout + * specification. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdReadTimeout(sdp, b, n, t) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, t) + +/** + * @brief Direct non-blocking read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdAsynchronousRead(sdp, b, n) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sdInit(void); + void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify); + void sdStart(SerialDriver *sdp, const SerialConfig *config); + void sdStop(SerialDriver *sdp); + void sdIncomingDataI(SerialDriver *sdp, uint8_t b); + msg_t sdRequestDataI(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_H_ */ + +/** @} */ diff --git a/os/hal/include/serial_usb.h b/os/hal/include/serial_usb.h new file mode 100644 index 000000000..28ab3a940 --- /dev/null +++ b/os/hal/include/serial_usb.h @@ -0,0 +1,234 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file serial_usb.h + * @brief Serial over USB Driver macros and structures. + * + * @addtogroup SERIAL_USB + * @{ + */ + +#ifndef _SERIAL_USB_H_ +#define _SERIAL_USB_H_ + +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CDC specific messages. + * @{ + */ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_AUX_LINE_STATE 0x10 +#define CDC_SET_HOOK_STATE 0x11 +#define CDC_PULSE_SETUP 0x12 +#define CDC_SEND_PULSE 0x13 +#define CDC_SET_PULSE_TIME 0x14 +#define CDC_RING_AUX_JACK 0x15 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 +#define CDC_SET_RINGER_PARMS 0x30 +#define CDC_GET_RINGER_PARMS 0x31 +#define CDC_SET_OPERATION_PARMS 0x32 +#define CDC_GET_OPERATION_PARMS 0x33 +/** @} */ + +/** + * @name Line Control bit definitions. + * @{ + */ +#define LC_STOP_1 0 +#define LC_STOP_1P5 1 +#define LC_STOP_2 2 + +#define LC_PARITY_NONE 0 +#define LC_PARITY_ODD 1 +#define LC_PARITY_EVEN 2 +#define LC_PARITY_MARK 3 +#define LC_PARITY_SPACE 4 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SERIAL_USB configuration options + * @{ + */ +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_USB || !CH_USE_QUEUES || !CH_USE_EVENTS +#error "Serial over USB Driver requires HAL_USE_USB, CH_USE_QUEUES, " + "CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of Line Coding structure. + */ +typedef struct { + uint8_t dwDTERate[4]; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} cdc_linecoding_t; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDU_UNINIT = 0, /**< Not initialized. */ + SDU_STOP = 1, /**< Stopped. */ + SDU_READY = 2 /**< Ready. */ +} sdustate_t; + +/** + * @brief Structure representing a serial over USB driver. + */ +typedef struct SerialUSBDriver SerialUSBDriver; + +/** + * @brief Serial over USB Driver configuration structure. + * @details An instance of this structure must be passed to @p sduStart() + * in order to configure and start the driver operations. + */ +typedef struct { + /** + * @brief USB driver to use. + */ + USBDriver *usbp; + /** + * @brief Bulk IN endpoint used for outgoing data transfer. + */ + usbep_t bulk_in; + /** + * @brief Bulk OUT endpoint used for incoming data transfer. + */ + usbep_t bulk_out; + /** + * @brief Interrupt IN endpoint used for notifications. + */ + usbep_t int_in; +} SerialUSBConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_usb_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdustate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input buffer.*/ \ + uint8_t ib[SERIAL_USB_BUFFERS_SIZE]; \ + /* Output buffer.*/ \ + uint8_t ob[SERIAL_USB_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Current configuration data.*/ \ + const SerialUSBConfig *config; + +/** + * @brief @p SerialUSBDriver specific methods. + */ +#define _serial_usb_driver_methods \ + _base_asynchronous_channel_methods + +/** + * @extends BaseAsynchronousChannelVMT + * + * @brief @p SerialDriver virtual methods table. + */ +struct SerialUSBDriverVMT { + _serial_usb_driver_methods +}; + +/** + * @extends BaseAsynchronousChannel + * + * @brief Full duplex serial driver class. + * @details This class extends @p BaseAsynchronousChannel by adding physical + * I/O queues. + */ +struct SerialUSBDriver { + /** @brief Virtual Methods Table.*/ + const struct SerialUSBDriverVMT *vmt; + _serial_usb_driver_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sduInit(void); + void sduObjectInit(SerialUSBDriver *sdp); + void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config); + void sduStop(SerialUSBDriver *sdup); + void sduConfigureHookI(SerialUSBDriver *sdup); + bool_t sduRequestsHook(USBDriver *usbp); + void sduDataTransmitted(USBDriver *usbp, usbep_t ep); + void sduDataReceived(USBDriver *usbp, usbep_t ep); + void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL_USB */ + +#endif /* _SERIAL_USB_H_ */ + +/** @} */ diff --git a/os/hal/include/spi.h b/os/hal/include/spi.h new file mode 100644 index 000000000..f9988631b --- /dev/null +++ b/os/hal/include/spi.h @@ -0,0 +1,323 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file spi.h + * @brief SPI Driver macros and structures. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SPI configuration options + * @{ + */ +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SPI_UNINIT = 0, /**< Not initialized. */ + SPI_STOP = 1, /**< Stopped. */ + SPI_READY = 2, /**< Ready. */ + SPI_ACTIVE = 3, /**< Exchanging data. */ + SPI_COMPLETE = 4 /**< Asynchronous operation complete. */ +} spistate_t; + +#include "spi_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @iclass + */ +#define spiSelectI(spip) { \ + spi_lld_select(spip); \ +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @iclass + */ +#define spiUnselectI(spip) { \ + spi_lld_unselect(spip); \ +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @iclass + */ +#define spiStartIgnoreI(spip, n) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_ignore(spip, n); \ +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +#define spiStartExchangeI(spip, n, txbuf, rxbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_exchange(spip, n, txbuf, rxbuf); \ +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @iclass + */ +#define spiStartSendI(spip, n, txbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_send(spip, n, txbuf); \ +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +#define spiStartReceiveI(spip, n, rxbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_receive(spip, n, rxbuf); \ +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * @note This API is implemented as a macro in order to minimize latency. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +#define spiPolledExchange(spip, frame) spi_lld_polled_exchange(spip, frame) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +#if SPI_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Waits for operation completion. + * @details This function waits for the driver to complete the current + * operation. + * @pre An operation must be running while the function is invoked. + * @note No more than one thread can wait on a SPI driver using + * this function. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_wait_s(spip) { \ + chDbgAssert((spip)->thread == NULL, \ + "_spi_wait(), #1", "already waiting"); \ + (spip)->thread = chThdSelf(); \ + chSchGoSleepS(THD_STATE_SUSPENDED); \ +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_wakeup_isr(spip) { \ + if ((spip)->thread != NULL) { \ + Thread *tp = (spip)->thread; \ + (spip)->thread = NULL; \ + chSysLockFromIsr(); \ + chSchReadyI(tp); \ + chSysUnlockFromIsr(); \ + } \ +} +#else /* !SPI_USE_WAIT */ +#define _spi_wait_s(spip) +#define _spi_wakeup_isr(spip) +#endif /* !SPI_USE_WAIT */ + +/** + * @brief Common ISR code. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread wakeup, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_isr_code(spip) { \ + if ((spip)->config->end_cb) { \ + (spip)->state = SPI_COMPLETE; \ + (spip)->config->end_cb(spip); \ + if ((spip)->state == SPI_COMPLETE) \ + (spip)->state = SPI_READY; \ + } \ + else \ + (spip)->state = SPI_READY; \ + _spi_wakeup_isr(spip); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void spiInit(void); + void spiObjectInit(SPIDriver *spip); + void spiStart(SPIDriver *spip, const SPIConfig *config); + void spiStop(SPIDriver *spip); + void spiSelect(SPIDriver *spip); + void spiUnselect(SPIDriver *spip); + void spiStartIgnore(SPIDriver *spip, size_t n); + void spiStartExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf); + void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf); +#if SPI_USE_WAIT + void spiIgnore(SPIDriver *spip, size_t n); + void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); + void spiSend(SPIDriver *spip, size_t n, const void *txbuf); + void spiReceive(SPIDriver *spip, size_t n, void *rxbuf); +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION + void spiAcquireBus(SPIDriver *spip); + void spiReleaseBus(SPIDriver *spip); +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_H_ */ + +/** @} */ diff --git a/os/hal/include/tm.h b/os/hal/include/tm.h new file mode 100644 index 000000000..14578a167 --- /dev/null +++ b/os/hal/include/tm.h @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file tm.h + * @brief Time Measurement driver header. + * + * @addtogroup TM + * @{ + */ + +#ifndef _TM_H_ +#define _TM_H_ + +#if HAL_USE_TM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a Time Measurement object. + * @note Start/stop of measurements is performed through the function + * pointers in order to avoid inlining of those functions which + * could compromise measurement accuracy. + * @note The maximum measurable time period depends on the implementation + * of the realtime counter in the HAL driver. + * @note The measurement is not 100% cycle-accurate, it can be in excess + * of few cycles depending on the compiler and target architecture. + * @note Interrupts can affect measurement if the measurement is performed + * with interrupts enabled. + */ +typedef struct TimeMeasurement TimeMeasurement; + +/** + * @brief Time Measurement structure. + */ +struct TimeMeasurement { + void (*start)(TimeMeasurement *tmp); /**< @brief Starts a measurement. */ + void (*stop)(TimeMeasurement *tmp); /**< @brief Stops a measurement. */ + halrtcnt_t last; /**< @brief Last measurement. */ + halrtcnt_t worst; /**< @brief Worst measurement. */ + halrtcnt_t best; /**< @brief Best measurement. */ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Starts a measurement. + * @pre The @p TimeMeasurement must be initialized. + * @note This function can be invoked in any context. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @special + */ +#define tmStartMeasurement(tmp) (tmp)->start(tmp) + +/** + * @brief Stops a measurement. + * @pre The @p TimeMeasurement must be initialized. + * @note This function can be invoked in any context. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @special + */ +#define tmStopMeasurement(tmp) (tmp)->stop(tmp) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void tmInit(void); + void tmObjectInit(TimeMeasurement *tmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_TM */ + +#endif /* _TM_H_ */ + +/** @} */ diff --git a/os/hal/include/uart.h b/os/hal/include/uart.h new file mode 100644 index 000000000..74b77e161 --- /dev/null +++ b/os/hal/include/uart.h @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file uart.h + * @brief UART Driver macros and structures. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_H_ +#define _UART_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name UART status flags + * @{ + */ +#define UART_NO_ERROR 0 /**< @brief No pending conditions. */ +#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */ +#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */ +#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */ +#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */ +#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + UART_UNINIT = 0, /**< Not initialized. */ + UART_STOP = 1, /**< Stopped. */ + UART_READY = 2 /**< Ready. */ +} uartstate_t; + +/** + * @brief Transmitter state machine states. + */ +typedef enum { + UART_TX_IDLE = 0, /**< Not transmitting. */ + UART_TX_ACTIVE = 1, /**< Transmitting. */ + UART_TX_COMPLETE = 2 /**< Buffer complete. */ +} uarttxstate_t; + +/** + * @brief Receiver state machine states. + */ +typedef enum { + UART_RX_IDLE = 0, /**< Not receiving. */ + UART_RX_ACTIVE = 1, /**< Receiving. */ + UART_RX_COMPLETE = 2 /**< Buffer complete. */ +} uartrxstate_t; + +#include "uart_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void uartInit(void); + void uartObjectInit(UARTDriver *uartp); + void uartStart(UARTDriver *uartp, const UARTConfig *config); + void uartStop(UARTDriver *uartp); + void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf); + void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uartStopSend(UARTDriver *uartp); + size_t uartStopSendI(UARTDriver *uartp); + void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf); + void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uartStopReceive(UARTDriver *uartp); + size_t uartStopReceiveI(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_H_ */ + +/** @} */ diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h new file mode 100644 index 000000000..b56385403 --- /dev/null +++ b/os/hal/include/usb.h @@ -0,0 +1,572 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file usb.h + * @brief USB Driver macros and structures. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_H_ +#define _USB_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define USB_RTYPE_DIR_MASK 0x80 +#define USB_RTYPE_DIR_HOST2DEV 0x00 +#define USB_RTYPE_DIR_DEV2HOST 0x80 +#define USB_RTYPE_TYPE_MASK 0x60 +#define USB_RTYPE_TYPE_STD 0x00 +#define USB_RTYPE_TYPE_CLASS 0x20 +#define USB_RTYPE_TYPE_VENDOR 0x40 +#define USB_RTYPE_TYPE_RESERVED 0x60 +#define USB_RTYPE_RECIPIENT_MASK 0x1F +#define USB_RTYPE_RECIPIENT_DEVICE 0x00 +#define USB_RTYPE_RECIPIENT_INTERFACE 0x01 +#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02 +#define USB_RTYPE_RECIPIENT_OTHER 0x03 + +#define USB_REQ_GET_STATUS 0 +#define USB_REQ_CLEAR_FEATURE 1 +#define USB_REQ_SET_FEATURE 3 +#define USB_REQ_SET_ADDRESS 5 +#define USB_REQ_GET_DESCRIPTOR 6 +#define USB_REQ_SET_DESCRIPTOR 7 +#define USB_REQ_GET_CONFIGURATION 8 +#define USB_REQ_SET_CONFIGURATION 9 +#define USB_REQ_GET_INTERFACE 10 +#define USB_REQ_SET_INTERFACE 11 +#define USB_REQ_SYNCH_FRAME 12 + +#define USB_DESCRIPTOR_DEVICE 1 +#define USB_DESCRIPTOR_CONFIGURATION 2 +#define USB_DESCRIPTOR_STRING 3 +#define USB_DESCRIPTOR_INTERFACE 4 +#define USB_DESCRIPTOR_ENDPOINT 5 +#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6 +#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7 +#define USB_DESCRIPTOR_INTERFACE_POWER 8 +#define USB_DESCRIPTOR_INTERFACE_ASSOCIATION 11 + +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +#define USB_EARLY_SET_ADDRESS 0 +#define USB_LATE_SET_ADDRESS 1 + +/** + * @name Helper macros for USB descriptors + * @{ + */ +/** + * @brief Helper macro for index values into descriptor strings. + */ +#define USB_DESC_INDEX(i) ((uint8_t)(i)) + +/** + * @brief Helper macro for byte values into descriptor strings. + */ +#define USB_DESC_BYTE(b) ((uint8_t)(b)) + +/** + * @brief Helper macro for word values into descriptor strings. + */ +#define USB_DESC_WORD(w) \ + (uint8_t)((w) & 255), \ + (uint8_t)(((w) >> 8) & 255) + +/** + * @brief Helper macro for BCD values into descriptor strings. + */ +#define USB_DESC_BCD(bcd) \ + (uint8_t)((bcd) & 255), \ + (uint8_t)(((bcd) >> 8) & 255) + +/** + * @brief Device Descriptor helper macro. + */ +#define USB_DESC_DEVICE(bcdUSB, bDeviceClass, bDeviceSubClass, \ + bDeviceProtocol, bMaxPacketSize, idVendor, \ + idProduct, bcdDevice, iManufacturer, \ + iProduct, iSerialNumber, bNumConfigurations) \ + USB_DESC_BYTE(18), \ + USB_DESC_BYTE(USB_DESCRIPTOR_DEVICE), \ + USB_DESC_BCD(bcdUSB), \ + USB_DESC_BYTE(bDeviceClass), \ + USB_DESC_BYTE(bDeviceSubClass), \ + USB_DESC_BYTE(bDeviceProtocol), \ + USB_DESC_BYTE(bMaxPacketSize), \ + USB_DESC_WORD(idVendor), \ + USB_DESC_WORD(idProduct), \ + USB_DESC_BCD(bcdDevice), \ + USB_DESC_INDEX(iManufacturer), \ + USB_DESC_INDEX(iProduct), \ + USB_DESC_INDEX(iSerialNumber), \ + USB_DESC_BYTE(bNumConfigurations) + +/** + * @brief Configuration Descriptor helper macro. + */ +#define USB_DESC_CONFIGURATION(wTotalLength, bNumInterfaces, \ + bConfigurationValue, iConfiguration, \ + bmAttributes, bMaxPower) \ + USB_DESC_BYTE(9), \ + USB_DESC_BYTE(USB_DESCRIPTOR_CONFIGURATION), \ + USB_DESC_WORD(wTotalLength), \ + USB_DESC_BYTE(bNumInterfaces), \ + USB_DESC_BYTE(bConfigurationValue), \ + USB_DESC_INDEX(iConfiguration), \ + USB_DESC_BYTE(bmAttributes), \ + USB_DESC_BYTE(bMaxPower) + +/** + * @brief Interface Descriptor helper macro. + */ +#define USB_DESC_INTERFACE(bInterfaceNumber, bAlternateSetting, \ + bNumEndpoints, bInterfaceClass, \ + bInterfaceSubClass, bInterfaceProtocol, \ + iInterface) \ + USB_DESC_BYTE(9), \ + USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE), \ + USB_DESC_BYTE(bInterfaceNumber), \ + USB_DESC_BYTE(bAlternateSetting), \ + USB_DESC_BYTE(bNumEndpoints), \ + USB_DESC_BYTE(bInterfaceClass), \ + USB_DESC_BYTE(bInterfaceSubClass), \ + USB_DESC_BYTE(bInterfaceProtocol), \ + USB_DESC_INDEX(iInterface) + +/** + * @brief Interface Association Descriptor helper macro. + */ +#define USB_DESC_INTERFACE_ASSOCIATION(bFirstInterface, \ + bInterfaceCount, bFunctionClass, \ + bFunctionSubClass, bFunctionProcotol, \ + iInterface) \ + USB_DESC_BYTE(8), \ + USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE_ASSOCIATION), \ + USB_DESC_BYTE(bFirstInterface), \ + USB_DESC_BYTE(bInterfaceCount), \ + USB_DESC_BYTE(bFunctionClass), \ + USB_DESC_BYTE(bFunctionSubClass), \ + USB_DESC_BYTE(bFunctionProcotol), \ + USB_DESC_INDEX(iInterface) + +/** + * @brief Endpoint Descriptor helper macro. + */ +#define USB_DESC_ENDPOINT(bEndpointAddress, bmAttributes, wMaxPacketSize, \ + bInterval) \ + USB_DESC_BYTE(7), \ + USB_DESC_BYTE(USB_DESCRIPTOR_ENDPOINT), \ + USB_DESC_BYTE(bEndpointAddress), \ + USB_DESC_BYTE(bmAttributes), \ + USB_DESC_WORD(wMaxPacketSize), \ + USB_DESC_BYTE(bInterval) +/** @} */ + +/** + * @name Endpoint types and settings + * @{ + */ +#define USB_EP_MODE_TYPE 0x0003 /**< Endpoint type mask. */ +#define USB_EP_MODE_TYPE_CTRL 0x0000 /**< Control endpoint. */ +#define USB_EP_MODE_TYPE_ISOC 0x0001 /**< Isochronous endpoint. */ +#define USB_EP_MODE_TYPE_BULK 0x0002 /**< Bulk endpoint. */ +#define USB_EP_MODE_TYPE_INTR 0x0003 /**< Interrupt endpoint. */ +#define USB_EP_MODE_LINEAR_BUFFER 0x0000 /**< Linear buffer mode. */ +#define USB_EP_MODE_QUEUE_BUFFER 0x0010 /**< Queue buffer mode. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an USB driver. + */ +typedef struct USBDriver USBDriver; + +/** + * @brief Type of an endpoint identifier. + */ +typedef uint8_t usbep_t; + +/** + * @brief Type of a driver state machine possible states. + */ +typedef enum { + USB_UNINIT = 0, /**< Not initialized. */ + USB_STOP = 1, /**< Stopped. */ + USB_READY = 2, /**< Ready, after bus reset. */ + USB_SELECTED = 3, /**< Address assigned. */ + USB_ACTIVE = 4 /**< Active, configuration selected.*/ +} usbstate_t; + +/** + * @brief Type of an endpoint status. + */ +typedef enum { + EP_STATUS_DISABLED = 0, /**< Endpoint not active. */ + EP_STATUS_STALLED = 1, /**< Endpoint opened but stalled. */ + EP_STATUS_ACTIVE = 2 /**< Active endpoint. */ +} usbepstatus_t; + +/** + * @brief Type of an endpoint zero state machine states. + */ +typedef enum { + USB_EP0_WAITING_SETUP, /**< Waiting for SETUP data. */ + USB_EP0_TX, /**< Transmitting. */ + USB_EP0_WAITING_TX0, /**< Waiting transmit 0. */ + USB_EP0_WAITING_STS, /**< Waiting status. */ + USB_EP0_RX, /**< Receiving. */ + USB_EP0_SENDING_STS, /**< Sending status. */ + USB_EP0_ERROR /**< Error, EP0 stalled. */ +} usbep0state_t; + +/** + * @brief Type of an enumeration of the possible USB events. + */ +typedef enum { + USB_EVENT_RESET = 0, /**< Driver has been reset by host. */ + USB_EVENT_ADDRESS = 1, /**< Address assigned. */ + USB_EVENT_CONFIGURED = 2, /**< Configuration selected. */ + USB_EVENT_SUSPEND = 3, /**< Entering suspend mode. */ + USB_EVENT_WAKEUP = 4, /**< Leaving suspend mode. */ + USB_EVENT_STALLED = 5 /**< Endpoint 0 error, stalled. */ +} usbevent_t; + +/** + * @brief Type of an USB descriptor. + */ +typedef struct { + /** + * @brief Descriptor size in unicode characters. + */ + size_t ud_size; + /** + * @brief Pointer to the descriptor. + */ + const uint8_t *ud_string; +} USBDescriptor; + +/** + * @brief Type of an USB generic notification callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + */ +typedef void (*usbcallback_t)(USBDriver *usbp); + +/** + * @brief Type of an USB endpoint callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @param[in] ep endpoint number + */ +typedef void (*usbepcallback_t)(USBDriver *usbp, usbep_t ep); + +/** + * @brief Type of an USB event notification callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @param[in] event event type + */ +typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event); + +/** + * @brief Type of a requests handler callback. + * @details The request is encoded in the @p usb_setup buffer. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @return The request handling exit code. + * @retval FALSE Request not recognized by the handler. + * @retval TRUE Request handled. + */ +typedef bool_t (*usbreqhandler_t)(USBDriver *usbp); + +/** + * @brief Type of an USB descriptor-retrieving callback. + */ +typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang); + +#include "usb_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the driver state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The driver state. + * + * @iclass + */ +#define usbGetDriverStateI(usbp) ((usbp)->state) + +/** + * @brief Fetches a 16 bits word value from an USB message. + * + * @param[in] p pointer to the 16 bits word + * + * @notapi + */ +#define usbFetchWord(p) ((uint16_t)*(p) | ((uint16_t)*((p) + 1) << 8)) + +/** + * @brief Connects the USB device. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @api + */ +#define usbConnectBus(usbp) usb_lld_connect_bus(usbp) + +/** + * @brief Disconnect the USB device. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @api + */ +#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp) + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @api + */ +#define usbGetFrameNumber(usbp) usb_lld_get_frame_number(usbp) + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint ready. + * @retval TRUE Endpoint transmitting. + * + * @iclass + */ +#define usbGetTransmitStatusI(usbp, ep) ((usbp)->transmitting & (1 << (ep))) + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint ready. + * @retval TRUE Endpoint receiving. + * + * @iclass + */ +#define usbGetReceiveStatusI(usbp, ep) ((usbp)->receiving & (1 << (ep))) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @iclass + */ +#define usbGetReceiveTransactionSizeI(usbp, ep) \ + usb_lld_get_transaction_size(usbp, ep) + +/** + * @brief Request transfer setup. + * @details This macro is used by the request handling callbacks in order to + * prepare a transaction over the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] buf pointer to a buffer for the transaction data + * @param[in] n number of bytes to be transferred + * @param[in] endcb callback to be invoked after the transfer or @p NULL + * + * @api + */ +#define usbSetupTransfer(usbp, buf, n, endcb) { \ + (usbp)->ep0next = (buf); \ + (usbp)->ep0n = (n); \ + (usbp)->ep0endcb = (endcb); \ +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @special + */ +#define usbReadSetup(usbp, ep, buf) usb_lld_read_setup(usbp, ep, buf) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +/** + * @brief Common ISR code, usb event callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] evt USB event code + * + * @notapi + */ +#define _usb_isr_invoke_event_cb(usbp, evt) { \ + if (((usbp)->config->event_cb) != NULL) \ + (usbp)->config->event_cb(usbp, evt); \ +} + +/** + * @brief Common ISR code, SOF callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +#define _usb_isr_invoke_sof_cb(usbp) { \ + if (((usbp)->config->sof_cb) != NULL) \ + (usbp)->config->sof_cb(usbp); \ +} + +/** + * @brief Common ISR code, setup packet callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_setup_cb(usbp, ep) { \ + (usbp)->epc[ep]->setup_cb(usbp, ep); \ +} + +/** + * @brief Common ISR code, IN endpoint callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_in_cb(usbp, ep) { \ + (usbp)->transmitting &= ~(1 << (ep)); \ + (usbp)->epc[ep]->in_cb(usbp, ep); \ +} + +/** + * @brief Common ISR code, OUT endpoint event. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_out_cb(usbp, ep) { \ + (usbp)->receiving &= ~(1 << (ep)); \ + (usbp)->epc[ep]->out_cb(usbp, ep); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void usbInit(void); + void usbObjectInit(USBDriver *usbp); + void usbStart(USBDriver *usbp, const USBConfig *config); + void usbStop(USBDriver *usbp); + void usbInitEndpointI(USBDriver *usbp, usbep_t ep, + const USBEndpointConfig *epcp); + void usbDisableEndpointsI(USBDriver *usbp); + void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usbPrepareReceive(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usbPrepareTransmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep, + InputQueue *iqp, size_t n); + void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep, + OutputQueue *oqp, size_t n); + bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep); + bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep); + bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep); + bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep); + void _usb_reset(USBDriver *usbp); + void _usb_ep0setup(USBDriver *usbp, usbep_t ep); + void _usb_ep0in(USBDriver *usbp, usbep_t ep); + void _usb_ep0out(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/adc_lld.c b/os/hal/platforms/AT91SAM7/adc_lld.c new file mode 100644 index 000000000..066e3c542 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/adc_lld.c @@ -0,0 +1,382 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + This file has been contributed by: + Andrew Hannam aka inmarket. +*/ +/** + * @file AT91SAM7/adc_lld.c + * @brief AT91SAM7 ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/** + * @brief ADC1 Prescaler + * @detail Prescale = RoundUp(MCK / 2 / ADCClock - 1) + */ +#if ((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1) > 255 + #define AT91_ADC1_PRESCALE 255 +#else + #define AT91_ADC1_PRESCALE ((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1) +#endif + +/** + * @brief ADC1 Startup Time + * @details Startup = RoundUp(ADCClock / 400,000 - 1) + * @note Corresponds to a startup delay > 20uS (as required from the datasheet) + */ +#if (((AT91_ADC1_CLOCK+399999)/400000)-1) > 127 + #define AT91_ADC1_STARTUP 127 +#else + #define AT91_ADC1_STARTUP (((AT91_ADC1_CLOCK+399999)/400000)-1) +#endif + +#if AT91_ADC1_RESOLUTION == 8 + #define AT91_ADC1_MAINMODE (((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_8_BIT) +#else + #define AT91_ADC1_MAINMODE (((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_10_BIT) +#endif + +#if AT91_ADC1_TIMER < 0 || AT91_ADC1_TIMER > 2 + #error "Unknown Timer specified for ADC1" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if !ADC_USE_ADC1 + #error "You must specify ADC_USE_ADC1 if you have specified HAL_USE_ADC" +#endif + +/** @brief ADC1 driver identifier.*/ +ADCDriver ADCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#define ADCReg1 ((AT91S_ADC *)AT91C_ADC_CR) + +#if AT91_ADC1_MAINMODE == 2 + #define ADCTimer1 ((AT91S_TC *)AT91C_TC2_CCR) + #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA2 + #define AT91_ADC1_TIMERID AT91C_ID_TC2 +#elif AT91_ADC1_MAINMODE == 1 + #define ADCTimer1 ((AT91S_TC *)AT91C_TC1_CCR) + #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA1 + #define AT91_ADC1_TIMERID AT91C_ID_TC1 +#else + #define ADCTimer1 ((AT91S_TC *)AT91C_TC0_CCR) + #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA0 + #define AT91_ADC1_TIMERID AT91C_ID_TC0 +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#define adc_sleep() ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_MODE | AT91C_ADC_TRGEN_DIS) +#define adc_wake() ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS) +#define adc_disable() { \ + ADCReg1->ADC_IDR = 0xFFFFFFFF; \ + ADCReg1->ADC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; \ + adc_wake(); \ + ADCReg1->ADC_CHDR = 0xFF; \ + } +#define adc_clrint() { \ + uint32_t isr, dummy; \ + \ + isr = ADCReg1->ADC_SR; \ + if ((isr & AT91C_ADC_DRDY)) dummy = ADCReg1->ADC_LCDR; \ + if ((isr & AT91C_ADC_EOC0)) dummy = ADCReg1->ADC_CDR0; \ + if ((isr & AT91C_ADC_EOC1)) dummy = ADCReg1->ADC_CDR1; \ + if ((isr & AT91C_ADC_EOC2)) dummy = ADCReg1->ADC_CDR2; \ + if ((isr & AT91C_ADC_EOC3)) dummy = ADCReg1->ADC_CDR3; \ + if ((isr & AT91C_ADC_EOC4)) dummy = ADCReg1->ADC_CDR4; \ + if ((isr & AT91C_ADC_EOC5)) dummy = ADCReg1->ADC_CDR5; \ + if ((isr & AT91C_ADC_EOC6)) dummy = ADCReg1->ADC_CDR6; \ + if ((isr & AT91C_ADC_EOC7)) dummy = ADCReg1->ADC_CDR7; \ + } +#define adc_stop() { \ + adc_disable(); \ + adc_clrint(); \ + } + +/** + * We must keep stack usage to a minimum - the default AT91SAM7 isr stack size is very small. + * We sacrifice some speed and code size in order to achieve this by accessing the structure + * and registers directly rather than through the passed in pointers. This works because the + * AT91SAM7 supports only a single ADC device (although with 8 channels). + */ +static void handleint(void) { + uint32_t isr; + + isr = ADCReg1->ADC_SR; + + if (ADCD1.grpp) { + + /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ + if ((isr & AT91C_ADC_GOVRE)) { + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + + /* Transfer complete processing.*/ + } else if ((isr & AT91C_ADC_RXBUFF)) { + if (ADCD1.grpp->circular) { + /* setup the DMA again */ + ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples; + if (ADCD1.depth <= 1) { + ADCReg1->ADC_RCR = ADCD1.grpp->num_channels; + ADCReg1->ADC_RNPR = 0; + ADCReg1->ADC_RNCR = 0; + } else { + ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels; + ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels)); + ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels; + } + ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN; // DMA enabled + } + _adc_isr_full_code(&ADCD1); + + /* Half transfer processing.*/ + } else if ((isr & AT91C_ADC_ENDRX)) { + _adc_isr_half_code(&ADCD1); + } + + } else { + /* Spurious interrupt - Make sure it doesn't happen again */ + adc_disable(); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC_IRQHandler) { + CH_IRQ_PROLOGUE(); + + handleint(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + /* Turn on ADC in the power management controller */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_ADC); + + /* Driver object initialization.*/ + adcObjectInit(&ADCD1); + + ADCReg1->ADC_CR = 0; // 0 or AT91C_ADC_SWRST if you want to do a ADC reset + adc_stop(); + adc_sleep(); + + /* Setup interrupt handler */ + AIC_ConfigureIT(AT91C_ID_ADC, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_ADC_IRQ_PRIORITY, + ADC_IRQHandler); + AIC_EnableIT(AT91C_ID_ADC); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then wake up the ADC */ + if (adcp->state == ADC_STOP) { + + /* Take it out of sleep mode */ + /* We could stay in sleep mode provided total conversion rate < 44kHz but we can't guarantee that here */ + adc_wake(); + + /* TODO: We really should perform a conversion here just to ensure that we are out of sleep mode */ + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + if (adcp->state != ADC_READY) { + adc_stop(); + adc_sleep(); + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t i; + + /* Make sure everything is stopped first */ + adc_stop(); + + /* Safety check the trigger value */ + switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) { + case ADC_TRIGGER_TIMER: + case ADC_TRIGGER_EXTERNAL: + break; + default: + ((ADCConversionGroup *)ADCD1.grpp)->trigger = ADC_TRIGGER_SOFTWARE; + ADCD1.depth = 1; + ((ADCConversionGroup *)ADCD1.grpp)->circular = 0; + break; + } + + /* Count the real number of activated channels in case the user got it wrong */ + ((ADCConversionGroup *)ADCD1.grpp)->num_channels = 0; + for(i=1; i < 0x100; i <<= 1) { + if ((ADCD1.grpp->channelselects & i)) + ((ADCConversionGroup *)ADCD1.grpp)->num_channels++; + } + + /* Set the channels */ + ADCReg1->ADC_CHER = ADCD1.grpp->channelselects; + + /* Set up the DMA */ + ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples; + if (adcp->depth <= 1) { + ADCReg1->ADC_RCR = ADCD1.grpp->num_channels; + ADCReg1->ADC_RNPR = 0; + ADCReg1->ADC_RNCR = 0; + } else { + ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels; + ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels)); + ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels; + } + ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN; + + /* Set up interrupts */ + ADCReg1->ADC_IER = AT91C_ADC_GOVRE | AT91C_ADC_ENDRX | AT91C_ADC_RXBUFF; + + /* Set the trigger */ + switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) { + case ADC_TRIGGER_TIMER: + // Set up the timer if ADCD1.grpp->frequency != 0 + if (ADCD1.grpp->frequency) { + /* Turn on Timer in the power management controller */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91_ADC1_TIMERID); + + /* Disable the clock and the interrupts */ + ADCTimer1->TC_CCR = AT91C_TC_CLKDIS; + ADCTimer1->TC_IDR = 0xFFFFFFFF; + + /* Set the Mode of the Timer Counter and calculate the period */ + i = (MCK/2)/ADCD1.grpp->frequency; + if (i < (0x10000<<0)) { + ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING | + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV1_CLOCK); + } else if (i < (0x10000<<2)) { + i >>= 2; + ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING | + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV2_CLOCK); + } else if (i < (0x10000<<4)) { + i >>= 4; + ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING | + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV3_CLOCK); + } else if (i < (0x10000<<6)) { + i >>= 6; + ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING | + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV4_CLOCK); + } else { + i >>= 9; + ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING | + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV5_CLOCK); + } + + /* RC is the period, RC-RA is the pulse width (in this case = 1) */ + ADCTimer1->TC_RC = i; + ADCTimer1->TC_RA = i - 1; + + /* Start the timer counter */ + ADCTimer1->TC_CCR = (AT91C_TC_CLKEN |AT91C_TC_SWTRG); + } + + ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91_ADC1_TIMERMODE; + break; + + case ADC_TRIGGER_EXTERNAL: + /* Make sure the ADTRG pin is set as an input - assume pull-ups etc have already been set */ + #if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512) + AT91C_BASE_PIOA->PIO_ODR = AT91C_PA8_ADTRG; + #elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || (SAM7_PLATFORM == SAM7X512) + AT91C_BASE_PIOB->PIO_ODR = AT91C_PB18_ADTRG; + #endif + ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91C_ADC_TRGSEL_EXT; + break; + + default: + ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS; + break; + } + + /* Manually start a conversion if we need to */ + if (ADCD1.grpp->trigger & ADC_TRIGGER_SOFTWARE) + ADCReg1->ADC_CR = AT91C_ADC_START; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + (void) adcp; + adc_stop(); +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/adc_lld.h b/os/hal/platforms/AT91SAM7/adc_lld.h new file mode 100644 index 000000000..e27931819 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/adc_lld.h @@ -0,0 +1,303 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + This file has been contributed by: + Andrew Hannam aka inmarket. +*/ +/** + * @file AT91SAM7/adc_lld.h + * @brief AT91SAM7 ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Trigger Sources + * @{ + */ +#define ADC_TRIGGER_SOFTWARE 0x8000 /**< @brief Software Triggering - Can be combined with another value */ +#define ADC_TRIGGER_TIMER 0x0001 /**< @brief TIO Timer Counter Channel */ +#define ADC_TRIGGER_EXTERNAL 0x0002 /**< @brief External Trigger */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(ADC_USE_ADC1) || defined(__DOXYGEN__) +#define ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC1 Timer to use when a periodic conversion is requested. + * @details Should be set to 0..2 + * @note The default is 0 + */ +#if !defined(AT91_ADC1_TIMER) || defined(__DOXYGEN__) +#define AT91_ADC1_TIMER 0 +#endif + +/** + * @brief ADC1 Resolution. + * @details Either 8 or 10 bits + * @note The default is 10 bits. + */ +#if !defined(AT91_ADC1_RESOLUTION) || defined(__DOXYGEN__) +#define AT91_ADC1_RESOLUTION 10 +#endif + +/** + * @brief ADC1 Clock + * @details Maximum is 5MHz for 10bit or 8MHz for 8bit + * @note The default is calculated from AT91_ADC1_RESOLUTION to give the fastest possible ADCClock + */ +#if !defined(AT91_ADC1_CLOCK) || defined(__DOXYGEN__) + #if AT91_ADC1_RESOLUTION == 8 + #define AT91_ADC1_CLOCK 8000000 + #else + #define AT91_ADC1_CLOCK 5000000 + #endif +#endif + +/** + * @brief ADC1 Sample and Hold Time + * @details SHTM = RoundUp(ADCClock * SampleHoldTime). Range = RoundUp(ADCClock / 1,666,666) to 15 + * @note Default corresponds to the minimum sample and hold time (600nS from the datasheet) + * @note Increasing the Sample Hold Time increases the ADC input impedance + */ +#if !defined(AT91_ADC1_SHTM) || defined(__DOXYGEN__) + #define AT91_ADC1_SHTM 0 +#endif +#if AT91_ADC1_SHTM < ((AT91_ADC1_CLOCK+1666665)/1666666) + #undef AT91_ADC1_SHTM + #define AT91_ADC1_SHTM ((AT91_ADC1_CLOCK+1666665)/1666666) +#endif +#if AT91_ADC1_SHTM > 15 + #undef AT91_ADC1_SHTM + #define AT91_ADC1_SHTM 15 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(AT91_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT91_ADC_IRQ_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT91_DMA_REQUIRED) +#define AT91_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +#if AT91_ADC1_RESOLUTION == AT91C_ADC_LOWRES_8_BIT + typedef uint8_t adcsample_t; +#else + typedef uint16_t adcsample_t; +#endif + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_OVERFLOW = 0, /**< ADC overflow condition. Something is not working fast enough. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief Select the ADC Channels to read. + * @details The number of bits at logic level one in this register must + * be equal to the number in the @p num_channels field. + */ + uint16_t channelselects; + /** + * @brief Select how to trigger the conversion. + */ + uint16_t trigger; + /** + * @brief When in ADC_TRIGGER_TIMER trigger mode - what frequency? + */ + uint32_t frequency; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h new file mode 100644 index 000000000..5d609f1cf --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h @@ -0,0 +1,3352 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7A3.h +// Object : AT91SAM7A3 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:10:41) +// +// CVS Reference : /AT91SAM7A3.pl/1.30/Wed Aug 30 14:08:29 2006// +// CVS Reference : /SYS_SAM7A3.pl/1.7/Thu Feb 3 17:24:14 2005// +// CVS Reference : /MC_SAM7A3.pl/1.3/Fri Sep 23 12:47:15 2005// +// CVS Reference : /PMC_SAM7A3.pl/1.2/Tue Feb 8 14:00:18 2005// +// CVS Reference : /RSTC_SAM7A3.pl/1.2/Wed Jul 13 15:25:16 2005// +// CVS Reference : /SHDWC_SAM7A3.pl/1.1/Thu Feb 3 17:23:24 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// +// CVS Reference : /PWM_SAM7A3.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /AES_6149A.pl/1.12/Wed Nov 2 14:17:53 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7A3_H +#define AT91SAM7A3_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[1]; // + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register + AT91_REG Reserved27[1]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved28[1]; // + AT91_REG SYS_GPBR0; // General Purpose Register 0 + AT91_REG SYS_GPBR1; // General Purpose Register 1 + AT91_REG Reserved29[106]; // + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved30[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved31[2]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_SYS, *AT91PS_SYS; +#else +#define SYS_GPBR0 (AT91_CAST(AT91_REG *) 0x00000D50) // (SYS_GPBR0) General Purpose Register 0 +#define SYS_GPBR1 (AT91_CAST(AT91_REG *) 0x00000D54) // (SYS_GPBR1) General Purpose Register 1 + +#endif +// -------- GPBR : (SYS Offset: 0xd50) GPBR General Purpose Register -------- +// -------- GPBR : (SYS Offset: 0xd54) GPBR General Purpose Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Shut Down Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SHDWC { + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register +} AT91S_SHDWC, *AT91PS_SHDWC; +#else +#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register +#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register +#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register + +#endif +// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- +#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset +#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password +// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- +#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection +#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0 +#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection +#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1 +#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable +// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- +#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status +#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status +#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status +#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_EOP (0x1 << 0) // (MC) End Of Programming Flag +#define AT91C_MC_EOL (0x1 << 1) // (MC) End Of Lock/Unlock Flag +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error Flag +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error Flag +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Status Register -------- +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG Reserved0[2]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; +#else +#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register +#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register +#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register +#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register +#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register +#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register +#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register +#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register +#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register +#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register +#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register +#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register +#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register + +#endif +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable +#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN (0xFFF << 18) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL (0xF << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[8]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7A3 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +#define AT91C_SYS_GPBR1 (AT91_CAST(AT91_REG *) 0xFFFFFD54) // (SYS) General Purpose Register 1 +#define AT91C_SYS_GPBR0 (AT91_CAST(AT91_REG *) 0xFFFFFD50) // (SYS) General Purpose Register 0 +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for SHDWC peripheral ========== +#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register +#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register +#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for CAN0_MB0 peripheral ========== +#define AT91C_CAN0_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFF80218) // (CAN0_MB0) MailBox Data High Register +#define AT91C_CAN0_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFF80214) // (CAN0_MB0) MailBox Data Low Register +#define AT91C_CAN0_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFF80204) // (CAN0_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFF8021C) // (CAN0_MB0) MailBox Control Register +#define AT91C_CAN0_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFF80200) // (CAN0_MB0) MailBox Mode Register +#define AT91C_CAN0_MB0_MID (AT91_CAST(AT91_REG *) 0xFFF80208) // (CAN0_MB0) MailBox ID Register +#define AT91C_CAN0_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFF8020C) // (CAN0_MB0) MailBox Family ID Register +#define AT91C_CAN0_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFF80210) // (CAN0_MB0) MailBox Status Register +// ========== Register definition for CAN0_MB1 peripheral ========== +#define AT91C_CAN0_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFF80230) // (CAN0_MB1) MailBox Status Register +#define AT91C_CAN0_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFF80238) // (CAN0_MB1) MailBox Data High Register +#define AT91C_CAN0_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFF8022C) // (CAN0_MB1) MailBox Family ID Register +#define AT91C_CAN0_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFF80224) // (CAN0_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFF80234) // (CAN0_MB1) MailBox Data Low Register +#define AT91C_CAN0_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFF80220) // (CAN0_MB1) MailBox Mode Register +#define AT91C_CAN0_MB1_MID (AT91_CAST(AT91_REG *) 0xFFF80228) // (CAN0_MB1) MailBox ID Register +#define AT91C_CAN0_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFF8023C) // (CAN0_MB1) MailBox Control Register +// ========== Register definition for CAN0_MB2 peripheral ========== +#define AT91C_CAN0_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFF8025C) // (CAN0_MB2) MailBox Control Register +#define AT91C_CAN0_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFF8024C) // (CAN0_MB2) MailBox Family ID Register +#define AT91C_CAN0_MB2_MID (AT91_CAST(AT91_REG *) 0xFFF80248) // (CAN0_MB2) MailBox ID Register +#define AT91C_CAN0_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFF80240) // (CAN0_MB2) MailBox Mode Register +#define AT91C_CAN0_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFF80244) // (CAN0_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFF80258) // (CAN0_MB2) MailBox Data High Register +#define AT91C_CAN0_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFF80250) // (CAN0_MB2) MailBox Status Register +#define AT91C_CAN0_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFF80254) // (CAN0_MB2) MailBox Data Low Register +// ========== Register definition for CAN0_MB3 peripheral ========== +#define AT91C_CAN0_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFF80260) // (CAN0_MB3) MailBox Mode Register +#define AT91C_CAN0_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFF8027C) // (CAN0_MB3) MailBox Control Register +#define AT91C_CAN0_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFF80278) // (CAN0_MB3) MailBox Data High Register +#define AT91C_CAN0_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFF80274) // (CAN0_MB3) MailBox Data Low Register +#define AT91C_CAN0_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFF80264) // (CAN0_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFF80270) // (CAN0_MB3) MailBox Status Register +#define AT91C_CAN0_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFF8026C) // (CAN0_MB3) MailBox Family ID Register +#define AT91C_CAN0_MB3_MID (AT91_CAST(AT91_REG *) 0xFFF80268) // (CAN0_MB3) MailBox ID Register +// ========== Register definition for CAN0_MB4 peripheral ========== +#define AT91C_CAN0_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFF8028C) // (CAN0_MB4) MailBox Family ID Register +#define AT91C_CAN0_MB4_MID (AT91_CAST(AT91_REG *) 0xFFF80288) // (CAN0_MB4) MailBox ID Register +#define AT91C_CAN0_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFF80298) // (CAN0_MB4) MailBox Data High Register +#define AT91C_CAN0_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFF80294) // (CAN0_MB4) MailBox Data Low Register +#define AT91C_CAN0_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFF80284) // (CAN0_MB4) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFF8029C) // (CAN0_MB4) MailBox Control Register +#define AT91C_CAN0_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFF80290) // (CAN0_MB4) MailBox Status Register +#define AT91C_CAN0_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFF80280) // (CAN0_MB4) MailBox Mode Register +// ========== Register definition for CAN0_MB5 peripheral ========== +#define AT91C_CAN0_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFF802B0) // (CAN0_MB5) MailBox Status Register +#define AT91C_CAN0_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFF802AC) // (CAN0_MB5) MailBox Family ID Register +#define AT91C_CAN0_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFF802A4) // (CAN0_MB5) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFF802B4) // (CAN0_MB5) MailBox Data Low Register +#define AT91C_CAN0_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFF802B8) // (CAN0_MB5) MailBox Data High Register +#define AT91C_CAN0_MB5_MID (AT91_CAST(AT91_REG *) 0xFFF802A8) // (CAN0_MB5) MailBox ID Register +#define AT91C_CAN0_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFF802A0) // (CAN0_MB5) MailBox Mode Register +#define AT91C_CAN0_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFF802BC) // (CAN0_MB5) MailBox Control Register +// ========== Register definition for CAN0_MB6 peripheral ========== +#define AT91C_CAN0_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFF802C4) // (CAN0_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB6_MID (AT91_CAST(AT91_REG *) 0xFFF802C8) // (CAN0_MB6) MailBox ID Register +#define AT91C_CAN0_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFF802D4) // (CAN0_MB6) MailBox Data Low Register +#define AT91C_CAN0_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFF802D8) // (CAN0_MB6) MailBox Data High Register +#define AT91C_CAN0_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFF802DC) // (CAN0_MB6) MailBox Control Register +#define AT91C_CAN0_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFF802C0) // (CAN0_MB6) MailBox Mode Register +#define AT91C_CAN0_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFF802CC) // (CAN0_MB6) MailBox Family ID Register +#define AT91C_CAN0_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFF802D0) // (CAN0_MB6) MailBox Status Register +// ========== Register definition for CAN0_MB7 peripheral ========== +#define AT91C_CAN0_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFF802F0) // (CAN0_MB7) MailBox Status Register +#define AT91C_CAN0_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFF802E0) // (CAN0_MB7) MailBox Mode Register +#define AT91C_CAN0_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFF802FC) // (CAN0_MB7) MailBox Control Register +#define AT91C_CAN0_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFF802F4) // (CAN0_MB7) MailBox Data Low Register +#define AT91C_CAN0_MB7_MID (AT91_CAST(AT91_REG *) 0xFFF802E8) // (CAN0_MB7) MailBox ID Register +#define AT91C_CAN0_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFF802F8) // (CAN0_MB7) MailBox Data High Register +#define AT91C_CAN0_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFF802EC) // (CAN0_MB7) MailBox Family ID Register +#define AT91C_CAN0_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFF802E4) // (CAN0_MB7) MailBox Acceptance Mask Register +// ========== Register definition for CAN0_MB8 peripheral ========== +#define AT91C_CAN0_MB8_MAM (AT91_CAST(AT91_REG *) 0xFFF80304) // (CAN0_MB8) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB8_MCR (AT91_CAST(AT91_REG *) 0xFFF8031C) // (CAN0_MB8) MailBox Control Register +#define AT91C_CAN0_MB8_MSR (AT91_CAST(AT91_REG *) 0xFFF80310) // (CAN0_MB8) MailBox Status Register +#define AT91C_CAN0_MB8_MID (AT91_CAST(AT91_REG *) 0xFFF80308) // (CAN0_MB8) MailBox ID Register +#define AT91C_CAN0_MB8_MDH (AT91_CAST(AT91_REG *) 0xFFF80318) // (CAN0_MB8) MailBox Data High Register +#define AT91C_CAN0_MB8_MFID (AT91_CAST(AT91_REG *) 0xFFF8030C) // (CAN0_MB8) MailBox Family ID Register +#define AT91C_CAN0_MB8_MMR (AT91_CAST(AT91_REG *) 0xFFF80300) // (CAN0_MB8) MailBox Mode Register +#define AT91C_CAN0_MB8_MDL (AT91_CAST(AT91_REG *) 0xFFF80314) // (CAN0_MB8) MailBox Data Low Register +// ========== Register definition for CAN0_MB9 peripheral ========== +#define AT91C_CAN0_MB9_MMR (AT91_CAST(AT91_REG *) 0xFFF80320) // (CAN0_MB9) MailBox Mode Register +#define AT91C_CAN0_MB9_MDH (AT91_CAST(AT91_REG *) 0xFFF80338) // (CAN0_MB9) MailBox Data High Register +#define AT91C_CAN0_MB9_MSR (AT91_CAST(AT91_REG *) 0xFFF80330) // (CAN0_MB9) MailBox Status Register +#define AT91C_CAN0_MB9_MDL (AT91_CAST(AT91_REG *) 0xFFF80334) // (CAN0_MB9) MailBox Data Low Register +#define AT91C_CAN0_MB9_MID (AT91_CAST(AT91_REG *) 0xFFF80328) // (CAN0_MB9) MailBox ID Register +#define AT91C_CAN0_MB9_MFID (AT91_CAST(AT91_REG *) 0xFFF8032C) // (CAN0_MB9) MailBox Family ID Register +#define AT91C_CAN0_MB9_MCR (AT91_CAST(AT91_REG *) 0xFFF8033C) // (CAN0_MB9) MailBox Control Register +#define AT91C_CAN0_MB9_MAM (AT91_CAST(AT91_REG *) 0xFFF80324) // (CAN0_MB9) MailBox Acceptance Mask Register +// ========== Register definition for CAN0_MB10 peripheral ========== +#define AT91C_CAN0_MB10_MCR (AT91_CAST(AT91_REG *) 0xFFF8035C) // (CAN0_MB10) MailBox Control Register +#define AT91C_CAN0_MB10_MID (AT91_CAST(AT91_REG *) 0xFFF80348) // (CAN0_MB10) MailBox ID Register +#define AT91C_CAN0_MB10_MAM (AT91_CAST(AT91_REG *) 0xFFF80344) // (CAN0_MB10) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB10_MFID (AT91_CAST(AT91_REG *) 0xFFF8034C) // (CAN0_MB10) MailBox Family ID Register +#define AT91C_CAN0_MB10_MDL (AT91_CAST(AT91_REG *) 0xFFF80354) // (CAN0_MB10) MailBox Data Low Register +#define AT91C_CAN0_MB10_MMR (AT91_CAST(AT91_REG *) 0xFFF80340) // (CAN0_MB10) MailBox Mode Register +#define AT91C_CAN0_MB10_MDH (AT91_CAST(AT91_REG *) 0xFFF80358) // (CAN0_MB10) MailBox Data High Register +#define AT91C_CAN0_MB10_MSR (AT91_CAST(AT91_REG *) 0xFFF80350) // (CAN0_MB10) MailBox Status Register +// ========== Register definition for CAN0_MB11 peripheral ========== +#define AT91C_CAN0_MB11_MCR (AT91_CAST(AT91_REG *) 0xFFF8037C) // (CAN0_MB11) MailBox Control Register +#define AT91C_CAN0_MB11_MFID (AT91_CAST(AT91_REG *) 0xFFF8036C) // (CAN0_MB11) MailBox Family ID Register +#define AT91C_CAN0_MB11_MDH (AT91_CAST(AT91_REG *) 0xFFF80378) // (CAN0_MB11) MailBox Data High Register +#define AT91C_CAN0_MB11_MAM (AT91_CAST(AT91_REG *) 0xFFF80364) // (CAN0_MB11) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB11_MID (AT91_CAST(AT91_REG *) 0xFFF80368) // (CAN0_MB11) MailBox ID Register +#define AT91C_CAN0_MB11_MMR (AT91_CAST(AT91_REG *) 0xFFF80360) // (CAN0_MB11) MailBox Mode Register +#define AT91C_CAN0_MB11_MSR (AT91_CAST(AT91_REG *) 0xFFF80370) // (CAN0_MB11) MailBox Status Register +#define AT91C_CAN0_MB11_MDL (AT91_CAST(AT91_REG *) 0xFFF80374) // (CAN0_MB11) MailBox Data Low Register +// ========== Register definition for CAN0_MB12 peripheral ========== +#define AT91C_CAN0_MB12_MCR (AT91_CAST(AT91_REG *) 0xFFF8039C) // (CAN0_MB12) MailBox Control Register +#define AT91C_CAN0_MB12_MID (AT91_CAST(AT91_REG *) 0xFFF80388) // (CAN0_MB12) MailBox ID Register +#define AT91C_CAN0_MB12_MDH (AT91_CAST(AT91_REG *) 0xFFF80398) // (CAN0_MB12) MailBox Data High Register +#define AT91C_CAN0_MB12_MAM (AT91_CAST(AT91_REG *) 0xFFF80384) // (CAN0_MB12) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB12_MFID (AT91_CAST(AT91_REG *) 0xFFF8038C) // (CAN0_MB12) MailBox Family ID Register +#define AT91C_CAN0_MB12_MDL (AT91_CAST(AT91_REG *) 0xFFF80394) // (CAN0_MB12) MailBox Data Low Register +#define AT91C_CAN0_MB12_MMR (AT91_CAST(AT91_REG *) 0xFFF80380) // (CAN0_MB12) MailBox Mode Register +#define AT91C_CAN0_MB12_MSR (AT91_CAST(AT91_REG *) 0xFFF80390) // (CAN0_MB12) MailBox Status Register +// ========== Register definition for CAN0_MB13 peripheral ========== +#define AT91C_CAN0_MB13_MCR (AT91_CAST(AT91_REG *) 0xFFF803BC) // (CAN0_MB13) MailBox Control Register +#define AT91C_CAN0_MB13_MDL (AT91_CAST(AT91_REG *) 0xFFF803B4) // (CAN0_MB13) MailBox Data Low Register +#define AT91C_CAN0_MB13_MAM (AT91_CAST(AT91_REG *) 0xFFF803A4) // (CAN0_MB13) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB13_MFID (AT91_CAST(AT91_REG *) 0xFFF803AC) // (CAN0_MB13) MailBox Family ID Register +#define AT91C_CAN0_MB13_MDH (AT91_CAST(AT91_REG *) 0xFFF803B8) // (CAN0_MB13) MailBox Data High Register +#define AT91C_CAN0_MB13_MID (AT91_CAST(AT91_REG *) 0xFFF803A8) // (CAN0_MB13) MailBox ID Register +#define AT91C_CAN0_MB13_MSR (AT91_CAST(AT91_REG *) 0xFFF803B0) // (CAN0_MB13) MailBox Status Register +#define AT91C_CAN0_MB13_MMR (AT91_CAST(AT91_REG *) 0xFFF803A0) // (CAN0_MB13) MailBox Mode Register +// ========== Register definition for CAN0_MB14 peripheral ========== +#define AT91C_CAN0_MB14_MSR (AT91_CAST(AT91_REG *) 0xFFF803D0) // (CAN0_MB14) MailBox Status Register +#define AT91C_CAN0_MB14_MMR (AT91_CAST(AT91_REG *) 0xFFF803C0) // (CAN0_MB14) MailBox Mode Register +#define AT91C_CAN0_MB14_MDL (AT91_CAST(AT91_REG *) 0xFFF803D4) // (CAN0_MB14) MailBox Data Low Register +#define AT91C_CAN0_MB14_MDH (AT91_CAST(AT91_REG *) 0xFFF803D8) // (CAN0_MB14) MailBox Data High Register +#define AT91C_CAN0_MB14_MID (AT91_CAST(AT91_REG *) 0xFFF803C8) // (CAN0_MB14) MailBox ID Register +#define AT91C_CAN0_MB14_MCR (AT91_CAST(AT91_REG *) 0xFFF803DC) // (CAN0_MB14) MailBox Control Register +#define AT91C_CAN0_MB14_MFID (AT91_CAST(AT91_REG *) 0xFFF803CC) // (CAN0_MB14) MailBox Family ID Register +#define AT91C_CAN0_MB14_MAM (AT91_CAST(AT91_REG *) 0xFFF803C4) // (CAN0_MB14) MailBox Acceptance Mask Register +// ========== Register definition for CAN0_MB15 peripheral ========== +#define AT91C_CAN0_MB15_MDH (AT91_CAST(AT91_REG *) 0xFFF803F8) // (CAN0_MB15) MailBox Data High Register +#define AT91C_CAN0_MB15_MMR (AT91_CAST(AT91_REG *) 0xFFF803E0) // (CAN0_MB15) MailBox Mode Register +#define AT91C_CAN0_MB15_MCR (AT91_CAST(AT91_REG *) 0xFFF803FC) // (CAN0_MB15) MailBox Control Register +#define AT91C_CAN0_MB15_MAM (AT91_CAST(AT91_REG *) 0xFFF803E4) // (CAN0_MB15) MailBox Acceptance Mask Register +#define AT91C_CAN0_MB15_MID (AT91_CAST(AT91_REG *) 0xFFF803E8) // (CAN0_MB15) MailBox ID Register +#define AT91C_CAN0_MB15_MFID (AT91_CAST(AT91_REG *) 0xFFF803EC) // (CAN0_MB15) MailBox Family ID Register +#define AT91C_CAN0_MB15_MSR (AT91_CAST(AT91_REG *) 0xFFF803F0) // (CAN0_MB15) MailBox Status Register +#define AT91C_CAN0_MB15_MDL (AT91_CAST(AT91_REG *) 0xFFF803F4) // (CAN0_MB15) MailBox Data Low Register +// ========== Register definition for CAN0 peripheral ========== +#define AT91C_CAN0_BR (AT91_CAST(AT91_REG *) 0xFFF80014) // (CAN0) Baudrate Register +#define AT91C_CAN0_TIMESTP (AT91_CAST(AT91_REG *) 0xFFF8001C) // (CAN0) Time Stamp Register +#define AT91C_CAN0_IER (AT91_CAST(AT91_REG *) 0xFFF80004) // (CAN0) Interrupt Enable Register +#define AT91C_CAN0_MR (AT91_CAST(AT91_REG *) 0xFFF80000) // (CAN0) Mode Register +#define AT91C_CAN0_TCR (AT91_CAST(AT91_REG *) 0xFFF80024) // (CAN0) Transfer Command Register +#define AT91C_CAN0_ACR (AT91_CAST(AT91_REG *) 0xFFF80028) // (CAN0) Abort Command Register +#define AT91C_CAN0_IDR (AT91_CAST(AT91_REG *) 0xFFF80008) // (CAN0) Interrupt Disable Register +#define AT91C_CAN0_IMR (AT91_CAST(AT91_REG *) 0xFFF8000C) // (CAN0) Interrupt Mask Register +#define AT91C_CAN0_TIM (AT91_CAST(AT91_REG *) 0xFFF80018) // (CAN0) Timer Register +#define AT91C_CAN0_VR (AT91_CAST(AT91_REG *) 0xFFF800FC) // (CAN0) Version Register +#define AT91C_CAN0_ECR (AT91_CAST(AT91_REG *) 0xFFF80020) // (CAN0) Error Counter Register +#define AT91C_CAN0_SR (AT91_CAST(AT91_REG *) 0xFFF80010) // (CAN0) Status Register +// ========== Register definition for CAN1_MB0 peripheral ========== +#define AT91C_CAN1_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFF8420C) // (CAN1_MB0) MailBox Family ID Register +#define AT91C_CAN1_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFF84214) // (CAN1_MB0) MailBox Data Low Register +#define AT91C_CAN1_MB0_MID (AT91_CAST(AT91_REG *) 0xFFF84208) // (CAN1_MB0) MailBox ID Register +#define AT91C_CAN1_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFF84200) // (CAN1_MB0) MailBox Mode Register +#define AT91C_CAN1_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFF84204) // (CAN1_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFF84210) // (CAN1_MB0) MailBox Status Register +#define AT91C_CAN1_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFF84218) // (CAN1_MB0) MailBox Data High Register +#define AT91C_CAN1_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFF8421C) // (CAN1_MB0) MailBox Control Register +// ========== Register definition for CAN1_MB1 peripheral ========== +#define AT91C_CAN1_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFF8422C) // (CAN1_MB1) MailBox Family ID Register +#define AT91C_CAN1_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFF84230) // (CAN1_MB1) MailBox Status Register +#define AT91C_CAN1_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFF84220) // (CAN1_MB1) MailBox Mode Register +#define AT91C_CAN1_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFF84238) // (CAN1_MB1) MailBox Data High Register +#define AT91C_CAN1_MB1_MID (AT91_CAST(AT91_REG *) 0xFFF84228) // (CAN1_MB1) MailBox ID Register +#define AT91C_CAN1_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFF84234) // (CAN1_MB1) MailBox Data Low Register +#define AT91C_CAN1_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFF8423C) // (CAN1_MB1) MailBox Control Register +#define AT91C_CAN1_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFF84224) // (CAN1_MB1) MailBox Acceptance Mask Register +// ========== Register definition for CAN1_MB2 peripheral ========== +#define AT91C_CAN1_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFF84250) // (CAN1_MB2) MailBox Status Register +#define AT91C_CAN1_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFF84240) // (CAN1_MB2) MailBox Mode Register +#define AT91C_CAN1_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFF84244) // (CAN1_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB2_MID (AT91_CAST(AT91_REG *) 0xFFF84248) // (CAN1_MB2) MailBox ID Register +#define AT91C_CAN1_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFF8424C) // (CAN1_MB2) MailBox Family ID Register +#define AT91C_CAN1_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFF84254) // (CAN1_MB2) MailBox Data Low Register +#define AT91C_CAN1_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFF84258) // (CAN1_MB2) MailBox Data High Register +#define AT91C_CAN1_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFF8425C) // (CAN1_MB2) MailBox Control Register +// ========== Register definition for CAN1_MB3 peripheral ========== +#define AT91C_CAN1_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFF8427C) // (CAN1_MB3) MailBox Control Register +#define AT91C_CAN1_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFF84278) // (CAN1_MB3) MailBox Data High Register +#define AT91C_CAN1_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFF84264) // (CAN1_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFF84274) // (CAN1_MB3) MailBox Data Low Register +#define AT91C_CAN1_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFF84260) // (CAN1_MB3) MailBox Mode Register +#define AT91C_CAN1_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFF84270) // (CAN1_MB3) MailBox Status Register +#define AT91C_CAN1_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFF8426C) // (CAN1_MB3) MailBox Family ID Register +#define AT91C_CAN1_MB3_MID (AT91_CAST(AT91_REG *) 0xFFF84268) // (CAN1_MB3) MailBox ID Register +// ========== Register definition for CAN1_MB4 peripheral ========== +#define AT91C_CAN1_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFF8429C) // (CAN1_MB4) MailBox Control Register +#define AT91C_CAN1_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFF84298) // (CAN1_MB4) MailBox Data High Register +#define AT91C_CAN1_MB4_MID (AT91_CAST(AT91_REG *) 0xFFF84288) // (CAN1_MB4) MailBox ID Register +#define AT91C_CAN1_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFF84294) // (CAN1_MB4) MailBox Data Low Register +#define AT91C_CAN1_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFF8428C) // (CAN1_MB4) MailBox Family ID Register +#define AT91C_CAN1_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFF84284) // (CAN1_MB4) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFF84290) // (CAN1_MB4) MailBox Status Register +#define AT91C_CAN1_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFF84280) // (CAN1_MB4) MailBox Mode Register +// ========== Register definition for CAN1_MB5 peripheral ========== +#define AT91C_CAN1_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFF842BC) // (CAN1_MB5) MailBox Control Register +#define AT91C_CAN1_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFF842B0) // (CAN1_MB5) MailBox Status Register +#define AT91C_CAN1_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFF842A0) // (CAN1_MB5) MailBox Mode Register +#define AT91C_CAN1_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFF842B4) // (CAN1_MB5) MailBox Data Low Register +#define AT91C_CAN1_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFF842A4) // (CAN1_MB5) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB5_MID (AT91_CAST(AT91_REG *) 0xFFF842A8) // (CAN1_MB5) MailBox ID Register +#define AT91C_CAN1_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFF842B8) // (CAN1_MB5) MailBox Data High Register +#define AT91C_CAN1_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFF842AC) // (CAN1_MB5) MailBox Family ID Register +// ========== Register definition for CAN1_MB6 peripheral ========== +#define AT91C_CAN1_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFF842D8) // (CAN1_MB6) MailBox Data High Register +#define AT91C_CAN1_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFF842D4) // (CAN1_MB6) MailBox Data Low Register +#define AT91C_CAN1_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFF842C4) // (CAN1_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFF842DC) // (CAN1_MB6) MailBox Control Register +#define AT91C_CAN1_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFF842C0) // (CAN1_MB6) MailBox Mode Register +#define AT91C_CAN1_MB6_MID (AT91_CAST(AT91_REG *) 0xFFF842C8) // (CAN1_MB6) MailBox ID Register +#define AT91C_CAN1_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFF842D0) // (CAN1_MB6) MailBox Status Register +#define AT91C_CAN1_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFF842CC) // (CAN1_MB6) MailBox Family ID Register +// ========== Register definition for CAN1_MB7 peripheral ========== +#define AT91C_CAN1_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFF842F8) // (CAN1_MB7) MailBox Data High Register +#define AT91C_CAN1_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFF842F4) // (CAN1_MB7) MailBox Data Low Register +#define AT91C_CAN1_MB7_MID (AT91_CAST(AT91_REG *) 0xFFF842E8) // (CAN1_MB7) MailBox ID Register +#define AT91C_CAN1_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFF842F0) // (CAN1_MB7) MailBox Status Register +#define AT91C_CAN1_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFF842EC) // (CAN1_MB7) MailBox Family ID Register +#define AT91C_CAN1_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFF842E4) // (CAN1_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFF842E0) // (CAN1_MB7) MailBox Mode Register +#define AT91C_CAN1_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFF842FC) // (CAN1_MB7) MailBox Control Register +// ========== Register definition for CAN1_MB8 peripheral ========== +#define AT91C_CAN1_MB8_MCR (AT91_CAST(AT91_REG *) 0xFFF8431C) // (CAN1_MB8) MailBox Control Register +#define AT91C_CAN1_MB8_MFID (AT91_CAST(AT91_REG *) 0xFFF8430C) // (CAN1_MB8) MailBox Family ID Register +#define AT91C_CAN1_MB8_MSR (AT91_CAST(AT91_REG *) 0xFFF84310) // (CAN1_MB8) MailBox Status Register +#define AT91C_CAN1_MB8_MAM (AT91_CAST(AT91_REG *) 0xFFF84304) // (CAN1_MB8) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB8_MDL (AT91_CAST(AT91_REG *) 0xFFF84314) // (CAN1_MB8) MailBox Data Low Register +#define AT91C_CAN1_MB8_MID (AT91_CAST(AT91_REG *) 0xFFF84308) // (CAN1_MB8) MailBox ID Register +#define AT91C_CAN1_MB8_MDH (AT91_CAST(AT91_REG *) 0xFFF84318) // (CAN1_MB8) MailBox Data High Register +#define AT91C_CAN1_MB8_MMR (AT91_CAST(AT91_REG *) 0xFFF84300) // (CAN1_MB8) MailBox Mode Register +// ========== Register definition for CAN1_MB9 peripheral ========== +#define AT91C_CAN1_MB9_MDH (AT91_CAST(AT91_REG *) 0xFFF84338) // (CAN1_MB9) MailBox Data High Register +#define AT91C_CAN1_MB9_MDL (AT91_CAST(AT91_REG *) 0xFFF84334) // (CAN1_MB9) MailBox Data Low Register +#define AT91C_CAN1_MB9_MFID (AT91_CAST(AT91_REG *) 0xFFF8432C) // (CAN1_MB9) MailBox Family ID Register +#define AT91C_CAN1_MB9_MMR (AT91_CAST(AT91_REG *) 0xFFF84320) // (CAN1_MB9) MailBox Mode Register +#define AT91C_CAN1_MB9_MAM (AT91_CAST(AT91_REG *) 0xFFF84324) // (CAN1_MB9) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB9_MID (AT91_CAST(AT91_REG *) 0xFFF84328) // (CAN1_MB9) MailBox ID Register +#define AT91C_CAN1_MB9_MCR (AT91_CAST(AT91_REG *) 0xFFF8433C) // (CAN1_MB9) MailBox Control Register +#define AT91C_CAN1_MB9_MSR (AT91_CAST(AT91_REG *) 0xFFF84330) // (CAN1_MB9) MailBox Status Register +// ========== Register definition for CAN1_MB10 peripheral ========== +#define AT91C_CAN1_MB10_MFID (AT91_CAST(AT91_REG *) 0xFFF8434C) // (CAN1_MB10) MailBox Family ID Register +#define AT91C_CAN1_MB10_MSR (AT91_CAST(AT91_REG *) 0xFFF84350) // (CAN1_MB10) MailBox Status Register +#define AT91C_CAN1_MB10_MDL (AT91_CAST(AT91_REG *) 0xFFF84354) // (CAN1_MB10) MailBox Data Low Register +#define AT91C_CAN1_MB10_MMR (AT91_CAST(AT91_REG *) 0xFFF84340) // (CAN1_MB10) MailBox Mode Register +#define AT91C_CAN1_MB10_MCR (AT91_CAST(AT91_REG *) 0xFFF8435C) // (CAN1_MB10) MailBox Control Register +#define AT91C_CAN1_MB10_MAM (AT91_CAST(AT91_REG *) 0xFFF84344) // (CAN1_MB10) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB10_MID (AT91_CAST(AT91_REG *) 0xFFF84348) // (CAN1_MB10) MailBox ID Register +#define AT91C_CAN1_MB10_MDH (AT91_CAST(AT91_REG *) 0xFFF84358) // (CAN1_MB10) MailBox Data High Register +// ========== Register definition for CAN1_MB11 peripheral ========== +#define AT91C_CAN1_MB11_MMR (AT91_CAST(AT91_REG *) 0xFFF84360) // (CAN1_MB11) MailBox Mode Register +#define AT91C_CAN1_MB11_MDL (AT91_CAST(AT91_REG *) 0xFFF84374) // (CAN1_MB11) MailBox Data Low Register +#define AT91C_CAN1_MB11_MAM (AT91_CAST(AT91_REG *) 0xFFF84364) // (CAN1_MB11) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB11_MID (AT91_CAST(AT91_REG *) 0xFFF84368) // (CAN1_MB11) MailBox ID Register +#define AT91C_CAN1_MB11_MCR (AT91_CAST(AT91_REG *) 0xFFF8437C) // (CAN1_MB11) MailBox Control Register +#define AT91C_CAN1_MB11_MDH (AT91_CAST(AT91_REG *) 0xFFF84378) // (CAN1_MB11) MailBox Data High Register +#define AT91C_CAN1_MB11_MSR (AT91_CAST(AT91_REG *) 0xFFF84370) // (CAN1_MB11) MailBox Status Register +#define AT91C_CAN1_MB11_MFID (AT91_CAST(AT91_REG *) 0xFFF8436C) // (CAN1_MB11) MailBox Family ID Register +// ========== Register definition for CAN1_MB12 peripheral ========== +#define AT91C_CAN1_MB12_MFID (AT91_CAST(AT91_REG *) 0xFFF8438C) // (CAN1_MB12) MailBox Family ID Register +#define AT91C_CAN1_MB12_MAM (AT91_CAST(AT91_REG *) 0xFFF84384) // (CAN1_MB12) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB12_MDH (AT91_CAST(AT91_REG *) 0xFFF84398) // (CAN1_MB12) MailBox Data High Register +#define AT91C_CAN1_MB12_MMR (AT91_CAST(AT91_REG *) 0xFFF84380) // (CAN1_MB12) MailBox Mode Register +#define AT91C_CAN1_MB12_MID (AT91_CAST(AT91_REG *) 0xFFF84388) // (CAN1_MB12) MailBox ID Register +#define AT91C_CAN1_MB12_MCR (AT91_CAST(AT91_REG *) 0xFFF8439C) // (CAN1_MB12) MailBox Control Register +#define AT91C_CAN1_MB12_MDL (AT91_CAST(AT91_REG *) 0xFFF84394) // (CAN1_MB12) MailBox Data Low Register +#define AT91C_CAN1_MB12_MSR (AT91_CAST(AT91_REG *) 0xFFF84390) // (CAN1_MB12) MailBox Status Register +// ========== Register definition for CAN1_MB13 peripheral ========== +#define AT91C_CAN1_MB13_MDL (AT91_CAST(AT91_REG *) 0xFFF843B4) // (CAN1_MB13) MailBox Data Low Register +#define AT91C_CAN1_MB13_MSR (AT91_CAST(AT91_REG *) 0xFFF843B0) // (CAN1_MB13) MailBox Status Register +#define AT91C_CAN1_MB13_MFID (AT91_CAST(AT91_REG *) 0xFFF843AC) // (CAN1_MB13) MailBox Family ID Register +#define AT91C_CAN1_MB13_MAM (AT91_CAST(AT91_REG *) 0xFFF843A4) // (CAN1_MB13) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB13_MMR (AT91_CAST(AT91_REG *) 0xFFF843A0) // (CAN1_MB13) MailBox Mode Register +#define AT91C_CAN1_MB13_MCR (AT91_CAST(AT91_REG *) 0xFFF843BC) // (CAN1_MB13) MailBox Control Register +#define AT91C_CAN1_MB13_MDH (AT91_CAST(AT91_REG *) 0xFFF843B8) // (CAN1_MB13) MailBox Data High Register +#define AT91C_CAN1_MB13_MID (AT91_CAST(AT91_REG *) 0xFFF843A8) // (CAN1_MB13) MailBox ID Register +// ========== Register definition for CAN1_MB14 peripheral ========== +#define AT91C_CAN1_MB14_MCR (AT91_CAST(AT91_REG *) 0xFFF843DC) // (CAN1_MB14) MailBox Control Register +#define AT91C_CAN1_MB14_MID (AT91_CAST(AT91_REG *) 0xFFF843C8) // (CAN1_MB14) MailBox ID Register +#define AT91C_CAN1_MB14_MMR (AT91_CAST(AT91_REG *) 0xFFF843C0) // (CAN1_MB14) MailBox Mode Register +#define AT91C_CAN1_MB14_MDH (AT91_CAST(AT91_REG *) 0xFFF843D8) // (CAN1_MB14) MailBox Data High Register +#define AT91C_CAN1_MB14_MSR (AT91_CAST(AT91_REG *) 0xFFF843D0) // (CAN1_MB14) MailBox Status Register +#define AT91C_CAN1_MB14_MFID (AT91_CAST(AT91_REG *) 0xFFF843CC) // (CAN1_MB14) MailBox Family ID Register +#define AT91C_CAN1_MB14_MDL (AT91_CAST(AT91_REG *) 0xFFF843D4) // (CAN1_MB14) MailBox Data Low Register +#define AT91C_CAN1_MB14_MAM (AT91_CAST(AT91_REG *) 0xFFF843C4) // (CAN1_MB14) MailBox Acceptance Mask Register +// ========== Register definition for CAN1_MB15 peripheral ========== +#define AT91C_CAN1_MB15_MSR (AT91_CAST(AT91_REG *) 0xFFF843F0) // (CAN1_MB15) MailBox Status Register +#define AT91C_CAN1_MB15_MDL (AT91_CAST(AT91_REG *) 0xFFF843F4) // (CAN1_MB15) MailBox Data Low Register +#define AT91C_CAN1_MB15_MDH (AT91_CAST(AT91_REG *) 0xFFF843F8) // (CAN1_MB15) MailBox Data High Register +#define AT91C_CAN1_MB15_MMR (AT91_CAST(AT91_REG *) 0xFFF843E0) // (CAN1_MB15) MailBox Mode Register +#define AT91C_CAN1_MB15_MAM (AT91_CAST(AT91_REG *) 0xFFF843E4) // (CAN1_MB15) MailBox Acceptance Mask Register +#define AT91C_CAN1_MB15_MFID (AT91_CAST(AT91_REG *) 0xFFF843EC) // (CAN1_MB15) MailBox Family ID Register +#define AT91C_CAN1_MB15_MCR (AT91_CAST(AT91_REG *) 0xFFF843FC) // (CAN1_MB15) MailBox Control Register +#define AT91C_CAN1_MB15_MID (AT91_CAST(AT91_REG *) 0xFFF843E8) // (CAN1_MB15) MailBox ID Register +// ========== Register definition for CAN1 peripheral ========== +#define AT91C_CAN1_ECR (AT91_CAST(AT91_REG *) 0xFFF84020) // (CAN1) Error Counter Register +#define AT91C_CAN1_BR (AT91_CAST(AT91_REG *) 0xFFF84014) // (CAN1) Baudrate Register +#define AT91C_CAN1_IDR (AT91_CAST(AT91_REG *) 0xFFF84008) // (CAN1) Interrupt Disable Register +#define AT91C_CAN1_ACR (AT91_CAST(AT91_REG *) 0xFFF84028) // (CAN1) Abort Command Register +#define AT91C_CAN1_IMR (AT91_CAST(AT91_REG *) 0xFFF8400C) // (CAN1) Interrupt Mask Register +#define AT91C_CAN1_TCR (AT91_CAST(AT91_REG *) 0xFFF84024) // (CAN1) Transfer Command Register +#define AT91C_CAN1_SR (AT91_CAST(AT91_REG *) 0xFFF84010) // (CAN1) Status Register +#define AT91C_CAN1_TIM (AT91_CAST(AT91_REG *) 0xFFF84018) // (CAN1) Timer Register +#define AT91C_CAN1_VR (AT91_CAST(AT91_REG *) 0xFFF840FC) // (CAN1) Version Register +#define AT91C_CAN1_MR (AT91_CAST(AT91_REG *) 0xFFF84000) // (CAN1) Mode Register +#define AT91C_CAN1_IER (AT91_CAST(AT91_REG *) 0xFFF84004) // (CAN1) Interrupt Enable Register +#define AT91C_CAN1_TIMESTP (AT91_CAST(AT91_REG *) 0xFFF8401C) // (CAN1) Time Stamp Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register +#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register +#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFA4014) // (TC3) Register A +#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFA4018) // (TC3) Register B +#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFA4010) // (TC3) Counter Value +#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (TC3) Status Register +#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFA401C) // (TC3) Register C +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFA4060) // (TC4) Status Register +#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFA4054) // (TC4) Register A +#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFA4050) // (TC4) Counter Value +#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFA4058) // (TC4) Register B +#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register +#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFA405C) // (TC4) Register C +#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register +#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFA4098) // (TC5) Register B +#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFA4090) // (TC5) Counter Value +#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFA409C) // (TC5) Register C +#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFA40A0) // (TC5) Status Register +#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFA4094) // (TC5) Register A +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFA40C4) // (TCB1) TC Block Mode Register +#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFA40C0) // (TCB1) TC Block Control Register +// ========== Register definition for TC6 peripheral ========== +#define AT91C_TC6_IDR (AT91_CAST(AT91_REG *) 0xFFFA8028) // (TC6) Interrupt Disable Register +#define AT91C_TC6_RA (AT91_CAST(AT91_REG *) 0xFFFA8014) // (TC6) Register A +#define AT91C_TC6_IER (AT91_CAST(AT91_REG *) 0xFFFA8024) // (TC6) Interrupt Enable Register +#define AT91C_TC6_RB (AT91_CAST(AT91_REG *) 0xFFFA8018) // (TC6) Register B +#define AT91C_TC6_CMR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (TC6) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC6_CCR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (TC6) Channel Control Register +#define AT91C_TC6_CV (AT91_CAST(AT91_REG *) 0xFFFA8010) // (TC6) Counter Value +#define AT91C_TC6_RC (AT91_CAST(AT91_REG *) 0xFFFA801C) // (TC6) Register C +#define AT91C_TC6_IMR (AT91_CAST(AT91_REG *) 0xFFFA802C) // (TC6) Interrupt Mask Register +#define AT91C_TC6_SR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (TC6) Status Register +// ========== Register definition for TC7 peripheral ========== +#define AT91C_TC7_IMR (AT91_CAST(AT91_REG *) 0xFFFA806C) // (TC7) Interrupt Mask Register +#define AT91C_TC7_SR (AT91_CAST(AT91_REG *) 0xFFFA8060) // (TC7) Status Register +#define AT91C_TC7_IDR (AT91_CAST(AT91_REG *) 0xFFFA8068) // (TC7) Interrupt Disable Register +#define AT91C_TC7_CMR (AT91_CAST(AT91_REG *) 0xFFFA8044) // (TC7) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC7_CV (AT91_CAST(AT91_REG *) 0xFFFA8050) // (TC7) Counter Value +#define AT91C_TC7_RA (AT91_CAST(AT91_REG *) 0xFFFA8054) // (TC7) Register A +#define AT91C_TC7_RB (AT91_CAST(AT91_REG *) 0xFFFA8058) // (TC7) Register B +#define AT91C_TC7_RC (AT91_CAST(AT91_REG *) 0xFFFA805C) // (TC7) Register C +#define AT91C_TC7_CCR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (TC7) Channel Control Register +#define AT91C_TC7_IER (AT91_CAST(AT91_REG *) 0xFFFA8064) // (TC7) Interrupt Enable Register +// ========== Register definition for TC8 peripheral ========== +#define AT91C_TC8_RA (AT91_CAST(AT91_REG *) 0xFFFA8094) // (TC8) Register A +#define AT91C_TC8_IDR (AT91_CAST(AT91_REG *) 0xFFFA80A8) // (TC8) Interrupt Disable Register +#define AT91C_TC8_RC (AT91_CAST(AT91_REG *) 0xFFFA809C) // (TC8) Register C +#define AT91C_TC8_CCR (AT91_CAST(AT91_REG *) 0xFFFA8080) // (TC8) Channel Control Register +#define AT91C_TC8_SR (AT91_CAST(AT91_REG *) 0xFFFA80A0) // (TC8) Status Register +#define AT91C_TC8_RB (AT91_CAST(AT91_REG *) 0xFFFA8098) // (TC8) Register B +#define AT91C_TC8_IMR (AT91_CAST(AT91_REG *) 0xFFFA80AC) // (TC8) Interrupt Mask Register +#define AT91C_TC8_CMR (AT91_CAST(AT91_REG *) 0xFFFA8084) // (TC8) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC8_IER (AT91_CAST(AT91_REG *) 0xFFFA80A4) // (TC8) Interrupt Enable Register +#define AT91C_TC8_CV (AT91_CAST(AT91_REG *) 0xFFFA8090) // (TC8) Counter Value +// ========== Register definition for TCB2 peripheral ========== +#define AT91C_TCB2_BMR (AT91_CAST(AT91_REG *) 0xFFFA80C4) // (TCB2) TC Block Mode Register +#define AT91C_TCB2_BCR (AT91_CAST(AT91_REG *) 0xFFFA80C0) // (TCB2) TC Block Control Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_MCI) Receive Counter Register +#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_MCI) PDC Transfer Control Register +#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_MCI) Transmit Next Counter Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFAC048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFAC040) // (MCI) MCI Status Register +#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFAC014) // (MCI) MCI Command Register +#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFAC044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (MCI) MCI Argument Register +#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (MCI) MCI SD Card Register +#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFAC04C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (MCI) MCI Mode Register +#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (MCI) MCI Response Register +#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (MCI) MCI Control Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register +#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register +#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register +#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register +#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (US2) Control Register +#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register +#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register +#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register +#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (US2) Mode Register +#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register +#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register +#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH4 peripheral ========== +#define AT91C_PWMC_CH4_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC294) // (PWMC_CH4) Reserved +#define AT91C_PWMC_CH4_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC284) // (PWMC_CH4) Channel Duty Cycle Register +#define AT91C_PWMC_CH4_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC290) // (PWMC_CH4) Channel Update Register +#define AT91C_PWMC_CH4_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC28C) // (PWMC_CH4) Channel Counter Register +#define AT91C_PWMC_CH4_CMR (AT91_CAST(AT91_REG *) 0xFFFCC280) // (PWMC_CH4) Channel Mode Register +#define AT91C_PWMC_CH4_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC288) // (PWMC_CH4) Channel Period Register +// ========== Register definition for PWMC_CH5 peripheral ========== +#define AT91C_PWMC_CH5_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2B4) // (PWMC_CH5) Reserved +#define AT91C_PWMC_CH5_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2AC) // (PWMC_CH5) Channel Counter Register +#define AT91C_PWMC_CH5_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2A4) // (PWMC_CH5) Channel Duty Cycle Register +#define AT91C_PWMC_CH5_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2A8) // (PWMC_CH5) Channel Period Register +#define AT91C_PWMC_CH5_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2A0) // (PWMC_CH5) Channel Mode Register +#define AT91C_PWMC_CH5_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2B0) // (PWMC_CH5) Channel Update Register +// ========== Register definition for PWMC_CH6 peripheral ========== +#define AT91C_PWMC_CH6_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2CC) // (PWMC_CH6) Channel Counter Register +#define AT91C_PWMC_CH6_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2C0) // (PWMC_CH6) Channel Mode Register +#define AT91C_PWMC_CH6_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2C4) // (PWMC_CH6) Channel Duty Cycle Register +#define AT91C_PWMC_CH6_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2D4) // (PWMC_CH6) Reserved +#define AT91C_PWMC_CH6_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2C8) // (PWMC_CH6) Channel Period Register +#define AT91C_PWMC_CH6_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2D0) // (PWMC_CH6) Channel Update Register +// ========== Register definition for PWMC_CH7 peripheral ========== +#define AT91C_PWMC_CH7_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2EC) // (PWMC_CH7) Channel Counter Register +#define AT91C_PWMC_CH7_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2E4) // (PWMC_CH7) Channel Duty Cycle Register +#define AT91C_PWMC_CH7_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2E8) // (PWMC_CH7) Channel Period Register +#define AT91C_PWMC_CH7_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2F4) // (PWMC_CH7) Reserved +#define AT91C_PWMC_CH7_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2F0) // (PWMC_CH7) Channel Update Register +#define AT91C_PWMC_CH7_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2E0) // (PWMC_CH7) Channel Mode Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register +#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register +#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFD0040) // (SSC0) Status Register +#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (SSC0) Control Register +#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register +#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register +// ========== Register definition for PDC_SSC1 peripheral ========== +#define AT91C_SSC1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register +#define AT91C_SSC1_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register +#define AT91C_SSC1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register +#define AT91C_SSC1_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register +#define AT91C_SSC1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register +#define AT91C_SSC1_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register +#define AT91C_SSC1_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register +#define AT91C_SSC1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register +#define AT91C_SSC1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register +#define AT91C_SSC1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register +// ========== Register definition for SSC1 peripheral ========== +#define AT91C_SSC1_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register +#define AT91C_SSC1_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register +#define AT91C_SSC1_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register +#define AT91C_SSC1_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register +#define AT91C_SSC1_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register +#define AT91C_SSC1_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister +#define AT91C_SSC1_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register +#define AT91C_SSC1_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register +#define AT91C_SSC1_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC1) Status Register +#define AT91C_SSC1_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register +#define AT91C_SSC1_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register +#define AT91C_SSC1_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC1) Control Register +#define AT91C_SSC1_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register +#define AT91C_SSC1_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register +// ========== Register definition for PDC_ADC0 peripheral ========== +#define AT91C_ADC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC0) PDC Transfer Status Register +#define AT91C_ADC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC0) PDC Transfer Control Register +#define AT91C_ADC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC0) Transmit Next Pointer Register +#define AT91C_ADC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC0) Transmit Next Counter Register +#define AT91C_ADC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC0) Receive Next Pointer Register +#define AT91C_ADC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC0) Receive Next Counter Register +#define AT91C_ADC0_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC0) Receive Pointer Register +#define AT91C_ADC0_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC0) Transmit Counter Register +#define AT91C_ADC0_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC0) Transmit Pointer Register +#define AT91C_ADC0_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC0) Receive Counter Register +// ========== Register definition for ADC0 peripheral ========== +#define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC0) ADC Channel Data Register 2 +#define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC0) ADC Channel Data Register 3 +#define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC0) ADC Channel Data Register 0 +#define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC0) ADC Channel Data Register 5 +#define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC0) ADC Channel Disable Register +#define AT91C_ADC0_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC0) ADC Status Register +#define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC0) ADC Channel Data Register 4 +#define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC0) ADC Channel Data Register 1 +#define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC0) ADC Last Converted Data Register +#define AT91C_ADC0_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC0) ADC Interrupt Disable Register +#define AT91C_ADC0_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC0) ADC Control Register +#define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC0) ADC Channel Data Register 7 +#define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC0) ADC Channel Data Register 6 +#define AT91C_ADC0_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC0) ADC Interrupt Enable Register +#define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC0) ADC Channel Enable Register +#define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC0) ADC Channel Status Register +#define AT91C_ADC0_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC0) ADC Mode Register +#define AT91C_ADC0_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC0) ADC Interrupt Mask Register +// ========== Register definition for PDC_ADC1 peripheral ========== +#define AT91C_ADC1_RCR (AT91_CAST(AT91_REG *) 0xFFFDC104) // (PDC_ADC1) Receive Counter Register +#define AT91C_ADC1_TPR (AT91_CAST(AT91_REG *) 0xFFFDC108) // (PDC_ADC1) Transmit Pointer Register +#define AT91C_ADC1_TNPR (AT91_CAST(AT91_REG *) 0xFFFDC118) // (PDC_ADC1) Transmit Next Pointer Register +#define AT91C_ADC1_RNCR (AT91_CAST(AT91_REG *) 0xFFFDC114) // (PDC_ADC1) Receive Next Counter Register +#define AT91C_ADC1_PTSR (AT91_CAST(AT91_REG *) 0xFFFDC124) // (PDC_ADC1) PDC Transfer Status Register +#define AT91C_ADC1_PTCR (AT91_CAST(AT91_REG *) 0xFFFDC120) // (PDC_ADC1) PDC Transfer Control Register +#define AT91C_ADC1_RNPR (AT91_CAST(AT91_REG *) 0xFFFDC110) // (PDC_ADC1) Receive Next Pointer Register +#define AT91C_ADC1_TNCR (AT91_CAST(AT91_REG *) 0xFFFDC11C) // (PDC_ADC1) Transmit Next Counter Register +#define AT91C_ADC1_TCR (AT91_CAST(AT91_REG *) 0xFFFDC10C) // (PDC_ADC1) Transmit Counter Register +#define AT91C_ADC1_RPR (AT91_CAST(AT91_REG *) 0xFFFDC100) // (PDC_ADC1) Receive Pointer Register +// ========== Register definition for ADC1 peripheral ========== +#define AT91C_ADC1_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (ADC1) ADC Interrupt Enable Register +#define AT91C_ADC1_CHSR (AT91_CAST(AT91_REG *) 0xFFFDC018) // (ADC1) ADC Channel Status Register +#define AT91C_ADC1_MR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (ADC1) ADC Mode Register +#define AT91C_ADC1_CR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (ADC1) ADC Control Register +#define AT91C_ADC1_LCDR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (ADC1) ADC Last Converted Data Register +#define AT91C_ADC1_CHER (AT91_CAST(AT91_REG *) 0xFFFDC010) // (ADC1) ADC Channel Enable Register +#define AT91C_ADC1_CHDR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (ADC1) ADC Channel Disable Register +#define AT91C_ADC1_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (ADC1) ADC Interrupt Mask Register +#define AT91C_ADC1_CDR1 (AT91_CAST(AT91_REG *) 0xFFFDC034) // (ADC1) ADC Channel Data Register 1 +#define AT91C_ADC1_CDR4 (AT91_CAST(AT91_REG *) 0xFFFDC040) // (ADC1) ADC Channel Data Register 4 +#define AT91C_ADC1_CDR0 (AT91_CAST(AT91_REG *) 0xFFFDC030) // (ADC1) ADC Channel Data Register 0 +#define AT91C_ADC1_CDR5 (AT91_CAST(AT91_REG *) 0xFFFDC044) // (ADC1) ADC Channel Data Register 5 +#define AT91C_ADC1_CDR3 (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (ADC1) ADC Channel Data Register 3 +#define AT91C_ADC1_CDR6 (AT91_CAST(AT91_REG *) 0xFFFDC048) // (ADC1) ADC Channel Data Register 6 +#define AT91C_ADC1_SR (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (ADC1) ADC Status Register +#define AT91C_ADC1_CDR2 (AT91_CAST(AT91_REG *) 0xFFFDC038) // (ADC1) ADC Channel Data Register 2 +#define AT91C_ADC1_CDR7 (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (ADC1) ADC Channel Data Register 7 +#define AT91C_ADC1_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (ADC1) ADC Interrupt Disable Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7A3 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_TWD (AT91C_PIO_PA0) // TWI Two-wire Serial Data +#define AT91C_PA0_ADTRG0 (AT91C_PIO_PA0) // ADC0 External Trigger +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TWCK (AT91C_PIO_PA1) // TWI Two-wire Serial Clock +#define AT91C_PA1_ADTRG1 (AT91C_PIO_PA1) // ADC1 External Trigger +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TXD2 (AT91C_PIO_PA10) // USART 2 Transmit Data +#define AT91C_PA10_SPI1_SPCK (AT91C_PIO_PA10) // SPI1 Serial Clock +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_SPI0_NPCS0 (AT91C_PIO_PA11) // SPI0 Peripheral Chip Select 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS1 (AT91C_PIO_PA12) // SPI0 Peripheral Chip Select 1 +#define AT91C_PA12_MCDA1 (AT91C_PIO_PA12) // Multimedia Card A Data 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS2 (AT91C_PIO_PA13) // SPI0 Peripheral Chip Select 2 +#define AT91C_PA13_MCDA2 (AT91C_PIO_PA13) // Multimedia Card A Data 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS3 (AT91C_PIO_PA14) // SPI0 Peripheral Chip Select 3 +#define AT91C_PA14_MCDA3 (AT91C_PIO_PA14) // Multimedia Card A Data 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_MISO (AT91C_PIO_PA15) // SPI0 Master In Slave +#define AT91C_PA15_MCDA0 (AT91C_PIO_PA15) // Multimedia Card A Data 0 +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MOSI (AT91C_PIO_PA16) // SPI0 Master Out Slave +#define AT91C_PA16_MCCDA (AT91C_PIO_PA16) // Multimedia Card A Command +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_SPCK (AT91C_PIO_PA17) // SPI0 Serial Clock +#define AT91C_PA17_MCCK (AT91C_PIO_PA17) // Multimedia Card Clock +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_PWM0 (AT91C_PIO_PA18) // PWMC Channel 0 +#define AT91C_PA18_PCK0 (AT91C_PIO_PA18) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_PWM1 (AT91C_PIO_PA19) // PWMC Channel 1 +#define AT91C_PA19_PCK1 (AT91C_PIO_PA19) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_RXD0 (AT91C_PIO_PA2) // USART 0 Receive Data +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_PWM2 (AT91C_PIO_PA20) // PWMC Channel 2 +#define AT91C_PA20_PCK2 (AT91C_PIO_PA20) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_PWM3 (AT91C_PIO_PA21) // PWMC Channel 3 +#define AT91C_PA21_PCK3 (AT91C_PIO_PA21) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_PWM4 (AT91C_PIO_PA22) // PWMC Channel 4 +#define AT91C_PA22_IRQ0 (AT91C_PIO_PA22) // Interrupt input 0 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_PWM5 (AT91C_PIO_PA23) // PWMC Channel 5 +#define AT91C_PA23_IRQ1 (AT91C_PIO_PA23) // Interrupt input 1 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_PWM6 (AT91C_PIO_PA24) // PWMC Channel 6 +#define AT91C_PA24_TCLK4 (AT91C_PIO_PA24) // Timer Counter 4 external Clock Input +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_PWM7 (AT91C_PIO_PA25) // PWMC Channel 7 +#define AT91C_PA25_TCLK5 (AT91C_PIO_PA25) // Timer Counter 5 external Clock Input +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_CANRX0 (AT91C_PIO_PA26) // CAN Receive 0 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_CANTX0 (AT91C_PIO_PA27) // CAN Transmit 0 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_CANRX1 (AT91C_PIO_PA28) // CAN Receive 1 +#define AT91C_PA28_TCLK3 (AT91C_PIO_PA28) // Timer Counter 3 external Clock Input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_CANTX1 (AT91C_PIO_PA29) // CAN Transmit 1 +#define AT91C_PA29_TCLK6 (AT91C_PIO_PA29) // Timer Counter 6 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TXD0 (AT91C_PIO_PA3) // USART 0 Transmit Data +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data +#define AT91C_PA30_TCLK7 (AT91C_PIO_PA30) // Timer Counter 7 external clock input +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data +#define AT91C_PA31_TCLK8 (AT91C_PIO_PA31) // Timer Counter 8 external clock input +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_SCK0 (AT91C_PIO_PA4) // USART 0 Serial Clock +#define AT91C_PA4_SPI1_NPCS0 (AT91C_PIO_PA4) // SPI1 Peripheral Chip Select 0 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RTS0 (AT91C_PIO_PA5) // USART 0 Ready To Send +#define AT91C_PA5_SPI1_NPCS1 (AT91C_PIO_PA5) // SPI1 Peripheral Chip Select 1 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_CTS0 (AT91C_PIO_PA6) // USART 0 Clear To Send +#define AT91C_PA6_SPI1_NPCS2 (AT91C_PIO_PA6) // SPI1 Peripheral Chip Select 2 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RXD1 (AT91C_PIO_PA7) // USART 1 Receive Data +#define AT91C_PA7_SPI1_NPCS3 (AT91C_PIO_PA7) // SPI1 Peripheral Chip Select 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_TXD1 (AT91C_PIO_PA8) // USART 1 Transmit Data +#define AT91C_PA8_SPI1_MISO (AT91C_PIO_PA8) // SPI1 Master In Slave +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_RXD2 (AT91C_PIO_PA9) // USART 2 Receive Data +#define AT91C_PA9_SPI1_MOSI (AT91C_PIO_PA9) // SPI1 Master Out Slave +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_IRQ2 (AT91C_PIO_PB0) // Interrupt input 2 +#define AT91C_PB0_PWM5 (AT91C_PIO_PB0) // PWMC Channel 5 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_IRQ3 (AT91C_PIO_PB1) // Interrupt input 3 +#define AT91C_PB1_PWM6 (AT91C_PIO_PB1) // PWMC Channel 6 +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_TCLK1 (AT91C_PIO_PB10) // Timer Counter 1 external clock input +#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_TCLK2 (AT91C_PIO_PB11) // Timer Counter 2 external clock input +#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TIOA0 (AT91C_PIO_PB12) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB12_TD1 (AT91C_PIO_PB12) // SSC Transmit Data 1 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TIOB0 (AT91C_PIO_PB13) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB13_RD1 (AT91C_PIO_PB13) // SSC Receive Data 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_TIOA1 (AT91C_PIO_PB14) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB14_PWM0 (AT91C_PIO_PB14) // PWMC Channel 0 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_TIOB1 (AT91C_PIO_PB15) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB15_PWM1 (AT91C_PIO_PB15) // PWMC Channel 1 +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TIOA2 (AT91C_PIO_PB16) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB16_PWM2 (AT91C_PIO_PB16) // PWMC Channel 2 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_TIOB2 (AT91C_PIO_PB17) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB17_PWM3 (AT91C_PIO_PB17) // PWMC Channel 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_TIOA3 (AT91C_PIO_PB18) // Timer Counter 3 Multipurpose Timer I/O Pin A +#define AT91C_PB18_PWM4 (AT91C_PIO_PB18) // PWMC Channel 4 +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_TIOB3 (AT91C_PIO_PB19) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PB19_SPI1_NPCS1 (AT91C_PIO_PB19) // SPI1 Peripheral Chip Select 1 +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_TF0 (AT91C_PIO_PB2) // SSC Transmit Frame Sync 0 +#define AT91C_PB2_PWM7 (AT91C_PIO_PB2) // PWMC Channel 7 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_TIOA4 (AT91C_PIO_PB20) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PB20_SPI1_NPCS2 (AT91C_PIO_PB20) // SPI1 Peripheral Chip Select 2 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_TIOB4 (AT91C_PIO_PB21) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PB21_SPI1_NPCS3 (AT91C_PIO_PB21) // SPI1 Peripheral Chip Select 3 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_TIOA5 (AT91C_PIO_PB22) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOB5 (AT91C_PIO_PB23) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOA6 (AT91C_PIO_PB24) // Timer Counter 6 Multipurpose Timer I/O Pin A +#define AT91C_PB24_RTS1 (AT91C_PIO_PB24) // USART 1 Ready To Send +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOB6 (AT91C_PIO_PB25) // Timer Counter 6 Multipurpose Timer I/O Pin B +#define AT91C_PB25_CTS1 (AT91C_PIO_PB25) // USART 1 Clear To Send +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOA7 (AT91C_PIO_PB26) // Timer Counter 7 Multipurpose Timer I/O Pin A +#define AT91C_PB26_SCK1 (AT91C_PIO_PB26) // USART 1 Serial Clock +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOB7 (AT91C_PIO_PB27) // Timer Counter 7 Multipurpose Timer I/O Pin B +#define AT91C_PB27_RTS2 (AT91C_PIO_PB27) // USART 2 Ready To Send +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOA8 (AT91C_PIO_PB28) // Timer Counter 8 Multipurpose Timer I/O Pin A +#define AT91C_PB28_CTS2 (AT91C_PIO_PB28) // USART 2 Clear To Send +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_TIOB8 (AT91C_PIO_PB29) // Timer Counter 8 Multipurpose Timer I/O Pin B +#define AT91C_PB29_SCK2 (AT91C_PIO_PB29) // USART 2 Serial Clock +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_TK0 (AT91C_PIO_PB3) // SSC Transmit Clock 0 +#define AT91C_PB3_PCK0 (AT91C_PIO_PB3) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TD0 (AT91C_PIO_PB4) // SSC Transmit data +#define AT91C_PB4_PCK1 (AT91C_PIO_PB4) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RD0 (AT91C_PIO_PB5) // SSC Receive Data +#define AT91C_PB5_PCK2 (AT91C_PIO_PB5) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_RK0 (AT91C_PIO_PB6) // SSC Receive Clock +#define AT91C_PB6_PCK3 (AT91C_PIO_PB6) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_RF0 (AT91C_PIO_PB7) // SSC Receive Frame Sync 0 +#define AT91C_PB7_CANTX1 (AT91C_PIO_PB7) // CAN Transmit 1 +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_FIQ (AT91C_PIO_PB8) // AIC Fast Interrupt Input +#define AT91C_PB8_TF1 (AT91C_PIO_PB8) // SSC Transmit Frame Sync 1 +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_TCLK0 (AT91C_PIO_PB9) // Timer Counter 0 external clock input +#define AT91C_PB9_TK1 (AT91C_PIO_PB9) // SSC Transmit Clock 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7A3 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_CAN0 ( 4) // Control Area Network Controller 0 +#define AT91C_ID_CAN1 ( 5) // Control Area Network Controller 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_US2 ( 8) // USART 2 +#define AT91C_ID_MCI ( 9) // Multimedia Card Interface +#define AT91C_ID_TWI (10) // Two-Wire Interface +#define AT91C_ID_SPI0 (11) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 (12) // Serial Peripheral Interface 1 +#define AT91C_ID_SSC0 (13) // Serial Synchronous Controller 0 +#define AT91C_ID_SSC1 (14) // Serial Synchronous Controller 1 +#define AT91C_ID_TC0 (15) // Timer Counter 0 +#define AT91C_ID_TC1 (16) // Timer Counter 1 +#define AT91C_ID_TC2 (17) // Timer Counter 2 +#define AT91C_ID_TC3 (18) // Timer Counter 3 +#define AT91C_ID_TC4 (19) // Timer Counter 4 +#define AT91C_ID_TC5 (20) // Timer Counter 5 +#define AT91C_ID_TC6 (21) // Timer Counter 6 +#define AT91C_ID_TC7 (22) // Timer Counter 7 +#define AT91C_ID_TC8 (23) // Timer Counter 8 +#define AT91C_ID_ADC0 (24) // Analog To Digital Converter 0 +#define AT91C_ID_ADC1 (25) // Analog To Digital Converter 1 +#define AT91C_ID_PWMC (26) // Pulse Width Modulation Controller +#define AT91C_ID_UDP (27) // USB Device Port +#define AT91C_ID_IRQ0 (28) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (29) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 (30) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ID_IRQ3 (31) // Advanced Interrupt Controller (IRQ3) +#define AT91C_ALL_INT (0xFFFFFFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7A3 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_CAN0_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80200) // (CAN0_MB0) Base Address +#define AT91C_BASE_CAN0_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80220) // (CAN0_MB1) Base Address +#define AT91C_BASE_CAN0_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80240) // (CAN0_MB2) Base Address +#define AT91C_BASE_CAN0_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80260) // (CAN0_MB3) Base Address +#define AT91C_BASE_CAN0_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80280) // (CAN0_MB4) Base Address +#define AT91C_BASE_CAN0_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802A0) // (CAN0_MB5) Base Address +#define AT91C_BASE_CAN0_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802C0) // (CAN0_MB6) Base Address +#define AT91C_BASE_CAN0_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802E0) // (CAN0_MB7) Base Address +#define AT91C_BASE_CAN0_MB8 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80300) // (CAN0_MB8) Base Address +#define AT91C_BASE_CAN0_MB9 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80320) // (CAN0_MB9) Base Address +#define AT91C_BASE_CAN0_MB10 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80340) // (CAN0_MB10) Base Address +#define AT91C_BASE_CAN0_MB11 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80360) // (CAN0_MB11) Base Address +#define AT91C_BASE_CAN0_MB12 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80380) // (CAN0_MB12) Base Address +#define AT91C_BASE_CAN0_MB13 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803A0) // (CAN0_MB13) Base Address +#define AT91C_BASE_CAN0_MB14 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803C0) // (CAN0_MB14) Base Address +#define AT91C_BASE_CAN0_MB15 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803E0) // (CAN0_MB15) Base Address +#define AT91C_BASE_CAN0 (AT91_CAST(AT91PS_CAN) 0xFFF80000) // (CAN0) Base Address +#define AT91C_BASE_CAN1_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84200) // (CAN1_MB0) Base Address +#define AT91C_BASE_CAN1_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84220) // (CAN1_MB1) Base Address +#define AT91C_BASE_CAN1_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84240) // (CAN1_MB2) Base Address +#define AT91C_BASE_CAN1_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84260) // (CAN1_MB3) Base Address +#define AT91C_BASE_CAN1_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84280) // (CAN1_MB4) Base Address +#define AT91C_BASE_CAN1_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842A0) // (CAN1_MB5) Base Address +#define AT91C_BASE_CAN1_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842C0) // (CAN1_MB6) Base Address +#define AT91C_BASE_CAN1_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842E0) // (CAN1_MB7) Base Address +#define AT91C_BASE_CAN1_MB8 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84300) // (CAN1_MB8) Base Address +#define AT91C_BASE_CAN1_MB9 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84320) // (CAN1_MB9) Base Address +#define AT91C_BASE_CAN1_MB10 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84340) // (CAN1_MB10) Base Address +#define AT91C_BASE_CAN1_MB11 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84360) // (CAN1_MB11) Base Address +#define AT91C_BASE_CAN1_MB12 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84380) // (CAN1_MB12) Base Address +#define AT91C_BASE_CAN1_MB13 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843A0) // (CAN1_MB13) Base Address +#define AT91C_BASE_CAN1_MB14 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843C0) // (CAN1_MB14) Base Address +#define AT91C_BASE_CAN1_MB15 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843E0) // (CAN1_MB15) Base Address +#define AT91C_BASE_CAN1 (AT91_CAST(AT91PS_CAN) 0xFFF84000) // (CAN1) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFA4000) // (TC3) Base Address +#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFA4040) // (TC4) Base Address +#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFA4080) // (TC5) Base Address +#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFA4000) // (TCB1) Base Address +#define AT91C_BASE_TC6 (AT91_CAST(AT91PS_TC) 0xFFFA8000) // (TC6) Base Address +#define AT91C_BASE_TC7 (AT91_CAST(AT91PS_TC) 0xFFFA8040) // (TC7) Base Address +#define AT91C_BASE_TC8 (AT91_CAST(AT91PS_TC) 0xFFFA8080) // (TC8) Base Address +#define AT91C_BASE_TCB2 (AT91_CAST(AT91PS_TCB) 0xFFFA8000) // (TCB2) Base Address +#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFAC000) // (MCI) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFC8000) // (US2) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH4 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC280) // (PWMC_CH4) Base Address +#define AT91C_BASE_PWMC_CH5 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2A0) // (PWMC_CH5) Base Address +#define AT91C_BASE_PWMC_CH6 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2C0) // (PWMC_CH6) Base Address +#define AT91C_BASE_PWMC_CH7 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2E0) // (PWMC_CH7) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address +#define AT91C_BASE_PDC_SSC1 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address +#define AT91C_BASE_SSC1 (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address +#define AT91C_BASE_PDC_ADC0 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC0) Base Address +#define AT91C_BASE_ADC0 (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC0) Base Address +#define AT91C_BASE_PDC_ADC1 (AT91_CAST(AT91PS_PDC) 0xFFFDC100) // (PDC_ADC1) Base Address +#define AT91C_BASE_ADC1 (AT91_CAST(AT91PS_ADC) 0xFFFDC000) // (ADC1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7A3 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h new file mode 100644 index 000000000..8fc3a9883 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S128.h +// Object : AT91SAM7S128 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:49) +// +// CVS Reference : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S128_H +#define AT91SAM7S128_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h new file mode 100644 index 000000000..a4f1af138 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S256.h +// Object : AT91SAM7S256 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:57) +// +// CVS Reference : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S256_H +#define AT91SAM7S256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h new file mode 100644 index 000000000..aa45c3924 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h @@ -0,0 +1,2303 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S512.h +// Object : AT91SAM7S512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:13:20) +// +// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// +// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// +// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005// +// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S512_H +#define AT91SAM7S512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h new file mode 100644 index 000000000..d124ce2a9 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:13:29) +// +// CVS Reference : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h new file mode 100644 index 000000000..7fab07f8b --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h @@ -0,0 +1,2914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:15:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.19/Wed Aug 30 14:09:08 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h new file mode 100644 index 000000000..20b0e747d --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h @@ -0,0 +1,2918 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) +// +// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h new file mode 100644 index 000000000..7c03a0db4 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h @@ -0,0 +1,2984 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X512.h +// Object : AT91SAM7X512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:15:41) +// +// CVS Reference : /AT91SAM7X512.pl/1.7/Wed Aug 30 14:09:17 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X512_H +#define AT91SAM7X512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00020000) // Internal SRAM size in byte (128 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.c b/os/hal/platforms/AT91SAM7/at91lib/aic.c new file mode 100644 index 000000000..66eebf94e --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/aic.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the interrupt associated with the given source, using the +/// specified mode and interrupt handler. +/// \param source Interrupt source to configure. +/// \param mode Triggering mode of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.h b/os/hal/platforms/AT91SAM7/at91lib/aic.h new file mode 100644 index 000000000..e8e52c78a --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91lib/aic.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Redefinition of missing constant. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/os/hal/platforms/AT91SAM7/at91sam7.h b/os/hal/platforms/AT91SAM7/at91sam7.h new file mode 100644 index 000000000..0d3ce288e --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91sam7.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _AT91SAM7_H_ +#define _AT91SAM7_H_ + +/* + * Supported platforms. + */ +#define SAM7S64 0 +#define SAM7S128 1 +#define SAM7S256 2 +#define SAM7S512 3 +#define SAM7X128 4 +#define SAM7X256 5 +#define SAM7X512 6 +#define SAM7A3 7 + +#ifndef SAM7_PLATFORM +#error "SAM7 platform not defined" +#endif + +#if SAM7_PLATFORM == SAM7S64 +#include "at91lib/AT91SAM7S64.h" +#elif SAM7_PLATFORM == SAM7S128 +#include "at91lib/AT91SAM7S128.h" +#elif SAM7_PLATFORM == SAM7S256 +#include "at91lib/AT91SAM7S256.h" +#elif SAM7_PLATFORM == SAM7S512 +#include "at91lib/AT91SAM7S512.h" +#elif SAM7_PLATFORM == SAM7X128 +#include "at91lib/AT91SAM7X128.h" +#elif SAM7_PLATFORM == SAM7X256 +#include "at91lib/AT91SAM7X256.h" +#elif SAM7_PLATFORM == SAM7X512 +#include "at91lib/AT91SAM7X512.h" +#elif SAM7_PLATFORM == SAM7A3 +#include "at91lib/AT91SAM7A3.h" +#else +#error "SAM7 platform not supported" +#endif + +#endif /* _AT91SAM7_H_ */ diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.c b/os/hal/platforms/AT91SAM7/at91sam7_mii.c new file mode 100644 index 000000000..b64a389a2 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91sam7_mii.c @@ -0,0 +1,144 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/at91sam7_mii.c + * @brief AT91SAM7 low level MII driver code. + * + * @addtogroup AT91SAM7_MII + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "at91sam7_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MII driver initialization. + * + * @notapi + */ +void miiInit(void) { + +} + +/** + * @brief Resets a PHY device. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void miiReset(MACDriver *macp) { + + (void)macp; + + /* + * Disables the pullups on all the pins that are latched on reset by the PHY. + */ + AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS; + +#ifdef PIOB_PHY_PD_MASK + /* + * PHY power control. + */ + AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; /* Becomes an output. */ + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;/* Default pullup disabled. */ +#if (PHY_HARDWARE == PHY_DAVICOM_9161) + AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; /* Output to low level. */ +#else + AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; /* Output to high level. */ +#endif +#endif + + /* + * PHY reset by pulsing the NRST pin. + */ + AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100; + AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST; + while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)) + ; +} + +/** + * @brief Reads a PHY register through the MII interface. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] addr the register address + * @return The register value. + * + * @notapi + */ +phyreg_t miiGet(MACDriver *macp, phyaddr_t addr) { + + (void)macp; + AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ + (0b10 << 28) | /* RW */ + (PHY_ADDRESS << 23) | /* PHYA */ + (addr << 18) | /* REGA */ + (0b10 << 16); /* CODE */ + while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) + ; + return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF); +} + +/** + * @brief Writes a PHY register through the MII interface. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] addr the register address + * @param[in] value the new register value + * + * @notapi + */ +void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value) { + + (void)macp; + AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ + (0b01 << 28) | /* RW */ + (PHY_ADDRESS << 23) | /* PHYA */ + (addr << 18) | /* REGA */ + (0b10 << 16) | /* CODE */ + value; + while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) + ; +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.h b/os/hal/platforms/AT91SAM7/at91sam7_mii.h new file mode 100644 index 000000000..f55db7e78 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/at91sam7_mii.h @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/at91sam7_mii.h + * @brief AT91SAM7 low level MII driver header. + * + * @addtogroup AT91SAM7_MII + * @{ + */ + +#ifndef _AT91SAM7_MII_H_ +#define _AT91SAM7_MII_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define PHY_MICREL_KS8721 0 +#define PHY_DAVICOM_9161 1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief PHY manufacturer and model. + */ +#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__) +#define PHY_HARDWARE PHY_MICREL_KS8721 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Pins latched by the PHY at reset. + */ +#if PHY_HARDWARE == PHY_MICREL_KS8721 +#define PHY_ADDRESS 1 +#define PHY_ID MII_KS8721_ID +#define PHY_LATCHED_PINS (AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ + AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \ + AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \ + AT91C_PIO_PB26) + +#elif PHY_HARDWARE == PHY_DAVICOM_9161 +#define PHY_ADDRESS 0 +#define PHY_ID MII_DM9161_ID +#define PHY_LATCHED_PINS (AT91C_PB0_ETXCK_EREFCK | AT91C_PB4_ECRS | \ + AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \ + AT91C_PB7_ERXER | AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ + AT91C_PB16_ECOL | AT91C_PB17_ERXCK) +#endif /* PHY_HARDWARE */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PHY register value. + */ +typedef uint16_t phyreg_t; + +/** + * @brief Type of a PHY register address. + */ +typedef uint8_t phyaddr_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void miiInit(void); + void miiReset(MACDriver *macp); + phyreg_t miiGet(MACDriver *macp, phyaddr_t addr); + void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _AT91SAM7_MII_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c new file mode 100644 index 000000000..91d0b7a8d --- /dev/null +++ b/os/hal/platforms/AT91SAM7/ext_lld.c @@ -0,0 +1,235 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/ext_lld.c + * @brief AT91SAM7 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTDA driver identifier. + */ +EXTDriver EXTDA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) +/** + * @brief EXTDB driver identifier. + */ +EXTDriver EXTDB; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Handles external interrupts. + * + * @param[in] extp pointer to the driver that received the interrupt + */ +static void ext_lld_serveInterrupt(EXTDriver *extp) { + uint32_t irqFlags; + uint32_t ch; + + chSysLockFromIsr(); + + /* Read flags of pending PIO interrupts.*/ + irqFlags = extp->pio->PIO_ISR; + + /* Call callback function for any pending interrupt.*/ + for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) { + + /* Check if the channel is activated and if its IRQ flag is set.*/ + if((extp->config->channels[ch].mode & + EXT_CH_MODE_ENABLED & EXT_CH_MODE_EDGES_MASK) + && ((1 << ch) & irqFlags)) { + (extp->config->channels[ch].cb)(extp, ch); + } + } + + chSysUnlockFromIsr(); + + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIA_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDA); + + CH_IRQ_EPILOGUE(); +} + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIB_IRQHandler) { + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDB); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTDA); + + /* Set PIO base addresses.*/ + EXTDA.pio = AT91C_BASE_PIOA; + + /* Set peripheral IDs.*/ + EXTDA.pid = AT91C_ID_PIOA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + /* Same for PIOB.*/ + extObjectInit(&EXTDB); + EXTDB.pio = AT91C_BASE_PIOB; + EXTDB.pid = AT91C_ID_PIOB; +#endif +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + uint16_t ch; + uint32_t ier = 0; + const EXTConfig *config = extp->config; + + switch(extp->pid) { + case AT91C_ID_PIOA: + AIC_ConfigureIT(AT91C_ID_PIOA, SAM7_computeSMR(config->mode, + config->priority), + EXTIA_IRQHandler); + break; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + case AT91C_ID_PIOB: + AIC_ConfigureIT(AT91C_ID_PIOB, SAM7_computeSMR(config->mode, + config->priority), + EXTIB_IRQHandler); + break; +#endif + } + + /* Enable and Disable channels with respect to config.*/ + for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) { + ier |= (config->channels[ch].mode & EXT_CH_MODE_EDGES_MASK & EXT_CH_MODE_ENABLED ? 1 : 0) << ch; + } + extp->pio->PIO_IER = ier; + extp->pio->PIO_IDR = ~ier; + + /* Enable interrupt on corresponding PIO port in AIC.*/ + AIC_EnableIT(extp->pid); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + /* Disable interrupt on corresponding PIO port in AIC.*/ + AIC_DisableIT(extp->pid); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp->config->channels[channel].cb != NULL), + "Call back pointer can not be NULL"); + + extp->pio->PIO_IER = (1 << channel); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + extp->pio->PIO_IDR = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/ext_lld.h b/os/hal/platforms/AT91SAM7/ext_lld.h new file mode 100644 index 000000000..3bc0baa99 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/ext_lld.h @@ -0,0 +1,239 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/ext_lld.h + * @brief AT91SAM7 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Pointer to the SAM7 AIC register block. + */ +#define SAM7_EXT_AIC ((AT91PS_AIC *)AT91C_BASE_AIC) + +/** + * @brief Number of channels within one ext driver. + */ +#define EXT_MAX_CHANNELS 32 + +/** + * @brief Mask of priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_MASK 0x00000007 + +/** + * @brief Shifter for priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_SHIFTER 0 + +/** + * @brief Shifter for mode bits in interrupt mode register. + */ +#define SAM7_EXT_MODE_SHIFTER 5 + +/* + * On the SAM7 architecture, a single channel can only be enables or disabled + * Hence, undefine the other channel mode constants + */ +#ifdef EXT_CH_MODE_RISING_EDGE +#undef EXT_CH_MODE_RISING_EDGE +#endif + +#ifdef EXT_CH_MODE_FALLING_EDGE +#undef EXT_CH_MODE_FALLING_EDGE +#endif + +#ifdef EXT_CH_MODE_BOTH_EDGES +#undef EXT_CH_MODE_BOTH_EDGES +#endif + +/** + * @name EXT channels mode + * @{ + */ +#define EXT_CH_MODE_ENABLED 1 /**< @brief Channel is enabled. */ +/** @} */ + +/** + * @name EXT drivers mode + * @{ + */ +/** + * @brief Mask for modes. + */ +#define SAM7_EXT_MODE_MASK AT91C_AIC_SRCTYPE +/** + * @brief Falling edge callback. + */ +#define SAM7_EXT_MODE_FALLING_EDGE AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE +/** + * @brief Rising edge callback. + */ +#define SAM7_EXT_MODE_RISING_EDGE AT91C_AIC_SRCTYPE_POSITIVE_EDGE +/** + * @brief High-level callback. + */ +#define SAM7_EXT_MODE_HIGH_LEVEL AT91C_AIC_SRCTYPE_HIGH_LEVEL +/** + * @brief Low-level callback. + */ +#define SAM7_EXT_MODE_LOW_LEVEL AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL +/** @} */ + +/** + * @name EXT drivers priorities + * @{ + */ +#define SAM7_EXT_PRIOR_HIGHEST AT91C_AIC_PRIOR_HIGHEST +#define SAM7_EXT_PRIOR_LOWEST AT91C_AIC_PRIOR_LOWEST +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief interrupt mode. + */ + uint32_t mode; + /** + * @brief interrupt priority. + */ + uint32_t priority; +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ + + /** + * @brief Pointer to the corresponding PIO registers block. + */ + AT91PS_PIO pio; + /** + * @brief peripheral ID of the corresponding PIO block. + */ + uint32_t pid; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Computes the content for the interrupt source mode register. + */ +#define SAM7_computeSMR(mode, prio) ( \ + ((mode & SAM7_EXT_MODE_MASK) << SAM7_EXT_MODE_SHIFTER) | \ + ((prio & SAM7_EXT_PRIORITY_MASK) << SAM7_EXT_PRIORITY_SHIFTER) \ +) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTDA; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) +extern EXTDriver EXTDB; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/hal_lld.c b/os/hal/platforms/AT91SAM7/hal_lld.c new file mode 100644 index 000000000..43659ed9c --- /dev/null +++ b/os/hal/platforms/AT91SAM7/hal_lld.c @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/hal_lld.c + * @brief AT91SAM7 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static CH_IRQ_HANDLER(spurious_handler) { + + CH_IRQ_PROLOGUE(); + + AT91SAM7_SPURIOUS_HANDLER_HOOK(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + unsigned i; + + /* FIQ Handler weak symbol defined in vectors.s.*/ + void FiqHandler(void); + + /* Default AIC setup, the device drivers will modify it as needed.*/ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; + } + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)spurious_handler; + +} + +/** + * @brief AT91SAM7 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void at91sam7_clock_init(void) { + + /* wait for reset */ + while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL) + ; + /* enable reset */ + AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN); + + /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/ +#if SAM7_PLATFORM == SAM7X512 + AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; +#else + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; +#endif + + /* Enables the main oscillator and waits 56 slow cycles as startup time.*/ + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + PLLfreq = 96109714 Hz (rounded).*/ + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91SAM7_USBDIV) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) + ; + + /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/ + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; + + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; +} + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/hal_lld.h b/os/hal/platforms/AT91SAM7/hal_lld.h new file mode 100644 index 000000000..2a489be6f --- /dev/null +++ b/os/hal/platforms/AT91SAM7/hal_lld.h @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/hal_lld.h + * @brief AT91SAM7 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "at91sam7.h" +#include "at91lib/aic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "AT91SAM7x" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Default action for the spurious handler, nothing. + */ +#if !defined(AT91SAM7_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__) +#define AT91SAM7_SPURIOUS_HANDLER_HOOK() +#endif + +/** + * @brief Default divider for the USB clock - half the PLL clock. + */ +#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__) +#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void at91sam7_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.c b/os/hal/platforms/AT91SAM7/i2c_lld.c new file mode 100644 index 000000000..1e6e02829 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/i2c_lld.c @@ -0,0 +1,450 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file AT91SAM7/i2c_lld.c + * @brief AT91SAM7 I2C subsystem low level driver source. + * @note I2C peripheral interrupts on AT91SAM7 platform must have highest + * priority in system. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Helper function. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void _i2c_lld_serve_rx_interrupt(I2CDriver *i2cp){ + if (i2cp->rxbytes == 1) + AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP; + + *(i2cp->rxbuf) = AT91C_BASE_TWI->TWI_RHR; + i2cp->rxbuf++; + i2cp->rxbytes--; + if (i2cp->rxbytes == 0){ + AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_RXRDY; + AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP; + } +} + +/** + * @brief Helper function. + * @note During write operation you do not need to set STOP manually. + * It sets automatically when THR and shift registers becomes empty. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void _i2c_lld_serve_tx_interrupt(I2CDriver *i2cp){ + + if (i2cp->txbytes == 0){ + AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXRDY; + AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP; + } + else{ + AT91C_BASE_TWI->TWI_THR = *(i2cp->txbuf); + i2cp->txbuf++; + i2cp->txbytes--; + } +} + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_interrupt(I2CDriver *i2cp) { + + uint32_t sr; + sr = AT91C_BASE_TWI->TWI_SR; + /* this masking doing in official Atmel driver. Is it needed ??? */ + sr &= AT91C_BASE_TWI->TWI_IMR; + + if (sr & AT91C_TWI_NACK){ + i2cp->errors |= I2CD_ACK_FAILURE; + wakeup_isr(i2cp, RDY_RESET); + return; + } + if (sr & AT91C_TWI_RXRDY){ + _i2c_lld_serve_rx_interrupt(i2cp); + } + else if (sr & AT91C_TWI_TXRDY){ + _i2c_lld_serve_tx_interrupt(i2cp); + } + else if (sr & AT91C_TWI_TXCOMP){ + AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP; + wakeup_isr(i2cp, RDY_OK); + } + else + chDbgPanic("Invalid value"); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(TWI_IRQHandler) { + + CH_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if SAM7_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.txbuf = NULL; + I2CD1.rxbuf = NULL; + I2CD1.txbytes = 0; + I2CD1.rxbytes = 0; + + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA0_TWD | AT91C_PA1_TWCK; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA0_TWD | AT91C_PA1_TWCK; + AT91C_BASE_PIOA->PIO_MDER = AT91C_PA0_TWD | AT91C_PA1_TWCK; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA0_TWD | AT91C_PA1_TWCK; + + AIC_ConfigureIT(AT91C_ID_TWI, + AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | SAM7_I2C_I2C1_IRQ_PRIORITY, + TWI_IRQHandler); +#endif /* STM32_I2C_USE_I2C1 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + + volatile uint32_t fake; + + /* If in stopped state then enables the I2C clocks.*/ + if (i2cp->state == I2C_STOP) { + +#if SAM7_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + /* enable peripheral clock */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TWI); + + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_TWI); + + /* Reset */ + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST; + fake = AT91C_BASE_TWI->TWI_RHR; + + /* Set master mode */ + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSDIS; + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSEN; + + /* Setup I2C parameters. */ + AT91C_BASE_TWI->TWI_CWGR = i2cp->config->cwgr; + } +#endif /* STM32_I2C_USE_I2C1 */ + } + + (void)fake; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + +#if SAM7_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP | AT91C_TWI_RXRDY | + AT91C_TWI_TXRDY | AT91C_TWI_NACK; + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_TWI); + AIC_DisableIT(AT91C_ID_TWI); + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout this value is ignored on SAM7 platform. + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + (void)timeout; + + /* delete trash from RHR*/ + volatile uint32_t fake; + fake = AT91C_BASE_TWI->TWI_RHR; + (void)fake; + + /* Initializes driver fields.*/ + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + i2cp->txbuf = NULL; + i2cp->txbytes = 0; + + /* tune master mode register */ + AT91C_BASE_TWI->TWI_MMR = 0; + AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | AT91C_TWI_MREAD; + + /* enable just needed interrupts */ + AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK; + + /* In single data byte master read or write, the START and STOP must both be set. */ + if (rxbytes == 1) + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START; + else + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START; + + /* Waits for the operation completion.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Read data via the I2C bus as master using internal slave addressing. + * @details Address bytes must be written in special purpose SAM7 registers. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout this value is ignored on SAM7 platform. + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * + * @notapi + */ +msg_t i2c_lld_transceive_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + (void)timeout; + + /* delete trash from RHR*/ + volatile uint32_t fake; + fake = AT91C_BASE_TWI->TWI_RHR; + (void)fake; + + /* Initializes driver fields.*/ + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* tune master mode register */ + AT91C_BASE_TWI->TWI_MMR = 0; + AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | (txbytes << 8) | AT91C_TWI_MREAD; + + /* store internal slave address in TWI_IADR registers */ + AT91C_BASE_TWI->TWI_IADR = 0; + while (txbytes > 0){ + AT91C_BASE_TWI->TWI_IADR = (AT91C_BASE_TWI->TWI_IADR << 8); + AT91C_BASE_TWI->TWI_IADR |= *(txbuf++); + txbytes--; + } + + /* enable just needed interrupts */ + AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK; + + /* Internal address of I2C slave was set in special Atmel registers. + * Now we must call read function. The I2C cell automatically sends + * bytes from IADR register to bus and issues repeated start. */ + if (rxbytes == 1) + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START; + else + AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START; + + /* Waits for the operation completion.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details When performing reading through write you can not write more than + * 3 bytes of data to I2C slave. This is SAM7 platform limitation. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout this value is ignored on SAM7 platform. + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + (void)timeout; + + /* SAM7 specific check */ + chDbgCheck(((rxbytes == 0) || + ((txbytes > 0) && (txbytes < 4) && (rxbuf != NULL))), + "i2c_lld_master_transmit_timeout"); + + /* prepare to read through write operation */ + if (rxbytes > 0){ + return i2c_lld_transceive_timeout(i2cp, addr, txbuf, txbytes, rxbuf, + rxbytes, timeout); + } + else{ + if (txbytes == 1){ + /* In single data byte master read or write, the START and STOP + * must both be set. */ + AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP; + } + AT91C_BASE_TWI->TWI_MMR = 0; + AT91C_BASE_TWI->TWI_MMR |= addr << 16; + + /* enable just needed interrupts */ + AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY | AT91C_TWI_NACK; + + /* correct size and pointer because first byte will be written + * for issue start condition */ + i2cp->txbuf = txbuf + 1; + i2cp->txbytes = txbytes - 1; + + /* According to datasheet there is no need to set START manually + * we just need to write first byte in THR */ + AT91C_BASE_TWI->TWI_THR = txbuf[0]; + + /* Waits for the operation completion.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + + return chThdSelf()->p_u.rdymsg; + } +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.h b/os/hal/platforms/AT91SAM7/i2c_lld.h new file mode 100644 index 000000000..8e22acaf6 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/i2c_lld.h @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file AT91SAM7/i2c_lld.h + * @brief AT91SAM7 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Peripheral clock frequency. + */ +#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM7_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define SAM7_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(SAM7_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_I2C_I2C1_IRQ_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief error checks */ +#if !SAM7_I2C_USE_I2C1 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CWGR regitster content. + */ + uint32_t cwgr; +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; + /** + * @brief Pointer to receive buffer. + */ + uint8_t *rxbuf; + /** + * @brief Pointer to transmit buffer. + */ + const uint8_t *txbuf; + /** + * @brief Bytes count to be received. + */ + size_t rxbytes; + /** + * @brief Bytes count to be transmitted. + */ + size_t txbytes; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if SAM7_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/mac_lld.c b/os/hal/platforms/AT91SAM7/mac_lld.c new file mode 100644 index 000000000..df1e0b88b --- /dev/null +++ b/os/hal/platforms/AT91SAM7/mac_lld.c @@ -0,0 +1,551 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/mac_lld.c + * @brief AT91SAM7 low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "mii.h" +#include "at91sam7_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK | AT91C_PB1_ETXEN | \ + AT91C_PB2_ETX0 | AT91C_PB3_ETX1 | \ + AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ + AT91C_PB8_EMDC | AT91C_PB9_EMDIO | \ + AT91C_PB10_ETX2 | AT91C_PB11_ETX3 | \ + AT91C_PB12_ETXER | AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ + AT91C_PB16_ECOL | AT91C_PB17_ERXCK) + +#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR) + +#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \ + AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#ifndef __DOXYGEN__ + +static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10}; + +static EMACDescriptor *rxptr; +static EMACDescriptor *txptr; +static EMACDescriptor rd[EMAC_RECEIVE_DESCRIPTORS] + __attribute__((aligned(8))); +static EMACDescriptor td[EMAC_TRANSMIT_DESCRIPTORS] + __attribute__((aligned(8))); +static uint8_t rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE] + __attribute__((aligned(8))); +static uint8_t tb[EMAC_TRANSMIT_DESCRIPTORS * EMAC_TRANSMIT_BUFFERS_SIZE] + __attribute__((aligned(8))); +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ handler. + */ +/** @cond never*/ +__attribute__((noinline)) +/** @endcond*/ +static void serve_interrupt(void) { + uint32_t isr, rsr, tsr; + + /* Fix for the EMAC errata */ + isr = AT91C_BASE_EMAC->EMAC_ISR; + rsr = AT91C_BASE_EMAC->EMAC_RSR; + tsr = AT91C_BASE_EMAC->EMAC_TSR; + + if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) { + if (rsr & AT91C_EMAC_REC) { + chSysLockFromIsr(); + chSemResetI(ÐD1.rdsem, 0); +#if MAC_USE_EVENTS + chEvtBroadcastI(ÐD1.rdevent); +#endif + chSysUnlockFromIsr(); + } + AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS; + } + + if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) { + if (tsr & AT91C_EMAC_COMP) { + chSysLockFromIsr(); + chSemResetI(ÐD1.tdsem, 0); + chSysUnlockFromIsr(); + } + AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS; + } + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +/** + * @brief Cleans an incomplete frame. + * + * @param[in] from the start position of the incomplete frame + */ +static void cleanup(EMACDescriptor *from) { + + while (from != rxptr) { + from->w1 &= ~W1_R_OWNERSHIP; + if (++from >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + from = rd; + } +} + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void set_address(const uint8_t *p) { + + AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) | + (p[1] << 8) | p[0]); + AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EMAC IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(irq_handler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + + miiInit(); + macObjectInit(ÐD1); + + /* + * Associated PHY initialization. + */ + miiReset(ÐD1); + + /* + * EMAC pins setup. Note, PB18 is not included because it is + * used as #PD control and not as EF100. + */ + AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + + /* + * Buffers initialization. + */ + for (i = 0; i < EMAC_RECEIVE_DESCRIPTORS; i++) { + rd[i].w1 = (uint32_t)&rb[i * EMAC_RECEIVE_BUFFERS_SIZE]; + rd[i].w2 = 0; + } + rd[EMAC_RECEIVE_DESCRIPTORS - 1].w1 |= W1_R_WRAP; + rxptr = rd; + for (i = 0; i < EMAC_TRANSMIT_DESCRIPTORS; i++) { + td[i].w1 = (uint32_t)&tb[i * EMAC_TRANSMIT_BUFFERS_SIZE]; + td[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_LAST_BUFFER | W2_T_USED; + } + td[EMAC_TRANSMIT_DESCRIPTORS - 1].w2 |= W2_T_WRAP; + txptr = td; + + /* + * EMAC clock enable. + */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; + + /* + * EMAC Initial setup. + */ + AT91C_BASE_EMAC->EMAC_NCR = 0; /* Stopped but MCE active.*/ + AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10; /* MDC-CLK = MCK / 32 */ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;/* Enable EMAC in MII mode.*/ + AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rd; /* RX descriptors list.*/ + AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)td; /* TX descriptors list.*/ + AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | + AT91C_EMAC_REC | + AT91C_EMAC_BNA; /* Clears RSR.*/ + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS;/* Initial NCFGR settings.*/ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | + AT91C_EMAC_RE | + AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/ + if (macp->config->mac_address == NULL) + set_address(default_mac); + else + set_address(macp->config->mac_address); + + /* + * PHY device identification. + */ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + if ((miiGet(ÐD1, MII_PHYSID1) != (PHY_ID >> 16)) || + ((miiGet(ÐD1, MII_PHYSID2) & 0xFFF0) != (PHY_ID & 0xFFF0))) + chSysHalt(); + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + + /* + * Interrupt configuration. + */ + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP; + AIC_ConfigureIT(AT91C_ID_EMAC, + AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | EMAC_INTERRUPT_PRIORITY, + irq_handler); + AIC_EnableIT(AT91C_ID_EMAC); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + (void)macp; +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + EMACDescriptor *edp; + + (void)macp; + + if (!macp->link_up) + return RDY_TIMEOUT; + + chSysLock(); + edp = txptr; + if (!(edp->w2 & W2_T_USED) || (edp->w2 & W2_T_LOCKED)) { + chSysUnlock(); + return RDY_TIMEOUT; + } + /* + * Set the buffer size and configuration, the buffer is also marked + * as locked. + */ + if (++txptr >= &td[EMAC_TRANSMIT_DESCRIPTORS]) { + edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER | W2_T_WRAP; + txptr = td; + } + else + edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER; + chSysUnlock(); + tdp->offset = 0; + tdp->size = EMAC_TRANSMIT_BUFFERS_SIZE; + tdp->physdesc = edp; + return RDY_OK; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->w1 & W1_T_ADDRESS_MASK) + + tdp->offset, + buf, size); + tdp->offset += size; + } + return size; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + chSysLock(); + tdp->physdesc->w2 = (tdp->physdesc->w2 & + ~(W2_T_LOCKED | W2_T_USED | W2_T_LENGTH_MASK)) | + tdp->offset; + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; + chSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + unsigned n; + EMACDescriptor *edp; + + (void)macp; + n = EMAC_RECEIVE_DESCRIPTORS; + + /* + * Skips unused buffers, if any. + */ +skip: + while ((n > 0) && !(rxptr->w1 & W1_R_OWNERSHIP)) { + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + + /* + * Skips fragments, if any, cleaning them up. + */ + while ((n > 0) && (rxptr->w1 & W1_R_OWNERSHIP) && + !(rxptr->w2 & W2_R_FRAME_START)) { + rxptr->w1 &= ~W1_R_OWNERSHIP; + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + + /* + * Now compute the total frame size skipping eventual incomplete frames + * or holes... + */ +restart: + edp = rxptr; + while (n > 0) { + if (!(rxptr->w1 & W1_R_OWNERSHIP)) { + /* Empty buffer for some reason... cleaning up the incomplete frame.*/ + cleanup(edp); + goto skip; + } + /* + * End Of Frame found. + */ + if (rxptr->w2 & W2_R_FRAME_END) { + rdp->offset = 0; + rdp->size = rxptr->w2 & W2_T_LENGTH_MASK; + rdp->physdesc = edp; + return RDY_OK; + } + + if ((edp != rxptr) && (rxptr->w2 & W2_R_FRAME_START)) { + /* Found another start... cleaning up the incomplete frame.*/ + cleanup(edp); + goto restart; /* Another start buffer for some reason... */ + } + + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + return RDY_TIMEOUT; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + if (size > 0) { + uint8_t *src = (uint8_t *)(rdp->physdesc->w1 & W1_R_ADDRESS_MASK) + + rdp->offset; + uint8_t *limit = &rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE]; + if (src >= limit) + src -= EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE; + if (src + size > limit ) { + memcpy(buf, src, (size_t)(limit - src)); + memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src)); + } + else + memcpy(buf, src, size); + rdp->offset += size; + } + return size; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + bool_t done; + EMACDescriptor *edp = rdp->physdesc; + + unsigned n = EMAC_RECEIVE_DESCRIPTORS; + do { + done = ((edp->w2 & W2_R_FRAME_END) != 0); + chDbgAssert(edp->w1 & W1_R_OWNERSHIP, + "mac_lld_release_receive_descriptor(), #1", + "found not owned descriptor"); + edp->w1 &= ~(W1_R_OWNERSHIP | W2_R_FRAME_START | W2_R_FRAME_END); + if (++edp >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + edp = rd; + n--; + } + while ((n > 0) && !done); + /* + * Make rxptr point to the descriptor where the next frame will most + * likely appear. + */ + rxptr = edp; +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + uint32_t ncfgr, bmsr, bmcr, lpa; + + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + (void)miiGet(macp, MII_BMSR); + bmsr = miiGet(macp, MII_BMSR); + if (!(bmsr & BMSR_LSTATUS)) { + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + return macp->link_up = FALSE; + } + + ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + bmcr = miiGet(macp, MII_BMCR); + if (bmcr & BMCR_ANENABLE) { + lpa = miiGet(macp, MII_LPA); + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + ncfgr |= AT91C_EMAC_SPD; + if (lpa & (LPA_10FULL | LPA_100FULL)) + ncfgr |= AT91C_EMAC_FD; + } + else { + if (bmcr & BMCR_SPEED100) + ncfgr |= AT91C_EMAC_SPD; + if (bmcr & BMCR_FULLDPLX) + ncfgr |= AT91C_EMAC_FD; + } + AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr; + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + return macp->link_up = TRUE; +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/mac_lld.h b/os/hal/platforms/AT91SAM7/mac_lld.h new file mode 100644 index 000000000..8a56b6793 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/mac_lld.h @@ -0,0 +1,252 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/mac_lld.h + * @brief AT91SAM7 low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation does not support the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY FALSE + +#define EMAC_RECEIVE_BUFFERS_SIZE 128 /* Do not modify */ +#define EMAC_TRANSMIT_BUFFERS_SIZE MAC_BUFFERS_SIZE +#define EMAC_RECEIVE_DESCRIPTORS \ + (((((MAC_BUFFERS_SIZE - 1) | (EMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \ + / EMAC_RECEIVE_BUFFERS_SIZE) * MAC_RECEIVE_BUFFERS) +#define EMAC_TRANSMIT_DESCRIPTORS MAC_TRANSMIT_BUFFERS + +#define W1_R_OWNERSHIP 0x00000001 +#define W1_R_WRAP 0x00000002 +#define W1_R_ADDRESS_MASK 0xFFFFFFFC + +#define W2_R_LENGTH_MASK 0x00000FFF +#define W2_R_FRAME_START 0x00004000 +#define W2_R_FRAME_END 0x00008000 +#define W2_R_CFI 0x00010000 +#define W2_R_VLAN_PRIO_MASK 0x000E0000 +#define W2_R_PRIO_TAG_DETECTED 0x00100000 +#define W2_R_VLAN_TAG_DETECTED 0x00200000 +#define W2_R_TYPE_ID_MATCH 0x00400000 +#define W2_R_ADDR4_MATCH 0x00800000 +#define W2_R_ADDR3_MATCH 0x01000000 +#define W2_R_ADDR2_MATCH 0x02000000 +#define W2_R_ADDR1_MATCH 0x04000000 +#define W2_R_RFU1 0x08000000 +#define W2_R_ADDR_EXT_MATCH 0x10000000 +#define W2_R_UNICAST_MATCH 0x20000000 +#define W2_R_MULTICAST_MATCH 0x40000000 +#define W2_R_BROADCAST_DETECTED 0x80000000 + +#define W1_T_ADDRESS_MASK 0xFFFFFFFF + +#define W2_T_LENGTH_MASK 0x000007FF +#define W2_T_LOCKED 0x00000800 /* Not an EMAC flag. */ +#define W2_T_RFU1 0x00003000 +#define W2_T_LAST_BUFFER 0x00008000 +#define W2_T_NO_CRC 0x00010000 +#define W2_T_RFU2 0x07FE0000 +#define W2_T_BUFFERS_EXHAUSTED 0x08000000 +#define W2_T_TRANSMIT_UNDERRUN 0x10000000 +#define W2_T_RETRY_LIMIT_EXC 0x20000000 +#define W2_T_WRAP 0x40000000 +#define W2_T_USED 0x80000000 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Number of available transmit buffers. + */ +#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define MAC_RECEIVE_BUFFERS 2 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define MAC_BUFFERS_SIZE 1518 +#endif + +/** + * @brief Interrupt priority level for the EMAC device. + */ +#if !defined(EMAC_INTERRUPT_PRIORITY) || defined(__DOXYGEN__) +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Structure representing a buffer physical descriptor. + * @note It represents both descriptor types. + */ +typedef struct { + uint32_t w1; + uint32_t w2; +} EMACDescriptor; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + const uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool_t link_up; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + EMACDescriptor *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the first descriptor of the buffers chain. + */ + EMACDescriptor *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/pal_lld.c b/os/hal/platforms/AT91SAM7/pal_lld.c new file mode 100644 index 000000000..506d42d22 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/pal_lld.c @@ -0,0 +1,150 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/pal_lld.c + * @brief AT91SAM7 PIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AT91SAM7 I/O ports configuration. + * @details PIO registers initialization. + * + * @param[in] config the AT91SAM7 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + uint32_t ports = (1 << AT91C_ID_PIOA); +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + ports |= (1 << AT91C_ID_PIOB); +#endif + AT91C_BASE_PMC->PMC_PCER = ports; + + /* + * PIOA setup. + */ + AT91C_BASE_PIOA->PIO_PPUER = config->P0Data.pusr; /* Pull-up as spec.*/ + AT91C_BASE_PIOA->PIO_PPUDR = ~config->P0Data.pusr; + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ + AT91C_BASE_PIOA->PIO_ODSR = config->P0Data.odsr; /* Data as specified.*/ + AT91C_BASE_PIOA->PIO_OER = config->P0Data.osr; /* Dir. as specified.*/ + AT91C_BASE_PIOA->PIO_ODR = ~config->P0Data.osr; + AT91C_BASE_PIOA->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ + AT91C_BASE_PIOA->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ + AT91C_BASE_PIOA->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ + AT91C_BASE_PIOA->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ + + /* + * PIOB setup. + */ +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) + AT91C_BASE_PIOB->PIO_PPUER = config->P1Data.pusr; /* Pull-up as spec.*/ + AT91C_BASE_PIOB->PIO_PPUDR = ~config->P1Data.pusr; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ + AT91C_BASE_PIOB->PIO_ODSR = config->P1Data.odsr; /* Data as specified.*/ + AT91C_BASE_PIOB->PIO_OER = config->P1Data.osr; /* Dir. as specified.*/ + AT91C_BASE_PIOB->PIO_ODR = ~config->P1Data.osr; + AT91C_BASE_PIOB->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ + AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ + AT91C_BASE_PIOB->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ + AT91C_BASE_PIOB->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ + AT91C_BASE_PIOB->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note This function is not meant to be invoked directly from the + * application code. + * @note @p PAL_MODE_RESET is implemented as input with pull-up. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note @p PAL_MODE_OUTPUT_OPENDRAIN also enables the pull-up resistor. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->PIO_PPUER = mask; + port->PIO_ODR = mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->PIO_PPUDR = mask; + port->PIO_ODR = mask; + break; + case PAL_MODE_UNCONNECTED: + port->PIO_SODR = mask; + /* Falls in */ + case PAL_MODE_OUTPUT_PUSHPULL: + port->PIO_PPUDR = mask; + port->PIO_OER = mask; + port->PIO_MDDR = mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->PIO_PPUER = mask; + port->PIO_OER = mask; + port->PIO_MDER = mask; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/pal_lld.h b/os/hal/platforms/AT91SAM7/pal_lld.h new file mode 100644 index 000000000..761a7142a --- /dev/null +++ b/os/hal/platforms/AT91SAM7/pal_lld.h @@ -0,0 +1,256 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/pal_lld.h + * @brief AT91SAM7 PIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief PIO port setup info. + */ +typedef struct { + /** Initial value for ODSR register (data).*/ + uint32_t odsr; + /** Initial value for OSR register (direction).*/ + uint32_t osr; + /** Initial value for PUSR register (Pull-ups).*/ + uint32_t pusr; +} at91sam7_pio_setup_t; + +/** + * @brief AT91SAM7 PIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port 0 setup data.*/ + at91sam7_pio_setup_t P0Data; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \ + defined(__DOXYGEN__) + /** @brief Port 1 setup data.*/ + at91sam7_pio_setup_t P1Data; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef AT91PS_PIO ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief PIO port A identifier. + */ +#define IOPORT1 AT91C_BASE_PIOA + +/** + * @brief PIO port B identifier. + */ +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \ + defined(__DOXYGEN__) +#define IOPORT2 AT91C_BASE_PIOB +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @details This function is implemented by reading the PIO_PDSR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->PIO_PDSR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the PIO_ODSR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->PIO_ODSR) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_ODSR register, the + * implementation has no side effects. + * + * @param[in] port the port identifier + * @param[in] bits the bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->PIO_ODSR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_SODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->PIO_SODR = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_CODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->PIO_CODR = (bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the PIO_OWER, PIO_ODSR and + * PIO_OWDR registers, the implementation is not atomic because the + * multiple accesses. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->PIO_OWER = (mask) << (offset), \ + (port)->PIO_ODSR = (bits) << (offset), \ + (port)->PIO_OWDR = (mask) << (offset)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/platform.dox b/os/hal/platforms/AT91SAM7/platform.dox new file mode 100644 index 000000000..b423bb461 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/platform.dox @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup AT91SAM7 AT91SAM7 Drivers + * @details This section describes all the supported drivers on the AT91SAM7 + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup AT91SAM7_HAL AT91SAM7 Initialization Support + * @details The AT91SAM7 HAL support is responsible for system initialization. + * + * @section at91sam7_hal_1 Supported HW resources + * - MC. + * - PMC. + * . + * @section at91sam7_hal_2 AT91SAM7 HAL driver implementation features + * - PLLs startup and stabilization. + * - Clock source selection. + * - Flash wait states. + * . +* @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_MAC AT91SAM7 MAC Support + * @details The AT91SAM7 MAC driver supports the EMAC peripheral. + * + * @section at91sam7_mac_1 Supported HW resources + * - EMAC. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_MII AT91SAM7 MII Support + * @details This driver supports the AT91SAM7 EMAC peripheral communicating + * with an external PHY transceiver. The driver currently supports + * the Micrel KS8721 PHY and the Davicom DV9161 modules. This driver + * is used internally by the MAC driver. + * + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_PAL AT91SAM7 PAL Support + * @details The AT91SAM7 PAL driver supports the PIO peripherals. + * + * @section at91sam7_pal_1 Supported HW resources + * - PIOA. + * - PIOB. + * . + * @section at91sam7_pal_2 AT91SAM7 PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 32 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section at91sam7_pal_3 Supported PAL setup modes + * The AT91SAM7 PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section at91sam7_pal_4 Suboptimal behavior + * The AT91SAM7 PIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_SERIAL AT91SAM7 Serial Support + * @details The AT91SAM7 Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section at91sam7_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - DBGU. + * . + * @section at91sam7_serial_2 AT91SAM7 Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each USART. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_SPI AT91SAM7 SPI Support + * @details The SPI driver supports the AT91SAM7 SPI peripherals using DMA + * channels for maximum performance. + * + * @section at91sam7_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * . + * @section at91sam7_spi_2 AT91SAM7 SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * . + * @ingroup AT91SAM7 + */ diff --git a/os/hal/platforms/AT91SAM7/platform.mk b/os/hal/platforms/AT91SAM7/platform.mk new file mode 100644 index 000000000..40a71afc9 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/platform.mk @@ -0,0 +1,15 @@ +# List of all the AT91SAM7 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91sam7_mii.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91lib/aic.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AT91SAM7 diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.c b/os/hal/platforms/AT91SAM7/pwm_lld.c new file mode 100644 index 000000000..7d4060427 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/pwm_lld.c @@ -0,0 +1,467 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + This file has been contributed by: + Andrew Hannam aka inmarket. +*/ + +/** + * @file AT91SAM7/pwm_lld.c + * @brief AT91SAM7 PWM Driver subsystem low level driver source. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#ifdef UNUSED +#elif defined(__GNUC__) +# define UNUSED(x) UNUSED_ ## x __attribute__((unused)) +#elif defined(__LCLINT__) +# define UNUSED(x) /*@unused@*/ x +#else +# define UNUSED(x) x +#endif + +#define PWMC_M ((AT91S_PWMC *)AT91C_PWMC_MR) + +#define PWM_MCK_MASK 0x0F00 +#define PWM_MCK_SHIFT 8 + +typedef struct pindef { + uint32_t portpin; /* Set to 0 if this pin combination is invalid */ + AT91S_PIO *pio; + AT91_REG *perab; +} pindef_t; + +typedef struct pwmpindefs { + pindef_t pin[3]; +} pwmpindefs_t; + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if PWM_USE_PWM1 && !defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \ + (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512) + +#if PWM_USE_PWM1 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP1 = {{ + { AT91C_PA0_PWM0 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR }, + { AT91C_PA11_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + { AT91C_PA23_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + }}; +#endif +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP2 = {{ + { AT91C_PA1_PWM1 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR }, + { AT91C_PA12_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + { AT91C_PA24_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + }}; +#endif +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP3 = {{ + { AT91C_PA2_PWM2 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR }, + { AT91C_PA13_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + { AT91C_PA25_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + }}; +#endif +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP4 = {{ + { AT91C_PA7_PWM3 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + { AT91C_PA14_PWM3, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR }, + { 0, 0, 0 }, + }}; +#endif + +#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + +#if PWM_USE_PWM1 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP1 = {{ + { AT91C_PB19_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR }, + { AT91C_PB27_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR }, + { 0, 0, 0 }, + }}; +#endif +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP2 = {{ + { AT91C_PB20_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR }, + { AT91C_PB28_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR }, + { 0, 0, 0 }, + }}; +#endif +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP3 = {{ + { AT91C_PB21_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR }, + { AT91C_PB29_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR }, + { 0, 0, 0 }, + }}; +#endif +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) +static const pwmpindefs_t PWMP4 = {{ + { AT91C_PB22_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR }, + { AT91C_PB30_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR }, + { 0, 0, 0 }, + }}; +#endif + +#else + #error "PWM pins not defined for this SAM7 version" +#endif + +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Common IRQ handler. + */ +static void pwm_lld_serve_interrupt(void) { + uint32_t isr; + + isr = PWMC_M->PWMC_ISR; +#if PWM_USE_PWM1 + if ((isr & 1) && PWMD1.config->channels[0].callback) + PWMD1.config->channels[0].callback(&PWMD1); +#endif +#if PWM_USE_PWM2 + if ((isr & 2) && PWMD2.config->channels[0].callback) + PWMD2.config->channels[0].callback(&PWMD2); +#endif +#if PWM_USE_PWM3 + if ((isr & 4) && PWMD3.config->channels[0].callback) + PWMD3.config->channels[0].callback(&PWMD3); +#endif +#if PWM_USE_PWM4 + if ((isr & 8) && PWMD4.config->channels[0].callback) + PWMD4.config->channels[0].callback(&PWMD4); +#endif +} + +CH_IRQ_HANDLER(PWMIrqHandler) { + CH_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + + /* Driver initialization.*/ +#if PWM_USE_PWM1 && !defined(__DOXYGEN__) + pwmObjectInit(&PWMD1); + PWMD1.chbit = 1; + PWMD1.reg = AT91C_BASE_PWMC_CH0; + PWMD1.pins = &PWMP1; +#endif + +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) + pwmObjectInit(&PWMD2); + PWMD2.chbit = 2; + PWMD2.reg = AT91C_BASE_PWMC_CH1; + PWMD2.pins = &PWMP2; +#endif + +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) + pwmObjectInit(&PWMD3); + PWMD3.chbit = 4; + PWMD3.reg = AT91C_BASE_PWMC_CH2; + PWMD3.pins = &PWMP3; +#endif + +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) + pwmObjectInit(&PWMD4); + PWMD4.chbit = 8; + PWMD4.reg = AT91C_BASE_PWMC_CH3; + PWMD4.pins = &PWMP4; +#endif + + /* Turn on PWM in the power management controller */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PWMC); + + /* Setup interrupt handler */ + PWMC_M->PWMC_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PWMC, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_PWM_PRIORITY, + PWMIrqHandler); + AIC_EnableIT(AT91C_ID_PWMC); +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t mode, mr, div, pre; + + /* Steps: + 1. Turn the IO pin to a PWM output + 2. Configuration of Clock if DIVA or DIVB used + 3. Selection of the clock for each channel (CPRE field in the PWM_CMRx register) + 4. Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) + 5. Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) + 6. Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in + PWM_CPRDx Register is possible while the channel is disabled. After validation of the + channel, the user must use PWM_CUPDx Register to update PWM_CPRDx + 7. Enable Interrupts (Writing CHIDx in the PWM_IER register) + */ + + /* Make sure it is off first */ + pwm_lld_disable_channel(pwmp, 0); + + /* Configuration.*/ + mode = pwmp->config->channels[0].mode; + + /* Step 1 */ + if (mode & PWM_OUTPUT_PIN1) { + pwmp->pins->pin[0].perab[0] = pwmp->pins->pin[0].portpin; /* Select A or B peripheral */ + pwmp->pins->pin[0].pio->PIO_PDR = pwmp->pins->pin[0].portpin; /* Turn PIO into PWM output */ + pwmp->pins->pin[0].pio->PIO_MDDR = pwmp->pins->pin[0].portpin; /* Turn off PIO multi-drive */ + if (mode & PWM_DISABLEPULLUP_PIN1) + pwmp->pins->pin[0].pio->PIO_PPUDR = pwmp->pins->pin[0].portpin; /* Turn off PIO pullup */ + else + pwmp->pins->pin[0].pio->PIO_PPUER = pwmp->pins->pin[0].portpin; /* Turn on PIO pullup */ + } + if (mode & PWM_OUTPUT_PIN2) { + pwmp->pins->pin[1].perab[0] = pwmp->pins->pin[1].portpin; + pwmp->pins->pin[1].pio->PIO_PDR = pwmp->pins->pin[1].portpin; + pwmp->pins->pin[1].pio->PIO_MDDR = pwmp->pins->pin[1].portpin; + if (mode & PWM_DISABLEPULLUP_PIN2) + pwmp->pins->pin[1].pio->PIO_PPUDR = pwmp->pins->pin[1].portpin; + else + pwmp->pins->pin[1].pio->PIO_PPUER = pwmp->pins->pin[1].portpin; + } + if ((mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin) { + pwmp->pins->pin[2].perab[0] = pwmp->pins->pin[2].portpin; + pwmp->pins->pin[2].pio->PIO_PDR = pwmp->pins->pin[2].portpin; + pwmp->pins->pin[2].pio->PIO_MDDR = pwmp->pins->pin[2].portpin; + if (mode & PWM_DISABLEPULLUP_PIN3) + pwmp->pins->pin[2].pio->PIO_PPUDR = pwmp->pins->pin[2].portpin; + else + pwmp->pins->pin[2].pio->PIO_PPUER = pwmp->pins->pin[2].portpin; + } + + /* Step 2 */ + if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKA) { + if (!pwmp->config->frequency) { + /* As slow as we go */ + PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (10 << 8) | (255 << 0); + } else if (pwmp->config->frequency > MCK) { + /* Just use MCLK */ + mode &= ~PWM_MCK_MASK; + } else { + div = MCK / pwmp->config->frequency; + if (mode & PWM_OUTPUT_CENTER) div >>= 1; + for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1; + if (div > 255) div = 255; + PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (pre << 8) | (div << 0); + } + } else if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKB) { + if (!pwmp->config->frequency) { + /* As slow as we go */ + PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (10 << 24) | (255 << 16); + } else if (pwmp->config->frequency > MCK) { + /* Just use MCLK */ + mode &= ~PWM_MCK_MASK; + } else { + div = MCK / pwmp->config->frequency; + if (mode & PWM_OUTPUT_CENTER) div >>= 1; + for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1; + if (div > 255) div = 255; + PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (pre << 24) | (div << 16); + } + } + + /* Step 3 -> 5 */ + mr = (mode & PWM_MCK_MASK) >> PWM_MCK_SHIFT; + if (mode & PWM_OUTPUT_CENTER) mr |= AT91C_PWMC_CALG; + if (mode & PWM_OUTPUT_ACTIVE_HIGH) mr |= AT91C_PWMC_CPOL; + pwmp->reg->PWMC_CMR = mr; + + /* Step 6 */ + pwmp->reg->PWMC_CPRDR = pwmp->period; + + /* Step 7 */ + if (pwmp->config->channels[0].callback) + PWMC_M->PWMC_IER = pwmp->chbit; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + /* Make sure it is off */ + pwm_lld_disable_channel(pwmp, 0); + + /* Turn the pin back to a PIO pin - we have forgotten pull-up and multi-drive state for the pin though */ + if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN1) + pwmp->pins->pin[0].pio->PIO_PER = pwmp->pins->pin[0].portpin; + if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN2) + pwmp->pins->pin[1].pio->PIO_PER = pwmp->pins->pin[1].portpin; + if ((pwmp->config->channels[0].mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin) + pwmp->pins->pin[2].pio->PIO_PER = pwmp->pins->pin[2].portpin; +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + pwmp->period = period; + + if (PWMC_M->PWMC_SR & pwmp->chbit) { + pwmp->reg->PWMC_CMR |= AT91C_PWMC_CPD; + pwmp->reg->PWMC_CUPDR = period; + } else { + pwmp->reg->PWMC_CPRDR = period; + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t UNUSED(channel), + pwmcnt_t width) { + /* + 6. Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). + Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of + the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx. + 7. Enable the PWM channel (Writing CHIDx in the PWM_ENA register) + */ + + /* Step 6 */ + if (PWMC_M->PWMC_SR & pwmp->chbit) { + pwmp->reg->PWMC_CMR &= ~AT91C_PWMC_CPD; + pwmp->reg->PWMC_CUPDR = width; + } else { + pwmp->reg->PWMC_CDTYR = width; + PWMC_M->PWMC_ENA = pwmp->chbit; + } + + /* Step 7 */ + PWMC_M->PWMC_ENA = pwmp->chbit; +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t UNUSED(channel)) { + PWMC_M->PWMC_IDR = pwmp->chbit; + PWMC_M->PWMC_DIS = pwmp->chbit; +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.h b/os/hal/platforms/AT91SAM7/pwm_lld.h new file mode 100644 index 000000000..cb1a830ff --- /dev/null +++ b/os/hal/platforms/AT91SAM7/pwm_lld.h @@ -0,0 +1,284 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + This file has been contributed by: + Andrew Hannam aka inmarket. +*/ +/** + * @file AT91SAM7/pwm_lld.h + * @brief AT91SAM7 PWM Driver subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 1 + +/** + * @brief PWM device interrupt priority level setting. + */ +#if !defined(AT91SAM7_PWM_PRIORITY) || defined(__DOXYGEN__) +#define AT91SAM7_PWM_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 4) +#endif + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(PWM_USE_PWM1) || defined(__DOXYGEN__) +#define PWM_USE_PWM1 TRUE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(PWM_USE_PWM2) || defined(__DOXYGEN__) +#define PWM_USE_PWM2 TRUE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(PWM_USE_PWM3) || defined(__DOXYGEN__) +#define PWM_USE_PWM3 TRUE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(PWM_USE_PWM4) || defined(__DOXYGEN__) +#define PWM_USE_PWM4 TRUE +#endif + +/** + * @brief PWM left (count up) logic + */ +#define PWM_OUTPUT_LEFT 0x00000000 + +/** + * @brief PWM center (count up-down) logic. Gives symetric waveform + */ +#define PWM_OUTPUT_CENTER 0x00000010 + +/** + * @brief PWM Master Clock = MCK / 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, CLKA or CLKB. CLKA or CLKB uses the frequency field + */ +#define PWM_MCK_DIV_1 0x00000000 +#define PWM_MCK_DIV_2 0x00000100 +#define PWM_MCK_DIV_4 0x00000200 +#define PWM_MCK_DIV_8 0x00000300 +#define PWM_MCK_DIV_16 0x00000400 +#define PWM_MCK_DIV_32 0x00000500 +#define PWM_MCK_DIV_64 0x00000600 +#define PWM_MCK_DIV_128 0x00000700 +#define PWM_MCK_DIV_256 0x00000800 +#define PWM_MCK_DIV_512 0x00000900 +#define PWM_MCK_DIV_1024 0x00000A00 +#define PWM_MCK_DIV_CLKA 0x00000B00 +#define PWM_MCK_DIV_CLKB 0x00000C00 + +/** + * @brief Which PWM output pins to turn on. PIN1 is the lowest numbered pin, PIN2 next lowest, and then on some packages PIN3. + */ +#define PWM_OUTPUT_PIN1 0x00001000 +#define PWM_OUTPUT_PIN2 0x00002000 +#define PWM_OUTPUT_PIN3 0x00004000 + +/** + * @brief Which PWM output pins should have pullups disabled. + */ +#define PWM_DISABLEPULLUP_PIN1 0x00010000 +#define PWM_DISABLEPULLUP_PIN2 0x00020000 +#define PWM_DISABLEPULLUP_PIN3 0x00040000 + + /*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + + /* End of the mandatory fields.*/ + + /** + * @brief The PWM internal channel number as a bit mask (1, 2, 4 or 8). + */ + uint32_t chbit; + /** + * @brief Pointer to the PWMCx registers block. + */ + AT91S_PWMC_CH *reg; + /** + * @brief Pointer to the output pins descriptor. + */ + const struct pwmpindefs *pins; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PWM_USE_PWM1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if PWM_USE_PWM2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if PWM_USE_PWM3 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if PWM_USE_PWM4 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/serial_lld.c b/os/hal/platforms/AT91SAM7/serial_lld.c new file mode 100644 index 000000000..e586a6342 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/serial_lld.c @@ -0,0 +1,444 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/serial_lld.c + * @brief AT91SAM7 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \ + (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512) + +#define SAM7_USART0_RX AT91C_PA5_RXD0 +#define SAM7_USART0_TX AT91C_PA6_TXD0 +#define SAM7_USART1_RX AT91C_PA21_RXD1 +#define SAM7_USART1_TX AT91C_PA22_TXD1 +#define SAM7_DBGU_RX AT91C_PA9_DRXD +#define SAM7_DBGU_TX AT91C_PA10_DTXD + +#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + +#define SAM7_USART0_RX AT91C_PA0_RXD0 +#define SAM7_USART0_TX AT91C_PA1_TXD0 +#define SAM7_USART1_RX AT91C_PA5_RXD1 +#define SAM7_USART1_TX AT91C_PA6_TXD1 +#define SAM7_DBGU_RX AT91C_PA27_DRXD +#define SAM7_DBGU_TX AT91C_PA28_DTXD + +#elif (SAM7_PLATFORM == SAM7A3) +#define SAM7_USART0_RX AT91C_PA2_RXD0 +#define SAM7_USART0_TX AT91C_PA3_TXD0 +#define SAM7_USART1_RX AT91C_PA7_RXD1 +#define SAM7_USART1_TX AT91C_PA8_TXD1 +#define SAM7_USART2_RX AT91C_PA9_RXD2 +#define SAM7_USART2_TX AT91C_PA10_TXD2 +#define SAM7_DBGU_RX AT91C_PA30_DRXD +#define SAM7_DBGU_TX AT91C_PA31_DTXD + +#else +#error "serial lines not defined for this SAM7 version" +#endif /* HAL_USE_SERIAL */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +/** @brief USART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +/** @brief USART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 || defined(__DOXYGEN__) +/** @brief USART2 serial driver identifier.*/ +SerialDriver SD3; +#endif +#endif + +#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) +/** @brief DBGU_UART serial driver identifier.*/ +SerialDriver SDDBG; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * + * @param[in] sdp communication channel associated to the USART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + AT91PS_USART u = sdp->usart; + + /* Disables IRQ sources and stop operations.*/ + u->US_IDR = 0xFFFFFFFF; + u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; + + /* New parameters setup.*/ + if (config->sc_mr & AT91C_US_OVER) + u->US_BRGR = MCK / (config->sc_speed * 8); + else + u->US_BRGR = MCK / (config->sc_speed * 16); + u->US_MR = config->sc_mr; + u->US_RTOR = 0; + u->US_TTGR = 0; + + /* Enables operations and IRQ sources.*/ + u->US_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_DTREN | AT91C_US_RTSEN; + u->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | + AT91C_US_RXBRK; +} + +/** + * @brief USART de-initialization. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(AT91PS_USART u) { + + /* Disables IRQ sources and stop operations.*/ + u->US_IDR = 0xFFFFFFFF; + u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; + u->US_MR = 0; + u->US_RTOR = 0; + u->US_TTGR = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] err USART CSR register value + * @param[in] sdp communication channel associated to the USART + */ +static void set_error(SerialDriver *sdp, AT91_REG csr) { + flagsmask_t sts = 0; + + if (csr & AT91C_US_OVRE) + sts |= SD_OVERRUN_ERROR; + if (csr & AT91C_US_PARE) + sts |= SD_PARITY_ERROR; + if (csr & AT91C_US_FRAME) + sts |= SD_FRAMING_ERROR; + if (csr & AT91C_US_RXBRK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +#if !USE_SAM7_DBGU_UART +static +#endif +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +void sd_lld_serve_interrupt(SerialDriver *sdp) { + uint32_t csr; + AT91PS_USART u = sdp->usart; + + csr = u->US_CSR; + if (csr & AT91C_US_RXRDY) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, u->US_RHR); + chSysUnlockFromIsr(); + } + if ((u->US_IMR & AT91C_US_TXRDY) && (csr & AT91C_US_TXRDY)) { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + u->US_IDR = AT91C_US_TXRDY; + } + else + u->US_THR = b; + chSysUnlockFromIsr(); + } + csr &= (AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK); + if (csr != 0) { + set_error(sdp, csr); + u->US_CR = AT91C_US_RSTSTA; + } + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_US0->US_IER = AT91C_US_TXRDY; +} +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_US1->US_IER = AT91C_US_TXRDY; +} +#endif + +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_US2->US_IER = AT91C_US_TXRDY; +} +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + +#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) +static void notify_dbg(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_DBGU->DBGU_IER = AT91C_US_TXRDY; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0IrqHandler) { + + CH_IRQ_PROLOGUE(); + sd_lld_serve_interrupt(&SD1); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1IrqHandler) { + + CH_IRQ_PROLOGUE(); + sd_lld_serve_interrupt(&SD2); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART2IrqHandler) { + + CH_IRQ_PROLOGUE(); + sd_lld_serve_interrupt(&SD3); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + +/* note - DBGU_UART IRQ is the SysIrq in board.c + since it's not vectored separately by the AIC.*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_SAM7_USART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = AT91C_BASE_US0; + AT91C_BASE_PIOA->PIO_PDR = SAM7_USART0_RX | SAM7_USART0_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_USART0_RX | SAM7_USART0_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART0_RX | SAM7_USART0_TX; + AIC_ConfigureIT(AT91C_ID_US0, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART0_PRIORITY, + USART0IrqHandler); +#endif + +#if USE_SAM7_USART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = AT91C_BASE_US1; + AT91C_BASE_PIOA->PIO_PDR = SAM7_USART1_RX | SAM7_USART1_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_USART1_RX | SAM7_USART1_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART1_RX | SAM7_USART1_TX; + AIC_ConfigureIT(AT91C_ID_US1, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART1_PRIORITY, + USART1IrqHandler); +#endif + +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = AT91C_BASE_US2; + AT91C_BASE_PIOA->PIO_PDR = SAM7_USART2_RX | SAM7_USART2_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_USART2_RX | SAM7_USART2_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART2_RX | SAM7_USART2_TX; + AIC_ConfigureIT(AT91C_ID_US2, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART2_PRIORITY, + USART2IrqHandler); +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + +#if USE_SAM7_DBGU_UART + sdObjectInit(&SDDBG, NULL, notify_dbg); + /* this is a little cheap, but OK for now since there's enough overlap + between dbgu and usart register maps. it means we can reuse all the + same usart interrupt handling and config that already exists.*/ + SDDBG.usart = (AT91PS_USART)AT91C_BASE_DBGU; + AT91C_BASE_PIOA->PIO_PDR = SAM7_DBGU_RX | SAM7_DBGU_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_DBGU_RX | SAM7_DBGU_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_DBGU_RX | SAM7_DBGU_TX; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if USE_SAM7_USART0 + if (&SD1 == sdp) { + /* Starts the clock and clears possible sources of immediate interrupts.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US0); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_US0); + } +#endif +#if USE_SAM7_USART1 + if (&SD2 == sdp) { + /* Starts the clock and clears possible sources of immediate interrupts.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_US1); + } +#endif +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 + if (&SD3 == sdp) { + /* Starts the clock and clears possible sources of immediate interrupts.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US2); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_US2); + } +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + /* Note - no explicit start for SD3 (DBGU_UART) since it's not included + in the AIC or PMC.*/ + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if USE_SAM7_USART0 + if (&SD1 == sdp) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US0); + AIC_DisableIT(AT91C_ID_US0); + return; + } +#endif +#if USE_SAM7_USART1 + if (&SD2 == sdp) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US1); + AIC_DisableIT(AT91C_ID_US1); + return; + } +#endif +#if USE_SAM7_DBGU_UART + if (&SDDBG == sdp) { + AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF; + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/serial_lld.h b/os/hal/platforms/AT91SAM7/serial_lld.h new file mode 100644 index 000000000..9b25b2be3 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/serial_lld.h @@ -0,0 +1,191 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/serial_lld.h + * @brief AT91SAM7 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_USART0) || defined(__DOXYGEN__) +#define USE_SAM7_USART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_USART1) || defined(__DOXYGEN__) +#define USE_SAM7_USART1 TRUE +#endif + +#if (SAM7_PLATFORM == SAM7A3) +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_USART2) || defined(__DOXYGEN__) +#define USE_SAM7_USART2 TRUE +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + +/** + * @brief DBGU UART driver enable switch. + * @details If set to @p TRUE the support for the DBGU UART is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_DBGU_UART) || defined(__DOXYGEN__) +#define USE_SAM7_DBGU_UART TRUE +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(SAM7_USART0_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(SAM7_USART1_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +#if (SAM7_PLATFORM == SAM7A3) +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(SAM7_USART2_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_USART2_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif +#endif /* (SAM7_PLATFORM == SAM7A3) */ + +/** + * @brief DBGU_UART interrupt priority level setting. + */ +#if !defined(SAM7_DBGU_UART_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_DBGU_UART_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AT91SAM7 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + * @details This is written to the US_BRGR register of the appropriate AT91S_USART + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the MR register. + * @details This is written to the US_MR register of the appropriate AT91S_USART + */ + uint32_t sc_mr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + AT91PS_USART usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SAM7_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if (SAM7_PLATFORM == SAM7A3) +#if USE_SAM7_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#endif +#if USE_SAM7_DBGU_UART +extern SerialDriver SDDBG; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#if USE_SAM7_DBGU_UART + void sd_lld_serve_interrupt(SerialDriver *sdp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/spi_lld.c b/os/hal/platforms/AT91SAM7/spi_lld.c new file mode 100644 index 000000000..a2ffcfd2e --- /dev/null +++ b/os/hal/platforms/AT91SAM7/spi_lld.c @@ -0,0 +1,397 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/spi_lld.c + * @brief AT91SAM7 low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Idle line value. + * @details This thing's DMA apparently does not allow to *not* increment + * the memory pointer so a buffer filled with ones is required + * somewhere. + * @note This buffer size also limits the maximum transfer size, 512B, + * for @p spiReceive() and @p spiIgnore(). @p spiSend() and + * @p spiExchange are not affected. + */ +static const uint16_t idle_buf[] = { + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes a SPI device. + */ +static void spi_init(AT91PS_SPI spi) { + + /* Software reset must be written twice (errata for revision B parts).*/ + spi->SPI_CR = AT91C_SPI_SWRST; + spi->SPI_CR = AT91C_SPI_SWRST; + spi->SPI_RCR = 0; + spi->SPI_RNCR = 0; + spi->SPI_TCR = 0; + spi->SPI_TNCR = 0; + spi->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; + spi->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS; +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Shared interrupt handling code. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_lld_serve_interrupt(SPIDriver *spip) { + uint32_t sr = spip->spi->SPI_SR; + + if ((sr & AT91C_SPI_ENDRX) != 0) { + (void)spip->spi->SPI_RDR; /* Clears eventual overflow.*/ + spip->spi->SPI_PTCR = AT91C_PDC_RXTDIS | + AT91C_PDC_TXTDIS; /* PDC disabled. */ + spip->spi->SPI_IDR = AT91C_SPI_ENDRX; /* Interrupt disabled. */ + spip->spi->SPI_CR = AT91C_SPI_SPIDIS; /* SPI disabled. */ + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** + * @brief SPI0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI0IrqHandler) { + + CH_IRQ_PROLOGUE(); + spi_lld_serve_interrupt(&SPID1); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** + * @brief SPI1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI1IrqHandler) { + + CH_IRQ_PROLOGUE(); + spi_lld_serve_interrupt(&SPID2); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if AT91SAM7_SPI_USE_SPI0 + spiObjectInit(&SPID1); + SPID1.spi = AT91C_BASE_SPI0; + spi_init(AT91C_BASE_SPI0); + AT91C_BASE_PIOA->PIO_PDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AT91C_BASE_PIOA->PIO_ASR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AT91C_BASE_PIOA->PIO_PPUDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AIC_ConfigureIT(AT91C_ID_SPI0, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI0_PRIORITY, + SPI0IrqHandler); +#endif + +#if AT91SAM7_SPI_USE_SPI1 + spiObjectInit(&SPID2); + SPID2.spi = AT91C_BASE_SPI1; + spi_init(AT91C_BASE_SPI1); + AT91C_BASE_PIOA->PIO_PDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AT91C_BASE_PIOA->PIO_BSR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AT91C_BASE_PIOA->PIO_PPUDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AIC_ConfigureIT(AT91C_ID_SPI1, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI1_PRIORITY, + SPI1IrqHandler); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { +#if AT91SAM7_SPI_USE_SPI0 + if (&SPID1 == spip) { + /* Clock activation.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI0); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_SPI0); + } +#endif +#if AT91SAM7_SPI_USE_SPI1 + if (&SPID2 == spip) { + /* Clock activation.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI1); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_SPI1); + } +#endif + } + /* Configuration.*/ + spip->spi->SPI_CSR[0] = spip->config->csr; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { +#if AT91SAM7_SPI_USE_SPI0 + if (&SPID1 == spip) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI0); + AIC_DisableIT(AT91C_ID_SPI0); + } +#endif +#if AT91SAM7_SPI_USE_SPI1 + if (&SPID1 == spip) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI1); + AIC_DisableIT(AT91C_ID_SPI0); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)idle_buf; + spip->spi->SPI_RPR = (AT91_REG)idle_buf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This function performs a simultaneous transmit/receive operation. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)txbuf; + spip->spi->SPI_RPR = (AT91_REG)rxbuf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Sends data over the SPI bus. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)txbuf; + spip->spi->SPI_RPR = (AT91_REG)idle_buf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Receives data from the SPI bus. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)idle_buf; + spip->spi->SPI_RPR = (AT91_REG)rxbuf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_TDR = frame; + while ((spip->spi->SPI_SR & AT91C_SPI_RDRF) == 0) + ; + return spip->spi->SPI_RDR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/spi_lld.h b/os/hal/platforms/AT91SAM7/spi_lld.h new file mode 100644 index 000000000..18299391a --- /dev/null +++ b/os/hal/platforms/AT91SAM7/spi_lld.h @@ -0,0 +1,219 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT91SAM7/spi_lld.h + * @brief AT91SAM7 low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Device compatibility.. */ +/*===========================================================================*/ + +#if defined (AT91C_BASE_SPI) +#define AT91C_BASE_SPI0 AT91C_BASE_SPI +#define AT91C_ID_SPI0 AT91C_ID_SPI + +#define SPI0_MISO (1 << 12) +#define SPI0_MOSI (1 << 13) +#define SPI0_SCK (1 << 14) +#else +#define SPI0_MISO (1 << 16) +#define SPI0_MOSI (1 << 17) +#define SPI0_SCK (1 << 18) + +#define SPI1_MISO (1 << 24) +#define SPI1_MOSI (1 << 23) +#define SPI1_SCK (1 << 22) +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPID1 enable switch (SPI0 device). + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p TRUE. + */ +#if !defined(AT91SAM7_SPI_USE_SPI0) || defined(__DOXYGEN__) +#define AT91SAM7_SPI_USE_SPI0 TRUE +#endif + +/** + * @brief SPID2 enable switch (SPI1 device). + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(AT91SAM7_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define AT91SAM7_SPI_USE_SPI1 TRUE +#endif + +/** + * @brief SPI0 device interrupt priority level setting. + */ +#if !defined(AT91SAM7_SPI0_PRIORITY) || defined(__DOXYGEN__) +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#endif + +/** + * @brief SPI1 device interrupt priority level setting. + */ +#if !defined(AT91SAM7_SPI1_PRIORITY) || defined(__DOXYGEN__) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined (AT91C_BASE_SPI) && AT91SAM7_SPI_USE_SPI1 +#error "SPI1 not present" +#endif + +#if !AT91SAM7_SPI_USE_SPI0 && !AT91SAM7_SPI_USE_SPI1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI Chip Select Register initialization data. + */ + uint32_t csr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + AT91PS_SPI spi; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if AT91SAM7_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AVR/hal_lld.c b/os/hal/platforms/AVR/hal_lld.c new file mode 100644 index 000000000..e01e291d9 --- /dev/null +++ b/os/hal/platforms/AVR/hal_lld.c @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/hal_lld.c + * @brief AVR HAL subsystem low level driver code. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + +} + +/** @} */ diff --git a/os/hal/platforms/AVR/hal_lld.h b/os/hal/platforms/AVR/hal_lld.h new file mode 100644 index 000000000..fd99a70aa --- /dev/null +++ b/os/hal/platforms/AVR/hal_lld.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/hal_lld.h + * @brief AVR HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "ATmega128" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AVR/i2c_lld.c b/os/hal/platforms/AVR/i2c_lld.c new file mode 100644 index 000000000..8db158fbd --- /dev/null +++ b/os/hal/platforms/AVR/i2c_lld.c @@ -0,0 +1,289 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/i2c_lld.c + * @brief AVR I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C driver identifier.*/ +#if USE_AVR_I2C || defined(__DOXYGEN__) +I2CDriver I2CD; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_AVR_I2C || defined(__DOXYGEN__) +/** + * @brief I2C event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(TWI_vect) { + CH_IRQ_PROLOGUE(); + + I2CDriver *i2cp = &I2CD; + + switch (TWSR & 0xF8) { + case TWI_START: + case TWI_REPEAT_START: + TWDR = (i2cp->addr << 1); + if ((i2cp->txbuf == NULL) || (i2cp->txbytes == 0) || (i2cp->txidx == i2cp->txbytes)) { + TWDR |= 0x01; + } + TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + break; + case TWI_MASTER_TX_ADDR_ACK: + case TWI_MASTER_TX_DATA_ACK: + if (i2cp->txidx < i2cp->txbytes) { + TWDR = i2cp->txbuf[i2cp->txidx++]; + TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } else { + if (i2cp->rxbuf && i2cp->rxbytes) { + TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } else { + TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN)); + wakeup_isr(i2cp, RDY_OK); + } + } + break; + case TWI_MASTER_RX_ADDR_ACK: + if (i2cp->rxidx == (i2cp->rxbytes - 1)) { + TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } else { + TWCR = ((1 << TWEA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } + break; + case TWI_MASTER_RX_DATA_ACK: + i2cp->rxbuf[i2cp->rxidx++] = TWDR; + if (i2cp->rxidx == (i2cp->rxbytes - 1)) { + TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } else { + TWCR = ((1 << TWEA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + } + break; + case TWI_MASTER_RX_DATA_NACK: + i2cp->rxbuf[i2cp->rxidx] = TWDR; + TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN)); + wakeup_isr(i2cp, RDY_OK); + case TWI_MASTER_TX_ADDR_NACK: + case TWI_MASTER_TX_DATA_NACK: + case TWI_MASTER_RX_ADDR_NACK: + i2cp->errors |= I2CD_ACK_FAILURE; + break; + case TWI_ARBITRATION_LOST: + i2cp->errors |= I2CD_ARBITRATION_LOST; + break; + case TWI_BUS_ERROR: + i2cp->errors |= I2CD_BUS_ERROR; + break; + default: + /* FIXME: only gets here if there are other MASTERs in the bus */ + TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN)); + wakeup_isr(i2cp, RDY_RESET); + } + + if (i2cp->errors != I2CD_NO_ERROR) { + TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN)); + wakeup_isr(i2cp, RDY_RESET); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_AVR_I2C */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + i2cObjectInit(&I2CD); +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + + /* TODO: Test TWI without external pull-ups (use internal) */ + + /* Configure prescaler to 1 */ + TWSR &= 0xF8; + + /* Configure baudrate */ + TWBR = ((F_CPU / i2cp->config->clock_speed) - 16) / 2; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + if (i2cp->state != I2C_STOP) { + /* Disable TWI subsystem and stop all operations */ + TWCR &= ~(1 << TWEN); + } +} + +/** + * @brief Receives data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + i2cp->addr = addr; + i2cp->txbuf = NULL; + i2cp->txbytes = 0; + i2cp->txidx = 0; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + i2cp->rxidx = 0; + + /* Send START */ + TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + + chSysLock(); + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chSysUnlock(); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + i2cp->addr = addr; + i2cp->txbuf = txbuf; + i2cp->txbytes = txbytes; + i2cp->txidx = 0; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + i2cp->rxidx = 0; + + TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE)); + + chSysLock(); + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chSysUnlock(); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/AVR/i2c_lld.h b/os/hal/platforms/AVR/i2c_lld.h new file mode 100644 index 000000000..9e49cefbe --- /dev/null +++ b/os/hal/platforms/AVR/i2c_lld.h @@ -0,0 +1,224 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/i2c_lld.h + * @brief AVR I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** @brief START transmitted.*/ +#define TWI_START 0x08 +/** @brief Repeated START transmitted.*/ +#define TWI_REPEAT_START 0x10 +/** @brief Arbitration Lost.*/ +#define TWI_ARBITRATION_LOST 0x38 +/** @brief Bus errors.*/ +#define TWI_BUS_ERROR 0x00 + +/** @brief SLA+W transmitted with ACK response.*/ +#define TWI_MASTER_TX_ADDR_ACK 0x18 +/** @brief SLA+W transmitted with NACK response.*/ +#define TWI_MASTER_TX_ADDR_NACK 0x20 +/** @brief DATA transmitted with ACK response.*/ +#define TWI_MASTER_TX_DATA_ACK 0x28 +/** @brief DATA transmitted with NACK response.*/ +#define TWI_MASTER_TX_DATA_NACK 0x30 + +/** @brief SLA+R transmitted with ACK response.*/ +#define TWI_MASTER_RX_ADDR_ACK 0x40 +/** @brief SLA+R transmitted with NACK response.*/ +#define TWI_MASTER_RX_ADDR_NACK 0x48 +/** @brief DATA received with ACK response.*/ +#define TWI_MASTER_RX_DATA_ACK 0x50 +/** @brief DATA received with NACK response.*/ +#define TWI_MASTER_RX_DATA_NACK 0x58 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C driver enable switch. + * @details If set to @p TRUE the support for I2C is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_AVR_I2C) || defined(__DOXYGEN__) +#define USE_AVR_I2C FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint8_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint8_t i2cflags_t; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + + /** + * @brief Specifies the I2C clock frequency. + */ + uint32_t clock_speed; + +} I2CConfig; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Address of slave device. + */ + i2caddr_t addr; + /** + * @brief Pointer to the buffer with data to send. + */ + const uint8_t *txbuf; + /** + * @brief Number of bytes of data to send. + */ + size_t txbytes; + /** + * @brief Current index in buffer when sending data. + */ + size_t txidx; + /** + * @brief Pointer to the buffer to put received data. + */ + uint8_t *rxbuf; + /** + * @brief Number of bytes of data to receive. + */ + size_t rxbytes; + /** + * @brief Current index in buffer when receiving data. + */ + size_t rxidx; +}; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if USE_AVR_I2C +extern I2CDriver I2CD; +#endif +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AVR/pal_lld.c b/os/hal/platforms/AVR/pal_lld.c new file mode 100644 index 000000000..def4bd430 --- /dev/null +++ b/os/hal/platforms/AVR/pal_lld.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/pal_lld.c + * @brief AVR GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AVR GPIO ports configuration. + * @details GPIO registers initialization. + * + * @param[in] config the AVR ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if defined(PORTA) || defined(__DOXYGEN__) + PORTA = config->porta.out; + DDRA = config->porta.dir; +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) + PORTB = config->portb.out; + DDRB = config->portb.dir; +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) + PORTC = config->portc.out; + DDRC = config->portc.dir; +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) + PORTD = config->portd.out; + DDRD = config->portd.dir; +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) + PORTE = config->porte.out; + DDRE = config->porte.dir; +#endif + +#if defined(PORTF) || defined(__DOXYGEN__) + PORTF = config->portf.out; + DDRF = config->portf.dir; +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) + PORTG = config->portg.out; + DDRG = config->portg.dir; +#endif + +#if defined(PORTH) || defined(__DOXYGEN__) + PORTH = config->porth.out; + DDRH = config->porth.dir; +#endif + +#if defined(PORTJ) || defined(__DOXYGEN__) + PORTJ = config->portj.out; + DDRJ = config->portj.dir; +#endif + +#if defined(PORTK) || defined(__DOXYGEN__) + PORTK = config->portk.out; + DDRK = config->portk.dir; +#endif + +#if defined(PORTL) || defined(__DOXYGEN__) + PORTL = config->portl.out; + DDRL = config->portl.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the AVR Family User's Guide. Unconnected pads are set to input + * with pull-up by default. + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->dir &= ~mask; + port->out &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_INPUT_PULLUP: + port->dir &= ~mask; + port->out |= mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/AVR/pal_lld.h b/os/hal/platforms/AVR/pal_lld.h new file mode 100644 index 000000000..f48b51ec3 --- /dev/null +++ b/os/hal/platforms/AVR/pal_lld.h @@ -0,0 +1,329 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/pal_lld.h + * @brief AVR GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief AVR setup registers. + */ +typedef struct { + uint8_t out; + uint8_t dir; +} avr_gpio_setup_t; + +/** + * @brief AVR registers block. + * @note On some devices registers do not follow this layout on some + * ports, the ports with abnormal layout cannot be used through + * PAL driver. Example: PORT F on Mega128. + */ +typedef struct { + volatile uint8_t in; + volatile uint8_t dir; + volatile uint8_t out; +} avr_gpio_registers_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(PORTA) || defined(__DOXYGEN__) + avr_gpio_setup_t porta; +#endif +#if defined(PORTB) || defined(__DOXYGEN__) + avr_gpio_setup_t portb; +#endif +#if defined(PORTC) || defined(__DOXYGEN__) + avr_gpio_setup_t portc; +#endif +#if defined(PORTD) || defined(__DOXYGEN__) + avr_gpio_setup_t portd; +#endif +#if defined(PORTE) || defined(__DOXYGEN__) + avr_gpio_setup_t porte; +#endif +#if defined(PORTF) || defined(__DOXYGEN__) + avr_gpio_setup_t portf; +#endif +#if defined(PORTG) || defined(__DOXYGEN__) + avr_gpio_setup_t portg; +#endif +#if defined(PORTH) || defined(__DOXYGEN__) + avr_gpio_setup_t porth; +#endif +#if defined(PORTJ) || defined(__DOXYGEN__) + avr_gpio_setup_t portj; +#endif +#if defined(PORTK) || defined(__DOXYGEN__) + avr_gpio_setup_t portk; +#endif +#if defined(PORTL) || defined(__DOXYGEN__) + avr_gpio_setup_t portl; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef avr_gpio_registers_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +#if defined(PORTA) || defined(__DOXYGEN__) +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 ((volatile avr_gpio_registers_t *)&PINA) +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 ((volatile avr_gpio_registers_t *)&PINB) +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 ((volatile avr_gpio_registers_t *)&PINC) +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 ((volatile avr_gpio_registers_t *)&PIND) +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 ((volatile avr_gpio_registers_t *)&PINE) +#endif + +#if defined(PORTF) || defined(__DOXYGEN__) +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 ((volatile avr_gpio_registers_t *)&PINF) +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 ((volatile avr_gpio_registers_t *)&PING) +#endif + +#if defined(PORTH) || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 ((volatile avr_gpio_registers_t *)&PINH) +#endif + +#if defined(PORTJ) || defined(__DOXYGEN__) +/** + * @brief GPIO port J identifier. + */ +#define IOPORT9 ((volatile avr_gpio_registers_t *)&PINJ) +#endif + +#if defined(PORTK) || defined(__DOXYGEN__) +/** + * @brief GPIO port K identifier. + */ +#define IOPORT10 ((volatile avr_gpio_registers_t *)&PINK) +#endif + +#if defined(PORTL) || defined(__DOXYGEN__) +/** + * @brief GPIO port L identifier. + */ +#define IOPORT11 ((volatile avr_gpio_registers_t *)&PINL) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config the architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->in) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->out) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->out = bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "sbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "cbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AVR/platform.dox b/os/hal/platforms/AVR/platform.dox new file mode 100644 index 000000000..bd6af1b1d --- /dev/null +++ b/os/hal/platforms/AVR/platform.dox @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup AVR_DRIVERS AVR Drivers + * @details This section describes all the supported drivers on the AVR + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup AVR_HAL AVR Initialization Support + * @details On the AVR platform the HAL driver is a stub and does not perform + * any platform-specific initialization, it still performs the + * initialization of the other drivers. + * + * @ingroup AVR_DRIVERS + */ + +/** + * @defgroup AVR_PAL AVR PAL Support + * @details The AVR PAL driver uses the PORT peripherals. + * + * @section avr_pal_1 Supported HW resources + * - PORTA. + * - PORTB. + * - PORTC. + * - PORTD. + * - PORTE. + * - PORTF. + * - PORTG. + * . + * @section avr_pal_2 AVR PAL driver implementation features + * The AVR PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section avr_pal_3 Supported PAL setup modes + * The AVR PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section avr_pal_4 Suboptimal behavior + * The AVR PORT is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * - Group set+reset function is not atomic. + * - Writing on pads/groups/ports programmed as input with pull-up + * resistor changes the resistor setting because the output latch is + * used for resistor selection. + * - The PORT registers layout on some devices is not regular (it does + * not have contiguous PIN, DDR, PORT registers in this order), such + * ports cannot be accessed using the PAL driver. For example, PORT F + * on ATmega128. Verify the user manual of your device. + * . + * @ingroup AVR_DRIVERS + */ + +/** + * @defgroup AVR_SERIAL AVR Serial Support + * @details The AVR Serial driver uses the USART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section avr_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART0. + * - USART1. + * . + * @section avr_serial_2 AVR Serial driver implementation features + * - Each USART can be independently enabled and programmed. + * - Fully interrupt driven. + * . + * @ingroup AVR_DRIVERS + */ + +/** + * @defgroup AVR_I2C AVR I2C Support + * @details The AVR I2C driver uses the TWI peripheral in an interrupt + * driven, implementation. + * + * @section avr_i2c Supported HW resources + * The i2c driver can support the following hardware resource: + * - I2C. + * . + * @ingroup AVR_DRIVERS + */ diff --git a/os/hal/platforms/AVR/platform.mk b/os/hal/platforms/AVR/platform.mk new file mode 100644 index 000000000..86a2c2eba --- /dev/null +++ b/os/hal/platforms/AVR/platform.mk @@ -0,0 +1,8 @@ +# List of all the AVR platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AVR/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/i2c_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AVR diff --git a/os/hal/platforms/AVR/serial_lld.c b/os/hal/platforms/AVR/serial_lld.c new file mode 100644 index 000000000..0b6127bb6 --- /dev/null +++ b/os/hal/platforms/AVR/serial_lld.c @@ -0,0 +1,360 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/serial_lld.c + * @brief AVR low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USART0 serial driver identifier. + * @note The name does not follow the convention used in the other ports + * (COMn) because a name conflict with the AVR headers. + */ +#if USE_AVR_USART0 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief USART1 serial driver identifier. + * @note The name does not follow the convention used in the other ports + * (COMn) because a name conflict with the AVR headers. + */ +#if USE_AVR_USART1 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + UBRR(SERIAL_DEFAULT_BITRATE), + USART_CHAR_SIZE_8 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(uint8_t sra, SerialDriver *sdp) { + flagsmask_t sts = 0; + uint8_t dor = 0; + uint8_t upe = 0; + uint8_t fe = 0; + +#if USE_AVR_USART0 + if (&SD1 == sdp) { + dor = (1 << DOR0); + upe = (1 << UPE0); + fe = (1 << FE0); + } +#endif + +#if USE_AVR_USART1 + if (&SD2 == sdp) { + dor = (1 << DOR1); + upe = (1 << UPE1); + fe = (1 << FE1); + } +#endif + + if (sra & dor) + sts |= SD_OVERRUN_ERROR; + if (sra & upe) + sts |= SD_PARITY_ERROR; + if (sra & fe) + sts |= SD_FRAMING_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if USE_AVR_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + UCSR0B |= (1 << UDRIE0); +} + +/** + * @brief USART0 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart0_init(const SerialConfig *config) { + + UBRR0L = config->sc_brr; + UBRR0H = config->sc_brr >> 8; + UCSR0A = 0; + UCSR0B = (1 << RXEN0) | (1 << TXEN0) | (1 << RXCIE0); + switch (config->sc_bits_per_char) { + case USART_CHAR_SIZE_5: + UCSR0C = 0; + break; + case USART_CHAR_SIZE_6: + UCSR0C = (1 << UCSZ00); + break; + case USART_CHAR_SIZE_7: + UCSR0C = (1 << UCSZ01); + break; + case USART_CHAR_SIZE_9: + UCSR0B |= (1 << UCSZ02); + UCSR0C = (1 << UCSZ00) | (1 << UCSZ01); + break; + case USART_CHAR_SIZE_8: + default: + UCSR0C = (1 << UCSZ00) | (1 << UCSZ01); + } +} + +/** + * @brief USART0 de-initialization. + */ +static void usart0_deinit(void) { + + UCSR0A = 0; + UCSR0B = 0; + UCSR0C = 0; +} +#endif + +#if USE_AVR_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + UCSR1B |= (1 << UDRIE1); +} + +/** + * @brief USART1 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart1_init(const SerialConfig *config) { + + UBRR1L = config->sc_brr; + UBRR1H = config->sc_brr >> 8; + UCSR1A = 0; + UCSR1B = (1 << RXEN1) | (1 << TXEN1) | (1 << RXCIE1); + switch (config->sc_bits_per_char) { + case USART_CHAR_SIZE_5: + UCSR1C = 0; + break; + case USART_CHAR_SIZE_6: + UCSR1C = (1 << UCSZ10); + break; + case USART_CHAR_SIZE_7: + UCSR1C = (1 << UCSZ11); + break; + case USART_CHAR_SIZE_9: + UCSR1B |= (1 << UCSZ12); + UCSR1C = (1 << UCSZ10) | (1 << UCSZ11); + break; + case USART_CHAR_SIZE_8: + default: + UCSR1C = (1 << UCSZ10) | (1 << UCSZ11); + } +} + +/** + * @brief USART1 de-initialization. + */ +static void usart1_deinit(void) { + + UCSR1A = 0; + UCSR1B = 0; + UCSR1C = 0; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_AVR_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0_RX_vect) { + uint8_t sra; + + CH_IRQ_PROLOGUE(); + + sra = UCSR0A; + if (sra & ((1 << DOR0) | (1 << UPE0) | (1 << FE0))) + set_error(sra, &SD1); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, UDR0); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART0 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0_UDRE_vect) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + UCSR0B &= ~(1 << UDRIE0); + else + UDR0 = b; + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_AVR_USART0 */ + +#if USE_AVR_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_RX_vect) { + uint8_t sra; + + CH_IRQ_PROLOGUE(); + + sra = UCSR1A; + if (sra & ((1 << DOR1) | (1 << UPE1) | (1 << FE1))) + set_error(sra, &SD2); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, UDR1); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_UDRE_vect) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + UCSR1B &= ~(1 << UDRIE1); + else + UDR1 = b; + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_AVR_USART1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_AVR_USART0 + sdObjectInit(&SD1, NULL, notify1); +#endif +#if USE_AVR_USART1 + sdObjectInit(&SD2, NULL, notify2); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_AVR_USART0 + if (&SD1 == sdp) { + usart0_init(config); + return; + } +#endif +#if USE_AVR_USART1 + if (&SD2 == sdp) { + usart1_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if USE_AVR_USART0 + if (&SD1 == sdp) + usart0_deinit(); +#endif +#if USE_AVR_USART1 + if (&SD2 == sdp) + usart1_deinit(); +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/AVR/serial_lld.h b/os/hal/platforms/AVR/serial_lld.h new file mode 100644 index 000000000..5a19befc7 --- /dev/null +++ b/os/hal/platforms/AVR/serial_lld.h @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AVR/serial_lld.h + * @brief AVR low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_AVR_USART0) || defined(__DOXYGEN__) +#define USE_AVR_USART0 TRUE +#endif + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_AVR_USART1) || defined(__DOXYGEN__) +#define USE_AVR_USART1 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AVR Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Initialization value for the BRR register. + */ + uint16_t sc_brr; + /** + * @brief Number of bits per character (USART_CHAR_SIZE_5 to USART_CHAR_SIZE_9). + */ + uint8_t sc_bits_per_char; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBRR(b) (((F_CPU / b) >> 4) - 1) + +/** + * @brief Macro for baud rate computation when U2Xn == 1. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBRR2x(b) (((F_CPU / b) >> 3) - 1) + +/** +* @brief Macro for baud rate computation. +* @note Make sure the final baud rate is within tolerance. +* @note This version uses floating point math for greater accuracy. +*/ +#define UBRR_F(b) ((((double) F_CPU / (double) b) / 16.0) - 0.5) + +/** +* @brief Macro for baud rate computation when U2Xn == 1. +* @note Make sure the final baud rate is within tolerance. +* @note This version uses floating point math for greater accuracy. +*/ +#define UBRR2x_F(b) ((((double) F_CPU / (double) b) / 8.0) - 0.5) + +#define USART_CHAR_SIZE_5 0 +#define USART_CHAR_SIZE_6 1 +#define USART_CHAR_SIZE_7 2 +#define USART_CHAR_SIZE_8 3 +#define USART_CHAR_SIZE_9 4 + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_AVR_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_AVR_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/LPC11Uxx.h new file mode 100644 index 000000000..81d37a704 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/LPC11Uxx.h @@ -0,0 +1,668 @@ + +/****************************************************************************************************//** + * @file LPC11Uxx.h + * + * + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * default LPC11Uxx Device Series + * + * @version V0.1 + * @date 21. March 2011 + * + * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 + * + * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, + * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 + * + *******************************************************************************************************/ + + + +/** @addtogroup NXP + * @{ + */ + +/** @addtogroup LPC11Uxx + * @{ + */ + +#ifndef __LPC11UXX_H__ +#define __LPC11UXX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + /* Interrupt Number Definition */ + +typedef enum { +// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ +FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ + FLEX_INT1_IRQn = 1, + FLEX_INT2_IRQn = 2, + FLEX_INT3_IRQn = 3, + FLEX_INT4_IRQn = 4, + FLEX_INT5_IRQn = 5, + FLEX_INT6_IRQn = 6, + FLEX_INT7_IRQn = 7, + GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ + GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ + Reserved0_IRQn = 10, /*!< Reserved Interrupt */ + Reserved1_IRQn = 11, + Reserved2_IRQn = 12, + Reserved3_IRQn = 13, + SSP1_IRQn = 14, /*!< SSP1 Interrupt */ + I2C_IRQn = 15, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ + SSP0_IRQn = 20, /*!< SSP0 Interrupt */ + UART_IRQn = 21, /*!< UART Interrupt */ + USB_IRQn = 22, /*!< USB IRQ Interrupt */ + USB_FIQn = 23, /*!< USB FIQ Interrupt */ + ADC_IRQn = 24, /*!< A/D Converter Interrupt */ + WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ + FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ + Reserved4_IRQn = 28, /*!< Reserved Interrupt */ + Reserved5_IRQn = 29, /*!< Reserved Interrupt */ + USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ + Reserved6_IRQn = 31, /*!< Reserved Interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ + +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +// ------------------------------------------------------------------------------------------------ +// ----- I2C ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) + */ + +typedef struct { /*!< (@ 0x40000000) I2C Structure */ + __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ + __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ + __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ + __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ + __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ + __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ + __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ + __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ + __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ + __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ + __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ + __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ +union{ + __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ + struct{ + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; + }; + }; +} LPC_I2C_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- WWDT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) + */ + +typedef struct { /*!< (@ 0x40004000) WWDT Structure */ + __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ + __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ + __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ + __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ + __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ + __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ + __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ +} LPC_WWDT_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- USART ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) + */ + +typedef struct { /*!< (@ 0x40008000) USART Structure */ + + union { + __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ + __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ + __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ + }; + + union { + __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ + __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ + }; + + union { + __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ + __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ + __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ + __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ + __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ + __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ + __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ + __I uint32_t RESERVED0[3]; + __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ + __I uint32_t RESERVED1; + __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ + __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ + __IO uint32_t SYNCCTRL; +} LPC_USART_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- Timer ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 + */ + +typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ + __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ + __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ + __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ + __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ + __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ + __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ + union { + __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ + struct{ + __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ + __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ + __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ + __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ + }; + }; + __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ + union{ + __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ + struct{ + __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ + __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ + __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ + __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ + }; + }; +__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ + __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ +} LPC_CTxxBx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- ADC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) + */ + +typedef struct { /*!< (@ 0x4001C000) ADC Structure */ + __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ + __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ + __I uint32_t RESERVED0[1]; + __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ + union{ + __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ + struct{ + __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ + __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ + __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ + __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ + __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ + __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ + __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ + __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ + }; + }; + __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ +} LPC_ADC_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- PMU ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) + */ + +typedef struct { /*!< (@ 0x40038000) PMU Structure */ + __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ + union{ + __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ + struct{ + __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ + __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ + __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ + __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ + }; + }; +} LPC_PMU_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- FLASHCTRL ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) + */ + +typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ + __I uint32_t RESERVED0[4]; + __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ + __I uint32_t RESERVED1[3]; + __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ + __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ + __I uint32_t RESERVED2[1]; + __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ + __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ + __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ + __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ + __I uint32_t RESERVED3[1001]; + __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ + __I uint32_t RESERVED4[1]; + __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ +} LPC_FLASHCTRL_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SSP0/1 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) + */ + +typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ + __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ + __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ + __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ + __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ +} LPC_SSPx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- IOCONFIG ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) + */ + +typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ + __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ + __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ + __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ + __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ + __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ + __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ + __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ + __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ + __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ + __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ + __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ + __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ + __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ + __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ + __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ + __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ + __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ + __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ + __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ + __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ + __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ + __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ + __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ + __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ + __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ + __IO uint32_t PIO1_1; + __IO uint32_t PIO1_2; + __IO uint32_t PIO1_3; + __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ + __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ + __IO uint32_t PIO1_9; + __IO uint32_t PIO1_10; + __IO uint32_t PIO1_11; + __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ + __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ + __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ + __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ + __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ + __IO uint32_t PIO1_17; + __IO uint32_t PIO1_18; + __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ + __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ + __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ + __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ + __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ + __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ + __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ + __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ + __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ + __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ + __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ + __IO uint32_t PIO1_30; + __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ +} LPC_IOCON_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SYSCON ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) + */ + +typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ + __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ + __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ + __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ + __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ + __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ + __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ + __I uint32_t RESERVED0[2]; + __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ + __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ + __I uint32_t RESERVED1[2]; + __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ + __I uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ + __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ + __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ + __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ + __I uint32_t RESERVED3[8]; + __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ + __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ + __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ + __I uint32_t RESERVED4[1]; + __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ + __I uint32_t RESERVED5[4]; + __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ + __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ + __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ + __I uint32_t RESERVED6[8]; + __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ + __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ + __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ + __I uint32_t RESERVED7[5]; + __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ + __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ + __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ + __I uint32_t RESERVED8[5]; + __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ + __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ + __I uint32_t RESERVED9[18]; + __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ + __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ + __I uint32_t RESERVED10[6]; + __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ + __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ + __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ + __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ + __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ + __I uint32_t RESERVED11[25]; + __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ + __I uint32_t RESERVED12[3]; + __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ + __I uint32_t RESERVED13[6]; + __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ + __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ + __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ + __I uint32_t RESERVED14[110]; + __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ +} LPC_SYSCON_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PIN_INT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) + */ + +typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ + __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ +} LPC_GPIO_PIN_INT_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_GROUP_INT0/1 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) + */ + +typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ + __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ + __I uint32_t RESERVED1[6]; + __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ +} LPC_GPIO_GROUP_INTx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- USB ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) + */ + +typedef struct { /*!< (@ 0x40080000) USB Structure */ + __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ + __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ + __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ + __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ + __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ + __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ + __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ + __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ + __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ + __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ + __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ + __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ + __I uint32_t RESERVED0[1]; + __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ +} LPC_USB_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PORT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) + */ + +typedef struct { + union { + struct { + __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ + __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ + }; + __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ + }; + __I uint32_t RESERVED0[1008]; + union { + struct { + __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ + __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ + }; + __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ + }; + uint32_t RESERVED1[960]; + __IO uint32_t DIR[2]; /* 0x2000 */ + uint32_t RESERVED2[30]; + __IO uint32_t MASK[2]; /* 0x2080 */ + uint32_t RESERVED3[30]; + __IO uint32_t PIN[2]; /* 0x2100 */ + uint32_t RESERVED4[30]; + __IO uint32_t MPIN[2]; /* 0x2180 */ + uint32_t RESERVED5[30]; + __IO uint32_t SET[2]; /* 0x2200 */ + uint32_t RESERVED6[30]; + __O uint32_t CLR[2]; /* 0x2280 */ + uint32_t RESERVED7[30]; + __O uint32_t NOT[2]; /* 0x2300 */ +} LPC_GPIO_Type; + + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral memory map ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C_BASE (0x40000000) +#define LPC_WWDT_BASE (0x40004000) +#define LPC_USART_BASE (0x40008000) +#define LPC_CT16B0_BASE (0x4000C000) +#define LPC_CT16B1_BASE (0x40010000) +#define LPC_CT32B0_BASE (0x40014000) +#define LPC_CT32B1_BASE (0x40018000) +#define LPC_ADC_BASE (0x4001C000) +#define LPC_PMU_BASE (0x40038000) +#define LPC_FLASHCTRL_BASE (0x4003C000) +#define LPC_SSP0_BASE (0x40040000) +#define LPC_SSP1_BASE (0x40058000) +#define LPC_IOCON_BASE (0x40044000) +#define LPC_SYSCON_BASE (0x40048000) +#define LPC_GPIO_PIN_INT_BASE (0x4004C000) +#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) +#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) +#define LPC_USB_BASE (0x40080000) +#define LPC_GPIO_BASE (0x50000000) + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral declaration ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) +#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) +#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) +#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) +#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) +#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) +#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) +#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) +#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) +#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) +#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) +#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) +#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) +#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) +#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) +#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group (null) */ +/** @} */ /* End of group LPC11Uxx */ + +#ifdef __cplusplus +} +#endif + + +#endif // __LPC11UXX_H__ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.c b/os/hal/platforms/LPC11Uxx/ext_lld.c new file mode 100644 index 000000000..81cdaf4aa --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/ext_lld.c @@ -0,0 +1,167 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/ext_lld.c + * @brief LPC11Uxx EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + int i; + + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<19); + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) + ext_lld_channel_enable(extp, i); + else + ext_lld_channel_disable(extp, i); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + int i; + + if (extp->state == EXT_ACTIVE) + for (i = 0; i < EXT_MAX_CHANNELS; i++) + ext_lld_exti_irq_disable(i); + + LPC_GPIO_PIN_INT->ISEL = 0; + LPC_GPIO_PIN_INT->CIENR = EXT_CHANNELS_MASK; + LPC_GPIO_PIN_INT->RISE = EXT_CHANNELS_MASK; + LPC_GPIO_PIN_INT->FALL = EXT_CHANNELS_MASK; + LPC_GPIO_PIN_INT->IST = EXT_CHANNELS_MASK; + + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<19); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + /* program the IOpin for this channel */ + LPC_SYSCON->PINTSEL[channel] = extp->config->channels[channel].iopin; + + /* Programming edge irq enables */ + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + LPC_GPIO_PIN_INT->SIENR = (1 << channel); + else + LPC_GPIO_PIN_INT->CIENR = (1 << channel); + + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + LPC_GPIO_PIN_INT->SIENF = (1 << channel); + else + LPC_GPIO_PIN_INT->CIENF = (1 << channel); + + LPC_GPIO_PIN_INT->RISE = (1<FALL = (1<IST = (1<ISEL &= ~(1 << channel); + LPC_GPIO_PIN_INT->CIENR = (1 << channel); + LPC_GPIO_PIN_INT->RISE = (1 << channel); + LPC_GPIO_PIN_INT->FALL = (1 << channel); + LPC_GPIO_PIN_INT->IST = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.h b/os/hal/platforms/LPC11Uxx/ext_lld.h new file mode 100644 index 000000000..9ec20f9f1 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/ext_lld.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/ext_lld.h + * @brief LPC11Uxx EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 8 + +/** + * @brief Mask of the available channels. + */ +#define EXT_CHANNELS_MASK ((1 << EXT_MAX_CHANNELS) - 1) + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + + * @brief EXT channel callback reason. + */ +typedef uint32_t expreason_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, + expchannel_t channel, + expreason_t reason); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint8_t mode; + /** + * @brief IO Pin. + */ + uint8_t iopin; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.c b/os/hal/platforms/LPC11Uxx/ext_lld_isr.c new file mode 100644 index 000000000..818d493e3 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/ext_lld_isr.c @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/ext_lld_isr.c + * @brief LPC11Uxx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +static void ext_lld_interrupt( uint32_t n ) { + uint32_t reason; + + reason = ((LPC_GPIO_PIN_INT->RISE)>> n ) & 0x01; + reason |= ((LPC_GPIO_PIN_INT->FALL)>>(n-1)) & 0x02; + LPC_GPIO_PIN_INT->RISE = (1<FALL = (1<IST = (1<channels[n].cb(&EXTD1, n, reason); +} + +/** + * @brief EXT[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector40) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(0); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector44) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(1); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector48) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(2); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector4C) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(3); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector50) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(4); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[5] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector54) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(5); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[6] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector58) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(6); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[7] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector5C) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(7); + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +static const uint8_t LPC11_EXT_EXTIn_IRQ_PRIORITY[] = + { LPC11_EXT_EXTI0_IRQ_PRIORITY, + LPC11_EXT_EXTI1_IRQ_PRIORITY, + LPC11_EXT_EXTI2_IRQ_PRIORITY, + LPC11_EXT_EXTI3_IRQ_PRIORITY, + LPC11_EXT_EXTI4_IRQ_PRIORITY, + LPC11_EXT_EXTI5_IRQ_PRIORITY, + LPC11_EXT_EXTI6_IRQ_PRIORITY, + LPC11_EXT_EXTI7_IRQ_PRIORITY }; + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable( uint32_t exti_n ) { + + nvicEnableVector(FLEX_INT0_IRQn + exti_n, + CORTEX_PRIORITY_MASK(LPC11_EXT_EXTIn_IRQ_PRIORITY[exti_n])); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable( uint32_t exti_n ) { + + nvicDisableVector(FLEX_INT0_IRQn + exti_n); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.h b/os/hal/platforms/LPC11Uxx/ext_lld_isr.h new file mode 100644 index 000000000..4fbbff862 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/ext_lld_isr.h @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/ext_lld_isr.h + * @brief LPC11Uxx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI0_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI2_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI3_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI4_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI5 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI5_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI6 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI6_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI7 interrupt priority level setting. + */ +#if !defined(LPC11_EXT_EXTI7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11_EXT_EXTI7_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable( uint32_t exti_n ); + void ext_lld_exti_irq_disable( uint32_t exti_n ); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.c b/os/hal/platforms/LPC11Uxx/gpt_lld.c new file mode 100644 index 000000000..15a1c6068 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.c @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/gpt_lld.c + * @brief LPC11Uxx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B0 */ + +#if LPC_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_CT16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_CT16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_CT32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_CT32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.h b/os/hal/platforms/LPC11Uxx/gpt_lld.h new file mode 100644 index 000000000..674960c7b --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.h @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/gpt_lld.h + * @brief LPC11Uxx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC_GPT_USE_CT16B0 && !LPC_GPT_USE_CT16B1 && \ + !LPC_GPT_USE_CT32B0 && !LPC_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_CTxxBx_Type *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c new file mode 100644 index 000000000..0e795c1a0 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/hal_lld.c @@ -0,0 +1,116 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/hal_lld.c + * @brief LPC11Uxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC11Uxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~3) | + LPC_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC_SYSPLLCTRL_MSEL | LPC_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.h b/os/hal/platforms/LPC11Uxx/hal_lld.h new file mode 100644 index 000000000..057dd47e3 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/hal_lld.h @@ -0,0 +1,218 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC11Uxx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC11Uxx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC_SYSPLL_MUL 4 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__) +#define LPC_SYSOSCCTRL 0 +#else +#define LPC_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC_SYSPLLCLKIN SYSOSCCLK +#elif LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC_SYSPLL_MUL >= 1) && (LPC_SYSPLL_MUL <= 32) || defined(__DOXYGEN__) +#define LPC_SYSPLLCTRL_MSEL (LPC_SYSPLL_MUL - 1) +#else +#error "LPC_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC_SYSPLL_DIV == 4 +#define LPC_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC_SYSPLL_DIV == 8 +#define LPC_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC_SYSPLL_DIV == 16 +#define LPC_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC_SYSPLLCCO (LPC_SYSPLLCLKIN * LPC_SYSPLL_MUL * \ + LPC_SYSPLL_DIV) + +#if (LPC_SYSPLLCCO < 156000000) || (LPC_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC_SYSPLLCLKOUT (LPC_SYSPLLCCO / LPC_SYSPLL_DIV) + +#if (LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC_MAINCLK IRCOSCCLK +#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC_MAINCLK LPC_SYSPLLCLKIN +#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC_MAINCLK WDGOSCCLK +#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC_MAINCLK LPC_SYSPLLCLKOUT +#else +#error "invalid LPC_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC_SYSCLK (LPC_MAINCLK / LPC_SYSABHCLK_DIV) +#if LPC_SYSCLK > 50000000 +#error "AHB clock frequency out of the acceptable range (50MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC_FLASHCFG_FLASHTIM 0 +#elif LPC_SYSCLK <= 40000000 +#define LPC_FLASHCFG_FLASHTIM 1 +#else +#define LPC_FLASHCFG_FLASHTIM 2 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.c b/os/hal/platforms/LPC11Uxx/pal_lld.c new file mode 100644 index 000000000..0b9d21391 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/pal_lld.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/pal_lld.c + * @brief LPC11Uxx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC11Uxx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC11Uxx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO->DIR[0] = config->P0.dir; + LPC_GPIO->DIR[1] = config->P1.dir; + LPC_GPIO->PIN[0] = config->P0.data; + LPC_GPIO->PIN[1] = config->P1.data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + LPC_GPIO->DIR[port] &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + LPC_GPIO->DIR[port] |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.h b/os/hal/platforms/LPC11Uxx/pal_lld.h new file mode 100644 index 000000000..a5072e70b --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/pal_lld.h @@ -0,0 +1,311 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/pal_lld.h + * @brief LPC11Uxx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + gpio_setup_t P1; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef uint32_t ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 0 +#define GPIO0 0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 1 +#define GPIO1 1 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (LPC_GPIO->PIN[(port)]) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) (LPC_GPIO->SET[(port)]) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) (LPC_GPIO->PIN[(port)] = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) (LPC_GPIO->SET[(port)] = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) (LPC_GPIO->CLR[(port)] = (bits)) + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @notapi + */ +#define pal_lld_toggleport(port, bits) (LPC_GPIO->NOT[(port)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) \ + (LPC_GPIO->B[((port) * 32) + (pad)]) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((LPC_GPIO->B[((port) * 32) + (pad)]) = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (LPC_GPIO->SET[(port)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (LPC_GPIO->CLR[(port)] = 1 << (pad)) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) \ + (LPC_GPIO->NOT[(port)] = 1 << (pad)) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/platform.mk b/os/hal/platforms/LPC11Uxx/platform.mk new file mode 100644 index 000000000..508238833 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/platform.mk @@ -0,0 +1,11 @@ +# List of all the LPC11Uxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld_isr.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.c b/os/hal/platforms/LPC11Uxx/serial_lld.c new file mode 100644 index 000000000..17587cbb0 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/serial_lld.c @@ -0,0 +1,296 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/serial_lld.c + * @brief LPC11Uxx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * + * @param[in] sdp communication channel associated to the USART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_USART_Type *u = sdp->uart; + + uint32_t div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief USART de-initialization. + * + * @param[in] u pointer to an USART I/O block + */ +static void uart_deinit(LPC_USART_Type *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_USART_Type *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_USART_Type *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector94) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_USART; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UARTCLKDIV = LPC_SERIAL_UART0CLKDIV; + nvicEnableVector(UART_IRQn, + CORTEX_PRIORITY_MASK(LPC_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UARTCLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.h b/os/hal/platforms/LPC11Uxx/serial_lld.h new file mode 100644 index 000000000..162e9ae16 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/serial_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/serial_lld.h + * @brief LPC11Uxx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC_SERIAL_UART0CLKDIV < 1) || (LPC_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC_SERIAL_FIFO_PRELOAD < 1) || (LPC_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC_SERIAL_UART0_PCLK \ + (LPC_MAINCLK / LPC_SERIAL_UART0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC11xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_USART_Type *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.c b/os/hal/platforms/LPC11Uxx/spi_lld.c new file mode 100644 index 000000000..67282e8a4 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.c @@ -0,0 +1,391 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/spi_lld.c + * @brief LPC11Uxx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ? + LPC_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; +#endif /* LPC_SPI_USE_SSP0 */ + +#if LPC_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; +#endif /* LPC_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.h b/os/hal/platforms/LPC11Uxx/spi_lld.h new file mode 100644 index 000000000..9d15dcee2 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.h @@ -0,0 +1,311 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/spi_lld.h + * @brief LPC11Uxx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP1 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC_SPI_SSP0CLKDIV < 1) || (LPC_SPI_SSP0CLKDIV > 255) +#error "invalid LPC_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC_SPI_SSP1CLKDIV < 1) || (LPC_SPI_SSP1CLKDIV > 255) +#error "invalid LPC_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC_SPI_SSP0_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC_SPI_SSP1_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSPx_Type *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h new file mode 100644 index 000000000..e490d17dc --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC11Uxx.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File + * for the NXP LPC11Uxx Device Series + * @version V1.10 + * @date 24. November 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC11Uxx_H +#define __SYSTEM_LPC11Uxx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC11Uxx_H */ diff --git a/os/hal/platforms/LPC11xx/LPC11xx.h b/os/hal/platforms/LPC11xx/LPC11xx.h new file mode 100644 index 000000000..3f96459c7 --- /dev/null +++ b/os/hal/platforms/LPC11xx/LPC11xx.h @@ -0,0 +1,561 @@ +/**************************************************************************** + * $Id:: LPC11xx.h 4070 2010-07-30 03:16:37Z usb00423 $ + * Project: NXP LPC11xx software example + * + * Description: + * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * NXP LPC11xx Device Series + * + **************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. +****************************************************************************/ +#ifndef __LPC11xx_H__ +#define __LPC11xx_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup LPC11xx_Definitions LPC11xx Definitions + This file defines all structures and symbols for LPC11xx: + - Registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions + Configuration of the Cortex-M0 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + CAN_IRQn = 13, /*!< CAN Interrupt */ + SSP1_IRQn = 14, /*!< SSP1 Interrupt */ + I2C_IRQn = 15, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ + SSP0_IRQn = 20, /*!< SSP0 Interrupt */ + UART_IRQn = 21, /*!< UART Interrupt */ + Reserved0_IRQn = 22, /*!< Reserved Interrupt */ + Reserved1_IRQn = 23, + ADC_IRQn = 24, /*!< A/D Converter Interrupt */ + WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ + FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ + EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC11xx_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_LPC11xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block + @{ +*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ + __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ + __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ + __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ + uint32_t RESERVED0[4]; + + __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ + __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ + __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */ + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ + __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ + uint32_t RESERVED3[10]; + + __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ + __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ + __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ + uint32_t RESERVED5[4]; + __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */ + __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */ + __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */ + uint32_t RESERVED6[4]; + + __IO uint32_t SYSTICKCLKDIV; /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */ + uint32_t RESERVED7[7]; + + __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */ + __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */ + __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */ + uint32_t RESERVED8[1]; + __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ + __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ + __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ + uint32_t RESERVED9[5]; + + __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ + __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */ + uint32_t RESERVED10[18]; + __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ + uint32_t RESERVED11[1]; + __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 System tick counter calibration (R/W) */ + uint32_t RESERVED12; + __IO uint32_t MAINREGVOUT0CFG; /*!< Offset: 0x160 Main Regulator Voltage 0 Configuration */ + __IO uint32_t MAINREGVOUT1CFG; /*!< Offset: 0x164 Main Regulator Voltage 1 Configuration */ + uint32_t RESERVED13[38]; + + __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */ + __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ + __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */ + __IO uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/W) */ + __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */ + __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */ + __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */ + __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */ + uint32_t RESERVED17[4]; + + __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ + __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ + __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ + uint32_t RESERVED15[101]; + __O uint32_t VOUTCFGPROT; /*!< Offset: 0x3D0 Voltage Output Configuration Protection Register (W) */ + uint32_t RESERVED16[8]; + __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ +} LPC_SYSCON_TypeDef; +/*@}*/ /* end of group LPC11xx_SYSCON */ + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block + @{ +*/ +typedef struct +{ + __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */ + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */ + __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */ + __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */ + __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */ + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */ + + __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */ + __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */ + __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */ + __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */ + __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */ + __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */ + __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */ + __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */ + + __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */ + __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */ + __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */ + __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */ + __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */ + __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */ + __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */ + __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */ + + __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */ + __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */ + __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */ + __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */ + __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */ + __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */ + __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */ + __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */ + + __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */ + __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */ + __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */ + __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */ + __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */ + __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */ + __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */ + __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */ + + __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */ + __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */ + __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */ + __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */ + __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */ + __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */ + __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */ + __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */ +} LPC_IOCON_TypeDef; +/*@}*/ /* end of group LPC11xx_IOCON */ + + +/*------------- Power Management Unit (PMU) --------------------------*/ +/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit + @{ +*/ +typedef struct +{ + __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ + __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ + __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ + __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ + __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ + __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */ +} LPC_PMU_TypeDef; +/*@}*/ /* end of group LPC11xx_PMU */ + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output + @{ +*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */ + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */ + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */ + __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */ + __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */ + __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */ + __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */ + __IO uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */ + __IO uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */ + __IO uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (R/W) */ +} LPC_GPIO_TypeDef; +/*@}*/ /* end of group LPC11xx_GPIO */ + +/*------------- Timer (TMR) --------------------------------------------------*/ +/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer + @{ +*/ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ + __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ + __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ + __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ + __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ + __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ + __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ + __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ + __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ + __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ + uint32_t RESERVED1[3]; + __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ + __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */ +} LPC_TMR_TypeDef; +/*@}*/ /* end of group LPC11xx_TMR */ + + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter + @{ +*/ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED1; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ + uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ + __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ + __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ + __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */ +} LPC_UART_TypeDef; +/*@}*/ /* end of group LPC11xx_UART */ + + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port + @{ +*/ +typedef struct +{ + __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ + __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ + __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ + __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ + __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ + __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ + __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ + __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ + __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ +} LPC_SSP_TypeDef; +/*@}*/ /* end of group LPC11xx_SSP */ + + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface + @{ +*/ +typedef struct +{ + __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ + __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ + __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ + __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ + __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ + __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ + __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ + __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ + __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ + __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ + __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ + __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ + __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ + __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ + __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ + __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ +} LPC_I2C_TypeDef; +/*@}*/ /* end of group LPC11xx_I2C */ + + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer + @{ +*/ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ + __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ + __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ + uint32_t RESERVED0; + __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ + __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ +} LPC_WDT_TypeDef; +/*@}*/ /* end of group LPC11xx_WDT */ + + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter + @{ +*/ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ + __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ + __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ + __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ +} LPC_ADC_TypeDef; +/*@}*/ /* end of group LPC11xx_ADC */ + + +/*------------- CAN Controller (CAN) ----------------------------*/ +/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) + @{ +*/ +typedef struct +{ + __IO uint32_t CNTL; /* 0x000 */ + __IO uint32_t STAT; + __IO uint32_t EC; + __IO uint32_t BT; + __IO uint32_t INT; + __IO uint32_t TEST; + __IO uint32_t BRPE; + uint32_t RESERVED0; + __IO uint32_t IF1_CMDREQ; /* 0x020 */ + __IO uint32_t IF1_CMDMSK; + __IO uint32_t IF1_MSK1; + __IO uint32_t IF1_MSK2; + __IO uint32_t IF1_ARB1; + __IO uint32_t IF1_ARB2; + __IO uint32_t IF1_MCTRL; + __IO uint32_t IF1_DA1; + __IO uint32_t IF1_DA2; + __IO uint32_t IF1_DB1; + __IO uint32_t IF1_DB2; + uint32_t RESERVED1[13]; + __IO uint32_t IF2_CMDREQ; /* 0x080 */ + __IO uint32_t IF2_CMDMSK; + __IO uint32_t IF2_MSK1; + __IO uint32_t IF2_MSK2; + __IO uint32_t IF2_ARB1; + __IO uint32_t IF2_ARB2; + __IO uint32_t IF2_MCTRL; + __IO uint32_t IF2_DA1; + __IO uint32_t IF2_DA2; + __IO uint32_t IF2_DB1; + __IO uint32_t IF2_DB2; + uint32_t RESERVED2[21]; + __I uint32_t TXREQ1; /* 0x100 */ + __I uint32_t TXREQ2; + uint32_t RESERVED3[6]; + __I uint32_t ND1; /* 0x120 */ + __I uint32_t ND2; + uint32_t RESERVED4[6]; + __I uint32_t IR1; /* 0x140 */ + __I uint32_t IR2; + uint32_t RESERVED5[6]; + __I uint32_t MSGV1; /* 0x160 */ + __I uint32_t MSGV2; + uint32_t RESERVED6[6]; + __IO uint32_t CLKDIV; /* 0x180 */ +} LPC_CAN_TypeDef; +/*@}*/ /* end of group LPC11xx_CAN */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC11xx_H__ */ diff --git a/os/hal/platforms/LPC11xx/ext_lld.c b/os/hal/platforms/LPC11xx/ext_lld.c new file mode 100644 index 000000000..c22cd83be --- /dev/null +++ b/os/hal/platforms/LPC11xx/ext_lld.c @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/ext_lld.c + * @brief LPC11xx EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD0 driver identifier. + */ +#if LPC11xx_EXT_USE_EXT0 || defined(__DOXYGEN__) +EXTDriver EXTD0; +#endif + +/** + * @brief EXTD1 driver identifier. + */ +#if LPC11xx_EXT_USE_EXT1 || defined(__DOXYGEN__) +EXTDriver EXTD1; +#endif + +/** + * @brief EXTD2 driver identifier. + */ +#if LPC11xx_EXT_USE_EXT2 || defined(__DOXYGEN__) +EXTDriver EXTD2; +#endif + +/** + * @brief EXTD3 driver identifier. + */ +#if LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__) +EXTDriver EXTD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ +#if LPC11xx_EXT_USE_EXT0 + extObjectInit(&EXTD0); + EXTD0.gpio = LPC_GPIO0; +#endif + +#if LPC11xx_EXT_USE_EXT1 + extObjectInit(&EXTD1); + EXTD1.gpio = LPC_GPIO1; +#endif + +#if LPC11xx_EXT_USE_EXT2 + extObjectInit(&EXTD2); + EXTD2.gpio = LPC_GPIO2; +#endif + +#if LPC11xx_EXT_USE_EXT3 + extObjectInit(&EXTD3); + EXTD3.gpio = LPC_GPIO3; +#endif +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + int i; + + /* Configure all pins as edge sensitive */ +#if LPC11xx_EXT_USE_EXT0 + if (extp == &EXTD0) { + LPC_GPIO0->IS = 0; + ext_lld_exti_irq_enable(EXTI0_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT1 + if (extp == &EXTD1) { + LPC_GPIO1->IS = 0; + ext_lld_exti_irq_enable(EXTI1_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT2 + if (extp == &EXTD2) { + LPC_GPIO2->IS = 0; + ext_lld_exti_irq_enable(EXTI2_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT3 + if (extp == &EXTD3) { + LPC_GPIO3->IS = 0; + ext_lld_exti_irq_enable(EXTI3_IRQ); + } +#endif + + /* Configuration of autostart channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) + ext_lld_channel_enable(extp, i); + else + ext_lld_channel_disable(extp, i); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + LPC_GPIO_TypeDef * gp = extp->gpio; + + if (extp->state == EXT_ACTIVE) { +#if LPC11xx_EXT_USE_EXT0 + if (extp == &EXTD0) { + ext_lld_exti_irq_disable(EXTI0_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT1 + if (extp == &EXTD1) { + ext_lld_exti_irq_disable(EXTI1_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT2 + if (extp == &EXTD2) { + ext_lld_exti_irq_disable(EXTI2_IRQ); + } +#endif + +#if LPC11xx_EXT_USE_EXT3 + if (extp == &EXTD3) { + ext_lld_exti_irq_disable(EXTI3_IRQ); + } +#endif + } + + gp->IE = 0; + gp->IC = 0xFFFFFFFF; + __NOP(); + __NOP(); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + LPC_GPIO_TypeDef * gp; + + gp = extp->gpio; + + /* Programming edge irq enables */ + if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES) + gp->IBE |= (1 << channel); + else { + gp->IBE &= ~(1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + gp->IEV |= (1 << channel); + else + gp->IEV &= (1 << channel); + } + + gp->IC = (1 << channel); /* Clear interrupt on selected channel */ + __NOP(); + __NOP(); + + gp->IE |= (1 << channel); /* Interrupt on selected channel + is not masked */ +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + LPC_GPIO_TypeDef * gp; + + gp = extp->gpio; + + gp->IE &= ~(1 << channel); /* Mask interrupt on selected channel */ + gp->IC = (1 << channel); /* Clear interrupt on selected channel */ + __NOP(); + __NOP(); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/ext_lld.h b/os/hal/platforms/LPC11xx/ext_lld.h new file mode 100644 index 000000000..9a05f6d22 --- /dev/null +++ b/os/hal/platforms/LPC11xx/ext_lld.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/ext_lld.h + * @brief LPC11xx EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 12 + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief EXT0 driver enable switch. + * @details If set to @p TRUE the support for EXT0 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_EXT_USE_EXT0) || defined(__DOXYGEN__) +#define LPC11xx_EXT_USE_EXT0 FALSE +#endif + +/** + * @brief EXT1 driver enable switch. + * @details If set to @p TRUE the support for EXT1 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_EXT_USE_EXT1) || defined(__DOXYGEN__) +#define LPC11xx_EXT_USE_EXT1 FALSE +#endif + +/** + * @brief EXT2 driver enable switch. + * @details If set to @p TRUE the support for EXT2 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_EXT_USE_EXT2) || defined(__DOXYGEN__) +#define LPC11xx_EXT_USE_EXT2 FALSE +#endif + +/** + * @brief EXT3 driver enable switch. + * @details If set to @p TRUE the support for EXT3 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_EXT_USE_EXT3) || defined(__DOXYGEN__) +#define LPC11xx_EXT_USE_EXT3 FALSE +#endif +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint8_t mode; + + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ + LPC_GPIO_TypeDef *gpio; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_EXT_USE_EXT0 || !defined(__DOXYGEN__) +extern EXTDriver EXTD0; +#endif + +#if LPC11xx_EXT_USE_EXT1 || !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#if LPC11xx_EXT_USE_EXT2 || !defined(__DOXYGEN__) +extern EXTDriver EXTD2; +#endif + +#if LPC11xx_EXT_USE_EXT3 || !defined(__DOXYGEN__) +extern EXTDriver EXTD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/ext_lld_isr.c b/os/hal/platforms/LPC11xx/ext_lld_isr.c new file mode 100644 index 000000000..9d3b92eeb --- /dev/null +++ b/os/hal/platforms/LPC11xx/ext_lld_isr.c @@ -0,0 +1,176 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/ext_lld_isr.c + * @brief LPC11xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if LPC11xx_EXT_USE_EXT0 || LPC11xx_EXT_USE_EXT1 || LPC11xx_EXT_USE_EXT2 || \ + LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__) +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void ext_lld_serve_interrupt(EXTDriver *extp) { + uint32_t port_stat; + uint8_t i; + + port_stat = extp->gpio->MIS; /* Read interrupt status */ + extp->gpio->IC = port_stat; /* Clear interrupt flags */ + + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (port_stat & 0x01) { + extp->config->channels[i].cb(extp, i); + } + port_stat = port_stat >> 1; + } +} +#endif +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief PIO0 interrupt handler. + * + * @isr + */ +#if LPC11xx_EXT_USE_EXT0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(VectorBC) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD0); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC11xx_EXT_USE_EXT1 || defined(__DOXYGEN__) +/** + * @brief PIO1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB8) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD1); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC11xx_EXT_USE_EXT2 || defined(__DOXYGEN__) +/** + * @brief PIO2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB4) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD2); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__) +/** + * @brief PIO_3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB0) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD3); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(extirq_t irqn) { + + uint32_t pmask; + + switch (irqn) { + case EXTI0_IRQ: + pmask = LPC11xx_EXT_EXTI0_IRQ_PRIORITY; + break; + case EXTI1_IRQ: + pmask = LPC11xx_EXT_EXTI1_IRQ_PRIORITY; + break; + case EXTI2_IRQ: + pmask = LPC11xx_EXT_EXTI2_IRQ_PRIORITY; + break; + case EXTI3_IRQ: + pmask = LPC11xx_EXT_EXTI3_IRQ_PRIORITY; + break; + } + nvicEnableVector(EINT0_IRQn - irqn, CORTEX_PRIORITY_MASK(pmask)); + +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(extirq_t irqn) { + + nvicDisableVector(EINT0_IRQn - irqn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/ext_lld_isr.h b/os/hal/platforms/LPC11xx/ext_lld_isr.h new file mode 100644 index 000000000..442d109da --- /dev/null +++ b/os/hal/platforms/LPC11xx/ext_lld_isr.h @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/ext_lld_isr.h + * @brief LPC11xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EXTI0_IRQ 0 +#define EXTI1_IRQ 1 +#define EXTI2_IRQ 2 +#define EXTI3_IRQ 3 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(LPC11xx_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_EXT_EXTI0_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(LPC11xx_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_EXT_EXTI1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(LPC11xx_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_EXT_EXTI2_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(LPC11xx_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_EXT_EXTI3_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT irq port identifier. + */ +typedef uint32_t extirq_t; +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(extirq_t irqn); + void ext_lld_exti_irq_disable(extirq_t irqn); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/gpt_lld.c b/os/hal/platforms/LPC11xx/gpt_lld.c new file mode 100644 index 000000000..82a51f50a --- /dev/null +++ b/os/hal/platforms/LPC11xx/gpt_lld.c @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/gpt_lld.c + * @brief LPC11xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC11xx_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC11xx_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC11xx_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC11xx_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC11xx_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT16B0 */ + +#if LPC11xx_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT16B0 */ + +#if LPC11xx_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT32B0 */ + +#if LPC11xx_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC11xx_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_TMR16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC11xx_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_TMR16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC11xx_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_TMR32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC11xx_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_TMR32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC11xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC11xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC11xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC11xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC11xx_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC11xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC11xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC11xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC11xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC11xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/gpt_lld.h b/os/hal/platforms/LPC11xx/gpt_lld.h new file mode 100644 index 000000000..cdf7ddd0a --- /dev/null +++ b/os/hal/platforms/LPC11xx/gpt_lld.h @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/gpt_lld.h + * @brief LPC11xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC11xx_GPT_USE_CT16B0 && !LPC11xx_GPT_USE_CT16B1 && \ + !LPC11xx_GPT_USE_CT32B0 && !LPC11xx_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_TMR_TypeDef *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC11xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC11xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC11xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/hal_lld.c b/os/hal/platforms/LPC11xx/hal_lld.c new file mode 100644 index 000000000..af14d406a --- /dev/null +++ b/os/hal/platforms/LPC11xx/hal_lld.c @@ -0,0 +1,120 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/hal_lld.c + * @brief LPC11xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Register missing in NXP header file. + */ +#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC11xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc111x_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/hal_lld.h b/os/hal/platforms/LPC11xx/hal_lld.h new file mode 100644 index 000000000..ee778dd47 --- /dev/null +++ b/os/hal/platforms/LPC11xx/hal_lld.h @@ -0,0 +1,219 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC11xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC11xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLL_MUL 4 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC11xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC11xx_SYSOSCCTRL 0 +#else +#define LPC11xx_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC11xx_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1) +#else +#error "LPC11xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC11xx_SYSPLL_DIV == 4 +#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC11xx_SYSPLL_DIV == 8 +#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC11xx_SYSPLL_DIV == 16 +#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \ + LPC11xx_SYSPLL_DIV) + +#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV) + +#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC11xx_MAINCLK IRCOSCCLK +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC11xx_MAINCLK WDGOSCCLK +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT +#else +#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV) +#if LPC11xx_SYSCLK > 50000000 +#error "AHB clock frequency out of the acceptable range (50MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC11xx_FLASHCFG_FLASHTIM 0 +#elif LPC11xx_SYSCLK <= 40000000 +#define LPC11xx_FLASHCFG_FLASHTIM 1 +#else +#define LPC11xx_FLASHCFG_FLASHTIM 2 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc111x_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/i2c_lld.c b/os/hal/platforms/LPC11xx/i2c_lld.c new file mode 100644 index 000000000..c68f11460 --- /dev/null +++ b/os/hal/platforms/LPC11xx/i2c_lld.c @@ -0,0 +1,438 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx I2C driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + + +/** + * @file LPC11xx/i2c_lld.h + * @brief LPC11xx I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +I2CDriver I2CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Handling of stalled I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_safety_timeout(void *p) { + I2CDriver *i2cp = (I2CDriver *)p; + + chSysLockFromIsr(); + if (i2cp->thread) { + Thread *tp = i2cp->thread; + i2cp->thread = NULL; + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + } + chSysUnlockFromIsr(); +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) { + i2cflags_t error = 0; + + switch (status) { + case I2C_STATE_ARB_LOST: + error = I2CD_ARBITRATION_LOST; + break; + case I2C_STATE_BUS_ERROR: + error = I2CD_BUS_ERROR; + break; + case I2C_STATE_MS_SLAR_NACK: + case I2C_STATE_MS_TDAT_NACK: + case I2C_STATE_MS_SLAW_NACK: + error = I2CD_ACK_FAILURE ; + break; + } + + /* If some error has been identified then sends wakes the waiting thread.*/ + i2cp->errors = error; + wakeup_isr(i2cp, RDY_RESET); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +/** + * @brief I2C event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(Vector7C) { + uint32_t status; + + CH_IRQ_PROLOGUE(); + status = LPC_I2C->STAT; + switch(status) { + case I2C_STATE_MS_START: /* A START condition has been transmitted. */ + if (I2CD1.txbytes > 0) { + LPC_I2C->DAT = I2CD1.addr; /* Write slave address with WR bit. */ + } + else { + LPC_I2C->DAT = I2CD1.addr | I2C_RD_BIT; /* Write slave address with RD bit. */ + } + + LPC_I2C->CONCLR = I2C_CONCLR_STAC | I2C_CONCLR_SIC; /* Clear START and SI bit. */ + break; + + case I2C_STATE_MS_SLAR_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + case I2C_STATE_MS_TDAT_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + case I2C_STATE_MS_SLAW_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + i2c_lld_serve_error_interrupt(&I2CD1, status); + break; + + case I2C_STATE_MS_SLAW_ACK: /* SLA + W has been transmitted, ACK has been received. */ + case I2C_STATE_MS_TDAT_ACK: /* Data byte has been transmitted, ACK has been received. */ + if (I2CD1.txbytes > 0) { + LPC_I2C->DAT = *I2CD1.txbuf++; /* Write data. */ + I2CD1.txbytes--; + } + else { + if (I2CD1.rxbytes > 0) { + LPC_I2C->CONSET = I2C_CONSET_STO | I2C_CONSET_STA; /* Set START and STOP bit. */ + } /* STOP bit will be transmit, then START bit. */ + else { + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + wakeup_isr(&I2CD1, RDY_OK); + } + } + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + break; + + case I2C_STATE_MS_SLAR_ACK: /* SLA + R has been transmitted, ACK has been received. */ + case I2C_STATE_MS_RDAT_ACK: /* Data byte has been received, ACK has been returned. */ + if (status == I2C_STATE_MS_RDAT_ACK) { + *I2CD1.rxbuf++ = LPC_I2C->DAT; /* Read data */ + I2CD1.rxbytes--; + } + if (I2CD1.rxbytes == 1) { + LPC_I2C->CONCLR = I2C_CONCLR_SIC | I2C_CONCLR_AAC; /* Clear SI and ACK bit. */ + } + else { + LPC_I2C->CONSET = I2C_CONSET_AA; /* Set ACK bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + } + break; + + case I2C_STATE_MS_RDAT_NACK: /* Data byte has been received, NOT ACK has been returned. */ + *I2CD1.rxbuf++ = LPC_I2C->DAT; /* Read data. */ + I2CD1.rxbytes--; + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + wakeup_isr(&I2CD1, RDY_OK); + break; + + case I2C_STATE_BUS_ERROR: /* Bus error. */ + case I2C_STATE_ARB_LOST: /* Arbitration lost. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + i2c_lld_serve_error_interrupt(&I2CD1, status); + break; + + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = LPC_I2C; + + LPC_IOCON->PIO0_4 = 0x01; /* Set I2C SCL pin function */ + LPC_IOCON->PIO0_5 = 0x01; /* Set I2C SDA pin function */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + uint32_t i2cscl; + uint32_t mulh, mull, div; + LPC_I2C_TypeDef *dp = i2cp->i2c; + + /* Make sure I2C peripheral is disabled */ + dp->CONCLR = I2C_CONCLR_ENC; + + /* If in stopped state then enables the I2C clock. */ + if (i2cp->state == I2C_STOP) { + + if (&I2CD1 == i2cp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); /* Enable clock. */ + LPC_SYSCON->PRESETCTRL &= ~(1 << 1); /* Reset I2C peripheral.*/ + __NOP(); + LPC_SYSCON->PRESETCTRL |= (1 << 1); + nvicEnableVector(I2C_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_I2C_IRQ_PRIORITY)); + } + + } + + /* Setup I2C clock parameters.*/ + i2cscl = (LPC11xx_SYSCLK/(i2cp->config->clock_timing)); + if (i2cp->config->mode == I2C_FAST_MODE) { + div = 19; + mull = 13; + mulh = 6; + } else if (i2cp->config->mode == I2C_FAST_MODE_PLUS) { + div = 3; + mull = 2; + mulh = 1; + } else { /* i2cp->config->mode == I2C_STANDARD_MODE */ + div = 2; + mull = 1; + mulh = 1; + } + + dp->SCLH = (mulh * i2cscl) / div; + dp->SCLL = (mull * i2cscl) / div; + + /* Enable I2C.*/ + dp->CONSET |= I2C_CONSET_EN; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2cp->i2c->CONCLR = I2C_CONCLR_ENC; + + if (&I2CD1 == i2cp) { + nvicDisableVector(I2C_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 5); + } + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on STM32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + LPC_I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + + i2cp->addr = addr << 1; + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields */ + i2cp->errors = 0; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CONSET = I2C_CONSET_STA; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + LPC_I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + + i2cp->addr = addr << 1; + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields */ + i2cp->errors = 0; + i2cp->txbuf = txbuf; + i2cp->txbytes = txbytes; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CONSET = I2C_CONSET_STA; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/i2c_lld.h b/os/hal/platforms/LPC11xx/i2c_lld.h new file mode 100644 index 000000000..b908ba6e4 --- /dev/null +++ b/os/hal/platforms/LPC11xx/i2c_lld.h @@ -0,0 +1,225 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx I2C driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file LPC11xx/i2c_lld.h + * @brief LPC11xx I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_CONSET_AA 0x04 /* Assert acknowledge flag. */ +#define I2C_CONSET_SI 0x08 /* I2C interrupt flag. */ +#define I2C_CONSET_STO 0x10 /* STOP flag. */ +#define I2C_CONSET_STA 0x20 /* START flag. */ +#define I2C_CONSET_EN 0x40 /* I2C interface enable. */ + +#define I2C_CONCLR_AAC 0x04 /* Assert acknowledge Clear bit. */ +#define I2C_CONCLR_SIC 0x08 /* I2C interrupt Clear bit. */ +#define I2C_CONCLR_STAC 0x20 /* START flag Clear bit. */ +#define I2C_CONCLR_ENC 0x40 /* I2C interface Disable bit. */ + +#define I2C_WR_BIT 0x00 +#define I2C_RD_BIT 0x01 + +#define I2C_STATE_MS_START 0x08 +#define I2C_STATE_MS_RSTART 0x10 +#define I2C_STATE_MS_SLAW_ACK 0x18 +#define I2C_STATE_MS_SLAW_NACK 0x20 +#define I2C_STATE_MS_TDAT_ACK 0x28 +#define I2C_STATE_MS_TDAT_NACK 0x30 +#define I2C_STATE_ARB_LOST 0x38 + +#define I2C_STATE_MS_SLAR_ACK 0x40 +#define I2C_STATE_MS_SLAR_NACK 0x48 +#define I2C_STATE_MS_RDAT_ACK 0x50 +#define I2C_STATE_MS_RDAT_NACK 0x58 + +#define I2C_STATE_BUS_ERROR 0x00 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(LPC11xx_I2C_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_I2C_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + I2C_STANDARD_MODE = 1, + I2C_FAST_MODE = 2, + I2C_FAST_MODE_PLUS = 3, +} i2cmode_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + i2cmode_t mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_timing; /**< @brief Specifies the clock timing */ +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief Pointer to the transmit buffer. + */ + const uint8_t *txbuf; + /** + * @brief Number of bytes to transmit. + */ + size_t txbytes; + /** + * @brief Pointer to the receive buffer. + */ + uint8_t *rxbuf; + /** + * @brief Number of bytes to receive. + */ + size_t rxbytes; + /** + * @brief Pointer to the I2C registers block. + */ + LPC_I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern I2CDriver I2CD1; +#endif + +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/pal_lld.c b/os/hal/platforms/LPC11xx/pal_lld.c new file mode 100644 index 000000000..2fc1201f0 --- /dev/null +++ b/os/hal/platforms/LPC11xx/pal_lld.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/pal_lld.c + * @brief LPC11xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC11xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC11xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO0->DIR = config->P0.dir; + LPC_GPIO1->DIR = config->P1.dir; + LPC_GPIO2->DIR = config->P2.dir; + LPC_GPIO3->DIR = config->P3.dir; + LPC_GPIO0->DATA = config->P0.data; + LPC_GPIO1->DATA = config->P1.data; + LPC_GPIO2->DATA = config->P2.data; + LPC_GPIO3->DATA = config->P3.data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/pal_lld.h b/os/hal/platforms/LPC11xx/pal_lld.h new file mode 100644 index 000000000..82a1d53f9 --- /dev/null +++ b/os/hal/platforms/LPC11xx/pal_lld.h @@ -0,0 +1,316 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/pal_lld.h + * @brief LPC11xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc111x_gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + lpc111x_gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + lpc111x_gpio_setup_t P1; + /** @brief GPIO 2 setup data.*/ + lpc111x_gpio_setup_t P2; + /** @brief GPIO 3 setup data.*/ + lpc111x_gpio_setup_t P3; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO0 +#define GPIO0 LPC_GPIO0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 LPC_GPIO1 +#define GPIO1 LPC_GPIO1 + +/** + * @brief GPIO2 port identifier. + */ +#define IOPORT3 LPC_GPIO2 +#define GPIO2 LPC_GPIO2 + +/** + * @brief GPIO3 port identifier. + */ +#define IOPORT4 LPC_GPIO3 +#define GPIO3 LPC_GPIO3 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DATA) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + ((port)->MASKED_ACCESS[(mask) << (offset)]) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->MASKED_ACCESS[1 << (pad)] = (bit) << (pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/platform.dox b/os/hal/platforms/LPC11xx/platform.dox new file mode 100644 index 000000000..dab5d1e86 --- /dev/null +++ b/os/hal/platforms/LPC11xx/platform.dox @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup LPC11xx LPC11xx Drivers + * @details This section describes all the supported drivers on the LPC11xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC11xx_HAL LPC11xx Initialization Support + * @details The LPC11xx HAL support is responsible for system initialization. + * + * @section lpc11xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc11xx_hal_2 LPC11xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_GPT LPC11xx GPT Support + * @details The LPC11xx GPT driver uses the CTxxBy peripherals. + * + * @section lpc11xx_gpt_1 Supported HW resources + * - CT16B0. + * - CT16B1. + * - CT32B0. + * - CT32B1. + * . + * @section lpc11xx_gpt_2 LPC11xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable CTxxBy interrupts priority level. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_PAL LPC11xx PAL Support + * @details The LPC11xx PAL driver uses the GPIO peripherals. + * + * @section lpc11xx_pal_1 Supported HW resources + * - GPIO0. + * - GPIO1. + * - GPIO2. + * - GPIO3. + * . + * @section lpc11xx_pal_2 LPC11xx PAL driver implementation features + * - 12 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc11xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc11xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * - Reading of the output latch for pads programmed as input is not possible, + * the input pin value is returned instead. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_SERIAL LPC11xx Serial Support + * @details The LPC11xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC11xx UARTs deep hardware buffers. + * + * @section lpc11xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc11xx_serial_2 LPC11xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_SPI LPC11xx SPI Support + * @details The SPI driver supports the LPC11xx SSP peripherals in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc11xx_spi_1 Supported HW resources + * - SSP0. + * - SSP1 (where present). + * . + * @section lpc11xx_spi_2 LPC11xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SSP can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each SSP. + * . + * @ingroup LPC11xx + */ diff --git a/os/hal/platforms/LPC11xx/platform.mk b/os/hal/platforms/LPC11xx/platform.mk new file mode 100644 index 000000000..61f2a49dd --- /dev/null +++ b/os/hal/platforms/LPC11xx/platform.mk @@ -0,0 +1,13 @@ +# List of all the LPC11xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/spi_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11xx diff --git a/os/hal/platforms/LPC11xx/pwm_lld.c b/os/hal/platforms/LPC11xx/pwm_lld.c new file mode 100644 index 000000000..06de0bbc6 --- /dev/null +++ b/os/hal/platforms/LPC11xx/pwm_lld.c @@ -0,0 +1,407 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/pwm_lld.c + * @brief LPC11xx PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. + */ +#if LPC11xx_PWM_USE_CT16B0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TIM2 when enabled. + */ +#if LPC11xx_PWM_USE_CT16B1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TIM3 when enabled. + */ +#if LPC11xx_PWM_USE_CT32B0 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TIM4 when enabled. + */ +#if LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if LPC11xx_PWM_USE_CT16B0 || LPC11xx_PWM_USE_CT16B1 || LPC11xx_PWM_USE_CT32B0 || \ + LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__) +/** + * @brief Common TIM2...TIM5 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint16_t sr; + + sr = pwmp->tim->IR; + pwmp->tim->IR = sr; + if ((sr & IR_MR0INT) != 0) + pwmp->config->channels[0].callback(pwmp); + if ((sr & IR_MR1INT) != 0) + pwmp->config->channels[1].callback(pwmp); + if ((sr & IR_MR3INT) != 0) + pwmp->config->callback(pwmp); +} +#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC11xx_PWM_USE_CT16B0 || defined(__DOXYGEN__) +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + CH_IRQ_EPILOGUE(); +} + +#endif /* STM32_PWM_USE_TIM1 */ + +#if LPC11xx_PWM_USE_CT16B1 || defined(__DOXYGEN__) +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_PWM_USE_CT16B1 */ + +#if LPC11xx_PWM_USE_CT32B0 || defined(__DOXYGEN__) +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_PWM_USE_CT32B0 */ + +#if LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__) +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_PWM_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if LPC11xx_PWM_USE_CT16B0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.tim = LPC_TMR16B0; + +#if LPC11xx_PWM_USE_CT16B0_CH0 + LPC_IOCON->PIO0_8 = 0xC2; +#endif + +#if LPC11xx_PWM_USE_CT16B0_CH1 + LPC_IOCON->PIO0_9 = 0xC2; +#endif +#endif + +#if LPC11xx_PWM_USE_CT16B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.tim = LPC_TMR16B1; + +#if LPC11xx_PWM_USE_CT16B1_CH0 + LPC_IOCON->PIO1_9 = 0xC1; +#endif + +#if LPC11xx_PWM_USE_CT16B1_CH1 + LPC_IOCON->PIO1_10 = 0xC2; +#endif +#endif + +#if LPC11xx_PWM_USE_CT32B0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.tim = LPC_TMR32B0; + +#if LPC11xx_PWM_USE_CT32B0_CH0 + LPC_IOCON->PIO1_6 = 0xC2; +#endif + +#if LPC11xx_PWM_USE_CT32B0_CH1 + LPC_IOCON->PIO1_7 = 0xC2; +#endif +#endif + +#if LPC11xx_PWM_USE_CT32B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.tim = LPC_TMR32B1; + +#if LPC11xx_PWM_USE_CT32B1_CH0 + LPC_IOCON->R_PIO1_1 = 0xC3; +#endif + +#if LPC11xx_PWM_USE_CT32B1_CH1 + LPC_IOCON->R_PIO1_2 = 0xC3; +#endif +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t pr; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if LPC11xx_PWM_USE_CT16B0 + if (&PWMD1 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, LPC11xx_PWM_CT16B0_IRQ_PRIORITY); + } +#endif +#if LPC11xx_PWM_USE_CT16B1 + if (&PWMD2 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, LPC11xx_PWM_CT16B1_IRQ_PRIORITY); + } +#endif +#if LPC11xx_PWM_USE_CT32B0 + if (&PWMD3 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, LPC11xx_PWM_CT32B0_IRQ_PRIORITY); + } +#endif +#if LPC11xx_PWM_USE_CT32B1 + if (&PWMD4 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, LPC11xx_PWM_CT32B1_IRQ_PRIORITY); + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->tim->TCR = 0; + } + + /* Output enables and polarities setup.*/ + if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) + pwmp->tim->PWMC = (1 << 0); + + if(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW) + pwmp->tim->PWMC |= (1 << 1); + + /* Timer configured and started.*/ + pr = (uint16_t)((LPC11xx_SYSCLK / pwmp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * pwmp->config->frequency) == LPC11xx_SYSCLK, + "pwm_lld_start(), #1", "invalid frequency"); + + pwmp->tim->TC = 0; + pwmp->tim->PR = pr; + pwmp->tim->IR = 0xFF; + pwmp->tim->MCR = MCR_MR3R; /* Reset on Match3 */ + pwmp->tim->MR3 = pwmp->config->period; + + if (pwmp->config->callback != NULL) + pwmp->tim->MCR |= MCR_MR3I; + + pwmp->tim->TCR = 1; /* Timer start */ +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->tim->TCR = 0; /* Timer disabled. */ + pwmp->tim->MCR = 0; /* All IRQs disabled. */ + pwmp->tim->IR = 0xFF; /* Clear eventual pending IRQs. */ + pwmp->tim->PWMC = 0; /* PWM outputs disable. */ + +#if LPC11xx_PWM_USE_CT16B0 + if (&PWMD1 == pwmp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC11xx_PWM_USE_CT16B1 + if (&PWMD2 == pwmp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC11xx_PWM_USE_CT32B0 + if (&PWMD3 == pwmp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC11xx_PWM_USE_CT32B1 + if (&PWMD4 == pwmp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + pwmp->tim->MCR &= ~(7 << (channel * 3)); + + if ( channel == 0) + pwmp->tim->MR0 = width; /* New duty cycle. */ + else + pwmp->tim->MR1 = width; /* New duty cycle. */ + /* If there is a callback defined for the channel then the associated + interrupt must be enabled.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->tim->IR = (1 << channel); /* Clear interrupt flag*/ + pwmp->tim->MCR |= (1 << (channel * 3)); /* Set interrupt on selected channel */ + } + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + if ( channel == 0) + pwmp->tim->MR0 = 0; + else + pwmp->tim->MR1 = 0; + pwmp->tim->MCR &= ~(7 << (channel * 3)); + pwmp->tim->IR = (1 << channel); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/pwm_lld.h b/os/hal/platforms/LPC11xx/pwm_lld.h new file mode 100644 index 000000000..2b3a37fd1 --- /dev/null +++ b/os/hal/platforms/LPC11xx/pwm_lld.h @@ -0,0 +1,364 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/pwm_lld.h + * @brief LPC11xx PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ +#undef PWM_OUTPUT_ACTIVE_HIGH + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IR_MR0INT (1 << 0) +#define IR_MR1INT (1 << 1) +#define IR_MR2INT (1 << 2) +#define IR_MR3INT (1 << 3) +#define IR_CR0INT (1 << 4) +#define IR_CR1INT (1 << 5) +#define IR_CR2INT (1 << 6) +#define IR_CR3INT (1 << 7) + +#define MCR_MR3I (1 << 9) +#define MCR_MR3R (1 << 10) +#define MCR_MR3S (1 << 11) +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B0 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B1 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B0 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B1 FALSE +#endif + +/** + * @brief PWMD1 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD1 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B0_CH0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B0_CH0 FALSE +#endif + +/** + * @brief PWMD1 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD1 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B0_CH1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B0_CH1 FALSE +#endif + +/** + * @brief PWMD2 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD2 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B1_CH0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B1_CH0 FALSE +#endif + +/** + * @brief PWMD2 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD2 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT16B1_CH1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT16B1_CH1 FALSE +#endif + +/** + * @brief PWMD3 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD3 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B0_CH0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B0_CH0 FALSE +#endif + +/** + * @brief PWMD3 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD3 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B0_CH1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B0_CH1 FALSE +#endif + +/** + * @brief PWMD4 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD4 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B1_CH0) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B1_CH0 FALSE +#endif + +/** + * @brief PWMD4 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD4 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC11xx_PWM_USE_CT32B1_CH1) || defined(__DOXYGEN__) +#define LPC11xx_PWM_USE_CT32B1_CH1 FALSE +#endif +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(LPC11xx_PWM_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_PWM_CT16B0_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(LPC11xx_PWM_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_PWM_CT16B1_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(LPC11xx_PWM_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_PWM_CT32B0_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(LPC11xx_PWM_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_PWM_CT32B1_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + LPC_TMR_TypeDef *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->MR3 = (period)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_PWM_USE_CT16B0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if LPC11xx_PWM_USE_CT16B1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if LPC11xx_PWM_USE_CT32B0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if LPC11xx_PWM_USE_CT32B1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/serial_lld.c b/os/hal/platforms/LPC11xx/serial_lld.c new file mode 100644 index 000000000..2fdb14ed0 --- /dev/null +++ b/os/hal/platforms/LPC11xx/serial_lld.c @@ -0,0 +1,298 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/serial_lld.c + * @brief LPC11xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_UART_TypeDef *u = sdp->uart; + + uint32_t div = LPC11xx_SERIAL_UART0_PCLK / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(LPC_UART_TypeDef *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC11xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC11xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector94) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC11xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_UART; + LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ + LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC11xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UARTCLKDIV = LPC11xx_SERIAL_UART0CLKDIV; + nvicEnableVector(UART_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC11xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UARTCLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/serial_lld.h b/os/hal/platforms/LPC11xx/serial_lld.h new file mode 100644 index 000000000..c4178816e --- /dev/null +++ b/os/hal/platforms/LPC11xx/serial_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/serial_lld.h + * @brief LPC11xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC11xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC11xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC11xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC11xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC11xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC11xx_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC11xx_SERIAL_FIFO_PRELOAD < 1) || (LPC11xx_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC11xx_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC11xx_SERIAL_UART0_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SERIAL_UART0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC11xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_UART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/spi_lld.c b/os/hal/platforms/LPC11xx/spi_lld.c new file mode 100644 index 000000000..ab09f540b --- /dev/null +++ b/os/hal/platforms/LPC11xx/spi_lld.c @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/spi_lld.c + * @brief LPC11xx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC11xx_SSP_FIFO_DEPTH ? + LPC11xx_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC11xx_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC11xx_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; + LPC_IOCON->SCK_LOC = LPC11xx_SPI_SCK0_SELECTOR; +#if LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10 + LPC_IOCON->SWCLK_PIO0_10 = 0xC2; /* SCK0 without resistors. */ +#elif LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11 + LPC_IOCON->PIO2_11 = 0xC1; /* SCK0 without resistors. */ +#else /* LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */ + LPC_IOCON->PIO0_6 = 0xC2; /* SCK0 without resistors. */ +#endif + LPC_IOCON->PIO0_8 = 0xC1; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0xC1; /* MOSI0 without resistors. */ +#endif /* LPC11xx_SPI_USE_SSP0 */ + +#if LPC11xx_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; + LPC_IOCON->PIO2_1 = 0xC2; /* SCK1 without resistors. */ + LPC_IOCON->PIO2_2 = 0xC2; /* MISO1 without resistors. */ + LPC_IOCON->PIO2_3 = 0xC2; /* MOSI1 without resistors. */ +#endif /* LPC11xx_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC11xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC11xx_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC11xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC11xx_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC11xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC11xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/spi_lld.h b/os/hal/platforms/LPC11xx/spi_lld.h new file mode 100644 index 000000000..4d6c56027 --- /dev/null +++ b/os/hal/platforms/LPC11xx/spi_lld.h @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11xx/spi_lld.h + * @brief LPC11xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC11xx_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/** + * @brief SCK0 signal assigned to pin PIO0_10. + */ +#define SCK0_IS_PIO0_10 0 + +/** + * @brief SCK0 signal assigned to pin PIO2_11. + */ +#define SCK0_IS_PIO2_11 1 + +/** + * @brief SCK0 signal assigned to pin PIO0_6. + */ +#define SCK0_IS_PIO0_6 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC11xx_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC11xx_SPI_USE_SSP1 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC11xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC11xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC11xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC11xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC11xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief SCK0 signal selector. + */ +#if !defined(LPC11xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC11xx_SPI_SSP0CLKDIV < 1) || (LPC11xx_SPI_SSP0CLKDIV > 255) +#error "invalid LPC11xx_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC11xx_SPI_SSP1CLKDIV < 1) || (LPC11xx_SPI_SSP1CLKDIV > 255) +#error "invalid LPC11xx_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC11xx_SPI_USE_SSP0 && !LPC11xx_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) && \ + (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) && \ + (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6) +#error "invalid pin assigned to SCK0 signal" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC11xx_SPI_SSP0_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SPI_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC11xx_SPI_SSP1_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SPI_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSP_TypeDef *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC11xx_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11xx/system_LPC11xx.h b/os/hal/platforms/LPC11xx/system_LPC11xx.h new file mode 100644 index 000000000..e4536b8a5 --- /dev/null +++ b/os/hal/platforms/LPC11xx/system_LPC11xx.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * @file: system_LPC11xx.h + * @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Header File + * for the NXP LPC11xx Device Series + * @version: V1.0 + * @date: 25. Nov. 2008 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2008 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M0 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC11xx_H +#define __SYSTEM_LPC11xx_H + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM (0x10000000) +#define NVIC_VectTab_FLASH (0x00000000) + +extern uint32_t ClockSource; +extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t SystemAHBFrequency; + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +extern void SystemInit (void); +#endif diff --git a/os/hal/platforms/LPC122x/LPC122x.h b/os/hal/platforms/LPC122x/LPC122x.h new file mode 100644 index 000000000..8415b06fa --- /dev/null +++ b/os/hal/platforms/LPC122x/LPC122x.h @@ -0,0 +1,725 @@ +/**************************************************************************//** + * $Id: LPC122x.h 6933 2011-03-23 19:02:11Z nxp28548 $ + * + * @file LPC122x.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * NXP LPC122x Device Series + * @version 1.1 + * @date $Date:: 2011-03-23#$ + * @author NXP MCU Team + * + * @note + * Copyright (C) 2011 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + + + +/** @addtogroup (null) + * @{ + */ + +/** @addtogroup LPC122x + * @{ + */ + +#ifndef __LPC122X_H__ +#define __LPC122X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + /* Interrupt Number Definition */ + +typedef enum { + // ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + // --------------------------- LPC122x Specific Interrupt Numbers ------------------------------- + WAKEUP0_IRQn = 0, /*!< PIO0_0 to PIO0_11 Wakeup */ + WAKEUP1_IRQn = 1, + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, /*!< PIO0_0 to PIO0_11 Wakeup */ + I2C_IRQn =12, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 13, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 14, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 15, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 16, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 17, /*!< SSP Interrupt */ + UART0_IRQn = 18, /*!< UART0 Interrupt */ + UART1_IRQn = 19, /*!< UART1 Interrupt */ + CMP_IRQn = 20, /*!< Comparator Interrupt */ + ADC_IRQn = 21, /*!< A/D Converter Interrupt */ + WDT_IRQn = 22, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 23, /*!< Brown Out Detect(BOD) Interrupt */ + EINT0_IRQn = 25, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 26, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 27, /*!< External Interrupt 2 Interrupt */ + DMA_IRQn = 29, /*!< DMA Interrupt */ + RTC_IRQn = 30, /*!< RTC Interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC12xx_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_LPC122x.h" /* System Header */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +// ------------------------------------------------------------------------------------------------ +// ----- I2C ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x I2C-bus controller Modification date=2/2/2011 Major revision=0 Minor revision=17 (I2C) + */ + +typedef struct { /*!< (@ 0x40000000) I2C Structure */ + __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ + __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ + __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ + __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ + __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */ + __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ + __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */ +} LPC_I2C_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- WWDT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x Windowed Watchdog Timer (WWDT) Modification date=2/2/2011 Major revision=0 Minor revision=17 (WWDT) + */ + +typedef struct { /*!< (@ 0x40004000) WWDT Structure */ + __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This register determines the time-out value. */ + __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ + __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ + __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock source selection register. */ + __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ + __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ +} LPC_WWDT_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- UART0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x UART0 with modem control Modification date=2/2/2011 Major revision=0 Minor revision=17 (UART0) + */ + +typedef struct { /*!< (@ 0x40008000) UART0 Structure */ + + union { + __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */ + __IO uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ + __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ + }; + + union { + __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0) */ + __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */ + }; + + union { + __IO uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls UART FIFO usage and modes. */ + __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ + __IO uint32_t MCR; /*!< (@ 0x40008010) Modem control register */ + __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t MSR; /*!< (@ 0x40008018) Modem status register */ + __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __I uint32_t RESERVED0[1]; + __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __I uint32_t RESERVED1[1]; + __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ + __I uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ + __I uint32_t FIFOLVL; /*!< (@ 0x40008058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ +} LPC_UART0_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- UART1 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x UART1 Modification date=2/3/2011 Major revision=0 Minor revision=17 (UART1) + */ + +typedef struct { /*!< (@ 0x4000C000) UART1 Structure */ + + union { + __IO uint32_t DLL; /*!< (@ 0x4000C000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. */ + __IO uint32_t THR; /*!< (@ 0x4000C000) Transmit Holding Register. The next character to be transmitted is written here. */ + __I uint32_t RBR; /*!< (@ 0x4000C000) Receiver Buffer Register. Contains the next received character to be read. */ + }; + + union { + __IO uint32_t IER; /*!< (@ 0x4000C004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. */ + __IO uint32_t DLM; /*!< (@ 0x4000C004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. */ + }; + + union { + __IO uint32_t FCR; /*!< (@ 0x4000C008) FIFO Control Register. Controls UART FIFO usage and modes. */ + __I uint32_t IIR; /*!< (@ 0x4000C008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4000C00C) Line Control Register. Contains controls for frame formatting and break generation. */ + __I uint32_t RESERVED0[1]; + __I uint32_t LSR; /*!< (@ 0x4000C014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t RESERVED1[1]; + __IO uint32_t SCR; /*!< (@ 0x4000C01C) Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< (@ 0x4000C020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __IO uint32_t ICR; /*!< (@ 0x4000C024) IrDA Control Register. Enables and configures the IrDA mode. */ + __IO uint32_t FDR; /*!< (@ 0x4000C028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __I uint32_t RESERVED2[1]; + __IO uint32_t TER; /*!< (@ 0x4000C030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ + __I uint32_t RESERVED3[9]; + __I uint32_t FIFOLVL; /*!< (@ 0x4000C058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ +} LPC_UART1_Type; + +// ------------------------------------------------------------------------------------------------ +// ----- CT32B0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x 32-bit Counter/timer 0/1 (CT32B0/1) Modification date=2/3/2011 Major revision=0 Minor revision=17 (CT32B0) + */ + +typedef struct { /*!< (@ 0x40018000) CT32B0 Structure */ + __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ + __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ + __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ + __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ + __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ + __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ + union { + __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ + struct{ + __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ + __IO uint32_t MR1; /*!< (@ 0x40018018) Match Register. MR1 */ + __IO uint32_t MR2; /*!< (@ 0x40018018) Match Register. MR2 */ + __IO uint32_t MR3; /*!< (@ 0x40018018) Match Register. MR3 */ + }; + }; + __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ + union{ + __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP input. */ + struct{ + __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ + __I uint32_t CR1; /*!< (@ 0x4001802C) Capture Register. CR 1 */ + __I uint32_t CR2; /*!< (@ 0x4001802C) Capture Register. CR 2 */ + __I uint32_t CR3; /*!< (@ 0x4001802C) Capture Register. CR 3 */ + }; + }; + __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ + __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */ +} LPC_CTxxBx_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- ADC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x ADC Modification date=2/9/2011 Major revision=0 Minor revision=17 (ADC) + */ + +typedef struct { /*!< (@ 0x40020000) ADC Structure */ + __IO uint32_t CR; /*!< (@ 0x40020000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */ + __IO uint32_t GDR; /*!< (@ 0x40020004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */ + __I uint32_t RESERVED0[1]; + __IO uint32_t INTEN; /*!< (@ 0x4002000C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ + union{ + __IO uint32_t DR[8]; /*!< (@ 0x40020010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel. */ + struct{ + __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ + __IO uint32_t DR1; /*!< (@ 0x40020010) A/D Channel Data Register 1*/ + __IO uint32_t DR2; /*!< (@ 0x40020010) A/D Channel Data Register 2*/ + __IO uint32_t DR3; /*!< (@ 0x40020010) A/D Channel Data Register 3*/ + __IO uint32_t DR4; /*!< (@ 0x40020010) A/D Channel Data Register 4*/ + __IO uint32_t DR5; /*!< (@ 0x40020010) A/D Channel Data Register 5*/ + __IO uint32_t DR6; /*!< (@ 0x40020010) A/D Channel Data Register 6*/ + __IO uint32_t DR7; /*!< (@ 0x40020010) A/D Channel Data Register 7*/ + }; + }; + __I uint32_t STAT; /*!< (@ 0x40020030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ + __IO uint32_t TRM; /*!< (@ 0x40020034) A/D trim register */ +} LPC_ADC_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- PMU ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x Power Monitor Unit (PMU) Modification date=2/10/2011 Major revision=0 Minor revision=17 (PMU) + */ + +typedef struct { /*!< (@ 0x40038000) PMU Structure */ + __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ + union{ + __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register */ + struct{ + __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ + __IO uint32_t GPREG1; /*!< (@ 0x40038004) General purpose register 1 */ + __IO uint32_t GPREG2; /*!< (@ 0x40038004) General purpose register 2 */ + __IO uint32_t GPREG3; /*!< (@ 0x40038004) General purpose register 3 */ + }; + }; + __IO uint32_t SYSCFG; /*!< (@ 0x40038014) System configuration register (RTC clock control and hysteresis of the WAKEUP pin). */ +} LPC_PMU_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SSP ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x SSP controller Modification date=2/10/2011 Major revision=0 Minor revision=17 (SSP) + */ + +typedef struct { /*!< (@ 0x40040000) SSP Structure */ + union{ + __IO uint32_t CR[2]; /*!< (@ 0x40040000) Control Registers. */ + struct{ + __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ + }; + }; + __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ + __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ + __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< (@ 0x40040024) DMA Control Register */ +} LPC_SSP_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- IOCON ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x /O configuration (IOCONFIG) Modification date=2/11/2011 Major revision=1 Minor revision=0 (IOCON) + */ + +typedef struct { /*!< (@ 0x40044000) IOCON Structure */ + __I uint32_t RESERVED0[2]; + __IO uint32_t PIO0_19; /*!< (@ 0x40044008) Configures pin PIO0_19/ACMP0_I0/CT32B0_1. */ + __IO uint32_t PIO0_20; /*!< (@ 0x4004400C) Configures pin PIO0_20/ACMP0_I1/CT32B0_2. */ + __IO uint32_t PIO0_21; /*!< (@ 0x40044010) Configures pin PIO0_21/ACMP0_I2/CT32B0_3. */ + __IO uint32_t PIO0_22; /*!< (@ 0x40044014) Configures pin PIO0_22/ACMP0_I3. */ + __IO uint32_t PIO0_23; /*!< (@ 0x40044018) Configures pin PIO0_23/ACMP1_I0/CT32B1_0. */ + __IO uint32_t PIO0_24; /*!< (@ 0x4004401C) Configures pin PIO0_24/ACMP1_I1/CT32B1_1. */ + __IO uint32_t SWDIO_PIO0_25; /*!< (@ 0x40044020) Configures pin SWDIO/ACMP1_I2/ CT32B1_2/PIO0_25. */ + __IO uint32_t SWCLK_PIO0_26; /*!< (@ 0x40044024) Configures pin SWCLK/PIO0_26/ACMP1_I3/ CT32B1_3/PIO0_26 */ + __IO uint32_t PIO0_27; /*!< (@ 0x40044028) Configures pin PIO0_27/ACMP0_O. */ + __IO uint32_t PIO2_12; /*!< (@ 0x4004402C) Configures pin PIO2_12/RXD1. */ + __IO uint32_t PIO2_13; /*!< (@ 0x40044030) Configures pin PIO2_13/TXD1. */ + __IO uint32_t PIO2_14; /*!< (@ 0x40044034) Configures pin PIO2_14. */ + __IO uint32_t PIO2_15; /*!< (@ 0x40044038) Configures pin PIO2_15. */ + __IO uint32_t PIO0_28; /*!< (@ 0x4004403C) Configures pin PIO0_28/ACMP1_O/CT16B0_0. */ + __IO uint32_t PIO0_29; /*!< (@ 0x40044040) Configures pin PIO0_29/ROSC/CT16B0_1. */ + __IO uint32_t PIO0_0; /*!< (@ 0x40044044) Configures pin PIO0_0/ RTS0. */ + __IO uint32_t PIO0_1; /*!< (@ 0x40044048) Configures pin PIO0_1CT32B0_0/RXD0. */ + __IO uint32_t PIO0_2; /*!< (@ 0x4004404C) Configures pin PIO0_2/TXD0/CT32B0_1. */ + __I uint32_t RESERVED1[1]; + __IO uint32_t PIO0_3; /*!< (@ 0x40044054) Configures pin PIO0_3/DTR0/CT32B0_2. */ + __IO uint32_t PIO0_4; /*!< (@ 0x40044058) Configures pin PIO0_4/ DSR0/CT32B0_3. */ + __IO uint32_t PIO0_5; /*!< (@ 0x4004405C) Configures pin PIO0_5. */ + __IO uint32_t PIO0_6; /*!< (@ 0x40044060) Configures pin PIO0_6/RI0/CT32B1_0. */ + __IO uint32_t PIO0_7; /*!< (@ 0x40044064) Configures pin PIO0_7CTS0/CT32B1_1. */ + __IO uint32_t PIO0_8; /*!< (@ 0x40044068) Configures pin PIO0_8/RXD1/CT32B1_2. */ + __IO uint32_t PIO0_9; /*!< (@ 0x4004406C) Configures pin PIO0_9/TXD1/CT32B1_3. */ + __IO uint32_t PIO2_0; /*!< (@ 0x40044070) Configures pin PIO2_0/CT16B0_0/ RTS0. */ + __IO uint32_t PIO2_1; /*!< (@ 0x40044074) Configures pin PIO2_1/CT16B0_1/RXD0. */ + __IO uint32_t PIO2_2; /*!< (@ 0x40044078) Configures pin PIO2_2/CT16B1_0/TXD0. */ + __IO uint32_t PIO2_3; /*!< (@ 0x4004407C) Configures pin PIO2_3/CT16B1_1/DTR0. */ + __IO uint32_t PIO2_4; /*!< (@ 0x40044080) Configures pin PIO2_4/CT32B0_0/CTS0. */ + __IO uint32_t PIO2_5; /*!< (@ 0x40044084) Configures pin PIO2_5/CT32B0_1/ DCD0. */ + __IO uint32_t PIO2_6; /*!< (@ 0x40044088) Configures pin PIO2_6/CT32B0_2/RI0. */ + __IO uint32_t PIO2_7; /*!< (@ 0x4004408C) Configures pin PIO2_7/CT32B0_3/DSR0. */ + __IO uint32_t PIO0_10; /*!< (@ 0x40044090) Configures pin PIO0_10/SCL. */ + __IO uint32_t PIO0_11; /*!< (@ 0x40044094) Configures pin PIO0_11/SDA/CT16B0_0. */ + __IO uint32_t PIO0_12; /*!< (@ 0x40044098) Configures pin PIO0_12/CLKOUT/CT16B0_1. */ + __IO uint32_t RESET_PIO0_13; /*!< (@ 0x4004409C) Configures pin RESET/PIO0_13. */ + __IO uint32_t PIO0_14; /*!< (@ 0x400440A0) Configures pin PIO0_14/SSP_CLK. */ + __IO uint32_t PIO0_15; /*!< (@ 0x400440A4) Configures pin PIO0_15/SSP_SSEL/CT16B1_0. */ + __IO uint32_t PIO0_16; /*!< (@ 0x400440A8) Configures pin PIO0_16/SSP_MISO/CT16B1_1. */ + __IO uint32_t PIO0_17; /*!< (@ 0x400440AC) Configures pin PIO0_17/SSP_MOSI. */ + __IO uint32_t PIO0_18; /*!< (@ 0x400440B0) Configures pin PIO0_18/SWCLK/CT32B0_0. */ + __IO uint32_t R_PIO0_30; /*!< (@ 0x400440B4) Configures pin R/PIO0_30/AD0. */ + __IO uint32_t R_PIO0_31; /*!< (@ 0x400440B8) Configures pin R/PIO0_31/AD1. */ + __IO uint32_t R_PIO1_0; /*!< (@ 0x400440BC) Configures pin R/PIO1_0/AD2. */ + __IO uint32_t R_PIO1_1; /*!< (@ 0x400440C0) Configures pin R/PIO1_1/AD3. */ + __IO uint32_t PIO1_2; /*!< (@ 0x400440C4) Configures pin PIO1_2/SWDIO/AD4. */ + __IO uint32_t PIO1_3; /*!< (@ 0x400440C8) Configures pin PIO1_3/AD5/WAKEUP. */ + __IO uint32_t PIO1_4; /*!< (@ 0x400440CC) Configures pin PIO1_4/AD6 */ + __IO uint32_t PIO1_5; /*!< (@ 0x400440D0) Configures pin PIO1_5/AD7/CT16B1_0. */ + __IO uint32_t PIO1_6; /*!< (@ 0x400440D4) Configures pin PIO1_6/CT16B1_1. */ + __I uint32_t RESERVED2[2]; + __IO uint32_t PIO2_8; /*!< (@ 0x400440E0) Configures pin PIO2_8/CT32B1_0. */ + __IO uint32_t PIO2_9; /*!< (@ 0x400440E4) Configures pin PIO2_9/CT32B1_1. */ + __IO uint32_t PIO2_10; /*!< (@ 0x400440E8) Configures pin PIO2_10/CT32B1_2/TXD1. */ + __IO uint32_t PIO2_11; /*!< (@ 0x400440EC) Configures pin PIO2_11/CT32B1_3/RXD1. */ +} LPC_IOCON_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SYSCON ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x System control (SYSCON) Modification date=2/10/2011 Major revision=1 Minor revision=0 (SYSCON) + */ + +typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ + __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ + __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control and flash timing overwrite */ + __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ + __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ + __I uint32_t RESERVED0[4]; + __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ + __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ + __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */ + __I uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /*!< (@ 0x40048030) System reset status register */ + __I uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ + __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ + __I uint32_t RESERVED3[10]; + __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ + __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ + __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System AHB clock divider */ + __I uint32_t RESERVED4[1]; + __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System AHB clock control */ + __I uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; /*!< (@ 0x40048094) SSP clock divder */ + __IO uint32_t UART0CLKDIV; /*!< (@ 0x40048098) UART0 clock divider */ + __IO uint32_t UART1CLKDIV; /*!< (@ 0x4004809C) UART1 clock divider */ + __IO uint32_t RTCCLKDIV; /*!< (@ 0x400480A0) RTC clock divider */ + __I uint32_t RESERVED6[15]; + __IO uint32_t CLKOUTCLKSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ + __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ + __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ + __I uint32_t RESERVED7[5]; + __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ + __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ + __I uint32_t RESERVED8[11]; + __IO uint32_t IOCONFIGCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV5; /*!< (@ 0x40048138) Peripheral clock 5 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV4; /*!< (@ 0x4004813C) Peripheral clock 4 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV3; /*!< (@ 0x40048140) Peripheral clock 3to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV2; /*!< (@ 0x40048144) Peripheral clock 2 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV1; /*!< (@ 0x40048148) Peripheral clock 1 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t IOCONFIGCLKDIV0; /*!< (@ 0x4004814C) Peripheral clock 0 to the IOCONFIG block for programmable glitch filter */ + __IO uint32_t BODCTRL; /*!< (@ 0x40048150) BOD control */ + __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ + __IO uint32_t AHBPRIO; /*!< (@ 0x40048158) AHB priority setting */ + __I uint32_t RESERVED9[5]; + __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */ + __IO uint32_t INTNMI; /*!< (@ 0x40048174) NMI interrupt source configuration control */ + __I uint32_t RESERVED10[34]; + __IO uint32_t STARTAPRP0; /*!< (@ 0x40048200) Start logic edge control register 0 */ + __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic signal enable register 0 */ + __IO uint32_t STARTRSRP0CLR; /*!< (@ 0x40048208) Start logic reset register 0 */ + __I uint32_t STARTSRP0; /*!< (@ 0x4004820C) Start logic status register 0 */ + __IO uint32_t STARTAPRP1; /*!< (@ 0x40048210) Start logic edge control register 1; peripheral interrupts */ + __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic signal enable register 1; peripheral interrupts */ + __IO uint32_t STARTRSRP1CLR; /*!< (@ 0x40048218) Start logic reset register 1; peripheral interrupts */ + __I uint32_t STARTSRP1; /*!< (@ 0x4004821C) Start logic status register 1; peripheral interrupts */ + __I uint32_t RESERVED11[4]; + __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in Deep-sleep mode */ + __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states after wake-up from Deep-sleep mode */ + __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power-down configuration register */ + __I uint32_t RESERVED12[110]; + __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ +} LPC_SYSCON_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- MICRO_DMA ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x General purpose micro DMA controller Modification date=2/10/2011 Major revision=0 Minor revision=17 (MICRO_DMA) + */ + +typedef struct { /*!< (@ 0x4004C000) MICRO_DMA Structure */ + __I uint32_t DMA_STATUS; /*!< (@ 0x4004C000) DMA status register */ + __IO uint32_t DMA_CFG; /*!< (@ 0x4004C004) DMA configuration register */ + __IO uint32_t CTRL_BASE_PTR; /*!< (@ 0x4004C008) Channel control base pointer register */ + __I uint32_t ATL_CTRL_BASE_PTR; /*!< (@ 0x4004C00C) Channel alternate control base pointer register */ + __I uint32_t DMA_WAITONREQ_STATUS; /*!< (@ 0x4004C010) Channel wait on request status register */ + __IO uint32_t CHNL_SW_REQUEST; /*!< (@ 0x4004C014) Channel software request register */ + __IO uint32_t CHNL_USEBURST_SET; /*!< (@ 0x4004C018) Channel useburst set register */ + __IO uint32_t CHNL_USEBURST_CLR; /*!< (@ 0x4004C01C) Channel useburst clear register */ + __IO uint32_t CHNL_REQ_MASK_SET; /*!< (@ 0x4004C020) Channel request mask set register */ + __IO uint32_t CHNL_REQ_MASK_CLR; /*!< (@ 0x4004C024) Channel request mask clear register */ + __IO uint32_t CHNL_ENABLE_SET; /*!< (@ 0x4004C028) Channel enable set register */ + __IO uint32_t CHNL_ENABLE_CLR; /*!< (@ 0x4004C02C) Channel enable clear register */ + __IO uint32_t CHNL_PRI_ALT_SET; /*!< (@ 0x4004C030) Channel primary-alternate set register */ + __IO uint32_t CHNL_PRI_ALT_CLR; /*!< (@ 0x4004C034) Channel primary-alternate clear register */ + __IO uint32_t CHNL_PRIORITY_SET; /*!< (@ 0x4004C038) Channel priority set register */ + __IO uint32_t CHNL_PRIORITY_CLR; /*!< (@ 0x4004C03C) Channel priority clear register */ + __I uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /*!< (@ 0x4004C04C) Bus error clear register */ + __I uint32_t RESERVED1[12]; + __IO uint32_t CHNL_IRQ_STATUS; /*!< (@ 0x4004C080) Channel DMA interrupt status register */ + __IO uint32_t IRQ_ERR_ENABLE; /*!< (@ 0x4004C084) DMA error interrupt enable register */ + __IO uint32_t CHNL_IRQ_ENABLE; /*!< (@ 0x4004C088) Channel DMA interrupt enable register */ +} LPC_MICRO_DMA_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- RTC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x Real-Time Clock (RTC) Modification date=2/11/2011 Major revision=1 Minor revision=0 (RTC) + */ + +typedef struct { /*!< (@ 0x40050000) RTC Structure */ + __I uint32_t DR; /*!< (@ 0x40050000) Data register */ + __IO uint32_t MR; /*!< (@ 0x40050004) Match register */ + __IO uint32_t LR; /*!< (@ 0x40050008) Load register */ + __IO uint32_t CR; /*!< (@ 0x4005000C) Control register */ + __IO uint32_t ICSC; /*!< (@ 0x40050010) Interrupt control set/clear register */ + __I uint32_t RIS; /*!< (@ 0x40050014) Raw interrupt status register */ + __I uint32_t MIS; /*!< (@ 0x40050018) Masked interrupt status register */ + __IO uint32_t ICR; /*!< (@ 0x4005001C) Interrupt clear register */ +} LPC_RTC_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- ACOMP ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x Comparator Modification date=2/11/2011 Major revision=0 Minor revision=17 (ACOMP) + */ + +typedef struct { /*!< (@ 0x40054000) ACOMP Structure */ + __IO uint32_t CMP; /*!< (@ 0x40054000) Comparator control register */ + __IO uint32_t VLAD; /*!< (@ 0x40054004) Voltage ladder register */ +} LPC_ACOMP_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO0/1/2 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x General Purpose I/O (GPIO) Modification date=2/11/2011 Major revision=0 Minor revision=17 (GPIO0) + */ + +typedef struct { /*!< (@ 0x500X0000) GPIO0 Structure */ + __IO uint32_t MASK; /*!< (@ 0x500X0000) Pin value mask register. Affects operations on PIN, OUT, SET, CLR, and NOT registers. */ + __I uint32_t PIN; /*!< (@ 0x500X0004) Pin value register. */ + __IO uint32_t OUT; /*!< (@ 0x500X0008) Pin output value register. */ + __IO uint32_t SET; /*!< (@ 0x500X000C) Pin output value set register. */ + __IO uint32_t CLR; /*!< (@ 0x500X0010) Pin output value clear register. */ + __IO uint32_t NOT; /*!< (@ 0x500X0014) Pin output value invert register. */ + __I uint32_t RESERVED0[2]; + __IO uint32_t DIR; /*!< (@ 0x500X0020) Data direction register. */ + __IO uint32_t IS; /*!< (@ 0x500X0024) Interrupt sense register. */ + __IO uint32_t IBE; /*!< (@ 0x500X0028) Interrupt both edges register. */ + __IO uint32_t IEV; /*!< (@ 0x500X002C) Interrupt event register. */ + __IO uint32_t IE; /*!< (@ 0x500X0030) Interrupt mask register. */ + __I uint32_t RIS; /*!< (@ 0x500X0034) Raw interrupt status register. */ + __I uint32_t MIS; /*!< (@ 0x500X0038) Masked interrupt status register. */ + __IO uint32_t IC; /*!< (@ 0x5000003C) Interrupt clear register. */ +} LPC_GPIO_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- FLASHCTRL ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x System control (SYSCON) Modification date=2/16/2011 Major revision=1 Minor revision=0 (FLASHCTRL) + */ + +typedef struct { /*!< (@ 0x50060000) FLASHCTRL Structure */ + __I uint32_t RESERVED0[10]; + __IO uint32_t FLASHCFG; /*!< (@ 0x50060028) Flash read cycle configuration */ +} LPC_FLASHCTRL_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- CRC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10441 Chapter title=LPC122x CRC engine Modification date=2/11/2011 Major revision=0 Minor revision=17 (CRC) + */ + +typedef struct { /*!< (@ 0x50070000) CRC Structure */ + __IO uint32_t MODE; /*!< (@ 0x50070000) CRC mode register */ + __IO uint32_t SEED; /*!< (@ 0x50070004) CRC seed register */ + + union { + union{ + __O uint8_t WR_DATA_8; /*!< (@ 0x50070008) CRC 8-bit data register */ + __O uint16_t WR_DATA_16; /*!< (@ 0x50070008) CRC 16-bit data register */ + __O uint32_t WR_DATA_32; /*!< (@ 0x50070008) CRC 32-bit data register */ + }; + __I uint32_t SUM; /*!< (@ 0x50070008) CRC checksum register */ + }; +} LPC_CRC_Type; + + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral memory map ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C_BASE (0x40000000) +#define LPC_WWDT_BASE (0x40004000) +#define LPC_UART0_BASE (0x40008000) +#define LPC_UART1_BASE (0x4000C000) +#define LPC_CT16B0_BASE (0x40010000) +#define LPC_CT16B1_BASE (0x40014000) +#define LPC_CT32B0_BASE (0x40018000) +#define LPC_CT32B1_BASE (0x4001C000) +#define LPC_ADC_BASE (0x40020000) +#define LPC_PMU_BASE (0x40038000) +#define LPC_SSP_BASE (0x40040000) +#define LPC_IOCON_BASE (0x40044000) +#define LPC_SYSCON_BASE (0x40048000) +#define LPC_MICRO_DMA_BASE (0x4004C000) +#define LPC_RTC_BASE (0x40050000) +#define LPC_ACOMP_BASE (0x40054000) +#define LPC_GPIO0_BASE (0x50000000) +#define LPC_GPIO1_BASE (0x50010000) +#define LPC_GPIO2_BASE (0x50020000) +#define LPC_FLASHCTRL_BASE (0x50060000) +#define LPC_CRC_BASE (0x50070000) + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral declaration ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) +#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) +#define LPC_UART0 ((LPC_UART0_Type *) LPC_UART0_BASE) +#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE) +#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) +#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) +#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) +#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) +#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) +#define LPC_SSP ((LPC_SSP_Type *) LPC_SSP_BASE) +#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) +#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) +#define LPC_MICRO_DMA ((LPC_MICRO_DMA_Type *) LPC_MICRO_DMA_BASE) +#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) +#define LPC_ACOMP ((LPC_ACOMP_Type *) LPC_ACOMP_BASE) +#define LPC_GPIO0 ((LPC_GPIO_Type *) LPC_GPIO0_BASE) +#define LPC_GPIO1 ((LPC_GPIO_Type *) LPC_GPIO1_BASE) +#define LPC_GPIO2 ((LPC_GPIO_Type *) LPC_GPIO2_BASE) +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) +#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group (null) */ +/** @} */ /* End of group LPC122x */ + +#ifdef __cplusplus +} +#endif + + +#endif // __LPC122X_H__ diff --git a/os/hal/platforms/LPC122x/ext_lld.c b/os/hal/platforms/LPC122x/ext_lld.c new file mode 100644 index 000000000..553ae9b5c --- /dev/null +++ b/os/hal/platforms/LPC122x/ext_lld.c @@ -0,0 +1,234 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/ext_lld.c + * @brief LPC122x EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD0 driver identifier. + */ +#if LPC122x_EXT_USE_EXT0 || defined(__DOXYGEN__) +EXTDriver EXTD0; +#endif + +/** + * @brief EXTD1 driver identifier. + */ +#if LPC122x_EXT_USE_EXT1 || defined(__DOXYGEN__) +EXTDriver EXTD1; +#endif + +/** + * @brief EXTD2 driver identifier. + */ +#if LPC122x_EXT_USE_EXT2 || defined(__DOXYGEN__) +EXTDriver EXTD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ +#if LPC122x_EXT_USE_EXT0 + extObjectInit(&EXTD0); + EXTD0.gpio = LPC_GPIO0; +#endif + +#if LPC122x_EXT_USE_EXT1 + extObjectInit(&EXTD1); + EXTD1.gpio = LPC_GPIO1; +#endif + +#if LPC122x_EXT_USE_EXT2 + extObjectInit(&EXTD2); + EXTD2.gpio = LPC_GPIO2; +#endif +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + int i; + + /* Configure all pins as edge sensitive */ +#if LPC122x_EXT_USE_EXT0 + if (extp == &EXTD0) { + LPC_GPIO0->IS = 0; + ext_lld_exti_irq_enable(EXTI0_IRQ); + } +#endif + +#if LPC122x_EXT_USE_EXT1 + if (extp == &EXTD1) { + LPC_GPIO1->IS = 0; + ext_lld_exti_irq_enable(EXTI1_IRQ); + } +#endif + +#if LPC122x_EXT_USE_EXT2 + if (extp == &EXTD2) { + LPC_GPIO2->IS = 0; + ext_lld_exti_irq_enable(EXTI2_IRQ); + } +#endif + + /* Configuration of autostart channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) + ext_lld_channel_enable(extp, i); + else + ext_lld_channel_disable(extp, i); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + LPC_GPIO_Type * gp = extp->gpio; + + if (extp->state == EXT_ACTIVE) { +#if LPC122x_EXT_USE_EXT0 + if (extp == &EXTD0) { + ext_lld_exti_irq_disable(EXTI0_IRQ); + } +#endif + +#if LPC122x_EXT_USE_EXT1 + if (extp == &EXTD1) { + ext_lld_exti_irq_disable(EXTI1_IRQ); + } +#endif + +#if LPC122x_EXT_USE_EXT2 + if (extp == &EXTD2) { + ext_lld_exti_irq_disable(EXTI2_IRQ); + } +#endif + } + + gp->IE = 0; + gp->IC = 0xFFFFFFFF; + __NOP(); + __NOP(); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + LPC_GPIO_Type * gp; + + gp = extp->gpio; + + /* Programming edge irq enables */ + if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES) + gp->IBE |= (1 << channel); + else { + gp->IBE &= ~(1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + gp->IEV |= (1 << channel); + else + gp->IEV &= (1 << channel); + } + + gp->IC = (1 << channel); /* Clear interrupt on selected channel */ + __NOP(); + __NOP(); + + gp->IE |= (1 << channel); /* Interrupt on selected channel + is not masked */ +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + LPC_GPIO_Type * gp; + + gp = extp->gpio; + + gp->IE &= ~(1 << channel); /* Mask interrupt on selected channel */ + gp->IC = (1 << channel); /* Clear interrupt on selected channel */ + __NOP(); + __NOP(); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/ext_lld.h b/os/hal/platforms/LPC122x/ext_lld.h new file mode 100644 index 000000000..89e720494 --- /dev/null +++ b/os/hal/platforms/LPC122x/ext_lld.h @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/ext_lld.h + * @brief LPC122x EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 32 + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief EXT0 driver enable switch. + * @details If set to @p TRUE the support for EXT1 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_EXT_USE_EXT0) || defined(__DOXYGEN__) +#define LPC122x_EXT_USE_EXT0 FALSE +#endif + +/** + * @brief EXT1 driver enable switch. + * @details If set to @p TRUE the support for EXT1 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_EXT_USE_EXT1) || defined(__DOXYGEN__) +#define LPC122x_EXT_USE_EXT1 FALSE +#endif + +/** + * @brief EXT2 driver enable switch. + * @details If set to @p TRUE the support for EXT1 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_EXT_USE_EXT2) || defined(__DOXYGEN__) +#define LPC122x_EXT_USE_EXT2 FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint8_t mode; + + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ + LPC_GPIO_Type *gpio; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC122x_EXT_USE_EXT0 || !defined(__DOXYGEN__) +extern EXTDriver EXTD0; +#endif + +#if LPC122x_EXT_USE_EXT1 || !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#if LPC122x_EXT_USE_EXT2 || !defined(__DOXYGEN__) +extern EXTDriver EXTD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/ext_lld_isr.c b/os/hal/platforms/LPC122x/ext_lld_isr.c new file mode 100644 index 000000000..e8ad6f841 --- /dev/null +++ b/os/hal/platforms/LPC122x/ext_lld_isr.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/ext_lld_isr.c + * @brief LPC122x EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if LPC122x_EXT_USE_EXT0 || LPC122x_EXT_USE_EXT1 || LPC122x_EXT_USE_EXT2 || \ + defined(__DOXYGEN__) +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void ext_lld_serve_interrupt(EXTDriver *extp) { + uint32_t port_stat; + uint8_t i; + + port_stat = extp->gpio->MIS; /* Read interrupt status */ + extp->gpio->IC = port_stat; /* Clear interrupt flags */ + + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (port_stat & 0x01) { + extp->config->channels[i].cb(extp, i); + } + port_stat = port_stat >> 1; + } +} +#endif +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC122x_EXT_USE_EXT0 || defined(__DOXYGEN__) +/** + * @brief PIO0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorA4) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD0); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC122x_EXT_USE_EXT1 || defined(__DOXYGEN__) +/** + * @brief PIO1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorA8) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD1); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC122x_EXT_USE_EXT2 || defined(__DOXYGEN__) +/** + * @brief PIO2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorAC) { + + CH_IRQ_PROLOGUE(); + ext_lld_serve_interrupt(&EXTD2); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(extirq_t irqn) { + + uint32_t pmask; + + switch (irqn) { + case EXTI0_IRQ: + pmask = LPC122x_EXT_EXTI0_IRQ_PRIORITY; + break; + case EXTI1_IRQ: + pmask = LPC122x_EXT_EXTI1_IRQ_PRIORITY; + break; + case EXTI2_IRQ: + pmask = LPC122x_EXT_EXTI2_IRQ_PRIORITY; + break; + } + nvicEnableVector(EINT0_IRQn + irqn, CORTEX_PRIORITY_MASK(pmask)); + +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(extirq_t irqn) { + + nvicDisableVector(EINT0_IRQn + irqn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/ext_lld_isr.h b/os/hal/platforms/LPC122x/ext_lld_isr.h new file mode 100644 index 000000000..a201cce9b --- /dev/null +++ b/os/hal/platforms/LPC122x/ext_lld_isr.h @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/ext_lld_isr.h + * @brief LPC122x EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EXTI0_IRQ 0 +#define EXTI1_IRQ 1 +#define EXTI2_IRQ 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(LPC122x_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_EXT_EXTI0_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(LPC122x_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_EXT_EXTI1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(LPC122x_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_EXT_EXTI2_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT irq port identifier. + */ +typedef uint32_t extirq_t; +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(extirq_t irqn); + void ext_lld_exti_irq_disable(extirq_t irqn); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/gpt_lld.c b/os/hal/platforms/LPC122x/gpt_lld.c new file mode 100644 index 000000000..86ea73759 --- /dev/null +++ b/os/hal/platforms/LPC122x/gpt_lld.c @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/gpt_lld.c + * @brief LPC122x GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC122x_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC122x_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC122x_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC122x_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC122x_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector74) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_GPT_USE_CT16B0 */ + +#if LPC122x_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_GPT_USE_CT16B0 */ + +#if LPC122x_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector7C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_GPT_USE_CT32B0 */ + +#if LPC122x_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC122x_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_CT16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC122x_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_CT16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC122x_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_CT32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC122x_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_CT32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC122x_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC122x_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC122x_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC122x_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC122x_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC122x_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC122x_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC122x_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC122x_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC122x_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/gpt_lld.h b/os/hal/platforms/LPC122x/gpt_lld.h new file mode 100644 index 000000000..e38fe17c1 --- /dev/null +++ b/os/hal/platforms/LPC122x/gpt_lld.h @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/gpt_lld.h + * @brief LPC122x GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC122x_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC122x_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC122x_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC122x_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC122x_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC122x_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC122x_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC122x_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC122x_GPT_USE_CT16B0 && !LPC122x_GPT_USE_CT16B1 && \ + !LPC122x_GPT_USE_CT32B0 && !LPC122x_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_CTxxBx_Type *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC122x_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC122x_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC122x_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC122x_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/hal_lld.c b/os/hal/platforms/LPC122x/hal_lld.c new file mode 100644 index 000000000..9069434ba --- /dev/null +++ b/os/hal/platforms/LPC122x/hal_lld.c @@ -0,0 +1,123 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/hal_lld.c + * @brief LPC122x HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC122x_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC122x clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc122x_clock_init(void) { + unsigned i; + + LPC_WWDT->MOD = 0; /* Disable Watchdog */ + LPC_WWDT->FEED = 0xAA; + LPC_WWDT->FEED = 0x55; + +#if LPC122x_FLASHCFG_FLASHTIM == 0 + LPC_SYSCON->PRESETCTRL |= (1 << 15); /* Flash 1-cycle read mode */ +#else + LPC_FLASHCTRL->FLASHCFG = 0; /* 2 system clock cycles flash access time */ + LPC_SYSCON->PRESETCTRL &= ~(1 << 15); /* Flash multi-cycle read mode */ +#endif + + /* System oscillator initialization if required.*/ +#if LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC122x_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC122x_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC122x_SYSPLLCTRL_MSEL | LPC122x_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC122x_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC122x_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0xE009001F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/os/hal/platforms/LPC122x/hal_lld.h b/os/hal/platforms/LPC122x/hal_lld.h new file mode 100644 index 000000000..35624962a --- /dev/null +++ b/os/hal/platforms/LPC122x/hal_lld.h @@ -0,0 +1,217 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC122x.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC122x" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC122x_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC122x_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC122x_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC122x_SYSPLL_MUL 2 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC122x_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC122x_SYSPLL_DIV 8 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC122x_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC122x_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC122x_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC122x_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC122x_SYSOSCCTRL 0 +#else +#define LPC122x_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC122x_SYSPLLCLKIN SYSOSCCLK +#elif LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC122x_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC122x_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC122x_SYSPLL_MUL >= 1) && (LPC122x_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC122x_SYSPLLCTRL_MSEL (LPC122x_SYSPLL_MUL - 1) +#else +#error "LPC122x_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC122x_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC122x_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC122x_SYSPLL_DIV == 4 +#define LPC122x_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC122x_SYSPLL_DIV == 8 +#define LPC122x_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC122x_SYSPLL_DIV == 16 +#define LPC122x_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC122x_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC122x_SYSPLLCCO (LPC122x_SYSPLLCLKIN * LPC122x_SYSPLL_MUL * \ + LPC122x_SYSPLL_DIV) + +#if (LPC122x_SYSPLLCCO < 156000000) || (LPC122x_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC122x_SYSPLLCLKOUT (LPC122x_SYSPLLCCO / LPC122x_SYSPLL_DIV) + +#if (LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC122x_MAINCLK IRCOSCCLK +#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC122x_MAINCLK LPC122x_SYSPLLCLKIN +#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC122x_MAINCLK WDGOSCCLK +#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC122x_MAINCLK LPC122x_SYSPLLCLKOUT +#else +#error "invalid LPC122x_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC122x_SYSCLK (LPC122x_MAINCLK / LPC122x_SYSABHCLK_DIV) +#if LPC122x_SYSCLK > 45000000 +#error "AHB clock frequency out of the acceptable range (45MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC122x_SYSCLK <= 30000000) || defined(__DOXYGEN__) +#define LPC122x_FLASHCFG_FLASHTIM 0 +#else +#define LPC122x_FLASHCFG_FLASHTIM 1 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc122x_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/i2c_lld.c b/os/hal/platforms/LPC122x/i2c_lld.c new file mode 100644 index 000000000..32055d4c2 --- /dev/null +++ b/os/hal/platforms/LPC122x/i2c_lld.c @@ -0,0 +1,438 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x I2C driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + + +/** + * @file LPC122x/i2c_lld.h + * @brief LPC122x I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +I2CDriver I2CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Handling of stalled I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_safety_timeout(void *p) { + I2CDriver *i2cp = (I2CDriver *)p; + + chSysLockFromIsr(); + if (i2cp->thread) { + Thread *tp = i2cp->thread; + i2cp->thread = NULL; + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + } + chSysUnlockFromIsr(); +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) { + i2cflags_t error = 0; + + switch (status) { + case I2C_STATE_ARB_LOST: + error = I2CD_ARBITRATION_LOST; + break; + case I2C_STATE_BUS_ERROR: + error = I2CD_BUS_ERROR; + break; + case I2C_STATE_MS_SLAR_NACK: + case I2C_STATE_MS_TDAT_NACK: + case I2C_STATE_MS_SLAW_NACK: + error = I2CD_ACK_FAILURE ; + break; + } + + /* If some error has been identified then sends wakes the waiting thread.*/ + i2cp->errors = error; + wakeup_isr(i2cp, RDY_RESET); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(Vector70) { + uint32_t status; + + CH_IRQ_PROLOGUE(); + status = LPC_I2C->STAT; + switch(status) { + case I2C_STATE_MS_START: /* A START condition has been transmitted. */ + if (I2CD1.txbytes > 0) { + LPC_I2C->DAT = I2CD1.addr; /* Write slave address with WR bit. */ + } + else { + LPC_I2C->DAT = I2CD1.addr | I2C_RD_BIT; /* Write slave address with RD bit. */ + } + + LPC_I2C->CONCLR = I2C_CONCLR_STAC | I2C_CONCLR_SIC; /* Clear START and SI bit. */ + break; + + case I2C_STATE_MS_SLAR_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + case I2C_STATE_MS_TDAT_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + case I2C_STATE_MS_SLAW_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */ + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + i2c_lld_serve_error_interrupt(&I2CD1, status); + break; + + case I2C_STATE_MS_SLAW_ACK: /* SLA + W has been transmitted, ACK has been received. */ + case I2C_STATE_MS_TDAT_ACK: /* Data byte has been transmitted, ACK has been received. */ + if (I2CD1.txbytes > 0) { + LPC_I2C->DAT = *I2CD1.txbuf++; /* Write data. */ + I2CD1.txbytes--; + } + else { + if (I2CD1.rxbytes > 0) { + LPC_I2C->CONSET = I2C_CONSET_STO | I2C_CONSET_STA; /* Set START and STOP bit. */ + } /* STOP bit will be transmit, then START bit. */ + else { + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + wakeup_isr(&I2CD1, RDY_OK); + } + } + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + break; + + case I2C_STATE_MS_SLAR_ACK: /* SLA + R has been transmitted, ACK has been received. */ + case I2C_STATE_MS_RDAT_ACK: /* Data byte has been received, ACK has been returned. */ + if (status == I2C_STATE_MS_RDAT_ACK) { + *I2CD1.rxbuf++ = LPC_I2C->DAT; /* Read data */ + I2CD1.rxbytes--; + } + if (I2CD1.rxbytes == 1) { + LPC_I2C->CONCLR = I2C_CONCLR_SIC | I2C_CONCLR_AAC; /* Clear SI and ACK bit. */ + } + else { + LPC_I2C->CONSET = I2C_CONSET_AA; /* Set ACK bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + } + break; + + case I2C_STATE_MS_RDAT_NACK: /* Data byte has been received, NOT ACK has been returned. */ + *I2CD1.rxbuf++ = LPC_I2C->DAT; /* Read data. */ + I2CD1.rxbytes--; + LPC_I2C->CONSET = I2C_CONSET_STO; /* Set STOP bit. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + wakeup_isr(&I2CD1, RDY_OK); + break; + + case I2C_STATE_BUS_ERROR: /* Bus error. */ + case I2C_STATE_ARB_LOST: /* Arbitration lost. */ + LPC_I2C->CONCLR = I2C_CONCLR_SIC; /* Clear SI bit. */ + i2c_lld_serve_error_interrupt(&I2CD1, status); + break; + + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = LPC_I2C; + + LPC_IOCON->PIO0_10 = 0x0482; /* Set I2C SCL pin function */ + LPC_IOCON->PIO0_11 = 0x0482; /* Set I2C SDA pin function */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + uint32_t i2cscl; + uint32_t mulh, mull, div; + LPC_I2C_Type *dp = i2cp->i2c; + + /* Make sure I2C peripheral is disabled */ + dp->CONCLR = I2C_CONCLR_ENC; + + /* If in stopped state then enables the I2C clock. */ + if (i2cp->state == I2C_STOP) { + + if (&I2CD1 == i2cp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); /* Enable clock. */ + LPC_SYSCON->PRESETCTRL &= ~(1 << 1); /* Reset I2C peripheral.*/ + __NOP(); + LPC_SYSCON->PRESETCTRL |= (1 << 1); + nvicEnableVector(I2C_IRQn, + CORTEX_PRIORITY_MASK(LPC122x_I2C_IRQ_PRIORITY)); + } + + } + + /* Setup I2C clock parameters.*/ + i2cscl = (LPC122x_SYSCLK/(i2cp->config->clock_timing)); + if (i2cp->config->mode == I2C_FAST_MODE) { + div = 19; + mull = 13; + mulh = 6; + } else if (i2cp->config->mode == I2C_FAST_MODE_PLUS) { + div = 3; + mull = 2; + mulh = 1; + } else { /* i2cp->config->mode == I2C_STANDARD_MODE */ + div = 2; + mull = 1; + mulh = 1; + } + + dp->SCLH = (mulh * i2cscl) / div; + dp->SCLL = (mull *i2cscl) / div; + + /* Enable I2C.*/ + dp->CONSET |= I2C_CONSET_EN; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2cp->i2c->CONCLR = I2C_CONCLR_ENC; + + if (&I2CD1 == i2cp) { + nvicDisableVector(I2C_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 5); + } + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on STM32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + LPC_I2C_Type *dp = i2cp->i2c; + VirtualTimer vt; + + i2cp->addr = addr << 1; + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields */ + i2cp->errors = 0; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CONSET = I2C_CONSET_STA; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + LPC_I2C_Type *dp = i2cp->i2c; + VirtualTimer vt; + + i2cp->addr = addr << 1; + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields */ + i2cp->errors = 0; + i2cp->txbuf = txbuf; + i2cp->txbytes = txbytes; + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CONSET = I2C_CONSET_STA; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/i2c_lld.h b/os/hal/platforms/LPC122x/i2c_lld.h new file mode 100644 index 000000000..edff13a95 --- /dev/null +++ b/os/hal/platforms/LPC122x/i2c_lld.h @@ -0,0 +1,228 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x I2C driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file LPC122x/i2c_lld.h + * @brief LPC122x I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_CONSET_AA 0x04 /* Assert acknowledge flag. */ +#define I2C_CONSET_SI 0x08 /* I2C interrupt flag. */ +#define I2C_CONSET_STO 0x10 /* STOP flag. */ +#define I2C_CONSET_STA 0x20 /* START flag. */ +#define I2C_CONSET_EN 0x40 /* I2C interface enable. */ + +#define I2C_CONCLR_AAC 0x04 /* Assert acknowledge Clear bit. */ +#define I2C_CONCLR_SIC 0x08 /* I2C interrupt Clear bit. */ +#define I2C_CONCLR_STAC 0x20 /* START flag Clear bit. */ +#define I2C_CONCLR_ENC 0x40 /* I2C interface Disable bit. */ + +#define I2C_WR_BIT 0x00 +#define I2C_RD_BIT 0x01 + +#define I2C_STATE_MS_START 0x08 +#define I2C_STATE_MS_RSTART 0x10 +#define I2C_STATE_MS_SLAW_ACK 0x18 +#define I2C_STATE_MS_SLAW_NACK 0x20 +#define I2C_STATE_MS_TDAT_ACK 0x28 +#define I2C_STATE_MS_TDAT_NACK 0x30 +#define I2C_STATE_ARB_LOST 0x38 + +#define I2C_STATE_MS_SLAR_ACK 0x40 +#define I2C_STATE_MS_SLAR_NACK 0x48 +#define I2C_STATE_MS_RDAT_ACK 0x50 +#define I2C_STATE_MS_RDAT_NACK 0x58 + +#define I2C_STATE_BUS_ERROR 0x00 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief I2C interrupt priority level setting. + */ +#if !defined(LPC122x_I2C_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_I2C_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + I2C_STANDARD_MODE = 1, + I2C_FAST_MODE = 2, + I2C_FAST_MODE_PLUS = 3 +} i2cmode_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + i2cmode_t mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_timing; /**< @brief Specifies the clock timing */ +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief Pointer to the transmit buffer. + */ + const uint8_t *txbuf; + /** + * @brief Number of bytes to transmit. + */ + size_t txbytes; + /** + * @brief Pointer to the receive buffer. + */ + uint8_t *rxbuf; + /** + * @brief Number of bytes to receive. + */ + size_t rxbytes; + /** + * @brief Pointer to the I2C registers block. + */ + LPC_I2C_Type *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern I2CDriver I2CD1; +#endif + +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + + + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/pal_lld.c b/os/hal/platforms/LPC122x/pal_lld.c new file mode 100644 index 000000000..c23608a75 --- /dev/null +++ b/os/hal/platforms/LPC122x/pal_lld.c @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +/** + * @file LPC122x/pal_lld.c + * @brief LPC122x GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC122x I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC122x ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO0->DIR = config->P0.dir; + LPC_GPIO1->DIR = config->P1.dir; + LPC_GPIO2->DIR = config->P2.dir; + LPC_GPIO0->MASK = 0; + LPC_GPIO1->MASK = 0; + LPC_GPIO2->MASK = 0; + LPC_GPIO0->OUT = config->P0.data; + LPC_GPIO1->OUT = config->P1.data; + LPC_GPIO2->OUT = config->P2.data; +} + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +uint32_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint32_t offset) { + + uint32_t p; + + port->MASK = ~((mask) << offset); + p = port->PIN; + port->MASK = 0; + return p; +} + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint32_t offset, + uint32_t bits) { + + port->MASK = ~((mask) << offset); + port->OUT = bits; + port->MASK = 0; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/pal_lld.h b/os/hal/platforms/LPC122x/pal_lld.h new file mode 100644 index 000000000..4cf870410 --- /dev/null +++ b/os/hal/platforms/LPC122x/pal_lld.h @@ -0,0 +1,337 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +/** + * @file LPC122x/pal_lld.h + * @brief LPC122x GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc122x_gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + lpc122x_gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + lpc122x_gpio_setup_t P1; + /** @brief GPIO 2 setup data.*/ + lpc122x_gpio_setup_t P2; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_Type *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO0 +#define GPIO0 LPC_GPIO0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 LPC_GPIO1 +#define GPIO1 LPC_GPIO1 + +/** + * @brief GPIO2 port identifier. + */ +#define IOPORT3 LPC_GPIO2 +#define GPIO2 LPC_GPIO2 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) \ + _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) \ + ((port)->PIN) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) \ + ((port)->PIN) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + ((port)->OUT = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) \ + ((port)->SET = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) \ + ((port)->CLR = (bits)) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + _pal_lld_readgroup(port, mask, offset) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + _pal_lld_writegroup(port, mask, offset, bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((bit) == PAL_LOW) ? pal_lld_clearpad(port, pad) : \ + pal_lld_setpad(port, pad) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->SET = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->CLR = 1 << (pad)) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) \ + ((port)->NOT = 1 << (pad)) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); + uint32_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint32_t offset); + void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint32_t offset, + uint32_t bits); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/platform.mk b/os/hal/platforms/LPC122x/platform.mk new file mode 100644 index 000000000..9a9853fbd --- /dev/null +++ b/os/hal/platforms/LPC122x/platform.mk @@ -0,0 +1,14 @@ +# List of all the LPC122x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC122x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC122x/spi_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC122x diff --git a/os/hal/platforms/LPC122x/pwm_lld.c b/os/hal/platforms/LPC122x/pwm_lld.c new file mode 100644 index 000000000..24e5b2639 --- /dev/null +++ b/os/hal/platforms/LPC122x/pwm_lld.c @@ -0,0 +1,446 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/pwm_lld.c + * @brief LPC122x PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. + */ +#if LPC122x_PWM_USE_CT16B0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TIM2 when enabled. + */ +#if LPC122x_PWM_USE_CT16B1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TIM3 when enabled. + */ +#if LPC122x_PWM_USE_CT32B0 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TIM4 when enabled. + */ +#if LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if LPC122x_PWM_USE_CT16B0 || LPC122x_PWM_USE_CT16B1 || \ + LPC122x_PWM_USE_CT32B0 || LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__) +/** + * @brief Common TIM2...TIM5 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint16_t sr; + + sr = pwmp->tim->IR; + pwmp->tim->IR = sr; + if ((sr & IR_MR0INT) != 0) + pwmp->config->channels[0].callback(pwmp); + if ((sr & IR_MR1INT) != 0) + pwmp->config->channels[1].callback(pwmp); + if ((sr & IR_MR3INT) != 0) + pwmp->config->callback(pwmp); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC122x_PWM_USE_CT16B0 || defined(__DOXYGEN__) +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector74) { + + CH_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD1); + CH_IRQ_EPILOGUE(); +} + +#endif /* STM32_PWM_USE_TIM1 */ + +#if LPC122x_PWM_USE_CT16B1 || defined(__DOXYGEN__) +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD2); + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_PWM_USE_CT16B1 */ + +#if LPC122x_PWM_USE_CT32B0 || defined(__DOXYGEN__) +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector7C) { + + CH_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD3); + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_PWM_USE_CT32B0 */ + +#if LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__) +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD4); + CH_IRQ_EPILOGUE(); +} +#endif /* LPC122x_PWM_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if LPC122x_PWM_USE_CT16B0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.tim = LPC_CT16B0; + +#if LPC122x_PWM_USE_CT16B0_CH0 +#if LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO0_11 + LPC_IOCON->PIO0_11 = 0x84; +#elif LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO0_28 + LPC_IOCON->PIO0_28 = 0x84; +#else /* LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO2_0 */ + LPC_IOCON->PIO2_0 = 0x84; +#endif +#endif + +#if LPC122x_PWM_USE_CT16B0_CH1 +#if LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO0_12 + LPC_IOCON->PIO0_12 = 0x84; +#elif LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO0_29 + LPC_IOCON->PIO0_29 = 0x84; +#else /* LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO2_1 */ + LPC_IOCON->PIO2_1 = 0x83; +#endif +#endif +#endif + +#if LPC122x_PWM_USE_CT16B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.tim = LPC_CT16B1; + +#if LPC122x_PWM_USE_CT16B1_CH0 +#if LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO0_15 + LPC_IOCON->PIO0_15 = 0x84; +#elif LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO1_5 + LPC_IOCON->PIO1_5 = 0x83; +#else /* LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO2_2 */ + LPC_IOCON->PIO2_2 = 0x83; +#endif +#endif + +#if LPC122x_PWM_USE_CT16B1_CH1 +#if LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO0_16 + LPC_IOCON->PIO0_16 = 0x84; +#elif LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO1_6 + LPC_IOCON->PIO1_6 = 0x82; +#else /* LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO2_3 */ + LPC_IOCON->PIO2_3 = 0x83; +#endif +#endif +#endif + +#if LPC122x_PWM_USE_CT32B0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.tim = LPC_CT32B0; + +#if LPC122x_PWM_USE_CT32B0_CH0 +#if LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO0_1 + LPC_IOCON->PIO0_1 = 0x84; +#elif LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO0_18 + LPC_IOCON->PIO0_18 = 0x84; +#else /* LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO2_4 */ + LPC_IOCON->PIO2_4 = 0x83; +#endif +#endif + +#if LPC122x_PWM_USE_CT32B0_CH1 +#if LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO0_2 + LPC_IOCON->PIO0_2 = 0x84; +#elif LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO0_19 + LPC_IOCON->PIO0_19 = 0x84; +#else /* LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO2_5 */ + LPC_IOCON->PIO2_5 = 0x83; +#endif +#endif +#endif + +#if LPC122x_PWM_USE_CT32B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.tim = LPC_CT32B1; + +#if LPC122x_PWM_USE_CT32B1_CH0 +#if LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO0_6 + LPC_IOCON->PIO0_6 = 0x84; +#elif LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO0_23 + LPC_IOCON->PIO0_23 = 0x84; +#else /* LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO2_8 */ + LPC_IOCON->PIO2_8 = 0x83; +#endif +#endif + +#if LPC122x_PWM_USE_CT32B1_CH1 +#if LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO0_7 + LPC_IOCON->PIO0_7 = 0x84; +#elif LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO0_24 + LPC_IOCON->PIO0_24 = 0x84; +#else /* LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO2_9 */ + LPC_IOCON->PIO2_9 = 0x83; +#endif +#endif +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t pr; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if LPC122x_PWM_USE_CT16B0 + if (&PWMD1 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, LPC122x_PWM_CT16B0_IRQ_PRIORITY); + } +#endif +#if LPC122x_PWM_USE_CT16B1 + if (&PWMD2 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, LPC122x_PWM_CT16B1_IRQ_PRIORITY); + } +#endif +#if LPC122x_PWM_USE_CT32B0 + if (&PWMD3 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, LPC122x_PWM_CT32B0_IRQ_PRIORITY); + } +#endif +#if LPC122x_PWM_USE_CT32B1 + if (&PWMD4 == pwmp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, LPC122x_PWM_CT32B1_IRQ_PRIORITY); + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->tim->TCR = 0; + } + + /* Output enables and polarities setup.*/ + if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) + pwmp->tim->PWMC = (1 << 0); + + if(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW) + pwmp->tim->PWMC |= (1 << 1); + + /* Timer configured and started.*/ + pr = (uint16_t)((LPC122x_SYSCLK / pwmp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * pwmp->config->frequency) == LPC122x_SYSCLK, + "pwm_lld_start(), #1", "invalid frequency"); + + pwmp->tim->TC = 0; + pwmp->tim->PR = pr; + pwmp->tim->IR = 0xFF; + pwmp->tim->MCR = MCR_MR3R; /* Reset on Match3 */ + pwmp->tim->MR3 = pwmp->config->period; + + if (pwmp->config->callback != NULL) + pwmp->tim->MCR |= MCR_MR3I; + + pwmp->tim->TCR = 1; /* Timer start */ +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->tim->TCR = 0; /* Timer disabled. */ + pwmp->tim->MCR = 0; /* All IRQs disabled. */ + pwmp->tim->IR = 0xFF; /* Clear eventual pending IRQs. */ + pwmp->tim->PWMC = 0; /* PWM outputs disable */ + +#if LPC122x_PWM_USE_CT16B0 + if (&PWMD1 == pwmp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC122x_PWM_USE_CT16B1 + if (&PWMD2 == pwmp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC122x_PWM_USE_CT32B0 + if (&PWMD3 == pwmp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC122x_PWM_USE_CT32B1 + if (&PWMD4 == pwmp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + pwmp->tim->MCR &= ~(7 << (channel * 3)); + + if ( channel == 0) + pwmp->tim->MR0 = width; /* New duty cycle. */ + else + pwmp->tim->MR1 = width; /* New duty cycle. */ + /* If there is a callback defined for the channel then the associated + interrupt must be enabled.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->tim->IR = (1 << channel); /* Clear interrupt flag*/ + pwmp->tim->MCR |= (1 << (channel * 3)); /* Set interrupt on selected channel */ + } + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + if ( channel == 0) + pwmp->tim->MR0 = 0; + else + pwmp->tim->MR1 = 0; + pwmp->tim->MCR &= ~(7 << (channel * 3)); + pwmp->tim->IR = (1 << channel); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/pwm_lld.h b/os/hal/platforms/LPC122x/pwm_lld.h new file mode 100644 index 000000000..d0d54d234 --- /dev/null +++ b/os/hal/platforms/LPC122x/pwm_lld.h @@ -0,0 +1,455 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/pwm_lld.h + * @brief LPC122x PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ +#undef PWM_OUTPUT_ACTIVE_HIGH + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IR_MR0INT (1 << 0) +#define IR_MR1INT (1 << 1) +#define IR_MR2INT (1 << 2) +#define IR_MR3INT (1 << 3) +#define IR_CR0INT (1 << 4) +#define IR_CR1INT (1 << 5) +#define IR_CR2INT (1 << 6) +#define IR_CR3INT (1 << 7) + +#define MCR_MR3I (1 << 9) +#define MCR_MR3R (1 << 10) +#define MCR_MR3S (1 << 11) + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 2 + +#define PWM_CT16B0_CH0_IS_PIO0_11 0 +#define PWM_CT16B0_CH0_IS_PIO0_28 1 +#define PWM_CT16B0_CH0_IS_PIO2_0 2 + +#define PWM_CT16B0_CH1_IS_PIO0_12 0 +#define PWM_CT16B0_CH1_IS_PIO0_29 1 +#define PWM_CT16B0_CH1_IS_PIO2_1 2 + +#define PWM_CT16B1_CH0_IS_PIO0_15 0 +#define PWM_CT16B1_CH0_IS_PIO1_5 1 +#define PWM_CT16B1_CH0_IS_PIO2_2 2 + +#define PWM_CT16B1_CH1_IS_PIO0_16 0 +#define PWM_CT16B1_CH1_IS_PIO1_6 1 +#define PWM_CT16B1_CH1_IS_PIO2_3 2 + + +#define PWM_CT32B0_CH0_IS_PIO0_1 0 +#define PWM_CT32B0_CH0_IS_PIO0_18 1 +#define PWM_CT32B0_CH0_IS_PIO2_4 2 + +#define PWM_CT32B0_CH1_IS_PIO0_2 0 +#define PWM_CT32B0_CH1_IS_PIO0_19 1 +#define PWM_CT32B0_CH1_IS_PIO2_5 2 + + +#define PWM_CT32B1_CH0_IS_PIO0_6 0 +#define PWM_CT32B1_CH0_IS_PIO0_23 1 +#define PWM_CT32B1_CH0_IS_PIO2_8 2 + +#define PWM_CT32B1_CH1_IS_PIO0_7 0 +#define PWM_CT32B1_CH1_IS_PIO0_24 1 +#define PWM_CT32B1_CH1_IS_PIO2_9 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_PWM_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B0 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_PWM_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B1 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_PWM_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B0 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_PWM_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B1 FALSE +#endif + +/** + * @brief PWMD1 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD1 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT16B0_CH0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B0_CH0 FALSE +#endif + +/** + * @brief PWMD1 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD1 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT16B0_CH1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B0_CH1 FALSE +#endif + +/** + * @brief PWMD2 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD2 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT16B1_CH0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B1_CH0 FALSE +#endif + +/** + * @brief PWMD2 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD2 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT16B1_CH1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT16B1_CH1 FALSE +#endif + +/** + * @brief PWMD3 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD3 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT32B0_CH0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B0_CH0 FALSE +#endif + +/** + * @brief PWMD3 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD3 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT32B0_CH1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B0_CH1 FALSE +#endif + +/** + * @brief PWMD4 Channel 0 driver enable switch. + * @details If set to @p TRUE PWMD4 Channel 0 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT32B1_CH0) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B1_CH0 FALSE +#endif + +/** + * @brief PWMD4 Channel 1 driver enable switch. + * @details If set to @p TRUE PWMD4 Channel 1 is enabled. + * @note The default is @p FALSE. + */ +#if !defined(LPC122x_PWM_USE_CT32B1_CH1) || defined(__DOXYGEN__) +#define LPC122x_PWM_USE_CT32B1_CH1 FALSE +#endif +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(LPC122x_PWM_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B0_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(LPC122x_PWM_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B1_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(LPC122x_PWM_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B0_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(LPC122x_PWM_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B1_IRQ_PRIORITY 3 +#endif + +/** + * @brief PWM_CT16B0_CH0 signal selector. + */ +#if !defined(LPC122x_PWM_CT16B0_CH0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B0_CH0_SELECTOR PWM_CT16B0_CH0_IS_PIO0_11 +#endif + +/** + * @brief PWM_CT16B0_CH1 signal selector. + */ +#if !defined(LPC122x_PWM_CT16B0_CH1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B0_CH1_SELECTOR PWM_CT16B0_CH1_IS_PIO0_12 +#endif + +/** + * @brief PWM_CT16B1_CH0 signal selector. + */ +#if !defined(LPC122x_PWM_CT16B1_CH0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B1_CH0_SELECTOR PWM_CT16B1_CH0_IS_PIO0_15 +#endif + +/** + * @brief PWM_CT16B1_CH1 signal selector. + */ +#if !defined(LPC122x_PWM_CT16B1_CH1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT16B1_CH1_SELECTOR PWM_CT16B1_CH1_IS_PIO0_16 +#endif + +/** + * @brief PWM_CT32B0_CH0 signal selector. + */ +#if !defined(LPC122x_PWM_CT32B0_CH0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B0_CH0_SELECTOR PWM_CT32B0_CH0_IS_PIO0_1 +#endif + +/** + * @brief PWM_CT32B0_CH1 signal selector. + */ +#if !defined(LPC122x_PWM_CT32B0_CH1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B0_CH1_SELECTOR PWM_CT32B0_CH1_IS_PIO0_2 +#endif + +/** + * @brief PWM_CT32B1_CH0 signal selector. + */ +#if !defined(LPC122x_PWM_CT32B1_CH0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B1_CH0_SELECTOR PWM_CT32B1_CH0_IS_PIO0_6 +#endif + +/** + * @brief PWM_CT32B1_CH1 signal selector. + */ +#if !defined(LPC122x_PWM_CT32B1_CH1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_PWM_CT32B1_CH1_SELECTOR PWM_CT32B1_CH1_IS_PIO0_7 +#endif + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + LPC_CTxxBx_Type *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->MR3 = (period)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC122x_PWM_USE_CT16B0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if LPC122x_PWM_USE_CT16B1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if LPC122x_PWM_USE_CT32B0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if LPC122x_PWM_USE_CT32B1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/rtc_lld.c b/os/hal/platforms/LPC122x/rtc_lld.c new file mode 100644 index 000000000..ad1a15f80 --- /dev/null +++ b/os/hal/platforms/LPC122x/rtc_lld.c @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file LPC122x/rtc_lld.c + * @brief LPC122x RTC low level driver. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ + +#if LPC122x_RTC_USE_ALARM || defined(__DOXYGEN__) +CH_IRQ_HANDLER(VectorB8) { + uint32_t flag; + + CH_IRQ_PROLOGUE(); + + flag = LPC_RTC->RIS; + LPC_RTC->ICR = flag; /* Clear interrupt flag */ + + if ((flag & RIS_RTCRIS) && (RTCD1.callback != NULL)) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers. + * + * @api + */ +void rtc_lld_init(void) { + uint32_t temp[2]; + + if(LPC_SYSCON->SYSRESSTAT & 0x1) { /* POR detected */ + + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1UL << 19); /* Disable clock for RTC */ + LPC_PMU->SYSCFG &= ~(0x0FUL << 11); /* Clear RTC clock source */ + LPC_SYSCON->RTCCLKDIV = LPC122x_RTC_CLKDIV; + LPC_PMU->SYSCFG |= (LPC122x_RTCCLK << 11); /* Set RTC clock source */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 19); /* Enable clock for RTC registers*/ + LPC_RTC->ICR = 0x01; /* Clear interrupt flag */ + LPC_RTC->CR= 1; /* Enable RTC start */ + LPC_SYSCON->SYSRESSTAT = 0x1; /* Clear POR flag */ + + while(LPC_RTC->DR <3 ) { /* Wait, data read not valid */ + __NOP(); + } + } + else { + + LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 19); /* Enable clock for RTC registers*/ + + do { + temp[0] = LPC_RTC->DR; + temp[1] = LPC_RTC->DR; + } while(temp[0] == temp[1]); + +#if LPC122x_RTC_USE_ALARM + if (temp[1] >= LPC_RTC->MR) { /* Check for match event in software, handle if found */ + CH_IRQ_HANDLER(VectorB8); /* Manually invoke ISR */ + } +#endif + + } + +#if LPC122x_RTC_USE_ALARM + nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(LPC122x_RTC_IRQ_PRIORITY)); +#endif + return; +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to set it on STM32 platform. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { + (void)rtcp; + + LPC_RTC->LR = timespec->tv_sec; +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { + (void)rtcp; + + timespec->tv_sec = LPC_RTC->DR; +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset for both comparators is 0. + * @note Function does not performs any checks of alarm time validity. + * + * @param[in] rtcp Pointer to RTC driver structure. + * @param[in] alarm Alarm identifier. Can be 1 or 2. + * @param[in] alarmspec Pointer to a @p RTCAlarm structure. + * + * @api + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + (void)rtcp; + (void)alarm; + LPC_RTC->MR = alarmspec->tv_sec; + +} + +/** + * @brief Get alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @api + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + (void)rtcp; + (void)alarm; + alarmspec->tv_sec = LPC_RTC->MR; + +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + LPC_RTC->ICR = 0x01; /* Clear interrupt flag */ + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + LPC_RTC->ICSC = ICSC_RTCCIC; /* Enable RTC interrupt */ + } + else { + + LPC_RTC->ICSC = 0; /* Disable RTC interrupt */ + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } +} + +#include "chrtclib.h" + +/** + * @brief Get current time in format suitable for usage in FatFS. + * + * @param[in] rtcp pointer to RTC driver structure + * @return FAT time value. + * + * @api + */ +uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) { + uint32_t fattime; + struct tm timp; + + rtcGetTimeTm(rtcp, &timp); + + fattime = (timp.tm_sec) >> 1; + fattime |= (timp.tm_min) << 5; + fattime |= (timp.tm_hour) << 11; + fattime |= (timp.tm_mday) << 16; + fattime |= (timp.tm_mon + 1) << 21; + fattime |= (timp.tm_year - 80) << 25; + + return fattime; +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/rtc_lld.h b/os/hal/platforms/LPC122x/rtc_lld.h new file mode 100644 index 000000000..b3d3b48ff --- /dev/null +++ b/os/hal/platforms/LPC122x/rtc_lld.h @@ -0,0 +1,236 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file LPC122x/rtc_lld.h + * @brief LPC122x RTC low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define CR_RTCSTART 1 +#define ICSC_RTCCIC 1 +#define RIS_RTCRIS 1 +#define MIS_RTCMIS 1 +#define ICR_RTCICR 1 + +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + +/** + * @brief RTC Clock source type + */ +#define SYSCFG_RTCCLK_1Hz 0 /* 1 Hz clock */ +#define SYSCFG_RTCCLK_DEL_1Hz 1 /* delayed 1 Hz clock */ +#define SYSCFG_RTCCLK_1kHz 10 /* 1 kHz clock */ +#define SYSCFG_RTCCLK_PCLK 4 /* Main clock source divided by RTC */ + /* clock divider */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ + +/** + * @brief RTC PCLK divider. + */ +#if !defined(LPC122x_RTC_CLKDIV) || defined(__DOXYGEN__) +#define LPC122x_RTC_CLKDIV 0 +#endif + +/** + * @brief RTC CLK Source + */ +#if !defined(LPC122x_RTCCLK) || defined(__DOXYGEN__) +#define LPC122x_RTCCLK SYSCFG_RTCCLK_1Hz +#endif + +/** + * @brief RTC Alarm enable. + */ +#if !defined(LPC122x_RTC_USE_ALARM) || defined(__DOXYGEN__) +#define LPC122x_RTC_USE_ALARM FALSE +#endif + +/** + * @brief RTC IRQ Priority. + */ +#if !defined(LPC122x_RTC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_RTC_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !(LPC122x_RTCCLK == SYSCFG_RTCCLK_1Hz) && \ + !(LPC122x_RTCCLK == SYSCFG_RTCCLK_DEL_1Hz) && \ + !(LPC122x_RTCCLK == SYSCFG_RTCCLK_1kHz) && \ + !(LPC122x_RTCCLK == SYSCFG_RTCCLK_PCLK) +#error "Invalid source selected for RTC clock" +#endif + +#if LPC122x_RTCCLK == SYSCFG_RTCCLK_1kHz +#error "1 kHz RTC clock not supported" +#endif + +#if LPC122x_RTCCLK == SYSCFG_RTCCLK_PCLK +#if (LPC122x_MAINCLK/LPC122x_RTC_CLKDIV) != 1 +#error "RTC clock is not 1 Hz" +#endif +#endif +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of a structure representing an RTC wakeup period. + */ +typedef struct RTCWakeup RTCWakeup; + +/** + * @brief Type of a structure representing an RTC callbacks config. + */ +typedef struct RTCCallbackConfig RTCCallbackConfig; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_ALARM = 0 /** Triggered on alarm. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC callbacks config. + */ +struct RTCCallbackConfig{ + /** + * @brief Generic RTC callback pointer. + */ + rtccb_t callback; +}; + +/** + * @brief Structure representing an RTC time stamp. + */ +struct RTCTime { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ + /** + * @brief Callback pointer. + */ + rtccb_t callback; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/serial_lld.c b/os/hal/platforms/LPC122x/serial_lld.c new file mode 100644 index 000000000..88ba5661f --- /dev/null +++ b/os/hal/platforms/LPC122x/serial_lld.c @@ -0,0 +1,383 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/serial_lld.c + * @brief LPC122x low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_UART0_Type *u = sdp->uart; + uint32_t upclk; +#if LPC122x_SERIAL_USE_UART0 + if (&SD1 == sdp) { + upclk = LPC122x_SERIAL_UART0_PCLK; + } +#endif +#if LPC122x_SERIAL_USE_UART1 + if (&SD2 == sdp) { + upclk = LPC122x_SERIAL_UART1_PCLK; + } +#endif + uint32_t div = upclk / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(LPC_UART0_Type *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_UART0_Type *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC122x_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_UART0_Type *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC122x_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/** + * @brief Driver SD2 output notification. + */ +#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + preload(&SD2); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC122x_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_UART0; +#if LLPC122x_SERIAL_RXD0_SELECTOR == RXD0_IS_PIO0_1 + LPC_IOCON->PIO0_1 = 0x82; /* RDX0 without resistors. */ +#else /* LPC122x_SERIAL_RXD0_SELECTOR == RXD1_IS_PIO2_1 */ + LPC_IOCON->PIO2_1 = 0x84; /* RXD0 without resistors. */ +#endif +#if LLPC122x_SERIAL_TXD0_SELECTOR == TXD0_IS_PIO0_8 + LPC_IOCON->PIO0_2 = 0x82; /* TDX0 without resistors. */ +#else /* LPC122x_SERIAL_TXD0_SELECTOR == TXD0_IS_PIO2_2 */ + LPC_IOCON->PIO2_2 = 0x84; /* TXD0 without resistors. */ +#endif +#endif + +#if LPC122x_SERIAL_USE_UART1 + sdObjectInit(&SD2, NULL, notify1); + SD2.uart = (LPC_UART0_Type *) LPC_UART1; +#if LLPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO0_8 + LPC_IOCON->PIO0_8 = 0x82; /* RXD1 without resistors. */ +#elif LPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO2_11 + LPC_IOCON->PIO2_11 = 0x85; /* RXD1 without resistors. */ +#else /* LPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO2_12 */ + LPC_IOCON->PIO2_12 = 0x83; /* RXD1 without resistors. */ +#endif +#if LLPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO0_8 + LPC_IOCON->PIO0_9 = 0x82; /* TXD1 without resistors. */ +#elif LPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO2_11 + LPC_IOCON->PIO2_10 = 0x85; /* TXD1 without resistors. */ +#else /* LPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO2_12 */ + LPC_IOCON->PIO2_13 = 0x83; /* TXD1 without resistors. */ +#endif +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC122x_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UART0CLKDIV = LPC122x_SERIAL_UART0CLKDIV; + nvicEnableVector(UART0_IRQn, + CORTEX_PRIORITY_MASK(LPC122x_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif +#if LPC122x_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13); + LPC_SYSCON->UART1CLKDIV = LPC122x_SERIAL_UART1CLKDIV; + nvicEnableVector(UART1_IRQn, + CORTEX_PRIORITY_MASK(LPC122x_SERIAL_UART1_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC122x_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UART0CLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART0_IRQn); + return; + } +#endif +#if LPC122x_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->UART1CLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 13); + nvicDisableVector(UART1_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/serial_lld.h b/os/hal/platforms/LPC122x/serial_lld.h new file mode 100644 index 000000000..c7ed627d0 --- /dev/null +++ b/os/hal/platforms/LPC122x/serial_lld.h @@ -0,0 +1,317 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/serial_lld.h + * @brief LPC122x low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/** + * @brief RXD0 signal assigned to pin PIO0_1. + */ +#define RXD0_IS_PIO0_1 0 + +/** + * @brief RXD0 signal assigned to pin PIO2_1. + */ +#define RXD0_IS_PIO2_1 1 + +/** + * @brief TXD0 signal assigned to pin PIO0_2. + */ +#define TXD0_IS_PIO0_2 0 + +/** + * @brief TXD0 signal assigned to pin PIO2_2. + */ +#define TXD0_IS_PIO2_2 1 + +/** + * @brief RXD1 signal assigned to pin PIO0_8. + */ +#define RXD1_IS_PIO0_8 0 + +/** + * @brief RXD1 signal assigned to pin PIO2_11. + */ +#define RXD1_IS_PIO2_11 1 + +/** + * @brief RXD1 signal assigned to pin PIO2_12. + */ +#define RXD1_IS_PIO2_12 2 + +/** + * @brief TXD1 signal assigned to pin PIO0_9. + */ +#define TXD1_IS_PIO0_9 0 + +/** + * @brief TXD1 signal assigned to pin PIO2_10. + */ +#define TXD1_IS_PIO2_10 1 + +/** + * @brief TXD1 signal assigned to pin PIO2_13. + */ +#define TXD1_IS_PIO2_13 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC122x_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC122x_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_USE_UART1 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC122x_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC122x_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART1 PCLK divider. + */ +#if !defined(LPC122x_SERIAL_UART1CLKDIV) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_UART1CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC122x_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC122x_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_UART1_IRQ_PRIORITY 3 +#endif + +/** + * @brief RXD0 signal selector. + */ +#if !defined(LPC122x_SERIAL_RXD0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_RXD0_SELECTOR RXD0_IS_PIO0_1 +#endif + +/** + * @brief TXD0 signal selector. + */ +#if !defined(LPC122x_SERIAL_TXD0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_TXD0_SELECTOR TXD0_IS_PIO0_2 +#endif + +/** + * @brief RXD1 signal selector. + */ +#if !defined(LPC122x_SERIAL_RXD1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_RXD1_SELECTOR RXD1_IS_PIO0_8 +#endif + +/** + * @brief TXD1 signal selector. + */ +#if !defined(LPC122x_SERIAL_TXD1_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_SERIAL_TXD1_SELECTOR TXD1_IS_PIO0_9 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC122x_SERIAL_UART0CLKDIV < 1) || (LPC122x_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC122x_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC122x_SERIAL_UART1CLKDIV < 1) || (LPC122x_SERIAL_UART10CLKDIV > 255) +#error "invalid LPC122x_SERIAL_UART1CLKDIV setting" +#endif + +#if (LPC122x_SERIAL_FIFO_PRELOAD < 1) || (LPC122x_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC122x_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC122x_SERIAL_UART0_PCLK \ + (LPC122x_MAINCLK / LPC122x_SERIAL_UART0CLKDIV) + +/** + * @brief UART0 clock. + */ +#define LPC122x_SERIAL_UART1_PCLK \ + (LPC122x_MAINCLK / LPC122x_SERIAL_UART1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC122x Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_UART0_Type *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC122x_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/spi_lld.c b/os/hal/platforms/LPC122x/spi_lld.c new file mode 100644 index 000000000..4f8799a54 --- /dev/null +++ b/os/hal/platforms/LPC122x/spi_lld.c @@ -0,0 +1,352 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/spi_lld.c + * @brief LPC122x low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC122x_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSP_Type *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC122x_SSP_FIFO_DEPTH ? + LPC122x_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSP_Type *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC122x_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC122x_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC122x_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP; + + LPC_IOCON->PIO0_14 = 0x82; /* SCK0 without resistors. */ + LPC_IOCON->PIO0_16 = 0x82; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_17 = 0x82; /* MOSI0 without resistors. */ +#endif /* LPC122x_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC122x_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSPCLKDIV = LPC122x_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP_IRQn, + CORTEX_PRIORITY_MASK(LPC122x_SPI_SSP0_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC122x_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSPCLKDIV = 0; + nvicDisableVector(SSP_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/spi_lld.h b/os/hal/platforms/LPC122x/spi_lld.h new file mode 100644 index 000000000..0cb48f89f --- /dev/null +++ b/os/hal/platforms/LPC122x/spi_lld.h @@ -0,0 +1,281 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC122x/spi_lld.h + * @brief LPC122x low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC122x_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC122x_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC122x_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC122x_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC122x_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC122x_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC122x_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC122x_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC122x_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief SCK0 signal selector. + */ +#if !defined(LPC122x_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__) +#define LPC122x_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC122x_SPI_SSP0CLKDIV < 1) || (LPC122x_SPI_SSP0CLKDIV > 255) +#error "invalid LPC122x_SPI_SSP0CLKDIV setting" +#endif + +#if !LPC122x_SPI_USE_SSP0 && !LPC122x_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC122x_SPI_SSP0_PCLK \ + (LPC122x_MAINCLK / LPC122x_SPI_SSP0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSP_Type *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC122x_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC122x/system_LPC122x.h b/os/hal/platforms/LPC122x/system_LPC122x.h new file mode 100644 index 000000000..0a8ecda0f --- /dev/null +++ b/os/hal/platforms/LPC122x/system_LPC122x.h @@ -0,0 +1,65 @@ +/**************************************************************************//** + * $Id: system_LPC122x.h 6933 2011-03-23 19:02:11Z nxp28548 $ + * + * @file system_LPC12xx.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File + * for the NXP LPC12xx Device Series + * @version 1.1 + * @date $Date:: 2011-03-23#$ + * @author NXP MCU Team + * + * @note + * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + ******************************************************************************/ + +#ifndef __SYSTEM_LPC12xx_H +#define __SYSTEM_LPC12xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t MainClock; /*!< Main Clock Frequency (Main Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC12xx_H */ diff --git a/os/hal/platforms/LPC13xx/LPC13xx.h b/os/hal/platforms/LPC13xx/LPC13xx.h new file mode 100644 index 000000000..89f937e22 --- /dev/null +++ b/os/hal/platforms/LPC13xx/LPC13xx.h @@ -0,0 +1,570 @@ +/**************************************************************************** +* $Id:: LPC13xx.h 7402 2011-05-25 18:48:12Z usb00175 $ +* Project: NXP LPC13xx software example + * +* Description: +* CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * +**************************************************************************** +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* products. This software is supplied "AS IS" without any warranties. +* NXP Semiconductors assumes no responsibility or liability for the +* use of the software, conveys no license or title under any patent, +* copyright, or mask work right to the product. NXP Semiconductors +* reserves the right to make changes in the software without +* notification. NXP Semiconductors also make no representation or +* warranty that such application will be suitable for the specified +* use without further testing or modification. +****************************************************************************/ + + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup LPC13xx_Definitions LPC13xx Definitions + This file defines all structures and symbols for LPC13xx: + - Registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup LPC13xx_CMSIS LPC13xx CMSIS Definitions + Configuration of the Cortex-M3 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP0_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ + SSP1_IRQn = 57, /*!< SSP1 Interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC13xx_CMSIS */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup LPC13xx_SYSCON LPC13xx System Control Block + @{ +*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 (R/W) System memory remap Register */ + __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 (R/W) Peripheral reset control Register */ + __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 (R/W) System PLL control Register */ + __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C (R/ ) System PLL status Register */ + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 (R/W) System oscillator control Register */ + __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 (R/W) Watchdog oscillator control Register */ + __IO uint32_t IRCCTRL; /*!< Offset: 0x028 (R/W) IRC control Register */ + uint32_t RESERVED1[1]; + __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 (R/W) System reset status Register */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 (R/W) System PLL clock source select Register */ + __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 (R/W) System PLL clock source update enable Register */ + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 (R/W) Main clock source select Register */ + __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 (R/W) Main clock source update enable Register */ + __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 (R/W) System AHB clock divider Register */ + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 (R/W) System AHB clock control Register */ + uint32_t RESERVED5[4]; + __IO uint32_t SSP0CLKDIV; + __IO uint32_t UARTCLKDIV; + __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */ + uint32_t RESERVED6[3]; + + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 (R/W) WDT clock source select Register */ + __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 (R/W) WDT clock source update enable Register */ + __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 (R/W) WDT clock divider Register */ + uint32_t RESERVED9[1]; + + __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 (R/W) CLKOUT clock source select Register */ + __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 (R/W) CLKOUT clock source update enable Register */ + __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 (R/W) CLKOUT clock divider Register */ + uint32_t RESERVED10[5]; + + __I uint32_t PIOPORCAP0; /*!< Offset: 0x100 (R/ ) POR captured PIO status 0 Register */ + __I uint32_t PIOPORCAP1; /*!< Offset: 0x104 (R/ ) POR captured PIO status 1 Register */ + uint32_t RESERVED11[11]; + uint32_t RESERVED12[7]; + __IO uint32_t BODCTRL; /*!< Offset: 0x150 (R/W) BOD control Register */ + uint32_t RESERVED13[1]; + __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 (R/W) System tick counter calibration Register */ + uint32_t RESERVED14[41]; + + __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 (R/W) Start logic edge control Register 0 */ + __IO uint32_t STARTERP0; /*!< Offset: 0x204 (R/W) Start logic signal enable Register 0 */ + __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 ( /W) Start logic reset Register 0 */ + __I uint32_t STARTSRP0; /*!< Offset: 0x20C (R/ ) Start logic status Register 0 */ + __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 (R/W) Start logic edge control Register 1 (LPC11UXX only) */ + __IO uint32_t STARTERP1; /*!< Offset: 0x214 (R/W) Start logic signal enable Register 1 (LPC11UXX only) */ + __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 ( /W) Start logic reset Register 1 (LPC11UXX only) */ + __I uint32_t STARTSRP1; /*!< Offset: 0x21C (R/ ) Start logic status Register 1 (LPC11UXX only) */ + uint32_t RESERVED17[4]; + + __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 (R/W) Power-down states in Deep-sleep mode Register */ + __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 (R/W) Power-down states after wake-up from Deep-sleep mode Register*/ + __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 (R/W) Power-down configuration Register*/ + uint32_t RESERVED18[110]; + __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 (R/ ) Device ID Register */ +} LPC_SYSCON_TypeDef; +/*@}*/ /* end of group LPC13xx_SYSCON */ + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +/** @addtogroup LPC13xx_IOCON LPC13xx I/O Configuration Block + @{ +*/ +typedef struct +{ + __IO uint32_t PIO2_6; /*!< Offset: 0x000 (R/W) I/O configuration for pin PIO2_6 */ + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; /*!< Offset: 0x008 (R/W) I/O configuration for pin PIO2_0/DTR/SSEL1 */ + __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C (R/W) I/O configuration for pin RESET/PIO0_0 */ + __IO uint32_t PIO0_1; /*!< Offset: 0x010 (R/W) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 */ + __IO uint32_t PIO1_8; /*!< Offset: 0x014 (R/W) I/O configuration for pin PIO1_8/CT16B1_CAP0 */ + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; /*!< Offset: 0x01C (R/W) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ + + __IO uint32_t PIO2_7; /*!< Offset: 0x020 (R/W) I/O configuration for pin PIO2_7 */ + __IO uint32_t PIO2_8; /*!< Offset: 0x024 (R/W) I/O configuration for pin PIO2_8 */ + __IO uint32_t PIO2_1; /*!< Offset: 0x028 (R/W) I/O configuration for pin PIO2_1/nDSR/SCK1 */ + __IO uint32_t PIO0_3; /*!< Offset: 0x02C (R/W) I/O configuration for pin PIO0_3 */ + __IO uint32_t PIO0_4; /*!< Offset: 0x030 (R/W) I/O configuration for pin PIO0_4/SCL */ + __IO uint32_t PIO0_5; /*!< Offset: 0x034 (R/W) I/O configuration for pin PIO0_5/SDA */ + __IO uint32_t PIO1_9; /*!< Offset: 0x038 (R/W) I/O configuration for pin PIO1_9/CT16B1_MAT0 */ + __IO uint32_t PIO3_4; /*!< Offset: 0x03C (R/W) I/O configuration for pin PIO3_4 */ + + __IO uint32_t PIO2_4; /*!< Offset: 0x040 (R/W) I/O configuration for pin PIO2_4 */ + __IO uint32_t PIO2_5; /*!< Offset: 0x044 (R/W) I/O configuration for pin PIO2_5 */ + __IO uint32_t PIO3_5; /*!< Offset: 0x048 (R/W) I/O configuration for pin PIO3_5 */ + __IO uint32_t PIO0_6; /*!< Offset: 0x04C (R/W) I/O configuration for pin PIO0_6/SCK0 */ + __IO uint32_t PIO0_7; /*!< Offset: 0x050 (R/W) I/O configuration for pin PIO0_7/nCTS */ + __IO uint32_t PIO2_9; /*!< Offset: 0x054 (R/W) I/O configuration for pin PIO2_9 */ + __IO uint32_t PIO2_10; /*!< Offset: 0x058 (R/W) I/O configuration for pin PIO2_10 */ + __IO uint32_t PIO2_2; /*!< Offset: 0x05C (R/W) I/O configuration for pin PIO2_2/DCD/MISO1 */ + + __IO uint32_t PIO0_8; /*!< Offset: 0x060 (R/W) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ + __IO uint32_t PIO0_9; /*!< Offset: 0x064 (R/W) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ + __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 (R/W) I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 */ + __IO uint32_t PIO1_10; /*!< Offset: 0x06C (R/W) I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 */ + __IO uint32_t PIO2_11; /*!< Offset: 0x070 (R/W) I/O configuration for pin PIO2_11/SCK0 */ + __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 (R/W) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ + __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 (R/W) I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 */ + __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C (R/W) I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 */ + + __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 (R/W) I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 */ + __IO uint32_t PIO3_0; /*!< Offset: 0x084 (R/W) I/O configuration for pin PIO3_0/nDTR */ + __IO uint32_t PIO3_1; /*!< Offset: 0x088 (R/W) I/O configuration for pin PIO3_1/nDSR */ + __IO uint32_t PIO2_3; /*!< Offset: 0x08C (R/W) I/O configuration for pin PIO2_3/RI/MOSI1 */ + __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 (R/W) I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 */ + __IO uint32_t PIO1_4; /*!< Offset: 0x094 (R/W) I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 */ + __IO uint32_t PIO1_11; /*!< Offset: 0x098 (R/W) I/O configuration for pin PIO1_11/AD7 */ + __IO uint32_t PIO3_2; /*!< Offset: 0x09C (R/W) I/O configuration for pin PIO3_2/nDCD */ + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */ + __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */ + __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */ + __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */ +} LPC_IOCON_TypeDef; +/*@}*/ /* end of group LPC13xx_IOCON */ + + +/*------------- Power Management Unit (PMU) --------------------------*/ +/** @addtogroup LPC13xx_PMU LPC13xx Power Management Unit + @{ +*/ +typedef struct +{ + __IO uint32_t PCON; /*!< Offset: 0x000 (R/W) Power control Register */ + __IO uint32_t GPREG0; /*!< Offset: 0x004 (R/W) General purpose Register 0 */ + __IO uint32_t GPREG1; /*!< Offset: 0x008 (R/W) General purpose Register 1 */ + __IO uint32_t GPREG2; /*!< Offset: 0x00C (R/W) General purpose Register 2 */ + __IO uint32_t GPREG3; /*!< Offset: 0x010 (R/W) General purpose Register 3 */ + __IO uint32_t GPREG4; /*!< Offset: 0x014 (R/W) General purpose Register 4 */ +} LPC_PMU_TypeDef; +/*@}*/ /* end of group LPC13xx_PMU */ + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** @addtogroup LPC13xx_GPIO LPC13xx General Purpose Input/Output + @{ +*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */ + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; /*!< Offset: 0x3FFC (R/W) Port data Register */ + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; /*!< Offset: 0x8000 (R/W) Data direction Register */ + __IO uint32_t IS; /*!< Offset: 0x8004 (R/W) Interrupt sense Register */ + __IO uint32_t IBE; /*!< Offset: 0x8008 (R/W) Interrupt both edges Register */ + __IO uint32_t IEV; /*!< Offset: 0x800C (R/W) Interrupt event Register */ + __IO uint32_t IE; /*!< Offset: 0x8010 (R/W) Interrupt mask Register */ + __I uint32_t RIS; /*!< Offset: 0x8014 (R/ ) Raw interrupt status Register */ + __I uint32_t MIS; /*!< Offset: 0x8018 (R/ ) Masked interrupt status Register */ + __O uint32_t IC; /*!< Offset: 0x801C ( /W) Interrupt clear Register */ +} LPC_GPIO_TypeDef; +/*@}*/ /* end of group LPC13xx_GPIO */ + + +/*------------- Timer (TMR) --------------------------------------------------*/ +/** @addtogroup LPC13xx_TMR LPC13xx 16/32-bit Counter/Timer + @{ +*/ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */ + __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */ + __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */ + __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */ + __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ + __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */ + __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */ + __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */ + __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */ + __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */ + __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */ + __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ + uint32_t RESERVED1[3]; + __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */ + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */ + __IO uint32_t PWMC; /*!< Offset: 0x074 (R/W) PWM Control Register */ +} LPC_TMR_TypeDef; +/*@}*/ /* end of group LPC13xx_TMR */ + + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @addtogroup LPC13xx_UART LPC13xx Universal Asynchronous Receiver/Transmitter + @{ +*/ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 (R/ ) Receiver Buffer Register */ + __O uint32_t THR; /*!< Offset: 0x000 ( /W) Transmit Holding Register */ + __IO uint32_t DLL; /*!< Offset: 0x000 (R/W) Divisor Latch LSB */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 (R/W) Divisor Latch MSB */ + __IO uint32_t IER; /*!< Offset: 0x000 (R/W) Interrupt Enable Register */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 (R/ ) Interrupt ID Register */ + __O uint32_t FCR; /*!< Offset: 0x008 ( /W) FIFO Control Register */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C (R/W) Line Control Register */ + __IO uint32_t MCR; /*!< Offset: 0x010 (R/W) Modem control Register */ + __I uint32_t LSR; /*!< Offset: 0x014 (R/ ) Line Status Register */ + __I uint32_t MSR; /*!< Offset: 0x018 (R/ ) Modem status Register */ + __IO uint32_t SCR; /*!< Offset: 0x01C (R/W) Scratch Pad Register */ + __IO uint32_t ACR; /*!< Offset: 0x020 (R/W) Auto-baud Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t FDR; /*!< Offset: 0x028 (R/W) Fractional Divider Register */ + uint32_t RESERVED1[1]; + __IO uint32_t TER; /*!< Offset: 0x030 (R/W) Transmit Enable Register */ + uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< Offset: 0x04C (R/W) RS-485/EIA-485 Control Register */ + __IO uint32_t ADRMATCH; /*!< Offset: 0x050 (R/W) RS-485/EIA-485 address match Register */ + __IO uint32_t RS485DLY; /*!< Offset: 0x054 (R/W) RS-485/EIA-485 direction control delay Register */ + +} LPC_UART_TypeDef; +/*@}*/ /* end of group LPC13xx_UART */ + + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** @addtogroup LPC13xx_SSP LPC13xx Synchronous Serial Port + @{ +*/ +typedef struct +{ + __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */ + __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */ + __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */ + __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */ + __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< Offset: 0x018 (R/ ) Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< Offset: 0x01C (R/ ) Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< Offset: 0x020 ( /W) SSPICR Interrupt Clear Register */ +} LPC_SSP_TypeDef; +/*@}*/ /* end of group LPC13xx_SSP */ + + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @addtogroup LPC13xx_I2C LPC13xx I2C-Bus Interface + @{ +*/ +typedef struct +{ + __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */ + __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */ + __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */ + __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */ + __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */ + __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */ + __O uint32_t CONCLR; /*!< Offset: 0x018 ( /W) I2C Control Clear Register */ + __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */ + __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */ + __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */ + __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */ + __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */ + __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */ + __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */ + __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */ +} LPC_I2C_TypeDef; +/*@}*/ /* end of group LPC13xx_I2C */ + + +/*------------- Windowed Watchdog Timer (WWDT) -----------------------------------------*/ +/** @addtogroup LPC13xx_WWDT LPC13xx Windowed WatchDog Timer + @{ +*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; + uint32_t RESERVED0; + __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ + __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ +} LPC_WWDT_TypeDef; +/*@}*/ /* end of group LPC13xx_WWDT */ + + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** @addtogroup LPC13xx_ADC LPC13xx Analog-to-Digital Converter + @{ +*/ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */ + __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */ + uint32_t RESERVED0[1]; + __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */ + __IO uint32_t DR[8]; /*!< Offset: 0x010 (R/W) A/D Channel 0..7 Data Register */ + __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */ +} LPC_ADC_TypeDef; +/*@}*/ /* end of group LPC13xx_ADC */ + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +/** @addtogroup LPC13xx_USB LPC13xx Universal Serial Bus + @{ +*/ +typedef struct +{ + __I uint32_t DevIntSt; /*!< Offset: 0x000 (R/ ) USB Device Interrupt Status Register */ + __IO uint32_t DevIntEn; /*!< Offset: 0x004 (R/W) USB Device Interrupt Enable Register */ + __O uint32_t DevIntClr; /*!< Offset: 0x008 ( /W) USB Device Interrupt Clear Register */ + __O uint32_t DevIntSet; /*!< Offset: 0x00C ( /W) USB Device Interrupt Set Register */ + + __O uint32_t CmdCode; /*!< Offset: 0x010 ( /W) USB Command Code Register */ + __I uint32_t CmdData; /*!< Offset: 0x014 (R/ ) USB Command Data Register */ + + __I uint32_t RxData; /*!< Offset: 0x018 (R/ ) USB Receive Data Register */ + __O uint32_t TxData; /*!< Offset: 0x01C ( /W) USB Transmit Data Register */ + __I uint32_t RxPLen; /*!< Offset: 0x020 (R/ ) USB Receive Packet Length Register */ + __O uint32_t TxPLen; /*!< Offset: 0x024 ( /W) USB Transmit Packet Length Register */ + __IO uint32_t Ctrl; /*!< Offset: 0x028 (R/ ) USB Control Register */ + __O uint32_t DevFIQSel; /*!< Offset: 0x02C ( /W) USB Device FIQ select Register */ +} LPC_USB_TypeDef; +/*@}*/ /* end of group LPC13xx_USB */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC13xx_H__ */ diff --git a/os/hal/platforms/LPC13xx/gpt_lld.c b/os/hal/platforms/LPC13xx/gpt_lld.c new file mode 100644 index 000000000..66581dfc9 --- /dev/null +++ b/os/hal/platforms/LPC13xx/gpt_lld.c @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/gpt_lld.c + * @brief LPC13xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC13xx_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC13xx_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC13xx_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC13xx_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC13xx_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE4) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT16B0 */ + +#if LPC13xx_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE8) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT16B0 */ + +#if LPC13xx_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorEC) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT32B0 */ + +#if LPC13xx_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorF0) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC13xx_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_TMR16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC13xx_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_TMR16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC13xx_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_TMR32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC13xx_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_TMR32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC13xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC13xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC13xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC13xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC13xx_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC13xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC13xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC13xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC13xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC13xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/gpt_lld.h b/os/hal/platforms/LPC13xx/gpt_lld.h new file mode 100644 index 000000000..87c8475e9 --- /dev/null +++ b/os/hal/platforms/LPC13xx/gpt_lld.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/gpt_lld.h + * @brief LPC13xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC13xx_GPT_USE_CT16B0 && !LPC13xx_GPT_USE_CT16B1 && \ + !LPC13xx_GPT_USE_CT32B0 && !LPC13xx_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_TMR_TypeDef *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC13xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC13xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC13xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/hal_lld.c b/os/hal/platforms/LPC13xx/hal_lld.c new file mode 100644 index 000000000..561537537 --- /dev/null +++ b/os/hal/platforms/LPC13xx/hal_lld.c @@ -0,0 +1,120 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/hal_lld.c + * @brief LPC13xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Register missing in NXP header file. + */ +#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC13xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void LPC13xx_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/hal_lld.h b/os/hal/platforms/LPC13xx/hal_lld.h new file mode 100644 index 000000000..0fd17871c --- /dev/null +++ b/os/hal/platforms/LPC13xx/hal_lld.h @@ -0,0 +1,219 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC13xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC13xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLL_MUL 6 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC13xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC13xx_SYSOSCCTRL 0 +#else +#define LPC13xx_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC13xx_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1) +#else +#error "LPC13xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC13xx_SYSPLL_DIV == 4 +#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC13xx_SYSPLL_DIV == 8 +#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC13xx_SYSPLL_DIV == 16 +#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC13xx_SYSPLLCCO (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL * \ + LPC13xx_SYSPLL_DIV) + +#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC13xx_SYSPLLCLKOUT (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV) + +#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC13xx_MAINCLK IRCOSCCLK +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKIN +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC13xx_MAINCLK WDGOSCCLK +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKOUT +#else +#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC13xx_SYSCLK (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV) +#if LPC13xx_SYSCLK > 72000000 +#error "AHB clock frequency out of the acceptable range (72MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC13xx_FLASHCFG_FLASHTIM 0 +#elif LPC13xx_SYSCLK <= 40000000 +#define LPC13xx_FLASHCFG_FLASHTIM 1 +#else +#define LPC13xx_FLASHCFG_FLASHTIM 2 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void LPC13xx_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/pal_lld.c b/os/hal/platforms/LPC13xx/pal_lld.c new file mode 100644 index 000000000..42a446b44 --- /dev/null +++ b/os/hal/platforms/LPC13xx/pal_lld.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/pal_lld.c + * @brief LPC13xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC13xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC13xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO0->DIR = config->P0.dir; + LPC_GPIO1->DIR = config->P1.dir; + LPC_GPIO2->DIR = config->P2.dir; + LPC_GPIO3->DIR = config->P3.dir; + LPC_GPIO0->DATA = config->P0.data; + LPC_GPIO1->DATA = config->P1.data; + LPC_GPIO2->DATA = config->P2.data; + LPC_GPIO3->DATA = config->P3.data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/pal_lld.h b/os/hal/platforms/LPC13xx/pal_lld.h new file mode 100644 index 000000000..a8df95e12 --- /dev/null +++ b/os/hal/platforms/LPC13xx/pal_lld.h @@ -0,0 +1,316 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/pal_lld.h + * @brief LPC13xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc13xx_gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + lpc13xx_gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + lpc13xx_gpio_setup_t P1; + /** @brief GPIO 2 setup data.*/ + lpc13xx_gpio_setup_t P2; + /** @brief GPIO 3 setup data.*/ + lpc13xx_gpio_setup_t P3; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO0 +#define GPIO0 LPC_GPIO0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 LPC_GPIO1 +#define GPIO1 LPC_GPIO1 + +/** + * @brief GPIO2 port identifier. + */ +#define IOPORT3 LPC_GPIO2 +#define GPIO2 LPC_GPIO2 + +/** + * @brief GPIO3 port identifier. + */ +#define IOPORT4 LPC_GPIO3 +#define GPIO3 LPC_GPIO3 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DATA) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + ((port)->MASKED_ACCESS[(mask) << (offset)]) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->MASKED_ACCESS[1 << (pad)] = (bit) << (pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/platform.dox b/os/hal/platforms/LPC13xx/platform.dox new file mode 100644 index 000000000..bda4ceb5c --- /dev/null +++ b/os/hal/platforms/LPC13xx/platform.dox @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup LPC13xx LPC13xx Drivers + * @details This section describes all the supported drivers on the LPC13xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC13xx_HAL LPC13xx Initialization Support + * @details The LPC13xx HAL support is responsible for system initialization. + * + * @section lpc13xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc13xx_hal_2 LPC13xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_GPT LPC13xx GPT Support + * @details The LPC13xx GPT driver uses the CTxxBy peripherals. + * + * @section lpc13xx_gpt_1 Supported HW resources + * - CT16B0. + * - CT16B1. + * - CT32B0. + * - CT32B1. + * . + * @section lpc13xx_gpt_2 LPC13xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable CTxxBy interrupts priority level. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_PAL LPC13xx PAL Support + * @details The LPC13xx PAL driver uses the GPIO peripherals. + * + * @section lpc13xx_pal_1 Supported HW resources + * - GPIO0. + * - GPIO1. + * - GPIO2. + * - GPIO3. + * . + * @section lpc13xx_pal_2 LPC13xx PAL driver implementation features + * - 12 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc13xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc13xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * - Reading of the output latch for pads programmed as input is not possible, + * the input pin value is returned instead. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_SERIAL LPC13xx Serial Support + * @details The LPC13xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC13xx UARTs deep hardware buffers. + * + * @section lpc13xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc13xx_serial_2 LPC13xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_SPI LPC13xx SPI Support + * @details The SPI driver supports the LPC13xx SSP peripherals in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc13xx_spi_1 Supported HW resources + * - SSP0. + * - SSP1 (where present). + * . + * @section lpc13xx_spi_2 LPC13xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SSP can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each SSP. + * . + * @ingroup LPC13xx + */ diff --git a/os/hal/platforms/LPC13xx/platform.mk b/os/hal/platforms/LPC13xx/platform.mk new file mode 100644 index 000000000..1171af7d7 --- /dev/null +++ b/os/hal/platforms/LPC13xx/platform.mk @@ -0,0 +1,9 @@ +# List of all the LPC13xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC13xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/spi_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC13xx diff --git a/os/hal/platforms/LPC13xx/serial_lld.c b/os/hal/platforms/LPC13xx/serial_lld.c new file mode 100644 index 000000000..3b59238d5 --- /dev/null +++ b/os/hal/platforms/LPC13xx/serial_lld.c @@ -0,0 +1,298 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/serial_lld.c + * @brief LPC13xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_UART_TypeDef *u = sdp->uart; + + uint32_t div = LPC13xx_SERIAL_UART0_PCLK / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(LPC_UART_TypeDef *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC13xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC13xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(VectorF8) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC13xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_UART; + LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ + LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC13xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UARTCLKDIV = LPC13xx_SERIAL_UART0CLKDIV; + nvicEnableVector(UART_IRQn, + CORTEX_PRIORITY_MASK(LPC13xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC13xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UARTCLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/serial_lld.h b/os/hal/platforms/LPC13xx/serial_lld.h new file mode 100644 index 000000000..cbc00d3f8 --- /dev/null +++ b/os/hal/platforms/LPC13xx/serial_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/serial_lld.h + * @brief LPC13xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC13xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC13xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC13xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC13xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC13xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC13xx_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC13xx_SERIAL_FIFO_PRELOAD < 1) || (LPC13xx_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC13xx_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC13xx_SERIAL_UART0_PCLK \ + (LPC13xx_MAINCLK / LPC13xx_SERIAL_UART0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC13xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_UART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/spi_lld.c b/os/hal/platforms/LPC13xx/spi_lld.c new file mode 100644 index 000000000..3b8ad65b6 --- /dev/null +++ b/os/hal/platforms/LPC13xx/spi_lld.c @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/spi_lld.c + * @brief LPC13xx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC13xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC13xx_SSP_FIFO_DEPTH ? + LPC13xx_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC13xx_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorF4) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC13xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector124) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC13xx_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; + LPC_IOCON->SCK_LOC = LPC13xx_SPI_SCK0_SELECTOR; +#if LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10 + LPC_IOCON->SWCLK_PIO0_10 = 0xC2; /* SCK0 without resistors. */ +#elif LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11 + LPC_IOCON->PIO2_11 = 0xC1; /* SCK0 without resistors. */ +#else /* LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */ + LPC_IOCON->PIO0_6 = 0xC2; /* SCK0 without resistors. */ +#endif + LPC_IOCON->PIO0_8 = 0xC1; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0xC1; /* MOSI0 without resistors. */ +#endif /* LPC13xx_SPI_USE_SSP0 */ + +#if LPC13xx_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; + LPC_IOCON->PIO2_1 = 0xC2; /* SCK1 without resistors. */ + LPC_IOCON->PIO2_2 = 0xC2; /* MISO1 without resistors. */ + LPC_IOCON->PIO2_3 = 0xC2; /* MOSI1 without resistors. */ +#endif /* LPC13xx_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC13xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC13xx_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC13xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC13xx_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC13xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC13xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/spi_lld.h b/os/hal/platforms/LPC13xx/spi_lld.h new file mode 100644 index 000000000..9328cd69d --- /dev/null +++ b/os/hal/platforms/LPC13xx/spi_lld.h @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC13xx/spi_lld.h + * @brief LPC13xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC13xx_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/** + * @brief SCK0 signal assigned to pin PIO0_10. + */ +#define SCK0_IS_PIO0_10 0 + +/** + * @brief SCK0 signal assigned to pin PIO2_11. + */ +#define SCK0_IS_PIO2_11 1 + +/** + * @brief SCK0 signal assigned to pin PIO0_6. + */ +#define SCK0_IS_PIO0_6 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC13xx_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC13xx_SPI_USE_SSP1 FALSE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC13xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC13xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC13xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC13xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP1_IRQ_PRIORITY 5 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC13xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief SCK0 signal selector. + */ +#if !defined(LPC13xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC13xx_SPI_SSP0CLKDIV < 1) || (LPC13xx_SPI_SSP0CLKDIV > 255) +#error "invalid LPC13xx_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC13xx_SPI_SSP1CLKDIV < 1) || (LPC13xx_SPI_SSP1CLKDIV > 255) +#error "invalid LPC13xx_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC13xx_SPI_USE_SSP0 && !LPC13xx_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) && \ + (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) && \ + (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6) +#error "invalid pin assigned to SCK0 signal" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC13xx_SPI_SSP0_PCLK \ + (LPC13xx_MAINCLK / LPC13xx_SPI_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC13xx_SPI_SSP1_PCLK \ + (LPC13xx_MAINCLK / LPC13xx_SPI_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSP_TypeDef *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC13xx_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC13xx/system_LPC13xx.h b/os/hal/platforms/LPC13xx/system_LPC13xx.h new file mode 100644 index 000000000..812f12365 --- /dev/null +++ b/os/hal/platforms/LPC13xx/system_LPC13xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC13xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC13xx Device Series + * @version V1.10 + * @date 24. November 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC13xx_H +#define __SYSTEM_LPC13xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC13xx_H */ diff --git a/os/hal/platforms/LPC214x/hal_lld.c b/os/hal/platforms/LPC214x/hal_lld.c new file mode 100644 index 000000000..4f6784e29 --- /dev/null +++ b/os/hal/platforms/LPC214x/hal_lld.c @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/hal_lld.c + * @brief LPC214x HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/* + * Non-vectored IRQs handler, the default action can be overridden by + * redefining the @p LPC214x_NON_VECTORED_IRQ_HOOK() hook macro. + */ +static CH_IRQ_HANDLER(irq_handler) { + + CH_IRQ_PROLOGUE(); + + LPC214x_NON_VECTORED_IRQ_HOOK(); + + VICVectAddr = 0; + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + vic_init(); + VICDefVectAddr = (IOREG32)irq_handler; + +} + +/** + * @brief LPC214x clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc214x_clock_init(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLL0Base; + pll->PLL_CFG = 0x23; /* P and M values. */ + pll->PLL_CON = 0x1; /* Enables the PLL 0. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + while (!(pll->PLL_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL_CON = 0x3; /* Connects the PLL. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; +} + +/** @} */ diff --git a/os/hal/platforms/LPC214x/hal_lld.h b/os/hal/platforms/LPC214x/hal_lld.h new file mode 100644 index 000000000..d58977e33 --- /dev/null +++ b/os/hal/platforms/LPC214x/hal_lld.h @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/hal_lld.h + * @brief LPC214x HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "lpc214x.h" +#include "vic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC214x" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Default action for the non vectored IRQ handler, nothing. + */ +#if !defined(LPC214x_NON_VECTORED_IRQ_HOOK) || defined(__DOXYGEN__) +#define LPC214x_NON_VECTORED_IRQ_HOOK() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc214x_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/lpc214x.h b/os/hal/platforms/LPC214x/lpc214x.h new file mode 100644 index 000000000..4aa4dd96b --- /dev/null +++ b/os/hal/platforms/LPC214x/lpc214x.h @@ -0,0 +1,523 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lpc214x.h + * @brief LPC214x register definitions. + */ + +#ifndef _LPC214X_H_ +#define _LPC214X_H_ + +typedef volatile uint8_t IOREG8; +typedef volatile uint16_t IOREG16; +typedef volatile uint32_t IOREG32; + +/* + * System. + */ +#define MEMMAP (*((IOREG32 *)0xE01FC040)) +#define PCON (*((IOREG32 *)0xE01FC0C0)) +#define PCONP (*((IOREG32 *)0xE01FC0C4)) +#define VPBDIV (*((IOREG32 *)0xE01FC100)) +#define EXTINT (*((IOREG32 *)0xE01FC140)) +#define INTWAKE (*((IOREG32 *)0xE01FC144)) +#define EXTMODE (*((IOREG32 *)0xE01FC148)) +#define EXTPOLAR (*((IOREG32 *)0xE01FC14C)) +#define RSID (*((IOREG32 *)0xE01FC180)) +#define CSPR (*((IOREG32 *)0xE01FC184)) +#define SCS (*((IOREG32 *)0xE01FC1A0)) + +#define VPD_D4 0 +#define VPD_D1 1 +#define VPD_D2 2 +#define VPD_RESERVED 3 + +#define PCTIM0 (1 << 1) +#define PCTIM1 (1 << 2) +#define PCUART0 (1 << 3) +#define PCUART1 (1 << 4) +#define PCPWM0 (1 << 5) +#define PCI2C0 (1 << 7) +#define PCSPI0 (1 << 8) +#define PCRTC (1 << 9) +#define PCSPI1 (1 << 10) +#define PCAD0 (1 << 12) +#define PCI2C1 (1 << 19) +#define PCAD1 (1 << 20) +#define PCUSB (1 << 31) +#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \ + PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \ + PCAD0 | PCI2C1 | PCAD1 | PCUSB) + +#define EINT0 1 +#define EINT1 2 +#define EINT2 4 +#define EINT3 8 + +#define EXTWAKE0 1 +#define EXTWAKE1 2 +#define EXTWAKE2 4 +#define EXTWAKE3 8 +#define USBWAKE 0x20 +#define BODWAKE 0x4000 +#define RTCWAKE 0x8000 + +#define EXTMODE0 1 +#define EXTMODE1 2 +#define EXTMODE2 4 +#define EXTMODE3 8 + +#define EXTPOLAR0 1 +#define EXTPOLAR1 2 +#define EXTPOLAR2 4 +#define EXTPOLAR3 8 + +typedef struct { + IOREG32 PLL_CON; + IOREG32 PLL_CFG; + IOREG32 PLL_STAT; + IOREG32 PLL_FEED; +} PLL; + +#define PLL0Base ((PLL *)0xE01FC080) +#define PLL1Base ((PLL *)0xE01FC0A0) +#define PLL0CON (PLL0Base->PLL_CON) +#define PLL0CFG (PLL0Base->PLL_CFG) +#define PLL0STAT (PLL0Base->PLL_STAT) +#define PLL0FEED (PLL0Base->PLL_FEED) +#define PLL1CON (PLL1Base->PLL_CON) +#define PLL1CFG (PLL1Base->PLL_CFG) +#define PLL1STAT (PLL1Base->PLL_STAT) +#define PLL1FEED (PLL1Base->PLL_FEED) + +/* + * Pins. + */ +typedef struct { + IOREG32 PS_SEL0; + IOREG32 PS_SEL1; + IOREG32 _dummy[3]; + IOREG32 PS_SEL2; +} PS; + +#define PSBase ((PS *)0xE002C000) +#define PINSEL0 (PSBase->PS_SEL0) +#define PINSEL1 (PSBase->PS_SEL1) +#define PINSEL2 (PSBase->PS_SEL2) + +/* + * VIC + */ +#define SOURCE_WDT 0 +#define SOURCE_ARMCore0 2 +#define SOURCE_ARMCore1 3 +#define SOURCE_Timer0 4 +#define SOURCE_Timer1 5 +#define SOURCE_UART0 6 +#define SOURCE_UART1 7 +#define SOURCE_PWM0 8 +#define SOURCE_I2C0 9 +#define SOURCE_SPI0 10 +#define SOURCE_SPI1 11 +#define SOURCE_PLL 12 +#define SOURCE_RTC 13 +#define SOURCE_EINT0 14 +#define SOURCE_EINT1 15 +#define SOURCE_EINT2 16 +#define SOURCE_EINT3 17 +#define SOURCE_ADC0 18 +#define SOURCE_I2C1 19 +#define SOURCE_BOD 20 +#define SOURCE_ADC1 21 +#define SOURCE_USB 22 + +#define INTMASK(n) (1 << (n)) +#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \ + INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \ + INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \ + INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \ + INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \ + INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \ + INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \ + INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \ + INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \ + INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \ + INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB)) + +typedef struct { + IOREG32 VIC_IRQStatus; + IOREG32 VIC_FIQStatus; + IOREG32 VIC_RawIntr; + IOREG32 VIC_IntSelect; + IOREG32 VIC_IntEnable; + IOREG32 VIC_IntEnClear; + IOREG32 VIC_SoftInt; + IOREG32 VIC_SoftIntClear; + IOREG32 VIC_Protection; + IOREG32 unused1[3]; + IOREG32 VIC_VectAddr; + IOREG32 VIC_DefVectAddr; + IOREG32 unused2[50]; + IOREG32 VIC_VectAddrs[16]; + IOREG32 unused3[48]; + IOREG32 VIC_VectCntls[16]; +} VIC; + +#define VICBase ((VIC *)0xFFFFF000) +#define VICVectorsBase ((IOREG32 *)0xFFFFF100) +#define VICControlsBase ((IOREG32 *)0xFFFFF200) + +#define VICIRQStatus (VICBase->VIC_IRQStatus) +#define VICFIQStatus (VICBase->VIC_FIQStatus) +#define VICRawIntr (VICBase->VIC_RawIntr) +#define VICIntSelect (VICBase->VIC_IntSelect) +#define VICIntEnable (VICBase->VIC_IntEnable) +#define VICIntEnClear (VICBase->VIC_IntEnClear) +#define VICSoftInt (VICBase->VIC_SoftInt) +#define VICSoftIntClear (VICBase->VIC_SoftIntClear) +#define VICProtection (VICBase->VIC_Protection) +#define VICVectAddr (VICBase->VIC_VectAddr) +#define VICDefVectAddr (VICBase->VIC_DefVectAddr) + +#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n]) +#define VICVectCntls(n) (VICBase->VIC_VectCntls[n]) + +/* + * MAM. + */ +typedef struct { + IOREG32 MAM_Control; + IOREG32 MAM_Timing; +} MAM; + +#define MAMBase ((MAM *)0xE01FC000) +#define MAMCR (MAMBase->MAM_Control) +#define MAMTIM (MAMBase->MAM_Timing) + +/* + * GPIO - FIO. + */ +typedef struct { + IOREG32 IO_PIN; + IOREG32 IO_SET; + IOREG32 IO_DIR; + IOREG32 IO_CLR; +} GPIO; + +#define GPIO0Base ((GPIO *)0xE0028000) +#define IO0PIN (GPIO0Base->IO_PIN) +#define IO0SET (GPIO0Base->IO_SET) +#define IO0DIR (GPIO0Base->IO_DIR) +#define IO0CLR (GPIO0Base->IO_CLR) + +#define GPIO1Base ((GPIO *)0xE0028010) +#define IO1PIN (GPIO1Base->IO_PIN) +#define IO1SET (GPIO1Base->IO_SET) +#define IO1DIR (GPIO1Base->IO_DIR) +#define IO1CLR (GPIO1Base->IO_CLR) + +typedef struct { + IOREG32 FIO_DIR; + IOREG32 unused1; + IOREG32 unused2; + IOREG32 unused3; + IOREG32 FIO_MASK; + IOREG32 FIO_PIN; + IOREG32 FIO_SET; + IOREG32 FIO_CLR; +} FIO; + +#define FIO0Base ((FIO *)0x3FFFC000) +#define FIO0DIR (FIO0Base->FIO_DIR) +#define FIO0MASK (FIO0Base->FIO_MASK) +#define FIO0PIN (FIO0Base->FIO_PIN) +#define FIO0SET (FIO0Base->FIO_SET) +#define FIO0CLR (FIO0Base->FIO_CLR) + +#define FIO1Base ((FIO *)0x3FFFC020) +#define FIO1DIR (FIO1Base->FIO_DIR) +#define FIO1MASK (FIO1Base->FIO_MASK) +#define FIO1PIN (FIO1Base->FIO_PIN) +#define FIO1SET (FIO1Base->FIO_SET) +#define FIO1CLR (FIO1Base->FIO_CLR) + +/* + * UART. + */ +typedef struct { + union { + IOREG32 UART_RBR; + IOREG32 UART_THR; + IOREG32 UART_DLL; + }; + union { + IOREG32 UART_IER; + IOREG32 UART_DLM; + }; + union { + IOREG32 UART_IIR; + IOREG32 UART_FCR; + }; + IOREG32 UART_LCR; + IOREG32 UART_MCR; + IOREG32 UART_LSR; + IOREG32 unused18; + IOREG32 UART_SCR; + IOREG32 UART_ACR; + IOREG32 unused24; + IOREG32 UART_FDR; + IOREG32 unused2C; + IOREG32 UART_TER; +} UART; + +#define U0Base ((UART *)0xE000C000) +#define U0RBR (U0Base->UART_RBR) +#define U0THR (U0Base->UART_THR) +#define U0DLL (U0Base->UART_DLL) +#define U0IER (U0Base->UART_IER) +#define U0DLM (U0Base->UART_DLM) +#define U0IIR (U0Base->UART_IIR) +#define U0FCR (U0Base->UART_FCR) +#define U0LCR (U0Base->UART_LCR) +#define U0LSR (U0Base->UART_LSR) +#define U0SCR (U0Base->UART_SCR) +#define U0ACR (U0Base->UART_ACR) +#define U0FDR (U0Base->UART_FDR) +#define U0TER (U0Base->UART_TER) + +#define U1Base ((UART *)0xE0010000) +#define U1RBR (U1Base->UART_RBR) +#define U1THR (U1Base->UART_THR) +#define U1DLL (U1Base->UART_DLL) +#define U1IER (U1Base->UART_IER) +#define U1DLM (U1Base->UART_DLM) +#define U1IIR (U1Base->UART_IIR) +#define U1FCR (U1Base->UART_FCR) +#define U1MCR (U1Base->UART_MCR) +#define U1LCR (U1Base->UART_LCR) +#define U1LSR (U1Base->UART_LSR) +#define U1SCR (U1Base->UART_SCR) +#define U1ACR (U1Base->UART_ACR) +#define U1FDR (U1Base->UART_FDR) +#define U1TER (U1Base->UART_TER) + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define IIR_INT_PENDING 1 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/* + * SSP. + */ +typedef struct { + IOREG32 SSP_CR0; + IOREG32 SSP_CR1; + IOREG32 SSP_DR; + IOREG32 SSP_SR; + IOREG32 SSP_CPSR; + IOREG32 SSP_IMSC; + IOREG32 SSP_RIS; + IOREG32 SSP_MIS; + IOREG32 SSP_ICR; +} SSP; + +#define SSPBase ((SSP *)0xE0068000) +#define SSPCR0 (SSPBase->SSP_CR0) +#define SSPCR1 (SSPBase->SSP_CR1) +#define SSPDR (SSPBase->SSP_DR) +#define SSPSR (SSPBase->SSP_SR) +#define SSPCPSR (SSPBase->SSP_CPSR) +#define SSPIMSC (SSPBase->SSP_IMSC) +#define SSPRIS (SSPBase->SSP_RIS) +#define SSPMIS (SSPBase->SSP_MIS) +#define SSPICR (SSPBase->SSP_ICR) + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 0x10 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/* + * Timers/Counters. + */ +typedef struct { + IOREG32 TC_IR; + IOREG32 TC_TCR; + IOREG32 TC_TC; + IOREG32 TC_PR; + IOREG32 TC_PC; + IOREG32 TC_MCR; + IOREG32 TC_MR0; + IOREG32 TC_MR1; + IOREG32 TC_MR2; + IOREG32 TC_MR3; + IOREG32 TC_CCR; + IOREG32 TC_CR0; + IOREG32 TC_CR1; + IOREG32 TC_CR2; + IOREG32 TC_CR3; + IOREG32 TC_EMR; + IOREG32 TC_CTCR; +} TC; + +#define T0Base ((TC *)0xE0004000) +#define T0IR (T0Base->TC_IR) +#define T0TCR (T0Base->TC_TCR) +#define T0TC (T0Base->TC_TC) +#define T0PR (T0Base->TC_PR) +#define T0PC (T0Base->TC_PC) +#define T0MCR (T0Base->TC_MCR) +#define T0MR0 (T0Base->TC_MR0) +#define T0MR1 (T0Base->TC_MR1) +#define T0MR2 (T0Base->TC_MR2) +#define T0MR3 (T0Base->TC_MR3) +#define T0CCR (T0Base->TC_CCR) +#define T0CR0 (T0Base->TC_CR0) +#define T0CR1 (T0Base->TC_CR1) +#define T0CR2 (T0Base->TC_CR2) +#define T0CR3 (T0Base->TC_CR3) +#define T0EMR (T0Base->TC_EMR) +#define T0CTCR (T0Base->TC_CTCR) + +#define T1Base ((TC *)0xE0008000) +#define T1IR (T1Base->TC_IR) +#define T1TCR (T1Base->TC_TCR) +#define T1TC (T1Base->TC_TC) +#define T1PR (T1Base->TC_PR) +#define T1PC (T1Base->TC_PC) +#define T1MCR (T1Base->TC_MCR) +#define T1MR0 (T1Base->TC_MR0) +#define T1MR1 (T1Base->TC_MR1) +#define T1MR2 (T1Base->TC_MR2) +#define T1MR3 (T1Base->TC_MR3) +#define T1CCR (T1Base->TC_CCR) +#define T1CR0 (T1Base->TC_CR0) +#define T1CR1 (T1Base->TC_CR1) +#define T1CR2 (T1Base->TC_CR2) +#define T1CR3 (T1Base->TC_CR3) +#define T1EMR (T1Base->TC_EMR) +#define T1CTCR (T1Base->TC_CTCR) + +/* + * Watchdog. + */ +typedef struct { + IOREG32 WD_MOD; + IOREG32 WD_TC; + IOREG32 WD_FEED; + IOREG32 WD_TV; +} WD; + +#define WDBase ((WD *)0xE0000000) +#define WDMOD (WDBase->WD_MOD) +#define WDTC (WDBase->WD_TC) +#define WDFEED (WDBase->WD_FEED) +#define WDTV (WDBase->WD_TV) + +/* + * DAC. + */ +#define DACR (*((IOREG32 *)0xE006C000)) + +#endif /* _LPC214X_H_ */ + diff --git a/os/hal/platforms/LPC214x/pal_lld.c b/os/hal/platforms/LPC214x/pal_lld.c new file mode 100644 index 000000000..1d0b45ad4 --- /dev/null +++ b/os/hal/platforms/LPC214x/pal_lld.c @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/pal_lld.c + * @brief LPC214x FIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief LPC214x I/O ports configuration. + * @details FIO units and PINSEL registers initialization. + * + * @param[in] config the LPC214x ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* Enables the access through the fast registers.*/ + SCS = 3; + + /* I/O pads initial assignment, device drivers may change this setup at a + * later time.*/ + PINSEL0 = config->pinsel0; + PINSEL1 = config->pinsel1; + PINSEL2 = config->pinsel2; + + /* I/O pads direction initial setting.*/ + FIO0Base->FIO_MASK = 0; + FIO0Base->FIO_PIN = config->P0Data.pin; + FIO0Base->FIO_DIR = config->P0Data.dir; + FIO1Base->FIO_MASK = 0; + FIO1Base->FIO_PIN = config->P1Data.pin; + FIO1Base->FIO_DIR = config->P1Data.dir; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->FIO_DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->FIO_PIN |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->FIO_DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/pal_lld.h b/os/hal/platforms/LPC214x/pal_lld.h new file mode 100644 index 000000000..6ffcabdf5 --- /dev/null +++ b/os/hal/platforms/LPC214x/pal_lld.h @@ -0,0 +1,261 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/pal_lld.h + * @brief LPC214x FIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief FIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t pin; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc214x_fio_setup_t; + +/** + * @brief LPC214x FIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief PINSEL0 initial value.*/ + uint32_t pinsel0; + /** @brief PINSEL1 initial value.*/ + uint32_t pinsel1; + /** @brief PINSEL2 initial value.*/ + uint32_t pinsel2; + /** @brief Port 0 setup data.*/ + lpc214x_fio_setup_t P0Data; + /** @brief Port 1 setup data.*/ + lpc214x_fio_setup_t P1Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef FIO * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief FIO port 0 identifier. + */ +#define IOPORT1 FIO0Base + +/** + * @brief FIO port 1 identifier. + */ +#define IOPORT2 FIO1Base + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief FIO subsystem initialization. + * @details Enables the access through the fast registers. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the FIO PIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->FIO_PIN) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the FIO SET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->FIO_SET) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the FIO PIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->FIO_PIN = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the FIO SET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->FIO_SET = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the FIO CLR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->FIO_CLR = (bits)) + +/** + * @brief Writes a value on an I/O bus. + * @details This function is implemented by writing the FIO PIN and MASK + * registers, the implementation is not atomic because the multiple + * accesses. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the + * output data + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->FIO_MASK = ~((mask) << (offset)), \ + (port)->FIO_PIN = (bits) << (offset), \ + (port)->FIO_MASK = 0) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +/** + * @brief FIO port setup. + * @details This function programs the pins direction within a port. + * + * @notapi + */ +#define pal_lld_lpc214x_set_direction(port, dir) ((port)->FIO_DIR = (dir)) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/platform.dox b/os/hal/platforms/LPC214x/platform.dox new file mode 100644 index 000000000..e5189558a --- /dev/null +++ b/os/hal/platforms/LPC214x/platform.dox @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup LPC214x LPC214x Drivers + * @details This section describes all the supported drivers on the LPC214x + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC214x_HAL LPC214x Initialization Support + * @details The LPC214x HAL support is responsible for system initialization. + * + * @section lpc214x_hal_1 Supported HW resources + * - PLL0. + * - MAM. + * - VPBDIV. + * . + * @section lpc214x_hal_2 LPC214x HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - MAM initialization. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_PAL LPC214x PAL Support + * @details The LPC214x PAL driver uses the FIO peripherals. + * + * @section lpc214x_pal_1 Supported HW resources + * - FIO0. + * - FIO1. + * . + * @section lpc214x_pal_2 LPC214x PAL driver implementation features + * - 32 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc214x_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc214x_pal_4 Suboptimal behavior + * Some FIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_SERIAL LPC214x Serial Support + * @details The LPC214x Serial driver uses the UART peripherals in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC214x UARTs deep hardware buffers. + * + * @section lpc214x_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART0. + * - UART1. + * . + * @section lpc214x_serial_2 LPC214x Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each UART. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_SPI LPC214x SPI Support + * @details The SPI driver supports the LPC214x SSP peripheral in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc214x_spi_1 Supported HW resources + * - SSP (SPI0). + * . + * @section lpc214x_spi_2 LPC214x SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority level. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_VIC LPC214x VIC Support + * @details This VIC helper driver is used by the other drivers in order to + * access the shared VIC resources in a consistent way. + * + * @ingroup LPC214x + */ diff --git a/os/hal/platforms/LPC214x/platform.mk b/os/hal/platforms/LPC214x/platform.mk new file mode 100644 index 000000000..0253e47f7 --- /dev/null +++ b/os/hal/platforms/LPC214x/platform.mk @@ -0,0 +1,9 @@ +# List of all the LPC214x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC214x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/vic.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC214x diff --git a/os/hal/platforms/LPC214x/serial_lld.c b/os/hal/platforms/LPC214x/serial_lld.c new file mode 100644 index 000000000..f552b094d --- /dev/null +++ b/os/hal/platforms/LPC214x/serial_lld.c @@ -0,0 +1,347 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/serial_lld.c + * @brief LPC214x low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +/** @brief UART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + UART *u = sdp->uart; + + uint32_t div = PCLK / (config->sc_speed << 4); + u->UART_LCR = config->sc_lcr | LCR_DLAB; + u->UART_DLL = div; + u->UART_DLM = div >> 8; + u->UART_LCR = config->sc_lcr; + u->UART_FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->UART_ACR = 0; + u->UART_FDR = 0x10; + u->UART_TER = TER_ENABLE; + u->UART_IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(UART *u) { + + u->UART_LCR = LCR_DLAB; + u->UART_DLL = 1; + u->UART_DLM = 0; + u->UART_LCR = 0; + u->UART_FDR = 0x10; + u->UART_IER = 0; + u->UART_FCR = FCR_RXRESET | FCR_TXRESET; + u->UART_ACR = 0; + u->UART_TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we dont want + * to go through the whole ISR and have another interrupt soon after. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + UART *u = sdp->uart; + + while (TRUE) { + switch (u->UART_IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->UART_LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->UART_LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->UART_RBR) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC214x_UART_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->UART_IER &= ~IER_THRE; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->UART_THR = b; + } while (--i); + } + break; + default: + (void) u->UART_THR; + (void) u->UART_RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + UART *u = sdp->uart; + + if (u->UART_LSR & LSR_THRE) { + int i = LPC214x_UART_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->UART_THR = b; + } while (--i); + } + u->UART_IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/** + * @brief Driver SD2 output notification. + */ +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + preload(&SD2); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(UART0IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART1 IRQ handler. + * + * @isr + */ +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(UART1IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_LPC214x_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = U0Base; + SetVICVector(UART0IrqHandler, LPC214x_UART0_PRIORITY, SOURCE_UART0); +#endif +#if USE_LPC214x_UART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = U1Base; + SetVICVector(UART1IrqHandler, LPC214x_UART1_PRIORITY, SOURCE_UART1); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if USE_LPC214x_UART0 + if (&SD1 == sdp) { + PCONP = (PCONP & PCALL) | PCUART0; + VICIntEnable = INTMASK(SOURCE_UART0); + } +#endif +#if USE_LPC214x_UART1 + if (&SD2 == sdp) { + PCONP = (PCONP & PCALL) | PCUART1; + VICIntEnable = INTMASK(SOURCE_UART1); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if USE_LPC214x_UART0 + if (&SD1 == sdp) { + PCONP = (PCONP & PCALL) & ~PCUART0; + VICIntEnClear = INTMASK(SOURCE_UART0); + return; + } +#endif +#if USE_LPC214x_UART1 + if (&SD2 == sdp) { + PCONP = (PCONP & PCALL) & ~PCUART1; + VICIntEnClear = INTMASK(SOURCE_UART1); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/serial_lld.h b/os/hal/platforms/LPC214x/serial_lld.h new file mode 100644 index 000000000..b57957580 --- /dev/null +++ b/os/hal/platforms/LPC214x/serial_lld.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/serial_lld.h + * @brief LPC214x low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(USE_LPC214x_UART0) || defined(__DOXYGEN__) +#define USE_LPC214x_UART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_LPC214x_UART1) || defined(__DOXYGEN__) +#define USE_LPC214x_UART1 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC214x_UART_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC214x_UART_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC214x_UART0_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_UART0_PRIORITY 1 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(LPC214x_UART1_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_UART1_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC214x_UART_FIFO_PRELOAD < 1) || (LPC214x_UART_FIFO_PRELOAD > 16) +#error "invalid LPC214x_UART_FIFO_PRELOAD setting" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC214x Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + UART *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_LPC214x_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_LPC214x_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/spi_lld.c b/os/hal/platforms/LPC214x/spi_lld.c new file mode 100644 index 000000000..b5e7f864f --- /dev/null +++ b/os/hal/platforms/LPC214x/spi_lld.c @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/spi_lld.c + * @brief LPC214x low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + SSP *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC214x_SSP_FIFO_DEPTH ? + LPC214x_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SSP_SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT) + ssp->SSP_DR = *(uint16_t *)spip->txptr++; + else + ssp->SSP_DR = *(uint8_t *)spip->txptr++; + } + else + ssp->SSP_DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void serve_interrupt(SPIDriver *spip) { + SSP *ssp = spip->ssp; + + if ((ssp->SSP_MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC214x_SPI_SSP_ERROR_HOOK(); + } + ssp->SSP_ICR = ICR_RT | ICR_ROR; + while ((ssp->SSP_SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT) + *(uint16_t *)spip->rxptr++ = ssp->SSP_DR; + else + *(uint8_t *)spip->rxptr++ = ssp->SSP_DR; + } + else + (void)ssp->SSP_DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->SSP_IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__) +/** + * @brief SPI1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI1IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SPID1); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC214x_SPI_USE_SSP + spiObjectInit(&SPID1); + SPID1.ssp = SSPBase; + SetVICVector(SPI1IrqHandler, LPC214x_SPI_SSP_IRQ_PRIORITY, SOURCE_SPI1); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC214x_SPI_USE_SSP + if (&SPID1 == spip) { + PCONP = (PCONP & PCALL) | PCSPI1; + VICIntEnable = INTMASK(SOURCE_SPI1); + } +#endif + } + /* Configuration.*/ + spip->ssp->SSP_CR1 = 0; + /* Emptying the receive FIFO, it happens to not be empty while debugging.*/ + while (spip->ssp->SSP_SR & SR_RNE) + (void) spip->ssp->SSP_DR; + spip->ssp->SSP_ICR = ICR_RT | ICR_ROR; + spip->ssp->SSP_CR0 = spip->config->cr0; + spip->ssp->SSP_CPSR = spip->config->cpsr; + spip->ssp->SSP_CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->SSP_CR1 = 0; + spip->ssp->SSP_CR0 = 0; + spip->ssp->SSP_CPSR = 0; +#if LPC214x_SPI_USE_SSP + if (&SPID1 == spip) { + PCONP = (PCONP & PCALL) & ~PCSPI1; + VICIntEnClear = INTMASK(SOURCE_SPI1); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->SSP_DR = (uint32_t)frame; + while ((spip->ssp->SSP_SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->SSP_DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/spi_lld.h b/os/hal/platforms/LPC214x/spi_lld.h new file mode 100644 index 000000000..9def6f16a --- /dev/null +++ b/os/hal/platforms/LPC214x/spi_lld.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/spi_lld.h + * @brief LPC214x low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC214x_SSP_FIFO_DEPTH 8 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SSP is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC214x_SPI_USE_SSP) || defined(__DOXYGEN__) +#define LPC214x_SPI_USE_SSP TRUE +#endif + +/** + * @brief SSP interrupt priority level setting. + */ +#if !defined(LPC214x_SPI_SSP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_SPI_SSP_IRQ_PRIORITY 4 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC214x_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC214x_SPI_SSP_ERROR_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC214x_SPI_USE_SSP +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + SSP *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC214x/vic.c b/os/hal/platforms/LPC214x/vic.c new file mode 100644 index 000000000..8c64f44ce --- /dev/null +++ b/os/hal/platforms/LPC214x/vic.c @@ -0,0 +1,65 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/vic.c + * @brief LPC214x VIC peripheral support code. + * + * @addtogroup LPC214x_VIC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief VIC Initialization. + * @note Better reset everything in the VIC, it is a HUGE source of trouble. + * + * @notapi + */ +void vic_init(void) { + int i; + + VIC *vic = VICBase; + vic->VIC_IntSelect = 0; /* All sources assigned to IRQ. */ + vic->VIC_SoftIntClear = ALLINTMASK; /* No interrupts enforced */ + vic->VIC_IntEnClear = ALLINTMASK; /* All sources disabled. */ + for (i = 0; i < 16; i++) { + vic->VIC_VectCntls[i] = 0; + vic->VIC_VectAddrs[i] = 0; + vic->VIC_VectAddr = 0; + } +} + +/** + * @brief Initializes a VIC vector. + * @details Set a vector for an interrupt source and enables it. + * + * @param[in] handler the pointer to the IRQ service routine + * @param[in] vector the vector number + * @param[in] source the IRQ source to be associated to the vector + * + * @api + */ +void SetVICVector(void *handler, int vector, int source) { + + VIC *vicp = VICBase; + vicp->VIC_VectAddrs[vector] = (IOREG32)handler; + vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); +} + +/** @} */ diff --git a/os/hal/platforms/LPC214x/vic.h b/os/hal/platforms/LPC214x/vic.h new file mode 100644 index 000000000..99c97b936 --- /dev/null +++ b/os/hal/platforms/LPC214x/vic.h @@ -0,0 +1,39 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC214x/vic.h + * @brief LPC214x VIC peripheral support header. + * + * @addtogroup LPC214x_VIC + * @{ + */ + +#ifndef _VIC_H_ +#define _VIC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + void vic_init(void); + void SetVICVector(void *handler, int vector, int source); +#ifdef __cplusplus +} +#endif + +#endif /* _VIC_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/LPC8xx.h b/os/hal/platforms/LPC8xx/LPC8xx.h new file mode 100644 index 000000000..41fe7da21 --- /dev/null +++ b/os/hal/platforms/LPC8xx/LPC8xx.h @@ -0,0 +1,686 @@ +/**************************************************************************** + * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ + * Project: NXP LPC8xx software example + * + * Description: + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for + * NXP LPC800 Device Series + * + **************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' + * relevant copyright in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. +****************************************************************************/ +#ifndef __LPC8xx_H__ +#define __LPC8xx_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup LPC8xx_Definitions LPC8xx Definitions + This file defines all structures and symbols for LPC8xx: + - Registers and bitfields + - peripheral base address + - PIO definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions + Configuration of the Cortex-M0+ Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** LPC8xx Specific Interrupt Numbers ********************************************************/ + SPI0_IRQn = 0, /*!< SPI0 */ + SPI1_IRQn = 1, /*!< SPI1 */ + Reserved0_IRQn = 2, /*!< Reserved Interrupt */ + UART0_IRQn = 3, /*!< USART0 */ + UART1_IRQn = 4, /*!< USART1 */ + UART2_IRQn = 5, /*!< USART2 */ + Reserved1_IRQn = 6, /*!< Reserved Interrupt */ + Reserved2_IRQn = 7, /*!< Reserved Interrupt */ + I2C_IRQn = 8, /*!< I2C */ + SCT_IRQn = 9, /*!< SCT */ + MRT_IRQn = 10, /*!< MRT */ + CMP_IRQn = 11, /*!< CMP */ + WDT_IRQn = 12, /*!< WDT */ + BOD_IRQn = 13, /*!< BOD */ + Reserved3_IRQn = 14, /*!< Reserved Interrupt */ + WKT_IRQn = 15, /*!< WKT Interrupt */ + Reserved4_IRQn = 16, /*!< Reserved Interrupt */ + Reserved5_IRQn = 17, /*!< Reserved Interrupt */ + Reserved6_IRQn = 18, /*!< Reserved Interrupt */ + Reserved7_IRQn = 19, /*!< Reserved Interrupt */ + Reserved8_IRQn = 20, /*!< Reserved Interrupt */ + Reserved9_IRQn = 21, /*!< Reserved Interrupt */ + Reserved10_IRQn = 22, /*!< Reserved Interrupt */ + Reserved11_IRQn = 23, /*!< Reserved Interrupt */ + PININT0_IRQn = 24, /*!< External Interrupt 0 */ + PININT1_IRQn = 25, /*!< External Interrupt 1 */ + PININT2_IRQn = 26, /*!< External Interrupt 2 */ + PININT3_IRQn = 27, /*!< External Interrupt 3 */ + PININT4_IRQn = 28, /*!< External Interrupt 4 */ + PININT5_IRQn = 29, /*!< External Interrupt 5 */ + PININT6_IRQn = 30, /*!< External Interrupt 6 */ + PININT7_IRQn = 31, /*!< External Interrupt 7 */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC8xx_CMSIS */ + + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_LPC8xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block + @{ +*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ + __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ + __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ + __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ + uint32_t RESERVED0[4]; + + __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ + __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ + uint32_t RESERVED1[2]; + __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ + __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ + uint32_t RESERVED3[10]; + + __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ + __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ + __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ + uint32_t RESERVED5[4]; + __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ + uint32_t RESERVED6[18]; + + __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ + __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ + __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ + uint32_t RESERVED7; + __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ + __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ + uint32_t RESERVED8[1]; + __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ + __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ + uint32_t RESERVED9[12]; + __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ + __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ + __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ + uint32_t RESERVED10[6]; + __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ + __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ + __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ + uint32_t RESERVED11[27]; + __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ + uint32_t RESERVED12[3]; + __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ + uint32_t RESERVED13[6]; + __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ + __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ + __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ + uint32_t RESERVED14[110]; + __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ +} LPC_SYSCON_TypeDef; +/*@}*/ /* end of group LPC8xx_SYSCON */ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) + */ + +typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ + __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ + __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ + __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ + __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ + __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ + __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ + __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ + __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ + __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ + __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ + __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ + __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ + __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ + __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ + __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ + __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ + __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ + __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ + __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ +} LPC_IOCON_TypeDef; +/*@}*/ /* end of group LPC8xx_IOCON */ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) + */ +typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ + __I uint32_t RESERVED0[4]; + __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ + __I uint32_t RESERVED1[3]; + __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ + __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ + __I uint32_t RESERVED2; + __I uint32_t FMSW0; +} LPC_FLASHCTRL_TypeDef; +/*@}*/ /* end of group LPC8xx_FLASHCTRL */ + + +/*------------- Power Management Unit (PMU) --------------------------*/ +/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit + @{ +*/ +typedef struct +{ + __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ + __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ + __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ + __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ + __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ + __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ +} LPC_PMU_TypeDef; +/*@}*/ /* end of group LPC8xx_PMU */ + + +/*------------- Switch Matrix Port --------------------------*/ +/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port + @{ +*/ +typedef struct +{ + union { + __IO uint32_t PINASSIGN[9]; + struct { + __IO uint32_t PINASSIGN0; + __IO uint32_t PINASSIGN1; + __IO uint32_t PINASSIGN2; + __IO uint32_t PINASSIGN3; + __IO uint32_t PINASSIGN4; + __IO uint32_t PINASSIGN5; + __IO uint32_t PINASSIGN6; + __IO uint32_t PINASSIGN7; + __IO uint32_t PINASSIGN8; + }; + }; + __I uint32_t RESERVED0[103]; + __IO uint32_t PINENABLE0; +} LPC_SWM_TypeDef; +/*@}*/ /* end of group LPC8xx_SWM */ + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PORT ----- +// ------------------------------------------------------------------------------------------------ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) + */ + +typedef struct { + __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ + __I uint16_t RESERVED0[2039]; + __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ + uint32_t RESERVED1[1006]; + __IO uint32_t DIR0; /* 0x2000 */ + uint32_t RESERVED2[31]; + __IO uint32_t MASK0; /* 0x2080 */ + uint32_t RESERVED3[31]; + __IO uint32_t PIN0; /* 0x2100 */ + uint32_t RESERVED4[31]; + __IO uint32_t MPIN0; /* 0x2180 */ + uint32_t RESERVED5[31]; + __IO uint32_t SET0; /* 0x2200 */ + uint32_t RESERVED6[31]; + __O uint32_t CLR0; /* 0x2280 */ + uint32_t RESERVED7[31]; + __O uint32_t NOT0; /* 0x2300 */ + +} LPC_GPIO_PORT_TypeDef; + + +// ------------------------------------------------------------------------------------------------ +// ----- PIN_INT ----- +// ------------------------------------------------------------------------------------------------ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) + */ + +typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ + __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ + __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ + __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ + __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ +} LPC_PIN_INT_TypeDef; + + +/*------------- CRC Engine (CRC) -----------------------------------------*/ +/** @addtogroup LPC8xx_CRC + @{ +*/ +typedef struct +{ + __IO uint32_t MODE; + __IO uint32_t SEED; + union { + __I uint32_t SUM; + __O uint32_t WR_DATA_DWORD; + __O uint16_t WR_DATA_WORD; + uint16_t RESERVED_WORD; + __O uint8_t WR_DATA_BYTE; + uint8_t RESERVED_BYTE[3]; + }; +} LPC_CRC_TypeDef; +/*@}*/ /* end of group LPC8xx_CRC */ + +/*------------- Comparator (CMP) --------------------------------------------------*/ +/** @addtogroup LPC8xx_CMP LPC8xx Comparator + @{ +*/ +typedef struct { /*!< (@ 0x40024000) CMP Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ + __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ +} LPC_CMP_TypeDef; +/*@}*/ /* end of group LPC8xx_CMP */ + + +/*------------- Wakeup Timer (WKT) --------------------------------------------------*/ +/** @addtogroup LPC8xx_WKT + @{ +*/ +typedef struct { /*!< (@ 0x40028000) WKT Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ + uint32_t Reserved[2]; + __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ +} LPC_WKT_TypeDef; +/*@}*/ /* end of group LPC8xx_WKT */ + + +/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ +typedef struct { +__IO uint32_t INTVAL; +__IO uint32_t TIMER; +__IO uint32_t CTRL; +__IO uint32_t STAT; +} MRT_Channel_cfg_Type; + +typedef struct { + MRT_Channel_cfg_Type Channel[4]; + uint32_t Reserved0[1]; + __IO uint32_t IDLE_CH; + __IO uint32_t IRQ_FLAG; +} LPC_MRT_TypeDef; + + +/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ +/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter + @{ +*/ +/** + * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) + */ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t CTRL; + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; /* 0x10 */ + __I uint32_t RXDATA; + __I uint32_t RXDATA_STAT; + __IO uint32_t TXDATA; + __IO uint32_t BRG; /* 0x20 */ + __IO uint32_t INTSTAT; +} LPC_USART_TypeDef; + +/*@}*/ /* end of group LPC8xx_USART */ + + +/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ +/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port + @{ +*/ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t DLY; + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; /* 0x10 */ + __I uint32_t RXDAT; + __IO uint32_t TXDATCTL; + __IO uint32_t TXDAT; + __IO uint32_t TXCTRL; /* 0x20 */ + __IO uint32_t DIV; + __I uint32_t INTSTAT; +} LPC_SPI_TypeDef; +/*@}*/ /* end of group LPC8xx_SPI */ + + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @addtogroup LPC8xx_I2C I2C-Bus Interface + @{ +*/ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; + __IO uint32_t TIMEOUT; /* 0x10 */ + __IO uint32_t DIV; + __IO uint32_t INTSTAT; + uint32_t Reserved0[1]; + __IO uint32_t MSTCTL; /* 0x20 */ + __IO uint32_t MSTTIME; + __IO uint32_t MSTDAT; + uint32_t Reserved1[5]; + __IO uint32_t SLVCTL; /* 0x40 */ + __IO uint32_t SLVDAT; + __IO uint32_t SLVADR0; + __IO uint32_t SLVADR1; + __IO uint32_t SLVADR2; /* 0x50 */ + __IO uint32_t SLVADR3; + __IO uint32_t SLVQUAL0; + uint32_t Reserved2[9]; + __I uint32_t MONRXDAT; /* 0x80 */ +} LPC_I2C_TypeDef; + +/*@}*/ /* end of group LPC8xx_I2C */ + +/** + * @brief State Configurable Timer (SCT) (SCT) + */ + +/** + * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) + */ + +#define CONFIG_SCT_nEV (6) /* Number of events */ +#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ +#define CONFIG_SCT_nOU (4) /* Number of outputs */ + +typedef struct +{ + __IO uint32_t CONFIG; /* 0x000 Configuration Register */ + union { + __IO uint32_t CTRL_U; /* 0x004 Control Register */ + struct { + __IO uint16_t CTRL_L; /* 0x004 low control register */ + __IO uint16_t CTRL_H; /* 0x006 high control register */ + }; + }; + __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ + __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ + __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ + __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ + __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ + __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ + __IO uint16_t START_L; /* 0x014 start register for counter L */ + __IO uint16_t START_H; /* 0x016 start register for counter H */ + uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ + union { + __IO uint32_t COUNT_U; /* 0x040 counter register */ + struct { + __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ + __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ + }; + }; + __IO uint16_t STATE_L; /* 0x044 state register for counter L */ + __IO uint16_t STATE_H; /* 0x046 state register for counter H */ + __I uint32_t INPUT; /* 0x048 input register */ + __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ + __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ + __IO uint32_t OUTPUT; /* 0x050 output register */ + __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ + __IO uint32_t RES; /* 0x058 conflict resolution register */ + uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ + __IO uint32_t EVEN; /* 0x0F0 event enable register */ + __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ + __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ + __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ + + union { + __IO union { /* 0x100-... Match / Capture value */ + uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCH[i].L Access to L value */ + uint16_t H; /* SCTMATCH[i].H Access to H value */ + }; + } MATCH[CONFIG_SCT_nRG]; + __I union { + uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAP[i].L Access to H value */ + uint16_t H; /* SCTCAP[i].H Access to H value */ + }; + } CAP[CONFIG_SCT_nRG]; + }; + + + uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ + + union { + __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ + __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ + }; + uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ + union { + __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ + __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ + }; + + uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ + + + union { + __IO union { /* 0x200-... Match Reload / Capture Control value */ + uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCHREL[i].L Access to L value */ + uint16_t H; /* SCTMATCHREL[i].H Access to H value */ + }; + } MATCHREL[CONFIG_SCT_nRG]; + __IO union { + uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ + uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ + }; + } CAPCTRL[CONFIG_SCT_nRG]; + }; + + uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ + + union { + __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ + __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ + }; + uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ + union { + __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ + __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ + }; + uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ + + __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ + uint32_t STATE; /* Event State Register */ + uint32_t CTRL; /* Event Control Register */ + } EVENT[CONFIG_SCT_nEV]; + + uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ + + __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ + uint32_t SET; /* Output n Set Register */ + uint32_t CLR; /* Output n Clear Register */ + } OUT[CONFIG_SCT_nOU]; + + uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ + + __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ + +} LPC_SCT_TypeDef; +/*@}*/ /* end of group LPC8xx_SCT */ + + +/*------------- Watchdog Timer (WWDT) -----------------------------------------*/ +/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer + @{ +*/ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ + __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ + __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ + uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ + __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ + __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ +} LPC_WWDT_TypeDef; +/*@}*/ /* end of group LPC8xx_WDT */ + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_ROM_BASE (0x1FFF0000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) + +#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) +#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) +#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) +#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) +#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) +#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) + +/* AHB peripherals */ +#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) + +#define LPC_GPIO_PORT_BASE (0xA0000000) +#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) +#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) + + +#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) +#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) + +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) +#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) +#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) +#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) +#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) + +#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) +#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) + +#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) +#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC8xx_H__ */ diff --git a/os/hal/platforms/LPC8xx/ext_lld.c b/os/hal/platforms/LPC8xx/ext_lld.c new file mode 100644 index 000000000..81e09c717 --- /dev/null +++ b/os/hal/platforms/LPC8xx/ext_lld.c @@ -0,0 +1,168 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/ext_lld.c + * @brief LPC8xx EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + int i; + + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) + ext_lld_channel_enable(extp, i); + else + ext_lld_channel_disable(extp, i); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + int i; + + if (extp->state == EXT_ACTIVE) + for (i = 0; i < EXT_MAX_CHANNELS; i++) + ext_lld_exti_irq_disable(i); + + LPC_PIN_INT->ISEL = 0; + LPC_PIN_INT->CIENR = EXT_CHANNELS_MASK; + LPC_PIN_INT->RISE = EXT_CHANNELS_MASK; + LPC_PIN_INT->FALL = EXT_CHANNELS_MASK; + LPC_PIN_INT->IST = EXT_CHANNELS_MASK; + + /* Leave clock enabled, its shared with GPIO */ + /*LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<6);*/ +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + /* program the IOpin for this channel */ + LPC_SYSCON->PINTSEL[channel] = extp->config->channels[channel].iopin; + + /* Programming edge irq enables */ + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + LPC_PIN_INT->SIENR = (1 << channel); + else + LPC_PIN_INT->CIENR = (1 << channel); + + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + LPC_PIN_INT->SIENF = (1 << channel); + else + LPC_PIN_INT->CIENF = (1 << channel); + + LPC_PIN_INT->RISE = (1<FALL = (1<IST = (1<ISEL &= ~(1 << channel); + LPC_PIN_INT->CIENR = (1 << channel); + LPC_PIN_INT->RISE = (1 << channel); + LPC_PIN_INT->FALL = (1 << channel); + LPC_PIN_INT->IST = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/ext_lld.h b/os/hal/platforms/LPC8xx/ext_lld.h new file mode 100644 index 000000000..af0f36b50 --- /dev/null +++ b/os/hal/platforms/LPC8xx/ext_lld.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/ext_lld.h + * @brief LPC8xx EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 8 + +/** + * @brief Mask of the available channels. + */ +#define EXT_CHANNELS_MASK ((1 << EXT_MAX_CHANNELS) - 1) + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + + * @brief EXT channel callback reason. + */ +typedef uint32_t expreason_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, + expchannel_t channel, + expreason_t reason); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint8_t mode; + /** + * @brief IO Pin. + */ + uint8_t iopin; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/ext_lld_isr.c b/os/hal/platforms/LPC8xx/ext_lld_isr.c new file mode 100644 index 000000000..312d61f9f --- /dev/null +++ b/os/hal/platforms/LPC8xx/ext_lld_isr.c @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/ext_lld_isr.c + * @brief LPC8xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +static void ext_lld_interrupt( uint32_t n ) { + uint32_t reason; + + reason = ((LPC_PIN_INT->RISE)>> n ) & 0x01; + reason |= ((LPC_PIN_INT->FALL)>>(n-1)) & 0x02; + LPC_PIN_INT->RISE = (1<FALL = (1<IST = (1<channels[n].cb(&EXTD1, n, reason); +} + +/** + * @brief EXT[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorA0) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(0); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorA4) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(1); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorA8) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(2); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorAC) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(3); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB0) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(4); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[5] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB4) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(5); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[6] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorB8) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(6); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXT[7] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorBC) { + + CH_IRQ_PROLOGUE(); + ext_lld_interrupt(7); + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +static const uint8_t LPC8xx_EXT_EXTIn_IRQ_PRIORITY[] = + { LPC8xx_EXT_EXTI0_IRQ_PRIORITY, + LPC8xx_EXT_EXTI1_IRQ_PRIORITY, + LPC8xx_EXT_EXTI2_IRQ_PRIORITY, + LPC8xx_EXT_EXTI3_IRQ_PRIORITY, + LPC8xx_EXT_EXTI4_IRQ_PRIORITY, + LPC8xx_EXT_EXTI5_IRQ_PRIORITY, + LPC8xx_EXT_EXTI6_IRQ_PRIORITY, + LPC8xx_EXT_EXTI7_IRQ_PRIORITY }; + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable( uint32_t exti_n ) { + + nvicEnableVector(PININT0_IRQn + exti_n, + CORTEX_PRIORITY_MASK(LPC8xx_EXT_EXTIn_IRQ_PRIORITY[exti_n])); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable( uint32_t exti_n ) { + + nvicDisableVector(PININT0_IRQn + exti_n); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/ext_lld_isr.h b/os/hal/platforms/LPC8xx/ext_lld_isr.h new file mode 100644 index 000000000..c2aa52655 --- /dev/null +++ b/os/hal/platforms/LPC8xx/ext_lld_isr.h @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/ext_lld_isr.h + * @brief LPC8xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI0_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI2_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI3_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI4_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI5 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI5_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI6 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI6_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI7 interrupt priority level setting. + */ +#if !defined(LPC8xx_EXT_EXTI7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_EXT_EXTI7_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable( uint32_t exti_n ); + void ext_lld_exti_irq_disable( uint32_t exti_n ); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/gpt_lld.c b/os/hal/platforms/LPC8xx/gpt_lld.c new file mode 100644 index 000000000..44601272b --- /dev/null +++ b/os/hal/platforms/LPC8xx/gpt_lld.c @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/gpt_lld.c + * @brief LPC8xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates MRT channel0 when enabled. + */ +#if LPC8xx_GPT_USE_MRT0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT1 allocates MRT channel1 when enabled. + */ +#if LPC8xx_GPT_USE_MRT1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT1 allocates MRT channel2 when enabled. + */ +#if LPC8xx_GPT_USE_MRT2 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT1 allocates MRT channel3 when enabled. + */ +#if LPC8xx_GPT_USE_MRT3 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ +static uint32_t clk_enabled; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] irq_flag irq flag bit + */ + +static void gpt_lld_serve_interrupt( GPTDriver *gptp ) { + + if (gptp->tmr->STAT & 0x01) { + gptp->tmr->STAT |= 0x01; + + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + } + gptp->config->callback(gptp); + } + return; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + + * @brief MRT IRQ handler. + * + */ +CH_IRQ_HANDLER(Vector68) { + CH_IRQ_PROLOGUE(); + +#if LPC8xx_GPT_USE_MRT0 + gpt_lld_serve_interrupt( &GPTD1 ); +#endif + +#if LPC8xx_GPT_USE_MRT1 + gpt_lld_serve_interrupt( &GPTD2 ); +#endif + +#if LPC8xx_GPT_USE_MRT2 + gpt_lld_serve_interrupt( &GPTD3 ); +#endif + +#if LPC8xx_GPT_USE_MRT3 + gpt_lld_serve_interrupt( &GPTD4 ); +#endif + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC8xx_GPT_USE_MRT0 + GPTD1.tmr = &(LPC_MRT->Channel[0]); + gptObjectInit(&GPTD1); + GPTD1.mask = (1<<0); +#endif + +#if LPC8xx_GPT_USE_MRT1 + GPTD2.tmr = &(LPC_MRT->Channel[1]); + gptObjectInit(&GPTD2); + GPTD1.mask = (1<<1); +#endif + +#if LPC8xx_GPT_USE_MRT2 + GPTD3.tmr = &(LPC_MRT->Channel[2]); + gptObjectInit(&GPTD3); + GPTD1.mask = (1<<2); +#endif + +#if LPC8xx_GPT_USE_MRT3 + GPTD4.tmr = &(LPC_MRT->Channel[3]); + gptObjectInit(&GPTD4); + GPTD1.mask = (1<<3); +#endif + + clk_enabled = FALSE; + return; +} + +/** + * @brief Configures and activates a GPT channel. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + + if( !clk_enabled ) { + + /* Enable clock & reset MRT */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); + LPC_SYSCON->PRESETCTRL &= ~(1<<7); + LPC_SYSCON->PRESETCTRL |= (1<<7); + + nvicEnableVector(MRT_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_GPT_MRT_IRQ_PRIORITY)); + + clk_enabled |= gptp->mask; + } + + /* Prescaler value calculation.*/ + gptp->pr = (LPC8xx_SYSCLK / gptp->config->frequency); + chDbgAssert((gptp->pr * gptp->config->frequency) == LPC8xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* MRT Channel configuration.*/ + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; + +} + +/** + * @brief Deactivates a GPT channel. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + /* Shared peripheral - + mark this channel as disabled */ + clk_enabled &= ~gptp->mask; + + /* All channels disabled? */ + if( !clk_enabled ) + { + /* Disable periheral */ + nvicDisableVector(MRT_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<10); + } + + return; +} + +/** + * @brief Starts the timer in continuous/One shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1); + + if (gptp->state == GPT_ONESHOT) + gptp->tmr->CTRL = (1<<1)|1; + else + gptp->tmr->CTRL = 1; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->INTVAL = (1<<31); + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1); + gptp->tmr->CTRL = (1<<1); + + while (gptp->tmr->STAT & (1<<1)) + ; + + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/gpt_lld.h b/os/hal/platforms/LPC8xx/gpt_lld.h new file mode 100644 index 000000000..73f080f66 --- /dev/null +++ b/os/hal/platforms/LPC8xx/gpt_lld.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/gpt_lld.h + * @brief LPC8xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC8xx_GPT_USE_MRT0) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT1) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT1 FALSE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT2) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT2 FALSE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT3) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT3 FALSE +#endif + +/** + * @brief GPT interrupt priority level setting. + */ +#if !defined(LPC8xx_GPT_MRT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_GPT_MRT_IRQ_PRIORITY 2 +#endif + + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC8xx_GPT_USE_MRT0 && !LPC8xx_GPT_USE_MRT1 && \ + !LPC8xx_GPT_USE_MRT2 && !LPC8xx_GPT_USE_MRT3 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the MRT Channelx registers block. + */ + MRT_Channel_cfg_Type *tmr; + /** + * @brief Prescaler. + */ + uint32_t pr; + /** + * @brief channel bitmask. + */ + uint32_t mask; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->tmr->INTVAL = ((interval*(gptp)->pr) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC8xx_GPT_USE_MRT0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC8xx_GPT_USE_MRT1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC8xx_GPT_USE_MRT2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC8xx_GPT_USE_MRT3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/hal_lld.c b/os/hal/platforms/LPC8xx/hal_lld.c new file mode 100644 index 000000000..e5170fcc4 --- /dev/null +++ b/os/hal/platforms/LPC8xx/hal_lld.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/hal_lld.c + * @brief LPC8xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC8xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC8xx clocks and PLL initialization. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc8xx_clock_init(void) { + int i; + + /* Enable clocks to IOCON & SWM. */ + LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7)); + + /* System oscillator initialization.*/ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) + // switch off pull-ups + LPC_IOCON->PIO0_8 &= ~(3<<3); + LPC_IOCON->PIO0_9 &= ~(3<<3); + + // enable xtalin/xtalout + LPC_SWM->PINENABLE0 &= ~(3<<4); + + LPC_SYSCON->SYSOSCCTRL = LPC8xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1<<5); /* System oscillator ON. */ + for (i = 0; i<200; i++) + __NOP(); /* Stabilization delay. */ +#endif + + /* CLKIN initialization.*/ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN) + // switch off pull-up + LPC_IOCON->PIO0_1 &= ~(3<<3); + + // enable clkin + LPC_SWM->PINENABLE0 &= ~(1<<7); +#endif + + /* Always set PLL clock source - + PLL IN can be a main clock source */ + LPC_SYSCON->SYSPLLCLKSEL = LPC8xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ + + /* PLL initialization.*/ +#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT + LPC_SYSCON->SYSPLLCTRL = LPC8xx_SYSPLLCTRL_MSEL | LPC8xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1<<7); /* System PLL ON. */ + while (!(LPC_SYSCON->SYSPLLSTAT & 1)) /* Wait PLL lock. */ + ; +#endif + +#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#error "WatchDog Oscillator not configured! Dont use as main clock source" + LPC_SYSCON->WDTOSCCTRL = ??; + LPC_SYSCON->PDRUNCFG &= ~(1<<6); /* WDT OSC On */ + for (i = 0; i<200; i++) + __NOP(); /* Stabilization delay. */ +#endif + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~1) | + LPC8xx_FLASHCFG_FLASHTIM; + + /* ABH divider initialization. Set this **before** switching Main clock + source to ensure AHB clock stays in spec */ + LPC_SYSCON->SYSAHBCLKDIV = LPC8xx_SYSABHCLK_DIV; + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC8xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; + while (!(LPC_SYSCON->MAINCLKUEN & 1)); /* Wait switch completion. */ + + /* Disable clocks to IOCON, SWM, FLASHREG & ROM. */ + LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7)|(1<<3)|(1<<1)); + +} + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/hal_lld.h b/os/hal/platforms/LPC8xx/hal_lld.h new file mode 100644 index 000000000..4f9c06dd2 --- /dev/null +++ b/os/hal/platforms/LPC8xx/hal_lld.h @@ -0,0 +1,221 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC8xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC8xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK ??????? /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ +#define SYSPLLCLKSEL_CLKIN 3 /**< External CLKIN clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC8xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC8xx_PLLCLK_SOURCE SYSPLLCLKSEL_IRCOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC8xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLL_MUL 4 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC8xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC8xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC8xx_SYSABHCLK_DIV) || defined(__DOXYGEN__) +#define LPC8xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC8xx_SYSOSCCTRL 0 +#else +#define LPC8xx_SYSOSCCTRL 2 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC8xx_SYSPLLCLKIN IRCOSCCLK +#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN +#define LPC8xx_SYSPLLCLKIN CLKINCLK +#else +#error "invalid LPC8xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC8xx_SYSPLL_MUL >= 1) && (LPC8xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCTRL_MSEL (LPC8xx_SYSPLL_MUL - 1) +#else +#error "LPC8xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC8xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC8xx_SYSPLL_DIV == 4 +#define LPC8xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC8xx_SYSPLL_DIV == 8 +#define LPC8xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC8xx_SYSPLL_DIV == 16 +#define LPC8xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC8xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCO frequency. + */ +#define LPC8xx_SYSPLLCCO (LPC8xx_SYSPLLCLKIN * LPC8xx_SYSPLL_MUL * \ + LPC8xx_SYSPLL_DIV) + +#if (LPC8xx_SYSPLLCCO < 156000000) || (LPC8xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320MHz)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC8xx_SYSPLLCLKOUT (LPC8xx_SYSPLLCCO / LPC8xx_SYSPLL_DIV) + +#if (LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC8xx_MAINCLK IRCOSCCLK +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC8xx_MAINCLK LPC8xx_SYSPLLCLKIN +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC8xx_MAINCLK WDGOSCCLK +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC8xx_MAINCLK LPC8xx_SYSPLLCLKOUT +#else +#error "invalid LPC8xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC8xx_SYSCLK (LPC8xx_MAINCLK / LPC8xx_SYSABHCLK_DIV) +#if LPC8xx_SYSCLK > 30000000 +#error "AHB clock frequency out of the acceptable range (30MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC8xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC8xx_FLASHCFG_FLASHTIM 0 +#else +#define LPC8xx_FLASHCFG_FLASHTIM 1 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc8xx_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/pal_lld.c b/os/hal/platforms/LPC8xx/pal_lld.c new file mode 100644 index 000000000..7f290db8f --- /dev/null +++ b/os/hal/platforms/LPC8xx/pal_lld.c @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/pal_lld.c + * @brief LPC8xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC8xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC8xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* Enable clocks to GPIO */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); + + LPC_GPIO_PORT->DIR0 = config->dir; + LPC_GPIO_PORT->PIN0 = config->data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) + { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR0 &= ~mask; + break; + + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + //no break + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR0 |= mask; + break; + } + + return; +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/pal_lld.h b/os/hal/platforms/LPC8xx/pal_lld.h new file mode 100644 index 000000000..f90932fa2 --- /dev/null +++ b/os/hal/platforms/LPC8xx/pal_lld.h @@ -0,0 +1,290 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/pal_lld.h + * @brief LPC8xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} PALConfig; + +/** + * @brief Width, in bits, of the I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0x3FFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_PORT_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO_PORT +#define GPIO0 LPC_GPIO_PORT + + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->PIN0) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->SET0) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->PIN0 = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->SET0 = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->CLR0 = (bits)) + + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @api + */ +#define pal_lld_toggleport(port, bits) ((port)->NOT0 = (bits)) + + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + (port)->MASK0 = (~(mask) << (offset)); \ + (port)->MPIN0 = ((bits) << (offset)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->W0[(pad)] = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->W0[(pad)] = 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->W0[(pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/platform.dox b/os/hal/platforms/LPC8xx/platform.dox new file mode 100644 index 000000000..85b60bcad --- /dev/null +++ b/os/hal/platforms/LPC8xx/platform.dox @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup LPC8xx LPC8xx Drivers + * @details This section describes all the supported drivers on the LPC8xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC8xx_HAL LPC8xx Initialization Support + * @details The LPC8xx HAL support is responsible for system initialization. + * + * @section lpc8xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc8xx_hal_2 LPC8xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_GPT LPC8xx GPT Support + * @details The LPC8xx GPT driver uses the MRT peripheral. + * + * @section lpc8xx_gpt_1 Supported HW resources + * - MRT. + * . + * @section lpc8xx_gpt_2 LPC8xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. + * - Programmable MRT interrupt priority level. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_PAL LPC8xx PAL Support + * @details The LPC8xx PAL driver uses the GPIO peripheral. + * + * @section lpc8xx_pal_1 Supported HW resources + * - GPIO_PORT. + * . + * @section lpc8xx_pal_2 LPC8xx PAL driver implementation features + * - 18 bits wide ports. + * - Atomic set/reset functions. + * - Atomic Toggle functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc8xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc8xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Group operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_SERIAL LPC8xx Serial Support + * @details The LPC8xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. + * + * @section lpc8xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc8xx_serial_2 LPC8xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * . + * @ingroup LPC8xx + */ + diff --git a/os/hal/platforms/LPC8xx/platform.mk b/os/hal/platforms/LPC8xx/platform.mk new file mode 100644 index 000000000..31f20d16c --- /dev/null +++ b/os/hal/platforms/LPC8xx/platform.mk @@ -0,0 +1,11 @@ +# List of all the LPC8xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC8xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/ext_lld_isr.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC8xx diff --git a/os/hal/platforms/LPC8xx/serial_lld.c b/os/hal/platforms/LPC8xx/serial_lld.c new file mode 100644 index 000000000..e9b53dc72 --- /dev/null +++ b/os/hal/platforms/LPC8xx/serial_lld.c @@ -0,0 +1,352 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/serial_lld.c + * @brief LPC8xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** @brief UART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** @brief UART2 serial driver identifier.*/ +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + (CFG_DL8 | CFG_NOPARITY | CFG_STOP1) +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART STAT register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & STAT_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & STAT_PARITYERR) + sts |= SD_PARITY_ERROR; + if (err & STAT_FRAMERR) + sts |= SD_FRAMING_ERROR; + if (err & STAT_RXBRK) + sts |= SD_BREAK_DETECTED; + + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_USART_TypeDef *u = sdp->uart; + + while (u->INTSTAT) { + + if (u->INTSTAT & STAT_RXRDY) { + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + if (chIQPutI(&sdp->iqueue, u->RXDATA) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + + if (u->INTSTAT & STAT_TXRDY) { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + + if (b < Q_OK) { + u->INTENCLR = STAT_TXRDY; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + else { + u->TXDATA = b; + } + } + + if (u->INTSTAT & (STAT_OVERRUN | STAT_DELTARXBRK | + STAT_FRAMERR | STAT_PARITYERR) ) { + IOREG32 stat = u->STAT; + set_error(sdp, stat); + u->STAT = stat; + } + + } +} + +/** + * @brief Attempts a TX preload. + */ +static void preload(SerialDriver *sdp) { + LPC_USART_TypeDef *u = sdp->uart; + + if (u->STAT & STAT_TXIDLE) { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->TXDATA = b; + } + u->INTENSET = STAT_TXRDY; +} + +/** + * @brief Driver output notification. + */ +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + preload(&SD2); +} +#endif + +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + preload(&SD3); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UARTn IRQ handlers. + * + * @isr + */ +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector4C) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD1 ); + CH_IRQ_EPILOGUE(); +} +#endif +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector50) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD2 ); + CH_IRQ_EPILOGUE(); +} +#endif +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector54) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD3 ); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC8xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_USART0; +#endif + +#if LPC8xx_SERIAL_USE_UART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = LPC_USART1; +#endif + +#if LPC8xx_SERIAL_USE_UART2 + sdObjectInit(&SD3, NULL, notify3); + SD3.uart = LPC_USART2; +#endif + + /* Reset fractional baudrate generator */ + LPC_SYSCON->PRESETCTRL &= ~(1<<2); + LPC_SYSCON->PRESETCTRL |= (1<<2); + + LPC_SYSCON->UARTCLKDIV = LPC8xx_SERIAL_UARTCLKDIV; + LPC_SYSCON->UARTFRGDIV = LPC8xx_SERIAL_UARTFRGDIV; + LPC_SYSCON->UARTFRGMULT = LPC8xx_SERIAL_UARTFRGMULT; + +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start( SerialDriver *sdp, const SerialConfig *config ) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { + +#if LPC8xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<14); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<3); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<3); + nvicEnableVector(UART0_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + +#if LPC8xx_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<4); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<4); + nvicEnableVector(UART1_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART1_IRQ_PRIORITY)); + } +#endif + +#if LPC8xx_SERIAL_USE_UART2 + if (&SD3 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<5); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<5); + nvicEnableVector(UART2_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART2_IRQ_PRIORITY)); + } +#endif + + } + + sdp->uart->BRG = (LPC8xx_SERIAL_U_PCLK / (config->sc_speed << 4)) -1; + sdp->uart->INTENSET = STAT_FRAMERR | STAT_OVERRUN | + STAT_PARITYERR | STAT_DELTARXBRK | + STAT_RXRDY; + sdp->uart->CFG = config->sc_cfg | CFG_ENA; +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop( SerialDriver *sdp ) { + + if (sdp->state == SD_READY) { + sdp->uart->INTENCLR = STAT_TXRDY | STAT_RXRDY; + sdp->uart->CFG = 0; + +#if LPC8xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12); + nvicDisableVector(UART0_IRQn); + return; + } +#endif + +#if LPC8xx_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<13); + nvicDisableVector(UART1_IRQn); + return; + } +#endif + +#if LPC8xx_SERIAL_USE_UART2 + if (&SD3 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<14); + nvicDisableVector(UART2_IRQn); + return; + } +#endif + + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/serial_lld.h b/os/hal/platforms/LPC8xx/serial_lld.h new file mode 100644 index 000000000..915c4e27e --- /dev/null +++ b/os/hal/platforms/LPC8xx/serial_lld.h @@ -0,0 +1,269 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/serial_lld.h + * @brief LPC8xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define CFG_ENA 0x0001 +#define CFG_DL7 0x0000 +#define CFG_DL8 0x0004 +#define CFG_DL9 0x0008 +#define CFG_NOPARITY 0x0000 +#define CFG_PARITYEVEN 0x0020 +#define CFG_PARITYODD 0x0030 +#define CFG_STOP1 0x0000 +#define CFG_STOP2 0x0040 +#define CFG_CTSEN 0x0200 +#define CFG_SYNCEN 0x0800 +#define CFG_CLKPOL_FALL 0x0000 +#define CFG_CLKPOL_RISE 0x1000 +#define CFG_SYNC_SLV 0x0000 +#define CFG_SYNC_MAST 0x4000 +#define CFG_LOOP_EN 0x8000 + +#define CTRL_TXBRKEN 0x0002 +#define CTRL_ADDRDET 0x0004 +#define CTRL_TXDIS 0x0040 +#define CTRL_CC 0x0100 +#define CTRL_CLRCC 0x0200 + +#define STAT_RXRDY 0x0001 +#define STAT_RXIDLE 0x0002 +#define STAT_TXRDY 0x0004 +#define STAT_TXIDLE 0x0008 +#define STAT_CTS 0x0010 +#define STAT_DELTACTS 0x0020 +#define STAT_TXDIS 0x0040 +#define STAT_OVERRUN 0x0100 +#define STAT_RXBRK 0x0400 +#define STAT_DELTARXBRK 0x0800 +#define STAT_START 0x1000 +#define STAT_FRAMERR 0x2000 +#define STAT_PARITYERR 0x4000 +#define STAT_RXNOISE 0x8000 + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART1_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART2_IRQ_PRIORITY 3 +#endif + + +/** + * @brief Uart Baud Clock (U_PCLK). + * @details The Baud clock rate we would like to achieve. + * @note The default is @p 11.0592MHz. + * A multiple of 1.8432MHz will give accurate + * results at all standard baud rates . + */ +#if !defined(LPC8xx_SERIAL_U_PCLK) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_U_PCLK 11059200 +#endif + +/** + * @brief UARTCLKDIV divider. + */ +#if !defined(LPC8xx_SERIAL_UARTCLKDIV) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UARTCLKDIV (LPC8xx_MAINCLK/LPC8xx_SERIAL_U_PCLK) +#endif + +// Output from uart clock divider +#define LPC8xx_UARTDIVCLK (LPC8xx_MAINCLK/LPC8xx_SERIAL_UARTCLKDIV) + +/** + * @brief UARTFRGDIV + * @details Fractional Baud rate generator denominator. + * @note If used, *must* be set to 256, otherwise set to 0 + */ +#if !defined(LPC8xx_SERIAL_UARTFRGDIV) || defined(__DOXYGEN__) + #if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK) + #define LPC8xx_SERIAL_UARTFRGDIV 0xFF + #else + #define LPC8xx_SERIAL_UARTFRGDIV 0x00 + #endif +#endif + +/** + * @brief UARTFRGMUL + * @details Fractional Baud rate generator numerator. + * Refer to LPC8xx User Manual 4.6.19 for calculation + * @note the *2, +1 and /2 are included to round to the nearest integer. + */ +#if !defined(LPC8xx_SERIAL_UARTFRGMUL) || defined(__DOXYGEN__) + #if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK) + #define LPC8xx_SERIAL_UARTFRGMULT ( ( ( ( (LPC8xx_UARTDIVCLK- \ + LPC8xx_SERIAL_U_PCLK) \ + *256*2 ) \ + /LPC8xx_SERIAL_U_PCLK ) \ + +1 ) \ + /2 ) + + #else + #define LPC8xx_SERIAL_UARTFRGMULT 0x00 + #endif +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC8xx_SERIAL_UARTCLKDIV < 1) || (LPC8xx_SERIAL_UARTCLKDIV > 255) +#error "invalid LPC8xx_SERIAL_UARTCLKDIV setting" +#endif + +#if (LPC8xx_SERIAL_UARTFRGDIV != 0) && (LPC8xx_SERIAL_UARTFRGDIV != 255) +#error "invalid LPC8xx_SERIAL_UARTFRGDIV setting" +#endif + +#if (LPC8xx_SERIAL_UARTFRGMUL != 0) && (LPC8xx_SERIAL_UARTFRGMUL > 255) +#error "invalid LPC8xx_SERIAL_UARTFRGMUL setting" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC8xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the CFG register. + */ + uint32_t sc_cfg; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_USART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC8xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#if LPC8xx_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#if LPC8xx_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/spi_lld.c b/os/hal/platforms/LPC8xx/spi_lld.c new file mode 100644 index 000000000..d5a8a4047 --- /dev/null +++ b/os/hal/platforms/LPC8xx/spi_lld.c @@ -0,0 +1,385 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/spi_lld.c + * @brief LPC8xx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC8xx_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC8xx_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void spi_load_txdata(SPIDriver *spip) { + + LPC_SPI_TypeDef *spi = spip->spi; + + if (--spip->txcnt == 0) { + spi->TXCTRL |= SPI_TXCTRL_EOT; + } + + if (spip->txptr != NULL) { + if ((spi->TXCTRL & SPI_TXCTRL_FLEN_MASK) > SPI_TXCTRL_FLEN(8)) { + const uint16_t *p = spip->txptr; + spi->TXDAT = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + spi->TXDAT = *p++; + spip->txptr = p; + } + } + else + spi->TXDAT = 0xffff; +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + + LPC_SPI_TypeDef *spi = spip->spi; + + if (spi->INTSTAT & (SPI_STAT_RXOV | SPI_STAT_TXUR)) { + /* The overflow condition should never happen becausepriority is given + to receive but a hook macro is provided anyway...*/ + LPC8xx_SPI_ERROR_HOOK(spip); + spi->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR); + } + + if (spi->INTSTAT & SPI_STAT_TXRDY) { + spi_load_txdata( spip ); + } + + if (spip->txcnt == 0) { + spi->INTENCLR = (SPI_STAT_TXRDY | SPI_STAT_TXUR); + } + + if (spi->INTSTAT & SPI_STAT_RXRDY) { + if (spip->rxptr != NULL) { + if ((spi->TXCTRL & SPI_TXCTRL_FLEN_MASK) > SPI_TXCTRL_FLEN(8)) { + uint16_t *p = spip->rxptr; + *p++ = spi->RXDAT; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = spi->RXDAT; + spip->rxptr = p; + } + } + else + (void)spi->RXDAT; + + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + spi->INTENCLR = (SPI_STAT_RXRDY | SPI_STAT_TXRDY | + SPI_STAT_RXOV | SPI_STAT_TXUR); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC8xx_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** + * @brief SPI0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector40) { + + CH_IRQ_PROLOGUE(); + spi_serve_interrupt(&SPID1); + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC8xx_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** + * @brief SPI1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector44) { + + CH_IRQ_PROLOGUE(); + spi_serve_interrupt(&SPID2); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC8xx_SPI_USE_SPI0 + spiObjectInit(&SPID1); + SPID1.spi = LPC_SPI0; +#endif + +#if LPC8xx_SPI_USE_SPI1 + spiObjectInit(&SPID2); + SPID2.spi = LPC_SPI1; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { +#if LPC8xx_SPI_USE_SPI0 + if (&SPID1 == spip) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11); + LPC_SYSCON->PRESETCTRL |= (1<<0); + spip->spi->DIV = LPC8xx_SPI_SPI0CLKDIV; + nvicEnableVector(SPI0_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SPI_SPI0_IRQ_PRIORITY)); + } +#endif +#if LPC8xx_SPI_USE_SPI1 + if (&SPID2 == spip) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); + LPC_SYSCON->PRESETCTRL |= (1<<1); + spip->spi->DIV = LPC8xx_SPI_SPI1CLKDIV; + nvicEnableVector(SPI1_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SPI_SPI1_IRQ_PRIORITY)); + } +#endif + } + + spip->spi->DLY = spip->config->dly; + spip->spi->TXCTRL = spip->config->txctrl; + spip->spi->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR); + spip->spi->CFG = spip->config->cfg | SPI_CFG_ENABLE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->spi->CFG = 0; + +#if LPC8xx_SPI_USE_SPI0 + if (&SPID1 == spip) { + nvicDisableVector(SPI0_IRQn); + LPC_SYSCON->PRESETCTRL &= ~(1<<0); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<11); + } +#endif + +#if LPC8xx_SPI_USE_SPI1 + if (&SPID2 == spip) { + nvicDisableVector(SPI1_IRQn); + LPC_SYSCON->PRESETCTRL &= ~(1<<1); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12); + } +#endif + + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + /* Hardware controls SSEL */ + (void)spip; +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + /* Hardware controls SSEL */ + (void)spip; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + spip->spi->TXCTRL &= ~SPI_TXCTRL_EOT; + spi_load_txdata(spip); + + if (spip->txcnt == 0) + spip->spi->INTENSET = (SPI_STAT_RXRDY | SPI_STAT_RXOV); + else + spip->spi->INTENSET = (SPI_STAT_RXRDY | SPI_STAT_TXRDY | + SPI_STAT_RXOV | SPI_STAT_TXUR); + +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spi_lld_exchange( spip, n, NULL, NULL); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spi_lld_exchange( spip, n, txbuf, NULL); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spi_lld_exchange( spip, n, NULL, rxbuf); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->TXCTRL |= SPI_TXCTRL_EOT; + spip->spi->TXDAT = frame; + while ((spip->spi->STAT & SPI_STAT_RXRDY) == 0) + ; + return (uint16_t)spip->spi->RXDAT; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/spi_lld.h b/os/hal/platforms/LPC8xx/spi_lld.h new file mode 100644 index 000000000..4acd52547 --- /dev/null +++ b/os/hal/platforms/LPC8xx/spi_lld.h @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC8xx/spi_lld.h + * @brief LPC8xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SPI_CFG_ENABLE (1<<0) +#define SPI_CFG_MASTER (1<<2) +#define SPI_CFG_LSBF (1<<3) +#define SPI_CFG_CHPA (1<<4) +#define SPI_CFG_CPOL (1<<5) +#define SPI_CFG_LOOP (1<<7) +#define SPI_CFG_SPOL (1<<8) + +#define SPI_DLY_PRE(n) (((n)&0x0f)<< 0) +#define SPI_DLY_POST(n) (((n)&0x0f)<< 4) +#define SPI_DLY_FRAME(n) (((n)&0x0f)<< 8) +#define SPI_DLY_TFER(n) (((n)&0x0f)<<12) + +#define SPI_STAT_RXRDY (1<<0) +#define SPI_STAT_TXRDY (1<<1) +#define SPI_STAT_RXOV (1<<2) +#define SPI_STAT_TXUR (1<<3) +#define SPI_STAT_SSA (1<<4) +#define SPI_STAT_SSD (1<<5) +#define SPI_STAT_STALL (1<<6) +#define SPI_STAT_EOT (1<<7) +#define SPI_STAT_IDLE (1<<8) + +#define SPI_TXCTRL_TXSSELN (1<<16) +#define SPI_TXCTRL_EOT (1<<20) +#define SPI_TXCTRL_EOF (1<<21) +#define SPI_TXCTRL_RXIGNORE (1<<22) +#define SPI_TXCTRL_FLEN(n) (((n)-1)<<24) +#define SPI_TXCTRL_FLEN_MASK (0x0f<<24) + + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SPI0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC8xx_SPI_USE_SPI0) || defined(__DOXYGEN__) +#define LPC8xx_SPI_USE_SPI0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC8xx_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define LPC8xx_SPI_USE_SPI1 FALSE +#endif + +/** + * @brief SPI0 PCLK divider. + */ +#if !defined(LPC8xx_SPI_SPI0CLKDIV) || defined(__DOXYGEN__) +#define LPC8xx_SPI_SPI0CLKDIV 1 +#endif + +/** + * @brief SPI1 PCLK divider. + */ +#if !defined(LPC8xx_SPI_SPI1CLKDIV) || defined(__DOXYGEN__) +#define LPC8xx_SPI_SPI1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC8xx_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SPI_SPI0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC8xx_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SPI_SPI1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC8xx_SPI_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC8xx_SPI_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC8xx_SPI_SPI0CLKDIV < 1) || (LPC8xx_SPI_SPI0CLKDIV > 255) +#error "invalid LPC8xx_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC8xx_SPI_SPI1CLKDIV < 1) || (LPC8xx_SPI_SPI1CLKDIV > 255) +#error "invalid LPC8xx_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC8xx_SPI_USE_SPI0 && !LPC8xx_SPI_USE_SPI1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/** + * @brief SPI0 clock. + */ +#define LPC8xx_SPI_SPI0_PCLK \ + (LPC8xx_SYSCLK / LPC8xx_SPI_SPI0CLKDIV) + +/** + * @brief SPI1 clock. + */ +#define LPC8xx_SPI_SPI1_PCLK \ + (LPC8xx_SYSCLK / LPC8xx_SPI_SPI1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + + /** + * @brief SPI CFG initialization data. + */ + uint16_t cfg; + /** + * @brief SPI DLY initialization data. + */ + uint16_t dly; + /** + * @brief SPI TXCTRL initialization data. + */ + uint32_t txctrl; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPI registers block. + */ + LPC_SPI_TypeDef *spi; + /** + * @brief Number of words yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of words yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC8xx_SPI_USE_SPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC8xx_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/system_LPC8xx.h b/os/hal/platforms/LPC8xx/system_LPC8xx.h new file mode 100644 index 000000000..108baa842 --- /dev/null +++ b/os/hal/platforms/LPC8xx/system_LPC8xx.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * @file: system_LPC8xx.h + * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File + * for the NXP LPC8xx Device Series + * @version: V1.0 + * @date: 16. Aug. 2012 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC8xx_H +#define __SYSTEM_LPC8xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC8xx_H */ diff --git a/os/hal/platforms/MSP430/hal_lld.c b/os/hal/platforms/MSP430/hal_lld.c new file mode 100644 index 000000000..9fc17af0c --- /dev/null +++ b/os/hal/platforms/MSP430/hal_lld.c @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/hal_lld.c + * @brief MSP430 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* RTC initially stopped.*/ + WDTCTL = 0x5A80; + + /* Clock sources setup.*/ + DCOCTL = VAL_DCOCTL; + BCSCTL1 = VAL_BCSCTL1; +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK + do { + int i; + IFG1 &= ~OFIFG; + for (i = 255; i > 0; i--) + asm("nop"); + } while (IFG1 & OFIFG); +#endif + BCSCTL2 = VAL_BCSCTL2; +} + +/** @} */ diff --git a/os/hal/platforms/MSP430/hal_lld.h b/os/hal/platforms/MSP430/hal_lld.h new file mode 100644 index 000000000..80ee0d14b --- /dev/null +++ b/os/hal/platforms/MSP430/hal_lld.h @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/hal_lld.h + * @brief MSP430 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "msp430.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "MSP430" + +#define MSP430_CLOCK_SOURCE_XT2CLK 0 /**< @brief XT2CLK clock selector. */ +#define MSP430_CLOCK_SOURCE_DCOCLK 1 /**< @brief DCOCLK clock selector. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Clock source. + * @details The clock source can be selected from: + * - @p MSP430_CLOCK_SOURCE_XT2CLK. + * - @p MSP430_CLOCK_SOURCE_DCOCLK. + * . + */ +#if !defined(MSP430_USE_CLOCK) || defined(__DOXYGEN__) +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Calculating the derived clock constants. + */ +#define ACLK LFXT1CLK +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK +#define MCLK XT2CLK +#define SMCLK (XT2CLK / 8) +#elif MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK +#define MCLK DCOCLK +#define SMCLK DCOCLK +#else +#error "unknown clock source specified" +#endif + +/* + * Calculating the initialization values. + */ +#define VAL_DCOCTL (DCO0 | DCO1) +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK +#define VAL_BCSCTL1 (RSEL2) +#define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) +#endif +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK +#define VAL_BCSCTL1 (XT2OFF | RSEL2) +#define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/MSP430/pal_lld.c b/os/hal/platforms/MSP430/pal_lld.c new file mode 100644 index 000000000..70f848d82 --- /dev/null +++ b/os/hal/platforms/MSP430/pal_lld.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/pal_lld.c + * @brief MSP430 Digital I/O low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MSP430 I/O ports configuration. + * @note The @p PxIFG, @p PxIE and @p PxSEL registers are cleared. @p PxOUT + * and @p PxDIR are configured as specified. + * + * @param[in] config the MSP430 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) + IOPORT1->iop_full.ie = 0; + IOPORT1->iop_full.ifg = 0; + IOPORT1->iop_full.sel = 0; + IOPORT1->iop_common.out = config->P1Data.out; + IOPORT1->iop_common.dir = config->P1Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) + IOPORT2->iop_full.ie = 0; + IOPORT2->iop_full.ifg = 0; + IOPORT2->iop_full.sel = 0; + IOPORT2->iop_common.out = config->P2Data.out; + IOPORT2->iop_common.dir = config->P2Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) + IOPORT3->iop_simple.sel = 0; + IOPORT3->iop_common.out = config->P3Data.out; + IOPORT3->iop_common.dir = config->P3Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) + IOPORT4->iop_simple.sel = 0; + IOPORT4->iop_common.out = config->P4Data.out; + IOPORT4->iop_common.dir = config->P4Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) + IOPORT5->iop_simple.sel = 0; + IOPORT5->iop_common.out = config->P5Data.out; + IOPORT5->iop_common.dir = config->P5Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) + IOPORT6->iop_simple.sel = 0; + IOPORT6->iop_common.out = config->P6Data.out; + IOPORT6->iop_common.dir = config->P6Data.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. Unconnected pads are set to + * high logic state by default. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->iop_common.dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->iop_common.out |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->iop_common.dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/MSP430/pal_lld.h b/os/hal/platforms/MSP430/pal_lld.h new file mode 100644 index 000000000..39138fba5 --- /dev/null +++ b/os/hal/platforms/MSP430/pal_lld.h @@ -0,0 +1,323 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/pal_lld.h + * @brief MSP430 Digital I/O low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Simple MSP430 I/O port. + */ +struct msp430_port_simple_t { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; + volatile uint8_t sel; +}; + +/** + * @brief Full MSP430 I/O port. + */ +struct msp430_port_full_t { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; + volatile uint8_t ifg; + volatile uint8_t ies; + volatile uint8_t ie; + volatile uint8_t sel; +#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) + volatile uint8_t ren; +#endif +}; + +/** + * @brief Simplified MSP430 I/O port representation. + * @details This structure represents the common part of all the MSP430 I/O + * ports. + */ +struct msp430_port_common { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; +}; + +/** + * @brief Generic MSP430 I/O port. + */ +typedef union { + struct msp430_port_common iop_common; + struct msp430_port_simple_t iop_simple; + struct msp430_port_full_t iop_full; +} msp430_ioport_t; + +/** + * @brief Setup registers common to all the MSP430 ports. + */ +typedef struct { + volatile uint8_t out; + volatile uint8_t dir; +} msp430_dio_setup_t; + +/** + * @brief MSP430 I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 1 setup data.*/ + msp430_dio_setup_t P1Data; +#endif +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 2 setup data.*/ + msp430_dio_setup_t P2Data; +#endif +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 3 setup data.*/ + msp430_dio_setup_t P3Data; +#endif +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 4 setup data.*/ + msp430_dio_setup_t P4Data; +#endif +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 5 setup data.*/ + msp430_dio_setup_t P5Data; +#endif +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 6 setup data.*/ + msp430_dio_setup_t P6Data; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint16_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef msp430_ioport_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief I/O port A identifier. + * @details This port identifier is mapped on the MSP430 port 1 (P1). + */ +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) +#define IOPORT1 ((ioportid_t)P1IN_) +#endif + +/** + * @brief I/O port B identifier. + * @details This port identifier is mapped on the MSP430 port 2 (P2). + */ +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) +#define IOPORT2 ((ioportid_t)P2IN_) +#endif + +/** + * @brief I/O port C identifier. + * @details This port identifier is mapped on the MSP430 port 3 (P3). + */ +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) +#define IOPORT3 ((ioportid_t)P3IN_) +#endif + +/** + * @brief I/O port D identifier. + * @details This port identifier is mapped on the MSP430 port 4 (P4). + */ +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) +#define IOPORT4 ((ioportid_t)P4IN_) +#endif + +/** + * @brief I/O port E identifier. + * @details This port identifier is mapped on the MSP430 port 5 (P5). + */ +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) +#define IOPORT5 ((ioportid_t)P5IN_) +#endif + +/** + * @brief I/O port F identifier. + * @details This port identifier is mapped on the MSP430 port 6 (P6). + */ +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) +#define IOPORT6 ((ioportid_t)P6IN_) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * @details In MSP430 programs all the ports as input. + * + * @param[in] config the MSP430 ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @details This function is implemented by reading the PxIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->iop_common.in) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->iop_common.out) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->iop_common.out = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* _PAL_LLD_H_ */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/MSP430/platform.dox b/os/hal/platforms/MSP430/platform.dox new file mode 100644 index 000000000..131743e66 --- /dev/null +++ b/os/hal/platforms/MSP430/platform.dox @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup MSP430_DRIVERS MSP430 Drivers + * @details This section describes all the supported drivers on the MSP430 + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup MSP430_HAL MSP430 Initialization Support + * @details The MSP430 HAL support is responsible for system initialization. + * + * @section msp430_hal_1 Supported HW resources + * - DCOCTL. + * - BCSCTL1. + * - BCSCTL2. + * . + * @section msp430_hal_2 MSP430 HAL driver implementation features + * - Clock source selection. + * . + * @ingroup MSP430_DRIVERS + */ + +/** + * @defgroup MSP430_PAL MSP430 PAL Support + * @details The MSP430 PAL driver uses the PORT peripherals. + * + * @section msp430_pal_1 Supported HW resources + * - PORT1 (where present). + * - PORT2 (where present). + * - PORT3 (where present). + * - PORT4 (where present). + * - PORT5 (where present). + * - PORT6 (where present). + * . + * @section msp430_pal_2 MSP430 PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special MSP430 instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section msp430_pal_3 Supported PAL setup modes + * The MSP430 PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section msp430_pal_4 Suboptimal behavior + * The MSP430 PORT is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writes is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup MSP430_DRIVERS + */ + +/** + * @defgroup MSP430_SERIAL MSP430 Serial Support + * @details The MSP430 Serial driver uses the USART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section msp430_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART0. + * - USART1. + * . + * @section msp430_serial_2 MSP430 Serial driver implementation features + * - Each USART can be independently enabled and programmed. + * - Fully interrupt driven. + * . + * @ingroup MSP430_DRIVERS + */ diff --git a/os/hal/platforms/MSP430/platform.mk b/os/hal/platforms/MSP430/platform.mk new file mode 100644 index 000000000..d0175c1df --- /dev/null +++ b/os/hal/platforms/MSP430/platform.mk @@ -0,0 +1,7 @@ +# List of all the MSP430 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/MSP430/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/MSP430/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/MSP430/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/MSP430 diff --git a/os/hal/platforms/MSP430/serial_lld.c b/os/hal/platforms/MSP430/serial_lld.c new file mode 100644 index 000000000..ed17c45c2 --- /dev/null +++ b/os/hal/platforms/MSP430/serial_lld.c @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/serial_lld.c + * @brief MSP430 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +/** @brief USART0 serial driver identifier.*/ +SerialDriver SD1; +#endif +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +/** @brief USART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + UBR(SERIAL_DEFAULT_BITRATE), + 0, + CHAR +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(SerialDriver *sdp, uint8_t urctl) { + flagsmask_t sts = 0; + + if (urctl & OE) + sts |= SD_OVERRUN_ERROR; + if (urctl & PE) + sts |= SD_PARITY_ERROR; + if (urctl & FE) + sts |= SD_FRAMING_ERROR; + if (urctl & BRK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (!(U0IE & UTXIE0)) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + U0IE |= UTXIE0; + U0TXBUF = (uint8_t)b; + } + } +} + +/** + * @brief USART0 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart0_init(const SerialConfig *config) { + + U0CTL = SWRST; /* Resets the USART. */ + /* USART init */ + U0TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ + U0MCTL = config->sc_mod; /* Modulator. */ + U0BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ + U0BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ + /* Clear USART status.*/ + (void)U0RXBUF; + U0RCTL = 0; + /* USART enable.*/ + U0ME |= UTXE0 + URXE0; /* Enables the USART. */ + U0CTL = config->sc_ctl & ~SWRST; /* Various settings. */ + U0IE |= URXIE0; /* Enables RX interrupt. */ +} + +/** + * @brief USART0 de-initialization. + */ +static void usart0_deinit(void) { + + U0IE &= ~URXIE0; + U0CTL = SWRST; +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (!(U1IE & UTXIE1)) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + U1IE |= UTXIE1; + U1TXBUF = (uint8_t)b; + } + } +} + +/** + * @brief USART1 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart1_init(const SerialConfig *config) { + + U1CTL = SWRST; /* Resets the USART. */ + /* USART init.*/ + U1TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ + U1MCTL = config->sc_mod; /* Modulator. */ + U1BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ + U1BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ + /* Clear USART status.*/ + (void)U0RXBUF; + U1RCTL = 0; + /* USART enable.*/ + U1ME |= UTXE0 + URXE0; /* Enables the USART. */ + U1CTL = config->sc_ctl & ~SWRST; /* Various settings. */ + U1IE |= URXIE0; /* Enables RX interrupt. */ +} + +/** + * @brief USART1 de-initialization. + */ +static void usart1_deinit(void) { + + U1IE &= ~URXIE0; + U1CTL = SWRST; +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0TX) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + U0IE &= ~UTXIE0; + else + U0TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART0 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0RX) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U0RCTL) & RXERR) + set_error(&SD1, urctl); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, U0RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1TX_VECTOR) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + U1IE &= ~UTXIE1; + else + U1TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1RX_VECTOR) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U1RCTL) & RXERR) + set_error(&SD2, urctl); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, U1RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_MSP430_USART0 + sdObjectInit(&SD1, NULL, notify1); +#endif + +#if USE_MSP430_USART1 + sdObjectInit(&SD2, NULL, notify2); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_init(config); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_deinit(); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_deinit(); + return; + } +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/MSP430/serial_lld.h b/os/hal/platforms/MSP430/serial_lld.h new file mode 100644 index 000000000..ae764d739 --- /dev/null +++ b/os/hal/platforms/MSP430/serial_lld.h @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MSP430/serial_lld.h + * @brief MSP430 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_MSP430_USART0) || defined(__DOXYGEN__) +#define USE_MSP430_USART0 TRUE +#endif + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_MSP430_USART1) || defined(__DOXYGEN__) +#define USE_MSP430_USART1 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief MSP430 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Initialization value for the UBRx registers. + */ + uint16_t sc_div; + /** + * @brief Initialization value for the MOD register. + */ + uint8_t sc_mod; + /** + * @brief Initialization value for the CTL register. + */ + uint8_t sc_ctl; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBR(b) (SMCLK / (b)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_MSP430_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Posix/console.c b/os/hal/platforms/Posix/console.c new file mode 100644 index 000000000..dbbfbf661 --- /dev/null +++ b/os/hal/platforms/Posix/console.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file console.c + * @brief Simulator console driver code. + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "console.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Console driver 1. + */ +BaseChannel CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static size_t write(void *ip, const uint8_t *bp, size_t n) { + size_t ret; + + (void)ip; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t read(void *ip, uint8_t *bp, size_t n) { + + (void)ip; + return fread(bp, 1, n, stdin); +} + +static msg_t put(void *ip, uint8_t b) { + + (void)ip; + + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t get(void *ip) { + + (void)ip; + + return fgetc(stdin); +} + +static msg_t putt(void *ip, uint8_t b, systime_t time) { + + (void)ip; + (void)time; + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t gett(void *ip, systime_t time) { + + (void)ip; + (void)time; + return fgetc(stdin); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + size_t ret; + + (void)ip; + (void)time; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + (void)ip; + (void)time; + return fread(bp, 1, n, stdin); +} + +static const struct BaseChannelVMT vmt = { + write, read, put, get, + putt, gett, writet, readt +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void conInit(void) { + + CD1.vmt = &vmt; +} + +/** @} */ diff --git a/os/hal/platforms/Posix/console.h b/os/hal/platforms/Posix/console.h new file mode 100644 index 000000000..491b6f36b --- /dev/null +++ b/os/hal/platforms/Posix/console.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file console.h + * @brief Simulator console driver header. + * @{ + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern BaseChannel CD1; + +#ifdef __cplusplus +extern "C" { +#endif + void conInit(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Posix/hal_lld.c b/os/hal/platforms/Posix/hal_lld.c new file mode 100644 index 000000000..fb1bed779 --- /dev/null +++ b/os/hal/platforms/Posix/hal_lld.c @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/hal_lld.c + * @brief Posix HAL subsystem low level driver code. + * + * @addtogroup POSIX_HAL + * @{ + */ + +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static struct timeval nextcnt; +static struct timeval tick = {0, 1000000 / CH_FREQUENCY}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + */ +void hal_lld_init(void) { + +#if defined(__APPLE__) + puts("ChibiOS/RT simulator (OS X)\n"); +#else + puts("ChibiOS/RT simulator (Linux)\n"); +#endif + gettimeofday(&nextcnt, NULL); + timeradd(&nextcnt, &tick, &nextcnt); +} + +/** + * @brief Interrupt simulation. + */ +void ChkIntSources(void) { + struct timeval tv; + +#if HAL_USE_SERIAL + if (sd_lld_interrupt_pending()) { + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + return; + } +#endif + + gettimeofday(&tv, NULL); + if (timercmp(&tv, &nextcnt, >=)) { + timeradd(&nextcnt, &tick, &nextcnt); + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); + + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + } +} + +/** @} */ diff --git a/os/hal/platforms/Posix/hal_lld.h b/os/hal/platforms/Posix/hal_lld.h new file mode 100644 index 000000000..fd1dd3245 --- /dev/null +++ b/os/hal/platforms/Posix/hal_lld.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/hal_lld.h + * @brief Posix simulator HAL subsystem low level driver header. + * + * @addtogroup POSIX_HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include +#include +#include + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "Linux" + +#define SOCKET int +#define INVALID_SOCKET -1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Posix/pal_lld.c b/os/hal/platforms/Posix/pal_lld.c new file mode 100644 index 000000000..05965722b --- /dev/null +++ b/os/hal/platforms/Posix/pal_lld.c @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/pal_lld.c + * @brief Posix low level simulated PAL driver code. + * + * @addtogroup POSIX_PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief VIO1 simulated port. + */ +sim_vio_port_t vio_port_1; + +/** + * @brief VIO2 simulated port. + */ +sim_vio_port_t vio_port_2; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high + * state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->latch |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/Posix/pal_lld.h b/os/hal/platforms/Posix/pal_lld.h new file mode 100644 index 000000000..439d93f97 --- /dev/null +++ b/os/hal/platforms/Posix/pal_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/pal_lld.h + * @brief Posix low level simulated PAL driver header. + * + * @addtogroup POSIX_PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN +#undef PAL_MODE_INPUT_ANALOG + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief VIO port structure. + */ +typedef struct { + /** + * @brief VIO_LATCH register. + * @details This register represents the output latch of the VIO port. + */ + uint32_t latch; + /** + * @brief VIO_PIN register. + * @details This register represents the logical level at the VIO port + * pin level. + */ + uint32_t pin; + /** + * @brief VIO_DIR register. + * @details Direction of the VIO port bits, 0=input, 1=output. + */ + uint32_t dir; +} sim_vio_port_t; + +/** + * @brief Virtual I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** + * @brief Virtual port 1 setup data. + */ + sim_vio_port_t VP1Data; + /** + * @brief Virtual port 2 setup data. + */ + sim_vio_port_t VP2Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef sim_vio_port_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief VIO port 1 identifier. + */ +#define IOPORT1 (&vio_port_1) + +/** + * @brief VIO port 2 identifier. + */ +#define IOPORT2 (&vio_port_2) + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) \ + (vio_port_1 = (config)->VP1Data, \ + vio_port_2 = (config)->VP2Data) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->pin) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->latch) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +#if !defined(__DOXYGEN__) +extern sim_vio_port_t vio_port_1; +extern sim_vio_port_t vio_port_2; +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Posix/platform.mk b/os/hal/platforms/Posix/platform.mk new file mode 100644 index 000000000..e2e3da821 --- /dev/null +++ b/os/hal/platforms/Posix/platform.mk @@ -0,0 +1,7 @@ +# List of all the Posix platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Posix/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Posix/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Posix/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Posix diff --git a/os/hal/platforms/Posix/serial_lld.c b/os/hal/platforms/Posix/serial_lld.c new file mode 100644 index 000000000..cfe6792ca --- /dev/null +++ b/os/hal/platforms/Posix/serial_lld.c @@ -0,0 +1,287 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/serial_lld.c + * @brief Posix low level simulated serial driver code. + * + * @addtogroup POSIX_SERIAL + * @{ + */ + +#include +#include +#include +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief Serial driver 1 identifier.*/ +#if USE_SIM_SERIAL1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif +/** @brief Serial driver 2 identifier.*/ +#if USE_SIM_SERIAL2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { +}; + +static u_long nb = 1; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void init(SerialDriver *sdp, uint16_t port) { + struct sockaddr_in sad; + struct protoent *prtp; + int sockval = 1; + socklen_t socklen = sizeof(sockval); + + + if ((prtp = getprotobyname("tcp")) == NULL) { + printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); + goto abort; + } + + sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); + if (sdp->com_listen == INVALID_SOCKET) { + printf("%s: Error creating simulator socket\n", sdp->com_name); + goto abort; + } + + + setsockopt(sdp->com_listen, SOL_SOCKET, SO_REUSEADDR, &sockval, socklen); + + if (ioctl(sdp->com_listen, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); + goto abort; + } + + memset(&sad, 0, sizeof(sad)); + sad.sin_family = AF_INET; + sad.sin_addr.s_addr = INADDR_ANY; + sad.sin_port = htons(port); + if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { + printf("%s: Error binding socket\n", sdp->com_name); + goto abort; + } + + if (listen(sdp->com_listen, 1) != 0) { + printf("%s: Error listening socket\n", sdp->com_name); + goto abort; + } + printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); + return; + +abort: + if (sdp->com_listen != INVALID_SOCKET) + close(sdp->com_listen); + exit(1); +} + +static bool_t connint(SerialDriver *sdp) { + + if (sdp->com_data == INVALID_SOCKET) { + struct sockaddr addr; + socklen_t addrlen = sizeof(addr); + + if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) + return FALSE; + + if (ioctl(sdp->com_data, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); + goto abort; + } + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_CONNECTED); + chSysUnlockFromIsr(); + return TRUE; + } + return FALSE; +abort: + if (sdp->com_listen != INVALID_SOCKET) + close(sdp->com_listen); + if (sdp->com_data != INVALID_SOCKET) + close(sdp->com_data); + exit(1); +} + +static bool_t inint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int i; + uint8_t data[32]; + + /* + * Input. + */ + int n = recv(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case INVALID_SOCKET: + if (errno == EWOULDBLOCK) + return FALSE; + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + for (i = 0; i < n; i++) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, data[i]); + chSysUnlockFromIsr(); + } + return TRUE; + } + return FALSE; +} + +static bool_t outint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int n; + uint8_t data[1]; + + /* + * Input. + */ + chSysLockFromIsr(); + n = sdRequestDataI(sdp); + chSysUnlockFromIsr(); + if (n < 0) + return FALSE; + data[0] = (uint8_t)n; + n = send(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case INVALID_SOCKET: + if (errno == EWOULDBLOCK) + return FALSE; + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + return TRUE; + } + return FALSE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + */ +void sd_lld_init(void) { + +#if USE_SIM_SERIAL1 + sdObjectInit(&SD1, NULL, NULL); + SD1.com_listen = INVALID_SOCKET; + SD1.com_data = INVALID_SOCKET; + SD1.com_name = "SD1"; +#endif + +#if USE_SIM_SERIAL2 + sdObjectInit(&SD2, NULL, NULL); + SD2.com_listen = INVALID_SOCKET; + SD2.com_data = INVALID_SOCKET; + SD2.com_name = "SD2"; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_SIM_SERIAL1 + if (sdp == &SD1) + init(&SD1, SIM_SD1_PORT); +#endif + +#if USE_SIM_SERIAL2 + if (sdp == &SD2) + init(&SD2, SIM_SD2_PORT); +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) { + + (void)sdp; +} + +bool_t sd_lld_interrupt_pending(void) { + bool_t b; + + CH_IRQ_PROLOGUE(); + + b = connint(&SD1) || connint(&SD2) || + inint(&SD1) || inint(&SD2) || + outint(&SD1) || outint(&SD2); + + CH_IRQ_EPILOGUE(); + + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/Posix/serial_lld.h b/os/hal/platforms/Posix/serial_lld.h new file mode 100644 index 000000000..4c770abe2 --- /dev/null +++ b/os/hal/platforms/Posix/serial_lld.h @@ -0,0 +1,151 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Posix/serial_lld.h + * @brief Posix low level simulated serial driver header. + * + * @addtogroup POSIX_SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 1024 +#endif + +/** + * @brief SD1 driver enable switch. + * @details If set to @p TRUE the support for SD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SIM_SERIAL1) || defined(__DOXYGEN__) +#define USE_SIM_SERIAL1 TRUE +#endif + +/** + * @brief SD2 driver enable switch. + * @details If set to @p TRUE the support for SD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SIM_SERIAL2) || defined(__DOXYGEN__) +#define USE_SIM_SERIAL2 TRUE +#endif + +/** + * @brief Listen port for SD1. + */ +#if !defined(SD1_PORT) || defined(__DOXYGEN__) +#define SIM_SD1_PORT 29001 +#endif + +/** + * @brief Listen port for SD2. + */ +#if !defined(SD2_PORT) || defined(__DOXYGEN__) +#define SIM_SD2_PORT 29002 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Listen socket for simulated serial port.*/ \ + SOCKET com_listen; \ + /* Data socket for simulated serial port.*/ \ + SOCKET com_data; \ + /* Port readable name.*/ \ + const char *com_name; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SIM_SERIAL1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SIM_SERIAL2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + bool_t sd_lld_interrupt_pending(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c new file mode 100644 index 000000000..5d14daf27 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/hal_lld.c @@ -0,0 +1,281 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/hal_lld.c + * @brief SPC560B/Cxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief PIT channel 3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector59) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + /* Resets the PIT channel 3 IRQ flag.*/ + PIT.CH[0].TFLG.R = 1; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t reg; + + /* The system is switched to the RUN0 mode, the default for normal + operations.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* PIT channel 0 initialization for Kernel ticks, the PIT is configured + to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other + modes.*/ + INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; + halSPCSetPeripheralClockMode(92, + SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); + reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; + PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ + PIT.CH[0].LDVAL.R = reg; + PIT.CH[0].CVAL.R = reg; + PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ + PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ +} + +/** + * @brief SPC560B/Cxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + + /* Waiting for IRC stabilization before attempting anything else.*/ + while (!ME.GS.B.S_FIRC) + ; + +#if !SPC5_NO_INIT + +#if SPC5_DISABLE_WATCHDOG + /* SWT disabled.*/ + SWT.SR.R = 0xC520; + SWT.SR.R = 0xD928; + SWT.CR.R = 0xFF00000A; +#endif + + /* SSCM initialization. Setting up the most restrictive handling of + invalid accesses to peripherals.*/ + SSCM.ERROR.R = 3; /* PAE and RAE bits. */ + + /* RGM errors clearing.*/ + RGM.FES.R = 0xFFFF; + RGM.DES.R = 0xFFFF; + + /* Oscillators dividers setup.*/ + CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1; + CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1; + + /* The system must be in DRUN mode on entry, if this is not the case then + it is considered a serious anomaly.*/ + if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) { + SPC5_CLOCK_FAILURE_HOOK(); + } + +#if defined(SPC5_OSC_BYPASS) + /* If the board is equipped with an oscillator instead of a xtal then the + bypass must be activated.*/ + CGM.OSC_CTL.B.OSCBYP = TRUE; +#endif /* SPC5_OSC_BYPASS */ + + /* Setting the various dividers and source selectors.*/ + CGM.SC_DC[0].R = SPC5_CGM_SC_DC0; + CGM.SC_DC[1].R = SPC5_CGM_SC_DC1; + CGM.SC_DC[2].R = SPC5_CGM_SC_DC2; + + /* Initialization of the FMPLLs settings.*/ + CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF | + ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL0_NDIV_VALUE << 16); + CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */ + + /* Run modes initialization.*/ + ME.IS.R = 8; /* Resetting I_ICONF status.*/ + ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ + ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */ + ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ + ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ + ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ + ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ + ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ + ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ + ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ + ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ + ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */ + if (ME.IS.B.I_CONF) { + /* Configuration rejected.*/ + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Peripherals run and low power modes initialization.*/ + ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; + ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; + ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; + ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; + ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; + ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; + ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; + ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; + ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; + ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; + ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; + ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; + ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; + ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; + ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; + ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; + + /* CFLASH settings calculated for a maximum clock of 64MHz.*/ + CFLASH.PFCR0.B.BK0_APC = 2; + CFLASH.PFCR0.B.BK0_RWSC = 2; + CFLASH.PFCR1.B.BK1_APC = 2; + CFLASH.PFCR1.B.BK1_RWSC = 2; + + /* Switches again to DRUN mode (current mode) in order to update the + settings.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } +#endif /* !SPC5_NO_INIT */ +} + +/** + * @brief Switches the system to the specified run mode. + * + * @param[in] mode one of the possible run modes + * + * @return The operation status. + * @retval CH_SUCCESS if the switch operation has been completed. + * @retval CH_FAILED if the switch operation failed. + */ +bool_t halSPCSetRunMode(spc5_runmode_t mode) { + + /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/ + ME.IS.R = 5; + + /* Starts a transition process.*/ + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; + + /* Waits for the mode switch or an error condition.*/ + while (TRUE) { + uint32_t r = ME.IS.R; + if (r & 1) + return CH_SUCCESS; + if (r & 4) + return CH_FAILED; + } +} + +/** + * @brief Changes the clock mode of a peripheral. + * + * @param[in] n index of the @p PCTL register + * @param[in] pctl new value for the @p PCTL register + * + * @notapi + */ +void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) { + uint32_t mode; + + ME.PCTL[n].R = pctl; + mode = ME.MCTL.B.TARGET_MODE; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; +} + +#if !SPC5_NO_INIT || defined(__DOXYGEN__) +/** + * @brief Returns the system clock under the current run mode. + * + * @return The system clock in Hertz. + */ +uint32_t halSPCGetSystemClock(void) { + uint32_t sysclk; + + sysclk = ME.GS.B.S_SYSCLK; + switch (sysclk) { + case SPC5_ME_GS_SYSCLK_IRC: + return SPC5_IRC_CLK; + case SPC5_ME_GS_SYSCLK_DIVIRC: + return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE; + case SPC5_ME_GS_SYSCLK_XOSC: + return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE; + case SPC5_ME_GS_SYSCLK_DIVXOSC: + return SPC5_XOSC_CLK; + case SPC5_ME_GS_SYSCLK_FMPLL0: + return SPC5_FMPLL0_CLK; + default: + return 0; + } +} +#endif /* !SPC5_NO_INIT */ + +/** @} */ diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h new file mode 100644 index 000000000..ddf44dff3 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -0,0 +1,779 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/hal_lld.h + * @brief SPC560B/Cxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * - SPC5_OSC_BYPASS (optionally). + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc560bc.h" +#include "spc560bc_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MAX 16000000 + +/** + * @brief Minimum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MIN 4000000 + +/** + * @brief Maximum SXOSC clock frequency. + */ +#define SPC5_SXOSC_CLK_MAX 40000 + +/** + * @brief Minimum SXOSC clock frequency. + */ +#define SPC5_SXOSC_CLK_MIN 32000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MAX 64000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MAX 512000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MIN 256000000 + +/** + * @brief Maximum FMPLL0 output clock frequency. + */ +#define SPC5_FMPLL0_CLK_MAX 64000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define SPC5_IRC_CLK 16000000 /**< Internal fast RC + oscillator. */ +#define SPC5_SIRC_CLK 128000 /**< Internal RC slow + oscillator. */ +/** @} */ + +/** + * @name FMPLL_CR register bits definitions + * @{ + */ +#define SPC5_FMPLL_ODF_DIV2 (0U << 24) +#define SPC5_FMPLL_ODF_DIV4 (1U << 24) +#define SPC5_FMPLL_ODF_DIV8 (2U << 24) +#define SPC5_FMPLL_ODF_DIV16 (3U << 24) +/** @} */ + +/** + * @name ME_GS register bits definitions + * @{ + */ +#define SPC5_ME_GS_SYSCLK_MASK (15U << 0) +#define SPC5_ME_GS_SYSCLK_IRC (0U << 0) +#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0) +#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) +#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0) +#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) +/** @} */ + +/** + * @name ME_ME register bits definitions + * @{ + */ +#define SPC5_ME_ME_RESET (1U << 0) +#define SPC5_ME_ME_TEST (1U << 1) +#define SPC5_ME_ME_SAFE (1U << 2) +#define SPC5_ME_ME_DRUN (1U << 3) +#define SPC5_ME_ME_RUN0 (1U << 4) +#define SPC5_ME_ME_RUN1 (1U << 5) +#define SPC5_ME_ME_RUN2 (1U << 6) +#define SPC5_ME_ME_RUN3 (1U << 7) +#define SPC5_ME_ME_HALT0 (1U << 8) +#define SPC5_ME_ME_STOP0 (1U << 10) +#define SPC5_ME_ME_STANDBY0 (1U << 13) +/** @} */ + +/** + * @name ME_xxx_MC registers bits definitions + * @{ + */ +#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) +#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_IRCON (1U << 4) +#define SPC5_ME_MC_XOSC0ON (1U << 5) +#define SPC5_ME_MC_PLL0ON (1U << 6) +#define SPC5_ME_MC_CFLAON_MASK (3U << 16) +#define SPC5_ME_MC_CFLAON(n) ((n) << 16) +#define SPC5_ME_MC_CFLAON_PD (1U << 16) +#define SPC5_ME_MC_CFLAON_LP (2U << 16) +#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16) +#define SPC5_ME_MC_DFLAON_MASK (3U << 18) +#define SPC5_ME_MC_DFLAON(n) ((n) << 18) +#define SPC5_ME_MC_DFLAON_PD (1U << 18) +#define SPC5_ME_MC_DFLAON_LP (2U << 18) +#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18) +#define SPC5_ME_MC_MVRON (1U << 20) +#define SPC5_ME_MC_PDO (1U << 23) +/** @} */ + +/** + * @name ME_MCTL register bits definitions + * @{ + */ +#define SPC5_ME_MCTL_KEY 0x5AF0U +#define SPC5_ME_MCTL_KEY_INV 0xA50FU +#define SPC5_ME_MCTL_MODE_MASK (15U << 28) +#define SPC5_ME_MCTL_MODE(n) ((n) << 28) +/** @} */ + +/** + * @name ME_RUN_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_RUN_PC_TEST (1U << 1) +#define SPC5_ME_RUN_PC_SAFE (1U << 2) +#define SPC5_ME_RUN_PC_DRUN (1U << 3) +#define SPC5_ME_RUN_PC_RUN0 (1U << 4) +#define SPC5_ME_RUN_PC_RUN1 (1U << 5) +#define SPC5_ME_RUN_PC_RUN2 (1U << 6) +#define SPC5_ME_RUN_PC_RUN3 (1U << 7) +/** @} */ + +/** + * @name ME_LP_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_LP_PC_HALT0 (1U << 8) +#define SPC5_ME_LP_PC_STOP0 (1U << 10) +#define SPC5_ME_LP_PC_STANDBY0 (1U << 10) +/** @} */ + +/** + * @name ME_PCTL registers bits definitions + * @{ + */ +#define SPC5_ME_PCTL_RUN_MASK (7U << 0) +#define SPC5_ME_PCTL_RUN(n) ((n) << 0) +#define SPC5_ME_PCTL_LP_MASK (7U << 3) +#define SPC5_ME_PCTL_LP(n) ((n) << 3) +#define SPC5_ME_PCTL_DBG (1U << 6) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief Disables the watchdog on start. + */ +#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__) +#define SPC5_DISABLE_WATCHDOG TRUE +#endif + +/** + * @brief FMPLL0 IDF divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_IDF_VALUE 1 +#endif + +/** + * @brief FMPLL0 NDIV divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_NDIV_VALUE 32 +#endif + +/** + * @brief FMPLL0 ODF divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#endif + +/** + * @brief XOSC divider value. + * @note The allowed range is 1...32. + */ +#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_XOSCDIV_VALUE 1 +#endif + +/** + * @brief Fast IRC divider value. + * @note The allowed range is 1...32. + */ +#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_IRCDIV_VALUE 1 +#endif + +/** + * @brief Peripherals Set 1 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Peripherals Set 2 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Peripherals Set 3 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Active run modes in ME_ME register. + * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there + * is no need to specify them. + */ +#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#endif + +/** + * @brief TEST mode settings. + */ +#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief SAFE mode settings. + */ +#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#endif + +/** + * @brief DRUN mode settings. + */ +#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN0 mode settings. + */ +#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN1 mode settings. + */ +#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN2 mode settings. + */ +#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN3 mode settings. + */ +#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief HALT0 mode settings. + */ +#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STOP0 mode settings. + */ +#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STANDBY0 mode settings. + */ +#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief Peripheral mode 0 (run mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (run mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 2 (run mode). + * @note Do not change this setting, it is expected to be the "only during + * normal run" mode. + */ +#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 3 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 4 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 5 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 6 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 7 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 0 (low power mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (low power mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#endif + +/** + * @brief Peripheral mode 2 (low power mode). + * @note Do not change this setting, it is expected to be the "halt only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#endif + +/** + * @brief Peripheral mode 3 (low power mode). + * @note Do not change this setting, it is expected to be the "stop only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 4 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 5 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 6 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 7 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief PIT channel 0 IRQ priority. + * @note This PIT channel is allocated permanently for system tick + * generation. + */ +#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#endif + +/** + * @brief Clock initialization failure hook. + * @note The default is to stop the system and let the RTC restart it. + * @note The hook code must not return. + */ +#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC560BCxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined" +#endif + +/* Check on the XOSC frequency.*/ +#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ + (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) +#error "invalid SPC5_XOSC_CLK value specified" +#endif + +/* Check on the XOSC divider.*/ +#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32) +#error "invalid SPC5_XOSCDIV_VALUE value specified" +#endif + +/* Check on the IRC divider.*/ +#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32) +#error "invalid SPC5_IRCDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_IDF_VALUE.*/ +#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL0_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_NDIV_VALUE.*/ +#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_ODF.*/ +#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL0_ODF_VALUE 2 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL0_ODF_VALUE 4 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL0_ODF_VALUE 8 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL0_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL0_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL0_VCO_CLK clock point. + */ +#define SPC5_FMPLL0_VCO_CLK \ + ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE) + +/* Check on FMPLL0 VCO output.*/ +#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL0_CLK clock point. + */ +#define SPC5_FMPLL0_CLK \ + (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE) + +/* Check on SPC5_FMPLL0_CLK.*/ +#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)" +#endif + +/* Check on the peripherals set 1 clock divider settings.*/ +#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC0 0 +#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified" +#endif + +/* Check on the peripherals set 2 clock divider settings.*/ +#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC1 0 +#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified" +#endif + +/* Check on the peripherals set 3 clock divider settings.*/ +#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC2 0 +#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef enum { + SPC5_RUNMODE_TEST = 1, + SPC5_RUNMODE_SAFE = 2, + SPC5_RUNMODE_DRUN = 3, + SPC5_RUNMODE_RUN0 = 4, + SPC5_RUNMODE_RUN1 = 5, + SPC5_RUNMODE_RUN2 = 6, + SPC5_RUNMODE_RUN3 = 7, + SPC5_RUNMODE_HALT0 = 8, + SPC5_RUNMODE_STOP0 = 10 +} spc5_runmode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); + bool_t halSPCSetRunMode(spc5_runmode_t mode); + void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); +#if !SPC5_NO_INIT + uint32_t halSPCGetSystemClock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560BCxx/platform.mk b/os/hal/platforms/SPC560BCxx/platform.mk new file mode 100644 index 000000000..3432a7b16 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/platform.mk @@ -0,0 +1,11 @@ +# List of all the SPC560B/Cxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1 diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h new file mode 100644 index 000000000..ebcf5fef5 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -0,0 +1,300 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/spc560bc_registry.h + * @brief SPC560B/Cxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC560BC_REGISTRY_H_ +#define _SPC560BC_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC560B/Cxx capabilities + * @{ + */ +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA FALSE + +/* LINFlex attributes.*/ +#define SPC5_HAS_LINFLEX0 TRUE +#define SPC5_LINFLEX0_PCTL 48 +#define SPC5_LINFLEX0_RXI_HANDLER vector79 +#define SPC5_LINFLEX0_TXI_HANDLER vector80 +#define SPC5_LINFLEX0_ERR_HANDLER vector81 +#define SPC5_LINFLEX0_RXI_NUMBER 79 +#define SPC5_LINFLEX0_TXI_NUMBER 80 +#define SPC5_LINFLEX0_ERR_NUMBER 81 +#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX1 TRUE +#define SPC5_LINFLEX1_PCTL 49 +#define SPC5_LINFLEX1_RXI_HANDLER vector99 +#define SPC5_LINFLEX1_TXI_HANDLER vector100 +#define SPC5_LINFLEX1_ERR_HANDLER vector101 +#define SPC5_LINFLEX1_RXI_NUMBER 99 +#define SPC5_LINFLEX1_TXI_NUMBER 100 +#define SPC5_LINFLEX1_ERR_NUMBER 101 +#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX2 TRUE +#define SPC5_LINFLEX2_PCTL 50 +#define SPC5_LINFLEX2_RXI_HANDLER vector119 +#define SPC5_LINFLEX2_TXI_HANDLER vector120 +#define SPC5_LINFLEX2_ERR_HANDLER vector121 +#define SPC5_LINFLEX2_RXI_NUMBER 119 +#define SPC5_LINFLEX2_TXI_NUMBER 120 +#define SPC5_LINFLEX2_ERR_NUMBER 121 +#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX3 TRUE +#define SPC5_LINFLEX3_PCTL 51 +#define SPC5_LINFLEX3_RXI_HANDLER vector122 +#define SPC5_LINFLEX3_TXI_HANDLER vector123 +#define SPC5_LINFLEX3_ERR_HANDLER vector124 +#define SPC5_LINFLEX3_RXI_NUMBER 122 +#define SPC5_LINFLEX3_TXI_NUMBER 123 +#define SPC5_LINFLEX3_ERR_NUMBER 124 +#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_PCTL 68 +#define SPC5_SIUL_NUM_PORTS 8 +#define SPC5_SIUL_NUM_PCRS 123 +#define SPC5_SIUL_NUM_PADSELS 32 +#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122 + +/* eMIOS attributes.*/ +#define SPC5_HAS_EMIOS0 TRUE +#define SPC5_EMIOS0_PCTL 72 +#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141 +#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142 +#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143 +#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144 +#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145 +#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146 +#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147 +#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148 +#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149 +#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150 +#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151 +#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152 +#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153 +#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154 +#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141 +#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142 +#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143 +#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144 +#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145 +#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146 +#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147 +#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148 +#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149 +#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150 +#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151 +#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152 +#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153 +#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154 + +#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL3_CLK_DIV_VALUE / \ + SPC5_EMIOS0_GLOBAL_PRESCALER) + + +#define SPC5_HAS_EMIOS1 TRUE +#define SPC5_EMIOS1_PCTL 73 +#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157 +#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158 +#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159 +#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160 +#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161 +#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162 +#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163 +#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164 +#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165 +#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166 +#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167 +#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168 +#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169 +#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170 +#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157 +#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158 +#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159 +#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160 +#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161 +#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162 +#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163 +#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164 +#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165 +#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166 +#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167 +#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168 +#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169 +#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170 + +#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL3_CLK_DIV_VALUE / \ + SPC5_EMIOS1_GLOBAL_PRESCALER) + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 64 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73 +#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL); +#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL); + +#define SPC5_HAS_FLEXCAN1 TRUE +#define SPC5_FLEXCAN1_PCTL 17 +#define SPC5_FLEXCAN1_MB 64 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93 +#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL); +#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL); + +#define SPC5_HAS_FLEXCAN2 TRUE +#define SPC5_FLEXCAN2_PCTL 18 +#define SPC5_FLEXCAN2_MB 64 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113 +#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL); +#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL); + +#define SPC5_HAS_FLEXCAN3 TRUE +#define SPC5_FLEXCAN3_PCTL 19 +#define SPC5_FLEXCAN3_MB 64 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181 +#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL); +#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL); + +#define SPC5_HAS_FLEXCAN4 TRUE +#define SPC5_FLEXCAN4_PCTL 20 +#define SPC5_FLEXCAN4_MB 64 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198 +#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL); +#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL); + +#define SPC5_HAS_FLEXCAN5 TRUE +#define SPC5_FLEXCAN5_PCTL 21 +#define SPC5_FLEXCAN5_MB 64 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210 +#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL); +#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL); +/** @} */ + +#endif /* _SPC560BC_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560BCxx/typedefs.h b/os/hal/platforms/SPC560BCxx/typedefs.h new file mode 100644 index 000000000..5ab294e4b --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC560BCxx/xpc560bc.h b/os/hal/platforms/SPC560BCxx/xpc560bc.h new file mode 100644 index 000000000..4d7425165 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/xpc560bc.h @@ -0,0 +1,3769 @@ +/***************************************************************** + * + * FILE : MPC5604B_0M27V_0100.h + * + * DESCRIPTION : This is the header file describing the register + * set for: + * MPC5604B, mask set = 0M27V + * SPC560B4, mask set = FB50X20B + * + * COPYRIGHT :(c) 2009, Freescale & STMicroelectronics + * + * VERSION : 01.02 + * DATE : 08 MAY 2009 + * AUTHOR : b04629 + * HISTORY : Original source taken from jdp_0100.h. + * Updated to be compatable with + * - MPC5604B Mask ID 0M27V + * - MPC5604B Reference Manual Rev 3 Draft A + * - SPC560B4 Mask ID FB50X20B + * - SPC560B4 Reference Manual Rev 3 Draft A + * + ******************************************************************/ + +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/***************************************************************** +* Example instantiation and use: +* +* ..B. = 1; +* ..R = 0x10000000; +* +******************************************************************/ + +#ifndef _MPC5604B_H_ +#define _MPC5604B_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { + +#endif /* + */ + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif /* + */ +/****************************************************************************/ +/* MODULE : ADC */ +/****************************************************************************/ + struct ADC_tag { + + union { + vuint32_t R; + struct { + vuint32_t OWREN:1; + vuint32_t WLSIDE:1; + vuint32_t MODE:1; + vuint32_t:4; + vuint32_t NSTART:1; + vuint32_t:1; + vuint32_t JTRGEN:1; + vuint32_t JEDGE:1; + vuint32_t JSTART:1; + vuint32_t:2; + vuint32_t CTUEN:1; + vuint32_t:8; + vuint32_t ADCLKSEL:1; + vuint32_t ABORTCHAIN:1; + vuint32_t ABORT:1; + vuint32_t ACK0:1; + vuint32_t:4; + vuint32_t PWDN:1; + } B; + } MCR; /* MAIN CONFIGURATION REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t NSTART:1; + vuint32_t JABORT:1; + vuint32_t:2; + vuint32_t JSTART:1; + vuint32_t:3; + vuint32_t CTUSTART:1; + vuint32_t CHADDR:7; + vuint32_t:3; + vuint32_t ACK0:1; + vuint32_t:2; + vuint32_t ADCSTATUS:3; + } B; + } MSR; /* MAIN STATUS REGISTER */ + + int32_t ADC_reserved1[2]; /* (0x010 - 0x008)/4 = 0x02 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t EOCTU:1; + vuint32_t JEOC:1; + vuint32_t JECH:1; + vuint32_t EOC:1; + vuint32_t ECH:1; + } B; + } ISR; /* INTERRUPT STATUS REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t EOC_CH31:1; + vuint32_t EOC_CH30:1; + vuint32_t EOC_CH29:1; + vuint32_t EOC_CH28:1; + vuint32_t EOC_CH27:1; + vuint32_t EOC_CH26:1; + vuint32_t EOC_CH25:1; + vuint32_t EOC_CH24:1; + vuint32_t EOC_CH23:1; + vuint32_t EOC_CH22:1; + vuint32_t EOC_CH21:1; + vuint32_t EOC_CH20:1; + vuint32_t EOC_CH19:1; + vuint32_t EOC_CH18:1; + vuint32_t EOC_CH17:1; + vuint32_t EOC_CH16:1; + vuint32_t EOC_CH15:1; + vuint32_t EOC_CH14:1; + vuint32_t EOC_CH13:1; + vuint32_t EOC_CH12:1; + vuint32_t EOC_CH11:1; + vuint32_t EOC_CH10:1; + vuint32_t EOC_CH9:1; + vuint32_t EOC_CH8:1; + vuint32_t EOC_CH7:1; + vuint32_t EOC_CH6:1; + vuint32_t EOC_CH5:1; + vuint32_t EOC_CH4:1; + vuint32_t EOC_CH3:1; + vuint32_t EOC_CH2:1; + vuint32_t EOC_CH1:1; + vuint32_t EOC_CH0:1; + } B; + } CEOCFR[3]; /* Channel Pending Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t MSKEOCTU:1; + vuint32_t MSKJEOC:1; + vuint32_t MSKJECH:1; + vuint32_t MSKEOC:1; + vuint32_t MSKECH:1; + } B; + } IMR; /* INTERRUPT MASK REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t CIM31:1; + vuint32_t CIM30:1; + vuint32_t CIM29:1; + vuint32_t CIM28:1; + vuint32_t CIM27:1; + vuint32_t CIM26:1; + vuint32_t CIM25:1; + vuint32_t CIM24:1; + vuint32_t CIM23:1; + vuint32_t CIM22:1; + vuint32_t CIM21:1; + vuint32_t CIM20:1; + vuint32_t CIM19:1; + vuint32_t CIM18:1; + vuint32_t CIM17:1; + vuint32_t CIM16:1; + vuint32_t CIM15:1; + vuint32_t CIM14:1; + vuint32_t CIM13:1; + vuint32_t CIM12:1; + vuint32_t CIM11:1; + vuint32_t CIM10:1; + vuint32_t CIM9:1; + vuint32_t CIM8:1; + vuint32_t CIM7:1; + vuint32_t CIM6:1; + vuint32_t CIM5:1; + vuint32_t CIM4:1; + vuint32_t CIM3:1; + vuint32_t CIM2:1; + vuint32_t CIM1:1; + vuint32_t CIM0:1; + } B; + } CIMR[3]; /* Channel Interrupt Mask Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t WDG3H:1; + vuint32_t WDG2H:1; + vuint32_t WDG1H:1; + vuint32_t WDG0H:1; + vuint32_t WDG3L:1; + vuint32_t WDG2L:1; + vuint32_t WDG1L:1; + vuint32_t WDG0L:1; + } B; + } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t MSKWDG3H:1; + vuint32_t MSKWDG2H:1; + vuint32_t MSKWDG1H:1; + vuint32_t MSKWDG0H:1; + vuint32_t MSKWDG3L:1; + vuint32_t MSKWDG2L:1; + vuint32_t MSKWDG1L:1; + vuint32_t MSKWDG0L:1; + } B; + } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER */ + + int32_t ADC_reserved2[6]; /* (0x050 - 0x038)/4 = 0x06 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t THREN:1; + vuint32_t THRINV:1; + vuint32_t:7; + vuint32_t THRCH:7; + } B; + } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRHLR[4]; /* THRESHOLD REGISTER */ + + int32_t ADC_reserved3[4]; /* (0x080 - 0x070)/4 = 0x04 */ + + union { + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t PREVAL2:2; + vuint32_t PREVAL1:2; + vuint32_t PREVAL0:2; + vuint32_t PRECONV:1; + } B; + } PSCR; /* PRESAMPLING CONTROL REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t PRES31:1; + vuint32_t PRES30:1; + vuint32_t PRES29:1; + vuint32_t PRES28:1; + vuint32_t PRES27:1; + vuint32_t PRES26:1; + vuint32_t PRES25:1; + vuint32_t PRES24:1; + vuint32_t PRES23:1; + vuint32_t PRES22:1; + vuint32_t PRES21:1; + vuint32_t PRES20:1; + vuint32_t PRES19:1; + vuint32_t PRES18:1; + vuint32_t PRES17:1; + vuint32_t PRES16:1; + vuint32_t PRES15:1; + vuint32_t PRES14:1; + vuint32_t PRES13:1; + vuint32_t PRES12:1; + vuint32_t PRES11:1; + vuint32_t PRES10:1; + vuint32_t PRES9:1; + vuint32_t PRES8:1; + vuint32_t PRES7:1; + vuint32_t PRES6:1; + vuint32_t PRES5:1; + vuint32_t PRES4:1; + vuint32_t PRES3:1; + vuint32_t PRES2:1; + vuint32_t PRES1:1; + vuint32_t PRES0:1; + } B; + } PSR[3]; /* PRESAMPLING REGISTER */ + + int32_t ADC_reserved4[1]; /* (0x094 - 0x090)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; + vuint32_t:4; + vuint32_t INPCMP:2; + vuint32_t:1; + vuint32_t INPSAMP:8; + } B; + } CTR[3]; /* CONVERSION TIMING REGISTER */ + + int32_t ADC_reserved5[1]; /* (0x0A4 - 0x0A0)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t CH31:1; + vuint32_t CH30:1; + vuint32_t CH29:1; + vuint32_t CH28:1; + vuint32_t CH27:1; + vuint32_t CH26:1; + vuint32_t CH25:1; + vuint32_t CH24:1; + vuint32_t CH23:1; + vuint32_t CH22:1; + vuint32_t CH21:1; + vuint32_t CH20:1; + vuint32_t CH19:1; + vuint32_t CH18:1; + vuint32_t CH17:1; + vuint32_t CH16:1; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER */ + + int32_t ADC_reserved6[1]; /* (0x0B4 - 0x0B0)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t CH31:1; + vuint32_t CH30:1; + vuint32_t CH29:1; + vuint32_t CH28:1; + vuint32_t CH27:1; + vuint32_t CH26:1; + vuint32_t CH25:1; + vuint32_t CH24:1; + vuint32_t CH23:1; + vuint32_t CH22:1; + vuint32_t CH21:1; + vuint32_t CH20:1; + vuint32_t CH19:1; + vuint32_t CH18:1; + vuint32_t CH17:1; + vuint32_t CH16:1; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } JCMR[3]; /* Injected CONVERSION MASK REGISTER */ + + int32_t ADC_reserved7[1]; /* (0x0C4 - 0x0C0)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t DSD:8; + } B; + } DSDR; /* DECODE SIGNALS DELAY REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t PDED:8; + } B; + } PDEDR; /* POWER DOWN DELAY REGISTER */ + + int32_t ADC_reserved8[13]; /* (0x100 - 0x0CC)/4 = 0x0D */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t VALID:1; + vuint32_t OVERW:1; + vuint32_t RESULT:2; + vuint32_t:6; + vuint32_t CDATA:10; + } B; + } CDR[96]; /* Channel 0-95 Data REGISTER */ + + }; /* end of ADC_tag */ +/****************************************************************************/ +/* MODULE : CANSP */ +/****************************************************************************/ + struct CANSP_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RX_COMPLETE:1; + vuint32_t BUSY:1; + vuint32_t ACTIVE_CK:1; + vuint32_t:3; + vuint32_t MODE:1; + vuint32_t CAN_RX_SEL:3; + vuint32_t BRP:5; + vuint32_t CAN_SMPLR_EN:1; + } B; + } CR; /* CANSP Control Register */ + + union { + vuint32_t R; + } SR[12]; /* CANSP Sample Register 0 to 11 */ + + }; /* end of CANSP_tag */ +/****************************************************************************/ +/* MODULE : CFLASH */ +/****************************************************************************/ + struct CFLASH_tag { + union { /* Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:1; + vuint32_t:1; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* LML Register */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:2; + vuint32_t MLK:2; + vuint32_t LLK:16; + } B; + } LML; + + union { /* HBL Register */ + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t:23; + vuint32_t HBLOCK:8; + } B; + } HBL; + + union { /* SLML Register */ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:2; + vuint32_t SMK:2; + vuint32_t SLK:16; + } B; + } SLL; + + union { /* LMS Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; + vuint32_t LSL:16; + } B; + } LMS; + + union { /* High Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HSL:6; + } B; + } HBS; + + union { /* Address Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t ADD:19; + vuint32_t:3; + } B; + } ADR; + + union { /* CFLASH Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t BK0_APC:5; + vuint32_t BK0_WWSC:5; + vuint32_t BK0_RWSC:5; + vuint32_t BK0_RWWC2:1; + vuint32_t BK0_RWWC1:1; + vuint32_t B0_P1_BCFG:2; + vuint32_t B0_P1_DPFE:1; + vuint32_t B0_P1_IPFE:1; + vuint32_t B0_P1_PFLM:2; + vuint32_t B0_P1_BFE:1; + vuint32_t BK0_RWWC0:1; + vuint32_t B0_P0_BCFG:2; + vuint32_t B0_P0_DPFE:1; + vuint32_t B0_P0_IPFE:1; + vuint32_t B0_P0_PFLM:2; + vuint32_t B0_P0_BFE:1; + } B; + } PFCR0; + + union { /* CFLASH Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t BK1_APC:5; + vuint32_t BK1_WWSC:5; + vuint32_t BK1_RWSC:5; + vuint32_t BK1_RWWC2:1; + vuint32_t BK1_RWWC1:1; + vuint32_t:6; + vuint32_t B0_P1_BFE:1; + vuint32_t BK1_RWWC0:1; + vuint32_t:6; + vuint32_t B1_P0_BFE:1; + } B; + } PFCR1; + + union { /* cflash Access Protection Register */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t ARBM:2; + vuint32_t M7PFD:1; + vuint32_t M6PFD:1; + vuint32_t M5PFD:1; + vuint32_t M4PFD:1; + vuint32_t M3PFD:1; + vuint32_t M2PFD:1; + vuint32_t M1PFD:1; + vuint32_t M0PFD:1; + vuint32_t M7AP:2; + vuint32_t M6AP:2; + vuint32_t M5AP:2; + vuint32_t M4AP:2; + vuint32_t M3AP:2; + vuint32_t M2AP:2; + vuint32_t M1AP:2; + vuint32_t M0AP:2; + } B; + } FAPR; + + int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */ + + union { /* User Test Register 0 */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test Register 1 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test Register 2 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-4 */ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + }; /* end of CFLASH_tag */ +/****************************************************************************/ +/* MODULE : CGM */ +/****************************************************************************/ + struct CGM_tag { + + /* The CGM provides a unified register interface, enabling access to + + all clock sources: + + Base Address | Clock Sources + + ----------------------------- + + 0xC3FE0000 | FXOSC_CTL + + ---------- | Reserved + + 0xC3FE0040 | SXOSC_CTL + + 0xC3FE0060 | FIRC_CTL + + 0xC3FE0080 | SIRC_CTL + + 0xC3FE00A0 | FMPLL_0 + + ---------- | Reserved + + 0xC3FE0100 | CMU_0 + + */ + /************************************/ + /* FXOSC_CTL @ CGM base address + 0x0000 */ + /************************************/ + union { + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t:7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t:2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t:7; + } B; + } FXOSC_CTL; /* Fast OSC Control Register */ + + /************************************/ + /* SXOSC_CTL @ CGM base address + 0x0040 */ + /************************************/ + int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */ + + union { + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t:7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t:2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t:5; + vuint32_t S_OSC:1; + vuint32_t OSCON:1; + } B; + } SXOSC_CTL; /* Slow OSC Control Register */ + + /************************************/ + /* FIRC_CTL @ CGM base address + 0x0060 */ + /************************************/ + int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */ + + union { + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t RCTRIM:6; + vuint32_t:3; + vuint32_t RCDIV:5; + vuint32_t:8; + } B; + } FIRC_CTL; /* Fast IRC Control Register */ + + /****************************************/ + /* SIRC_CTL @ CGM base address + 0x0080 */ + /****************************************/ + int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */ + + union { + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t RCTRIM:5; + vuint32_t:3; + vuint32_t RCDIV:5; + vuint32_t:3; + vuint32_t S_SIRC:1; + vuint32_t:3; + vuint32_t SIRCON_STDBY:1; + } B; + } SIRC_CTL; /* Slow IRC Control Register */ + + /*************************************/ + /* FMPLL @ CGM base address + 0x00A0 */ + /*************************************/ + int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t IDF:4; + vuint32_t ODF:2; + vuint32_t:1; + vuint32_t NDIV:7; + vuint32_t:7; + vuint32_t EN_PLL_SW:1; + vuint32_t MODE:1; + vuint32_t UNLOCK_ONCE:1; + vuint32_t:1; + vuint32_t I_LOCK:1; + vuint32_t S_LOCK:1; + vuint32_t PLL_FAIL_MASK:1; + vuint32_t PLL_FAIL_FLAG:1; + vuint32_t:1; + } B; + } FMPLL_CR; /* FMPLL Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t STRB_BYPASS:1; + vuint32_t:1; + vuint32_t SPRD_SEL:1; + vuint32_t MOD_PERIOD:13; + vuint32_t FM_EN:1; + vuint32_t INC_STEP:15; + } B; + } FMPLL_MR; /* FMPLL Modulation Register */ + + /************************************/ + /* CMU @ CGM base address + 0x0100 */ + /************************************/ + int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SFM:1; + vuint32_t:13; + vuint32_t CLKSEL1:2; + vuint32_t:5; + vuint32_t RCDIV:2; + vuint32_t CME_A:1; + } B; + } CMU_CSR; /* Control Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t FD:20; + } B; + } CMU_FDR; /* Frequency Display Register */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t HFREF_A:12; + } B; + } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t LFREF_A:12; + } B; + } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t FLCI_A:1; + vuint32_t FHHI_A:1; + vuint32_t FLLI_A:1; + vuint32_t OLRI:1; + } B; + } CMU_ISR; /* Interrupt Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } CMU_IMR; /* Interrupt Mask Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t MD:20; + } B; + } CMU_MDR; /* Measurement Duration Register */ + + /************************************/ + /* CGM General Registers @ CGM base address + 0x0370 */ + /************************************/ + int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t EN:1; + } B; + } OC_EN; /* Output Clock Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t SELDIV:2; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } OCDS_SC; /* Output Clock Division Select Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELSTAT:4; + vuint32_t:24; + } B; + } SC_SS; /* System Clock Select Status */ + + union { + vuint8_t R; + struct { + vuint8_t DE:1; + vuint8_t:3; + vuint8_t DIV:4; + } B; + } SC_DC[3]; /* System Clock Divider Configuration 0->2 */ + + }; /* end of CGM_tag */ +/****************************************************************************/ +/* MODULE : CTU */ +/****************************************************************************/ + struct CTU_tag { + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t TRGIEN:1; + vuint32_t TRGI:1; + vuint32_t:6; + } B; + } CSR; /* Control Status Register */ + + int32_t CTU_reserved0[11]; /* (0x030 - 0x004)/4 = 0x0B */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TM:1; + vuint32_t:7; + vuint32_t CLR_FLAG:1; + vuint32_t:1; + vuint32_t CHANNELVALUE:6; + } B; + } EVTCFGR[64]; /* Event Configuration Register */ + + }; /* end of CTU_tag */ +/****************************************************************************/ +/* MODULE : DFLASH */ +/****************************************************************************/ + struct DFLASH_tag { + union { /* Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:1; + vuint32_t:1; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* LML Register */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:2; + vuint32_t MLK:2; + vuint32_t LLK:16; + } B; + } LML; + + union { /* HBL Register */ + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t:23; + vuint32_t HBLOCK:8; + } B; + } HBL; + + union { /* SLML Register */ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:2; + vuint32_t SMK:2; + vuint32_t SLK:16; + } B; + } SLL; + + union { /* LMS Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; + vuint32_t LSL:16; + } B; + } LMS; + + union { /* High Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HSL:6; + } B; + } HBS; + + union { /* Address Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t ADD:19; + vuint32_t:3; + } B; + } ADR; + + int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */ + + union { /* User Test Register 0 */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test Register 1 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test Register 2 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-4 */ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + }; /* end of Dflash_tag */ +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t:2; + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t DOZE:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:7; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; + vuint32_t:16; + } B; + } TCR; + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; + vuint32_t:2; + vuint32_t EOQFRE:1; + vuint32_t TFUFRE:1; + vuint32_t:1; + vuint32_t TFFFRE:1; + vuint32_t TFFFDIRS:1; + vuint32_t:4; + vuint32_t RFOFRE:1; + vuint32_t:1; + vuint32_t RFDFRE:1; + vuint32_t RFDFDIRS:1; + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t:4; + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + vuint32_t DSPI_reserved_txf[12]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t:1; + vuint32_t MTOCNT:6; + vuint32_t:4; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:6; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; /* end of DSPI_tag */ +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + union { + vuint16_t R; + } PCT; /* ECSM Processor Core Type Register */ + + union { + vuint16_t R; + } REV; /* ECSM Revision Register */ + + int32_t ECSM_reserved1; + + union { + vuint32_t R; + } IMC; /* ECSM IPS Module Configuration Register */ + + int8_t ECSM_reserved2[7]; + + union { + vuint8_t R; + struct { + vuint8_t ENBWCR:1; + vuint8_t:3; + vuint8_t PRILVL:4; + } B; + } MWCR; /* ECSM Miscellaneous Wakeup Control Register */ + + int32_t ECSM_reserved3[2]; + int8_t ECSM_reserved4[3]; + + union { + vuint8_t R; + struct { + vuint8_t FB0AI:1; + vuint8_t FB0SI:1; + vuint8_t FB1AI:1; + vuint8_t FB1SI:1; + vuint8_t:4; + } B; + } MIR; /* ECSM Miscellaneous Interrupt Register */ + + int32_t ECSM_reserved5; + + union { + vuint32_t R; + } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */ + + int32_t ECSM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */ + int8_t ECSM_reserved7[3]; + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t ER1BR:1; + vuint8_t EF1BR:1; + vuint8_t:2; + vuint8_t ERNCR:1; + vuint8_t EFNCR:1; + } B; + } ECR; /* ECSM ECC Configuration Register */ + + int8_t ECSM_reserved8[3]; + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t R1BC:1; + vuint8_t F1BC:1; + vuint8_t:2; + vuint8_t RNCE:1; + vuint8_t FNCE:1; + } B; + } ESR; /* ECSM ECC Status Register */ + + int16_t ECSM_reserved9; + + union { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t FRC1BI:1; + vuint16_t FR11BI:1; + vuint16_t:2; + vuint16_t FRCNCI:1; + vuint16_t FR1NCI:1; + vuint16_t:1; + vuint16_t ERRBIT:7; + } B; + } EEGR; /* ECSM ECC Error Generation Register */ + + int32_t ECSM_reserved10; + + union { + vuint32_t R; + } FEAR; /* ECSM Flash ECC Address Register */ + + int16_t ECSM_reserved11; + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; + } B; + } FEMR; /* ECSM Flash ECC Master Number Register */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } FEAT; /* ECSM Flash ECC Attributes Register */ + + int32_t ECSM_reserved12; + + union { + vuint32_t R; + } FEDR; /* ECSM Flash ECC Data Register */ + + union { + vuint32_t R; + } REAR; /* ECSM RAM ECC Address Register */ + + int8_t ECSM_reserved13; + + union { + vuint8_t R; + } RESR; /* ECSM RAM ECC Address Register */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; + } B; + } REMR; /* ECSM RAM ECC Master Number Register */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } REAT; /* ECSM RAM ECC Attributes Register */ + + int32_t ECSM_reserved14; + + union { + vuint32_t R; + } REDR; /* ECSM RAM ECC Data Register */ + + }; /* end of ECSM_tag */ +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_CHANNEL_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CADR:16; + } B; + } CADR; /* Channel A Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CBDR:16; + } B; + } CBDR; /* Channel B Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CCNTR:16; + } B; + } CCNTR; /* Channel Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPEN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + vuint32_t R; /* Alternate Channel A Data Register */ + } ALTCADR; + + uint32_t emios_channel_reserved[2]; + + }; /* end of EMIOS_CHANNEL_tag */ + + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t F27:1; + vuint32_t F26:1; + vuint32_t F25:1; + vuint32_t F24:1; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t OU27:1; + vuint32_t OU26:1; + vuint32_t OU25:1; + vuint32_t OU24:1; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CHDIS27:1; + vuint32_t CHDIS26:1; + vuint32_t CHDIS25:1; + vuint32_t CHDIS24:1; + vuint32_t CHDIS23:1; + vuint32_t CHDIS22:1; + vuint32_t CHDIS21:1; + vuint32_t CHDIS20:1; + vuint32_t CHDIS19:1; + vuint32_t CHDIS18:1; + vuint32_t CHDIS17:1; + vuint32_t CHDIS16:1; + vuint32_t CHDIS15:1; + vuint32_t CHDIS14:1; + vuint32_t CHDIS13:1; + vuint32_t CHDIS12:1; + vuint32_t CHDIS11:1; + vuint32_t CHDIS10:1; + vuint32_t CHDIS9:1; + vuint32_t CHDIS8:1; + vuint32_t CHDIS7:1; + vuint32_t CHDIS6:1; + vuint32_t CHDIS5:1; + vuint32_t CHDIS4:1; + vuint32_t CHDIS3:1; + vuint32_t CHDIS2:1; + vuint32_t CHDIS1:1; + vuint32_t CHDIS0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CHANNEL_tag CH[28]; + + }; /* end of EMIOS_tag */ +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + vuint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + vuint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAKMSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t SLFWAK:1; + vuint32_t WRNEN:1; + vuint32_t LPMACK:1; + vuint32_t WAKSRC:1; + vuint32_t DOZE:1; + vuint32_t SRXDIS:1; + vuint32_t BCC:1; + vuint32_t:2; + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t:1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */ + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : i2c */ +/****************************************************************************/ + struct I2C_tag { + union { + vuint8_t R; + struct { + vuint8_t ADR:7; + vuint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + vuint8_t R; + struct { + vuint8_t IBC:8; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + vuint8_t R; + struct { + vuint8_t MDIS:1; + vuint8_t IBIE:1; + vuint8_t MS:1; + vuint8_t TX:1; + vuint8_t NOACK:1; + vuint8_t RSTA:1; + vuint8_t DMAEN:1; + vuint8_t IBDOZE:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + vuint8_t R; + struct { + vuint8_t TCF:1; + vuint8_t IAAS:1; + vuint8_t IBB:1; + vuint8_t IBAL:1; + vuint8_t:1; + vuint8_t SRW:1; + vuint8_t IBIF:1; + vuint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + vuint8_t R; + struct { + vuint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + vuint8_t R; + struct { + vuint8_t BIIE:1; + vuint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; /* end of I2C_tag */ +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t VTES:1; + vuint32_t:4; + vuint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; + vuint32_t INTVEC:9; + vuint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t SET:1; + vuint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PRI:4; + } B; + } PSR[512]; /* Software Set/Clear Interrupt Register */ + + }; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : LINFLEX */ +/****************************************************************************/ + + struct LINFLEX_tag { + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CCD:1; + vuint32_t CFD:1; + vuint32_t LASE:1; + vuint32_t AWUM:1; + vuint32_t MBL:4; + vuint32_t BF:1; + vuint32_t SLFM:1; + vuint32_t LBKM:1; + vuint32_t MME:1; + vuint32_t SBDT:1; + vuint32_t RBLM:1; + vuint32_t SLEEP:1; + vuint32_t INIT:1; + } B; + } LINCR1; /* LINFLEX LIN Control Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZIE:1; + vuint32_t OCIE:1; + vuint32_t BEIE:1; + vuint32_t CEIE:1; + vuint32_t HEIE:1; + vuint32_t:2; + vuint32_t FEIE:1; + vuint32_t BOIE:1; + vuint32_t LSIE:1; + vuint32_t WUIE:1; + vuint32_t DBFIE:1; + vuint32_t DBEIE:1; + vuint32_t DRIE:1; + vuint32_t DTIE:1; + vuint32_t HRIE:1; + } B; + } LINIER; /* LINFLEX LIN Interrupt Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t LINS:4; + vuint32_t:2; + vuint32_t RMB:1; + vuint32_t:1; + vuint32_t RBSY:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t DBFF:1; + vuint32_t DBEF:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t HRF:1; + } B; + } LINSR; /* LINFLEX LIN Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t BEF:1; + vuint32_t CEF:1; + vuint32_t SFEF:1; + vuint32_t SDEF:1; + vuint32_t IDPEF:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t:6; + vuint32_t NF:1; + } B; + } LINESR; /* LINFLEX LIN Error Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:1; + vuint32_t TDFL:2; + vuint32_t:1; + vuint32_t RDFL:2; + vuint32_t:4; + vuint32_t RXEN:1; + vuint32_t TXEN:1; + vuint32_t OP:1; + vuint32_t PCE:1; + vuint32_t WL:1; + vuint32_t UART:1; + } B; + } UARTCR; /* LINFLEX UART Mode Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t PE:4; + vuint32_t RMB:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t:2; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t NF:1; + } B; + } UARTSR; /* LINFLEX UART Mode Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:5; + vuint32_t LTOM:1; + vuint32_t IOT:1; + vuint32_t TOCE:1; + vuint32_t CNT:8; + } B; + } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t OC2:8; + vuint32_t OC1:8; + } B; + } LINOCR; /* LINFLEX LIN Output Compare Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:4; + vuint32_t RTO:4; + vuint32_t:1; + vuint32_t HTO:7; + } B; + } LINTOCR; /* LINFLEX LIN Output Compare Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:12; + vuint32_t DIV_F:4; + } B; + } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:3; + vuint32_t DIV_M:13; + } B; + } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:8; + vuint32_t CF:8; + } B; + } LINCFR; /* LINFLEX LIN Checksum Field Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:1; + vuint32_t IOBE:1; + vuint32_t IOPE:1; + vuint32_t WURQ:1; + vuint32_t DDRQ:1; + vuint32_t DTRQ:1; + vuint32_t ABRQ:1; + vuint32_t HTRQ:1; + vuint32_t:8; + } B; + } LINCR2; /* LINFLEX LIN Control Register 2 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } BIDR; /* LINFLEX Buffer Identifier Register */ + + union { + vuint32_t R; + struct { + vuint32_t DATA3:8; + vuint32_t DATA2:8; + vuint32_t DATA1:8; + vuint32_t DATA0:8; + } B; + } BDRL; /* LINFLEX Buffer Data Register Least Significant */ + + union { + vuint32_t R; + struct { + vuint32_t DATA7:8; + vuint32_t DATA6:8; + vuint32_t DATA5:8; + vuint32_t DATA4:8; + } B; + } BDRM; /* LINFLEX Buffer Data Register Most Significant */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:8; + vuint32_t FACT:8; + } B; + } IFER; /* LINFLEX Identifier Filter Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:12; + vuint32_t IFMI:4; + } B; + } IFMI; /* LINFLEX Identifier Filter Match Index Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:12; + vuint32_t IFM:4; + } B; + } IFMR; /* LINFLEX Identifier Filter Mode Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:3; + vuint32_t DFL:3; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } IFCR[16]; /* LINFLEX Identifier Filter Control Register 0-15 */ + + }; /* end of LINFLEX_tag */ +/****************************************************************************/ +/* MODULE : ME */ +/****************************************************************************/ + struct ME_tag { + + union { + vuint32_t R; + struct { + vuint32_t S_CURRENTMODE:4; + vuint32_t S_MTRANS:1; + vuint32_t S_DC:1; + vuint32_t:2; + vuint32_t S_PDO:1; + vuint32_t:2; + vuint32_t S_MVR:1; + vuint32_t S_DFLA:2; + vuint32_t S_CFLA:2; + vuint32_t:9; + vuint32_t S_FMPLL:1; + vuint32_t S_FXOSC:1; + vuint32_t S_FIRC:1; + vuint32_t S_SYSCLK:4; + } B; + } GS; /* Global Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t TARGET_MODE:4; + vuint32_t:12; + vuint32_t KEY:16; + } B; + } MCTL; /* Mode Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STANDBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } MER; /* Mode Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t I_CONF:1; + vuint32_t I_MODE:1; + vuint32_t I_SAFE:1; + vuint32_t I_MTC:1; + } B; + } IS; /* Interrupt Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t M_CONF:1; + vuint32_t M_MODE:1; + vuint32_t M_SAFE:1; + vuint32_t M_MTC:1; + } B; + } IM; /* Interrupt Mask Register */ + + union { + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t S_MTI:1; + vuint32_t S_MRI:1; + vuint32_t S_DMA:1; + vuint32_t S_NMA:1; + vuint32_t S_SEA:1; + } B; + } IMTS; /* Invalid Mode Transition Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t MPH_BUSY:1; + vuint32_t:2; + vuint32_t PMC_PROG:1; + vuint32_t CORE_DBG:1; + vuint32_t:2; + vuint32_t SMR:1; + vuint32_t:1; + vuint32_t FMPLL_SC:1; + vuint32_t FXOSC_SC:1; + vuint32_t FIRC_SC:1; + vuint32_t:1; + vuint32_t SYSCLK_SW:1; + vuint32_t DFLASH_SC:1; + vuint32_t CFLASH_SC:1; + vuint32_t CDP_PRPH_0_143:1; + vuint32_t:3; + vuint32_t CDP_PRPH_96_127:1; + vuint32_t CDP_PRPH_64_95:1; + vuint32_t CDP_PRPH_32_63:1; + vuint32_t CDP_PRPH_0_31:1; + } B; + } DMTS; /* Invalid Mode Transition Status Register */ + + int32_t ME_reserved0; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } RESET; /* Reset Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } TEST; /* Test Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } SAFE; /* Safe Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } DRUN; /* DRUN Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } RUN[4]; /* RUN 0->4 Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } HALT0; /* HALT0 Mode Configuration Register */ + + int32_t ME_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } STOP0; /* STOP0 Mode Configuration Register */ + + int32_t ME_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:9; + vuint32_t FMPLLON:1; + vuint32_t FXOSC0ON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } STANDBY0; /* STANDBY0 Mode Configuration Register */ + + int32_t ME_reserved3[2]; + + union { + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t S_FLEXCAN5:1; + vuint32_t S_FLEXCAN4:1; + vuint32_t S_FLEXCAN3:1; + vuint32_t S_FLEXCAN2:1; + vuint32_t S_FLEXCAN1:1; + vuint32_t S_FLEXCAN0:1; + vuint32_t:9; + vuint32_t S_DSPI2:1; + vuint32_t S_DSPI1:1; + vuint32_t S_DSPI0:1; + vuint32_t:4; + } B; + } PS0; /* Peripheral Status Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t S_CANSAMPLER:1; + vuint32_t:2; + vuint32_t S_CTU:1; + vuint32_t:5; + vuint32_t S_LINFLEX3:1; + vuint32_t S_LINFLEX2:1; + vuint32_t S_LINFLEX1:1; + vuint32_t S_LINFLEX0:1; + vuint32_t:3; + vuint32_t S_I2C:1; + vuint32_t:11; + vuint32_t S_ADC:1; + } B; + } PS1; /* Peripheral Status Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t S_PIT_RTI:1; + vuint32_t S_RTC_API:1; + vuint32_t:18; + vuint32_t S_EMIOS:1; + vuint32_t:2; + vuint32_t S_WKUP:1; + vuint32_t S_SIU:1; + vuint32_t:4; + } B; + } PS2; /* Peripheral Status Register 2 */ + + union { + vuint32_t R; + struct { + vuint32_t:23; + vuint32_t S_CMU:1; + vuint32_t:8; + } B; + } PS3; /* Peripheral Status Register 3 */ + + int32_t ME_reserved4[4]; + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */ + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STANDBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t:8; + } B; + } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t DBG_F:1; + vuint8_t LP_CFG:3; + vuint8_t RUN_CFG:3; + } B; + } PCTL[144]; /* Peripheral Control 0->143 Register */ + + }; /* end of ME_tag */ +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + struct MPU_tag { + union { + vuint32_t R; + struct { + vuint32_t SPERR:8; + vuint32_t:4; + vuint32_t HRL:4; + vuint32_t NSP:4; + vuint32_t NGRD:4; + vuint32_t:7; + vuint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */ + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR0; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR0; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR1; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR1; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR2; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR2; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR3; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR3; + + uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t SRTADDR:27; + vuint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + vuint32_t R; + struct { + vuint32_t ENDADDR:27; + vuint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + vuint32_t R; + struct { + vuint32_t PID:8; + vuint32_t PIDMASK:8; + vuint32_t:15; + vuint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */ + + union { + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + + }; /* end of MPU_tag */ +/****************************************************************************/ +/* MODULE : PCU */ +/****************************************************************************/ + struct PCU_tag { + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RST:1; + } B; + } PCONF[3]; /* Power domain 0-2 configuration register */ + + int32_t PCU_reserved0[13]; /* (0x040 - 0x00C)/4 = 0x0D */ + + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t PD2:1; + vuint32_t PD1:1; + vuint32_t PD0:1; + } B; + } PSTAT; /* Power Domain Status Register */ + + int32_t PCU_reserved1[15]; /* {0x0080-0x0044}/0x4 = 0xF */ + + union { + vuint32_t R; + struct { + vuint32_t:15; + vuint32_t MASK_LVDHV5:1; + } B; + } VCTL; /* Voltage Regulator Control Register */ + + }; /* end of PCU_tag */ +/****************************************************************************/ +/* MODULE : pit */ +/****************************************************************************/ + struct PIT_tag { + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; + + uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t TSV:32; + } B; + } LDVAL; + + union { + vuint32_t R; + struct { + vuint32_t TVL:32; + } B; + } CVAL; + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; + } CH[6]; + + }; /* end of PIT_tag */ +/****************************************************************************/ +/* MODULE : RGM */ +/****************************************************************************/ + struct RGM_tag { + + union { + vuint16_t R; + struct { + vuint16_t F_EXR:1; + vuint16_t:6; + vuint16_t F_FLASH:1; + vuint16_t F_LVD45:1; + vuint16_t F_CMU_FHL:1; + vuint16_t F_CMU_OLR:1; + vuint16_t F_FMPLL:1; + vuint16_t F_CHKSTOP:1; + vuint16_t F_SOFT:1; + vuint16_t F_CORE:1; + vuint16_t F_JTAG:1; + } B; + } FES; /* Functional Event Status */ + + union { + vuint16_t R; + struct { + vuint16_t F_POR:1; + vuint16_t:11; + vuint16_t F_LVD27:1; + vuint16_t F_SWT:1; + vuint16_t F_LVD12_PD1:1; + vuint16_t F_LVD12_PD0:1; + } B; + } DES; /* Destructive Event Status */ + + union { + vuint16_t R; + struct { + vuint16_t D_EXR:1; + vuint16_t:6; + vuint16_t D_FLASH:1; + vuint16_t D_LVD45:1; + vuint16_t D_CMU_FHL:1; + vuint16_t D_CMU_OLR:1; + vuint16_t D_FMPLL:1; + vuint16_t D_CHKSTOP:1; + vuint16_t D_SOFT:1; + vuint16_t D_CORE:1; + vuint16_t D_JTAG:1; + } B; + } FERD; /* Functional Event Reset Disable */ + + union { + vuint16_t R; + struct { + vuint16_t D_POR:1; + vuint16_t:11; + vuint16_t D_LVD27:1; + vuint16_t D_SWT:1; + vuint16_t D_LVD12_PD1:1; + vuint16_t D_LVD12_PD0:1; + } B; + } DERD; /* Destructive Event Reset Disable */ + + int16_t RGM_reserved0[4]; + + union { + vuint16_t R; + struct { + vuint16_t AR_EXR:1; + vuint16_t:6; + vuint16_t AR_FLASH:1; + vuint16_t AR_LVD45:1; + vuint16_t AR_CMU_FHL:1; + vuint16_t AR_CMU_OLR:1; + vuint16_t AR_FMPLL:1; + vuint16_t AR_CHKSTOP:1; + vuint16_t AR_SOFT:1; + vuint16_t AR_CORE:1; + vuint16_t AR_JTAG:1; + } B; + } FEAR; /* Functional Event Alternate Request */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t AR_LVD27:1; + vuint16_t AR_SWT:1; + vuint16_t AR_LVD12_PD1:1; + vuint16_t AR_LVD12_PD0:1; + } B; + } DEAR; /* Destructive Event Alternate Request */ + + int16_t RGM_reserved1[2]; + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t SS_LVD45:1; + vuint16_t SS_CMU_FHL:1; + vuint16_t SS_CMU_OLR:1; + vuint16_t SS_PLL:1; + vuint16_t SS_CHKSTOP:1; + vuint16_t SS_SOFT:1; + vuint16_t SS_CORE:1; + vuint16_t SS_JTAG:1; + } B; + } FESS; /* Functional Event Short Sequence */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t BOOT_FROM_BKP_RAM:1; + vuint16_t:7; + } B; + } STDBY; /* STANDBY reset sequence */ + + union { + vuint16_t R; + struct { + vuint16_t BE_EXR:1; + vuint16_t:6; + vuint16_t BE_FLASH:1; + vuint16_t BE_LVD45:1; + vuint16_t BE_CMU_FHL:1; + vuint16_t BE_CMU_OLR:1; + vuint16_t BE_FMPLL:1; + vuint16_t BE_CHKSTOP:1; + vuint16_t BE_SOFT:1; + vuint16_t BE_CORE:1; + vuint16_t BE_JTAG:1; + } B; + } FBRE; /* Functional Bidirectional Reset Enable */ + + }; /* end of RGM_tag */ +/****************************************************************************/ +/* MODULE : RTC */ +/****************************************************************************/ + struct RTC_tag { + union { + vuint32_t R; + struct { + vuint32_t SUPV:1; + vuint32_t:31; + } B; + } RTCSUPV; /* RTC Supervisor Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t CNTEN:1; + vuint32_t RTCIE:1; + vuint32_t FRZEN:1; + vuint32_t ROVREN:1; + vuint32_t RTCVAL:12; + vuint32_t APIEN:1; + vuint32_t APIIE:1; + vuint32_t CLKSEL:2; + vuint32_t DIV512EN:1; + vuint32_t DIV32EN:1; + vuint32_t APIVAL:10; + } B; + } RTCC; /* RTC Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t RTCF:1; + vuint32_t:15; + vuint32_t APIF:1; + vuint32_t:2; + vuint32_t ROVRF:1; + vuint32_t:10; + } B; + } RTCS; /* RTC Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + }; /* end of RTC_tag */ +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; /* {0x004-0x000}/4 = 0x01 */ + + union { /* MCU ID Register 1 */ + vuint32_t R; + struct { + vuint32_t PARTNUM:16; + vuint32_t CSP:1; + vuint32_t PKG:5; + vuint32_t:2; + vuint32_t MAJOR_MASK:4; + vuint32_t MINOR_MASK:4; + } B; + } MIDR; + + union { /* MCU ID Register 2 */ + vuint32_t R; + struct { + vuint32_t SF:1; + vuint32_t FLASH_SIZE_1:4; + vuint32_t FLASH_SIZE_2:4; + vuint32_t:7; + vuint32_t PARTNUM:8; + vuint32_t:3; + vuint32_t EE:1; + vuint32_t:4; + } B; + } MIDR2; + + int32_t SIU_reserved1[2]; /* {0x014-0x00C}/4 = 0x02 */ + + union { /* Interrupt Status Flag Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t EIF15:1; + vuint32_t EIF14:1; + vuint32_t EIF13:1; + vuint32_t EIF12:1; + vuint32_t EIF11:1; + vuint32_t EIF10:1; + vuint32_t EIF9:1; + vuint32_t EIF8:1; + vuint32_t EIF7:1; + vuint32_t EIF6:1; + vuint32_t EIF5:1; + vuint32_t EIF4:1; + vuint32_t EIF3:1; + vuint32_t EIF2:1; + vuint32_t EIF1:1; + vuint32_t EIF0:1; + } B; + } ISR; + + union { /* Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t EIRE15:1; + vuint32_t EIRE14:1; + vuint32_t EIRE13:1; + vuint32_t EIRE12:1; + vuint32_t EIRE11:1; + vuint32_t EIRE10:1; + vuint32_t EIRE9:1; + vuint32_t EIRE8:1; + vuint32_t EIRE7:1; + vuint32_t EIRE6:1; + vuint32_t EIRE5:1; + vuint32_t EIRE4:1; + vuint32_t EIRE3:1; + vuint32_t EIRE2:1; + vuint32_t EIRE1:1; + vuint32_t EIRE0:1; + } B; + } IRER; + + int32_t SIU_reserved2[3]; /* {0x028-0x01C}/4 = 0x03 */ + + union { /* Interrupt Rising-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t IREE15:1; + vuint32_t IREE14:1; + vuint32_t IREE13:1; + vuint32_t IREE12:1; + vuint32_t IREE11:1; + vuint32_t IREE10:1; + vuint32_t IREE9:1; + vuint32_t IREE8:1; + vuint32_t IREE7:1; + vuint32_t IREE6:1; + vuint32_t IREE5:1; + vuint32_t IREE4:1; + vuint32_t IREE3:1; + vuint32_t IREE2:1; + vuint32_t IREE1:1; + vuint32_t IREE0:1; + } B; + } IREER; + + union { /* Interrupt Falling-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t IFEE15:1; + vuint32_t IFEE14:1; + vuint32_t IFEE13:1; + vuint32_t IFEE12:1; + vuint32_t IFEE11:1; + vuint32_t IFEE10:1; + vuint32_t IFEE9:1; + vuint32_t IFEE8:1; + vuint32_t IFEE7:1; + vuint32_t IFEE6:1; + vuint32_t IFEE5:1; + vuint32_t IFEE4:1; + vuint32_t IFEE3:1; + vuint32_t IFEE2:1; + vuint32_t IFEE1:1; + vuint32_t IFEE0:1; + } B; + } IFEER; + + union { /* Interrupt Filter Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t IFE15:1; + vuint32_t IFE14:1; + vuint32_t IFE13:1; + vuint32_t IFE12:1; + vuint32_t IFE11:1; + vuint32_t IFE10:1; + vuint32_t IFE9:1; + vuint32_t IFE8:1; + vuint32_t IFE7:1; + vuint32_t IFE6:1; + vuint32_t IFE5:1; + vuint32_t IFE4:1; + vuint32_t IFE3:1; + vuint32_t IFE2:1; + vuint32_t IFE1:1; + vuint32_t IFE0:1; + } B; + } IFER; + + int32_t SIU_reserved3[3]; /* {0x040-0x034}/4 = 0x03 */ + + union { /* Pad Configuration Registers */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SMC:1; + vuint16_t APC:1; + vuint16_t:1; + vuint16_t PA:2; + vuint16_t OBE:1; + vuint16_t IBE:1; + vuint16_t:2; + vuint16_t ODE:1; + vuint16_t:2; + vuint16_t SRC:1; + vuint16_t WPE:1; + vuint16_t WPS:1; + } B; + } PCR[123]; + + int32_t SIU_reserved4[242]; /* {0x500-0x136}/0xF2 */ + + union { /* Pad Selection for Multiplexed Input Register */ + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PADSEL:4; + } B; + } PSMI[32]; + + int32_t SIU_reserved5[56]; /* {0x600-0x520}/4 = 0x38 */ + + union { /* GPIO Pin Data Output Registers */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDO:1; + } B; + } GPDO[124]; + + int32_t SIU_reserved6[97]; /* {0x800-0x67C}/4 = 0x61 */ + + union { /* GPIO Pin Data Input Registers */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDI:1; + } B; + } GPDI[124]; + + int32_t SIU_reserved7[225]; /* {0xC00-0x87C}/0x4 = 0xE1 */ + + union { /* Parallel GPIO Pin Data Output Register */ + vuint32_t R; + struct { + vuint32_t PPD0:32; + } B; + } PGPDO[4]; + + int32_t SIU_reserved8[12]; /* {0xC40-0xC10}/0x4 = 0x0C */ + + union { /* Parallel GPIO Pin Data Input Register */ + vuint32_t R; + struct { + vuint32_t PPDI:32; + } B; + } PGPDI[4]; + + int32_t SIU_reserved9[12]; /* {0xC80-0xC50}/0x4 = 0x0C */ + + union { /* Masked Parallel GPIO Pin Data Out Register */ + vuint32_t R; + struct { + vuint32_t MASK:16; + vuint32_t MPPDO:16; + } B; + } MPGPDO[8]; + + int32_t SIU_reserved10[216]; /* {0x1000-0x0CA0}/4 = 0xD8 */ + + union { /* Interrupt Filter Maximum Counter Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t MAXCNT:4; + } B; + } IFMC[16]; + + int32_t SIU_reserved11[16]; /* {0x1080-0x1040}/4 = 0x10 */ + + union { /* Interrupt Filter Clock Prescaler Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFCP:4; + } B; + } IFCPR; + + }; /* end of SIU_tag */ +/****************************************************************************/ +/* MODULE : SSCM */ +/****************************************************************************/ + struct SSCM_tag { + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t NXEN:1; + vuint16_t:3; + vuint16_t BMODE:3; + vuint16_t:1; + vuint16_t ABD:1; + vuint16_t:3; + } B; + } STATUS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t SRAM_SIZE:5; + vuint16_t PRSZ:5; + vuint16_t PVLB:1; + vuint16_t DTSZ:4; + vuint16_t DVLD:1; + } B; + } MEMCONFIG; /* System Memory Configuration Register */ + + int16_t SSCM_reserved; + + union { + vuint16_t R; + struct { + vuint16_t:14; + vuint16_t PAE:1; + vuint16_t RAE:1; + } B; + } ERROR; /* Error Configuration Register */ + + int16_t SSCM_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t PWD_HI:32; + } B; + } PWCMPH; /* Password Comparison Register High Word */ + + union { + vuint32_t R; + struct { + vuint32_t PWD_LO:32; + } B; + } PWCMPL; /* Password Comparison Register Low Word */ + + }; /* end of SSCM_tag */ +/****************************************************************************/ +/* MODULE : STM */ +/****************************************************************************/ + struct STM_CHANNEL_tag { + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR; /* STM Channel Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR; /* STM Channel Interrupt Register */ + + union { + vuint32_t R; + } CMP; /* STM Channel Compare Register 0 */ + + int32_t STM_CHANNEL_reserved; + + }; /* end of STM_CHANNEL_tag */ + + struct STM_tag { + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; /* STM Control Register */ + + union { + vuint32_t R; + } CNT; /* STM Count Register */ + + int32_t STM_reserved[2]; + + struct STM_CHANNEL_tag CH[4]; + + }; /* end of STM_tag */ +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:15; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } CR; /* SWT Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* SWT Interrupt Register */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* SWT Time-Out Register */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + } B; + } WN; /* SWT Window Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* SWT Service Register */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* SWT Counter Output Register */ + + }; /* end of SWT_tag */ +/****************************************************************************/ +/* MODULE : WKUP */ +/****************************************************************************/ + struct WKUP_tag { + union { + vuint32_t R; + struct { + vuint32_t NIF0:1; + vuint32_t NOVF0:1; + vuint32_t:30; + } B; + } NSR; /* NMI Status Register */ + + int32_t WKUP_reserved; + + union { + vuint32_t R; + struct { + vuint32_t NLOCK:1; + vuint32_t NDSS:2; + vuint32_t NWRE:1; + vuint32_t:1; + vuint32_t NREE:1; + vuint32_t NFEE:1; + vuint32_t NFE:1; + vuint32_t:24; + } B; + } NCR; /* NMI Configuration Register */ + + int32_t WKUP_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t EIF:20; + } B; + } WISR; /* Wakeup/Interrupt Status Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t EIRE:20; + } B; + } IRER; /* Interrupt Request Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t WRE:20; + } B; + } WRER; /* Wakeup Request Enable Register */ + + int32_t WKUP_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t IREE:20; + } B; + } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t IFEE:20; + } B; + } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t IFE:20; + } B; + } WIFER; /* Wakeup/Interrupt Filter Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t IPUE:20; + } B; + } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */ + + }; /* end of WKUP_tag */ +/****************************************************************** +| defines and macros (scope: module-local) +|-----------------------------------------------------------------*/ +/* Define instances of modules */ +#define ADC (*(volatile struct ADC_tag *) 0xFFE00000UL) +#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL) +#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL) +#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL) +#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL) +#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL) +#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL) +#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL) +#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL) +#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL) +#define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL) +#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL) +#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL) +#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL) +#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL) +#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL) +#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL) +#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL) +#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL) +#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL) +#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) +#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) +#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif /* + */ + +#ifdef __cplusplus +} +#endif /* + */ + +#endif /* ifdef _MPC5604B_H */ + +/* End of file */ diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.c b/os/hal/platforms/SPC560Dxx/hal_lld.c new file mode 100644 index 000000000..229051979 --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/hal_lld.c @@ -0,0 +1,284 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/hal_lld.c + * @brief SPC560Dxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief PIT channel 3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector59) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + /* Resets the PIT channel 3 IRQ flag.*/ + PIT.CH[0].TFLG.R = 1; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t reg; + + /* The system is switched to the RUN0 mode, the default for normal + operations.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* PIT channel 0 initialization for Kernel ticks, the PIT is configured + to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other + modes.*/ + INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; + halSPCSetPeripheralClockMode(92, + SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); + reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; + PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ + PIT.CH[0].LDVAL.R = reg; + PIT.CH[0].CVAL.R = reg; + PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ + PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ + + /* EDMA initialization.*/ + edmaInit(); +} + +/** + * @brief SPC560B/Cxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + + /* Waiting for IRC stabilization before attempting anything else.*/ + while (!ME.GS.B.S_FIRC) + ; + +#if !SPC5_NO_INIT + +#if SPC5_DISABLE_WATCHDOG + /* SWT disabled.*/ + SWT.SR.R = 0xC520; + SWT.SR.R = 0xD928; + SWT.CR.R = 0xFF00000A; +#endif + + /* SSCM initialization. Setting up the most restrictive handling of + invalid accesses to peripherals.*/ + SSCM.ERROR.R = 3; /* PAE and RAE bits. */ + + /* RGM errors clearing.*/ + RGM.FES.R = 0xFFFF; + RGM.DES.R = 0xFFFF; + + /* Oscillators dividers setup.*/ + CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1; + CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1; + + /* The system must be in DRUN mode on entry, if this is not the case then + it is considered a serious anomaly.*/ + if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) { + SPC5_CLOCK_FAILURE_HOOK(); + } + +#if defined(SPC5_OSC_BYPASS) + /* If the board is equipped with an oscillator instead of a xtal then the + bypass must be activated.*/ + CGM.OSC_CTL.B.OSCBYP = TRUE; +#endif /* SPC5_OSC_BYPASS */ + + /* Setting the various dividers and source selectors.*/ + CGM.SC_DC0.R = SPC5_CGM_SC_DC0; + CGM.SC_DC1.R = SPC5_CGM_SC_DC1; + CGM.SC_DC2.R = SPC5_CGM_SC_DC2; + + /* Initialization of the FMPLLs settings.*/ + CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF | + ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL0_NDIV_VALUE << 16); + CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */ + + /* Run modes initialization.*/ + ME.IS.R = 8; /* Resetting I_ICONF status.*/ + ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ + ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */ + ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ + ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ + ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ + ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ + ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ + ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ + ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ + ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ + ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */ + if (ME.IS.B.I_ICONF) { + /* Configuration rejected.*/ + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Peripherals run and low power modes initialization.*/ + ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; + ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; + ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; + ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; + ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; + ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; + ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; + ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; + ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; + ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; + ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; + ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; + ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; + ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; + ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; + ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; + + /* CFLASH settings calculated for a maximum clock of 64MHz.*/ + CFLASH.PFCR0.B.BK0_APC = 2; + CFLASH.PFCR0.B.BK0_RWSC = 2; + CFLASH.PFCR1.B.BK1_APC = 2; + CFLASH.PFCR1.B.BK1_RWSC = 2; + + /* Switches again to DRUN mode (current mode) in order to update the + settings.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } +#endif /* !SPC5_NO_INIT */ +} + +/** + * @brief Switches the system to the specified run mode. + * + * @param[in] mode one of the possible run modes + * + * @return The operation status. + * @retval CH_SUCCESS if the switch operation has been completed. + * @retval CH_FAILED if the switch operation failed. + */ +bool_t halSPCSetRunMode(spc5_runmode_t mode) { + + /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/ + ME.IS.R = 5; + + /* Starts a transition process.*/ + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; + + /* Waits for the mode switch or an error condition.*/ + while (TRUE) { + uint32_t r = ME.IS.R; + if (r & 1) + return CH_SUCCESS; + if (r & 4) + return CH_FAILED; + } +} + +/** + * @brief Changes the clock mode of a peripheral. + * + * @param[in] n index of the @p PCTL register + * @param[in] pctl new value for the @p PCTL register + * + * @notapi + */ +void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) { + uint32_t mode; + + ME.PCTL[n].R = pctl; + mode = ME.MCTL.B.TARGET_MODE; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; +} + +#if !SPC5_NO_INIT || defined(__DOXYGEN__) +/** + * @brief Returns the system clock under the current run mode. + * + * @return The system clock in Hertz. + */ +uint32_t halSPCGetSystemClock(void) { + uint32_t sysclk; + + sysclk = ME.GS.B.S_SYSCLK; + switch (sysclk) { + case SPC5_ME_GS_SYSCLK_IRC: + return SPC5_IRC_CLK; + case SPC5_ME_GS_SYSCLK_DIVIRC: + return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE; + case SPC5_ME_GS_SYSCLK_XOSC: + return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE; + case SPC5_ME_GS_SYSCLK_DIVXOSC: + return SPC5_XOSC_CLK; + case SPC5_ME_GS_SYSCLK_FMPLL0: + return SPC5_FMPLL0_CLK; + default: + return 0; + } +} +#endif /* !SPC5_NO_INIT */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.h b/os/hal/platforms/SPC560Dxx/hal_lld.h new file mode 100644 index 000000000..5bc08014c --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/hal_lld.h @@ -0,0 +1,769 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/hal_lld.h + * @brief SPC560Dxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * - SPC5_OSC_BYPASS (optionally). + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc560d.h" +#include "spc560d_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "SPC560Dxx Car Body and Convenience" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MAX 16000000 + +/** + * @brief Minimum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MAX 48000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MAX 512000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MIN 256000000 + +/** + * @brief Maximum FMPLL0 output clock frequency. + */ +#define SPC5_FMPLL0_CLK_MAX 48000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define SPC5_IRC_CLK 16000000 /**< Internal fast RC + oscillator. */ +#define SPC5_SIRC_CLK 128000 /**< Internal RC slow + oscillator. */ +/** @} */ + +/** + * @name FMPLL_CR register bits definitions + * @{ + */ +#define SPC5_FMPLL_ODF_DIV2 (0U << 24) +#define SPC5_FMPLL_ODF_DIV4 (1U << 24) +#define SPC5_FMPLL_ODF_DIV8 (2U << 24) +#define SPC5_FMPLL_ODF_DIV16 (3U << 24) +/** @} */ + +/** + * @name ME_GS register bits definitions + * @{ + */ +#define SPC5_ME_GS_SYSCLK_MASK (15U << 0) +#define SPC5_ME_GS_SYSCLK_IRC (0U << 0) +#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0) +#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) +#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0) +#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) +/** @} */ + +/** + * @name ME_ME register bits definitions + * @{ + */ +#define SPC5_ME_ME_RESET (1U << 0) +#define SPC5_ME_ME_TEST (1U << 1) +#define SPC5_ME_ME_SAFE (1U << 2) +#define SPC5_ME_ME_DRUN (1U << 3) +#define SPC5_ME_ME_RUN0 (1U << 4) +#define SPC5_ME_ME_RUN1 (1U << 5) +#define SPC5_ME_ME_RUN2 (1U << 6) +#define SPC5_ME_ME_RUN3 (1U << 7) +#define SPC5_ME_ME_HALT0 (1U << 8) +#define SPC5_ME_ME_STOP0 (1U << 10) +#define SPC5_ME_ME_STANDBY0 (1U << 13) +/** @} */ + +/** + * @name ME_xxx_MC registers bits definitions + * @{ + */ +#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) +#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_IRCON (1U << 4) +#define SPC5_ME_MC_XOSC0ON (1U << 5) +#define SPC5_ME_MC_PLL0ON (1U << 6) +#define SPC5_ME_MC_CFLAON_MASK (3U << 16) +#define SPC5_ME_MC_CFLAON(n) ((n) << 16) +#define SPC5_ME_MC_CFLAON_PD (1U << 16) +#define SPC5_ME_MC_CFLAON_LP (2U << 16) +#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16) +#define SPC5_ME_MC_DFLAON_MASK (3U << 18) +#define SPC5_ME_MC_DFLAON(n) ((n) << 18) +#define SPC5_ME_MC_DFLAON_PD (1U << 18) +#define SPC5_ME_MC_DFLAON_LP (2U << 18) +#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18) +#define SPC5_ME_MC_MVRON (1U << 20) +#define SPC5_ME_MC_PDO (1U << 23) +/** @} */ + +/** + * @name ME_MCTL register bits definitions + * @{ + */ +#define SPC5_ME_MCTL_KEY 0x5AF0U +#define SPC5_ME_MCTL_KEY_INV 0xA50FU +#define SPC5_ME_MCTL_MODE_MASK (15U << 28) +#define SPC5_ME_MCTL_MODE(n) ((n) << 28) +/** @} */ + +/** + * @name ME_RUN_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_RUN_PC_TEST (1U << 1) +#define SPC5_ME_RUN_PC_SAFE (1U << 2) +#define SPC5_ME_RUN_PC_DRUN (1U << 3) +#define SPC5_ME_RUN_PC_RUN0 (1U << 4) +#define SPC5_ME_RUN_PC_RUN1 (1U << 5) +#define SPC5_ME_RUN_PC_RUN2 (1U << 6) +#define SPC5_ME_RUN_PC_RUN3 (1U << 7) +/** @} */ + +/** + * @name ME_LP_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_LP_PC_HALT0 (1U << 8) +#define SPC5_ME_LP_PC_STOP0 (1U << 10) +#define SPC5_ME_LP_PC_STANDBY0 (1U << 10) +/** @} */ + +/** + * @name ME_PCTL registers bits definitions + * @{ + */ +#define SPC5_ME_PCTL_RUN_MASK (7U << 0) +#define SPC5_ME_PCTL_RUN(n) ((n) << 0) +#define SPC5_ME_PCTL_LP_MASK (7U << 3) +#define SPC5_ME_PCTL_LP(n) ((n) << 3) +#define SPC5_ME_PCTL_DBG (1U << 6) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief Disables the watchdog on start. + */ +#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__) +#define SPC5_DISABLE_WATCHDOG TRUE +#endif + +/** + * @brief FMPLL0 IDF divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=48MHz. + */ +#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_IDF_VALUE 1 +#endif + +/** + * @brief FMPLL0 NDIV divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=48MHz. + */ +#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_NDIV_VALUE 48 +#endif + +/** + * @brief FMPLL0 ODF divider value. + * @note The default value is calculated for XOSC=8MHz and PHI=48MHz. + */ +#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8 +#endif + +/** + * @brief XOSC divider value. + * @note The allowed range is 1...32. + */ +#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_XOSCDIV_VALUE 1 +#endif + +/** + * @brief Fast IRC divider value. + * @note The allowed range is 1...32. + */ +#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_IRCDIV_VALUE 1 +#endif + +/** + * @brief Peripherals Set 1 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Peripherals Set 2 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Peripherals Set 3 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#endif + +/** + * @brief Active run modes in ME_ME register. + * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there + * is no need to specify them. + */ +#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#endif + +/** + * @brief TEST mode settings. + */ +#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief SAFE mode settings. + */ +#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#endif + +/** + * @brief DRUN mode settings. + */ +#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN0 mode settings. + */ +#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN1 mode settings. + */ +#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN2 mode settings. + */ +#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN3 mode settings. + */ +#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief HALT0 mode settings. + */ +#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STOP0 mode settings. + */ +#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STANDBY0 mode settings. + */ +#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief Peripheral mode 0 (run mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (run mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 2 (run mode). + * @note Do not change this setting, it is expected to be the "only during + * normal run" mode. + */ +#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 3 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 4 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 5 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 6 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 7 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 0 (low power mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (low power mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#endif + +/** + * @brief Peripheral mode 2 (low power mode). + * @note Do not change this setting, it is expected to be the "halt only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#endif + +/** + * @brief Peripheral mode 3 (low power mode). + * @note Do not change this setting, it is expected to be the "stop only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 4 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 5 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 6 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 7 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief PIT channel 0 IRQ priority. + * @note This PIT channel is allocated permanently for system tick + * generation. + */ +#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#endif + +/** + * @brief Clock initialization failure hook. + * @note The default is to stop the system and let the RTC restart it. + * @note The hook code must not return. + */ +#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC560Dxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined" +#endif + +/* Check on the XOSC frequency.*/ +#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ + (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) +#error "invalid SPC5_XOSC_CLK value specified" +#endif + +/* Check on the XOSC divider.*/ +#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32) +#error "invalid SPC5_XOSCDIV_VALUE value specified" +#endif + +/* Check on the IRC divider.*/ +#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32) +#error "invalid SPC5_IRCDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_IDF_VALUE.*/ +#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL0_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_NDIV_VALUE.*/ +#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_ODF.*/ +#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL0_ODF_VALUE 2 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL0_ODF_VALUE 4 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL0_ODF_VALUE 8 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL0_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL0_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL0_VCO_CLK clock point. + */ +#define SPC5_FMPLL0_VCO_CLK \ + ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE) + +/* Check on FMPLL0 VCO output.*/ +#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL0_CLK clock point. + */ +#define SPC5_FMPLL0_CLK \ + (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE) + +/* Check on SPC5_FMPLL0_CLK.*/ +#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)" +#endif + +/* Check on the peripherals set 1 clock divider settings.*/ +#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC0 0 +#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified" +#endif + +/* Check on the peripherals set 2 clock divider settings.*/ +#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC1 0 +#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified" +#endif + +/* Check on the peripherals set 3 clock divider settings.*/ +#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0 +#define SPC5_CGM_SC_DC2 0 +#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \ + (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16) +#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1)) +#else +#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef enum { + SPC5_RUNMODE_TEST = 1, + SPC5_RUNMODE_SAFE = 2, + SPC5_RUNMODE_DRUN = 3, + SPC5_RUNMODE_RUN0 = 4, + SPC5_RUNMODE_RUN1 = 5, + SPC5_RUNMODE_RUN2 = 6, + SPC5_RUNMODE_RUN3 = 7, + SPC5_RUNMODE_HALT0 = 8, + SPC5_RUNMODE_STOP0 = 10 +} spc5_runmode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); + bool_t halSPCSetRunMode(spc5_runmode_t mode); + void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); +#if !SPC5_NO_INIT + uint32_t halSPCGetSystemClock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Dxx/platform.mk b/os/hal/platforms/SPC560Dxx/platform.mk new file mode 100644 index 000000000..8e6c8d73a --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/platform.mk @@ -0,0 +1,13 @@ +# List of all the SPC560Dxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1 diff --git a/os/hal/platforms/SPC560Dxx/spc560d_registry.h b/os/hal/platforms/SPC560Dxx/spc560d_registry.h new file mode 100644 index 000000000..72fd5b36c --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/spc560d_registry.h @@ -0,0 +1,123 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/spc560d_registry.h + * @brief SPC560Dxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC560D_REGISTRY_H_ +#define _SPC560D_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC560Dxx capabilities + * @{ + */ +/* DSPI attribures.*/ +#define SPC5_HAS_DSPI0 TRUE +#define SPC5_HAS_DSPI1 TRUE +#define SPC5_HAS_DSPI2 FALSE +#define SPC5_HAS_DSPI3 FALSE +#define SPC5_HAS_DSPI4 FALSE +#define SPC5_DSPI_FIFO_DEPTH 4 +#define SPC5_DSPI0_PCTL 4 +#define SPC5_DSPI1_PCTL 5 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_DSPI0_TX1_DMA_DEV_ID 1 +#define SPC5_DSPI0_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI0_RX_DMA_DEV_ID 2 +#define SPC5_DSPI1_TX1_DMA_DEV_ID 3 +#define SPC5_DSPI1_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI1_RX_DMA_DEV_ID 4 +#define SPC5_DSPI0_TFFF_HANDLER vector76 +#define SPC5_DSPI0_TFFF_NUMBER 76 +#define SPC5_DSPI1_TFFF_HANDLER vector96 +#define SPC5_DSPI1_TFFF_NUMBER 96 +#define SPC5_DSPI0_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL) +#define SPC5_DSPI0_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL) +#define SPC5_DSPI1_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL) +#define SPC5_DSPI1_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL) + +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA TRUE +#define SPC5_EDMA_NCHANNELS 16 +#define SPC5_EDMA_HAS_MUX TRUE +#define SPC5_EDMA_MUX_PCTL 23 + +/* LINFlex attributes.*/ +#define SPC5_HAS_LINFLEX0 TRUE +#define SPC5_LINFLEX0_PCTL 48 +#define SPC5_LINFLEX0_RXI_HANDLER vector79 +#define SPC5_LINFLEX0_TXI_HANDLER vector80 +#define SPC5_LINFLEX0_ERR_HANDLER vector81 +#define SPC5_LINFLEX0_RXI_NUMBER 79 +#define SPC5_LINFLEX0_TXI_NUMBER 80 +#define SPC5_LINFLEX0_ERR_NUMBER 81 +#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX1 TRUE +#define SPC5_LINFLEX1_PCTL 49 +#define SPC5_LINFLEX1_RXI_HANDLER vector99 +#define SPC5_LINFLEX1_TXI_HANDLER vector100 +#define SPC5_LINFLEX1_ERR_HANDLER vector101 +#define SPC5_LINFLEX1_RXI_NUMBER 99 +#define SPC5_LINFLEX1_TXI_NUMBER 100 +#define SPC5_LINFLEX1_ERR_NUMBER 101 +#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX2 TRUE +#define SPC5_LINFLEX2_PCTL 50 +#define SPC5_LINFLEX2_RXI_HANDLER vector119 +#define SPC5_LINFLEX2_TXI_HANDLER vector120 +#define SPC5_LINFLEX2_ERR_HANDLER vector121 +#define SPC5_LINFLEX2_RXI_NUMBER 119 +#define SPC5_LINFLEX2_TXI_NUMBER 120 +#define SPC5_LINFLEX2_ERR_NUMBER 121 +#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \ + SPC5_PERIPHERAL1_CLK_DIV_VALUE) + +#define SPC5_HAS_LINFLEX3 FALSE + +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_PCTL 68 +#define SPC5_SIUL_NUM_PORTS 8 +#define SPC5_SIUL_NUM_PCRS 77 +#define SPC5_SIUL_NUM_PADSELS 63 +#define SPC5_SIUL_SYSTEM_PINS 32,33 +/** @} */ + +#endif /* _SPC560D_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Dxx/typedefs.h b/os/hal/platforms/SPC560Dxx/typedefs.h new file mode 100644 index 000000000..290173872 --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC560Dxx/xpc560d.h b/os/hal/platforms/SPC560Dxx/xpc560d.h new file mode 100644 index 000000000..e511c24c8 --- /dev/null +++ b/os/hal/platforms/SPC560Dxx/xpc560d.h @@ -0,0 +1,5557 @@ +/**************************************************************************** + * PROJECT : MPC5602Dx + * + * FILE : MPC5602Dx_2.03.h + * + * DESCRIPTION : This is the header file describing the register + * set for MPC560xBx family of MCUs. It supports the following devices: + * + * - MPC5602D + * + * + * COPYRIGHT :(c) 2012, Freescale + * + * VERSION : 2.03 + * DATE : 06.05.2012 + * AUTHOR : r23668 + * HISTORY : New header Based Upon MPC5607B and MPC5606BK. Version 1.04 + * 0.12 Oct 2011: MPC5606BK + * 1.0 Alpha Nov 2011 : MPC560xBx combined header file. Out for Review and comments. + * 1.01 Jan 2012: Checked with both MPC5607x and MPC5606Bx, no comments recieved. + * 1.04 Mar 2012: Supersedes MPC5607B ver 1.03 and becomes Ver 1.04. + * 2.01 Added missing ADC registers CIMR1, CIMR2, PSR1, NCMR1, NCMR2 + * 2.02 Added more missing ADC registers CEOCFR2, DMAR1/2, PSR1, DSDR, CDR, CWSEL8-11, CWENR2, AWORR2, NCMR2, JCMR2 + * 2.03 Corrected RM discrepancies. + ***************************************************************** + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ******************************************************************/ + +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/***************************************************************** +* Example instantiation and use: +* +* ..B. = 1; +* ..R = 0x10000000; +* +******************************************************************/ + +#ifndef _JDP_H_ +#define _JDP_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : CFLASH (base address - 0xC3F8_8000) */ +/****************************************************************************/ + struct CFLASH_tag { + union { /* Module Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:2; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* Low/Mid address block locking (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:2; + vuint32_t MLK:2; + vuint32_t:10; + vuint32_t LLK:6; + } B; + } LML; + + union { /* High address space block locking (Base+0x0008)*/ + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t :27; + vuint32_t HLK:4; + } B; + } HBL; + + union { /* Secondary Low/Mid block lock (Base+0x000C)*/ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:2; + vuint32_t SMK:2; + vuint32_t:10; + vuint32_t SLK:6; + } B; + } SLL; + + union { /* Low/Mid address space block sel (Base+0x0010)*/ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; + vuint32_t:10; + vuint32_t LSL:6; + } B; + } LMS; + + union { /* High address Space block select (Base+0x0014)*/ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t HSL:4; + } B; + } HBS; + + union { /* Address Register (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t ADD:20; + vuint32_t:3; + } B; + } ADR; + + /* Note the following 3 registers, BIU[0..2] are mirrored to */ + /* the code flash configuraiton PFCR[0..2] registers */ + /* To make it easier to code, the BIU registers have been */ + /* replaced with the PFCR registers in this header file! */ + /* A commented out BIU register is shown for reference! */ + + + union { /* CFLASH Configuration 0 (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t BK0_APC:5; + vuint32_t BK0_WWSC:5; + vuint32_t BK0_RWSC:5; + vuint32_t BK0_RWWC2:1; + vuint32_t BK0_RWWC1:1; + vuint32_t :7; + vuint32_t BK0_RWWC0:1; + vuint32_t B0_P0_BCFG:2; + vuint32_t B0_P0_DPFE:1; + vuint32_t B0_P0_IPFE:1; + vuint32_t B0_P0_PFLM:2; + vuint32_t B0_P0_BFE:1; + } B; + } PFCR0; + + /* Commented out Bus Interface Unit 0 (Base+0x001C) */ + /*union { + + vuint32_t R; + + struct { + + vuint32_t BI0:32; + + } B; + + } BIU0; */ + union { /* CFLASH Configuration Register 1 (Base+0x0020)*/ + vuint32_t R; + struct { + vuint32_t BK1_APC:5; + vuint32_t BK1_WWSC:5; + vuint32_t BK1_RWSC:5; + vuint32_t BK1_RWWC2:1; + vuint32_t BK1_RWWC1:1; + vuint32_t:7; + vuint32_t BK1_RWWC0:1; + vuint32_t:6; + vuint32_t B1_P0_BFE:1; + } B; + } PFCR1; + /* Commented out Bus Interface Unit 1 (Base+0x0020) */ + /*union { + + vuint32_t R; + + struct { + + vuint32_t BI1:32; + + } B; + + } BIU1; */ + + + union { /* CFLASH Access Protection (Base+0x0024) */ + vuint32_t R; + struct { + vuint32_t:13; + vuint32_t M2PFD:1; + vuint32_t:1; + vuint32_t M0PFD:1; + vuint32_t:10; + vuint32_t M2AP:2; + vuint32_t:2; + vuint32_t M0AP:2; + } B; + } PFAPR; + /* Commented out Bus Interface Unit 2 (Base+0x0024) */ + /*union { + + vuint32_t R; + + struct { + + vuint32_t BI2:32; + + } B; + + } BIU2; */ + + + vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */ + + union { /* User Test 0 (Base+0x003C) */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test 1 (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test 2 (Base+0x0044) */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/ + + }; /* end of CFLASH_tag */ + +/****************************************************************************/ +/* MODULE : DFLASH (base address - 0xC3F8C000) */ +/****************************************************************************/ + struct DFLASH_tag { + union { /* Module Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:2; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* Low/Mid address block locking (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:16; + vuint32_t LLK:4; + } B; + } LML; + + vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */ + + + union { /* Secondary Low/mid block locking (Base+0x000C)*/ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:16; + vuint32_t SLK:4; + } B; + } SLL; + + union { /* Low/Mid address space block sel (Base+0x0010)*/ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t LSL:4; + } B; + } LMS; + + vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017)*/ + + union { /* Address Register (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t ADD:20; + vuint32_t:3; + } B; + } ADR; + + vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */ + + union { /* User Test 0 (Base+0x003C) */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test 1 (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test 2 (Base+0x0044) */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + }; /* end of Dflash_tag */ + +/****************************************************************************/ +/* MODULE : SIU Lite (tagged as SIU for compatibility) */ +/****************************************************************************/ +struct SIU_tag { + + vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */ + + union { /* MCU ID1 (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t PARTNUM:16; + vuint32_t CSP:1; + vuint32_t PKG:5; + vuint32_t :2; + vuint32_t MAJOR_MASK:4; + vuint32_t MINOR_MASK:4; + } B; + } MIDR1; + + union { /* MCU ID2 (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t SF:1; + vuint32_t FLASH_SIZE_1:4; + vuint32_t FLASH_SIZE_2:4; + vuint32_t :7; + vuint32_t PARTNUM:8; + vuint32_t :3; + vuint32_t EE:1; + vuint32_t :3; + vuint32_t FR:1; + } B; + } MIDR2; + + vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */ + + union { /* Interrupt Status Flag (Base+0x0014)*/ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t EIF23:1; + vuint32_t EIF22:1; + vuint32_t EIF21:1; + vuint32_t EIF20:1; + vuint32_t EIF19:1; + vuint32_t EIF18:1; + vuint32_t EIF17:1; + vuint32_t EIF16:1; + vuint32_t EIF15:1; + vuint32_t EIF14:1; + vuint32_t EIF13:1; + vuint32_t EIF12:1; + vuint32_t EIF11:1; + vuint32_t EIF10:1; + vuint32_t EIF9:1; + vuint32_t EIF8:1; + vuint32_t EIF7:1; + vuint32_t EIF6:1; + vuint32_t EIF5:1; + vuint32_t EIF4:1; + vuint32_t EIF3:1; + vuint32_t EIF2:1; + vuint32_t EIF1:1; + vuint32_t EIF0:1; + } B; + } ISR; + + union { /* Interrupt Request Enable (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t IRE23:1; + vuint32_t IRE22:1; + vuint32_t IRE21:1; + vuint32_t IRE20:1; + vuint32_t IRE19:1; + vuint32_t IRE18:1; + vuint32_t IRE17:1; + vuint32_t IRE16:1; + vuint32_t IRE15:1; + vuint32_t IRE14:1; + vuint32_t IRE13:1; + vuint32_t IRE12:1; + vuint32_t IRE11:1; + vuint32_t IRE10:1; + vuint32_t IRE9:1; + vuint32_t IRE8:1; + vuint32_t IRE7:1; + vuint32_t IRE6:1; + vuint32_t IRE5:1; + vuint32_t IRE4:1; + vuint32_t IRE3:1; + vuint32_t IRE2:1; + vuint32_t IRE1:1; + vuint32_t IRE0:1; + } B; + } IRER; + + vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */ + + union { /* Interrupt Rising-Edge Event Enable (+0x0028) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t IREE23:1; + vuint32_t IREE22:1; + vuint32_t IREE21:1; + vuint32_t IREE20:1; + vuint32_t IREE19:1; + vuint32_t IREE18:1; + vuint32_t IREE17:1; + vuint32_t IREE16:1; + vuint32_t IREE15:1; + vuint32_t IREE14:1; + vuint32_t IREE13:1; + vuint32_t IREE12:1; + vuint32_t IREE11:1; + vuint32_t IREE10:1; + vuint32_t IREE9:1; + vuint32_t IREE8:1; + vuint32_t IREE7:1; + vuint32_t IREE6:1; + vuint32_t IREE5:1; + vuint32_t IREE4:1; + vuint32_t IREE3:1; + vuint32_t IREE2:1; + vuint32_t IREE1:1; + vuint32_t IREE0:1; + } B; + } IREER; + + union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t IFEE23:1; + vuint32_t IFEE22:1; + vuint32_t IFEE21:1; + vuint32_t IFEE20:1; + vuint32_t IFEE19:1; + vuint32_t IFEE18:1; + vuint32_t IFEE17:1; + vuint32_t IFEE16:1; + vuint32_t IFEE15:1; + vuint32_t IFEE14:1; + vuint32_t IFEE13:1; + vuint32_t IFEE12:1; + vuint32_t IFEE11:1; + vuint32_t IFEE10:1; + vuint32_t IFEE9:1; + vuint32_t IFEE8:1; + vuint32_t IFEE7:1; + vuint32_t IFEE6:1; + vuint32_t IFEE5:1; + vuint32_t IFEE4:1; + vuint32_t IFEE3:1; + vuint32_t IFEE2:1; + vuint32_t IFEE1:1; + vuint32_t IFEE0:1; + } B; + } IFEER; + + union { /* Interrupt Filter Enable (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t IFE23:1; + vuint32_t IFE22:1; + vuint32_t IFE21:1; + vuint32_t IFE20:1; + vuint32_t IFE19:1; + vuint32_t IFE18:1; + vuint32_t IFE17:1; + vuint32_t IFE16:1; + vuint32_t IFE15:1; + vuint32_t IFE14:1; + vuint32_t IFE13:1; + vuint32_t IFE12:1; + vuint32_t IFE11:1; + vuint32_t IFE10:1; + vuint32_t IFE9:1; + vuint32_t IFE8:1; + vuint32_t IFE7:1; + vuint32_t IFE6:1; + vuint32_t IFE5:1; + vuint32_t IFE4:1; + vuint32_t IFE3:1; + vuint32_t IFE2:1; + vuint32_t IFE1:1; + vuint32_t IFE0:1; + } B; + } IFER; + + vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */ + + union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SMC:1; + vuint16_t APC:1; + vuint16_t:1; + vuint16_t PA:2; + vuint16_t OBE:1; + vuint16_t IBE:1; + vuint16_t:2; + vuint16_t ODE:1; + vuint16_t:2; + vuint16_t SRC:1; + vuint16_t WPE:1; + vuint16_t WPS:1; + } B; + } PCR[149]; + + vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */ + + union { /* Pad Selection for Mux Input (0x0500-0x53C) */ + vuint8_t R; + struct { + vuint8_t :4; + vuint8_t PADSEL:4; + } B; + } PSMI[64]; + + vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */ + + union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */ + vuint8_t R; + struct { + vuint8_t :7; + vuint8_t PDO:1; + } B; + } GPDO[124]; // only 124 GPD0 registers + + vuint8_t SIU_reserved6[388]; /*Reserved 388 Bytes 512-124=388 */ + + union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */ + vuint8_t R; + struct { + vuint8_t :7; + vuint8_t PDI:1; + } B; + } GPDI[124]; // only 152 GPD0 registers + + vuint8_t SIU_reserved7[900]; /*Reserved 900 Bytes 1024-124=900 */ + + union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */ + vuint32_t R; + struct { + vuint32_t PPD0:32; + } B; + } PGPDO[5]; + + vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */ + + union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */ + vuint32_t R; + struct { + vuint32_t PPDI:32; + } B; + } PGPDI[5]; + + vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */ + + union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */ + vuint32_t R; + struct { + vuint32_t MASK:16; + vuint32_t MPPDO:16; + } B; + } MPGPDO[10]; + + vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/ + + union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */ + vuint32_t R; + struct { + vuint32_t :28; + vuint32_t MAXCNT:4; + } B; + } IFMC[24]; + + vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/ + + union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */ + vuint32_t R; + struct { + vuint32_t :28; + vuint32_t IFCP:4; + } B; + } IFCPR; + + vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/ + +}; /* end of SIU_tag */ + +/****************************************************************************/ +/* MODULE : WKUP */ +/****************************************************************************/ +struct WKUP_tag{ + + union { /* NMI Status Flag (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t NIF0:1; + vuint32_t NOVF0:1; + vuint32_t :30; + } B; + } NSR; + + vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */ + + union { /* NMI Configuration (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t NLOCK0:1; + vuint32_t NDSS0:2; + vuint32_t NWRE0:1; + vuint32_t :1; + vuint32_t NREE0:1; + vuint32_t NFEE0:1; + vuint32_t NFE0:1; + vuint32_t :24; + } B; + } NCR; + + vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */ + + union { /* Wakeup/Interrup status flag (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t EIF:29; + } B; + } WISR; + + union { /* Interrupt Request Enable (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t EIRE:29; + } B; + } IRER; + + union { /* Wakeup Request Enable (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t WRE:29; + } B; + } WRER; + + vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */ + + union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t IREE:29; + } B; + } WIREER; + + union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t IFEE:29; + } B; + } WIFEER; + + union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t IFE:29; + } B; + } WIFER; + + union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t IPUE:29; + } B; + } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */ + + vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */ + +}; /* end of WKUP_tag */ + +/****************************************************************************/ +/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */ +/****************************************************************************/ + +struct EMIOS_CHANNEL_tag{ + + union { /* Channel A Data (UCn Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t A:16; + } B; + } CADR; + + union { /* Channel B Data (UCn Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t B:16; + } B; + } CBDR; + + union { /* Channel Counter (UCn Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t C:16; + } B; + } CCNTR; + + union { /* Channel Control (UCn Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t :3; + vuint32_t UCPRE:2; + vuint32_t UCPEN:1; + vuint32_t DMA:1; + vuint32_t :1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t :3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t :1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; + + union { /* Channel Status (UCn Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t :15; + vuint32_t OVFL:1; + vuint32_t :12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; + + union { /* Alternate Channel A Data (UCn Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t ALTA:16; + } B; + } ALTCADR; + + vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */ + +}; /* end of EMIOS_CHANNEL_tag */ + + +struct EMIOS_tag{ + + union { /* Module Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t :1; + vuint32_t GPREN:1; + vuint32_t :10; + vuint32_t GPRE:8; + vuint32_t :8; + } B; + } MCR; + + union { /* Global Flag (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t F31:1; + vuint32_t F30:1; + vuint32_t F29:1; + vuint32_t F28:1; + vuint32_t F27:1; + vuint32_t F26:1; + vuint32_t F25:1; + vuint32_t F24:1; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; + + union { /* Output Update Disable (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t OU31:1; + vuint32_t OU30:1; + vuint32_t OU29:1; + vuint32_t OU28:1; + vuint32_t OU27:1; + vuint32_t OU26:1; + vuint32_t OU25:1; + vuint32_t OU24:1; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; + + union { /* Disable Channel (Base+0x000F) */ + vuint32_t R; + struct { + vuint32_t CHDIS31:1; + vuint32_t CHDIS30:1; + vuint32_t CHDIS29:1; + vuint32_t CHDIS28:1; + vuint32_t CHDIS27:1; + vuint32_t CHDIS26:1; + vuint32_t CHDIS25:1; + vuint32_t CHDIS24:1; + vuint32_t CHDIS23:1; + vuint32_t CHDIS22:1; + vuint32_t CHDIS21:1; + vuint32_t CHDIS20:1; + vuint32_t CHDIS19:1; + vuint32_t CHDIS18:1; + vuint32_t CHDIS17:1; + vuint32_t CHDIS16:1; + vuint32_t CHDIS15:1; + vuint32_t CHDIS14:1; + vuint32_t CHDIS13:1; + vuint32_t CHDIS12:1; + vuint32_t CHDIS11:1; + vuint32_t CHDIS10:1; + vuint32_t CHDIS9:1; + vuint32_t CHDIS8:1; + vuint32_t CHDIS7:1; + vuint32_t CHDIS6:1; + vuint32_t CHDIS5:1; + vuint32_t CHDIS4:1; + vuint32_t CHDIS3:1; + vuint32_t CHDIS2:1; + vuint32_t CHDIS1:1; + vuint32_t CHDIS0:1; + } B; + } UCDIS; + + vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */ + + struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */ + + vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */ + +}; /* end of EMIOS_tag */ + +/****************************************************************************/ +/* MODULE : SSCM */ +/****************************************************************************/ +struct SSCM_tag{ + + union { /* Status (Base+0x0000) */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t PUB:1; + vuint16_t SEC:1; + vuint16_t:1; + vuint16_t BMODE:3; + vuint16_t:5; + } B; + } STATUS; + + union { /* System Memory Configuration (Base+0x002) */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t PRSZ:5; + vuint16_t PVLB:1; + vuint16_t DTSZ:4; + vuint16_t DVLD:1; + } B; + } MEMCONFIG; + + vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */ + + union { /* Error Configuration (Base+0x0006) */ + vuint16_t R; + struct { + vuint16_t :14; + vuint16_t PAE:1; + vuint16_t RAE:1; + } B; + } ERROR; + + union { /* Debug Status Port (Base+0x0008) */ + vuint16_t R; + struct { + vuint16_t :13; + vuint16_t DEBUG_MODE:3; + } B; + } DEBUGPORT; + + vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */ + + union { /* Password Comparison High Word (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t PWD_HI:32; + } B; + } PWCMPH; + + union { /* Password Comparison Low Word (Base+0x0010)*/ + vuint32_t R; + struct { + vuint32_t PWD_LO:32; + } B; + } PWCMPL; + +}; /* end of SSCM_tag */ + +/****************************************************************************/ +/* MODULE : ME */ +/****************************************************************************/ +struct ME_tag{ + + union { /* Global Status (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t S_CURRENTMODE:4; + vuint32_t S_MTRANS:1; + vuint32_t S_DC:1; + vuint32_t :2; + vuint32_t S_PDO:1; + vuint32_t :2; + vuint32_t S_MVR:1; + vuint32_t S_DFLA:2; + vuint32_t S_CFLA:2; + vuint32_t :9; + vuint32_t S_FMPLL:1; + vuint32_t S_FXOSC:1; + vuint32_t S_FIRC:1; + vuint32_t S_SYSCLK:4; + } B; + } GS; + + union { /* Mode Control (Base+0x004) */ + vuint32_t R; + struct { + vuint32_t TARGET_MODE:4; + vuint32_t :12; + vuint32_t KEY:16; + } B; + } MCTL; + + union { /* Mode Enable (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :18; + vuint32_t STANDBY:1; + vuint32_t :2; + vuint32_t STOP:1; + vuint32_t :1; + vuint32_t HALT:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } MER; + + union { /* Interrupt Status (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t :28; + vuint32_t I_ICONF:1; + vuint32_t I_IMODE:1; + vuint32_t I_SAFE:1; + vuint32_t I_MTC:1; + } B; + } IS; + + union { /* Interrupt Mask (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t :28; + vuint32_t M_ICONF:1; + vuint32_t M_IMODE:1; + vuint32_t M_SAFE:1; + vuint32_t M_MTC:1; + } B; + } IM; + + union { /* Invalid Mode Transition Status (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :27; + vuint32_t S_MTI:1; + vuint32_t S_MRI:1; + vuint32_t S_DMA:1; + vuint32_t S_NMA:1; + vuint32_t S_SEA:1; + } B; + } IMTS; + + union { /* Debug Mode Transition Status (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t MPH_BUSY:1; + vuint32_t :2; + vuint32_t PMC_PROG:1; + vuint32_t CORE_DBG:1; + vuint32_t :2; + vuint32_t SMR:1; + vuint32_t :1; + vuint32_t FMPLL_SC:1; + vuint32_t FXOSC_SC:1; + vuint32_t FIRC_SC:1; + vuint32_t :1; + vuint32_t SYSCLK_SW:1; + vuint32_t DFLASH_SC:1; + vuint32_t CFLASH_SC:1; + vuint32_t CDP_PRPH_0_143:1; + vuint32_t :3; + vuint32_t CDP_PRPH_96_127:1; + vuint32_t CDP_PRPH_64_95:1; + vuint32_t CDP_PRPH_32_63:1; + vuint32_t CDP_PRPH_0_31:1; + } B; + } DMTS; + + vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */ + + union { /* Reset Mode Configuration (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } RESET; + + union { /* Test Mode Configuration (Base+0x0024) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } TEST; + + union { /* Safe Mode Configuration (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } SAFE; + + union { /* DRUN Mode Configuration (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } DRUN; + + union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } RUN[4]; + + union { /* HALT Mode Configuration (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } HALT; + + vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */ + + union { /* STOP Mode Configuration (Base+0x0048) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } STOP; + + vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */ + + union { /* STANDBY Mode Configuration (Base+0x0054) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t PDO:1; + vuint32_t :2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t :9; + vuint32_t FMPLLON:1; + vuint32_t FXOSCON:1; + vuint32_t FIRCON:1; + vuint32_t SYSCLK:4; + } B; + } STANDBY; + + vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */ + + union { + vuint32_t R; + struct { /* Peripheral Status 0 (Base+0x0060) */ + vuint32_t :8; + vuint32_t S_DMA_CH_MUX:1; + vuint32_t :6; + vuint32_t S_FLEXCAN0:1; + vuint32_t :10; + vuint32_t S_DSPI1:1; + vuint32_t S_DSPI0:1; + vuint32_t :4; + } B; + } PS0; + + union { /* Peripheral Status 1 (Base+0x0064)*/ + vuint32_t R; + struct { + vuint32_t :6; + vuint32_t S_CTU:1; + vuint32_t :6; + vuint32_t S_LINFLEX2:1; + vuint32_t S_LINFLEX1:1; + vuint32_t S_LINFLEX0:1; + vuint32_t :14; + vuint32_t S_ADC1:1; + vuint32_t :1; + } B; + } PS1; + + union { /* Peripheral Status 2 (Base+0x0068) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t S_PIT_RTI:1; + vuint32_t S_RTC_API:1; + vuint32_t :18; + vuint32_t S_EMIOS0:1; + vuint32_t :2; + vuint32_t S_WKPU:1; + vuint32_t S_SIUL:1; + vuint32_t :4; + } B; + } PS2; + + union { /* Peripheral Status 3 (Base+0x006C) */ + vuint32_t R; + struct { + vuint32_t :23; + vuint32_t S_CMU:1; + vuint32_t :8; + } B; + } PS3; + + vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */ + + union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */ + vuint32_t R; + struct { + vuint32_t :24; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } RUNPC[8]; + + union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */ + vuint32_t R; + struct { + vuint32_t :18; + vuint32_t STANDBY:1; + vuint32_t :2; + vuint32_t STOP:1; + vuint32_t :1; + vuint32_t HALT:1; + vuint32_t :8; + } B; + } LPPC[8]; + + + /* Note on PCTL registers: There are only some PCTL implemented in */ + /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */ + /* are defined as an array (ie ME.PCTL[x].R). This means you have */ + /* to be careful when addressing these registers in order not to */ + /* access a PCTL that is not implemented. Following are available: */ + /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 52, 51, 50, 49,48, */ + /* 44, 33, 32, 23, 21-16, 9-4 */ + + union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t DBG_F:1; + vuint8_t LP_CFG:3; + vuint8_t RUN_CFG:3; + } B; + } PCTL[105]; + +}; /* end of ME_tag */ + +/****************************************************************************/ +/* MODULE : CGM */ +/****************************************************************************/ +struct CGM_tag{ + /* + The "CGM" has fairly wide coverage and essentially includes everything in + + chapter 6/7 of the Bolero Reference Manual: + + Base Address | Clock Sources + + ----------------------------- + + 0xC3FE0000 | FXOSC_CTL + + 0xC3FE0040 | SXOSC_CTL + + 0xC3FE0060 | FIRC_CTL + + 0xC3FE0080 | SIRC_CTL + + 0xC3FE00A0 | FMPLL + + 0xC3FE00C0 | CGM Block 1 + + 0xC3FE0100 | CMU + + 0xC3FE0120 | CGM Block 2 + + + + In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 + + */ + /* FXOSC - 0xC3FE_0000*/ + union { /* Fast OSC Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t :7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t :2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t:7; + } B; + } FXOSC_CTL; + + + /* Reserved Space between end of FXOSC and start SXOSC */ + vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */ + + + /* SXOSC - 0xC3FE_0040*/ + union { /* Slow Osc Control (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t :7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t :2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t :5; + vuint32_t S_OSC:1; + vuint32_t OSCON:1; + } B; + } SXOSC_CTL; + + + /* Reserved space between end of SXOSC and start of FIRC */ + vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */ + + + /* FIRC - 0xC3FE_0060 */ + union { /* Fast IRC Control (Base+0x0060) */ + vuint32_t R; + struct { + vuint32_t :10; + vuint32_t RCTRIM:6; + vuint32_t :3; + vuint32_t RCDIV:5; + vuint32_t :2; + vuint32_t FIRCON_STDBY:1; + vuint32_t :5; + } B; + } FIRC_CTL; + + + /* Reserved space between end of FIRC and start of SIRC */ + vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */ + + + /* SIRC - 0xC3FE_0080 */ + union { /* Slow IRC Control (Base+0x0080) */ + vuint32_t R; + struct { + vuint32_t :11; + vuint32_t SIRCTRIM:5; + vuint32_t :3; + vuint32_t SIRCDIV:5; + vuint32_t :3; + vuint32_t S_SIRC:1; + vuint32_t :3; + vuint32_t SIRCON_STDBY:1; + } B; + } SIRC_CTL; + + + /* Reserved space between end of SIRC and start of FMPLL */ + vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */ + + + /* FMPLL - 0xC3FE_00A0 */ + union { /* FMPLL Control (Base+0x00A0) */ + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t IDF:4; + vuint32_t ODF:2; + vuint32_t:1; + vuint32_t NDIV:7; + vuint32_t:7; + vuint32_t EN_PLL_SW:1; + vuint32_t MODE:1; + vuint32_t UNLOCK_ONCE:1; + vuint32_t:1; + vuint32_t I_LOCK:1; + vuint32_t S_LOCK:1; + vuint32_t PLL_FAIL_MASK:1; + vuint32_t PLL_FAIL_FLAG:1; + vuint32_t:1; + } B; + } FMPLL_CR; + + union { /* FMPLL Modulation (Base+0x00A4) */ + vuint32_t R; + struct { + vuint32_t STRB_BYPASS:1; + vuint32_t :1; + vuint32_t SPRD_SEL:1; + vuint32_t MOD_PERIOD:13; + vuint32_t FM_EN:1; + vuint32_t INC_STEP:15; + } B; + } FMPLL_MR; + + + /* Reserved space between end of FMPLL and start of CGM Block 1 */ + vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */ + + /* CMU - 0xC3FE_0100 */ + union { /* CMU Control Status (Base+0x0100) */ + vuint32_t R; + struct { + vuint32_t :8; + vuint32_t SFM:1; + vuint32_t :13; + vuint32_t CLKSEL1:2; + vuint32_t :5; + vuint32_t RCDIV:2; + vuint32_t CME_A:1; + } B; + } CMU_CSR; + + union { /* CMU Frequency Display (Base+0x0104) */ + vuint32_t R; + struct { + vuint32_t :12; + vuint32_t FD:20; + } B; + } CMU_FDR; + + union { /* CMU High Freq Reference FMPLL (Base+0x0108) */ + vuint32_t R; + struct { + vuint32_t :20; + vuint32_t HFREF:12; + } B; + } CMU_HFREFR; + + union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */ + vuint32_t R; + struct { + vuint32_t :20; + vuint32_t LFREF:12; + } B; + } CMU_LFREFR; + + union { /* CMU Interrupt Status (Base+0x0110) */ + vuint32_t R; + struct { + vuint32_t :29; + vuint32_t FHHI:1; // *_A not present in RM + vuint32_t FLLI:1; // *_A not present in RM + vuint32_t OLRI:1; + } B; + } CMU_ISR; + + /* Reserved space where IMR was previously positioned */ + vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */ + + union { /* CMU Measurement Duration (Base+0x0118) */ + vuint32_t R; + struct { + vuint32_t :12; + vuint32_t MD:20; + } B; + } CMU_MDR; + + + /* Reserved space between end of CMU and start of CGM Block 2 */ + vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */ + + union { /* GCM Output Clock Enable (Base+0x0370) */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t EN:1; + } B; + } OC_EN; + + union { /* CGM Output Clock Division Sel (Base+0x0374) */ + vuint32_t R; + struct { + vuint32_t :2; + vuint32_t SELDIV:2; + vuint32_t SELCTL:4; + vuint32_t :24; + } B; + } OCDS_SC; + + union { /* CGM System Clock Select Status (Base+0x0378) */ + vuint32_t R; + struct { + vuint32_t :4; + vuint32_t SELSTAT:4; + vuint32_t :24; + } B; + } SC_SS; + + union { /* CGM Sys Clk Div Config0 (Base+0x037C) */ + vuint8_t R; + struct { + vuint8_t DE0:1; + vuint8_t :3; + vuint8_t DIV0:4; + } B; + } SC_DC0; + + union { /* CGM Sys Clk Div Config1 (Base+0x037D) */ + vuint8_t R; + struct { + vuint8_t DE1:1; + vuint8_t :3; + vuint8_t DIV1:4; + } B; + } SC_DC1; + + union { /* CGM Sys Clk Div Config1 (Base+0x037E) */ + vuint8_t R; + struct { + vuint8_t DE2:1; + vuint8_t :3; + vuint8_t DIV2:4; + } B; + } SC_DC2; + + vuint8_t CGM_reserved7[1]; /*Reserved 1 byte (Base+0x037F) */ + + union { /* CGM Aux clock select control register (Base+0x0380) */ + vuint32_t R; + struct { + vuint32_t :4; + vuint32_t SELCTL:4; + vuint32_t :24; + } B; + } AC0_SC; + + + +}; /* end of CGM_tag */ + +/****************************************************************************/ +/* MODULE : RGM base address - 0xC3FE_4000 */ +/****************************************************************************/ +struct RGM_tag{ + + union { /* Functional Event Status (Base+0x0000) */ + vuint16_t R; + struct { + vuint16_t F_EXR:1; + vuint16_t :6; + vuint16_t F_FLASH:1; + vuint16_t F_LVD45:1; + vuint16_t F_CMU_FHL:1; + vuint16_t F_CMU_OLR:1; + vuint16_t F_FMPLL:1; + vuint16_t F_CHKSTOP:1; + vuint16_t F_SOFT_FUNC :1; + vuint16_t F_CORE:1; + vuint16_t F_JTAG:1; + } B; + } FES; + + union { /* Destructive Event Status (Base+0x0002) */ + vuint16_t R; + struct { + vuint16_t F_POR:1; + vuint16_t :10; + vuint16_t F_LVD27_VREG:1; + vuint16_t F_LVD27:1; + vuint16_t F_SWT:1; + vuint16_t F_LVD12_PD1:1; + vuint16_t F_LVD12_PD0:1; + } B; + } DES; + + union { /* Functional Event Reset Disable (+0x0004) */ + vuint16_t R; + struct { + vuint16_t D_EXR:1; + vuint16_t :6; + vuint16_t D_FLASH:1; + vuint16_t D_LVD45:1; + vuint16_t D_CMU_FHL:1; + vuint16_t D_CMU_OLR:1; + vuint16_t D_FMPLL:1; + vuint16_t D_CHKSTOP:1; + vuint16_t D_SOFT_FUNC:1; + vuint16_t D_CORE:1; + vuint16_t D_JTAG:1; + } B; + } FERD; + + union { /* Destructive Event Reset Disable (Base+0x0006)*/ + vuint16_t R; + struct { + vuint16_t :11; + vuint16_t D_LVD27_VREG:1; + vuint16_t D_LVD27:1; + vuint16_t D_SWT:1; + vuint16_t D_LVD12_PD1:1; + vuint16_t D_LVD12_PD0:1; + } B; + } DERD; + + vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */ + + union { /* Functional Event Alt Request (Base+0x0010) */ + vuint16_t R; + struct { + vuint16_t AR_EXR:1; + vuint16_t:6; + vuint16_t AR_FLASH:1; + vuint16_t AR_LVD45:1; + vuint16_t AR_CMU_FHL:1; + vuint16_t AR_CMU_OLR:1; + vuint16_t AR_FMPLL:1; + vuint16_t AR_CHKSTOP:1; + vuint16_t AR_SOFT_FUNC:1; + vuint16_t AR_CORE:1; + vuint16_t AR_JTAG:1; + } B; + } FEAR; + + union { /* Destructive Event Alt Request (Base+0x0012) */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t AR_LVD27_VREG:1; + vuint16_t AR_LVD27:1; + vuint16_t AR_SWT:1; + vuint16_t AR_LVD12_PD1:1; + vuint16_t AR_LVD12_PD0:1; + } B; + } DEAR; /* Destructive Event Alternate Request */ + + vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */ + + union { /* Functional Event Short Sequence (+0x0018) */ + vuint16_t R; + struct { + vuint16_t SS_EXR:1; + vuint16_t :6; + vuint16_t SS_FLASH:1; + vuint16_t SS_LVD45:1; + vuint16_t SS_CMU_FHL:1; + vuint16_t SS_CMU_OLR:1; + vuint16_t SS_FMPLL:1; + vuint16_t SS_CHKSTOP:1; + vuint16_t SS_SOFT_FUNC:1; + vuint16_t SS_CORE:1; + vuint16_t SS_JTAG:1; + } B; + } FESS; + + union { /* STANDBY reset sequence (Base+0x001A) */ + vuint16_t R; + struct { + vuint16_t :8; + vuint16_t BOOT_FROM_BKP_RAM:1; + vuint16_t :7; + } B; + } STDBY; + + union { /* Functional Bidirectional Reset En (+0x001C) */ + vuint16_t R; + struct { + vuint16_t BE_EXR:1; + vuint16_t :6; + vuint16_t BE_FLASH:1; + vuint16_t BE_LVD45:1; + vuint16_t BE_CMU_FHL:1; + vuint16_t BE_CMU_OLR:1; + vuint16_t BE_FMPLL:1; + vuint16_t BE_CHKSTOP:1; + vuint16_t BE_SOFT_FUNC:1; + vuint16_t BE_CORE:1; + vuint16_t BE_JTAG:1; + } B; + } FBRE; + +}; /* end of RGM_tag */ +/****************************************************************************/ +/* MODULE : PCU (base address 0xC3FE_8000) */ +/****************************************************************************/ +struct PCU_tag{ + + union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */ + vuint32_t R; + struct { + vuint32_t :18; + vuint32_t STBY:1; + vuint32_t :2; + vuint32_t STOP:1; + vuint32_t :1; + vuint32_t HALT:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RST:1; + } B; + } PCONF[4]; + + vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */ + + union { /* PCU Power Domain Status (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t :28; + vuint32_t PD3:1; + vuint32_t PD2:1; + vuint32_t PD1:1; + vuint32_t PD0:1; + } B; + } PSTAT; + + vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */ + + + /* Following register is from Voltage Regulators chapter of RM */ + + union { /* PCU Voltage Regulator Control (Base+0x0080) */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t MASK_LVDHV5:1; + } B; + } VREG_CTL; /* Changed from VCTL for consistency with other regs here */ + + }; /* end of PCU_tag */ +/****************************************************************************/ +/* MODULE : RTC/API */ +/****************************************************************************/ +struct RTC_tag{ + + union { /* RTC Supervisor Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t SUPV:1; + vuint32_t :31; + } B; + } RTCSUPV ; + + union { /* RTC Control (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t CNTEN:1; + vuint32_t RTCIE:1; + vuint32_t FRZEN:1; + vuint32_t ROVREN:1; + vuint32_t RTCVAL:12; + vuint32_t APIEN:1; + vuint32_t APIIE:1; + vuint32_t CLKSEL:2; + vuint32_t DIV512EN:1; + vuint32_t DIV32EN:1; + vuint32_t APIVAL:10; + } B; + } RTCC; + + union { /* RTC Status (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :2; + vuint32_t RTCF:1; + vuint32_t :15; + vuint32_t APIF:1; + vuint32_t :2; + vuint32_t ROVRF:1; + vuint32_t :10; + } B; + } RTCS; + + union { /* RTC Counter (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t RTCCNT:32; + } B; + } RTCCNT; + +}; /* end of RTC_tag */ + +/****************************************************************************/ +/* MODULE : PIT (base address - 0xC3FF_FFFF) */ +/****************************************************************************/ + struct PIT_tag { + + union { /* PIT Module Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; + + vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */ + + /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */ + struct { + + union { /* PIT Timer Load Value (Offset+0x0000) */ + vuint32_t R; + struct { + vuint32_t TSV:32; + } B; + } LDVAL; + + union { /* PIT Current Timer Value (Offset+0x0004) */ + vuint32_t R; + struct { + vuint32_t TVL:32; + } B; + } CVAL; + + union { /* PIT Timer Control (Offset+0x0008) */ + vuint32_t R; + struct { + vuint32_t :30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; + + union { /* PIT Timer Control (Offset+0x0008) */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t TIF:1; + } B; + } TFLG; + + }CH[8]; /* End of PIT Timer Channels */ + +}; /* end of PIT_tag */ + +/****************************************************************************/ +/* MODULE : ADC1 (12 Bit) */ +/****************************************************************************/ +struct ADC1_tag { + + union { /* ADC1 Main Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t OWREN:1; + vuint32_t WLSIDE:1; + vuint32_t MODE:1; + vuint32_t:4; + vuint32_t NSTART:1; + vuint32_t:1; + vuint32_t JTRGEN:1; + vuint32_t JEDGE:1; + vuint32_t JSTART:1; + vuint32_t:2; + vuint32_t CTUEN:1; + vuint32_t:8; + vuint32_t ADCLKSEL:1; + vuint32_t ABORTCHAIN:1; + vuint32_t ABORT:1; + vuint32_t ACKO:1; + vuint32_t:4; + vuint32_t PWDN:1; + } B; + } MCR; + + union { /* ADC1 Main Status (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t NSTART:1; + vuint32_t JABORT:1; + vuint32_t:2; + vuint32_t JSTART:1; + vuint32_t:3; + vuint32_t CTUSTART:1; + vuint32_t CHADDR:7; + vuint32_t:3; + vuint32_t ACKO:1; + vuint32_t:2; + vuint32_t ADCSTATUS:3; + } B; + } MSR; + + vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */ + + union { /* ADC1 Interrupt Status (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t EOCTU:1; + vuint32_t JEOC:1; + vuint32_t JECH:1; + vuint32_t EOC:1; + vuint32_t ECH:1; + } B; + } ISR; + + union { /* ADC1 Channel Pending 0 (Base+0x0014) */ + vuint32_t R; /* (For precision channels) */ + struct { + vuint32_t :16; + vuint32_t EOC_CH15:1; + vuint32_t EOC_CH14:1; + vuint32_t EOC_CH13:1; + vuint32_t EOC_CH12:1; + vuint32_t EOC_CH11:1; + vuint32_t EOC_CH10:1; + vuint32_t EOC_CH9:1; + vuint32_t EOC_CH8:1; + vuint32_t EOC_CH7:1; + vuint32_t EOC_CH6:1; + vuint32_t EOC_CH5:1; + vuint32_t EOC_CH4:1; + vuint32_t EOC_CH3:1; + vuint32_t EOC_CH2:1; + vuint32_t EOC_CH1:1; + vuint32_t EOC_CH0:1; + } B; + } CEOCFR0; + + union { /* ADC1 Channel Pending 1 (Base+0x0018) */ + vuint32_t R; /* (For standard Channels) */ + struct { + vuint32_t:19; + vuint32_t EOC_CH44:1; + vuint32_t EOC_CH43:1; + vuint32_t EOC_CH42:1; + vuint32_t EOC_CH41:1; + vuint32_t EOC_CH40:1; + vuint32_t EOC_CH39:1; + vuint32_t EOC_CH38:1; + vuint32_t EOC_CH37:1; + vuint32_t EOC_CH36:1; + vuint32_t EOC_CH35:1; + vuint32_t EOC_CH34:1; + vuint32_t EOC_CH33:1; + vuint32_t EOC_CH32:1; + } B; + } CEOCFR1; + + union { /* ADC1 Channel Pending 2 (Base+0x001C) */ + vuint32_t R; /* (For External Channels) */ + struct { + vuint32_t EOC_CH95:1; + vuint32_t EOC_CH94:1; + vuint32_t EOC_CH93:1; + vuint32_t EOC_CH92:1; + vuint32_t EOC_CH91:1; + vuint32_t EOC_CH90:1; + vuint32_t EOC_CH89:1; + vuint32_t EOC_CH88:1; + vuint32_t EOC_CH87:1; + vuint32_t EOC_CH86:1; + vuint32_t EOC_CH85:1; + vuint32_t EOC_CH84:1; + vuint32_t EOC_CH83:1; + vuint32_t EOC_CH82:1; + vuint32_t EOC_CH81:1; + vuint32_t EOC_CH80:1; + vuint32_t EOC_CH79:1; + vuint32_t EOC_CH78:1; + vuint32_t EOC_CH77:1; + vuint32_t EOC_CH76:1; + vuint32_t EOC_CH75:1; + vuint32_t EOC_CH74:1; + vuint32_t EOC_CH73:1; + vuint32_t EOC_CH72:1; + vuint32_t EOC_CH71:1; + vuint32_t EOC_CH70:1; + vuint32_t EOC_CH69:1; + vuint32_t EOC_CH68:1; + vuint32_t EOC_CH67:1; + vuint32_t EOC_CH66:1; + vuint32_t EOC_CH65:1; + vuint32_t EOC_CH64:1; + } B; + } CEOCFR2; + + + union { /* ADC1 Interrupt Mask (Base+0020) */ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t MSKEOCTU:1; + vuint32_t MSKJEOC:1; + vuint32_t MSKJECH:1; + vuint32_t MSKEOC:1; + vuint32_t MSKECH:1; + } B; + } IMR; + + union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */ + vuint32_t R; /* (For Precision Channels) */ + struct { + vuint32_t:16; + vuint32_t CIM15:1; + vuint32_t CIM14:1; + vuint32_t CIM13:1; + vuint32_t CIM12:1; + vuint32_t CIM11:1; + vuint32_t CIM10:1; + vuint32_t CIM9:1; + vuint32_t CIM8:1; + vuint32_t CIM7:1; + vuint32_t CIM6:1; + vuint32_t CIM5:1; + vuint32_t CIM4:1; + vuint32_t CIM3:1; + vuint32_t CIM2:1; + vuint32_t CIM1:1; + vuint32_t CIM0:1; + } B; + } CIMR0; + + union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */ + vuint32_t R; /* (For Standard Channels) */ + struct { + vuint32_t:19; + vuint32_t CIM44:1; + vuint32_t CIM43:1; + vuint32_t CIM42:1; + vuint32_t CIM41:1; + vuint32_t CIM40:1; + vuint32_t CIM39:1; + vuint32_t CIM38:1; + vuint32_t CIM37:1; + vuint32_t CIM36:1; + vuint32_t CIM35:1; + vuint32_t CIM34:1; + vuint32_t CIM33:1; + vuint32_t CIM32:1; + } B; + } CIMR1; + + union { /* ADC1 Channel Interrupt Mask 2 (Base+0x002C) */ + vuint32_t R; /* (For External Mux'd Channels) */ + struct { + vuint32_t CIM95:1; + vuint32_t CIM94:1; + vuint32_t CIM93:1; + vuint32_t CIM92:1; + vuint32_t CIM91:1; + vuint32_t CIM90:1; + vuint32_t CIM89:1; + vuint32_t CIM88:1; + vuint32_t CIM87:1; + vuint32_t CIM86:1; + vuint32_t CIM85:1; + vuint32_t CIM84:1; + vuint32_t CIM83:1; + vuint32_t CIM82:1; + vuint32_t CIM81:1; + vuint32_t CIM80:1; + vuint32_t CIM79:1; + vuint32_t CIM78:1; + vuint32_t CIM77:1; + vuint32_t CIM76:1; + vuint32_t CIM75:1; + vuint32_t CIM74:1; + vuint32_t CIM73:1; + vuint32_t CIM72:1; + vuint32_t CIM71:1; + vuint32_t CIM70:1; + vuint32_t CIM69:1; + vuint32_t CIM68:1; + vuint32_t CIM67:1; + vuint32_t CIM66:1; + vuint32_t CIM65:1; + vuint32_t CIM64:1; + } B; + } CIMR2; + + + union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t WDG2H:1; + vuint32_t WDG2L:1; + vuint32_t WDG1H:1; + vuint32_t WDG1L:1; + vuint32_t WDG0H:1; + vuint32_t WDG0L:1; + } B; + } WTISR; + + union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t MSKWDG2H:1; + vuint32_t MSKWDG2L:1; + vuint32_t MSKWDG1H:1; + vuint32_t MSKWDG1L:1; + vuint32_t MSKWDG0H:1; + vuint32_t MSKWDG0L:1; + } B; + } WTIMR; + + vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */ + + union { /* ADC1 DMA Enable (Base+0x0040) */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t DCLR:1; + vuint32_t DMAEN:1; + } B; + } DMAE; + + union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */ + vuint32_t R; /* (for precision channels) */ + struct { + vuint32_t:16; + vuint32_t DMA15:1; + vuint32_t DMA14:1; + vuint32_t DMA13:1; + vuint32_t DMA12:1; + vuint32_t DMA11:1; + vuint32_t DMA10:1; + vuint32_t DMA9:1; + vuint32_t DMA8:1; + vuint32_t DMA7:1; + vuint32_t DMA6:1; + vuint32_t DMA5:1; + vuint32_t DMA4:1; + vuint32_t DMA3:1; + vuint32_t DMA2:1; + vuint32_t DMA1:1; + vuint32_t DMA0:1; + } B; + } DMAR0; + + union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */ + vuint32_t R; /* (for precision channels) */ + struct { + vuint32_t:19; + vuint32_t DMA44:1; + vuint32_t DMA43:1; + vuint32_t DMA42:1; + vuint32_t DMA41:1; + vuint32_t DMA40:1; + vuint32_t DMA39:1; + vuint32_t DMA38:1; + vuint32_t DMA37:1; + vuint32_t DMA36:1; + vuint32_t DMA35:1; + vuint32_t DMA34:1; + vuint32_t DMA33:1; + vuint32_t DMA32:1; + } B; + } DMAR1; + + union { /* ADC1 DMA Channel Select 2 (Base+0x004C) */ + vuint32_t R; /* (for External channels) */ + struct { + vuint32_t DMA95:1; + vuint32_t DMA94:1; + vuint32_t DMA93:1; + vuint32_t DMA92:1; + vuint32_t DMA91:1; + vuint32_t DMA90:1; + vuint32_t DMA89:1; + vuint32_t DMA88:1; + vuint32_t DMA87:1; + vuint32_t DMA86:1; + vuint32_t DMA85:1; + vuint32_t DMA84:1; + vuint32_t DMA83:1; + vuint32_t DMA82:1; + vuint32_t DMA81:1; + vuint32_t DMA80:1; + vuint32_t DMA79:1; + vuint32_t DMA78:1; + vuint32_t DMA77:1; + vuint32_t DMA76:1; + vuint32_t DMA75:1; + vuint32_t DMA74:1; + vuint32_t DMA73:1; + vuint32_t DMA72:1; + vuint32_t DMA71:1; + vuint32_t DMA70:1; + vuint32_t DMA69:1; + vuint32_t DMA68:1; + vuint32_t DMA67:1; + vuint32_t DMA66:1; + vuint32_t DMA65:1; + vuint32_t DMA64:1; + } B; + } DMAR2; + + vuint8_t ADC1_reserved4[16]; /* Reserved 16 bytes (Base+0x0048-0x005F) */ + + /* Note the threshold registers are not implemented as an array for */ + /* concistency with ADC0 header section */ + + union { /* ADC1 Threshold 0 (Base+0x0060) */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRHLR0; + + union { /* ADC1 Threshold 1 (Base+0x0064) */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRHLR1; + + union { /* ADC1 Threshold 2 (Base+0x0068) */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRHLR2; + + vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */ + + union { /* ADC1 Presampling Control (Base+0x0080) */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t PREVAL2:2; + vuint32_t PREVAL1:2; + vuint32_t PREVAL0:2; + vuint32_t PRECONV:1; + } B; + } PSCR; + + union { /* ADC1 Presampling 0 (Base+0x0084) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t:16; + vuint32_t PRES15:1; + vuint32_t PRES14:1; + vuint32_t PRES13:1; + vuint32_t PRES12:1; + vuint32_t PRES11:1; + vuint32_t PRES10:1; + vuint32_t PRES9:1; + vuint32_t PRES8:1; + vuint32_t PRES7:1; + vuint32_t PRES6:1; + vuint32_t PRES5:1; + vuint32_t PRES4:1; + vuint32_t PRES3:1; + vuint32_t PRES2:1; + vuint32_t PRES1:1; + vuint32_t PRES0:1; + } B; + } PSR0; + + union { /* ADC1 Presampling 1 (Base+0x0088) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t:19; + vuint32_t PRES44:1; + vuint32_t PRES43:1; + vuint32_t PRES42:1; + vuint32_t PRES41:1; + vuint32_t PRES40:1; + vuint32_t PRES39:1; + vuint32_t PRES38:1; + vuint32_t PRES37:1; + vuint32_t PRES36:1; + vuint32_t PRES35:1; + vuint32_t PRES34:1; + vuint32_t PRES33:1; + vuint32_t PRES32:1; + } B; + } PSR1; + + + union { /* ADC1 Presampling 2 (Base+0x008C) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t PRES95:1; + vuint32_t PRES94:1; + vuint32_t PRES93:1; + vuint32_t PRES92:1; + vuint32_t PRES91:1; + vuint32_t PRES90:1; + vuint32_t PRES89:1; + vuint32_t PRES88:1; + vuint32_t PRES87:1; + vuint32_t PRES86:1; + vuint32_t PRES85:1; + vuint32_t PRES84:1; + vuint32_t PRES83:1; + vuint32_t PRES82:1; + vuint32_t PRES81:1; + vuint32_t PRES80:1; + vuint32_t PRES79:1; + vuint32_t PRES78:1; + vuint32_t PRES77:1; + vuint32_t PRES76:1; + vuint32_t PRES75:1; + vuint32_t PRES74:1; + vuint32_t PRES73:1; + vuint32_t PRES72:1; + vuint32_t PRES71:1; + vuint32_t PRES70:1; + vuint32_t PRES69:1; + vuint32_t PRES68:1; + vuint32_t PRES67:1; + vuint32_t PRES66:1; + vuint32_t PRES65:1; + vuint32_t PRES64:1; + } B; + } PSR2; + + + vuint8_t ADC1_reserved6[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */ + + /* Note the following CTR registers are NOT implemented as an array to */ + /* try and maintain some concistency through the header file */ + /* (The registers are however identical) */ + + union { /* ADC1 Conversion Timing 0 (Base+0x0094) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; + vuint32_t:1; + vuint32_t OFFSHIFT:2; + vuint32_t:1; + vuint32_t INPCMP:2; + vuint32_t:1; + vuint32_t INPSAMP:8; + } B; + } CTR0; + + union { /* ADC1 Conversion Timing 1 (Base+0x0098) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; + vuint32_t:4; + vuint32_t INPCMP:2; + vuint32_t:1; + vuint32_t INPSAMP:8; + } B; + } CTR1; + + + union { /* ADC1 Conversion Timing 2 (Base+0x009C) */ + vuint32_t R; /* (External channels) */ + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; + vuint32_t:4; + vuint32_t INPCMP:2; + vuint32_t:1; + vuint32_t INPSAMP:8; + } B; + } CTR2; + + vuint8_t ADC1_reserved7[8]; /* Reserved 12 bytes (Base+0x009C-0x00A3) */ + + union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t :16; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } NCMR0; + + union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t:19; + vuint32_t CH44:1; + vuint32_t CH43:1; + vuint32_t CH42:1; + vuint32_t CH41:1; + vuint32_t CH40:1; + vuint32_t CH39:1; + vuint32_t CH38:1; + vuint32_t CH37:1; + vuint32_t CH36:1; + vuint32_t CH35:1; + vuint32_t CH34:1; + vuint32_t CH33:1; + vuint32_t CH32:1; + } B; + } NCMR1; + + + union { /* ADC1 Normal Conversion Mask 2 (Base+0x00AC) */ + vuint32_t R; /* (External channels) */ + struct { + vuint32_t CH95:1; + vuint32_t CH94:1; + vuint32_t CH93:1; + vuint32_t CH92:1; + vuint32_t CH91:1; + vuint32_t CH90:1; + vuint32_t CH89:1; + vuint32_t CH88:1; + vuint32_t CH87:1; + vuint32_t CH86:1; + vuint32_t CH85:1; + vuint32_t CH84:1; + vuint32_t CH83:1; + vuint32_t CH82:1; + vuint32_t CH81:1; + vuint32_t CH80:1; + vuint32_t CH79:1; + vuint32_t CH78:1; + vuint32_t CH77:1; + vuint32_t CH76:1; + vuint32_t CH75:1; + vuint32_t CH74:1; + vuint32_t CH73:1; + vuint32_t CH72:1; + vuint32_t CH71:1; + vuint32_t CH70:1; + vuint32_t CH69:1; + vuint32_t CH68:1; + vuint32_t CH67:1; + vuint32_t CH66:1; + vuint32_t CH65:1; + vuint32_t CH64:1; + } B; + } NCMR2; + + vuint8_t ADC1_reserved8[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B4) */ + + union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t :16; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } JCMR0; + + union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t :19; + vuint32_t CH44:1; + vuint32_t CH43:1; + vuint32_t CH42:1; + vuint32_t CH41:1; + vuint32_t CH40:1; + vuint32_t CH39:1; + vuint32_t CH38:1; + vuint32_t CH37:1; + vuint32_t CH36:1; + vuint32_t CH35:1; + vuint32_t CH34:1; + vuint32_t CH33:1; + vuint32_t CH32:1; + } B; + } JCMR1; + + + union { /* ADC1 Injected Conversion Mask 2 (Base+0x00BC) */ + vuint32_t R; /* (External channels) */ + struct { + vuint32_t CH95:1; + vuint32_t CH94:1; + vuint32_t CH93:1; + vuint32_t CH92:1; + vuint32_t CH91:1; + vuint32_t CH90:1; + vuint32_t CH89:1; + vuint32_t CH88:1; + vuint32_t CH87:1; + vuint32_t CH86:1; + vuint32_t CH85:1; + vuint32_t CH84:1; + vuint32_t CH83:1; + vuint32_t CH82:1; + vuint32_t CH81:1; + vuint32_t CH80:1; + vuint32_t CH79:1; + vuint32_t CH78:1; + vuint32_t CH77:1; + vuint32_t CH76:1; + vuint32_t CH75:1; + vuint32_t CH74:1; + vuint32_t CH73:1; + vuint32_t CH72:1; + vuint32_t CH71:1; + vuint32_t CH70:1; + vuint32_t CH69:1; + vuint32_t CH68:1; + vuint32_t CH67:1; + vuint32_t CH66:1; + vuint32_t CH65:1; + vuint32_t CH64:1; + } B; + } JCMR2; + + vuint8_t ADC1_reserved9[4]; /* Reserved 4 bytes (Base+0x00C0=0x00C4) */ + + union { /* Decode Signals Delay Register (base+0x00C4)*/ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t DSD:12; + } B; + } DSDR; + + + union { /* Power Down Exit Delay Register (base+0x00C8)*/ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t PDED:8; + } B; + } PDEDR; + + vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */ + + union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */ + vuint32_t R; /* Note CDR[16..31] and [44..63] are reserved 0x0140-0x017F */ + struct { + vuint32_t:12; + vuint32_t VALID:1; + vuint32_t OVERW:1; + vuint32_t RESULT:2; + vuint32_t:4; + vuint32_t CDATA:12; + } B; + } CDR[96]; + + vuint8_t ADC1_reserved11[48]; /* Reserved 48 bytes (Base+0x0280-0x002B0) */ + + union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t WSEL_CH7:4; + vuint32_t WSEL_CH6:4; + vuint32_t WSEL_CH5:4; + vuint32_t WSEL_CH4:4; + vuint32_t WSEL_CH3:4; + vuint32_t WSEL_CH2:4; + vuint32_t WSEL_CH1:4; + vuint32_t WSEL_CH0:4; + } B; + } CWSELR0; + + union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t WSEL_CH15:4; + vuint32_t WSEL_CH14:4; + vuint32_t WSEL_CH13:4; + vuint32_t WSEL_CH12:4; + vuint32_t WSEL_CH11:4; + vuint32_t WSEL_CH10:4; + vuint32_t WSEL_CH9:4; + vuint32_t WSEL_CH8:4; + } B; + } CWSELR1; + + vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */ + + union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t WSEL_CH39:4; + vuint32_t WSEL_CH38:4; + vuint32_t WSEL_CH37:4; + vuint32_t WSEL_CH36:4; + vuint32_t WSEL_CH35:4; + vuint32_t WSEL_CH34:4; + vuint32_t WSEL_CH33:4; + vuint32_t WSEL_CH32:4; + } B; + } CWSELR4; + + union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t:12; + vuint32_t WSEL_CH44:4; + vuint32_t WSEL_CH43:4; + vuint32_t WSEL_CH42:4; + vuint32_t WSEL_CH41:4; + vuint32_t WSEL_CH40:4; + } B; + } CWSELR5; + + vuint8_t ADC1_reserved42[8]; /* Reserved 8 bytes (Base+0x02C8-0x02D0) */ + + union { /* ADC1 Channel Watchdog Select 8 (Base+0x02D0) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t WSEL_CH71:4; + vuint32_t WSEL_CH70:4; + vuint32_t WSEL_CH69:4; + vuint32_t WSEL_CH68:4; + vuint32_t WSEL_CH67:4; + vuint32_t WSEL_CH66:4; + vuint32_t WSEL_CH65:4; + vuint32_t WSEL_CH64:4; + } B; + } CWSELR8; + + union { /* ADC1 Channel Watchdog Select 9 (Base+0x02D4) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t WSEL_CH79:4; + vuint32_t WSEL_CH78:4; + vuint32_t WSEL_CH77:4; + vuint32_t WSEL_CH76:4; + vuint32_t WSEL_CH75:4; + vuint32_t WSEL_CH74:4; + vuint32_t WSEL_CH73:4; + vuint32_t WSEL_CH72:4; + } B; + } CWSELR9; + + union { /* ADC1 Channel Watchdog Select 10 (Base+0x02D8) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t WSEL_CH87:4; + vuint32_t WSEL_CH86:4; + vuint32_t WSEL_CH85:4; + vuint32_t WSEL_CH84:4; + vuint32_t WSEL_CH83:4; + vuint32_t WSEL_CH82:4; + vuint32_t WSEL_CH81:4; + vuint32_t WSEL_CH80:4; + } B; + } CWSELR10; + + union { /* ADC1 Channel Watchdog Select 11 (Base+0x02DC) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t WSEL_CH95:4; + vuint32_t WSEL_CH94:4; + vuint32_t WSEL_CH93:4; + vuint32_t WSEL_CH92:4; + vuint32_t WSEL_CH91:4; + vuint32_t WSEL_CH90:4; + vuint32_t WSEL_CH89:4; + vuint32_t WSEL_CH88:4; + } B; + } CWSELR11; + + + union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */ + vuint32_t R; /* (precision channels) */ + struct { + vuint32_t :16; + vuint32_t CWEN15:1; + vuint32_t CWEN14:1; + vuint32_t CWEN13:1; + vuint32_t CWEN12:1; + vuint32_t CWEN11:1; + vuint32_t CWEN10:1; + vuint32_t CWEN9:1; + vuint32_t CWEN8:1; + vuint32_t CWEN7:1; + vuint32_t CWEN6:1; + vuint32_t CWEN5:1; + vuint32_t CWEN4:1; + vuint32_t CWEN3:1; + vuint32_t CWEN2:1; + vuint32_t CWEN1:1; + vuint32_t CWEN0:1; + } B; + } CWENR0; + + union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */ + vuint32_t R; /* (standard channels) */ + struct { + vuint32_t :19; + vuint32_t CWEN44:1; + vuint32_t CWEN43:1; + vuint32_t CWEN42:1; + vuint32_t CWEN41:1; + vuint32_t CWEN40:1; + vuint32_t CWEN39:1; + vuint32_t CWEN38:1; + vuint32_t CWEN37:1; + vuint32_t CWEN36:1; + vuint32_t CWEN35:1; + vuint32_t CWEN34:1; + vuint32_t CWEN33:1; + vuint32_t CWEN32:1; + } B; + } CWENR1; + + union { /* ADC1 Channel Watchdog Enable2 (Base++0x02E8) */ + vuint32_t R; /* (External channels) */ + struct { + vuint32_t CWEN95:1; + vuint32_t CWEN94:1; + vuint32_t CWEN93:1; + vuint32_t CWEN92:1; + vuint32_t CWEN91:1; + vuint32_t CWEN90:1; + vuint32_t CWEN89:1; + vuint32_t CWEN88:1; + vuint32_t CWEN87:1; + vuint32_t CWEN86:1; + vuint32_t CWEN85:1; + vuint32_t CWEN84:1; + vuint32_t CWEN83:1; + vuint32_t CWEN82:1; + vuint32_t CWEN81:1; + vuint32_t CWEN80:1; + vuint32_t CWEN79:1; + vuint32_t CWEN78:1; + vuint32_t CWEN77:1; + vuint32_t CWEN76:1; + vuint32_t CWEN75:1; + vuint32_t CWEN74:1; + vuint32_t CWEN73:1; + vuint32_t CWEN72:1; + vuint32_t CWEN71:1; + vuint32_t CWEN70:1; + vuint32_t CWEN69:1; + vuint32_t CWEN68:1; + vuint32_t CWEN67:1; + vuint32_t CWEN66:1; + vuint32_t CWEN65:1; + vuint32_t CWEN64:1; + } B; + } CWENR2; + + vuint8_t ADC1_reserved14[4]; /* Reserved 4 bytes (Base+0x02EC-0x02F0) */ + + union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t AWORR_CH15:1; + vuint32_t AWORR_CH14:1; + vuint32_t AWORR_CH13:1; + vuint32_t AWORR_CH12:1; + vuint32_t AWORR_CH11:1; + vuint32_t AWORR_CH10:1; + vuint32_t AWORR_CH9:1; + vuint32_t AWORR_CH8:1; + vuint32_t AWORR_CH7:1; + vuint32_t AWORR_CH6:1; + vuint32_t AWORR_CH5:1; + vuint32_t AWORR_CH4:1; + vuint32_t AWORR_CH3:1; + vuint32_t AWORR_CH2:1; + vuint32_t AWORR_CH1:1; + vuint32_t AWORR_CH0:1; + } B; + } AWORR0; + + union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */ + vuint32_t R; + struct { + vuint32_t :19; + vuint32_t AWORR_CH44:1; + vuint32_t AWORR_CH43:1; + vuint32_t AWORR_CH42:1; + vuint32_t AWORR_CH41:1; + vuint32_t AWORR_CH40:1; + vuint32_t AWORR_CH39:1; + vuint32_t AWORR_CH38:1; + vuint32_t AWORR_CH37:1; + vuint32_t AWORR_CH36:1; + vuint32_t AWORR_CH35:1; + vuint32_t AWORR_CH34:1; + vuint32_t AWORR_CH33:1; + vuint32_t AWORR_CH32:1; + } B; + } AWORR1; + + union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */ + vuint32_t R; + struct { + vuint32_t AWORR_CH95:1; + vuint32_t AWORR_CH94:1; + vuint32_t AWORR_CH93:1; + vuint32_t AWORR_CH92:1; + vuint32_t AWORR_CH91:1; + vuint32_t AWORR_CH90:1; + vuint32_t AWORR_CH89:1; + vuint32_t AWORR_CH88:1; + vuint32_t AWORR_CH87:1; + vuint32_t AWORR_CH86:1; + vuint32_t AWORR_CH85:1; + vuint32_t AWORR_CH84:1; + vuint32_t AWORR_CH83:1; + vuint32_t AWORR_CH82:1; + vuint32_t AWORR_CH81:1; + vuint32_t AWORR_CH80:1; + vuint32_t AWORR_CH79:1; + vuint32_t AWORR_CH78:1; + vuint32_t AWORR_CH77:1; + vuint32_t AWORR_CH76:1; + vuint32_t AWORR_CH75:1; + vuint32_t AWORR_CH74:1; + vuint32_t AWORR_CH73:1; + vuint32_t AWORR_CH72:1; + vuint32_t AWORR_CH71:1; + vuint32_t AWORR_CH70:1; + vuint32_t AWORR_CH69:1; + vuint32_t AWORR_CH68:1; + vuint32_t AWORR_CH67:1; + vuint32_t AWORR_CH66:1; + vuint32_t AWORR_CH65:1; + vuint32_t AWORR_CH64:1; + } B; + } AWORR2; + + vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */ + +}; /* end of ADC1_tag */ + +/****************************************************************************/ +/* MODULE : LINFLEX - non DMA master only */ +/****************************************************************************/ +struct LINFLEX_tag { + + union { /* LINFLEX LIN Control 1 (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t CCD:1; + vuint32_t CFD:1; + vuint32_t LASE:1; + vuint32_t AWUM:1; + vuint32_t MBL:4; + vuint32_t BF:1; + vuint32_t SFTM:1; + vuint32_t LBKM:1; + vuint32_t MME:1; + vuint32_t SBDT:1; + vuint32_t RBLM:1; + vuint32_t SLEEP:1; + vuint32_t INIT:1; + } B; + } LINCR1; + + union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZIE:1; + vuint32_t OCIE:1; + vuint32_t BEIE:1; + vuint32_t CEIE:1; + vuint32_t HEIE:1; + vuint32_t :2; + vuint32_t FEIE:1; + vuint32_t BOIE:1; + vuint32_t LSIE:1; + vuint32_t WUIE:1; + vuint32_t DBFIE:1; + vuint32_t DBEIE:1; + vuint32_t DRIE:1; + vuint32_t DTIE:1; + vuint32_t HRIE:1; + } B; + } LINIER; + + union { /* LINFLEX LIN Status (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t LINS:4; + vuint32_t:2; + vuint32_t RMB:1; + vuint32_t:1; + vuint32_t RBSY:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t DBFF:1; + vuint32_t DBEF:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t HRF:1; + } B; + } LINSR; + + union { /* LINFLEX LIN Error Status (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t BEF:1; + vuint32_t CEF:1; + vuint32_t SFEF:1; + vuint32_t BDEF:1; + vuint32_t IDPEF:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t:6; + vuint32_t NF:1; + } B; + } LINESR; + + union { /* LINFLEX UART Mode Control (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t:1; + vuint32_t TDFL:2; + vuint32_t:1; + vuint32_t RDFL:2; + vuint32_t:4; + vuint32_t RXEN:1; + vuint32_t TXEN:1; + vuint32_t OP:1; + vuint32_t PCE:1; + vuint32_t WL:1; + vuint32_t UART:1; + } B; + } UARTCR; + + union { /* LINFLEX UART Mode Status (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/ + vuint32_t RMB:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t :1; + vuint32_t TO:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t NF:1; + } B; + } UARTSR; + + union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t:5; + vuint32_t LTOM:1; + vuint32_t IOT:1; + vuint32_t TOCE:1; + vuint32_t CNT:8; + } B; + } LINTCSR; + + union { /* LINFLEX LIN Output Compare (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t OC2:8; + vuint32_t OC1:8; + } B; + } LINOCR; + + union { /* LINFLEX LIN Timeout Control (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t :20; + vuint32_t RTO:4; + vuint32_t:1; + vuint32_t HTO:7; + } B; + } LINTOCR; + + union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DIV_F:4; + } B; + } LINFBRR; + + union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t DIV_M:20; + } B; + } LINIBRR; + + union { /* LINFLEX LIN Checksum Field (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t CF:8; + } B; + } LINCFR; + + union { /* LINFLEX LIN Control 2 (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t IOBE:1; + vuint32_t IOPE:1; + vuint32_t WURQ:1; + vuint32_t DDRQ:1; + vuint32_t DTRQ:1; + vuint32_t ABRQ:1; + vuint32_t HTRQ:1; + vuint32_t:8; + } B; + } LINCR2; + + union { /* LINFLEX Buffer Identifier (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } BIDR; + + union { /* LINFLEX Buffer Data LSB (Base+0x0038) */ + vuint32_t R; + struct { + vuint32_t DATA3:8; + vuint32_t DATA2:8; + vuint32_t DATA1:8; + vuint32_t DATA0:8; + } B; + } BDRL; + + union { /* LINFLEX Buffer Data MSB (Base+0x003C */ + vuint32_t R; + struct { + vuint32_t DATA7:8; + vuint32_t DATA6:8; + vuint32_t DATA5:8; + vuint32_t DATA4:8; + } B; + } BDRM; + + union { /* LINFLEX Identifier Filter Enable (+0x0040) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t FACT:8; + } B; + } IFER; + + union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFMI:4; + } B; + } IFMI; + + union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t IFM:5; + } B; + } IFMR; + + union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t:3; /* for LINflexD no reseve here*/ + vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } IFCR[16]; + + +}; /* end of LINFLEX_tag */ + + +/****************************************************************************/ +/* MODULE : LINFLEXD0 Master/Slave DMA Enabled */ +/****************************************************************************/ +struct LINFLEXD0_tag { + + union { /* LINFLEX LIN Control 1 (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t CCD:1; + vuint32_t CFD:1; + vuint32_t LASE:1; + vuint32_t AWUM:1; + vuint32_t MBL:4; + vuint32_t BF:1; + vuint32_t SFTM:1; + vuint32_t LBKM:1; + vuint32_t MME:1; + vuint32_t SBDT:1; + vuint32_t RBLM:1; + vuint32_t SLEEP:1; + vuint32_t INIT:1; + } B; + } LINCR1; + + union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZIE:1; + vuint32_t OCIE:1; + vuint32_t BEIE:1; + vuint32_t CEIE:1; + vuint32_t HEIE:1; + vuint32_t :2; + vuint32_t FEIE:1; + vuint32_t BOIE:1; + vuint32_t LSIE:1; + vuint32_t WUIE:1; + vuint32_t DBFIE:1; + vuint32_t DBEIE:1; + vuint32_t DRIE:1; + vuint32_t DTIE:1; + vuint32_t HRIE:1; + } B; + } LINIER; + + union { /* LINFLEX LIN Status (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t LINS:4; + vuint32_t:2; + vuint32_t RMB:1; + vuint32_t:1; + vuint32_t RBSY:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t DBFF:1; + vuint32_t DBEF:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t HRF:1; + } B; + } LINSR; + + union { /* LINFLEX LIN Error Status (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t BEF:1; + vuint32_t CEF:1; + vuint32_t SFEF:1; + vuint32_t BDEF:1; + vuint32_t IDPEF:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t:6; + vuint32_t NF:1; + } B; + } LINESR; + + union { /* LINFLEX UART Mode Control (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t TDFLTFC:3; + vuint32_t RDFLTFC:3; + vuint32_t RFBM:1; + vuint32_t TFBM:1; + vuint32_t WL1:1; + vuint32_t PC1:1; + vuint32_t RXEN:1; + vuint32_t TXEN:1; + vuint32_t PC0:1; + vuint32_t PCE:1; + vuint32_t WL0:1; + vuint32_t UART:1; + } B; + } UARTCR; + + union { /* LINFLEX UART Mode Status (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/ + vuint32_t RMB:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t :1; + vuint32_t TO:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t NF:1; + } B; + } UARTSR; + + union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t:5; + vuint32_t LTOM:1; + vuint32_t IOT:1; + vuint32_t TOCE:1; + vuint32_t CNT:8; + } B; + } LINTCSR; + + union { /* LINFLEX LIN Output Compare (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t OC2:8; + vuint32_t OC1:8; + } B; + } LINOCR; + + union { /* LINFLEX LIN Timeout Control (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t :20; + vuint32_t RTO:4; + vuint32_t:1; + vuint32_t HTO:7; + } B; + } LINTOCR; + + union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DIV_F:4; + } B; + } LINFBRR; + + union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t DIV_M:20; + } B; + } LINIBRR; + + union { /* LINFLEX LIN Checksum Field (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t CF:8; + } B; + } LINCFR; + + union { /* LINFLEX LIN Control 2 (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t IOBE:1; + vuint32_t IOPE:1; + vuint32_t WURQ:1; + vuint32_t DDRQ:1; + vuint32_t DTRQ:1; + vuint32_t ABRQ:1; + vuint32_t HTRQ:1; + vuint32_t:8; + } B; + } LINCR2; + + union { /* LINFLEX Buffer Identifier (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } BIDR; + + union { /* LINFLEX Buffer Data LSB (Base+0x0038) */ + vuint32_t R; + struct { + vuint32_t DATA3:8; + vuint32_t DATA2:8; + vuint32_t DATA1:8; + vuint32_t DATA0:8; + } B; + } BDRL; + + union { /* LINFLEX Buffer Data MSB (Base+0x003C */ + vuint32_t R; + struct { + vuint32_t DATA7:8; + vuint32_t DATA6:8; + vuint32_t DATA5:8; + vuint32_t DATA4:8; + } B; + } BDRM; + + union { /* LINFLEX Identifier Filter Enable (+0x0040) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t FACT:8; + } B; + } IFER; + + union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t IFMI:5; + } B; + } IFMI; + + union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t IFM:8; + } B; + } IFMR; + + union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } IFCR[16]; + + union { /* LINFLEX Global Counter (+0x008C) */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t TDFBM:1; + vuint32_t RDFBM:1; + vuint32_t TDLIS:1; + vuint32_t RDLIS:1; + vuint32_t STOP:1; + vuint32_t SR:1; + } B; + } GCR; + + union { /* LINFLEX UART preset timeout (+0x0090) */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t PTO:12; + } B; + } UARTPTO; + + union { /* LINFLEX UART current timeout (+0x0094) */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t CTO:12; + } B; + } UARTCTO; + + union { /* LINFLEX DMA Tx Enable (+0x0098) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DTE15:1; + vuint32_t DTE14:1; + vuint32_t DTE13:1; + vuint32_t DTE12:1; + vuint32_t DTE11:1; + vuint32_t DTE10:1; + vuint32_t DTE9:1; + vuint32_t DTE8:1; + vuint32_t DTE7:1; + vuint32_t DTE6:1; + vuint32_t DTE5:1; + vuint32_t DTE4:1; + vuint32_t DTE3:1; + vuint32_t DTE2:1; + vuint32_t DTE1:1; + vuint32_t DTE0:1; + } B; + } DMATXE; + + union { /* LINFLEX DMA RX Enable (+0x009C) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DRE15:1; + vuint32_t DRE14:1; + vuint32_t DRE13:1; + vuint32_t DRE12:1; + vuint32_t DRE11:1; + vuint32_t DRE10:1; + vuint32_t DRE9:1; + vuint32_t DRE8:1; + vuint32_t DRE7:1; + vuint32_t DRE6:1; + vuint32_t DRE5:1; + vuint32_t DRE4:1; + vuint32_t DRE3:1; + vuint32_t DRE2:1; + vuint32_t DRE1:1; + vuint32_t DRE0:1; + } B; + } DMARXE; +}; /* end of LINFLEXD0_tag */ +/****************************************************************************/ +/* MODULE : LINFLEXD1 Master only DMA enable */ +/****************************************************************************/ +struct LINFLEXD1_tag { + + union { /* LINFLEX LIN Control 1 (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t CCD:1; + vuint32_t CFD:1; + vuint32_t LASE:1; + vuint32_t AWUM:1; + vuint32_t MBL:4; + vuint32_t BF:1; + vuint32_t SFTM:1; + vuint32_t LBKM:1; + vuint32_t MME:1; + vuint32_t SBDT:1; + vuint32_t RBLM:1; + vuint32_t SLEEP:1; + vuint32_t INIT:1; + } B; + } LINCR1; + + union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZIE:1; + vuint32_t OCIE:1; + vuint32_t BEIE:1; + vuint32_t CEIE:1; + vuint32_t HEIE:1; + vuint32_t :2; + vuint32_t FEIE:1; + vuint32_t BOIE:1; + vuint32_t LSIE:1; + vuint32_t WUIE:1; + vuint32_t DBFIE:1; + vuint32_t DBEIE:1; + vuint32_t DRIE:1; + vuint32_t DTIE:1; + vuint32_t HRIE:1; + } B; + } LINIER; + + union { /* LINFLEX LIN Status (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t LINS:4; + vuint32_t:2; + vuint32_t RMB:1; + vuint32_t:1; + vuint32_t RBSY:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t DBFF:1; + vuint32_t DBEF:1; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t HRF:1; + } B; + } LINSR; + + union { /* LINFLEX LIN Error Status (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t BEF:1; + vuint32_t CEF:1; + vuint32_t SFEF:1; + vuint32_t BDEF:1; + vuint32_t IDPEF:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t:6; + vuint32_t NF:1; + } B; + } LINESR; + + union { /* LINFLEX UART Mode Control (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t TDFLTFC:3; + vuint32_t RDFLTFC:3; + vuint32_t RFBM:1; + vuint32_t TFBM:1; + vuint32_t WL1:1; + vuint32_t PC1:1; + vuint32_t RXEN:1; + vuint32_t TXEN:1; + vuint32_t PC0:1; + vuint32_t PCE:1; + vuint32_t WL0:1; + vuint32_t UART:1; + } B; + } UARTCR; + + union { /* LINFLEX UART Mode Status (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SZF:1; + vuint32_t OCF:1; + vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/ + vuint32_t RMB:1; + vuint32_t FEF:1; + vuint32_t BOF:1; + vuint32_t RPS:1; + vuint32_t WUF:1; + vuint32_t:2; + vuint32_t DRF:1; + vuint32_t DTF:1; + vuint32_t NF:1; + } B; + } UARTSR; + + union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t:5; + vuint32_t LTOM:1; + vuint32_t IOT:1; + vuint32_t TOCE:1; + vuint32_t CNT:8; + } B; + } LINTCSR; + + union { /* LINFLEX LIN Output Compare (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t OC2:8; + vuint32_t OC1:8; + } B; + } LINOCR; + + union { /* LINFLEX LIN Timeout Control (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t :20; + vuint32_t RTO:4; + vuint32_t:1; + vuint32_t HTO:7; + } B; + } LINTOCR; + + union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DIV_F:4; + } B; + } LINFBRR; + + union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t DIV_M:20; + } B; + } LINIBRR; + + union { /* LINFLEX LIN Checksum Field (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t CF:8; + } B; + } LINCFR; + + union { /* LINFLEX LIN Control 2 (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t IOBE:1; + vuint32_t IOPE:1; + vuint32_t WURQ:1; + vuint32_t DDRQ:1; + vuint32_t DTRQ:1; + vuint32_t ABRQ:1; + vuint32_t HTRQ:1; + vuint32_t:8; + } B; + } LINCR2; + + union { /* LINFLEX Buffer Identifier (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; + vuint32_t DIR:1; + vuint32_t CCS:1; + vuint32_t:2; + vuint32_t ID:6; + } B; + } BIDR; + + union { /* LINFLEX Buffer Data LSB (Base+0x0038) */ + vuint32_t R; + struct { + vuint32_t DATA3:8; + vuint32_t DATA2:8; + vuint32_t DATA1:8; + vuint32_t DATA0:8; + } B; + } BDRL; + + union { /* LINFLEX Buffer Data MSB (Base+0x003C */ + vuint32_t R; + struct { + vuint32_t DATA7:8; + vuint32_t DATA6:8; + vuint32_t DATA5:8; + vuint32_t DATA4:8; + } B; + } BDRM; + + union { /* LINFLEX Identifier Filter Enable (+0x0040) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t FACT:8; + } B; + } IFER; + + union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t IFMI:5; + } B; + } IFMI; + + union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t IFM:8; + } B; + } IFMR; + +/* No IFCR registers on LinFlexD_1 */ + + union { /* LINFLEX Global Counter (+0x004C) */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t TDFBM:1; + vuint32_t RDFBM:1; + vuint32_t TDLIS:1; + vuint32_t RDLIS:1; + vuint32_t STOP:1; + vuint32_t SR:1; + } B; + } GCR; + + union { /* LINFLEX UART preset timeout (+0x0050) */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t PTO:12; + } B; + } UARTPTO; + + union { /* LINFLEX UART current timeout (+0x0054) */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t CTO:12; + } B; + } UARTCTO; + + union { /* LINFLEX DMA Tx Enable (+0x0058) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DTE15:1; + vuint32_t DTE14:1; + vuint32_t DTE13:1; + vuint32_t DTE12:1; + vuint32_t DTE11:1; + vuint32_t DTE10:1; + vuint32_t DTE9:1; + vuint32_t DTE8:1; + vuint32_t DTE7:1; + vuint32_t DTE6:1; + vuint32_t DTE5:1; + vuint32_t DTE4:1; + vuint32_t DTE3:1; + vuint32_t DTE2:1; + vuint32_t DTE1:1; + vuint32_t DTE0:1; + } B; + } DMATXE; + + union { /* LINFLEX DMA RX Enable (+0x005C) */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DRE15:1; + vuint32_t DRE14:1; + vuint32_t DRE13:1; + vuint32_t DRE12:1; + vuint32_t DRE11:1; + vuint32_t DRE10:1; + vuint32_t DRE9:1; + vuint32_t DRE8:1; + vuint32_t DRE7:1; + vuint32_t DRE6:1; + vuint32_t DRE5:1; + vuint32_t DRE4:1; + vuint32_t DRE3:1; + vuint32_t DRE2:1; + vuint32_t DRE1:1; + vuint32_t DRE0:1; + } B; + } DMARXE; +}; /* end of LINFLEXD1_tag */ + /****************************************************************************/ +/* MODULE : CTU Lite(base address - 0xFFE6_4000) */ +/****************************************************************************/ +struct CTU_tag{ + + vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */ + + union { /* Event Config 0..63 (Base+0x0030-0x012C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t TM:1; + vuint32_t CLR_FLAG:1; + vuint32_t :5; + vuint32_t ADC_SEL:1; + vuint32_t :1; + vuint32_t CHANNEL_VALUE:7; + } B; + } EVTCFGR[64]; + + +}; /* end of CTU_tag */ + + +/****************************************************************************/ +/* MODULE : MPU (base address - 0xFFF1_0000) */ +/****************************************************************************/ + struct MPU_tag { + + union { /* Control/Error Status (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t SPERR:3; + vuint32_t:9; + vuint32_t HRL:4; + vuint32_t NSP:4; + vuint32_t NGRD:4; + vuint32_t :7; + vuint32_t VLD:1; + } B; + } CESR; + + vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */ + + + union { /* Error Address Slave Port0 (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR0; + + union { /* Error Detail Slave Port0 (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t EACD:8; + vuint32_t:8; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR0; + + + union { /* Error Address Slave Port1 (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR1; + + union { /* Error Detail Slave Port1 (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t EACD:8; + vuint32_t:8; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR1; + + + union { /* Error Address Slave Port2 (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR2; + + union { /* Error Detail Slave Port2 (Base+0x0024) */ + vuint32_t R; + struct { + vuint32_t EACD:8; + vuint32_t:8; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR2; + + vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */ + + struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */ + + union { /* - Word 0 */ + vuint32_t R; + struct { + vuint32_t SRTADDR:27; + vuint32_t :5; + } B; + } WORD0; + + union { /* - Word 1 */ + vuint32_t R; + struct { + vuint32_t ENDADDR:27; + vuint32_t :5; + } B; + } WORD1; + + union { /* - Word 2 */ + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:2; + vuint32_t :7; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } WORD2; + + union { /* - Word 3 */ + vuint32_t R; + struct { + vuint32_t PID:8; + vuint32_t PIDMASK:8; + vuint32_t :15; + vuint32_t VLD:1; + } B; + } WORD3; + + }RGD[8]; /* End of Region Descriptor Structure) */ + + vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */ + + union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */ + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:2; + vuint32_t :7; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } RGDAAC[8]; + + vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */ + +}; /* end of MPU_tag */ + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ +struct SWT_tag{ + + union { /* SWT Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t :14; + vuint32_t KEY:1; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } CR; + + union { /* SWT Interrupt (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t TIF:1; + } B; + } IR; + + union { /* SWT Time-Out (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; + + union { /* SWT Window (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t WST:32; + } B; + } WN; + + union { /* SWT Service (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t WSC:16; + } B; + } SR; + + union { /* SWT Counter Output (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; + +}; /* end of SWT_tag */ + +/****************************************************************************/ +/* MODULE : STM */ +/****************************************************************************/ + struct STM_CHANNEL_tag{ + + union { /* STM Channel Control 0..3 */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t CEN:1; + } B; + } CCR; + + union { /* STM Channel Interrupt 0..3 */ + vuint32_t R; + struct { + vuint32_t :31; + vuint32_t CIF:1; + } B; + } CIR; + + union { /* STM Channel Compare 0..3 */ + vuint32_t R; + struct { + vuint32_t CMP:32; + } B; + } CMP; + + vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */ + + }; /* end of STM_CHANNEL_tag */ + + +struct STM_tag{ + + union { /* STM Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t CPS:8; + vuint32_t :6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; + + union { /* STM Count (Base+0x0004) */ + vuint32_t R; + } CNT; + + vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */ + + struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */ + +}; /* end of STM_tag */ + +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ +struct ECSM_tag{ + + union { /* ECSM Processor Core Type (Base+0x0000) */ + vuint16_t R; + } PCT; + + union { /* ECSM Revision (Base+0x0002) */ + vuint16_t R; + } REV; + + vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */ + + union { /* ECSM IPS Module Configuration (Base+0x0008) */ + vuint32_t R; + } IMC; + + vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */ + + union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */ + vuint8_t R; + struct { + vuint8_t ENBWCR:1; + vuint8_t :3; + vuint8_t PRILVL:4; + } B; + } MWCR; + + vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */ + + union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */ + vuint8_t R; + struct { + vuint8_t FB0AI:1; + vuint8_t FB0SI:1; + vuint8_t FB1AI:1; + vuint8_t FB1SI:1; + vuint8_t :4; + } B; + } MIR; + + vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */ + + union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/ + vuint32_t R; + } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */ + + vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */ + + union { /* ECSM ECC Configuration (Base+0x0043) */ + vuint8_t R; + struct { + vuint8_t :2; + vuint8_t ER1BR:1; + vuint8_t EF1BR:1; + vuint8_t :2; + vuint8_t ERNCR:1; + vuint8_t EFNCR:1; + } B; + } ECR; + + vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */ + + union { /* ECSM ECC Status (Base+0x0047) */ + vuint8_t R; + struct { + vuint8_t :2; + vuint8_t R1BC:1; + vuint8_t F1BC:1; + vuint8_t :2; + vuint8_t RNCE:1; + vuint8_t FNCE:1; + } B; + } ESR; + + vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */ + + union { /* ECSM ECC Error Generation (Base+0x004A) */ + vuint16_t R; + struct { + vuint16_t :2; + vuint16_t FRC1BI:1; + vuint16_t FR11BI:1; + vuint16_t :2; + vuint16_t FRCNCI:1; + vuint16_t FR1NCI:1; + vuint16_t :1; + vuint16_t ERRBIT:7; + } B; + } EEGR; + + vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */ + + union { /* ECSM Flash ECC Address(Base+0x0050) */ + vuint32_t R; + } FEAR; + + vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */ + + union { /* ECSM Flash ECC Master Number (Base+0x0056) */ + vuint8_t R; + struct { + vuint8_t :4; + vuint8_t FEMR:4; + } B; + } FEMR; + + union { /* ECSM Flash ECC Attributes (Base+0x0057) */ + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } FEAT; + + vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */ + + union { /* ECSM Flash ECC Data (Base+0x005C) */ + vuint32_t R; + } FEDR; + + union { /* ECSM RAM ECC Address (Base+0x0060) */ + vuint32_t R; + } REAR; + + vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */ + + union { /* ECSM RAM ECC Address (Base+0x0065) */ + vuint8_t R; + } RESR; + + union { /* ECSM RAM ECC Master Number (Base+0x0066) */ + vuint8_t R; + struct { + vuint8_t :4; + vuint8_t REMR:4; + } B; + } REMR; + + union { /* ECSM RAM ECC Attributes (Base+0x0067) */ + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } REAT; + + vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */ + + union { /* ECSM RAM ECC Data (Base+0x006C) */ + vuint32_t R; + } REDR; + +}; /* end of ECSM_tag */ + +/****************************************************************************/ +/* MODULE : eDMA (base address - 0xFFF4_4000) */ +/****************************************************************************/ + + /* There are 4 different TCD structures which should be used based on */ + /* how the DMA is configured as below. CAUTION - Do not mix TCD's */ + /* */ + /* Channel Linking Minor Loop Mapping Addressing TCD */ + /* OFF OFF XBAR.TCD[x] */ + /* OFF ON XBAR.ML_TCD[x] */ + /* ON OFF XBAR.CL_TCD[X] */ + /* ON ON XBAR.MLCL_TCD[X] */ + /* */ + + /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */ + /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF */ + struct EDMA_TCD_STD_tag { + + vuint32_t SADDR; /* Source address */ + + vuint16_t SMOD:5; /* Source address modulo */ + vuint16_t SSIZE:3; /* Source data transfer size */ + vuint16_t DMOD:5; /* Destination address modulo */ + vuint16_t DSIZE:3; /* Destination data transfer size */ + vint16_t SOFF; /* Source address signed offset */ + + vuint32_t NBYTES; /* Inner "minor" byte transfer count */ + + vint32_t SLAST; /* Last source address adjustment */ + + vuint32_t DADDR; /* Destination address */ + + vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t CITER:15; /* Current Major iteration count */ + vint16_t DOFF; /* Destination address signed offset */ + + vint32_t DLAST_SGA; /* Last desitination address adjustment */ + + vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t BITER:15; /* Starting major iteration count */ + vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */ + vuint16_t MAJORLINKCH:6; /* Link channel number */ + vuint16_t DONE:1; /* Channel done */ + vuint16_t ACTIVE:1; /* Channel active */ + vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */ + vuint16_t E_SG:1; /* Enable scatter/gather processing */ + vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */ + vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */ + vuint16_t INT_MAJ:1; /* interrupt on major loop complete */ + vuint16_t START:1; /* Chanel start */ + + }; /* End of Standard TCD tag */ + + + /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled */ + /* (EMLM = 1) */ + struct EDMA_TCD_MLMIRROR_tag { + + vuint32_t SADDR; /* Source address */ + + vuint16_t SMOD:5; /* Source address modulo */ + vuint16_t SSIZE:3; /* Source data transfer size */ + vuint16_t DMOD:5; /* Destination address modulo */ + vuint16_t DSIZE:3; /* Destination data transfer size */ + vint16_t SOFF; /* Source address signed offset */ + + vuint32_t SMLOE:1; /* Source minor loop offset enabled */ + vuint32_t DMLOE:1; /* Destination minor loop offset enable */ + vuint32_t MLOFF:20; /* Minor loop offset */ + vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */ + + vint32_t SLAST; /* Last source address adjustment */ + + vuint32_t DADDR; /* Destination address */ + + vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t CITER:15; /* Current Major iteration count */ + vint16_t DOFF; /* Destination address signed offset */ + + vint32_t DLAST_SGA; /* Last desitination address adjustment */ + + vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t BITER:15; /* Starting major iteration count */ + vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */ + vuint16_t MAJORLINKCH:6; /* Link channel number */ + vuint16_t DONE:1; /* Channel done */ + vuint16_t ACTIVE:1; /* Channel active */ + vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */ + vuint16_t E_SG:1; /* Enable scatter/gather processing */ + vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */ + vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */ + vuint16_t INT_MAJ:1; /* interrupt on major loop complete */ + vuint16_t START:1; /* Chanel start */ + + }; /* End of EDMA_TCD_MLMIRROR_tag */ + + /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/ + /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF */ + /* (CITERE_LINK = BITERE_LINK = 1) */ + struct EDMA_TCD_CHLINK_tag { + + vuint32_t SADDR; /* Source address */ + + vuint16_t SMOD:5; /* Source address modulo */ + vuint16_t SSIZE:3; /* Source data transfer size */ + vuint16_t DMOD:5; /* Destination address modulo */ + vuint16_t DSIZE:3; /* Destination data transfer size */ + vint16_t SOFF; /* Source address signed offset */ + + vuint32_t NBYTES; /* Inner "minor" byte transfer count */ + + vint32_t SLAST; /* Last source address adjustment */ + + vuint32_t DADDR; /* Destination address */ + + vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t CITERLINKCH:6; /* Link channel number */ + vuint16_t CITER:9; /* Current Major iteration count */ + vint16_t DOFF; /* Destination address signed offset */ + + vint32_t DLAST_SGA; /* Last desitination address adjustment */ + + vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t BITERLINKCH:6; /* Link channel number */ + vuint16_t BITER:9; /* Starting Major iteration count */ + vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */ + vuint16_t MAJORLINKCH:6; /* Link channel number */ + vuint16_t DONE:1; /* Channel done */ + vuint16_t ACTIVE:1; /* Channel active */ + vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */ + vuint16_t E_SG:1; /* Enable scatter/gather processing */ + vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */ + vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */ + vuint16_t INT_MAJ:1; /* interrupt on major loop complete */ + vuint16_t START:1; /* Chanel start */ + + }; /* end of EDMA_TCD_CHLINK_tag */ + + /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled */ + /* (CITERE_LINK = BITERE_LINK = 1, EMLM = 1) */ + struct EDMA_TCD_MLMIRROR_CHLINK_tag { + + vuint32_t SADDR; /* Source address */ + + vuint16_t SMOD:5; /* Source address modulo */ + vuint16_t SSIZE:3; /* Source data transfer size */ + vuint16_t DMOD:5; /* Destination address modulo */ + vuint16_t DSIZE:3; /* Destination data transfer size */ + vint16_t SOFF; /* Source address signed offset */ + + vuint32_t SMLOE:1; /* Source minor loop offset enabled */ + vuint32_t DMLOE:1; /* Destination minor loop offset enable */ + vuint32_t MLOFF:20; /* Minor loop offset */ + vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */ + + vint32_t SLAST; /* Last source address adjustment */ + + vuint32_t DADDR; /* Destination address */ + + vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t CITERLINKCH:6; /* Link channel number */ + vuint16_t CITER:9; /* Current Major iteration count */ + vint16_t DOFF; /* Destination address signed offset */ + + vint32_t DLAST_SGA; /* Last desitination address adjustment */ + + vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */ + vuint16_t BITERLINKCH:6; /* Link channel number */ + vuint16_t BITER:9; /* Starting Major iteration count */ + vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */ + vuint16_t MAJORLINKCH:6; /* Link channel number */ + vuint16_t DONE:1; /* Channel done */ + vuint16_t ACTIVE:1; /* Channel active */ + vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */ + vuint16_t E_SG:1; /* Enable scatter/gather processing */ + vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */ + vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */ + vuint16_t INT_MAJ:1; /* interrupt on major loop complete */ + vuint16_t START:1; /* Chanel start */ + + }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag */ + +struct EDMA_tag { + + union { /* Control (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t :14; + vuint32_t CX:1; + vuint32_t ECX:1; + vuint32_t :6; + vuint32_t GRP0PRI:2; + vuint32_t EMLM:1; + vuint32_t CLM:1; + vuint32_t HALT:1; + vuint32_t HOE:1; + vuint32_t ERGA:1; + vuint32_t ERCA:1; + vuint32_t EDBG:1; + vuint32_t EBW:1; + } B; + } CR; + + union { /* Error Status (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t VLD:1; + vuint32_t :16; + vuint32_t CPE:1; + vuint32_t ERRCHN:6; + vuint32_t SAE:1; + vuint32_t SOE:1; + vuint32_t DAE:1; + vuint32_t DOE:1; + vuint32_t NCE:1; + vuint32_t SGE:1; + vuint32_t SBE:1; + vuint32_t DBE:1; + } B; + } ESR; + + vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/ + + union { /* Enable Request Low Ch15..0 (Base+0x000C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t ERQ15:1; + vuint32_t ERQ14:1; + vuint32_t ERQ13:1; + vuint32_t ERQ12:1; + vuint32_t ERQ11:1; + vuint32_t ERQ10:1; + vuint32_t ERQ09:1; + vuint32_t ERQ08:1; + vuint32_t ERQ07:1; + vuint32_t ERQ06:1; + vuint32_t ERQ05:1; + vuint32_t ERQ04:1; + vuint32_t ERQ03:1; + vuint32_t ERQ02:1; + vuint32_t ERQ01:1; + vuint32_t ERQ00:1; + } B; + } ERQRL; + + vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/ + + union { /* Enable Error Interrupt Low (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t EEI15:1; + vuint32_t EEI14:1; + vuint32_t EEI13:1; + vuint32_t EEI12:1; + vuint32_t EEI11:1; + vuint32_t EEI10:1; + vuint32_t EEI09:1; + vuint32_t EEI08:1; + vuint32_t EEI07:1; + vuint32_t EEI06:1; + vuint32_t EEI05:1; + vuint32_t EEI04:1; + vuint32_t EEI03:1; + vuint32_t EEI02:1; + vuint32_t EEI01:1; + vuint32_t EEI00:1; + } B; + } EEIRL; + + union { /* DMA Set Enable Request (Base+0x0018) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t SERQ:7; + } B; + } SERQR; + + union { /* DMA Clear Enable Request (Base+0x0019) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t CERQ:7; + } B; + } CERQR; + + union { /* DMA Set Enable Error Interrupt (Base+0x001A) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t SEEI:7; + } B; + } SEEIR; + + union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CEEI:7; + } B; + } CEEIR; + + union { /* DMA Clear Interrupt Request (Base+0x001C) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t CINT:7; + } B; + } CIRQR; + + union { /* DMA Clear error (Base+0x001D) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t CERR:7; + } B; + } CER; + + union { /* DMA Set Start Bit (Base+0x001E) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t SSB:7; + } B; + } SSBR; + + union { /* DMA Clear Done Status Bit (Base+0x001F) */ + vuint8_t R; + struct { + vuint8_t :1; + vuint8_t CDSB:7; + } B; + } CDSBR; + + vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/ + + union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t INT15:1; + vuint32_t INT14:1; + vuint32_t INT13:1; + vuint32_t INT12:1; + vuint32_t INT11:1; + vuint32_t INT10:1; + vuint32_t INT09:1; + vuint32_t INT08:1; + vuint32_t INT07:1; + vuint32_t INT06:1; + vuint32_t INT05:1; + vuint32_t INT04:1; + vuint32_t INT03:1; + vuint32_t INT02:1; + vuint32_t INT01:1; + vuint32_t INT00:1; + } B; + } IRQRL; + + vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/ + + union { /* DMA Error Low Ch15..0 (Base+0x002C)*/ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t ERR15:1; + vuint32_t ERR14:1; + vuint32_t ERR13:1; + vuint32_t ERR12:1; + vuint32_t ERR11:1; + vuint32_t ERR10:1; + vuint32_t ERR09:1; + vuint32_t ERR08:1; + vuint32_t ERR07:1; + vuint32_t ERR06:1; + vuint32_t ERR05:1; + vuint32_t ERR04:1; + vuint32_t ERR03:1; + vuint32_t ERR02:1; + vuint32_t ERR01:1; + vuint32_t ERR00:1; + } B; + } ERL; + + vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/ + + union { /* DMA Hardware Request Stat Low (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t HRS15:1; + vuint32_t HRS14:1; + vuint32_t HRS13:1; + vuint32_t HRS12:1; + vuint32_t HRS11:1; + vuint32_t HRS10:1; + vuint32_t HRS09:1; + vuint32_t HRS08:1; + vuint32_t HRS07:1; + vuint32_t HRS06:1; + vuint32_t HRS05:1; + vuint32_t HRS04:1; + vuint32_t HRS03:1; + vuint32_t HRS02:1; + vuint32_t HRS01:1; + vuint32_t HRS00:1; + } B; + } HRSL; + + vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/ + + union { /* Channel n Priority (Base+0x0100-0x010F)*/ + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[16]; + + vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */ + + +union { /* 4 different TCD definitions depending on operating mode */ + + /* Default TCD (Channel Linking and Minor Loop Maping disabled) */ + struct EDMA_TCD_STD_tag TCD[16]; + + /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled) */ + struct EDMA_TCD_MLMIRROR_tag ML_TCD[16]; + + /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled) */ + struct EDMA_TCD_CHLINK_tag CL_TCD[16]; + + /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled) */ + struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[16]; + }; + + + vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */ + +}; /* end of EDMA_tag */ +/*************************************************************************/ +/* MODULE : INTC (base address - 0xFFF4_8000) */ +/*************************************************************************/ +struct INTC_tag { + + union { /* INTC Module Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t VTES:1; + vuint32_t:4; + vuint32_t HVEN:1; + } B; + } MCR; + + vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */ + + union { /* INTC Current Priority (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t PRI:4; + } B; + } CPR; + + vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */ + + union { /* INTC Interrupt Acknowledge (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t VTBA_PRC0:21; + vuint32_t INTVEC_PRC0:9; + vuint32_t:2; + } B; + } IACKR; + + vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */ + + union { /* INTC End Of Interrupt (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t:32; + } B; + } EOIR; + + vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */ + + union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */ + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t SET:1; + vuint8_t CLR:1; + } B; + } SSCIR[8]; + + vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */ + + union { /* INTC Priority Select (Base+0x0040-0x0128) */ + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PRI:4; + } B; + } PSR[234]; + +}; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : DSPI */ +/* Base Addresses: */ +/* DSPI_0 - 0xFFF9_0000 */ +/* DSPI_1 - 0xFFF9_4000 */ +/* DSPI_2 - 0xFFF9_8000 */ +/* DSPI_3 - 0xFFF9_C000 */ +/* DSPI_4 - 0xFFFA_0000 */ +/* DSPI_5 - 0xFFFA_4000 */ +/****************************************************************************/ +struct DSPI_tag{ + + union { /* DSPI Module Configuraiton (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t :2; + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t :1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t :7; + vuint32_t HALT:1; + } B; + } MCR; + + vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */ + + union { /* DSPI Transfer Count (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t TCNT:16; + vuint32_t :16; + } B; + } TCR; + + union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */ + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[6]; + + vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */ + + union { /* DSPI Status (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t :1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t :1; + vuint32_t TFFF:1; + vuint32_t :5; + vuint32_t RFOF:1; + vuint32_t :1; + vuint32_t RFDF:1; + vuint32_t :1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; + + union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */ + vuint32_t R; + struct { + vuint32_t TCFRE:1; + vuint32_t :2; + vuint32_t EOQFRE:1; + vuint32_t TFUFRE:1; + vuint32_t :1; + vuint32_t TFFFRE:1; + vuint32_t TFFFDIRS:1; + vuint32_t :4; + vuint32_t RFOFRE:1; + vuint32_t :1; + vuint32_t RFDFRE:1; + vuint32_t RFDFDIRS:1; + vuint32_t :16; + } B; + } RSER; + + union { /* DSPI Push TX FIFO (Base+0x0034) */ + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t :4; + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; + + union { /* DSPI Pop RX FIFO (Base+0x0038) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t RXDATA:16; + } B; + } POPR; + + union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/ + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; + + vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */ + + union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; + }; /* end of DSPI_tag */ + /****************************************************************************/ +/* MODULE : FlexCAN */ +/* Base Addresses: */ +/* FlexCAN_0 - 0xFFFC_0000 */ +/****************************************************************************/ +struct FLEXCAN_BUF_t{ + + union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */ + vuint32_t R; + struct { + vuint32_t :4; + vuint32_t CODE:4; + vuint32_t :1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { /* FLEXCAN MBx Identifier (Offset+0x0084) */ + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */ + vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + vuint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + +}; /* end of FLEXCAN_BUF_t */ + + +struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */ + + union { /* RxFIFO Control & Status (Offset+0x0080) */ + vuint32_t R; + struct { + vuint32_t :9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { /* RxFIFO Identifier (Offset+0x0084) */ + vuint32_t R; + struct { + vuint32_t :3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { /* RxFIFO Data 0..7 (Offset+0x0088) */ + vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + vuint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/ + + union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */ + vuint32_t R; + } IDTABLE[8]; + +}; /* end of FLEXCAN_RXFIFO_t */ + + +struct FLEXCAN_tag{ + + union { /* FLEXCAN Module Configuration (Base+0x0000) */ + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAKMSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t :1; + vuint32_t WRNEN:1; + vuint32_t LPMACK:1; + vuint32_t WAKSRC:1; + vuint32_t :1; + vuint32_t SRXDIS:1; + vuint32_t BCC:1; + vuint32_t:2; + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + vuint32_t MAXMB:6; + } B; + } MCR; + + union { /* FLEXCAN Control (Base+0x0004) */ + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t :2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; + } CR; + + union { /* FLEXCAN Free Running Timer (Base+0x0008) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t TIMER:16; + } B; + } TIMER; + + vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */ + + union { /* FLEXCAN RX Global Mask (Base+0x0010) */ + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXGMASK; + + /* --- Following 2 registers are included for legacy purposes only --- */ + + union { /* FLEXCAN RX 14 Mask (Base+0x0014) */ + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX14MASK; + + union { /* FLEXCAN RX 15 Mask (Base+0x0018) */ + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX15MASK; + + /* --- */ + + union { /* FLEXCAN Error Counter (Base+0x001C) */ + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; + + union { /* FLEXCAN Error & Status (Base+0x0020) */ + vuint32_t R; + struct { + vuint32_t :14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t :1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t :1; + } B; + } ESR; + + union { /* FLEXCAN Interruput Masks H (Base+0x0024) */ + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; + } IMRH; + + union { /* FLEXCAN Interruput Masks L (Base+0x0028) */ + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; + } IMRL; + + union { /* FLEXCAN Interruput Flag H (Base+0x002C) */ + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; + } IFRH; + + union { /* FLEXCAN Interruput Flag l (Base+0x0030) */ + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/ + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/ + + union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */ + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXIMR[64]; + +}; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : DMAMUX (base address - 0xFFFD_C000) */ +/****************************************************************************/ + struct DMAMUX_tag { + union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */ + vuint8_t R; + struct { + vuint8_t ENBL:1; + vuint8_t TRIG:1; + vuint8_t SOURCE:6; + } B; + } CHCONFIG[16]; + + }; /* end of DMAMUX_tag */ + +/****************************************************************** +| defines and macros (scope: module-local) +|-----------------------------------------------------------------*/ +/* Define instances of modules */ + +#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL) +#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL) +#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL) +#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL) +#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL) +#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL) +#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL) +#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL) +#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL) +#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL) +#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL) +#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL) +#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL) +#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL) +#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL) +#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL) +#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) +#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) + + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif +/* End of file */ diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c new file mode 100644 index 000000000..799908d46 --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -0,0 +1,307 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Pxx/hal_lld.c + * @brief SPC560Pxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief PIT channel 3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector59) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + /* Resets the PIT channel 3 IRQ flag.*/ + PIT.CH[0].TFLG.R = 1; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t reg; + + /* The system is switched to the RUN0 mode, the default for normal + operations.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* PIT channel 0 initialization for Kernel ticks, the PIT is configured + to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other + modes.*/ + INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; + halSPCSetPeripheralClockMode(92, + SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); + reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; + PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ + PIT.CH[0].LDVAL.R = reg; + PIT.CH[0].CVAL.R = reg; + PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ + PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ + + /* EDMA initialization.*/ + edmaInit(); +} + +/** + * @brief SPC560Pxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + + /* Waiting for IRC stabilization before attempting anything else.*/ + while (!ME.GS.B.S_RC) + ; + +#if !SPC5_NO_INIT + +#if SPC5_DISABLE_WATCHDOG + /* SWT disabled.*/ + SWT.SR.R = 0xC520; + SWT.SR.R = 0xD928; + SWT.CR.R = 0xFF00000A; +#endif + + /* SSCM initialization. Setting up the most restrictive handling of + invalid accesses to peripherals.*/ + SSCM.ERROR.R = 3; /* PAE and RAE bits. */ + + /* RGM errors clearing.*/ + RGM.FES.R = 0xFFFF; + RGM.DES.R = 0xFFFF; + + /* The system must be in DRUN mode on entry, if this is not the case then + it is considered a serious anomaly.*/ + if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) { + SPC5_CLOCK_FAILURE_HOOK(); + } + +#if defined(SPC5_OSC_BYPASS) + /* If the board is equipped with an oscillator instead of a xtal then the + bypass must be activated.*/ + CGM.OSC_CTL.B.OSCBYP = TRUE; +#endif /* SPC5_OSC_BYPASS */ + + /* Setting the various dividers and source selectors.*/ +#if SPC5_HAS_AC0 + CGM.AC0DC.R = SPC5_CGM_AC0_DC0; + CGM.AC0SC.R = SPC5_AUX0CLK_SRC; +#endif +#if SPC5_HAS_AC1 + CGM.AC1DC.R = SPC5_CGM_AC1_DC0; + CGM.AC1SC.R = SPC5_AUX1CLK_SRC; +#endif +#if SPC5_HAS_AC2 + CGM.AC2DC.R = SPC5_CGM_AC2_DC0; + CGM.AC2SC.R = SPC5_AUX2CLK_SRC; +#endif +#if SPC5_HAS_AC3 + CGM.AC3DC.R = SPC5_CGM_AC3_DC0; + CGM.AC3SC.R = SPC5_AUX3CLK_SRC; +#endif + + /* Enables the XOSC in order to check its functionality before proceeding + with the initialization.*/ + ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | SPC5_ME_MC_MVRON; + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Initialization of the FMPLLs settings.*/ + CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF | + ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL0_NDIV_VALUE << 16); + CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */ +#if SPC5_HAS_FMPLL1 + CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF | + ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL1_NDIV_VALUE << 16); + CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */ +#endif + + /* Run modes initialization.*/ + ME.IS.R = 8; /* Resetting I_ICONF status.*/ + ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ + ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */ + ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ + ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ + ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ + ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ + ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ + ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ + ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ + ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ + if (ME.IS.B.I_CONF) { + /* Configuration rejected.*/ + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Peripherals run and low power modes initialization.*/ + ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; + ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; + ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; + ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; + ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; + ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; + ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; + ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; + ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; + ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; + ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; + ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; + ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; + ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; + ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; + ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; + + /* CFLASH settings calculated for a maximum clock of 64MHz.*/ + CFLASH.PFCR0.B.BK0_APC = 2; + CFLASH.PFCR0.B.BK0_RWSC = 2; + CFLASH.PFCR1.B.BK1_APC = 2; + CFLASH.PFCR1.B.BK1_RWSC = 2; + + /* Switches again to DRUN mode (current mode) in order to update the + settings.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } +#endif /* !SPC5_NO_INIT */ +} + +/** + * @brief Switches the system to the specified run mode. + * + * @param[in] mode one of the possible run modes + * + * @return The operation status. + * @retval CH_SUCCESS if the switch operation has been completed. + * @retval CH_FAILED if the switch operation failed. + */ +bool_t halSPCSetRunMode(spc5_runmode_t mode) { + + /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/ + ME.IS.R = 5; + + /* Starts a transition process.*/ + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; + + /* Waits for the mode switch or an error condition.*/ + while (TRUE) { + uint32_t r = ME.IS.R; + if (r & 1) + return CH_SUCCESS; + if (r & 4) + return CH_FAILED; + } +} + +/** + * @brief Changes the clock mode of a peripheral. + * + * @param[in] n index of the @p PCTL register + * @param[in] pctl new value for the @p PCTL register + * + * @notapi + */ +void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) { + uint32_t mode; + + ME.PCTL[n].R = pctl; + mode = ME.MCTL.B.TARGET_MODE; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; +} + +#if !SPC5_NO_INIT || defined(__DOXYGEN__) +/** + * @brief Returns the system clock under the current run mode. + * + * @return The system clock in Hertz. + */ +uint32_t halSPCGetSystemClock(void) { + uint32_t sysclk; + + sysclk = ME.GS.B.S_SYSCLK; + switch (sysclk) { + case SPC5_ME_GS_SYSCLK_IRC: + return SPC5_IRC_CLK; + case SPC5_ME_GS_SYSCLK_XOSC: + return SPC5_XOSC_CLK; + case SPC5_ME_GS_SYSCLK_FMPLL0: + return SPC5_FMPLL0_CLK; +#if SPC5_HAS_FMPLL1 + case SPC5_ME_GS_SYSCLK_FMPLL1: + return SPC5_FMPLL1_CLK; +#endif + default: + return 0; + } +} +#endif /* !SPC5_NO_INIT */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h new file mode 100644 index 000000000..4486b76cb --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -0,0 +1,985 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Pxx/hal_lld.h + * @brief SPC560Pxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * - SPC5_OSC_BYPASS (optionally). + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc560p.h" +#include "spc560p_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @name Platform identification + * @{ + */ +#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__) +#define PLATFORM_NAME "SPC56APxx Chassis and Safety" +#else +#define PLATFORM_NAME "SPC560Pxx Chassis and Safety" +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MAX 40000000 + +/** + * @brief Minimum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MAX 16000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MAX 512000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MIN 256000000 + +/** + * @brief Maximum FMPLL0 output clock frequency. + */ +#define SPC5_FMPLL0_CLK_MAX 64000000 + +/** + * @brief Maximum FMPLL1 output clock frequency. + * @note FMPLL1 is not present on all devices. + */ +#define SPC5_FMPLL1_CLK_MAX 120000000 + +/** + * @brief Maximum FMPLL1 1D1 output clock frequency. + * @note FMPLL1 is not present on all devices. + */ +#define SPC5_FMPLL1_1D1_CLK_MAX 80000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/ +/** @} */ + +/** + * @name FMPLL_CR register bits definitions + * @{ + */ +#define SPC5_FMPLL_ODF_DIV2 (0U << 24) +#define SPC5_FMPLL_ODF_DIV4 (1U << 24) +#define SPC5_FMPLL_ODF_DIV8 (2U << 24) +#define SPC5_FMPLL_ODF_DIV16 (3U << 24) +/** @} */ + +/** + * @name Clock selectors used in the various GCM SC registers + * @{ + */ +#define SPC5_CGM_SS_MASK (15U << 24) +#define SPC5_CGM_SS_IRC (0U << 24) +#define SPC5_CGM_SS_XOSC (2U << 24) +#define SPC5_CGM_SS_FMPLL0 (4U << 24) +#define SPC5_CGM_SS_FMPLL1 (5U << 24) +#define SPC5_CGM_SS_FMPLL1_1D1 (8U << 24) +/** @} */ + +/** + * @name ME_GS register bits definitions + * @{ + */ +#define SPC5_ME_GS_SYSCLK_MASK (15U << 0) +#define SPC5_ME_GS_SYSCLK_IRC (0U << 0) +#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) +#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) +#define SPC5_ME_GS_SYSCLK_FMPLL1 (5U << 0) +/** @} */ + +/** + * @name ME_ME register bits definitions + * @{ + */ +#define SPC5_ME_ME_RESET (1U << 0) +#define SPC5_ME_ME_TEST (1U << 1) +#define SPC5_ME_ME_SAFE (1U << 2) +#define SPC5_ME_ME_DRUN (1U << 3) +#define SPC5_ME_ME_RUN0 (1U << 4) +#define SPC5_ME_ME_RUN1 (1U << 5) +#define SPC5_ME_ME_RUN2 (1U << 6) +#define SPC5_ME_ME_RUN3 (1U << 7) +#define SPC5_ME_ME_HALT0 (1U << 8) +#define SPC5_ME_ME_STOP0 (1U << 10) +/** @} */ + +/** + * @name ME_xxx_MC registers bits definitions + * @{ + */ +#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) +#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_IRCON (1U << 4) +#define SPC5_ME_MC_XOSC0ON (1U << 5) +#define SPC5_ME_MC_PLL0ON (1U << 6) +#define SPC5_ME_MC_PLL1ON (1U << 7) +#define SPC5_ME_MC_CFLAON_MASK (3U << 16) +#define SPC5_ME_MC_CFLAON(n) ((n) << 16) +#define SPC5_ME_MC_CFLAON_PD (1U << 16) +#define SPC5_ME_MC_CFLAON_LP (2U << 16) +#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16) +#define SPC5_ME_MC_DFLAON_MASK (3U << 18) +#define SPC5_ME_MC_DFLAON(n) ((n) << 18) +#define SPC5_ME_MC_DFLAON_PD (1U << 18) +#define SPC5_ME_MC_DFLAON_LP (2U << 18) +#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18) +#define SPC5_ME_MC_MVRON (1U << 20) +#define SPC5_ME_MC_PDO (1U << 23) +/** @} */ + +/** + * @name ME_MCTL register bits definitions + * @{ + */ +#define SPC5_ME_MCTL_KEY 0x5AF0U +#define SPC5_ME_MCTL_KEY_INV 0xA50FU +#define SPC5_ME_MCTL_MODE_MASK (15U << 28) +#define SPC5_ME_MCTL_MODE(n) ((n) << 28) +/** @} */ + +/** + * @name ME_RUN_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_RUN_PC_TEST (1U << 1) +#define SPC5_ME_RUN_PC_SAFE (1U << 2) +#define SPC5_ME_RUN_PC_DRUN (1U << 3) +#define SPC5_ME_RUN_PC_RUN0 (1U << 4) +#define SPC5_ME_RUN_PC_RUN1 (1U << 5) +#define SPC5_ME_RUN_PC_RUN2 (1U << 6) +#define SPC5_ME_RUN_PC_RUN3 (1U << 7) +/** @} */ + +/** + * @name ME_LP_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_LP_PC_HALT0 (1U << 8) +#define SPC5_ME_LP_PC_STOP0 (1U << 10) +/** @} */ + +/** + * @name ME_PCTL registers bits definitions + * @{ + */ +#define SPC5_ME_PCTL_RUN_MASK (7U << 0) +#define SPC5_ME_PCTL_RUN(n) ((n) << 0) +#define SPC5_ME_PCTL_LP_MASK (7U << 3) +#define SPC5_ME_PCTL_LP(n) ((n) << 3) +#define SPC5_ME_PCTL_DBG (1U << 6) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief Disables the watchdog on start. + */ +#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__) +#define SPC5_DISABLE_WATCHDOG TRUE +#endif + +/** + * @brief FMPLL0 IDF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_IDF_VALUE 5 +#endif + +/** + * @brief FMPLL0 NDIV divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_NDIV_VALUE 32 +#endif + +/** + * @brief FMPLL0 ODF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=64MHz. + */ +#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#endif + +/** + * @brief FMPLL1 IDF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_IDF_VALUE 5 +#endif + +/** + * @brief FMPLL1 NDIV divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_NDIV_VALUE 60 +#endif + +/** + * @brief FMPLL1 ODF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#endif + +/** + * @brief AUX0 clock source. + */ +#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief Motor Control clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX1 clock source. + * @note Not configurable, always selects FMPLL1. + */ +#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX1CLK_SRC 0 +#endif + +/** + * @brief FMPLL1 clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_FMPLL1_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX2 clock source. + */ +#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief SP clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_SP_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX3 clock source. + */ +#if !defined(SPC5_AUX3CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief FR clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_FR_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#endif + +/** + * @brief Active run modes in ME_ME register. + * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there + * is no need to specify them. + */ +#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#endif + +/** + * @brief TEST mode settings. + */ +#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief SAFE mode settings. + */ +#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#endif + +/** + * @brief DRUN mode settings. + */ +#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN0 mode settings. + */ +#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN1 mode settings. + */ +#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN2 mode settings. + */ +#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN3 mode settings. + */ +#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief HALT0 mode settings. + */ +#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STOP0 mode settings. + */ +#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief Peripheral mode 0 (run mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (run mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 2 (run mode). + * @note Do not change this setting, it is expected to be the "only during + * normal run" mode. + */ +#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 3 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 4 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 5 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 6 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 7 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 0 (low power mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (low power mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 2 (low power mode). + * @note Do not change this setting, it is expected to be the "halt only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#endif + +/** + * @brief Peripheral mode 3 (low power mode). + * @note Do not change this setting, it is expected to be the "stop only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 4 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 5 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 6 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 7 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief PIT channel 0 IRQ priority. + * @note This PIT channel is allocated permanently for system tick + * generation. + */ +#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#endif + +/** + * @brief Clock initialization failure hook. + * @note The default is to stop the system and let the RTC restart it. + * @note The hook code must not return. + */ +#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC560Pxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC560Pxx_MCUCONF not defined" +#endif + +/* Check on the XOSC frequency.*/ +#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ + (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) +#error "invalid SPC5_XOSC_CLK value specified" +#endif + +/* Check on SPC5_FMPLL0_IDF_VALUE.*/ +#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL0_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_NDIV_VALUE.*/ +#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_ODF.*/ +#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL0_ODF_VALUE 2 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL0_ODF_VALUE 4 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL0_ODF_VALUE 8 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL0_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL0_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL0_VCO_CLK clock point. + */ +#define SPC5_FMPLL0_VCO_CLK \ + ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE) + +/* Check on FMPLL0 VCO output.*/ +#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL0_CLK clock point. + */ +#define SPC5_FMPLL0_CLK \ + (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE) + +/* Check on SPC5_FMPLL0_CLK.*/ +#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)" +#endif + +#if SPC5_HAS_FMPLL1 +/* Check on SPC5_FMPLL1_IDF_VALUE.*/ +#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL1_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL1_NDIV_VALUE.*/ +#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL1_ODF.*/ +#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL1_ODF_VALUE 2 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL1_ODF_VALUE 4 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL1_ODF_VALUE 8 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL1_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL1_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL1_VCO_CLK clock point. + */ +#define SPC5_FMPLL1_VCO_CLK \ + ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE) + +/* Check on FMPLL1 VCO output.*/ +#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL1_CLK clock point. + */ +#define SPC5_FMPLL1_CLK \ + (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE) + +/* Check on SPC5_FMPLL1_CLK.*/ +#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)" +#endif +#endif /* SPC5_HAS_FMPLL1 */ + +#if SPC5_HAS_AC0 || defined(__DOXYGEN__) +/** + * @brief AUX0 clock point. + */ +#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__) +#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_IRC +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC +#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_XOSC +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0 +#define SPC5_AUX0_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX0_CLK SPC5_FMPLL1_CLK +#else +#error "invalid SPC5_AUX0CLK_SRC value specified" +#endif + +#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1) +#error "SPC5_AUX0CLK_SRC, FMPLL1 not present" +#endif + +/* Check on the AUX0 divider 0 settings.*/ +#if SPC5_MCONTROL_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC0_DC0 0 +#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC0_DC0 ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified" +#endif + +/** + * @brief Motor Control clock point. + */ +#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_MCONTROL_CLK (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE) +#else +#define SPC5_MCONTROL_CLK 0 +#endif +#endif /* #if SPC5_HAS_AC0 */ + +#if SPC5_HAS_AC1 || defined(__DOXYGEN__) +/** + * @brief AUX1 clock point. + */ +#if (SPC5_AUX1CLK_SRC == 0) || defined(__DOXYGEN__) +#define SPC5_AUX1_CLK SPC5_FMPLL1_CLK +#else +#error "invalid SPC5_AUX1CLK_SRC value specified" +#endif + +#if !SPC5_HAS_FMPLL1 +#error "SPC5_AUX1_CLK, FMPLL1 not present" +#endif + +/* Check on the AUX1 divider 0 settings.*/ +#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC1_DC0 0 +#elif (SPC5_FMPLL1_CLK_DIVIDER_VALUE >= 1) && (SPC5_FMPLL1_CLK_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC1_DC0 ((0x80U | (SPC5_FMPLL1_CLK_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_FMPLL1_CLK_DIVIDER_VALUE value specified" +#endif + +/** + * @brief FMPLL1 clock point. + */ +#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_FMPLL1_DIV_CLK (SPC5_AUX1_CLK / SPC5_FMPLL1_CLK_DIVIDER_VALUE) +#else +#define SPC5_FMPLL1_DIV_CLK 0 +#endif +#endif /* SPC5_HAS_AC1 */ + +#if SPC5_HAS_AC2 || defined(__DOXYGEN__) +/** + * @brief AUX2 clock point. + */ +#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__) +#define SPC5_AUX2_CLK SPC5_FMPLL_SRC_IRC +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_XOSC +#define SPC5_AUX2_CLK SPC5_FMPLL_SRC_XOSC +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0 +#define SPC5_AUX2_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX2_CLK SPC5_FMPLL1_CLK +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1 +#define SPC5_AUX2_CLK SPC5_FMPLL1_1D1_CLK +#else +#error "invalid SPC5_AUX2CLK_SRC value specified" +#endif + +#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1) || \ + (SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1_1D1)) +#error "SPC5_AUX2_CLK, FMPLL1 not present" +#endif + +/* Check on the AUX2 divider 0 settings.*/ +#if SPC5_SP_CLK_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC2_DC0 0 +#elif (SPC5_SP_CLK_DIVIDER_VALUE >= 1) && (SPC5_SP_CLK_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC2_DC0 ((0x80U | (SPC5_SP_CLK_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_SP_CLK_DIVIDER_VALUE value specified" +#endif + +/** + * @brief SP clock point. + */ +#if (SPC5_SP_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_SP_CLK (SPC5_AUX2_CLK / SPC5_SP_CLK_DIVIDER_VALUE) +#else +#define SPC5_SP_CLK 0 +#endif +#endif /* SPC5_HAS_AC2 */ + +#if SPC5_HAS_AC3 || defined(__DOXYGEN__) +/** + * @brief AUX3 clock point. + */ +#if (SPC5_AUX3CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__) +#define SPC5_AUX3_CLK SPC5_FMPLL_SRC_IRC +#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_XOSC +#define SPC5_AUX3_CLK SPC5_FMPLL_SRC_XOSC +#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL0 +#define SPC5_AUX3_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX3_CLK SPC5_FMPLL1_CLK +#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1 +#define SPC5_AUX3_CLK SPC5_FMPLL1_1D1_CLK +#else +#error "invalid SPC5_AUX3CLK_SRC value specified" +#endif + +#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) || \ + (SPC5_AUX3_CLK == SPC5_CGM_SS_FMPLL1_1D1)) +#error "SPC5_AUX3_CLK, FMPLL1 not present" +#endif + +/* Check on the AUX3 divider 0 settings.*/ +#if SPC5_FR_CLK_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC3_DC0 0 +#elif (SPC5_FR_CLK_DIVIDER_VALUE >= 1) && (SPC5_FR_CLK_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC3_DC0 ((0x80U | (SPC5_FR_CLK_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_FR_CLK_DIVIDER_VALUE value specified" +#endif + +/** + * @brief FR clock point. + */ +#if (SPC5_FR_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_FR_CLK (SPC5_AUX3_CLK / SPC5_FR_CLK_DIVIDER_VALUE) +#else +#define SPC5_FR_CLK 0 +#endif +#endif /* SPC5_HAS_AC3 */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef enum { + SPC5_RUNMODE_TEST = 1, + SPC5_RUNMODE_SAFE = 2, + SPC5_RUNMODE_DRUN = 3, + SPC5_RUNMODE_RUN0 = 4, + SPC5_RUNMODE_RUN1 = 5, + SPC5_RUNMODE_RUN2 = 6, + SPC5_RUNMODE_RUN3 = 7, + SPC5_RUNMODE_HALT0 = 8, + SPC5_RUNMODE_STOP0 = 10 +} spc5_runmode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); + bool_t halSPCSetRunMode(spc5_runmode_t mode); + void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); +#if !SPC5_NO_INIT + uint32_t halSPCGetSystemClock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Pxx/platform.mk b/os/hal/platforms/SPC560Pxx/platform.mk new file mode 100644 index 000000000..2e82732d1 --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/platform.mk @@ -0,0 +1,17 @@ +# List of all the SPC560Pxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1 diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h new file mode 100644 index 000000000..4f528056e --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -0,0 +1,324 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Pxx/spc560p_registry.h + * @brief SPC560Pxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC560P_REGISTRY_H_ +#define _SPC560P_REGISTRY_H_ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_) +#define _SPC560P34_ +#define _SPC560PXX_SMALL_ +#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_) +#define _SPC560P40_ +#define _SPC560PXX_SMALL_ +#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_) +#define _SPC560P44_ +#define _SPC560PXX_MEDIUM_ +#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_) +#define _SPC560P50_ +#define _SPC560PXX_MEDIUM_ +#elif defined(_SPC560P54L5_) || defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_) +#define _SPC560P54_ +#define _SPC560PXX_LARGE_ +#elif defined(_SPC560P60L5_) || defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_) +#define _SPC560P60_ +#define _SPC560PXX_LARGE_ +#else +#error "SPC56xPxx platform not defined" +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC560Pxx capabilities + * @{ + */ +/* Clock attributes.*/ +#if defined(_SPC560PXX_SMALL_) +#define SPC5_HAS_FMPLL1 FALSE +#define SPC5_HAS_CLOCKOUT TRUE +#define SPC5_HAS_AC0 FALSE +#define SPC5_HAS_AC1 FALSE +#define SPC5_HAS_AC2 FALSE +#define SPC5_HAS_AC3 FALSE + +#elif defined(_SPC560PXX_MEDIUM_) +#define SPC5_HAS_FMPLL1 TRUE +#define SPC5_HAS_CLOCKOUT TRUE +#define SPC5_HAS_AC0 TRUE +#define SPC5_HAS_AC1 TRUE +#define SPC5_HAS_AC2 TRUE +#define SPC5_HAS_AC3 TRUE + +#else /* defined(_SPC560PXX_LARGE_) */ +#define SPC5_HAS_FMPLL1 FALSE +#define SPC5_HAS_CLOCKOUT TRUE +#define SPC5_HAS_AC0 FALSE +#define SPC5_HAS_AC1 FALSE +#define SPC5_HAS_AC2 FALSE +#define SPC5_HAS_AC3 TRUE +#endif + +/* DSPI attribures.*/ +#define SPC5_HAS_DSPI0 TRUE +#define SPC5_HAS_DSPI1 TRUE +#define SPC5_HAS_DSPI2 TRUE +#define SPC5_DSPI_FIFO_DEPTH 5 +#define SPC5_DSPI0_PCTL 4 +#define SPC5_DSPI1_PCTL 5 +#define SPC5_DSPI2_PCTL 6 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_DSPI2_TX1_DMA_CH_ID 10 +#define SPC5_DSPI2_TX2_DMA_CH_ID 11 +#define SPC5_DSPI2_RX_DMA_CH_ID 12 +#define SPC5_DSPI0_TX1_DMA_DEV_ID 1 +#define SPC5_DSPI0_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI0_RX_DMA_DEV_ID 2 +#define SPC5_DSPI1_TX1_DMA_DEV_ID 3 +#define SPC5_DSPI1_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI1_RX_DMA_DEV_ID 4 +#define SPC5_DSPI2_TX1_DMA_DEV_ID 5 +#define SPC5_DSPI2_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI2_RX_DMA_DEV_ID 6 +#define SPC5_DSPI0_TFFF_HANDLER vector76 +#define SPC5_DSPI0_TFFF_NUMBER 76 +#define SPC5_DSPI1_TFFF_HANDLER vector96 +#define SPC5_DSPI1_TFFF_NUMBER 96 +#define SPC5_DSPI2_TFFF_HANDLER vector116 +#define SPC5_DSPI2_TFFF_NUMBER 116 +#define SPC5_DSPI0_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL) +#define SPC5_DSPI0_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL) +#define SPC5_DSPI1_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL) +#define SPC5_DSPI1_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL) +#define SPC5_DSPI2_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL) +#define SPC5_DSPI2_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL) + +#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_) +#define SPC5_HAS_DSPI3 TRUE +#define SPC5_DSPI3_PCTL 7 +#define SPC5_DSPI3_TX1_DMA_CH_ID 13 +#define SPC5_DSPI3_TX2_DMA_CH_ID 14 +#define SPC5_DSPI3_RX_DMA_CH_ID 15 +#define SPC5_DSPI3_TX1_DMA_DEV_ID 7 +#define SPC5_DSPI3_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI3_RX_DMA_DEV_ID 8 +#define SPC5_DSPI3_TFFF_HANDLER vector219 +#define SPC5_DSPI3_TFFF_NUMBER 219 +#define SPC5_DSPI3_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL) +#define SPC5_DSPI3_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL) +#else +#define SPC5_HAS_DSPI3 FALSE +#endif + +#if defined(_SPC560PXX_LARGE_) +#define SPC5_HAS_DSPI4 TRUE +#define SPC5_DSPI4_PCTL 8 +#define SPC5_DSPI4_TX1_DMA_CH_ID 1 +#define SPC5_DSPI4_TX2_DMA_CH_ID 2 +#define SPC5_DSPI4_RX_DMA_CH_ID 3 +#define SPC5_DSPI4_TX1_DMA_DEV_ID 15 +#define SPC5_DSPI4_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI4_RX_DMA_DEV_ID 21 +#define SPC5_DSPI4_TFFF_HANDLER vector258 +#define SPC5_DSPI4_TFFF_NUMBER 258 +#define SPC5_DSPI4_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL) +#define SPC5_DSPI4_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI4_STOP_PCTL) +#else +#define SPC5_HAS_DSPI4 FALSE +#endif + +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA TRUE +#define SPC5_EDMA_NCHANNELS 16 +#define SPC5_EDMA_HAS_MUX TRUE + +/* LINFlex attributes.*/ +#define SPC5_HAS_LINFLEX0 TRUE +#define SPC5_LINFLEX0_PCTL 48 +#define SPC5_LINFLEX0_RXI_HANDLER vector79 +#define SPC5_LINFLEX0_TXI_HANDLER vector80 +#define SPC5_LINFLEX0_ERR_HANDLER vector81 +#define SPC5_LINFLEX0_RXI_NUMBER 79 +#define SPC5_LINFLEX0_TXI_NUMBER 80 +#define SPC5_LINFLEX0_ERR_NUMBER 81 +#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / 1) + +#define SPC5_HAS_LINFLEX1 TRUE +#define SPC5_LINFLEX1_PCTL 49 +#define SPC5_LINFLEX1_RXI_HANDLER vector99 +#define SPC5_LINFLEX1_TXI_HANDLER vector100 +#define SPC5_LINFLEX1_ERR_HANDLER vector101 +#define SPC5_LINFLEX1_RXI_NUMBER 99 +#define SPC5_LINFLEX1_TXI_NUMBER 100 +#define SPC5_LINFLEX1_ERR_NUMBER 101 +#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / 1) + +#define SPC5_HAS_LINFLEX2 FALSE + +#define SPC5_HAS_LINFLEX3 FALSE + +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_NUM_PORTS 8 +#if defined(_SPC560PXX_SMALL_) +#define SPC5_SIUL_NUM_PCRS 72 +#else +#define SPC5_SIUL_NUM_PCRS 108 +#endif +#define SPC5_SIUL_NUM_PADSELS 36 + +/* FlexPWM attributes.*/ +#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_) +#define SPC5_HAS_FLEXPWM0 TRUE +#define SPC5_FLEXPWM0_PCTL 41 +#define SPC5_FLEXPWM0_RF0_HANDLER vector179 +#define SPC5_FLEXPWM0_COF0_HANDLER vector180 +#define SPC5_FLEXPWM0_CAF0_HANDLER vector181 +#define SPC5_FLEXPWM0_RF1_HANDLER vector182 +#define SPC5_FLEXPWM0_COF1_HANDLER vector183 +#define SPC5_FLEXPWM0_CAF1_HANDLER vector184 +#define SPC5_FLEXPWM0_RF2_HANDLER vector185 +#define SPC5_FLEXPWM0_COF2_HANDLER vector186 +#define SPC5_FLEXPWM0_CAF2_HANDLER vector187 +#define SPC5_FLEXPWM0_RF3_HANDLER vector188 +#define SPC5_FLEXPWM0_COF3_HANDLER vector189 +#define SPC5_FLEXPWM0_CAF3_HANDLER vector190 +#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191 +#define SPC5_FLEXPWM0_REF_HANDLER vector192 +#define SPC5_FLEXPWM0_RF0_NUMBER 179 +#define SPC5_FLEXPWM0_COF0_NUMBER 180 +#define SPC5_FLEXPWM0_CAF0_NUMBER 181 +#define SPC5_FLEXPWM0_RF1_NUMBER 182 +#define SPC5_FLEXPWM0_COF1_NUMBER 183 +#define SPC5_FLEXPWM0_CAF1_NUMBER 184 +#define SPC5_FLEXPWM0_RF2_NUMBER 185 +#define SPC5_FLEXPWM0_COF2_NUMBER 186 +#define SPC5_FLEXPWM0_CAF2_NUMBER 187 +#define SPC5_FLEXPWM0_RF3_NUMBER 188 +#define SPC5_FLEXPWM0_COF3_NUMBER 189 +#define SPC5_FLEXPWM0_CAF3_NUMBER 190 +#define SPC5_FLEXPWM0_FFLAG_NUMBER 191 +#define SPC5_FLEXPWM0_REF_NUMBER 192 +#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK +#else /* defined(_SPC560PXX_LARGE_) */ +#define SPC5_HAS_FLEXPWM0 FALSE +#endif /* defined(_SPC560PXX_LARGE_) */ + +#define SPC5_HAS_FLEXPWM1 FALSE + +/* eTimer attributes.*/ +#define SPC5_HAS_ETIMER0 TRUE +#define SPC5_ETIMER0_PCTL 38 +#define SPC5_ETIMER0_TC0IR_HANDLER vector157 +#define SPC5_ETIMER0_TC1IR_HANDLER vector158 +#define SPC5_ETIMER0_TC2IR_HANDLER vector159 +#define SPC5_ETIMER0_TC3IR_HANDLER vector160 +#define SPC5_ETIMER0_TC4IR_HANDLER vector161 +#define SPC5_ETIMER0_TC5IR_HANDLER vector162 +#define SPC5_ETIMER0_WTIF_HANDLER vector165 +#define SPC5_ETIMER0_RCF_HANDLER vector167 +#define SPC5_ETIMER0_TC0IR_NUMBER 157 +#define SPC5_ETIMER0_TC1IR_NUMBER 158 +#define SPC5_ETIMER0_TC2IR_NUMBER 159 +#define SPC5_ETIMER0_TC3IR_NUMBER 160 +#define SPC5_ETIMER0_TC4IR_NUMBER 161 +#define SPC5_ETIMER0_TC5IR_NUMBER 162 +#define SPC5_ETIMER0_WTIF_NUMBER 165 +#define SPC5_ETIMER0_RCF_NUMBER 167 +#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK + +#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_) +#define SPC5_HAS_ETIMER1 TRUE +#define SPC5_ETIMER1_PCTL 39 +#define SPC5_ETIMER1_TC0IR_HANDLER vector168 +#define SPC5_ETIMER1_TC1IR_HANDLER vector169 +#define SPC5_ETIMER1_TC2IR_HANDLER vector170 +#define SPC5_ETIMER1_TC3IR_HANDLER vector171 +#define SPC5_ETIMER1_TC4IR_HANDLER vector172 +#define SPC5_ETIMER1_TC5IR_HANDLER vector173 +#define SPC5_ETIMER1_RCF_HANDLER vector178 +#define SPC5_ETIMER1_TC0IR_NUMBER 168 +#define SPC5_ETIMER1_TC1IR_NUMBER 169 +#define SPC5_ETIMER1_TC2IR_NUMBER 170 +#define SPC5_ETIMER1_TC3IR_NUMBER 171 +#define SPC5_ETIMER1_TC4IR_NUMBER 172 +#define SPC5_ETIMER1_TC5IR_NUMBER 173 +#define SPC5_ETIMER1_RCF_NUMBER 178 +#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK + +#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */ +#define SPC5_HAS_ETIMER1 FALSE +#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */ + +#define SPC5_HAS_ETIMER2 FALSE + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 32 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 +#define SPC5_FLEXCAN0_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL) +#define SPC5_FLEXCAN0_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL) +/** @} */ + +#endif /* _SPC560P_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC560Pxx/typedefs.h b/os/hal/platforms/SPC560Pxx/typedefs.h new file mode 100644 index 000000000..9393cb167 --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Pxx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC560Pxx/xpc560p.h b/os/hal/platforms/SPC560Pxx/xpc560p.h new file mode 100644 index 000000000..76ea503ca --- /dev/null +++ b/os/hal/platforms/SPC560Pxx/xpc560p.h @@ -0,0 +1,7801 @@ +/***************************************************************** + * PROJECT : MPC5604P + * FILE : 5604P_Header_v1_10.h + * + * DESCRIPTION : This is the header file describing the register + * set for the named projects. + * + * COPYRIGHT :(c) 2012, Freescale + * + * VERSION : 01.10 + * DATE : 12.06.2012 + * AUTHOR : B16991 + * HISTORY : Changes: typo fixed in PSR1 register:SCP -> CSP, MCR: PRESCALE->BITRATE (b16991) + * HISTORY : Changes: typo fixed in ME register MTC bit, SSCM fix, CMU changes(b16991) + * HISTORY : Changes to CTU Module: CR register (LC->FC), CLR changed to 24 bits (b16991) + * HISTORY : Modified to add reserved space in CTU (b16991) + * HISTORY : Modified to support ADC on Pictus cut 2 - do not distribute! (ttz778) + * HISTORY : Modified to support CRC on Pictus cut 2 - do not distribute! (r60321) + * HISTORY : Modified to support DSPI0 CS7&8 and new FlexPWM naming on Pictus cut 2 (r60321) + * HISTORY : Modified to update MIDR1&2 registers and LINCR1-SFTM and LINESR-BDEF bit on Pictus (r60321) + * HISTORY : Modified to update RGM, CFLASH & DFLASH registers and FlexCAN & CTU Registers on Pictus (r60321) + * HISTORY : Modified to update DSPI Registers (FIFO deep) on Pictus (b16991) + * + ***************************************************************** + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ******************************************************************/ +/***************************************************************** +* Example instantiation and use: +* +* ..B. = 1; +* ..R = 0x10000000; +* +******************************************************************/ + +#ifndef _JDP_H_ +#define _JDP_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif +/****************************************************************************/ +/* MODULE : ADC */ +/****************************************************************************/ + struct ADC_tag { + + union { + vuint32_t R; + struct { + vuint32_t OWREN:1; + vuint32_t WLSIDE:1; + vuint32_t MODE:1; + vuint32_t EDGLEV:1; + vuint32_t TRGEN:1; + vuint32_t EDGE:1; + vuint32_t XSTRTEN:1; + vuint32_t NSTART:1; + vuint32_t:1; + vuint32_t JTRGEN:1; + vuint32_t JEDGE:1; + vuint32_t JSTART:1; + vuint32_t:2; + vuint32_t CTUEN:1; + vuint32_t:8; + vuint32_t ADCLKSEL:1; + vuint32_t ABORTCHAIN:1; + vuint32_t ABORT:1; + vuint32_t ACK0:1; + vuint32_t OFFREFRESH:1; + vuint32_t OFFCANC:1; + vuint32_t:2; + vuint32_t PWDN:1; + } B; + } MCR; /* MAIN CONFIGURATION REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t NSTART:1; + vuint32_t JABORT:1; + vuint32_t:2; + vuint32_t JSTART:1; + vuint32_t:3; + vuint32_t CTUSTART:1; + vuint32_t CHADDR:7; + vuint32_t:3; + vuint32_t ACK0:1; + vuint32_t OFFREFRESH:1; + vuint32_t OFFCANC:1; + vuint32_t ADCSTATUS:3; + } B; + } MSR; /* MAIN STATUS REGISTER */ + + int32_t ADC_reserved1[2]; /* (0x008 - 0x00F)/4 = 0x02 */ + + union { + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t OFFCANCOVR:1; + vuint32_t EOFFSET:1; + vuint32_t EOCTU:1; + vuint32_t JEOC:1; + vuint32_t JECH:1; + vuint32_t EOC:1; + vuint32_t ECH:1; + } B; + } ISR; /* INTERRUPT STATUS REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t EOC31:1; + vuint32_t EOC30:1; + vuint32_t EOC29:1; + vuint32_t EOC28:1; + vuint32_t EOC27:1; + vuint32_t EOC26:1; + vuint32_t EOC25:1; + vuint32_t EOC24:1; + vuint32_t EOC23:1; + vuint32_t EOC22:1; + vuint32_t EOC21:1; + vuint32_t EOC20:1; + vuint32_t EOC19:1; + vuint32_t EOC18:1; + vuint32_t EOC17:1; + vuint32_t EOC16:1; + vuint32_t EOC15:1; + vuint32_t EOC14:1; + vuint32_t EOC13:1; + vuint32_t EOC12:1; + vuint32_t EOC11:1; + vuint32_t EOC10:1; + vuint32_t EOC9:1; + vuint32_t EOC8:1; + vuint32_t EOC7:1; + vuint32_t EOC6:1; + vuint32_t EOC5:1; + vuint32_t EOC4:1; + vuint32_t EOC3:1; + vuint32_t EOC2:1; + vuint32_t EOC1:1; + vuint32_t EOC0:1; + } B; + } CEOCFR[3]; /* Channel Pending Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:25; //One bit added + vuint32_t MSKOFFCANCOVR:1; //Moved up + vuint32_t MSKEOFFSET:1; //Moved up + vuint32_t MSKEOCTU:1; //New for cut 2 + vuint32_t MSKJEOC:1; + vuint32_t MSKJECH:1; + vuint32_t MSKEOC:1; + vuint32_t MSKECH:1; + } B; + } IMR; /* INTERRUPT MASK REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t CIM31:1; + vuint32_t CIM30:1; + vuint32_t CIM29:1; + vuint32_t CIM28:1; + vuint32_t CIM27:1; + vuint32_t CIM26:1; + vuint32_t CIM25:1; + vuint32_t CIM24:1; + vuint32_t CIM23:1; + vuint32_t CIM22:1; + vuint32_t CIM21:1; + vuint32_t CIM20:1; + vuint32_t CIM19:1; + vuint32_t CIM18:1; + vuint32_t CIM17:1; + vuint32_t CIM16:1; + vuint32_t CIM15:1; + vuint32_t CIM14:1; + vuint32_t CIM13:1; + vuint32_t CIM12:1; + vuint32_t CIM11:1; + vuint32_t CIM10:1; + vuint32_t CIM9:1; + vuint32_t CIM8:1; + vuint32_t CIM7:1; + vuint32_t CIM6:1; + vuint32_t CIM5:1; + vuint32_t CIM4:1; + vuint32_t CIM3:1; + vuint32_t CIM2:1; + vuint32_t CIM1:1; + vuint32_t CIM0:1; + } B; + } CIMR[3]; /* Channel Interrupt Mask Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t WDG3H:1; + vuint32_t WDG2H:1; + vuint32_t WDG1H:1; + vuint32_t WDG0H:1; + vuint32_t WDG3L:1; + vuint32_t WDG2L:1; + vuint32_t WDG1L:1; + vuint32_t WDG0L:1; + } B; + } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER was WDGTHR */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t MSKWDG3H:1; + vuint32_t MSKWDG2H:1; + vuint32_t MSKWDG1H:1; + vuint32_t MSKWDG0H:1; + vuint32_t MSKWDG3L:1; + vuint32_t MSKWDG2L:1; + vuint32_t MSKWDG1L:1; + vuint32_t MSKWDG0L:1; + } B; + } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER was IMWDGTHR */ + + int32_t ADC_reserved2[2]; /* (0x038 - 0x03F)/4 = 0x02 */ + + union { + vuint32_t R; + struct { + vuint32_t:30; //was 16 + vuint32_t DCLR:1; //moved + vuint32_t DMAEN:1; //moved + } B; + } DMAE; /* DMAE REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t DMA31:1; //was unused [16] + vuint32_t DMA30:1; + vuint32_t DMA29:1; + vuint32_t DMA28:1; + vuint32_t DMA27:1; + vuint32_t DMA26:1; + vuint32_t DMA25:1; + vuint32_t DMA24:1; + vuint32_t DMA23:1; + vuint32_t DMA22:1; + vuint32_t DMA21:1; + vuint32_t DMA20:1; + vuint32_t DMA19:1; + vuint32_t DMA18:1; + vuint32_t DMA17:1; + vuint32_t DMA16:1; + vuint32_t DMA15:1; + vuint32_t DMA14:1; + vuint32_t DMA13:1; + vuint32_t DMA12:1; + vuint32_t DMA11:1; + vuint32_t DMA10:1; + vuint32_t DMA9:1; + vuint32_t DMA8:1; + vuint32_t DMA7:1; + vuint32_t DMA6:1; + vuint32_t DMA5:1; + vuint32_t DMA4:1; + vuint32_t DMA3:1; + vuint32_t DMA2:1; + vuint32_t DMA1:1; + vuint32_t DMA0:1; + } B; + } DMAR[3]; /* DMA REGISTER was [6] */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t THREN:1; + vuint32_t THRINV:1; + vuint32_t THROP:1; + vuint32_t:6; + vuint32_t THRCH:7; + } B; + } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */ + + union { + vuint32_t R; + struct { //were in TRA & TRB + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRHLR[4]; /* THRESHOLD REGISTER */ + + union { + vuint32_t R; + struct { //were in TRAALT & TRBALT + vuint32_t:4; + vuint32_t THRH:12; + vuint32_t:4; + vuint32_t THRL:12; + } B; + } THRALT[4]; /* ADC THRESHOLD REGISTER REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:25; //was 26 + vuint32_t PREVAL2:2; + vuint32_t PREVAL1:2; + vuint32_t PREVAL0:2; + vuint32_t PREONCE:1; + } B; + } PSCR; /* PRESAMPLING CONTROL REGISTER was PREREG */ + + union { + vuint32_t R; + struct { + vuint32_t PRES31:1; //was reserved 16 + vuint32_t PRES30:1; + vuint32_t PRES29:1; + vuint32_t PRES28:1; + vuint32_t PRES27:1; + vuint32_t PRES26:1; + vuint32_t PRES25:1; + vuint32_t PRES24:1; + vuint32_t PRES23:1; + vuint32_t PRES22:1; + vuint32_t PRES21:1; + vuint32_t PRES20:1; + vuint32_t PRES19:1; + vuint32_t PRES18:1; + vuint32_t PRES17:1; + vuint32_t PRES16:1; + vuint32_t PRES15:1; + vuint32_t PRES14:1; + vuint32_t PRES13:1; + vuint32_t PRES12:1; + vuint32_t PRES11:1; + vuint32_t PRES10:1; + vuint32_t PRES9:1; + vuint32_t PRES8:1; + vuint32_t PRES7:1; + vuint32_t PRES6:1; + vuint32_t PRES5:1; + vuint32_t PRES4:1; + vuint32_t PRES3:1; + vuint32_t PRES2:1; + vuint32_t PRES1:1; + vuint32_t PRES0:1; + } B; + } PSR[3]; /* PRESAMPLING REGISTER was PRER[6]*/ + + int32_t ADC_reserved3[1]; /* (0x090 - 0x093)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; + vuint32_t:1; + vuint32_t OFFSHIFT:2; //!!! This field only in CTR[0] + vuint32_t:1; + vuint32_t INPCMP:2; + vuint32_t:1; + vuint32_t INPSAMP:8; + } B; + } CTR[3]; /* CONVERSION TIMING REGISTER was CT[3] */ + + int32_t ADC_reserved4[1]; /* (0x0A0 - 0x0A3)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t CH31:1; //was reserved 16 + vuint32_t CH30:1; + vuint32_t CH29:1; + vuint32_t CH28:1; + vuint32_t CH27:1; + vuint32_t CH26:1; + vuint32_t CH25:1; + vuint32_t CH24:1; + vuint32_t CH23:1; + vuint32_t CH22:1; + vuint32_t CH21:1; + vuint32_t CH20:1; + vuint32_t CH19:1; + vuint32_t CH18:1; + vuint32_t CH17:1; + vuint32_t CH16:1; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER was [6] */ + + int32_t ADC_reserved5[1]; /* (0x0B0 - 0x0B3)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t CH31:1; //was reserved 16 + vuint32_t CH30:1; + vuint32_t CH29:1; + vuint32_t CH28:1; + vuint32_t CH27:1; + vuint32_t CH26:1; + vuint32_t CH25:1; + vuint32_t CH24:1; + vuint32_t CH23:1; + vuint32_t CH22:1; + vuint32_t CH21:1; + vuint32_t CH20:1; + vuint32_t CH19:1; + vuint32_t CH18:1; + vuint32_t CH17:1; + vuint32_t CH16:1; + vuint32_t CH15:1; + vuint32_t CH14:1; + vuint32_t CH13:1; + vuint32_t CH12:1; + vuint32_t CH11:1; + vuint32_t CH10:1; + vuint32_t CH9:1; + vuint32_t CH8:1; + vuint32_t CH7:1; + vuint32_t CH6:1; + vuint32_t CH5:1; + vuint32_t CH4:1; + vuint32_t CH3:1; + vuint32_t CH2:1; + vuint32_t CH1:1; + vuint32_t CH0:1; + } B; + } JCMR[3]; /* Injected CONVERSION MASK REGISTER was ICMR[6] */ + + union { + vuint32_t R; + struct { + vuint32_t:15; + vuint32_t OFFSETLOAD:1; //new + vuint32_t:8; + vuint32_t OFFSETWORD:8; + } B; + } OFFWR; /* OFFSET WORD REGISTER was OFFREG*/ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t DSD:8; + } B; + } DSDR; /* DECODE SIGNALS DELAY REGISTER was DSD */ + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t PDED:8; //was PDD + } B; + } PDEDR; /* POWER DOWN DELAY REGISTER was PDD */ + + int32_t ADC_reserved6[9]; /* (0x0CC - 0x0EF)/4 = 0x09 */ + + union { + vuint32_t R; + struct { + vuint32_t TEST_CTL:32; + } B; + } TCTLR; /* Test control REGISTER */ + + int32_t ADC_reserved7[3]; /* (0x0F4 - 0x0FF)/4 = 0x03 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t VALID:1; + vuint32_t OVERW:1; + vuint32_t RESULT:2; + vuint32_t:4; + vuint32_t CDATA:12; + } B; + } CDR[96]; /* Channel 0-95 Data REGISTER */ + + }; /* end of ADC_tag */ +/****************************************************************************/ +/* MODULE : CANSP */ +/****************************************************************************/ + struct CANSP_tag { + union { + vuint16_t R; + struct { + vuint16_t RX_COMPLETE:1; + vuint16_t BUSY:1; + vuint16_t ACTIVE_CK:1; + vuint16_t:3; + vuint16_t MODE:1; + vuint16_t CAN_RX_SEL:3; + vuint16_t BRP:5; + vuint16_t CAN_SMPLR_EN:1; + } B; + } CR; /* CANSP Control Register */ + + int16_t CANSP_reserved; + + union { + vuint32_t R; + } SR[12]; /* CANSP Sample Register 0 to 11 */ + + }; /* end of CANSP_tag */ +/****************************************************************************/ +/* MODULE : MCM */ +/****************************************************************************/ + struct MCM_tag { + + union { + vuint16_t R; + } PCT; /* MCM Processor Core Type Register */ + + union { + vuint16_t R; + } REV; /* MCM Revision Register */ + + int32_t MCM_reserved; + + union { + vuint32_t R; + } MC; /* MCM Configuration Register */ + + int8_t MCM_reserved1[3]; + + union { + vuint8_t R; + struct { + vuint8_t POR:1; + vuint8_t DIR:1; + vuint8_t:6; + } B; + } MRSR; /* MCM Miscellaneous Reset Status Register */ + + int8_t MCM_reserved2[3]; + + union { + vuint8_t R; + struct { + vuint8_t ENBWCR:1; + vuint8_t:3; + vuint8_t PRILVL:4; + } B; + } MWCR; /* MCM Miscellaneous Wakeup Control Register */ + + int32_t MCM_reserved3[2]; + int8_t MCM_reserved4[3]; + + union { + vuint8_t R; + struct { + vuint8_t FB0AI:1; + vuint8_t FB0SI:1; + vuint8_t FB1AI:1; + vuint8_t FB1SI:1; + vuint8_t:4; + } B; + } MIR; /* MCM Miscellaneous Interrupt Register */ + + int32_t MCM_reserved5; + + union { + vuint32_t R; + } MUDCR; /* MCM Miscellaneous User-Defined Control Register */ + + int32_t MCM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */ + int8_t MCM_reserved7[3]; + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t ER1BR:1; + vuint8_t EF1BR:1; + vuint8_t:2; + vuint8_t ERNCR:1; + vuint8_t EFNCR:1; + } B; + } ECR; /* MCM ECC Configuration Register */ + + int8_t MCM_reserved8[3]; + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t R1BC:1; + vuint8_t F1BC:1; + vuint8_t:2; + vuint8_t RNCE:1; + vuint8_t FNCE:1; + } B; + } ESR; /* MCM ECC Status Register */ + + int16_t MCM_reserved9; + + union { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t FRC1BI:1; + vuint16_t FR11BI:1; + vuint16_t:2; + vuint16_t FRCNCI:1; + vuint16_t FR1NCI:1; + vuint16_t:1; + vuint16_t ERRBIT:7; + } B; + } EEGR; /* MCM ECC Error Generation Register */ + + int32_t MCM_reserved10; + + union { + vuint32_t R; + } FEAR; /* MCM Flash ECC Address Register */ + + int16_t MCM_reserved11; + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; + } B; + } FEMR; /* MCM Flash ECC Master Number Register */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } FEAT; /* MCM Flash ECC Attributes Register */ + + int32_t MCM_reserved12; + + union { + vuint32_t R; + } FEDR; /* MCM Flash ECC Data Register */ + + union { + vuint32_t R; + } REAR; /* MCM RAM ECC Address Register */ + + int8_t MCM_reserved13; + + union { + vuint8_t R; + } RESR; /* MCM RAM ECC Address Register */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; + } B; + } REMR; /* MCM RAM ECC Master Number Register */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROTECTION:4; + } B; + } REAT; /* MCM RAM ECC Attributes Register */ + + int32_t MCM_reserved14; + + union { + vuint32_t R; + } REDR; /* MCM RAM ECC Data Register */ + + }; /* end of MCM_tag */ +/****************************************************************************/ +/* MODULE : RTC */ +/****************************************************************************/ + struct RTC_tag { + union { + vuint32_t R; + struct { + vuint32_t SUPV:1; + vuint32_t:31; + } B; + } RTCSUPV; /* RTC Supervisor Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t CNTEN:1; + vuint32_t RTCIE:1; + vuint32_t FRZEN:1; + vuint32_t ROVREN:1; + vuint32_t RTCVAL:12; + vuint32_t APIEN:1; + vuint32_t APIE:1; + vuint32_t CLKSEL:2; + vuint32_t DIV512EN:1; + vuint32_t DIV32EN:1; + vuint32_t APIVAL:10; + } B; + } RTCC; /* RTC Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t RTCF:1; + vuint32_t:15; + vuint32_t APIF:1; + vuint32_t:2; + vuint32_t ROVRF:1; + vuint32_t:10; + } B; + } RTCS; /* RTC Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + }; /* end of RTC_tag */ +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; + + union { /* MCU ID Register 1 */ + vuint32_t R; + struct { + vuint32_t PARTNUM:16; + vuint32_t CSP:1; + vuint32_t PKG:5; + vuint32_t:2; + vuint32_t MAJORMASK:4; + vuint32_t MINORMASK:4; + } B; + } MIDR; + + union { /* MCU ID Register 2 */ + vuint32_t R; + struct { + vuint32_t SF:1; + vuint32_t FLASH_SIZE_1:4; + vuint32_t FLASH_SIZE_2:4; + vuint32_t:7; + vuint32_t PARTNUM:8; + vuint32_t:3; + vuint32_t EE:1; + vuint32_t:3; + vuint32_t FR:1; + } B; + } MIDR2; + + int32_t SIU_reserved1[2]; + + union { /* Interrupt Status Flag Register */ + vuint32_t R; + struct { + vuint32_t EIF31:1; + vuint32_t EIF30:1; + vuint32_t EIF29:1; + vuint32_t EIF28:1; + vuint32_t EIF27:1; + vuint32_t EIF26:1; + vuint32_t EIF25:1; + vuint32_t EIF24:1; + vuint32_t EIF23:1; + vuint32_t EIF22:1; + vuint32_t EIF21:1; + vuint32_t EIF20:1; + vuint32_t EIF19:1; + vuint32_t EIF18:1; + vuint32_t EIF17:1; + vuint32_t EIF16:1; + vuint32_t EIF15:1; + vuint32_t EIF14:1; + vuint32_t EIF13:1; + vuint32_t EIF12:1; + vuint32_t EIF11:1; + vuint32_t EIF10:1; + vuint32_t EIF9:1; + vuint32_t EIF8:1; + vuint32_t EIF7:1; + vuint32_t EIF6:1; + vuint32_t EIF5:1; + vuint32_t EIF4:1; + vuint32_t EIF3:1; + vuint32_t EIF2:1; + vuint32_t EIF1:1; + vuint32_t EIF0:1; + } B; + } ISR; + + union { /* Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t EIRE31:1; + vuint32_t EIRE30:1; + vuint32_t EIRE29:1; + vuint32_t EIRE28:1; + vuint32_t EIRE27:1; + vuint32_t EIRE26:1; + vuint32_t EIRE25:1; + vuint32_t EIRE24:1; + vuint32_t EIRE23:1; + vuint32_t EIRE22:1; + vuint32_t EIRE21:1; + vuint32_t EIRE20:1; + vuint32_t EIRE19:1; + vuint32_t EIRE18:1; + vuint32_t EIRE17:1; + vuint32_t EIRE16:1; + vuint32_t EIRE15:1; + vuint32_t EIRE14:1; + vuint32_t EIRE13:1; + vuint32_t EIRE12:1; + vuint32_t EIRE11:1; + vuint32_t EIRE10:1; + vuint32_t EIRE9:1; + vuint32_t EIRE8:1; + vuint32_t EIRE7:1; + vuint32_t EIRE6:1; + vuint32_t EIRE5:1; + vuint32_t EIRE4:1; + vuint32_t EIRE3:1; + vuint32_t EIRE2:1; + vuint32_t EIRE1:1; + vuint32_t EIRE0:1; + } B; + } IRER; + + int32_t SIU_reserved2[3]; + + union { /* Interrupt Rising-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t IREE31:1; + vuint32_t IREE30:1; + vuint32_t IREE29:1; + vuint32_t IREE28:1; + vuint32_t IREE27:1; + vuint32_t IREE26:1; + vuint32_t IREE25:1; + vuint32_t IREE24:1; + vuint32_t IREE23:1; + vuint32_t IREE22:1; + vuint32_t IREE21:1; + vuint32_t IREE20:1; + vuint32_t IREE19:1; + vuint32_t IREE18:1; + vuint32_t IREE17:1; + vuint32_t IREE16:1; + vuint32_t IREE15:1; + vuint32_t IREE14:1; + vuint32_t IREE13:1; + vuint32_t IREE12:1; + vuint32_t IREE11:1; + vuint32_t IREE10:1; + vuint32_t IREE9:1; + vuint32_t IREE8:1; + vuint32_t IREE7:1; + vuint32_t IREE6:1; + vuint32_t IREE5:1; + vuint32_t IREE4:1; + vuint32_t IREE3:1; + vuint32_t IREE2:1; + vuint32_t IREE1:1; + vuint32_t IREE0:1; + } B; + } IREER; + + union { /* Interrupt Falling-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t IFEE31:1; + vuint32_t IFEE30:1; + vuint32_t IFEE29:1; + vuint32_t IFEE28:1; + vuint32_t IFEE27:1; + vuint32_t IFEE26:1; + vuint32_t IFEE25:1; + vuint32_t IFEE24:1; + vuint32_t IFEE23:1; + vuint32_t IFEE22:1; + vuint32_t IFEE21:1; + vuint32_t IFEE20:1; + vuint32_t IFEE19:1; + vuint32_t IFEE18:1; + vuint32_t IFEE17:1; + vuint32_t IFEE16:1; + vuint32_t IFEE15:1; + vuint32_t IFEE14:1; + vuint32_t IFEE13:1; + vuint32_t IFEE12:1; + vuint32_t IFEE11:1; + vuint32_t IFEE10:1; + vuint32_t IFEE9:1; + vuint32_t IFEE8:1; + vuint32_t IFEE7:1; + vuint32_t IFEE6:1; + vuint32_t IFEE5:1; + vuint32_t IFEE4:1; + vuint32_t IFEE3:1; + vuint32_t IFEE2:1; + vuint32_t IFEE1:1; + vuint32_t IFEE0:1; + } B; + } IFEER; + + union { /* Interrupt Filter Enable Register */ + vuint32_t R; + struct { + vuint32_t IFE31:1; + vuint32_t IFE30:1; + vuint32_t IFE29:1; + vuint32_t IFE28:1; + vuint32_t IFE27:1; + vuint32_t IFE26:1; + vuint32_t IFE25:1; + vuint32_t IFE24:1; + vuint32_t IFE23:1; + vuint32_t IFE22:1; + vuint32_t IFE21:1; + vuint32_t IFE20:1; + vuint32_t IFE19:1; + vuint32_t IFE18:1; + vuint32_t IFE17:1; + vuint32_t IFE16:1; + vuint32_t IFE15:1; + vuint32_t IFE14:1; + vuint32_t IFE13:1; + vuint32_t IFE12:1; + vuint32_t IFE11:1; + vuint32_t IFE10:1; + vuint32_t IFE9:1; + vuint32_t IFE8:1; + vuint32_t IFE7:1; + vuint32_t IFE6:1; + vuint32_t IFE5:1; + vuint32_t IFE4:1; + vuint32_t IFE3:1; + vuint32_t IFE2:1; + vuint32_t IFE1:1; + vuint32_t IFE0:1; + } B; + } IFER; + + int32_t SIU_reserved3[3]; + + union { /* Pad Configuration Registers */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SME:1; + vuint16_t APC:1; + vuint16_t:1; + vuint16_t PA:2; + vuint16_t OBE:1; + vuint16_t IBE:1; + vuint16_t DCS:2; + vuint16_t ODE:1; + vuint16_t HYS:1; + vuint16_t SRC:2; + vuint16_t WPE:1; + vuint16_t WPS:1; + } B; + } PCR[512]; + + int32_t SIU_reserved4[48]; /* {0x500-0x440}/0x4 */ + + union { /* Pad Selection for Multiplexed Input Register */ + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PADSEL:4; + } B; + } PSMI[256]; + + union { /* GPIO Pin Data Output Registers */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDO:1; + } B; + } GPDO[512]; + + union { /* GPIO Pin Data Input Registers */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDI:1; + } B; + } GPDI[512]; + + int32_t SIU_reserved5[128]; /* {0xC00-0xA00}/0x4 */ + + union { /* Parallel GPIO Pin Data Output Register */ + vuint32_t R; + struct { + vuint32_t PPD0:32; + } B; + } PGPDO[16]; + + union { /* Parallel GPIO Pin Data Input Register */ + vuint32_t R; + struct { + vuint32_t PPDI:32; + } B; + } PGPDI[16]; + + union { /* Masked Parallel GPIO Pin Data Out Register */ + vuint32_t R; + struct { + vuint32_t MASK:16; + vuint32_t MPPDO:16; + } B; + } MPGPDO[32]; + + int32_t SIU_reserved6[192]; /* {0x1000-0x0D00}/0x4 */ + + union { /* Interrupt Filter Maximum Counter Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t MAXCNT:4; + } B; + } IFMC[32]; + + union { /* Interrupt Filter Clock Prescaler Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFCP:4; + } B; + } IFCPR; + + }; /* end of SIU_tag */ +/****************************************************************************/ +/* MODULE : SSCM */ +/****************************************************************************/ + struct SSCM_tag { + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t NXEN:1; + vuint16_t PUB:1; + vuint16_t SEC:1; + vuint16_t:1; + vuint16_t BMODE:3; + vuint16_t:1; + vuint16_t ABD:1; + vuint16_t:3; + } B; + } STATUS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t SRAMSIZE:5; + vuint16_t IFLASHSIZE:5; + vuint16_t IVLD:1; + vuint16_t DFLASHSIZE:4; + vuint16_t DVLD:1; + } B; + } MEMCONFIG; /* System Memory Configuration Register */ + + int16_t SSCM_reserved; + + union { + vuint16_t R; + struct { + vuint16_t:14; + vuint16_t PAE:1; + vuint16_t RAE:1; + } B; + } ERROR; /* Error Configuration Register */ + + union { + vuint16_t R; + struct { + vuint16_t:13; + vuint16_t DEBUG_MODE:3; + } B; + } DEBUGPORT; /* Debug Status Port Register */ + + int16_t SSCM_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t PWD_HI:32; + } B; + } PWCMPH; /* Password Comparison Register High Word */ + + union { + vuint32_t R; + struct { + vuint32_t PWD_LO:32; + } B; + } PWCMPL; /* Password Comparison Register Low Word */ + + }; /* end of SSCM_tag */ +/****************************************************************************/ +/* MODULE : STM */ +/****************************************************************************/ + struct STM_tag { + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR0; /* STM Control Register */ + + union { + vuint32_t R; + } CNT0; /* STM Count Register */ + + int32_t STM_reserved[2]; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register 0 */ + + union { + vuint32_t R; + } CMP0; /* STM Channel Compare Register 0 */ + + int32_t STM_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register 1 */ + + union { + vuint32_t R; + } CMP1; /* STM Channel Compare Register 1 */ + + int32_t STM_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register 2 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register 2 */ + + union { + vuint32_t R; + } CMP2; /* STM Channel Compare Register 2 */ + + int32_t STM_reserved3; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register 3 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register 3 */ + + union { + vuint32_t R; + } CMP3; /* STM Channel Compare Register 3 */ + + }; /* end of STM_tag */ +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:15; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } CR; /* SWT Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* SWT Interrupt Register */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* SWT Time-Out Register */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + } B; + } WN; /* SWT Window Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* SWT Service Register */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* SWT Counter Output Register */ + + }; /* end of SWT_tag */ +/****************************************************************************/ +/* MODULE : WKUP */ +/****************************************************************************/ + struct WKUP_tag { + union { + vuint32_t R; + struct { + vuint32_t NIF0:1; + vuint32_t NOVF0:1; + vuint32_t:6; + vuint32_t NIF1:1; + vuint32_t NOVF1:1; + vuint32_t:6; + vuint32_t NIF2:1; + vuint32_t NOVF2:1; + vuint32_t:6; + vuint32_t NIF3:1; + vuint32_t NOVF3:1; + vuint32_t:6; + } B; + } NSR; /* NMI Status Register */ + + int32_t WKUP_reserved; + + union { + vuint32_t R; + struct { + vuint32_t NLOCK0:1; + vuint32_t NDSS0:2; + vuint32_t NWRE0:1; + vuint32_t:1; + vuint32_t NREE0:1; + vuint32_t NFEE0:1; + vuint32_t NFE0:1; + vuint32_t NLOCK1:1; + vuint32_t NDSS1:2; + vuint32_t NWRE1:1; + vuint32_t:1; + vuint32_t NREE1:1; + vuint32_t NFEE1:1; + vuint32_t NFE1:1; + vuint32_t NLOCK2:1; + vuint32_t NDSS2:2; + vuint32_t NWRE2:1; + vuint32_t:1; + vuint32_t NREE2:1; + vuint32_t NFEE2:1; + vuint32_t NFE2:1; + vuint32_t NLOCK3:1; + vuint32_t NDSS3:2; + vuint32_t NWRE3:1; + vuint32_t:1; + vuint32_t NREE3:1; + vuint32_t NFEE3:1; + vuint32_t NFE3:1; + } B; + } NCR; /* NMI Configuration Register */ + + int32_t WKUP_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t EIF:32; + } B; + } WISR; /* Wakeup/Interrupt Status Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t EIRE:32; + } B; + } IRER; /* Interrupt Request Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t WRE:32; + } B; + } WRER; /* Wakeup Request Enable Register */ + + int32_t WKUP_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t IREE:32; + } B; + } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t IFEE:32; + } B; + } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t IFE:32; + } B; + } WIFER; /* Wakeup/Interrupt Filter Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t IPUE:32; + } B; + } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */ + + }; /* end of WKUP_tag */ +/****************************************************************************/ +/* MODULE : LINFLEX */ +/****************************************************************************/ + + struct LINFLEX_tag { + + int16_t LINFLEX_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t CCD:1; + vuint16_t CFD:1; + vuint16_t LASE:1; + vuint16_t AWUM:1; // LCH vuint16_t AUTOWU:1; + vuint16_t MBL:4; + vuint16_t BF:1; + vuint16_t SFTM:1; + vuint16_t LBKM:1; + vuint16_t MME:1; + vuint16_t SBDT:1; // LCH vuint16_t SSBL:1; + vuint16_t RBLM:1; + vuint16_t SLEEP:1; + vuint16_t INIT:1; + } B; + } LINCR1; /* LINFLEX LIN Control Register 1 */ + + int16_t LINFLEX_reserved2; + + union { + vuint16_t R; + struct { + vuint16_t SZIE:1; + vuint16_t OCIE:1; + vuint16_t BEIE:1; + vuint16_t CEIE:1; + vuint16_t HEIE:1; + vuint16_t:2; + vuint16_t FEIE:1; + vuint16_t BOIE:1; + vuint16_t LSIE:1; + vuint16_t WUIE:1; + vuint16_t DBFIE:1; + vuint16_t DBEIE:1; + vuint16_t DRIE:1; + vuint16_t DTIE:1; + vuint16_t HRIE:1; + } B; + } LINIER; /* LINFLEX LIN Interrupt Enable Register */ + + int16_t LINFLEX_reserved3; + + union { + vuint16_t R; + struct { + vuint16_t LINS:4; + vuint16_t:2; + vuint16_t RMB:1; + vuint16_t:1; + vuint16_t RBSY:1; // LCH vuint16_t RXBUSY:1; + vuint16_t RPS:1; // LCH vuint16_t RDI:1; + vuint16_t WUF:1; + vuint16_t DBFF:1; + vuint16_t DBEF:1; + vuint16_t DRF:1; + vuint16_t DTF:1; + vuint16_t HRF:1; + } B; + } LINSR; /* LINFLEX LIN Status Register */ + + int16_t LINFLEX_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t SZF:1; + vuint16_t OCF:1; + vuint16_t BEF:1; + vuint16_t CEF:1; + vuint16_t SFEF:1; + vuint16_t BDEF:1; + vuint16_t IDPEF:1; + vuint16_t FEF:1; + vuint16_t BOF:1; + vuint16_t:6; + vuint16_t NF:1; + } B; + } LINESR; /* LINFLEX LIN Error Status Register */ + + int16_t LINFLEX_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t TDFL:2; + vuint16_t:1; + vuint16_t RDFL:2; + vuint16_t:4; + vuint16_t RXEN:1; + vuint16_t TXEN:1; + vuint16_t OP:1; //LCH vuint16_t PARITYODD:1; + vuint16_t PCE:1; + vuint16_t WL:1; + vuint16_t UART:1; + } B; + } UARTCR; /* LINFLEX UART Mode Control Register */ + + int16_t LINFLEX_reserved6; + + union { + vuint16_t R; + struct { + vuint16_t SZF:1; + vuint16_t OCF:1; + vuint16_t PE:4; + vuint16_t RMB:1; + vuint16_t FEF:1; + vuint16_t BOF:1; + vuint16_t RPS:1; // LCH vuint16_t RDI:1; + vuint16_t WUF:1; + vuint16_t:2; + vuint16_t DRF:1; + vuint16_t DTF:1; + vuint16_t NF:1; + } B; + } UARTSR; /* LINFLEX UART Mode Status Register */ + + int16_t LINFLEX_reserved7; + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t LTOM:1; //LCH vuint16_t MODE:1; + vuint16_t IOT:1; + vuint16_t TOCE:1; + vuint16_t CNT:8; + } B; + } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */ + + int16_t LINFLEX_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t OC2:8; + vuint16_t OC1:8; + } B; + } LINOCR; /* LINFLEX LIN Output Compare Register */ + + int16_t LINFLEX_reserved9; + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t RTO:4; // LCH vuint16_t RTC:4; + vuint16_t:1; + vuint16_t HTO:7; // LCH vuint16_t HTC:7; + } B; + } LINTOCR; /* LINFLEX LIN Output Compare Register */ + + int16_t LINFLEX_reserved10; + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t DIV_F:4; // LCH vuint16_t FBR:4; + } B; + } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */ + + int16_t LINFLEX_reserved11; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DIV_M:13; // LCH vuint16_t IBR:13; + } B; + } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */ + + int16_t LINFLEX_reserved12; + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t CF:8; + } B; + } LINCFR; /* LINFLEX LIN Checksum Field Register */ + + int16_t LINFLEX_reserved13; + + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t IOBE:1; + vuint16_t IOPE:1; + vuint16_t WURQ:1; + vuint16_t DDRQ:1; + vuint16_t DTRQ:1; + vuint16_t ABRQ:1; + vuint16_t HTRQ:1; + vuint16_t:8; + } B; + } LINCR2; /* LINFLEX LIN Control Register 2 */ + + int16_t LINFLEX_reserved14; + + union { + vuint16_t R; + struct { + vuint16_t DFL:6; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; // LCH vuint16_t:1; + vuint16_t ID:6; + } B; + } BIDR; /* LINFLEX Buffer Identifier Register */ + + union { + vuint32_t R; + struct { + vuint32_t DATA3:8; + vuint32_t DATA2:8; + vuint32_t DATA1:8; + vuint32_t DATA0:8; + } B; + } BDRL; /* LINFLEX Buffer Data Register Least Significant */ + + union { + vuint32_t R; + struct { + vuint32_t DATA7:8; + vuint32_t DATA6:8; + vuint32_t DATA5:8; + vuint32_t DATA4:8; + } B; + } BDRM; /* LINFLEX Buffer Data Register Most Significant */ + + int16_t LINFLEX_reserved15; + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t FACT:8; + } B; + } IFER; /* LINFLEX Identifier Filter Enable Register */ + + int16_t LINFLEX_reserved16; + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t IFMI:4; + } B; + } IFMI; /* LINFLEX Identifier Filter Match Index Register */ + + int16_t LINFLEX_reserved17; + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t IFM:4; + } B; + } IFMR; /* LINFLEX Identifier Filter Mode Register */ + + int16_t LINFLEX_reserved18; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR0; /* LINFLEX Identifier Filter Control Register 0 */ + + int16_t LINFLEX_reserved19; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR1; /* LINFLEX Identifier Filter Control Register 1 */ + + int16_t LINFLEX_reserved20; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR2; /* LINFLEX Identifier Filter Control Register 2 */ + + int16_t LINFLEX_reserved21; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR3; /* LINFLEX Identifier Filter Control Register 3 */ + + int16_t LINFLEX_reserved22; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR4; /* LINFLEX Identifier Filter Control Register 4 */ + + int16_t LINFLEX_reserved23; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR5; /* LINFLEX Identifier Filter Control Register 5 */ + + int16_t LINFLEX_reserved24; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR6; /* LINFLEX Identifier Filter Control Register 6 */ + + int16_t LINFLEX_reserved25; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t DFL:3; + vuint16_t DIR:1; + vuint16_t CCS:1; + vuint16_t:2; + vuint16_t ID:6; + } B; + } IFCR7; /* LINFLEX Identifier Filter Control Register 7 */ + + }; /* end of LINFLEX_tag */ +/****************************************************************************/ +/* MODULE : ME */ +/****************************************************************************/ + struct ME_tag { + + union { + vuint32_t R; + struct { + vuint32_t S_CURRENTMODE:4; + vuint32_t S_MTRANS:1; + vuint32_t S_DC:1; + vuint32_t:2; + vuint32_t S_PDO:1; + vuint32_t:2; + vuint32_t S_MVR:1; + vuint32_t S_DFLA:2; + vuint32_t S_CFLA:2; + vuint32_t:8; + vuint32_t S_PLL1:1; + vuint32_t S_PLL0:1; + vuint32_t S_OSC:1; + vuint32_t S_RC:1; + vuint32_t S_SYSCLK:4; + } B; + } GS; /* Global Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t TARGET_MODE:4; + vuint32_t:12; + vuint32_t KEY:16; + } B; + } MCTL; /* Mode Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STANDBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } MER; /* Mode Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t I_CONF:1; + vuint32_t I_MODE:1; + vuint32_t I_SAFE:1; + vuint32_t I_MTC:1; + } B; + } IS; /* Interrupt Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t M_CONF:1; + vuint32_t M_MODE:1; + vuint32_t M_SAFE:1; + vuint32_t M_TC:1; + } B; + } IM; /* Interrupt Mask Register */ + + union { + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t S_MTI:1; + vuint32_t S_MRI:1; + vuint32_t S_DMA:1; + vuint32_t S_NMA:1; + vuint32_t S_SEA:1; + } B; + } IMTS; /* Invalid Mode Transition Status Register */ + + int32_t ME_reserved0[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } RESET; /* Reset Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } TEST; /* Test Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } SAFE; /* Safe Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } DRUN; /* DRUN Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } RUN[4]; /* RUN 0->4 Mode Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } HALT0; /* HALT0 Mode Configuration Register */ + + int32_t ME_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } STOP0; /* STOP0 Mode Configuration Register */ + + int32_t ME_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; + vuint32_t:2; + vuint32_t MVRON:1; + vuint32_t DFLAON:2; + vuint32_t CFLAON:2; + vuint32_t:8; + vuint32_t PLL2ON:1; + vuint32_t PLL1ON:1; + vuint32_t XOSC0ON:1; + vuint32_t IRCON:1; + vuint32_t SYSCLK:4; + } B; + } STANDBY0; /* STANDBY0 Mode Configuration Register */ + + int32_t ME_reserved3[2]; + + union { + vuint32_t R; + struct { + vuint32_t PERIPH:32; + } B; + } PS[4]; /* Peripheral Status 0->4 Register */ + + int32_t ME_reserved4[4]; + + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RESET:1; + } B; + } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */ + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STANDBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t:8; + } B; + } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t DBG_F:1; + vuint8_t LP_CFG:3; + vuint8_t RUN_CFG:3; + } B; + } PCTL[144]; /* Peripheral Control 0->143 Register */ + + }; /* end of ME_tag */ +/****************************************************************************/ +/* MODULE : CGM */ +/****************************************************************************/ + struct CGM_tag { + + /* The CGM provides a unified register interface, enabling access to + all clock sources: + + Clock Type | Starting Address Map | Associated Clock Sources + ------------------------------------------------------------ + System | C3FE0000 | OSC_CTL + " | - | Reserved + " | C3FE0040 | LPOSC_CTL + " | C3FE0060 | RC_CTL + " | C3FE0080 | LPRC_CTL + " | C3FE00A0 | FMPLL_0 + " | C3FE00C0 | FMPLL_1 + " | - | Reserved + MISC | C3FE0100 | CMU_0 & CMU_1 + + */ + + /************************************/ + /* OSC_CTL @ CGM base address + 0x0000 */ + /************************************/ + union { + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t:7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t:2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t:5; + vuint32_t S_OSC:1; + vuint32_t OSCON:1; + } B; + } OSC_CTL; /* Main OSC Control Register */ + + /************************************/ + /* LPOSC_CTL @ CGM base address + 0x0040 */ + /************************************/ + int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */ + /*int32_t $RESERVED[15]; */ + + union { + vuint32_t R; + struct { + vuint32_t OSCBYP:1; + vuint32_t:7; + vuint32_t EOCV:8; + vuint32_t M_OSC:1; + vuint32_t:2; + vuint32_t OSCDIV:5; + vuint32_t I_OSC:1; + vuint32_t:5; + vuint32_t S_OSC:1; + vuint32_t OSCON:1; + } B; + } LPOSC_CTL; /* Low Power OSC Control Register */ + + /************************************/ + /* RC_CTL @ CGM base address + 0x0060 */ + /************************************/ + int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */ + + union { + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t RCTRIM:6; + vuint32_t:3; + vuint32_t RCDIV:5; + vuint32_t:2; + vuint32_t S_RC_STDBY:1; + vuint32_t:5; + } B; + } RC_CTL; /* RC OSC Control Register */ + + /*************************************/ + /* LPRC_CTL @ CGM base address + 0x0080 */ + /*************************************/ + int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */ + + union { + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t LRCTRIM:5; + vuint32_t:3; + vuint32_t LPRCDIV:5; + vuint32_t:3; + vuint32_t S_LPRC:1; + vuint32_t:3; + vuint32_t LPRCON_STDBY:1; + } B; + } LPRC_CTL; /* Low Power RC OSC Control Register */ + + /************************************/ + /* FMPLL_0 @ CGM base address + 0x00A0 */ + /* FMPLL_1 @ CGM base address + 0x0100 */ + /************************************/ + int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t IDF:4; + vuint32_t ODF:2; + vuint32_t:1; + vuint32_t NDIV:7; + vuint32_t:7; + vuint32_t EN_PLL_SW:1; + vuint32_t MODE:1; + vuint32_t UNLOCK_ONCE:1; + vuint32_t:1; + vuint32_t I_LOCK:1; + vuint32_t S_LOCK:1; + vuint32_t PLL_FAIL_MASK:1; + vuint32_t PLL_FAIL_FLAG:1; + vuint32_t:1; + } B; + } CR; /* FMPLL Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t STRB_BYPASS:1; + vuint32_t:1; + vuint32_t SPRD_SEL:1; + vuint32_t MOD_PERIOD:13; + vuint32_t FM_EN:1; + vuint32_t INC_STEP:15; + } B; + } MR; /* FMPLL Modulation Register */ + + int32_t CGM_reserved4[6]; /* (0x0C0 - 0x0A8)/4 = 0x06 */ + /* (0x0E0 - 0x0C8)/4 = 0x06 */ + + } FMPLL[2]; + + /************************************/ + /* CMU @ CGM base address + 0x0100 */ + /************************************/ + int32_t CGM_reserved5[8]; /* (0x100 - 0x0E0)/4 = 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SFM:1; + vuint32_t:13; + vuint32_t CLKSEL1:2; + vuint32_t:5; + vuint32_t RCDIV:2; + vuint32_t CME_A:1; + } B; + } CMU_0_CSR; /* Control Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t FD:20; + } B; + } CMU_0_FDR; /* Frequency Display Register */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t HFREF_A:12; + } B; + } CMU_0_HFREFR_A; /* High Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t LFREF_A:12; + } B; + } CMU_0_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t FLCI_0:1; + vuint32_t FHHI_0:1; + vuint32_t FLLI_0:1; + vuint32_t OLRI:1; + } B; + } CMU_0_ISR; /* Interrupt Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } CMU_0_IMR; /* Interrupt Mask Register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t MD:20; + } B; + } CMU_0_MDR; /* Measurement Duration Register */ + + int32_t CGM_reserved5A; /* (0x020 - 0x01C)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SFM:1; + vuint32_t:13; + vuint32_t CLKSEL1:2; + vuint32_t:5; + vuint32_t RCDIV:2; + vuint32_t CME_A:1; + } B; + } CMU_1_CSR; /* Control Status Register */ + + int32_t CGM_reserved6; /* (0x028 - 0x024)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t HFREF_A:12; + } B; + } CMU_1_HFREFR_A; /* High Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t LFREF_A:12; + } B; + } CMU_1_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t FLCI_1:1; + vuint32_t FHHI_1:1; + vuint32_t FLLI_1:1; + vuint32_t:1; + } B; + } CMU_1_ISR; /* Interrupt Status Register */ + + /************************************/ + /* CGM General Registers @ CGM base address + 0x0370 */ + /************************************/ + int32_t CGM_reserved7[143]; /* (0x370 - 0x134)/4 = 0x8F */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t EN:1; + } B; + } OCEN; /* Output Clock Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t SELDIV:2; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } OCDSSC; /* Output Clock Division Select Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELSTAT:4; + vuint32_t:24; + } B; + } SCSS; /* System Clock Select Status */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } SCDC; /* GSystem Clock Divider Configuration 0->4 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC0SC; /* Aux Clock 0 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC0DC; /* Aux Clock 0 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC1SC; /* Aux Clock 1 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC1DC; /* Aux Clock 1 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC2SC; /* Aux Clock 2 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC2DC; /* Aux Clock 2 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC3SC; /* Aux Clock 3 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC3DC; /* Aux Clock 3 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC4SC; /* Aux Clock 4 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC4DC; /* Aux Clock 4 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC5SC; /* Aux Clock 5 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC5DC; /* Aux Clock 5 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC6SC; /* Aux Clock 6 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC6DC; /* Aux Clock 6 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC7SC; /* Aux Clock 7 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC7DC; /* Aux Clock 7 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC8SC; /* Aux Clock 8 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC8DC; /* Aux Clock 8 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC9SC; /* Aux Clock 9 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC9DC; /* Aux Clock 9 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC10SC; /* Aux Clock 10 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC10DC; /* Aux Clock 10 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC11SC; /* Aux Clock 11 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC11DC; /* Aux Clock 11 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC12SC; /* Aux Clock 12 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC12DC; /* Aux Clock 12 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC13SC; /* Aux Clock 13 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC13DC; /* Aux Clock 13 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC14SC; /* Aux Clock 14 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC14DC; /* Aux Clock 14 Divider Configuration 0->3 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t SELCTL:4; + vuint32_t:24; + } B; + } AC15SC; /* Aux Clock 15 Select Control */ + + union { + vuint32_t R; + struct { + vuint32_t DE0:1; + vuint32_t:3; + vuint32_t DIV0:4; + vuint32_t DE1:1; + vuint32_t:3; + vuint32_t DIV1:4; + vuint32_t DE2:1; + vuint32_t:3; + vuint32_t DIV2:4; + vuint32_t DE3:1; + vuint32_t:3; + vuint32_t DIV3:4; + } B; + } AC15DC; /* Aux Clock 15 Divider Configuration 0->3 */ + + }; /* end of CGM_tag */ +/****************************************************************************/ +/* MODULE : RGM */ +/****************************************************************************/ + struct RGM_tag { + + union { + vuint16_t R; + struct { + vuint16_t F_EXR:1; + vuint16_t:3; + vuint16_t F_CMU1_FHL:1; + vuint16_t:1; + vuint16_t F_PLL1:1; + vuint16_t F_FLASH:1; + vuint16_t F_LVD45:1; + vuint16_t F_CMU0_FHL:1; + vuint16_t F_CMU0_OLR:1; + vuint16_t F_PLL0:1; + vuint16_t F_CHKSTOP:1; + vuint16_t F_SOFT:1; + vuint16_t F_CORE:1; + vuint16_t F_JTAG:1; + } B; + } FES; /* Functional Event Status */ + + union { + vuint16_t R; + struct { + vuint16_t POR:1; + vuint16_t:7; + vuint16_t F_COMP:1; + vuint16_t F_LVD27_IO:1; + vuint16_t F_LVD27_FLASH:1; + vuint16_t F_LVD27_VREG:1; + vuint16_t F_LVD27:1; + vuint16_t F_SWT:1; + vuint16_t F_LVD12_PD1:1; + vuint16_t F_LVD12_PD0:1; + } B; + } DES; /* Destructive Event Status */ + + union { + vuint16_t R; + struct { + vuint16_t D_EXR:1; + vuint16_t:3; + vuint16_t D_CMU1_FHL:1; + vuint16_t:1; + vuint16_t D_PLL1:1; + vuint16_t D_FLASH:1; + vuint16_t D_LVD45:1; + vuint16_t D_CMU0_FHL:1; + vuint16_t D_CMU0_OLR:1; + vuint16_t D_PLL0:1; + vuint16_t D_CHKSTOP:1; + vuint16_t D_SOFT:1; + vuint16_t D_CORE:1; + vuint16_t D_JTAG:1; + } B; + } FERD; /* Functional Event Reset Disable */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t D_COMP:1; + vuint16_t D_LVD27_IO:1; + vuint16_t D_LVD27_FLASH:1; + vuint16_t D_LVD27_VREG:1; + vuint16_t D_LVD27:1; + vuint16_t D_SWT:1; + vuint16_t D_LVD12_PD1:1; + vuint16_t D_LVD12_PD0:1; + } B; + } DERD; /* Destructive Event Reset Disable */ + + int16_t RGM_reserved0[4]; + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t AR_CMU1_FHL:1; + vuint16_t:1; + vuint16_t AR_PLL1:1; + vuint16_t AR_FLASH:1; + vuint16_t AR_LVD45:1; + vuint16_t AR_CMU0_FHL:1; + vuint16_t AR_CMU0_OLR:1; + vuint16_t AR_PLL0:1; + vuint16_t AR_CHKSTOP:1; + vuint16_t AR_SOFT:1; + vuint16_t AR_CORE:1; + vuint16_t AR_JTAG:1; + } B; + } FEAR; /* Functional Event Alternate Request */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t AR_COMP:1; + vuint16_t AR_LVD27_IO:1; + vuint16_t AR_LVD27_FLASH:1; + vuint16_t AR_LVD27_VREG:1; + vuint16_t AR_LVD27:1; + vuint16_t AR_SWT:1; + vuint16_t AR_LVD12_PD1:1; + vuint16_t AR_LVD12_PD0:1; + } B; + } DEAR; /* Destructive Event Alternate Request */ + + int16_t RGM_reserved1[2]; + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t SS_CMU1_FHL:1; + vuint16_t:1; + vuint16_t SS_PLL1:1; + vuint16_t SS_FLASH:1; + vuint16_t SS_LVD45:1; + vuint16_t SS_CMU0_FHL:1; + vuint16_t SS_CMU0_OLR:1; + vuint16_t SS_PLL0:1; + vuint16_t SS_CHKSTOP:1; + vuint16_t SS_SOFT:1; + vuint16_t SS_CORE:1; + vuint16_t SS_JTAG:1; + } B; + } FESS; /* Functional Event Short Sequence */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t BOOT:1; + vuint16_t:4; + vuint16_t DRUND_FLA:1; + vuint16_t:1; + vuint16_t DRUNC_FLA:1; + } B; + } STDBY; /* STANDBY reset sequence */ + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t BE_CMU1_FHL:1; + vuint16_t:1; + vuint16_t BE_PLL1:1; + vuint16_t BE_FLASH:1; + vuint16_t BE_LVD45:1; + vuint16_t BE_CMU0_FHL:1; + vuint16_t BE_CMU0_OLR:1; + vuint16_t BE_PLL0:1; + vuint16_t BE_CHKSTOP:1; + vuint16_t BE_SOFT:1; + vuint16_t BE_CORE:1; + vuint16_t BE_JTAG:1; + } B; + } FBRE; /* Functional Bidirectional Reset Enable */ + + }; /* end of RGM_tag */ +/****************************************************************************/ +/* MODULE : PCU */ +/****************************************************************************/ + struct PCU_tag { + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STBY0:1; + vuint32_t:2; + vuint32_t STOP0:1; + vuint32_t:1; + vuint32_t HALT0:1; + vuint32_t RUN3:1; + vuint32_t RUN2:1; + vuint32_t RUN1:1; + vuint32_t RUN0:1; + vuint32_t DRUN:1; + vuint32_t SAFE:1; + vuint32_t TEST:1; + vuint32_t RST:1; + } B; + } PCONF[16]; /* Power domain 0-15 configuration register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t PD15:1; + vuint32_t PD14:1; + vuint32_t PD13:1; + vuint32_t PD12:1; + vuint32_t PD11:1; + vuint32_t PD10:1; + vuint32_t PD9:1; + vuint32_t PD8:1; + vuint32_t PD7:1; + vuint32_t PD6:1; + vuint32_t PD5:1; + vuint32_t PD4:1; + vuint32_t PD3:1; + vuint32_t PD2:1; + vuint32_t PD1:1; + vuint32_t PD0:1; + } B; + } PSTAT; /* Power Domain Status Register */ + + int32_t PCU_reserved0[15]; /* {0x0080-0x0044}/0x4 = 0xF */ + + union { + vuint32_t R; + struct { + vuint32_t:15; + vuint32_t MASK_LVDHV5:1; + } B; + } VCTL; /* Voltage Regulator Control Register */ + + }; /* end of PCU_tag */ +/****************************************************************************/ +/* MODULE : FLEXPWM */ +/****************************************************************************/ + struct FLEXPWM_SUB_tag { + + union { + vuint16_t R; + } CNT; /* Counter Register */ + + union { + vuint16_t R; + } INIT; /* Initial Count Register */ + + union { + vuint16_t R; + struct { + vuint16_t DBGEN:1; + vuint16_t WAITEN:1; + vuint16_t INDEP:1; + vuint16_t PWMA_INIT:1; + vuint16_t PWMB_INIT:1; + vuint16_t PWMX_INIT:1; + vuint16_t INIT_SEL:2; + vuint16_t FRCEN:1; + vuint16_t FORCE:1; + vuint16_t FORCE_SEL:3; + vuint16_t RELOAD_SEL:1; + vuint16_t CLK_SEL:2; + } B; + } CTRL2; /* Control 2 Register */ + + union { + vuint16_t R; + struct { + vuint16_t LDFQ:4; + vuint16_t HALF:1; + vuint16_t FULL:1; + vuint16_t DT:2; + vuint16_t:1; + vuint16_t PRSC:3; + vuint16_t:3; + vuint16_t DBLEN:1; + } B; + } CTRL; /* Control Register */ + + union { + vuint16_t R; + } VAL[6]; /* Value Register 0->5 */ + + union { + vuint16_t R; + struct { + vuint16_t FRACAEN:1; + vuint16_t:10; + vuint16_t FRACADLY:5; + } B; + } FRACA; /* Fractional Delay Register A */ + + union { + vuint16_t R; + struct { + vuint16_t FRACBEN:1; + vuint16_t:10; + vuint16_t FRACBDLY:5; + } B; + } FRACB; /* Fractional Delay Register B */ + + union { + vuint16_t R; + struct { + vuint16_t PWMA_IN:1; + vuint16_t PWMB_IN:1; + vuint16_t PWMX_IN:1; + vuint16_t:2; + vuint16_t POLA:1; + vuint16_t POLB:1; + vuint16_t POLX:1; + vuint16_t:2; + vuint16_t PWMAFS:2; + vuint16_t PWMBFS:2; + vuint16_t PWMXFS:2; + } B; + } OCTRL; /* Output Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t RUF:1; + vuint16_t REF:1; + vuint16_t RF:1; + vuint16_t CFA1:1; + vuint16_t CFA0:1; + vuint16_t CFB1:1; + vuint16_t CFB0:1; + vuint16_t CFX1:1; + vuint16_t CFX0:1; + vuint16_t CMPF:6; + } B; + } STS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t REIE:1; + vuint16_t RIE:1; + vuint16_t:4; + vuint16_t CX1IE:1; + vuint16_t CX0IE:1; + vuint16_t CMPIE:6; + } B; + } INTEN; /* Interrupt Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t VALDE:1; + vuint16_t FAND:1; + vuint16_t CAPTDE:2; + vuint16_t CA1DE:1; + vuint16_t CA0DE:1; + vuint16_t CB1DE:1; + vuint16_t CB0DE:1; + vuint16_t CX1DE:1; + vuint16_t CX0DE:1; + } B; + } DMAEN; /* DMA Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t:10; + vuint16_t OUT_TRIG_EN:6; + } B; + } TCTRL; /* Output Trigger Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t DISX:4; + vuint16_t DISB:4; + vuint16_t DISA:4; + } B; + } DISMAP; /* Fault Disable Mapping Register */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t DTCNT0:11; + } B; + } DTCNT0; /* Deadtime Count Register 0 */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t DTCNT1:11; + } B; + } DTCNT1; /* Deadtime Count Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CA1CNT:3; + vuint16_t CA0CNT:3; + vuint16_t CFAWM:2; + vuint16_t EDGCNTAEN:1; + vuint16_t INPSELA:1; + vuint16_t EDGA1:2; + vuint16_t EDGA0:2; + vuint16_t ONESHOTA:1; + vuint16_t ARMA:1; + } B; + } CAPTCTRLA; /* Capture Control Register A */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTA:8; + vuint16_t EDGCMPA:8; + } B; + } CAPTCOMPA; /* Capture Compare Register A */ + + union { + vuint16_t R; + struct { + vuint16_t CB1CNT:3; + vuint16_t CB0CNT:3; + vuint16_t CFBWM:2; + vuint16_t EDGCNTBEN:1; + vuint16_t INPSELB:1; + vuint16_t EDGB1:2; + vuint16_t EDGB0:2; + vuint16_t ONESHOTB:1; + vuint16_t ARMB:1; + } B; + } CAPTCTRLB; /* Capture Control Register B */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTB:8; + vuint16_t EDGCMPB:8; + } B; + } CAPTCOMPB; /* Capture Compare Register B */ + + union { + vuint16_t R; + struct { + vuint16_t CX1CNT:3; + vuint16_t CX0CNT:3; + vuint16_t CFXWM:2; + vuint16_t EDGCNTX_EN:1; + vuint16_t INP_SELX:1; + vuint16_t EDGX1:2; + vuint16_t EDGX0:2; + vuint16_t ONESHOTX:1; + vuint16_t ARMX:1; + } B; + } CAPTCTRLX; /* Capture Control Register B */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTX:8; + vuint16_t EDGCMPX:8; + } B; + } CAPTCOMPX; /* Capture Compare Register X */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL0:16; + } B; + } CVAL0; /* Capture Value 0 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL0CYC:4; + } B; + } CVAL0C; /* Capture Value 0 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL1:16; + } B; + } CVAL1; /* Capture Value 1 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL1CYC:4; + } B; + } CVAL1C; /* Capture Value 1 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL2:16; + } B; + } CVAL2; /* Capture Value 2 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL2CYC:4; + } B; + } CVAL2C; /* Capture Value 2 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL3:16; + } B; + } CVAL3; /* Capture Value 3 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL3CYC:4; + } B; + } CVAL3C; /* Capture Value 3 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL4:16; + } B; + } CVAL4; /* Capture Value 4 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL4CYC:4; + } B; + } CVAL4C; /* Capture Value 4 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL5:16; + } B; + } CVAL5; /* Capture Value 5 Register */ + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL5CYC:4; + } B; + } CVAL5C; /* Capture Value 5 Cycle Register */ + + uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */ + + }; /* end of FLEXPWM_SUB_tag */ + + struct FLEXPWM_tag { + + /* eg. FLEXPWM.SUB<[x]>.CNT.R {x = 0->3} */ + struct FLEXPWM_SUB_tag SUB[4]; + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t PWMA_EN:4; + vuint16_t PWMB_EN:4; + vuint16_t PWMX_EN:4; + } B; + } OUTEN; /* Output Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t MASKA:4; + vuint16_t MASKB:4; + vuint16_t MASKX:4; + } B; + } MASK; /* Output Mask Register */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t OUTA_3:1; + vuint16_t OUTB_3:1; + vuint16_t OUTA_2:1; + vuint16_t OUTB_2:1; + vuint16_t OUTA_1:1; + vuint16_t OUTB_1:1; + vuint16_t OUTA_0:1; + vuint16_t OUTB_0:1; + } B; + } SWCOUT; /* Software Controlled Output Register */ + + union { + vuint16_t R; + struct { + vuint16_t SELA_3:2; + vuint16_t SELB_3:2; + vuint16_t SELA_2:2; + vuint16_t SELB_2:2; + vuint16_t SELA_1:2; + vuint16_t SELB_1:2; + vuint16_t SELA_0:2; + vuint16_t SELB_0:2; + } B; + } DTSRCSEL; /* Deadtime Source Select Register */ + + union { + vuint16_t R; + struct { + vuint16_t IPOL:4; + vuint16_t RUN:4; + vuint16_t CLDOK:4; + vuint16_t LDOK:4; + } B; + } MCTRL; /* Master Control Register */ + + int16_t FLEXPWM_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t FLVL:4; + vuint16_t FAUTO:4; + vuint16_t FSAFE:4; + vuint16_t FIE:4; + } B; + } FCTRL; /* Fault Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t FTEST:1; + vuint16_t FFPIN:4; + vuint16_t:4; + vuint16_t FFLAG:4; + } B; + } FSTS; /* Fault Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FILT_CNT:3; + vuint16_t FILT_PER:8; + } B; + } FFILT; /* Fault FilterRegister */ + + }; /* end of FLEXPWM_tag */ +/****************************************************************************/ +/* MODULE : ETIMER */ +/****************************************************************************/ + struct ETIMER_CHANNEL_tag { + + union { + vuint16_t R; + struct { + vuint16_t COMP1:16; + } B; + } COMP1; /* Compare Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t COMP2:16; + } B; + } COMP2; /* Compare Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t CAPT1:16; + } B; + } CAPT1; /* Capture Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CAPT2:16; + } B; + } CAPT2; /* Capture Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t LOAD:16; + } B; + } LOAD; /* Load Register */ + + union { + vuint16_t R; + struct { + vuint16_t HOLD:16; + } B; + } HOLD; /* Hold Register */ + + union { + vuint16_t R; + struct { + vuint16_t CNTR:16; + } B; + } CNTR; /* Counter Register */ + + union { + vuint16_t R; + struct { + vuint16_t CNTMODE:3; + vuint16_t PRISRC:5; + vuint16_t ONCE:1; + vuint16_t LENGTH:1; + vuint16_t DIR:1; + vuint16_t SECSRC:5; + } B; + } CTRL; /* Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t OEN:1; + vuint16_t RDNT:1; + vuint16_t INPUT:1; + vuint16_t VAL:1; + vuint16_t FORCE:1; + vuint16_t COFRC:1; + vuint16_t COINIT:2; + vuint16_t SIPS:1; + vuint16_t PIPS:1; + vuint16_t OPS:1; + vuint16_t MSTR:1; + vuint16_t OUTMODE:4; + } B; + } CTRL2; /* Control Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t STPEN:1; + vuint16_t ROC:2; + vuint16_t FMODE:1; + vuint16_t FDIS:4; + vuint16_t C2FCNT:3; + vuint16_t C1FCNT:3; + vuint16_t DBGEN:2; + } B; + } CTRL3; /* Control Register 3 */ + + union { + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t WDF:1; + vuint16_t RCF:1; + vuint16_t ICF2:1; + vuint16_t ICF1:1; + vuint16_t IEHF:1; + vuint16_t IELF:1; + vuint16_t TOF:1; + vuint16_t TCF2:1; + vuint16_t TCF1:1; + vuint16_t TCF:1; + } B; + } STS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t ICF2DE:1; + vuint16_t ICF1DE:1; + vuint16_t CMPLD2DE:1; + vuint16_t CMPLD1DE:1; + vuint16_t:2; + vuint16_t WDFIE:1; + vuint16_t RCFIE:1; + vuint16_t ICF2IE:1; + vuint16_t ICF1IE:1; + vuint16_t IEHFIE:1; + vuint16_t IELFIE:1; + vuint16_t TOFIE:1; + vuint16_t TCF2IE:1; + vuint16_t TCF1IE:1; + vuint16_t TCFIE:1; + } B; + } INTDMA; /* Interrupt and DMA Register */ + + union { + vuint16_t R; + struct { + vuint16_t CMPLD1:16; + } B; + } CMPLD1; /* Compare Load Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CMPLD2:16; + } B; + } CMPLD2; /* Compare Load Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t CLC2:3; + vuint16_t CLC1:3; + vuint16_t CMPMODE:2; + vuint16_t CPT2MODE:2; + vuint16_t CPT1MODE:2; + vuint16_t CFWM:2; + vuint16_t ONESHOT:1; + vuint16_t ARM:1; + } B; + } CCCTRL; /* Compare and Capture Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FILTCNT:3; + vuint16_t FILTPER:8; + } B; + } FILT; /* Input Filter Register */ + + }; /* end of ETIMER_CHANNEL_tag */ + + struct ETIMER_tag { + + struct ETIMER_CHANNEL_tag CHANNEL[8]; + + union { + vuint16_t R; + struct { + vuint16_t WDTOL:16; + } B; + } WDTOL; /* Watchdog Time-out Low Register */ + + union { + vuint16_t R; + struct { + vuint16_t WDTOH:16; + } B; + } WDTOH; /* Watchdog Time-out High Register */ + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t FTEST:1; + vuint16_t FIE:4; + vuint16_t:4; + vuint16_t FLVL:4; + } B; + } FCTRL; /* Fault Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t FFPIN:4; + vuint16_t:4; + vuint16_t FFLAG:4; + } B; + } FSTS; /* Fault Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FFILTCNT:3; + vuint16_t FFILTPER:8; + } B; + } FFILT; /* Fault Filter Register */ + + int16_t ETIMER_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t ENBL:8; + } B; + } ENBL; /* Channel Enable Register */ + + int16_t ETIMER_reserved2; + + union { + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t DREQ:5; + } B; + } DREQ[4]; /* DMA Request 0->3 Select Register */ + + }; /* end of ETIMER_tag */ + +/****************************************************************************/ +/* MODULE : CTUL */ +/****************************************************************************/ + struct CTUL_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t PRESC_CONF:4; + vuint32_t:4; + vuint32_t TRGIEN:1; + vuint32_t TRGI:1; + vuint32_t:2; + vuint32_t CNT3_EN:1; + vuint32_t CNT2_EN:1; + vuint32_t CNT1_EN:1; + vuint32_t CNT0_EN:1; + } B; + } CSR; /* Control Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t:23; + vuint32_t SV:9; + } B; + } SVR[7]; /* Start Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:23; + vuint32_t CV:9; + } B; + } CVR[4]; /* Current Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TM:1; + vuint32_t CNT:2; + vuint32_t DELAY:3; + vuint32_t:4; + vuint32_t CHANNELVALUE:6; + } B; + } EVTCFGR[64]; /* Event Configuration Register */ + + }; /* end of CTUL_tag */ +/****************************************************************************/ +/* MODULE : CTU */ +/****************************************************************************/ + struct CTU_tag { + + union { + vuint32_t R; + struct { + vuint32_t I15_FE:1; + vuint32_t I15_RE:1; + vuint32_t I14_FE:1; + vuint32_t I14_RE:1; + vuint32_t I13_FE:1; + vuint32_t I13_RE:1; + vuint32_t I12_FE:1; + vuint32_t I12_RE:1; + vuint32_t I11_FE:1; + vuint32_t I11_RE:1; + vuint32_t I10_FE:1; + vuint32_t I10_RE:1; + vuint32_t I9_FE:1; + vuint32_t I9_RE:1; + vuint32_t I8_FE:1; + vuint32_t I8_RE:1; + vuint32_t I7_FE:1; + vuint32_t I7_RE:1; + vuint32_t I6_FE:1; + vuint32_t I6_RE:1; + vuint32_t I5_FE:1; + vuint32_t I5_RE:1; + vuint32_t I4_FE:1; + vuint32_t I4_RE:1; + vuint32_t I3_FE:1; + vuint32_t I3_RE:1; + vuint32_t I2_FE:1; + vuint32_t I2_RE:1; + vuint32_t I1_FE:1; + vuint32_t I1_RE:1; + vuint32_t I0_FE:1; + vuint32_t I0_RE:1; + } B; + } TGSISR; /* -Trigger Generator Subunit Input Selection Register */ + + union { + vuint16_t R; + struct { + vuint16_t:7; + vuint16_t ETTM:1; + vuint16_t PRES:2; + vuint16_t MRSSM:5; + vuint16_t TGSM:1; + } B; + } TGSCR; /* Trigger Generator Subunit Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t TCRV:16; + } B; + } TCR[8]; /* Trigger 0->7 Compare Register */ + + union { + vuint16_t R; + struct { + vuint16_t TGSCCV:16; + } B; + } TGSCCR; /* TGS Counter Compare Register */ + + union { + vuint16_t R; + struct { + vuint16_t TGSCRV:16; + } B; + } TGSCRR; /* TGS Counter Reload Register */ + + uint16_t CTU_reserved0; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T3INDEX:5; + vuint32_t:3; + vuint32_t T2INDEX:5; + vuint32_t:3; + vuint32_t T1INDEX:5; + vuint32_t:3; + vuint32_t T0INDEX:5; + } B; + } CLCR1; /* Command List Control Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T7INDEX:5; + vuint32_t:3; + vuint32_t T6INDEX:5; + vuint32_t:3; + vuint32_t T5INDEX:5; + vuint32_t:3; + vuint32_t T4INDEX:5; + } B; + } CLCR2; /* Command List Control Register 2 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T3E:1; + vuint32_t T3ETE:1; + vuint32_t T3T1E:1; + vuint32_t T3T0E:1; + vuint32_t T3ADCE:1; + vuint32_t:3; + vuint32_t T2E:1; + vuint32_t T2ETE:1; + vuint32_t T2T1E:1; + vuint32_t T2T0E:1; + vuint32_t T2ADCE:1; + vuint32_t:3; + vuint32_t T1E:1; + vuint32_t T1ETE:1; + vuint32_t T1T1E:1; + vuint32_t T1T0E:1; + vuint32_t T1ADCE:1; + vuint32_t:3; + vuint32_t T0E:1; + vuint32_t T0ETE:1; + vuint32_t T0T1E:1; + vuint32_t T0T0E:1; + vuint32_t T0ADCE:1; + } B; + } THCR1; /* Trigger Handler Control Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T7E:1; + vuint32_t T7ETE:1; + vuint32_t T7T1E:1; + vuint32_t T7T0E:1; + vuint32_t T7ADCE:1; + vuint32_t:3; + vuint32_t T6E:1; + vuint32_t T6ETE:1; + vuint32_t T6T1E:1; + vuint32_t T6T0E:1; + vuint32_t T6ADCE:1; + vuint32_t:3; + vuint32_t T5E:1; + vuint32_t T5ETE:1; + vuint32_t T5T1E:1; + vuint32_t T5T0E:1; + vuint32_t T5ADCE:1; + vuint32_t:3; + vuint32_t T4E:1; + vuint32_t T4ETE:1; + vuint32_t T4T1E:1; + vuint32_t T4T0E:1; + vuint32_t T4ADCE:1; + } B; + } THCR2; /* Trigger Handler Control Register 2 */ + + /* Single Conversion Mode - Comment for Dual Conversion Mode */ + union { + vuint16_t R; + struct { + vuint16_t CIR:1; + vuint16_t FC:1; + vuint16_t CMS:1; + vuint16_t:1; + vuint16_t FIFO:2; + vuint16_t:4; + vuint16_t SU:1; + vuint16_t:1; + vuint16_t CH:4; + } B; + } CLR[24]; /* Commands List Register x (double-buffered) (x = 1,...,24) */ + + /* Uncomment for Dual Conversion Mode */ + /*union { + vuint16_t R; + struct { + vuint16_t CIR:1; + vuint16_t FC:1; + vuint16_t CMS:1; + vuint16_t:1; + vuint16_t FIFO:2; + vuint16_t:1; + vuint16_t CHB:4; + vuint16_t :1; + vuint16_t CHA:4; + } B; + } CLR[24]; */ + /* Commands List Register x (double-buffered) (x = 1,...,24) */ + + uint16_t CTU_reserved1[8]; + + + union { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t DMAEN3:1; + vuint16_t DMAEN2:1; + vuint16_t DMAEN1:1; + vuint16_t DMAEN0:1; + } B; + } CR; /* Control Register */ + + uint16_t CTU_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t FIFO_OVERRUN_EN7:1; + vuint32_t FIFO_OVERFLOW_EN7:1; + vuint32_t FIFO_EMPTY_EN7:1; + vuint32_t FIFO_FULL_EN7:1; + vuint32_t FIFO_OVERRUN_EN6:1; + vuint32_t FIFO_OVERFLOW_EN6:1; + vuint32_t FIFO_EMPTY_EN6:1; + vuint32_t FIFO_FULL_EN6:1; + vuint32_t FIFO_OVERRUN_EN5:1; + vuint32_t FIFO_OVERFLOW_EN5:1; + vuint32_t FIFO_EMPTY_EN5:1; + vuint32_t FIFO_FULL_EN5:1; + vuint32_t FIFO_OVERRUN_EN4:1; + vuint32_t FIFO_OVERFLOW_EN4:1; + vuint32_t FIFO_EMPTY_EN4:1; + vuint32_t FIFO_FULL_EN4:1; + vuint32_t FIFO_OVERRUN_EN3:1; + vuint32_t FIFO_OVERFLOW_EN3:1; + vuint32_t FIFO_EMPTY_EN3:1; + vuint32_t FIFO_FULL_EN3:1; + vuint32_t FIFO_OVERRUN_EN2:1; + vuint32_t FIFO_OVERFLOW_EN2:1; + vuint32_t FIFO_EMPTY_EN2:1; + vuint32_t FIFO_FULL_EN2:1; + vuint32_t FIFO_OVERRUN_EN1:1; + vuint32_t FIFO_OVERFLOW_EN1:1; + vuint32_t FIFO_EMPTY_EN1:1; + vuint32_t FIFO_FULL_EN1:1; + vuint32_t FIFO_OVERRUN_EN0:1; + vuint32_t FIFO_OVERFLOW_EN0:1; + vuint32_t FIFO_EMPTY_EN0:1; + vuint32_t FIFO_FULL_EN0:1; + } B; + } FCR; /* CONTROL REGISTER FIFO */ + + union { + vuint32_t R; + struct { + vuint32_t THRESHOLD3:8; + vuint32_t THRESHOLD2:8; + vuint32_t THRESHOLD1:8; + vuint32_t THRESHOLD0:8; + } B; + } TH1; /* Threshold Register */ + + union { + vuint32_t R; + struct { + vuint32_t THRESHOLD7:8; + vuint32_t THRESHOLD6:8; + vuint32_t THRESHOLD5:8; + vuint32_t THRESHOLD4:8; + } B; + } TH2; /* Threshold Register */ + + union { + vuint32_t R; + struct { + vuint32_t FIFO_OVERRUN7:1; + vuint32_t FIFO_OVERFLOW7:1; + vuint32_t FIFO_EMPTY7:1; + vuint32_t FIFO_FULL7:1; + vuint32_t FIFO_OVERRUN6:1; + vuint32_t FIFO_OVERFLOW6:1; + vuint32_t FIFO_EMPTY6:1; + vuint32_t FIFO_FULL6:1; + vuint32_t FIFO_OVERRUN5:1; + vuint32_t FIFO_OVERFLOW5:1; + vuint32_t FIFO_EMPTY5:1; + vuint32_t FIFO_FULL5:1; + vuint32_t FIFO_OVERRUN4:1; + vuint32_t FIFO_OVERFLOW4:1; + vuint32_t FIFO_EMPTY4:1; + vuint32_t FIFO_FULL4:1; + vuint32_t FIFO_OVERRUN3:1; + vuint32_t FIFO_OVERFLOW3:1; + vuint32_t FIFO_EMPTY3:1; + vuint32_t FIFO_FULL3:1; + vuint32_t FIFO_OVERRUN2:1; + vuint32_t FIFO_OVERFLOW2:1; + vuint32_t FIFO_EMPTY2:1; + vuint32_t FIFO_FULL2:1; + vuint32_t FIFO_OVERRUN1:1; + vuint32_t FIFO_OVERFLOW1:1; + vuint32_t FIFO_EMPTY1:1; + vuint32_t FIFO_FULL1:1; + vuint32_t FIFO_OVERRUN0:1; + vuint32_t FIFO_OVERFLOW0:1; + vuint32_t FIFO_EMPTY0:1; + vuint32_t FIFO_FULL0:1; + } B; + } STATUS; /* STATUS REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t NCH:5; + vuint32_t:6; + vuint32_t DATA:10; + } B; + } FRA[8]; /* FIFO RIGHT aligned REGISTER */ + + union { + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t NCH:5; + vuint32_t DATA:10; + vuint32_t:6; + } B; + } FLA[8]; /* FIFO LEFT aligned REGISTER */ + + union { + vuint16_t R; + struct { + vuint16_t:7; + vuint16_t ETOE:1; + vuint16_t T1OE:1; + vuint16_t T0OE:1; + vuint16_t ADCOE:1; + vuint16_t TGSOSM:1; + vuint16_t MRSO:1; + vuint16_t ICE:1; + vuint16_t SMTO:1; + vuint16_t MRSRE:1; + } B; + } CTUEFR; /* Cross Triggering Unit Error Flag Register */ + + union { + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t ADC:1; + vuint16_t T7:1; + vuint16_t T6:1; + vuint16_t T5:1; + vuint16_t T4:1; + vuint16_t T3:1; + vuint16_t T2:1; + vuint16_t T1:1; + vuint16_t T0:1; + vuint16_t MRS:1; + } B; + } CTUIFR; /* Cross Triggering Unit Interrupt Flag Register */ + + union { + vuint16_t R; + struct { + vuint16_t T7IE:1; + vuint16_t T6IE:1; + vuint16_t T5IE:1; + vuint16_t T4IE:1; + vuint16_t T3IE:1; + vuint16_t T2IE:1; + vuint16_t T1IE:1; + vuint16_t T0IE:1; + vuint16_t:5; + vuint16_t MRSDMAE:1; + vuint16_t MRSIE:1; + vuint16_t IEE:1; + } B; + } CTUIR; /* Cross Triggering Unit Interrupt/DMA Register */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t COTR:8; + } B; + } COTR; /* Control On-Time Register */ + + union { + vuint16_t R; + struct { + vuint16_t T7SG:1; + vuint16_t T6SG:1; + vuint16_t T5SG:1; + vuint16_t T4SG:1; + vuint16_t T3SG:1; + vuint16_t T2SG:1; + vuint16_t T1SG:1; + vuint16_t T0SG:1; + vuint16_t CTUADCRESET:1; + vuint16_t CTUODIS:1; + vuint16_t FILTERENABLE:1; + vuint16_t CGRE:1; + vuint16_t FGRE:1; + vuint16_t MRSSG:1; + vuint16_t GRE:1; + vuint16_t TGSISRRE:1; + } B; + } CTUCR; /* Cross Triggering Unit Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t FILTERVALUE:8; + } B; + } CTUFILTER; /* Cross Triggering Unit Digital Filter */ + + union { + vuint16_t R; + struct { + vuint16_t:15; + vuint16_t MDIS:1; + } B; + } CTUPCR; /* Cross Triggering Unit Power Control */ + + }; /* end of CTU_tag */ +/****************************************************************************/ +/* MODULE : FCU */ +/****************************************************************************/ + struct FCU_tag { + + union { + vuint32_t R; + struct { + vuint32_t MCL:1; + vuint32_t TM:2; + vuint32_t:19; + vuint32_t PS:2; + vuint32_t FOM:2; + vuint32_t FOP:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t SRF0:1; + vuint32_t SRF1:1; + vuint32_t SRF2:1; + vuint32_t SRF3:1; + vuint32_t SRF4:1; + vuint32_t SRF5:1; + vuint32_t SRF6:1; + vuint32_t SRF7:1; + vuint32_t SRF8:1; + vuint32_t SRF9:1; + vuint32_t SRF10:1; + vuint32_t SRF11:1; + vuint32_t SRF12:1; + vuint32_t SRF13:1; + vuint32_t SRF14:1; + vuint32_t SRF15:1; + vuint32_t HRF15:1; + vuint32_t HRF14:1; + vuint32_t HRF13:1; + vuint32_t HRF12:1; + vuint32_t HRF11:1; + vuint32_t HRF10:1; + vuint32_t HRF9:1; + vuint32_t HRF8:1; + vuint32_t HRF7:1; + vuint32_t HRF6:1; + vuint32_t HRF5:1; + vuint32_t HRF4:1; + vuint32_t HRF3:1; + vuint32_t HRF2:1; + vuint32_t HRF1:1; + vuint32_t HRF0:1; + } B; + } FFR; /* Fault Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t FRSRF0:1; + vuint32_t FRSRF1:1; + vuint32_t FRSRF2:1; + vuint32_t FRSRF3:1; + vuint32_t FRSRF4:1; + vuint32_t FRSRF5:1; + vuint32_t FRSRF6:1; + vuint32_t FRSRF7:1; + vuint32_t FRSRF8:1; + vuint32_t FRSRF9:1; + vuint32_t FRSRF10:1; + vuint32_t FRSRF11:1; + vuint32_t FRSRF12:1; + vuint32_t FRSRF13:1; + vuint32_t FRSRF14:1; + vuint32_t FRSRF15:1; + vuint32_t FRHRF15:1; + vuint32_t FRHRF14:1; + vuint32_t FRHRF13:1; + vuint32_t FRHRF12:1; + vuint32_t FRHRF11:1; + vuint32_t FRHRF10:1; + vuint32_t FRHRF9:1; + vuint32_t FRHRF8:1; + vuint32_t FRHRF7:1; + vuint32_t FRHRF6:1; + vuint32_t FRHRF5:1; + vuint32_t FRHRF4:1; + vuint32_t FRHRF3:1; + vuint32_t FRHRF2:1; + vuint32_t FRHRF1:1; + vuint32_t FRHRF0:1; + } B; + } FFFR; /* Frozen Fault Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t FSRF2:1; + vuint32_t FSRF3:1; + vuint32_t FSRF4:1; + vuint32_t FSRF5:1; + vuint32_t FSRF6:1; + vuint32_t FSRF7:1; + vuint32_t FSRF8:1; + vuint32_t FSRF9:1; + vuint32_t FSRF10:1; + vuint32_t FSRF11:1; + vuint32_t FSRF12:1; + vuint32_t FSRF13:1; + vuint32_t FSRF14:1; + vuint32_t FSRF15:1; + vuint32_t FHRF15:1; + vuint32_t FHRF14:1; + vuint32_t FHRF13:1; + vuint32_t FHRF12:1; + vuint32_t FHRF11:1; + vuint32_t FHRF10:1; + vuint32_t FHRF9:1; + vuint32_t FHRF8:1; + vuint32_t FHRF7:1; + vuint32_t FHRF6:1; + vuint32_t FHRF5:1; + vuint32_t FHRF4:1; + vuint32_t FHRF3:1; + vuint32_t FHRF2:1; + vuint32_t FHRF1:1; + vuint32_t FHRF0:1; + } B; + } FFGR; /* Fake Fault Generation Register */ + + union { + vuint32_t R; + struct { + vuint32_t ESF0:1; + vuint32_t ESF1:1; + vuint32_t ESF2:1; + vuint32_t ESF3:1; + vuint32_t ESF4:1; + vuint32_t ESF5:1; + vuint32_t ESF6:1; + vuint32_t ESF7:1; + vuint32_t ESF8:1; + vuint32_t ESF9:1; + vuint32_t ESF10:1; + vuint32_t ESF11:1; + vuint32_t ESF12:1; + vuint32_t ESF13:1; + vuint32_t ESF14:1; + vuint32_t ESF15:1; + vuint32_t EHF15:1; + vuint32_t EHF14:1; + vuint32_t EHF13:1; + vuint32_t EHF12:1; + vuint32_t EHF11:1; + vuint32_t EHF10:1; + vuint32_t EHF9:1; + vuint32_t EHF8:1; + vuint32_t EHF7:1; + vuint32_t EHF6:1; + vuint32_t EHF5:1; + vuint32_t EHF4:1; + vuint32_t EHF3:1; + vuint32_t EHF2:1; + vuint32_t EHF1:1; + vuint32_t EHF0:1; + } B; + } FER; /* Fault Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t KR:32; + } B; + } KR; /* Fault Collection Unit Key Register */ + + union { + vuint32_t R; + struct { + vuint32_t TR:32; + } B; + } TR; /* Fault Collection Unit Timeout Register */ + + union { + vuint32_t R; + struct { + vuint32_t TESF0:1; + vuint32_t TESF1:1; + vuint32_t TESF2:1; + vuint32_t TESF3:1; + vuint32_t TESF4:1; + vuint32_t TESF5:1; + vuint32_t TESF6:1; + vuint32_t TESF7:1; + vuint32_t TESF8:1; + vuint32_t TESF9:1; + vuint32_t TESF10:1; + vuint32_t TESF11:1; + vuint32_t TESF12:1; + vuint32_t TESF13:1; + vuint32_t TESF14:1; + vuint32_t TESF15:1; + vuint32_t TEHF15:1; + vuint32_t TEHF14:1; + vuint32_t TEHF13:1; + vuint32_t TEHF12:1; + vuint32_t TEHF11:1; + vuint32_t TEHF10:1; + vuint32_t TEHF9:1; + vuint32_t TEHF8:1; + vuint32_t TEHF7:1; + vuint32_t TEHF6:1; + vuint32_t TEHF5:1; + vuint32_t TEHF4:1; + vuint32_t TEHF3:1; + vuint32_t TEHF2:1; + vuint32_t TEHF1:1; + vuint32_t TEHF0:1; + } B; + } TER; /* Fault Collection Unit Timeout Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t S0:1; + vuint32_t S1:1; + vuint32_t S2:1; + vuint32_t S3:1; + } B; + } MSR; /* Module state register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t MCPS:4; + vuint32_t:12; + vuint32_t MCAS:4; + } B; + } MCSR; /* MC state register */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t FRMCPS:4; + vuint32_t:12; + vuint32_t FRMCAS:4; + } B; + } FMCSR; /* Frozen MC State Register */ + + }; /* end of FCU_tag */ +/****************************************************************************/ +/* MODULE : SMC - Stepper Motor Control */ +/****************************************************************************/ + struct SMC_tag { + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t MCPRE:2; + vuint8_t MCSWAI:1; + vuint8_t:1; + vuint8_t DITH:1; + vuint8_t:1; + vuint8_t MCTOIF:1; + } B; + } CTL0; /* Motor Controller Control Register 0 */ + + union { + vuint8_t R; + struct { + vuint8_t RECIRC:1; + vuint8_t:6; + vuint8_t MCTOIE:1; + } B; + } CTL1; /* Motor Controller Control Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t P:11; + } B; + } PER; /* Motor Controller Period Register */ + + int32_t SMC_reserved0[3]; /* (0x010 - 0x004)/4 = 0x01 */ + + union { + vuint8_t R; + struct { + vuint8_t MCOM:2; + vuint8_t MCAM:2; + vuint8_t:2; + vuint8_t CD:2; + } B; + } CC[12]; /* Motor Controller Channel Control Register 0->11 */ + + int32_t SMC_reserved1; /* (0x020 - 0x01C)/4 = 0x01 */ + + union { + vuint16_t R; + struct { + vuint16_t S:5; + vuint16_t D:11; + } B; + } DC[12]; /* Motor Controller Duty Cycle Register 0->11 */ + + int8_t SMC_reserved2[8]; /* (0x040 - 0x038) = 0x08 */ + + union { + vuint8_t R; + struct { + vuint8_t TOUT:8; + } B; + } SDTO; /* Shortcut detector time-out register */ + + int8_t SMC_reserved3[3]; /* (0x044 - 0x041) = 0x03 */ + + union { + vuint8_t R; + struct { + vuint8_t EN:8; + } B; + } SDE[3]; /* Shortcut detector enable register 0->2 */ + + int8_t SMC_reserved4; /* (0x048 - 0x047) = 0x01 */ + + union { + vuint8_t R; + struct { + vuint8_t IRQ_EN:8; + } B; + } SDIEN[3]; /* Shortcut detector interrupt enable register 0->2 */ + + int8_t SMC_reserved5; /* (0x04C - 0x04B) = 0x01 */ + + union { + vuint8_t R; + struct { + vuint8_t IRQ:8; + } B; + } SDI[3]; /* Shortcut detector interrupt register 0->2 */ + + }; /* end of SMC_tag */ +/****************************************************************************/ +/* MODULE : SSD - Stepper Stall Detect */ +/****************************************************************************/ + struct SSD_tag { + + union { + vuint16_t R; + struct { + vuint16_t TRIG:1; + vuint16_t STEP:2; + vuint16_t RCIR:1; + vuint16_t ITGDIR:1; + vuint16_t BLNDCL:1; + vuint16_t ITGDCL:1; + vuint16_t RTZE:1; + vuint16_t:1; + vuint16_t BLNST:1; + vuint16_t ITGST:1; + vuint16_t:3; + vuint16_t SDCPU:1; + vuint16_t DZDIS:1; + } B; + } CONTROL; /* Control & Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t BLNIF:1; + vuint16_t ITGIF:1; + vuint16_t:5; + vuint16_t ACOVIF:1; + vuint16_t BLNIE:1; + vuint16_t ITGIE:1; + vuint16_t:5; + vuint16_t ACOVIE:1; + } B; + } IRQ; /* Interrupt Flag and Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t ITGACC:16; + } B; + } ITGACC; /* Integrator Accumulator register */ + + union { + vuint16_t R; + struct { + vuint16_t DCNT:16; + } B; + } DCNT; /* Down Counter Count register */ + + union { + vuint16_t R; + struct { + vuint16_t BLNCNTLD:16; + } B; + } BLNCNTLD; /* Blanking Counter Load register */ + + union { + vuint16_t R; + struct { + vuint16_t ITGCNTLD:16; + } B; + } ITGCNTLD; /* Integration Counter Load register */ + + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t BLNDIV:3; + vuint16_t:1; + vuint16_t ITSSDIV:3; + vuint16_t:2; + vuint16_t OFFCNC:2; + vuint16_t:1; + vuint16_t ACDIV:3; + } B; + } PRESCALE; /* Prescaler register */ + + union { + vuint16_t R; + struct { + vuint16_t TMST:1; + vuint16_t ANLOUT:1; + vuint16_t ANLIN:1; + vuint16_t SSDEN:1; + vuint16_t STEP1:1; + vuint16_t POL:1; + vuint16_t ITG:1; + vuint16_t DACHIZ:1; + vuint16_t BUFHIZ:1; + vuint16_t AMPHIZ:1; + vuint16_t RESSHORT:1; + vuint16_t ITSSDRV:1; + vuint16_t ITSSDRVEN:1; + vuint16_t REFDRV:1; + vuint16_t REFDRVEN:1; + } B; + } FNTEST; /* Functional Test Mode register */ + + }; /* end of SSD_tag */ +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_CHANNEL_tag { + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t CADR:24; + } B; + } CADR; /* Channel A Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t CBDR:24; + } B; + } CBDR; /* Channel B Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t CCNTR:24; + } B; + } CCNTR; /* Channel Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPEN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + vuint32_t R; /* Alternate Channel A Data Register */ + } ALTCADR; + + uint32_t emios_channel_reserved[2]; + + }; /* end of EMIOS_CHANNEL_tag */ + + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t CHDIS23:1; + vuint32_t CHDIS22:1; + vuint32_t CHDIS21:1; + vuint32_t CHDIS20:1; + vuint32_t CHDIS19:1; + vuint32_t CHDIS18:1; + vuint32_t CHDIS17:1; + vuint32_t CHDIS16:1; + vuint32_t CHDIS15:1; + vuint32_t CHDIS14:1; + vuint32_t CHDIS13:1; + vuint32_t CHDIS12:1; + vuint32_t CHDIS11:1; + vuint32_t CHDIS10:1; + vuint32_t CHDIS9:1; + vuint32_t CHDIS8:1; + vuint32_t CHDIS7:1; + vuint32_t CHDIS6:1; + vuint32_t CHDIS5:1; + vuint32_t CHDIS4:1; + vuint32_t CHDIS3:1; + vuint32_t CHDIS2:1; + vuint32_t CHDIS1:1; + vuint32_t CHDIS0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CHANNEL_tag CH[28]; + + }; /* end of EMIOS_tag */ +/****************************************************************************/ +/* MODULE : pit */ +/****************************************************************************/ + struct PIT_tag { + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t FRZ:1; + } B; + } PITMCR; + + uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t TSV:32; + } B; + } LDVAL; + + union { + vuint32_t R; + struct { + vuint32_t TVL:32; + } B; + } CVAL; + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; + } CH[6]; + + }; /* end of PIT_tag */ +/****************************************************************************/ +/* MODULE : i2c */ +/****************************************************************************/ + struct I2C_tag { + union { + vuint8_t R; + struct { + vuint8_t ADR:7; + vuint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + vuint8_t R; + struct { + vuint8_t IBC:8; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + vuint8_t R; + struct { + vuint8_t MDIS:1; + vuint8_t IBIE:1; + vuint8_t MS:1; + vuint8_t TX:1; + vuint8_t NOACK:1; + vuint8_t RSTA:1; + vuint8_t DMAEN:1; + vuint8_t IBDOZE:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + vuint8_t R; + struct { + vuint8_t TCF:1; + vuint8_t IAAS:1; + vuint8_t IBB:1; + vuint8_t IBAL:1; + vuint8_t:1; + vuint8_t SRW:1; + vuint8_t IBIF:1; + vuint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + vuint8_t R; + struct { + vuint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + vuint8_t R; + struct { + vuint8_t BIIE:1; + vuint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; /* end of I2C_tag */ +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + struct MPU_tag { + union { + vuint32_t R; + struct { + vuint32_t SPERR:8; + vuint32_t:4; + vuint32_t HRL:4; + vuint32_t NSP:4; + vuint32_t NGRD:4; + vuint32_t:7; + vuint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */ + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR0; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR0; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR1; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR1; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR2; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR2; + + union { + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR3; + + union { + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR3; + + uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t SRTADDR:27; + vuint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + vuint32_t R; + struct { + vuint32_t ENDADDR:27; + vuint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + vuint32_t R; + struct { + vuint32_t PID:8; + vuint32_t PIDMASK:8; + vuint32_t:15; + vuint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */ + + union { + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t M5RE:1; + vuint32_t M5WE:1; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + + }; /* end of MPU_tag */ +/****************************************************************************/ +/* MODULE : eDMA */ +/****************************************************************************/ + +/*for "standard" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */ + struct EDMA_TCD_STD_tag { + + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + + vuint32_t NBYTES; /* inner (“minor”) byte count */ + + vint32_t SLAST; /* last destination address adjustment, or + scatter/gather address (if e_sg = 1) */ + + vuint32_t DADDR; /* destination address */ + + vuint16_t CITERE_LINK:1; + vuint16_t CITER:15; + + vint16_t DOFF; /* signed destination address offset */ + + vint32_t DLAST_SGA; + + vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ + vuint16_t BITER:15; + + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + + }; /* end of EDMA_TCD_STD_tag */ + +/*for "channel link" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/ + struct EDMA_TCD_CHLINK_tag { + + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + + vuint32_t NBYTES; /* inner (“minor”) byte count */ + + vint32_t SLAST; /* last destination address adjustment, or + scatter/gather address (if e_sg = 1) */ + + vuint32_t DADDR; /* destination address */ + + vuint16_t CITERE_LINK:1; + vuint16_t CITERLINKCH:6; + vuint16_t CITER:9; + + vint16_t DOFF; /* signed destination address offset */ + + vint32_t DLAST_SGA; + + vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ + vuint16_t BITERLINKCH:6; + vuint16_t BITER:9; + + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + + }; /* end of EDMA_TCD_CHLINK_tag */ + + struct EDMA_tag { + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t ERCA:1; + vuint32_t EDBG:1; + vuint32_t:1; + } B; + } CR; /* Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t VLD:1; + vuint32_t:15; + vuint32_t GPE:1; + vuint32_t CPE:1; + vuint32_t ERRCHN:6; + vuint32_t SAE:1; + vuint32_t SOE:1; + vuint32_t DAE:1; + vuint32_t DOE:1; + vuint32_t NCE:1; + vuint32_t SGE:1; + vuint32_t SBE:1; + vuint32_t DBE:1; + } B; + } ESR; /* Error Status Register */ + + int16_t EDMA_reserved1[3]; /* (0x0E - 0x08)/2 = 0x03 */ + + union { + vuint16_t R; + struct { + vuint16_t ERQ15:1; + vuint16_t ERQ14:1; + vuint16_t ERQ13:1; + vuint16_t ERQ12:1; + vuint16_t ERQ11:1; + vuint16_t ERQ10:1; + vuint16_t ERQ09:1; + vuint16_t ERQ08:1; + vuint16_t ERQ07:1; + vuint16_t ERQ06:1; + vuint16_t ERQ05:1; + vuint16_t ERQ04:1; + vuint16_t ERQ03:1; + vuint16_t ERQ02:1; + vuint16_t ERQ01:1; + vuint16_t ERQ00:1; + } B; + } ERQRL; /* DMA Enable Request Register Low */ + + int16_t EDMA_reserved2[3]; /* (0x16 - 0x10)/2 = 0x03 */ + + union { + vuint16_t R; + struct { + vuint16_t EEI15:1; + vuint16_t EEI14:1; + vuint16_t EEI13:1; + vuint16_t EEI12:1; + vuint16_t EEI11:1; + vuint16_t EEI10:1; + vuint16_t EEI09:1; + vuint16_t EEI08:1; + vuint16_t EEI07:1; + vuint16_t EEI06:1; + vuint16_t EEI05:1; + vuint16_t EEI04:1; + vuint16_t EEI03:1; + vuint16_t EEI02:1; + vuint16_t EEI01:1; + vuint16_t EEI00:1; + } B; + } EEIRL; /* DMA Enable Error Interrupt Register Low */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SERQ:7; + } B; + } SERQR; /* DMA Set Enable Request Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CERQ:7; + } B; + } CERQR; /* DMA Clear Enable Request Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SEEI:7; + } B; + } SEEIR; /* DMA Set Enable Error Interrupt Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CEEI:7; + } B; + } CEEIR; /* DMA Clear Enable Error Interrupt Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CINT:7; + } B; + } CIRQR; /* DMA Clear Interrupt Request Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CER:7; + } B; + } CERR; /* DMA Clear error Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SSB:7; + } B; + } SSBR; /* Set Start Bit Register */ + + union { + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CDSB:7; + } B; + } CDSBR; /* Clear Done Status Bit Register */ + + int16_t EDMA_reserved3[3]; /* (0x26 - 0x20)/2 = 0x03 */ + + union { + vuint16_t R; + struct { + vuint16_t INT15:1; + vuint16_t INT14:1; + vuint16_t INT13:1; + vuint16_t INT12:1; + vuint16_t INT11:1; + vuint16_t INT10:1; + vuint16_t INT09:1; + vuint16_t INT08:1; + vuint16_t INT07:1; + vuint16_t INT06:1; + vuint16_t INT05:1; + vuint16_t INT04:1; + vuint16_t INT03:1; + vuint16_t INT02:1; + vuint16_t INT01:1; + vuint16_t INT00:1; + } B; + } IRQRL; /* DMA Interrupt Request Low */ + + int16_t EDMA_reserved4[3]; /* (0x2E - 0x28)/2 = 0x03 */ + + union { + vuint16_t R; + struct { + vuint16_t ERR15:1; + vuint16_t ERR14:1; + vuint16_t ERR13:1; + vuint16_t ERR12:1; + vuint16_t ERR11:1; + vuint16_t ERR10:1; + vuint16_t ERR09:1; + vuint16_t ERR08:1; + vuint16_t ERR07:1; + vuint16_t ERR06:1; + vuint16_t ERR05:1; + vuint16_t ERR04:1; + vuint16_t ERR03:1; + vuint16_t ERR02:1; + vuint16_t ERR01:1; + vuint16_t ERR00:1; + } B; + } ERL; /* DMA Error Low */ + + int16_t EDMA_reserved5[3]; /* (0x36 - 0x30)/2 = 0x03 */ + + union { + vuint16_t R; + struct { + vuint16_t HRS15:1; + vuint16_t HRS14:1; + vuint16_t HRS13:1; + vuint16_t HRS12:1; + vuint16_t HRS11:1; + vuint16_t HRS10:1; + vuint16_t HRS09:1; + vuint16_t HRS08:1; + vuint16_t HRS07:1; + vuint16_t HRS06:1; + vuint16_t HRS05:1; + vuint16_t HRS04:1; + vuint16_t HRS03:1; + vuint16_t HRS02:1; + vuint16_t HRS01:1; + vuint16_t HRS00:1; + } B; + } HRSL; /* DMA Hardware Request Status Low */ + + uint32_t edma_reserved1[50]; /* (0x100 - 0x038)/4 = 0x32 */ + + union { + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[16]; /* Channel n Priority */ + + uint32_t edma_reserved2[956]; /* (0x1000 - 0x0110)/4 = 0x3BC */ + + struct EDMA_TCD_STD_tag TCD[16]; + /* struct EDMA_TCD_CHLINK_tag TCD[16]; */ + + }; /* end of EDMA_tag */ +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t VTES:1; + vuint32_t:4; + vuint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; + vuint32_t INTVEC:9; + vuint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t SET:1; + vuint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PRI:4; + } B; + } PSR[512]; /* Software Set/Clear Interrupt Register */ + + }; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t PCSIS7:1; + vuint32_t PCSIS6:1; + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:7; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; + vuint32_t:16; + } B; + } TCR; + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; + vuint32_t:2; + vuint32_t EOQFRE:1; + vuint32_t TFUFRE:1; + vuint32_t:1; + vuint32_t TFFFRE:1; + vuint32_t TFFFDIRS:1; + vuint32_t:4; + vuint32_t RFOFRE:1; + vuint32_t:1; + vuint32_t RFDFRE:1; + vuint32_t RFDFDIRS:1; + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t:2; + vuint32_t PCS7:1; + vuint32_t PCS6:1; + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[5]; /* Transmit FIFO Registers */ + + vuint32_t DSPI_reserved_txf[11]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[5]; /* Receive FIFO Registers */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t:1; + vuint32_t MTOCNT:6; + vuint32_t:4; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:6; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; /* end of DSPI_tag */ +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAKMSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t SLFWAK:1; + vuint32_t WRNEN:1; + vuint32_t LPMACK:1; + vuint32_t WAKSRC:1; + vuint32_t:1; + vuint32_t SRXDIS:1; + vuint32_t BCC:1; + vuint32_t:2; + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t:1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */ + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : DMAMUX */ +/****************************************************************************/ + struct DMAMUX_tag { + union { + vuint8_t R; + struct { + vuint8_t ENBL:1; + vuint8_t TRIG:1; + vuint8_t SOURCE:6; + } B; + } CHCONFIG[16]; /* DMA Channel Configuration Register */ + + }; /* end of DMAMUX_tag */ +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + vuint16_t R; + struct { + vuint16_t CHIVER:8; /* CHI Version Number */ + vuint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + vuint16_t R; + struct { + vuint16_t MEN:1; /* module enable */ + vuint16_t:1; + vuint16_t SCMD:1; /* single channel mode */ + vuint16_t CHB:1; /* channel B enable */ + vuint16_t CHA:1; /* channel A enable */ + vuint16_t SFFE:1; /* synchronization frame filter enable */ + vuint16_t:5; + vuint16_t CLKSEL:1; /* protocol engine clock source select */ + vuint16_t BITRATE:3; /* protocol engine clock prescaler */ + vuint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t STBSSEL:7; /* strobe signal select */ + vuint16_t:3; + vuint16_t ENB:1; /* strobe signal enable */ + vuint16_t:2; + vuint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t STB3EN:1; /* strobe port enable */ + vuint16_t STB2EN:1; /* strobe port enable */ + vuint16_t STB1EN:1; /* strobe port enable */ + vuint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + vuint16_t:1; + vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + + typedef union uMBSSUTR { + vuint16_t R; + struct { + + vuint16_t:2; + vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ + vuint16_t:2; + vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + vuint16_t R; + vuint8_t byte[2]; + struct { + vuint16_t WME:1; /* write mode external correction command */ + vuint16_t:3; + vuint16_t EOC_AP:2; /* external offset correction application */ + vuint16_t ERC_AP:2; /* external rate correction application */ + vuint16_t BSY:1; /* command write busy / write mode command */ + vuint16_t:3; + vuint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + vuint16_t R; + struct { + vuint16_t MIF:1; /* module interrupt flag */ + vuint16_t PRIF:1; /* protocol interrupt flag */ + vuint16_t CHIF:1; /* CHI interrupt flag */ + vuint16_t WKUPIF:1; /* wakeup interrupt flag */ + vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + vuint16_t RBIF:1; /* receive message buffer interrupt flag */ + vuint16_t TBIF:1; /* transmit buffer interrupt flag */ + vuint16_t MIE:1; /* module interrupt enable */ + vuint16_t PRIE:1; /* protocol interrupt enable */ + vuint16_t CHIE:1; /* CHI interrupt enable */ + vuint16_t WKUPIE:1; /* wakeup interrupt enable */ + vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + vuint16_t RBIE:1; /* receive message buffer interrupt enable */ + vuint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + vuint16_t R; + struct { + vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + vuint16_t INTLIF:1; /* internal protocol error interrupt flag */ + vuint16_t ILCFIF:1; /* illegal protocol configuration flag */ + vuint16_t CSAIF:1; /* cold start abort interrupt flag */ + vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + vuint16_t MTXIF:1; /* media access test symbol received flag */ + vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + vuint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + vuint16_t R; + struct { + vuint16_t EMCIF:1; /* error mode changed interrupt flag */ + vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t:2; + vuint16_t EVTIF:1; /* even cycle table written interrupt flag */ + vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + vuint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + vuint16_t R; + struct { + vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + vuint16_t CSAIE:1; /* cold start abort interrupt enable */ + vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + vuint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + vuint16_t R; + struct { + vuint16_t EMCIE:1; /* error mode changed interrupt enable */ + vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t:2; + vuint16_t EVTIE:1; /* even cycle table written interrupt enable */ + vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + vuint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + vuint16_t R; + struct { + vuint16_t FRLBEF:1; /* flame lost channel B error flag */ + vuint16_t FRLAEF:1; /* frame lost channel A error flag */ + vuint16_t PCMIEF:1; /* command ignored error flag */ + vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + vuint16_t MSBEF:1; /* message buffer search error flag */ + vuint16_t MBUEF:1; /* message buffer utilization error flag */ + vuint16_t LCKEF:1; /* lock error flag */ + vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + vuint16_t SBCFEF:1; /* system bus communication failure error flag */ + vuint16_t FIDEF:1; /* frame ID error flag */ + vuint16_t DPLEF:1; /* dynamic payload length error flag */ + vuint16_t SPLEF:1; /* static payload length error flag */ + vuint16_t NMLEF:1; /* network management length error flag */ + vuint16_t NMFEF:1; /* network management frame error flag */ + vuint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + vuint16_t R; + struct { + + vuint16_t:2; + vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */ + vuint16_t:2; + vuint16_t RBIVEC:6; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + vuint16_t R; + struct { + vuint16_t ERRMODE:2; /* error mode */ + vuint16_t SLOTMODE:2; /* slot mode */ + vuint16_t:1; + vuint16_t PROTSTATE:3; /* protocol state */ + vuint16_t SUBSTATE:4; /* protocol sub state */ + vuint16_t:1; + vuint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + vuint16_t R; + struct { + vuint16_t CSAA:1; /* cold start attempt abort flag */ + vuint16_t CSP:1; /* cold start path */ + vuint16_t:1; + vuint16_t REMCSAT:5; /* remanining coldstart attempts */ + vuint16_t CPN:1; /* cold start noise path */ + vuint16_t HHR:1; /* host halt request pending */ + vuint16_t FRZ:1; /* freeze occured */ + vuint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + vuint16_t R; + struct { + vuint16_t NBVB:1; /* NIT boundary violation on channel B */ + vuint16_t NSEB:1; /* NIT syntax error on channel B */ + vuint16_t STCB:1; /* symbol window transmit conflict on channel B */ + vuint16_t SBVB:1; /* symbol window boundary violation on channel B */ + vuint16_t SSEB:1; /* symbol window syntax error on channel B */ + vuint16_t MTB:1; /* media access test symbol MTS received on channel B */ + vuint16_t NBVA:1; /* NIT boundary violation on channel A */ + vuint16_t NSEA:1; /* NIT syntax error on channel A */ + vuint16_t STCA:1; /* symbol window transmit conflict on channel A */ + vuint16_t SBVA:1; /* symbol window boundary violation on channel A */ + vuint16_t SSEA:1; /* symbol window syntax error on channel A */ + vuint16_t MTA:1; /* media access test symbol MTS received on channel A */ + vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t WUB:1; /* wakeup symbol received on channel B */ + vuint16_t ABVB:1; /* aggregated boundary violation on channel B */ + vuint16_t AACB:1; /* aggregated additional communication on channel B */ + vuint16_t ACEB:1; /* aggregated content error on channel B */ + vuint16_t ASEB:1; /* aggregated syntax error on channel B */ + vuint16_t AVFB:1; /* aggregated valid frame on channel B */ + vuint16_t:2; + vuint16_t WUA:1; /* wakeup symbol received on channel A */ + vuint16_t ABVA:1; /* aggregated boundary violation on channel A */ + vuint16_t AACA:1; /* aggregated additional communication on channel A */ + vuint16_t ACEA:1; /* aggregated content error on channel A */ + vuint16_t ASEA:1; /* aggregated syntax error on channel A */ + vuint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t MIFR:1; /* module interrupt flag */ + vuint16_t PRIFR:1; /* protocol interrupt flag */ + vuint16_t CHIFR:1; /* CHI interrupt flag */ + vuint16_t WUPIFR:1; /* wakeup interrupt flag */ + vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + vuint16_t RBIFR:1; /* receive message buffer interrupt flag */ + vuint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + vuint16_t R; + struct { + vuint16_t SFEVB:4; /* sync frames channel B, even cycle */ + vuint16_t SFEVA:4; /* sync frames channel A, even cycle */ + vuint16_t SFODB:4; /* sync frames channel B, odd cycle */ + vuint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + vuint16_t R; + struct { + vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + vuint16_t CYCNUM:6; /* cycle number */ + vuint16_t ELKS:1; /* even cycle tables lock status */ + vuint16_t OLKS:1; /* odd cycle tables lock status */ + vuint16_t EVAL:1; /* even cycle tables valid */ + vuint16_t OVAL:1; /* odd cycle tables valid */ + vuint16_t:1; + vuint16_t OPT:1; /*one pair trigger */ + vuint16_t SDVEN:1; /* sync frame deviation table enable */ + vuint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t T2CFG:1; /* timer 2 configuration */ + vuint16_t T2REP:1; /* timer 2 repetitive mode */ + vuint16_t:1; + vuint16_t T2SP:1; /* timer 2 stop */ + vuint16_t T2TR:1; /* timer 2 trigger */ + vuint16_t T2ST:1; /* timer 2 state */ + vuint16_t:3; + vuint16_t T1REP:1; /* timer 1 repetitive mode */ + vuint16_t:1; + vuint16_t T1SP:1; /* timer 1 stop */ + vuint16_t T1TR:1; /* timer 1 trigger */ + vuint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + vuint16_t:2; + vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* static slot number */ + vuint16_t:1; + vuint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* selector */ + vuint16_t:1; + vuint16_t CNTCFG:2; /* counter configuration */ + vuint16_t MCY:1; /* multi cycle selection */ + vuint16_t VFR:1; /* valid frame selection */ + vuint16_t SYF:1; /* sync frame selection */ + vuint16_t NUF:1; /* null frame selection */ + vuint16_t SUF:1; /* startup frame selection */ + vuint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + vuint16_t R; + struct { + vuint16_t VFB:1; /* valid frame on channel B */ + vuint16_t SYB:1; /* valid sync frame on channel B */ + vuint16_t NFB:1; /* valid null frame on channel B */ + vuint16_t SUB:1; /* valid startup frame on channel B */ + vuint16_t SEB:1; /* syntax error on channel B */ + vuint16_t CEB:1; /* content error on channel B */ + vuint16_t BVB:1; /* boundary violation on channel B */ + vuint16_t TCB:1; /* tx conflict on channel B */ + vuint16_t VFA:1; /* valid frame on channel A */ + vuint16_t SYA:1; /* valid sync frame on channel A */ + vuint16_t NFA:1; /* valid null frame on channel A */ + vuint16_t SUA:1; /* valid startup frame on channel A */ + vuint16_t SEA:1; /* syntax error on channel A */ + vuint16_t CEA:1; /* content error on channel A */ + vuint16_t BVA:1; /* boundary violation on channel A */ + vuint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + vuint16_t R; + struct { + vuint16_t MTE:1; /* media access test symbol transmission enable */ + vuint16_t:1; + vuint16_t CYCCNTMSK:6; /* cycle counter mask */ + vuint16_t:2; + vuint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + + typedef union uRSBIR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* selector */ + vuint16_t:5; + vuint16_t RSBIDX:7; /* receive shadow buffer index */ + } B; + } RSBIR_t; + + typedef union uRFDSR { + vuint16_t R; + struct { + vuint16_t FIFODEPTH:8; /* fifo depth */ + vuint16_t:1; + vuint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t IBD:1; /* interval boundary */ + vuint16_t SEL:2; /* filter number */ + vuint16_t:1; + vuint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t F3MD:1; /* filter mode */ + vuint16_t F2MD:1; /* filter mode */ + vuint16_t F1MD:1; /* filter mode */ + vuint16_t F0MD:1; /* filter mode */ + vuint16_t:4; + vuint16_t F3EN:1; /* filter enable */ + vuint16_t F2EN:1; /* filter enable */ + vuint16_t F1EN:1; /* filter enable */ + vuint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + vuint16_t R; + struct { + vuint16_t ACTION_POINT_OFFSET:6; + vuint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + vuint16_t R; + struct { + vuint16_t MINISLOT_AFTER_ACTION_POINT:6; + vuint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + vuint16_t R; + struct { + vuint16_t WAKEUP_SYMBOL_RX_LOW:6; + vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; + vuint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + vuint16_t R; + struct { + vuint16_t CAS_RX_LOW_MAX:7; + vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + vuint16_t R; + struct { + vuint16_t TSS_TRANSMITTER:4; + vuint16_t WAKEUP_SYMBOL_TX_LOW:6; + vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + vuint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_B:9; + vuint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + vuint16_t R; + struct { + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + vuint16_t R; + struct { + vuint16_t MINISLOT_EXISTS:1; + vuint16_t SYMBOL_WINDOW_EXISTS:1; + vuint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + vuint16_t R; + struct { + vuint16_t SINGLE_SLOT_ENABLED:1; + vuint16_t WAKEUP_CHANNEL:1; + vuint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + vuint16_t R; + struct { + vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; + vuint16_t KEY_SLOT_USED_FOR_SYNC:1; + vuint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + vuint16_t R; + struct { + vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + vuint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + vuint16_t R; + struct { + vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + vuint16_t R; + struct { + vuint16_t RATE_CORRECTION_OUT:11; + vuint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + vuint16_t R; + struct { + vuint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + vuint16_t R; + struct { + vuint16_t MACRO_INITIAL_OFFSET_B:7; + vuint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + vuint16_t R; + struct { + vuint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + vuint16_t R; + struct { + vuint16_t WAKEUP_PATTERN:6; + vuint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_A:9; + vuint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + vuint16_t R; + struct { + vuint16_t MICRO_INITIAL_OFFSET_B:8; + vuint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + vuint16_t R; + struct { + vuint16_t EXTERN_RATE_CORRECTION:3; + vuint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + vuint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + vuint16_t R; + struct { + vuint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + vuint16_t R; + struct { + vuint16_t CLUSTER_DRIFT_DAMPING:5; + vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + vuint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + vuint16_t R; + struct { + vuint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + vuint16_t R; + struct { + vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + vuint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + vuint16_t R; + struct { + vuint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + vuint16_t R; + struct { + vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + vuint16_t R; + struct { + vuint16_t EXTERN_OFFSET_CORRECTION:3; + vuint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MCM:1; /* message buffer commit mode */ + vuint16_t MBT:1; /* message buffer type */ + vuint16_t MTD:1; /* message buffer direction */ + vuint16_t CMT:1; /* commit for transmission */ + vuint16_t EDT:1; /* enable / disable trigger */ + vuint16_t LCKT:1; /* lock request trigger */ + vuint16_t MBIE:1; /* message buffer interrupt enable */ + vuint16_t:3; + vuint16_t DUP:1; /* data updated */ + vuint16_t DVAL:1; /* data valid */ + vuint16_t EDS:1; /* lock status */ + vuint16_t LCKS:1; /* enable / disable status */ + vuint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + vuint16_t R; + struct { + vuint16_t MTM:1; /* message buffer transmission mode */ + vuint16_t CHNLA:1; /* channel assignement */ + vuint16_t CHNLB:1; /* channel assignement */ + vuint16_t CCFE:1; /* cycle counter filter enable */ + vuint16_t CCFMSK:6; /* cycle counter filter mask */ + vuint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + + union { + vuint16_t R; + struct { + vuint16_t:9; + vuint16_t MBIDX:7; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + vuint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + vuint16_t R; + } SYSBADLR_t; + typedef union uPADR { + vuint16_t R; + } PADR_t; + typedef union uPDAR { + vuint16_t R; + } PDAR_t; + typedef union uCASERCR { + vuint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + vuint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + vuint16_t R; + } CYCTR_t; + typedef union uMTCTR { + vuint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + vuint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + vuint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + vuint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + vuint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + vuint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + vuint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + vuint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + vuint16_t R; + } NMVR_t; + typedef union uNMVLR { + vuint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + vuint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + vuint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + vuint16_t R; + } TI2CR1_t; + typedef union uSSCR { + vuint16_t R; + } SSCR_t; + typedef union uRFSR { + vuint16_t R; + } RFSR_t; + typedef union uRFSIR { + vuint16_t R; + } RFSIR_t; + typedef union uRFARIR { + vuint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + vuint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + vuint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + vuint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + vuint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + vuint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + vuint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + vuint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + volatile PADR_t PADR; /*PE address register *//*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + vuint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + vuint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + vuint16_t:5; + vuint16_t HDCRC:11; /* Header CRC */ + vuint16_t:2; + vuint16_t CYCCNT:6; /* Cycle Count */ + vuint16_t:1; + vuint16_t PLDLEN:7; /* Payload Length */ + vuint16_t:1; + vuint16_t PPI:1; /* Payload Preamble Indicator */ + vuint16_t NUF:1; /* Null Frame Indicator */ + vuint16_t SYF:1; /* Sync Frame Indicator */ + vuint16_t SUF:1; /* Startup Frame Indicator */ + vuint16_t FID:11; /* Frame ID */ + } B; + vuint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + vuint16_t VFB:1; /* Valid Frame on channel B */ + vuint16_t SYB:1; /* Sync Frame Indicator channel B */ + vuint16_t NFB:1; /* Null Frame Indicator channel B */ + vuint16_t SUB:1; /* Startup Frame Indicator channel B */ + vuint16_t SEB:1; /* Syntax Error on channel B */ + vuint16_t CEB:1; /* Content Error on channel B */ + vuint16_t BVB:1; /* Boundary Violation on channel B */ + vuint16_t CH:1; /* Channel */ + vuint16_t VFA:1; /* Valid Frame on channel A */ + vuint16_t SYA:1; /* Sync Frame Indicator channel A */ + vuint16_t NFA:1; /* Null Frame Indicator channel A */ + vuint16_t SUA:1; /* Startup Frame Indicator channel A */ + vuint16_t SEA:1; /* Syntax Error on channel A */ + vuint16_t CEA:1; /* Content Error on channel A */ + vuint16_t BVA:1; /* Boundary Violation on channel A */ + vuint16_t:1; + } RX; + struct { + vuint16_t VFB:1; /* Valid Frame on channel B */ + vuint16_t SYB:1; /* Sync Frame Indicator channel B */ + vuint16_t NFB:1; /* Null Frame Indicator channel B */ + vuint16_t SUB:1; /* Startup Frame Indicator channel B */ + vuint16_t SEB:1; /* Syntax Error on channel B */ + vuint16_t CEB:1; /* Content Error on channel B */ + vuint16_t BVB:1; /* Boundary Violation on channel B */ + vuint16_t TCB:1; /* Tx Conflict on channel B */ + vuint16_t VFA:1; /* Valid Frame on channel A */ + vuint16_t SYA:1; /* Sync Frame Indicator channel A */ + vuint16_t NFA:1; /* Null Frame Indicator channel A */ + vuint16_t SUA:1; /* Startup Frame Indicator channel A */ + vuint16_t SEA:1; /* Syntax Error on channel A */ + vuint16_t CEA:1; /* Content Error on channel A */ + vuint16_t BVA:1; /* Boundary Violation on channel A */ + vuint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + vuint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + vuint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; +/****************************************************************************/ +/* MODULE : LCD */ +/****************************************************************************/ + struct LCD_tag { + + union { + vuint32_t R; + struct { + vuint32_t LCDEN:1; + vuint32_t LCDRST:1; + vuint32_t LCDRCS:1; + vuint32_t DUTY:3; + vuint32_t BIAS:1; + vuint32_t VLCDS:1; + vuint32_t PWR:2; + vuint32_t BSTEN:1; + vuint32_t BSTSEL:1; + vuint32_t BSTAO:1; + vuint32_t:1; + vuint32_t LCDINT:1; + vuint32_t EOFF:1; + vuint32_t NOF:8; + vuint32_t:2; + vuint32_t LCDBPA:1; + vuint32_t:2; + vuint32_t LCDBPS:3; + } B; + } CR; /* LCD Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t LCLK:4; + vuint32_t:24; + } B; + } PCR; /* LCD Prescaler Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t CCEN:1; + vuint32_t:4; + vuint32_t LCC:11; + vuint32_t:16; + } B; + } CCR; /* LCD Contrast Control Register */ + + int32_t LCD_reserved1; /* (0x10 - 0x0C)/4 = 0x01 */ + + union { + vuint32_t R; + struct { + vuint32_t FP31EN:1; + vuint32_t FP30EN:1; + vuint32_t FP29EN:1; + vuint32_t FP28EN:1; + vuint32_t FP27EN:1; + vuint32_t FP26EN:1; + vuint32_t FP25EN:1; + vuint32_t FP24EN:1; + vuint32_t FP23EN:1; + vuint32_t FP22EN:1; + vuint32_t FP21EN:1; + vuint32_t FP20EN:1; + vuint32_t FP19EN:1; + vuint32_t FP18EN:1; + vuint32_t FP17EN:1; + vuint32_t FP16EN:1; + vuint32_t FP15EN:1; + vuint32_t FP14EN:1; + vuint32_t FP13EN:1; + vuint32_t FP12EN:1; + vuint32_t FP11EN:1; + vuint32_t FP10EN:1; + vuint32_t FP9EN:1; + vuint32_t FP8EN:1; + vuint32_t FP7EN:1; + vuint32_t FP6EN:1; + vuint32_t FP5EN:1; + vuint32_t FP4EN:1; + vuint32_t FP3EN:1; + vuint32_t FP2EN:1; + vuint32_t FP1EN:1; + vuint32_t FP0EN:1; + } B; + } FPENR0; /* LCD Frontplane Enable Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t FP63EN:1; + vuint32_t FP62EN:1; + vuint32_t FP61EN:1; + vuint32_t FP60EN:1; + vuint32_t FP59EN:1; + vuint32_t FP58EN:1; + vuint32_t FP57EN:1; + vuint32_t FP56EN:1; + vuint32_t FP55EN:1; + vuint32_t FP54EN:1; + vuint32_t FP53EN:1; + vuint32_t FP52EN:1; + vuint32_t FP51EN:1; + vuint32_t FP50EN:1; + vuint32_t FP49EN:1; + vuint32_t FP48EN:1; + vuint32_t FP47EN:1; + vuint32_t FP46EN:1; + vuint32_t FP45EN:1; + vuint32_t FP44EN:1; + vuint32_t FP43EN:1; + vuint32_t FP42EN:1; + vuint32_t FP41EN:1; + vuint32_t FP40EN:1; + vuint32_t FP39EN:1; + vuint32_t FP38EN:1; + vuint32_t FP37EN:1; + vuint32_t FP36EN:1; + vuint32_t FP35EN:1; + vuint32_t FP34EN:1; + vuint32_t FP33EN:1; + vuint32_t FP32EN:1; + } B; + } FPENR1; /* LCD Frontplane Enable Register 1 */ + + int32_t LCD_reserved2[2]; /* (0x20 - 0x18)/4 = 0x02 */ + + union { + vuint32_t R; + } RAM[16]; /* LCD RAM Register */ + + }; /* end of LCD_tag */ +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + struct EBI_CS_tag { + union { /* Base Register Bank */ + vuint32_t R; + struct { + vuint32_t BA:17; + vuint32_t:3; + vuint32_t PS:1; + vuint32_t:4; + vuint32_t BL:1; + vuint32_t WEBS:1; + vuint32_t TBDIP:1; + vuint32_t:2; + vuint32_t BI:1; + vuint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + vuint32_t R; + struct { + vuint32_t AM:17; + vuint32_t:7; + vuint32_t SCY:4; + vuint32_t:1; + vuint32_t BSCY:2; + vuint32_t:1; + } B; + } OR; + }; /* end of EBI_CS_tag */ + + struct EBI_tag { + union { /* Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t SIZEN:1; + vuint32_t SIZE:2; + vuint32_t:8; + vuint32_t ACGE:1; + vuint32_t EXTM:1; + vuint32_t EARB:1; + vuint32_t EARP:2; + vuint32_t:4; + vuint32_t MDIS:1; + vuint32_t:4; + vuint32_t AD_MUX:1; + vuint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TEAF:1; + vuint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t BMT:8; + vuint32_t BME:1; + vuint32_t:7; + } B; + } BMCR; + + struct EBI_CS_tag CS[2]; + + }; /* end of EBI_tag */ +/****************************************************************************/ +/* MODULE : DFLASH */ +/****************************************************************************/ + struct DFLASH_tag { + union { /* Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:1; + vuint32_t:1; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* LML Register */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:2; + vuint32_t MLK:2; + vuint32_t LLK:16; + } B; + } LML; + + union { /* HBL Register */ + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t:23; + vuint32_t HBLOCK:8; + } B; + } HBL; + + union { /* SLML Register */ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:2; + vuint32_t SMK:2; + vuint32_t SLK:16; + } B; + } SLL; + + union { /* LMS Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; + vuint32_t LSL:16; + } B; + } LMS; + + union { /* High Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HSL:6; + } B; + } HBS; + + union { /* Address Register */ + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t ADD:20; + vuint32_t:3; + } B; + } ADR; + + int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */ + + union { /* User Test Register 0 */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test Register 1 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test Register 2 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-4 */ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + }; /* end of Dflash_tag */ +/****************************************************************************/ +/* MODULE : CFLASH */ +/****************************************************************************/ + struct CFLASH_tag { + union { /* Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t EDC:1; + vuint32_t:4; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t:1; + vuint32_t:1; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { /* LML Register */ + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t TSLK:1; + vuint32_t:2; + vuint32_t MLK:2; + vuint32_t LLK:16; + } B; + } LML; + + union { /* HBL Register */ + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t:23; + vuint32_t HBLOCK:8; + } B; + } HBL; + + union { /* SLML Register */ + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t STSLK:1; + vuint32_t:2; + vuint32_t SMK:2; + vuint32_t SLK:16; + } B; + } SLL; + + union { /* LMS Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; + vuint32_t LSL:16; + } B; + } LMS; + + union { /* High Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HSL:6; + } B; + } HBS; + + union { /* Address Register */ + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t ADD:20; + vuint32_t:3; + } B; + } ADR; + + union { /* CFLASH Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t BK0_APC:5; + vuint32_t BK0_WWSC:5; + vuint32_t BK0_RWSC:5; + vuint32_t BK0_RWWC2:1; + vuint32_t BK0_RWWC1:1; + vuint32_t B0_P1_BCFG:2; + vuint32_t B0_P1_DPFE:1; + vuint32_t B0_P1_IPFE:1; + vuint32_t B0_P1_PFLM:2; + vuint32_t B0_P1_BFE:1; + vuint32_t BK0_RWWC0:1; + vuint32_t B0_P0_BCFG:2; + vuint32_t B0_P0_DPFE:1; + vuint32_t B0_P0_IPFE:1; + vuint32_t B0_P0_PFLM:2; + vuint32_t B0_P0_BFE:1; + } B; + } PFCR0; + + union { /* CFLASH Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t BK1_APC:5; + vuint32_t BK1_WWSC:5; + vuint32_t BK1_RWSC:5; + vuint32_t BK1_RWWC2:1; + vuint32_t BK1_RWWC1:1; + vuint32_t:6; + vuint32_t B0_P1_BFE:1; + vuint32_t BK1_RWWC0:1; + vuint32_t:6; + vuint32_t B1_P0_BFE:1; + } B; + } PFCR1; + + union { /* cflash Access Protection Register */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t ARBM:2; + vuint32_t M7PFD:1; + vuint32_t M6PFD:1; + vuint32_t M5PFD:1; + vuint32_t M4PFD:1; + vuint32_t M3PFD:1; + vuint32_t M2PFD:1; + vuint32_t M1PFD:1; + vuint32_t M0PFD:1; + vuint32_t M7AP:2; + vuint32_t M6AP:2; + vuint32_t M5AP:2; + vuint32_t M4AP:2; + vuint32_t M3AP:2; + vuint32_t M2AP:2; + vuint32_t M1AP:2; + vuint32_t M0AP:2; + } B; + } FAPR; + + int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */ + + union { /* User Test Register 0 */ + vuint32_t R; + struct { + vuint32_t UTE:1; + vuint32_t:7; + vuint32_t DSI:8; + vuint32_t:10; + vuint32_t MRE:1; + vuint32_t MRV:1; + vuint32_t EIE:1; + vuint32_t AIS:1; + vuint32_t AIE:1; + vuint32_t AID:1; + } B; + } UT0; + + union { /* User Test Register 1 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT1; + + union { /* User Test Register 2 */ + vuint32_t R; + struct { + vuint32_t DAI:32; + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-4 */ + vuint32_t R; + struct { + vuint32_t MS:32; + } B; + } UMISR[5]; + + }; /* end of CFLASH_tag */ + +/****************************************************************************/ +/* MODULE : CRC */ +/****************************************************************************/ + struct CRC_SUB_tag { + union { + vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W; /* Data buffer in words (32 bits) */ + struct { + vuint32_t INV:1; + vuint32_t SWAP:1; + vuint32_t POLYG:1; + vuint32_t:29; + }BIT; + } CRC_CFG; /* CRC Configuration Register */ + + union { + vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W; /* Data buffer in words (32 bits) */ + } CRC_INP; /* CRC Input Register */ + + union { + vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W; /* Data buffer in words (32 bits) */ + } CRC_CSTAT; /*CRC Current Status Register */ + + union { + vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W; /* Data buffer in words (32 bits) */ + } CRC_OUTP; /* CRC Output Register */ + + }; /* end of CRC_tag */ + + struct CRC_tag { + struct CRC_SUB_tag CNTX[2]; + }; + +/****************************************************************** +| defines and macros (scope: module-local) +|-----------------------------------------------------------------*/ +/* Define instances of modules */ +#define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL) +#define ADC_1 (*(volatile struct ADC_tag *) 0xFFE04000UL) +#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL) +#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL) +#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL) +#define CTU_0 (*(volatile struct CTU_tag *) 0xFFE0C000UL) +#define CTU_1 (*(volatile struct CTU_tag *) 0xFFE10000UL) +#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL) +#define DCU (*(volatile struct DCU_tag *) 0xFFE7C000UL) +#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) +#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL) +#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL) +#define EBI (*(volatile struct EBI_tag *) 0xC3F84000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL) +#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL) +#define ETIMER_0 (*(volatile struct ETIMER_tag *) 0xFFE18000UL) +#define ETIMER_1 (*(volatile struct ETIMER_tag *) 0xFFE1C000UL) +#define FCU (*(volatile struct FCU_tag *) 0xFFE6C000UL) +#define FLEXPWM_0 (*(volatile struct FLEXPWM_tag *) 0xFFE24000UL) +#define FLEXPWM_1 (*(volatile struct FLEXPWM_tag *) 0xFFE28000UL) +#define FR (*(volatile struct FR_tag *) 0xFFFE0000UL) +#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL) +#define I2C_1 (*(volatile struct I2C_tag *) 0xFFE34000UL) +#define I2C_2 (*(volatile struct I2C_tag *) 0xFFE38000UL) +#define I2C_3 (*(volatile struct I2C_tag *) 0xFFE3C000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define LCD (*(volatile struct LCD_tag *) 0xFFE74000UL) +#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL) +#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL) +#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL) +#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL) +#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL) +#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL) +#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL) +#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL) +#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL) +#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL) +#define SAFEPORT (*(volatile struct FLEXCAN_tag *) 0xFFFE8000UL) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL) +#define SMC (*(volatile struct SMC_tag *) 0xFFE60000UL) +#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL) +#define SSD_0 (*(volatile struct SSD_tag *) 0xFFE61000UL) +#define SSD_1 (*(volatile struct SSD_tag *) 0xFFE61800UL) +#define SSD_2 (*(volatile struct SSD_tag *) 0xFFE62000UL) +#define SSD_3 (*(volatile struct SSD_tag *) 0xFFE62800UL) +#define SSD_4 (*(volatile struct SSD_tag *) 0xFFE63000UL) +#define SSD_5 (*(volatile struct SSD_tag *) 0xFFE63800UL) +#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) +#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) +#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL) +#define CRC (*(volatile struct CRC_tag *) 0xFFE68000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ifdef _JDP_H */ +/* End of file */ diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c new file mode 100644 index 000000000..22979e61b --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/hal_lld.c @@ -0,0 +1,128 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/hal_lld.c + * @brief SPC563Mxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t n; + + /* FLASH wait states and prefetching setup.*/ + CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; + CFLASH0.BIUCR2.R = 0; + CFLASH0.PFCR3.R = 0; + + /* Optimal crossbar settings. The DMA priority is placed above the CPU + priority in order to not starve I/O activities while the CPU is + executing tight loops (FLASH and SRAM slave ports only). + The SRAM is parked on the load/store port, for some unknown reason it + is defaulted on the instructions port and this kills performance.*/ + XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/ + XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + + /* Downcounter timer initialized for system tick use, TB enabled for debug + and measurements.*/ + n = SPC5_SYSCLK / CH_FREQUENCY; + asm volatile ("li %%r3, 0 \t\n" + "mtspr 284, %%r3 \t\n" /* Clear TBL register. */ + "mtspr 285, %%r3 \t\n" /* Clear TBU register. */ + "mtspr 22, %[n] \t\n" /* Init. DEC register. */ + "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ + "li %%r3, 0x4000 \t\n" /* TBEN bit. */ + "mtspr 1008, %%r3 \t\n" /* HID0 register. */ + "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ + "mtspr 340, %%r3" /* TCR register. */ + : : [n] "r" (n) : "r3"); + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); +} + +/** + * @brief SPC563 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + +#if !SPC5_NO_INIT + /* PLL activation.*/ + FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */ + FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ +#if !SPC5_CLK_BYPASS + FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ + FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV; + FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD; + FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD; + while (!FMPLL.SYNSR.B.LOCK) + ; + FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ +#endif /* !SPC5_CLK_BYPASS */ +#endif /* !SPC5_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.h b/os/hal/platforms/SPC563Mxx/hal_lld.h new file mode 100644 index 000000000..eec53fd5a --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/hal_lld.h @@ -0,0 +1,267 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/hal_lld.h + * @brief SPC563Mxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc563m.h" +#include "spc563m_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "SPC563Mxx Powertrain" + +/** + * @name ESYNCR2 register definitions + * @{ + */ +#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */ +#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */ +#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */ +#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ +/** @} */ + +/** + * @name BIUCR register definitions + * @{ + */ +#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ +#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ +#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ +#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ +#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ +#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ +#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ +#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ +#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ +#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ +#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ +#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ +#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ +#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ +#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ +#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ +#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ +#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ +#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ +#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ +#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ +#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ +#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ +#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ +#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ +#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ +#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ +#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ +#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ +#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ +#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ +#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ +#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ +#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ +#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ +#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ +#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ +#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Clock bypass. + * @note If set to @p TRUE then the PLL is not started and initialized, the + * external clock is used as-is and the other clock-related settings + * are ignored. + */ +#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__) +#define SPC5_CLK_BYPASS FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief External clock pre-divider. + * @note Must be in range 1...15. + */ +#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_CLK_PREDIV_VALUE 2 +#endif + +/** + * @brief Multiplication factor divider. + * @note Must be in range 32...96. + */ +#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__) +#define SPC5_CLK_MFD_VALUE 80 +#endif + +/** + * @brief Reduced frequency divider. + */ +#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__) +#define SPC5_CLK_RFD RFD_DIV4 +#endif + +/** + * @brief Flash buffer and prefetching settings. + * @note Please refer to the SPC563M64 reference manual about the meaning + * of the following bits, if in doubt DO NOT MODIFY IT. + * @note Do not specify the APC, WWSC, RWSC bits in this value because + * those are calculated from the system clock and ORed with this + * value. + */ +#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__) +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC563Mxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC563Mxx_MCUCONF not defined" +#endif + +#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15) +#error "invalid SPC5_CLK_PREDIV_VALUE value specified" +#endif + +#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96) +#error "invalid SPC5_CLK_MFD_VALUE value specified" +#endif + +#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \ + (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16) +#error "invalid SPC5_CLK_RFD value specified" +#endif + +/** + * @brief PLL input divider. + */ +#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1) + +/** + * @brief PLL multiplier. + */ +#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE) + +/** + * @brief PLL output clock. + */ +#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \ + SPC5_CLK_MFD_VALUE) + +#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000) +#error "VCO frequency out of the acceptable range (256...512)" +#endif + +/** + * @brief PLL output clock. + */ +#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__) +#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1))) +#else +#define SPC5_SYSCLK SPC5_XOSC_CLK +#endif + +#if (SPC5_SYSCLK > 80000000) && !SPC5_ALLOW_OVERCLOCK +#error "System clock above maximum rated frequency (80MHz)" +#endif + +/** + * @brief Flash wait states are a function of the system clock. + */ +#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1) +#elif SPC5_SYSCLK <= 40000000 +#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1) +#elif SPC5_SYSCLK <= 64000000 +#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1) +#else +#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_1) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/platform.dox b/os/hal/platforms/SPC563Mxx/platform.dox new file mode 100644 index 000000000..21401e88d --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/platform.dox @@ -0,0 +1,64 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @defgroup SPC563 SPC563Mx Drivers + * @details This section describes all the supported drivers on the + * SPC563Mx/MPC563xM platform and the implementation details + * of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup SPC563_HAL SPC563Mx Initialization Support + * @details The SPC563Mx/MPC563xM HAL support is responsible for system + * initialization. + * + * @section spc563_hal_1 Supported HW resources + * - FMPLL. + * - INTC. + * - XBAR. + * - CFLASH0. + * . + * @section spc563_hal_2 SPC563Mx HAL driver implementation features + * - FMPLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup SPC563 + */ + +/** + * @defgroup SPC563_SERIAL SPC563Mx Serial Support + * @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals + * in a buffered, interrupt driven, implementation. + * + * @section spc563_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - ESCIA. + * - ESCIB. + * . + * @section spc563_serial_2 SPC563Mx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each ESCI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each ESCI. + * . + * @ingroup SPC563 + */ diff --git a/os/hal/platforms/SPC563Mxx/platform.mk b/os/hal/platforms/SPC563Mxx/platform.mk new file mode 100644 index 000000000..5bf53c67b --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/platform.mk @@ -0,0 +1,15 @@ +# List of all the SPC563Mxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1 diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h new file mode 100644 index 000000000..b26a65de9 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h @@ -0,0 +1,131 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/spc563m_registry.h + * @brief SPC563Mxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC563M_REGISTRY_H_ +#define _SPC563M_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC563Mxx capabilities + * @{ + */ +/* DSPI attribures.*/ +#define SPC5_HAS_DSPI0 FALSE +#define SPC5_HAS_DSPI1 TRUE +#define SPC5_HAS_DSPI2 TRUE +#define SPC5_HAS_DSPI3 FALSE +#define SPC5_HAS_DSPI4 FALSE +#define SPC5_DSPI_FIFO_DEPTH 16 +#define SPC5_DSPI1_TX1_DMA_CH_ID 12 +#define SPC5_DSPI1_TX2_DMA_CH_ID 25 +#define SPC5_DSPI1_RX_DMA_CH_ID 13 +#define SPC5_DSPI2_TX1_DMA_CH_ID 14 +#define SPC5_DSPI2_TX2_DMA_CH_ID 26 +#define SPC5_DSPI2_RX_DMA_CH_ID 15 +#define SPC5_DSPI1_EOQF_HANDLER vector132 +#define SPC5_DSPI1_EOQF_NUMBER 132 +#define SPC5_DSPI1_TFFF_HANDLER vector133 +#define SPC5_DSPI1_TFFF_NUMBER 133 +#define SPC5_DSPI2_EOQF_HANDLER vector137 +#define SPC5_DSPI2_EOQF_NUMBER 137 +#define SPC5_DSPI2_TFFF_HANDLER vector138 +#define SPC5_DSPI2_TFFF_NUMBER 138 +#define SPC5_DSPI1_ENABLE_CLOCK() +#define SPC5_DSPI1_DISABLE_CLOCK() +#define SPC5_DSPI2_ENABLE_CLOCK() +#define SPC5_DSPI2_DISABLE_CLOCK() + +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA TRUE +#define SPC5_EDMA_NCHANNELS 32 +#define SPC5_EDMA_HAS_MUX FALSE + +/* eQADC attributes.*/ +#define SPC5_HAS_EQADC TRUE + +/* eSCI attributes.*/ +#define SPC5_HAS_ESCIA TRUE +#define SPC5_ESCIA_HANDLER vector146 +#define SPC5_ESCIA_NUMBER 146 + +#define SPC5_HAS_ESCIB TRUE +#define SPC5_ESCIB_HANDLER vector149 +#define SPC5_ESCIB_NUMBER 149 + +#define SPC5_HAS_ESCIC FALSE + +/* SIU attributes.*/ +#define SPC5_HAS_SIU TRUE +#define SPC5_SIU_SUPPORTS_PORTS FALSE + +/* EMIOS attributes.*/ +#define SPC5_HAS_EMIOS TRUE + +#define SPC5_EMIOS_NUM_CHANNELS 16 + +#define SPC5_EMIOS_FLAG_F0_HANDLER vector51 +#define SPC5_EMIOS_FLAG_F1_HANDLER vector52 +#define SPC5_EMIOS_FLAG_F2_HANDLER vector53 +#define SPC5_EMIOS_FLAG_F3_HANDLER vector54 +#define SPC5_EMIOS_FLAG_F4_HANDLER vector55 +#define SPC5_EMIOS_FLAG_F5_HANDLER vector56 +#define SPC5_EMIOS_FLAG_F6_HANDLER vector57 +#define SPC5_EMIOS_FLAG_F8_HANDLER vector59 +#define SPC5_EMIOS_FLAG_F9_HANDLER vector60 +#define SPC5_EMIOS_FLAG_F10_HANDLER vector61 +#define SPC5_EMIOS_FLAG_F11_HANDLER vector62 +#define SPC5_EMIOS_FLAG_F12_HANDLER vector63 +#define SPC5_EMIOS_FLAG_F13_HANDLER vector64 +#define SPC5_EMIOS_FLAG_F14_HANDLER vector65 +#define SPC5_EMIOS_FLAG_F15_HANDLER vector66 +#define SPC5_EMIOS_FLAG_F23_HANDLER vector209 +#define SPC5_EMIOS_FLAG_F0_NUMBER 51 +#define SPC5_EMIOS_FLAG_F1_NUMBER 52 +#define SPC5_EMIOS_FLAG_F2_NUMBER 53 +#define SPC5_EMIOS_FLAG_F3_NUMBER 54 +#define SPC5_EMIOS_FLAG_F4_NUMBER 55 +#define SPC5_EMIOS_FLAG_F5_NUMBER 56 +#define SPC5_EMIOS_FLAG_F6_NUMBER 57 +#define SPC5_EMIOS_FLAG_F8_NUMBER 59 +#define SPC5_EMIOS_FLAG_F9_NUMBER 60 +#define SPC5_EMIOS_FLAG_F10_NUMBER 61 +#define SPC5_EMIOS_FLAG_F11_NUMBER 62 +#define SPC5_EMIOS_FLAG_F12_NUMBER 63 +#define SPC5_EMIOS_FLAG_F13_NUMBER 64 +#define SPC5_EMIOS_FLAG_F14_NUMBER 65 +#define SPC5_EMIOS_FLAG_F15_NUMBER 66 +#define SPC5_EMIOS_FLAG_F23_NUMBER 209 + +#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \ + SPC5_EMIOS_GLOBAL_PRESCALER) +#define SPC5_EMIOS_ENABLE_CLOCK() +#define SPC5_EMIOS_DISABLE_CLOCK() +/** @} */ + +#endif /* _SPC563M_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/typedefs.h b/os/hal/platforms/SPC563Mxx/typedefs.h new file mode 100644 index 000000000..9c521fb90 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC563Mxx/xpc563m.h b/os/hal/platforms/SPC563Mxx/xpc563m.h new file mode 100644 index 000000000..8ee2b5787 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/xpc563m.h @@ -0,0 +1,4123 @@ +/**************************************************************************/ + +/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ +/* VERSION: 2.0 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC563xM. This version supports revision 1.0 and later. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 1.0 G. Emerson 31/OCT/07 Initial version. */ +/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ +/* Added ESYNCR1 ESYNCR2 SYNFMMR */ +/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ +/* 8 channels in the middle of the range */ +/* do not exist */ +/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ +/* RXIMR added */ +/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ +/* SIU - Added SIU.ISEL0-3 */ +/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ +/* MCM - Replaced ECSM with MCM */ +/* removing SWT registers as defined at */ +/* seperate memory location. PFLASH */ +/* registers pre-fixed with P*. Added PCT,*/ +/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ +/* PBRIDGE - Removed as no PBRIDGE */ +/* registers. */ +/* INTC - Updated number of PSR from */ +/* 358 to 360. */ +/* mpc5500_spr.h - Added RI to MSR and NMI*/ +/* to MSCR. */ +/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ +/* Changes to SIU.MIDR as per RM. */ +/* 1.5 May 2009 Changes to match documentation, removed*/ +/* Not released */ +/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ +/* & R. Dees */ +/* INTC - All Processor 0 regs matched to previous */ +/* version */ +/* INTC - BCR renamed to MCR to match previous */ +/* version */ +/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ +/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ +/* registers added */ +/* INTC - 512 PSR registers instead of 364 */ +/* ECSM - (Internal - mcm -> ecsm in the source files*/ +/* for generating the header file */ +/* ECSM - All bits and regs got an additional "p" in */ +/* the name in the user manual for "Platform" */ +/* -> deleted to match */ +/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ +/* MPC563xM -> deleted */ +/* ECSM - PROTECTION in the URM is one bitfield, */ +/* in mop5534 this are four: PROT1-4 -> */ +/* changed to match */ +/* EMCM - removed undocumented registers */ +/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ +/* XBAR - removed AMPR and ASGPCR registers */ +/* XBAR - removed HPE bits for nonexistant masters */ +/* EBI - added: D16_31, AD_MUX and SETA bits */ +/* EBI - Added reserved register at address 0x4. */ +/* EBI - Corrected number of chip selects in for both*/ +/* the EBI_CS and the CAL_EBI_CS */ +/* SIU - corrected number of GPDO registers and */ +/* allowed for maximum PCR registers. */ +/* SWT - add KEY bit to CR, correct WND (from WNO) */ +/* SWT - add SK register */ +/* PMC - moved bits from CFGR to Status Register (SR)*/ +/* PMC - Added SR */ +/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ +/* TORE, & TRFE to MCR. Added IBIC, OBIC, */ +/* DIVRC, IBIF, OBIF, DIVR to MSR. */ +/* changed OUTTEG to OUTTAG in OB */ +/* Change COEF to TAG in TAG register */ +/* EQADC - removed REDLCCR - not supported */ +/* FLASH - Aligned register and bit names with legacy*/ +/* 1.7 K. Odenthal 10/November/09 */ +/* SIU - changed PCR[n].PA from 3 bit to 4 bit */ +/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ +/* DECFIL - changed COEF.R and TAP.R from 16 bit to */ +/* 32 bit */ +/* 2.0 K. Odenthal 12/February/2010 */ +/* TSENS - Temperature Sensor Module added to */ +/* header file */ +/* ANSI C Compliance - Register structures have a */ +/* Bitfield Tag ('B') tag only if there is */ +/* at least one Bitfiels defined. Empty */ +/* tags like 'vuint32_t:32;' are not */ +/* allowed. */ +/* DECFIL - removed MXCR register. This register is */ +/* not supported on this part */ +/* SIU - SWT_SEL bit added in SIU DIRER register */ +/* EDMA - removed HRSL, HRSH and GPOR registers. */ +/* Those registers are not supported in */ +/* that part. */ +/* ESCI - removed LDBG and DSF bits from LCR */ +/* registers. Those bits are not supported */ +/* in that part. */ +/* Those registers are not supported in */ +/* that part. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC563M_H_ +#define _MPC563M_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { + +#endif /* + */ + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif /* + */ + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t PREDIV:3; + vuint32_t MFD:5; + vuint32_t:1; + vuint32_t RFD:3; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t:1; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + */ + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:13; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + + + */ + } B; + } SYNCR; + union { + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t LOLF:1; + vuint32_t LOC:1; + vuint32_t MODE:1; + vuint32_t PLLSEL:1; + vuint32_t PLLREF:1; + vuint32_t LOCKS:1; + vuint32_t LOCK:1; + vuint32_t LOCF:1; + vuint32_t:2; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + */ + } B; + } SYNSR; + union { + vuint32_t R; + struct { + vuint32_t EMODE:1; + vuint32_t CLKCFG:3; + vuint32_t:8; + vuint32_t EPREDIV:4; + vuint32_t:9; + vuint32_t EMFD:7; + } B; + } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:17; + vuint32_t ERFD:2; + } B; + } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ + int32_t FMPLL_reserved0[2]; + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t MODEN:1; + vuint32_t MODSEL:1; + vuint32_t MODPERIOD:13; + vuint32_t:1; + vuint32_t INCSTEP:15; + } B; + } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ + }; +/****************************************************************************/ +/* MODULE : EBI */ +/****************************************************************************/ + struct CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_BR */ + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_OR */ + }; + struct CAL_CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_CAL_BR */ + + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_CAL_OR */ + + }; + + struct EBI_tag { + union { + vuint32_t R; + struct { + vuint32_t:5; /* */ + vuint32_t SIZEEN:1; /* SIZEN */ + vuint32_t SIZE:2; /* */ + vuint32_t:8; /* */ + vuint32_t ACGE:1; /* */ + vuint32_t EXTM:1; /* */ + vuint32_t EARB:1; /* */ + vuint32_t EARP:2; /* */ + vuint32_t:4; /* */ + vuint32_t MDIS:1; /* */ + vuint32_t:3; /* */ + vuint32_t D16_31:1; /* new in MPC563xM */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t DBM:1; /* */ + } B; + } MCR; /* EBI Module Configuration Register (MCR) EBI_MCR @baseaddress + 0x00 */ + + uint32_t EBI_reserved1[1]; + + union { + vuint32_t R; + struct { + vuint32_t:30; /* */ + vuint32_t TEAF:1; /* */ + vuint32_t BMTF:1; /* */ + } B; + } TESR; /* EBI Transfer Error Status Register (TESR) EBI_TESR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t BMT:8; /* */ + vuint32_t BME:1; /* */ + vuint32_t:7; /* */ + } B; + } BMCR; /* EBI_BMCR @baseaddress + 0x0C */ + + struct CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + /* Calibration registers */ + struct CAL_CS_tag CAL_CS[4]; + + }; /* end of EBI_tag */ +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ +/* 3 flash modules implemented. */ +/* HBL and HBS not used in Bank 0 / Array 0 */ +/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ +/* Bank 1 / Array 1 or Bank 1 / Array 3 */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ + vuint32_t:4; /* Reserved */ + vuint32_t SIZE:3; /* Array Size (Read Only) */ + vuint32_t:1; /* Reserved */ + vuint32_t LAS:3; /* Low Address Space (Read Only) */ + vuint32_t:3; /* Reserved */ + vuint32_t MAS:1; /* Mid Address Space (Read Only) */ + vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* BBEPE and EPE */ + vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ + vuint32_t:2; /* Reserved */ + vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ + vuint32_t DONE:1; /* Status (Read Only) */ + vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ + vuint32_t:4; /* Reserved *//* RSD PEG STOP RSVD */ + vuint32_t PGM:1; /* Program (Read/Write) */ + vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ + vuint32_t ERS:1; /* Erase (Read/Write) */ + vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ + vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ + } B; + } MCR; + + union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SLOCK:1; /*SLK *//* Shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t MLOCK:2; /*MLK *//* Mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LLOCK:8; /*LLK *//* Low address space block lock (Read/Write) */ + } B; + } LMLR; /*LML */ + + union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ + vuint32_t R; + struct { + vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ + vuint32_t:27; /* Reserved */ + vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ + } B; + } HLR; /*HBL */ + + union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ + vuint32_t R; + struct { + vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SSLOCK:1; /*SSLK *//* Secondary shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t SMLOCK:2; /*SMK *//* Secondary mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t SLLOCK:8; /*SLK *//* Secondary low address space block lock (Read/Write) */ + } B; + } SLMLR; /*SLL */ + + union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t MSEL:2; /*MSL *//* Mid address space block select (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LSEL:8; /*LSL *//* Low address space block select (Read/Write) */ + } B; + } LMSR; /*LMS */ + + union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t HBSEL:4; /*HSL *//* High address space block select (Read/Write) */ + } B; + } HSR; /*HBS */ + + union { /* Address Register (ADR)@baseaddress + 0x18 */ + vuint32_t R; + struct { + vuint32_t SAD:1; /* Shadow address (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t ADDR:18; /*AD *//* Address 20-3 (Read Only) */ + vuint32_t:3; /* Reserved */ + } B; + } AR; /*ADR */ + + union { /* @baseaddress + 0x1C */ + vuint32_t R; + struct { + vuint32_t:7; /* Reserved */ + vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ + vuint32_t:4; /* Reserved */ + vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ + vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ + vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ + vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ + vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ + vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ + vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t DPFEN:1; /*DPFE *//* Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t IPFEN:1; /*IPFE *//* Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ + vuint32_t BFEN:1; /*BFE *//* Buffer Enable (Read/Write) */ + } B; + } BIUCR; /*PFCR1 */ + + union { /* @baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t:24; /* Reserved */ + vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ + vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ + vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ + vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ + } B; + } BIUAPR; /*PFAPR */ + + union { /* @baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ + vuint32_t:30; /* Reserved */ + } B; + } BIUCR2; + + union { /* @baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:25; /* Reserved */ + vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ + vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ + } B; + } PFCR3; + + int32_t FLASH_reserverd_89[4]; + + union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ + vuint32_t R; + struct { + vuint32_t UTE:1; /* User test enable (Read/Clear) */ + vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ + vuint32_t:6; /* Reserved */ + vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ + vuint32_t:9; /* Reserved */ + vuint32_t:1; /* Reserved (Read/Write) */ + vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ + vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ + vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ + vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ + vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ + vuint32_t AID:1; /* Array Integrity Done (Read Only) */ + } B; + } UT0; + + union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT1; + + union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ + vuint32_t R; + struct { + vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ + } B; + } UMISR[5]; + + }; /* end of FLASH_tag */ +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + union { + vuint32_t R; + struct { + vuint32_t S_F:1; /* Identifies the Manufacturer S/F */ + vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) Flash Size 1 */ + vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) Flash Size 1 */ + vuint32_t TEMP_RANGE:2; /* Define maximum operating range Temp Range */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t MAX_FREQ:2; /* Define maximum device speed Max Freq */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V Supply */ + vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product Part Number */ + vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ + vuint32_t:2; /* Reserved for future enhancements */ + vuint32_t EE:1; /* Indicates if Data Flash is present */ + vuint32_t:3; /* Reserved for future enhancements */ + vuint32_t FR:1; /* Indicates if Data FlexRay is present */ + } B; + } MIDR2; /* MCU ID Register 2 SIU_MIDR2 @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ + vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ + vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ + } B; + } MIDR; /* MCU ID Register (MIDR) SIU_MIDR @baseaddress + 0x8 */ + + union { + vuint32_t R; + } TST; /* SIU Test Register (SIU_TST) SIU_TST @baseaddress + 0xC */ + + union { + vuint32_t R; + struct { + vuint32_t PORS:1; /* Power-On Reset Status */ + vuint32_t ERS:1; /* External Reset Status */ + vuint32_t LLRS:1; /* Loss of Lock Reset Status */ + vuint32_t LCRS:1; /* Loss of Clock Reset Status */ + vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ + vuint32_t CRS:1; /* Checkstop Reset Status */ + vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SSRS:1; /* Software System Reset Status */ + vuint32_t SERF:1; /* Software External Reset Flag */ + vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ + vuint32_t:11; /* */ + vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ + vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ + vuint32_t RGF:1; /* RESET Glitch Flag */ + } B; + } RSR; /* Reset Status Register (SIU_RSR) SIU_RSR @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t SSR:1; /* Software System Reset */ + vuint32_t SER:1; /* Software External Reset */ + vuint32_t:14; /* */ + vuint32_t CRE:1; /* Checkstop Reset Enable */ + vuint32_t:15; /* */ + } B; + } SRCR; /* System Reset Control Register (SRCR) SIU_SRCR @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t EIF15:1; /* External Interrupt Request Flag x */ + vuint32_t EIF14:1; /* External Interrupt Request Flag x */ + vuint32_t EIF13:1; /* External Interrupt Request Flag x */ + vuint32_t EIF12:1; /* External Interrupt Request Flag x */ + vuint32_t EIF11:1; /* External Interrupt Request Flag x */ + vuint32_t EIF10:1; /* External Interrupt Request Flag x */ + vuint32_t EIF9:1; /* External Interrupt Request Flag x */ + vuint32_t EIF8:1; /* External Interrupt Request Flag x */ + vuint32_t:3; /* (reserved in MPC563xM) */ + vuint32_t EIF4:1; /* External Interrupt Request Flag x */ + vuint32_t EIF3:1; /* External Interrupt Request Flag x */ + vuint32_t:2; /* (reserved in MPC563xM) */ + vuint32_t EIF0:1; /* External Interrupt Request Flag x */ + } B; + } EISR; /* SIU External Interrupt Status Register (EISR) SIU_EISR @baseaddress + 0x18 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT_SEL:1; + vuint32_t:7; + vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ + } B; + } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) SIU_DIRER @baseaddress + 0x1C */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ + } B; + } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) SIU_DIRSR @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t OVF15:1; /* Overrun Flag x */ + vuint32_t OVF14:1; /* Overrun Flag x */ + vuint32_t OVF13:1; /* Overrun Flag x */ + vuint32_t OVF12:1; /* Overrun Flag x */ + vuint32_t OVF11:1; /* Overrun Flag x */ + vuint32_t OVF10:1; /* Overrun Flag x */ + vuint32_t OVF9:1; /* Overrun Flag x */ + vuint32_t OVF8:1; /* Overrun Flag x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t OVF4:1; /* Overrun Flag x */ + vuint32_t OVF3:1; /* Overrun Flag x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t OVF0:1; /* Overrun Flag x */ + } B; + } OSR; /* Overrun Status Register (OSR) SIU_OSR @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t ORE15:1; /* Overrun Request Enable x */ + vuint32_t ORE14:1; /* Overrun Request Enable x */ + vuint32_t ORE13:1; /* Overrun Request Enable x */ + vuint32_t ORE12:1; /* Overrun Request Enable x */ + vuint32_t ORE11:1; /* Overrun Request Enable x */ + vuint32_t ORE10:1; /* Overrun Request Enable x */ + vuint32_t ORE9:1; /* Overrun Request Enable x */ + vuint32_t ORE8:1; /* Overrun Request Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t ORE4:1; /* Overrun Request Enable x */ + vuint32_t ORE3:1; /* Overrun Request Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t ORE0:1; /* Overrun Request Enable x */ + } B; + } ORER; /* Overrun Request Enable Register (ORER) SIU_ORER @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ + vuint32_t:15; /* reserved in MPC563xM */ + vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) SIU_IREER @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ + vuint32_t Reserverd:15; /* */ + vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) SIU_IFEER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DFL:4; /* Digital Filter Length */ + } B; + } IDFR; /* External IRQ Digital Filter Register (IDFR) SIU_IDFR @baseaddress + 0x40 */ + + int32_t SIU_reserverd_153[3]; + + union { + vuint16_t R; + struct { + vuint16_t:2; /* */ + vuint16_t PA:4; /* */ + vuint16_t OBE:1; /* */ + vuint16_t IBE:1; /* */ + vuint16_t DSC:2; /* */ + vuint16_t ODE:1; /* */ + vuint16_t HYS:1; /* */ + vuint16_t SRC:2; /* */ + vuint16_t WPE:1; /* */ + vuint16_t WPS:1; /* */ + } B; + } PCR[512]; /* Pad Configuration Register (PCR) SIU_PCR @baseaddress + 0x600 */ + + int32_t SIU_reserverd_164[112]; + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDO:1; /* */ + } B; + } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) SIU_GDPO @baseaddress + 0x800 */ + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDI:1; /* */ + } B; + } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) SIU_GDPI @baseaddress + 0x900 */ + + union { + vuint32_t R; + struct { + vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ + vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ + vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ + vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ + vuint32_t:20; /* */ + } B; + } ETISR; /* eQADC Trigger Input Select Register (ETISR) SIU_ETISR @baseaddress + 0x904 */ + + union { + vuint32_t R; + struct { + vuint32_t ESEL15:2; /* External IRQ Input Select x */ + vuint32_t ESEL14:2; /* External IRQ Input Select x */ + vuint32_t ESEL13:2; /* External IRQ Input Select x */ + vuint32_t ESEL12:2; /* External IRQ Input Select x */ + vuint32_t ESEL11:2; /* External IRQ Input Select x */ + vuint32_t ESEL10:2; /* External IRQ Input Select x */ + vuint32_t ESEL9:2; /* External IRQ Input Select x */ + vuint32_t ESEL8:2; /* External IRQ Input Select x */ + vuint32_t ESEL7:2; /* External IRQ Input Select x */ + vuint32_t ESEL6:2; /* External IRQ Input Select x */ + vuint32_t ESEL5:2; /* External IRQ Input Select x */ + vuint32_t ESEL4:2; /* External IRQ Input Select x */ + vuint32_t ESEL3:2; /* External IRQ Input Select x */ + vuint32_t ESEL2:2; /* External IRQ Input Select x */ + vuint32_t ESEL1:2; /* External IRQ Input Select x */ + vuint32_t ESEL0:2; /* External IRQ Input Select x */ + } B; + } EIISR; /* External IRQ Input Select Register (EIISR) SIU_EIISR @baseaddress + 0x908 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* reserved in MPC563xM */ + vuint32_t SINSELB:2; /* DSPI_B Data Input Select SIN-SELB */ + vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select SS-SELB */ + vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select SCK-SELB */ + vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select TRIG-SELB */ + vuint32_t SINSELC:2; /* DSPI_C Data Input Select SIN-SELC */ + vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select SSSELC */ + vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select SCK-SELC */ + vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select TRIG-SELC */ + vuint32_t:8; /* reserved in MPC563xM */ + } B; + } DISR; /* DSPI Input Select Register (DISR) SIU_DISR @baseaddress + 0x90c */ + + union { + vuint32_t R; + struct { + vuint32_t:2; /* */ + vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection eTSEL5 */ + vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection eTSEL4 */ + vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection eTSEL3 */ + vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection eTSEL2 */ + vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection eTSEL1 */ + vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection eTSEL0 */ + } B; + } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) SIU_ISEL3 @baseaddress + 0x920 */ + + int32_t SIU_reserverd_214[4]; + + union { + vuint32_t R; + struct { + vuint32_t:11; /* */ + vuint32_t ESEL5:1; /* eSEL5 */ + vuint32_t:3; /* */ + vuint32_t ESEL4:1; /* eSEL4 */ + vuint32_t:3; /* */ + vuint32_t ESEL3:1; /* eSEL3 */ + vuint32_t:3; /* */ + vuint32_t ESEL2:1; /* eSEL2 */ + vuint32_t:3; /* */ + vuint32_t ESEL1:1; /* eSEL1 */ + vuint32_t:3; /* */ + vuint32_t ESEL0:1; /* eSEL0 */ + } B; + } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) SIU_ISEL8 @baseaddress + 0x924 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; /* */ + vuint32_t ETSEL0A:5; /* eTSEL0A */ + } B; + } ISEL9; /* MUX Select Register 9(ISEL9) SIU_ISEL9 @baseaddress + 0x980 */ + + int32_t SIU_reserverd_230[22]; + + union { + vuint32_t R; + struct { + vuint32_t:14; /* */ + vuint32_t MATCH:1; /* Compare Register Match */ + vuint32_t DISNEX:1; /* Disable Nexus */ + vuint32_t:14; /* */ + vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ + vuint32_t:1; /* */ + } B; + } CCR; /* Chip Configuration Register (CCR) SIU_CCR @baseaddress + 0x984 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ + vuint32_t EBTS:1; /* External Bus Tap Select */ + vuint32_t:1; /* */ + vuint32_t EBDF:2; /* External Bus Division Factor */ + } B; + } ECCR; /* External Clock Control Register (ECCR) SIU_ECCR @baseaddress + 0x988 */ + + union { + vuint32_t R; + } CARH; /* Compare A High Register (CARH) SIU_CMPAH @baseaddress + 0x98C */ + + union { + vuint32_t R; + } CARL; /* Compare A Low Register (CARL) SIU_CMPAL @baseaddress + 0x990 */ + + union { + vuint32_t R; + } CBRH; /* Compare B High Register (CBRH) SIU_CMPBH @baseaddress + 0x994 */ + + union { + vuint32_t R; + } CBRL; /* Compare B Low Register (CBRL) SIU_CMPBL @baseaddress + 0x9A0 */ + + int32_t SIU_reserverd_250[2]; + + union { + vuint32_t R; + struct { + vuint32_t:27; /* Reserved */ + vuint32_t BYPASS:1; /* Bypass bit BY-PASS */ + vuint32_t SYSCLKDIV:2; /* System Clock Divide SYS-CLKDIV */ + vuint32_t:2; /* Reserved */ + } B; + } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) SIU_SYSDIV @baseaddress + 0x9A4 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ + vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ + vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ + vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSSTP:1; /* Stop mode request */ + vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ + vuint32_t:1; /* Reserved */ + vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ + vuint32_t:1; /* Reserved */ + vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ + vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ + vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ + } B; + } HLT; /* Halt Register (HLT) (new in MPC563xM) SIU_HLT @baseaddress + 0x9A8 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ + vuint32_t:1; /* Reserved */ + vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ + } B; + } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) SIU_HLTACK @baseaddress + 0x9ac */ + + int32_t SIU_reserved3[21]; + + }; /* end of SIU_tag */ +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t DOZEEN:1; /* new in MPC563xM */ + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register EMIOSMCR */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register EMIOSGFLAG */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register EMIOSOUDIS */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ + } B; + } UCDIS; /* Disable Channel (EMIOSUCDIS) EMIOSUCDIS (new in MPC563xM) @baseaddress + 0x0C */ + + int32_t EMIOS_reserverd_30[4]; + + struct { + union { + vuint32_t R; /* Channel A Data Register */ + } CADR; /* EMIOSA */ + + union { + vuint32_t R; /* Channel B Data Register */ + } CBDR; /* EMIOSB */ + + union { + vuint32_t R; /* Channel Counter Register */ + } CCNTR; /* EMIOSCNT */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPREN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register EMIOSC */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register EMIOSS */ + + union { + vuint32_t R; /* Alternate Channel A Data Register */ + } ALTA; /* new in MPC563xM EMIOSALTA */ + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; /* end of EMIOS_tag */ +/****************************************************************************/ +/* MODULE : ETPU */ +/****************************************************************************/ + struct ETPU_tag { /* offset 0x0000 */ + union { /* eTPU module configuration register@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t GEC:1; /* Global Exception Clear */ + vuint32_t SDMERR:1; /* */ + vuint32_t WDTOA:1; /* */ + vuint32_t WDTOB:1; /* */ + vuint32_t MGE1:1; /* MGEA */ + vuint32_t MGE2:1; /* MGEB */ + vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. ILFFA */ + vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. ILFFB */ + vuint32_t SCMERR:1; /* . */ + vuint32_t:2; /* */ + vuint32_t SCMSIZE:5; /* Shared Code Memory size */ + vuint32_t:4; /* */ + vuint32_t SCMMISC:1; /* SCM MISC Flag */ + vuint32_t SCMMISF:1; /* SCM MISC Flag */ + vuint32_t SCMMISEN:1; /* SCM MISC Enable */ + vuint32_t:2; /* */ + vuint32_t VIS:1; /* SCM Visability */ + vuint32_t:5; /* */ + vuint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; /* ETPU_MCR */ + + /* offset 0x0004 */ + union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t STS:1; /* Start Status bit */ + vuint32_t CTBASE:5; /* Channel Transfer Base */ + vuint32_t PBASE:10; /* Parameter Buffer Base Address PBBASE */ + vuint32_t PWIDTH:1; /* Parameter Width */ + vuint32_t PARAM0:7; /* Channel Parameter 0 PARM0 */ + vuint32_t WR:1; /* */ + vuint32_t PARAM1:7; /* Channel Parameter 1 PARM1 */ + } B; + } CDCR; /*ETPU_CDCR */ + + vuint32_t ETPU_reserved_0; + + /* offset 0x000C */ + union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ + vuint32_t R; + struct { + vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. EMISCCMP */ + } B; + } MISCCMPR /*ETPU_MISCCMPR */ ; + + /* offset 0x0010 */ + union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ + } B; + } SCMOFFDATAR; /*ETPU_SCMOFFDATAR */ + + /* offset 0x0014 */ + union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t FEND:1; /* Force END */ + vuint32_t MDIS:1; /* Low power Stop */ + vuint32_t:1; /* */ + vuint32_t STF:1; /* Stop Flag */ + vuint32_t:4; /* */ + vuint32_t HLTF:1; /* Halt Mode Flag */ + vuint32_t:3; /* */ + vuint32_t FCSS:1; + vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + vuint32_t CDFC:2; /* */ + vuint32_t:1; /* */ + vuint32_t ERBA:5; /* */ + vuint32_t SPPDIS:1; /* */ + vuint32_t:2; /* */ + vuint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; /*ETPU_ECR */ + + vuint32_t ETPU_reserved_1[2]; + + /* offset 0x0020 */ + union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + vuint32_t AM:2; /* Angle Mode */ + vuint32_t:3; /* */ + vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ + vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + vuint32_t TCR1CS:1; /* */ + vuint32_t:5; /* */ + vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; /*ETPU_TBCR */ + + /* offset 0x0024 */ + union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ + } B; + } TB1R_A; /*ETPU_TB1R */ + + /* offset 0x0028 */ + union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ + } B; + } TB2R_A; /*ETPU_TB2R */ + + /* offset 0x002C */ + union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ + vuint32_t R; + struct { + vuint32_t REN1:1; /* Resource Enable TCR1 */ + vuint32_t RSC1:1; /* Resource Control TCR1 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID1:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV1:4; /* Resource Server Slot */ + vuint32_t REN2:1; /* Resource Enable TCR2 */ + vuint32_t RSC2:1; /* Resource Control TCR2 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID2:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; /*ETPU_REDCR */ + + vuint32_t ETPU_reserved_2[12]; + + /* offset 0x0060 */ + union { /* ETPU1 WDTR Register */ + vuint32_t R; + struct { + vuint32_t WDM:2; + vuint32_t:14; + vuint32_t WDCNT:16; + } B; + } WDTR_A; + + vuint32_t ETPU1_reserved_3; + + /* offset 0x0068 */ + union { /* ETPU1 IDLE Register */ + vuint32_t R; + struct { + vuint32_t IDLE_CNT:31; + vuint32_t ICLR:1; + } B; + } IDLE_A; + + vuint32_t ETPU_reserved_4[101]; + + /* offset 0x0200 */ + union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ + vuint32_t R; + struct { + vuint32_t CIS31:1; /* Channel 31 Interrut Status */ + vuint32_t CIS30:1; /* Channel 30 Interrut Status */ + vuint32_t CIS29:1; /* Channel 29 Interrut Status */ + vuint32_t CIS28:1; /* Channel 28 Interrut Status */ + vuint32_t CIS27:1; /* Channel 27 Interrut Status */ + vuint32_t CIS26:1; /* Channel 26 Interrut Status */ + vuint32_t CIS25:1; /* Channel 25 Interrut Status */ + vuint32_t CIS24:1; /* Channel 24 Interrut Status */ + vuint32_t CIS23:1; /* Channel 23 Interrut Status */ + vuint32_t CIS22:1; /* Channel 22 Interrut Status */ + vuint32_t CIS21:1; /* Channel 21 Interrut Status */ + vuint32_t CIS20:1; /* Channel 20 Interrut Status */ + vuint32_t CIS19:1; /* Channel 19 Interrut Status */ + vuint32_t CIS18:1; /* Channel 18 Interrut Status */ + vuint32_t CIS17:1; /* Channel 17 Interrut Status */ + vuint32_t CIS16:1; /* Channel 16 Interrut Status */ + vuint32_t CIS15:1; /* Channel 15 Interrut Status */ + vuint32_t CIS14:1; /* Channel 14 Interrut Status */ + vuint32_t CIS13:1; /* Channel 13 Interrut Status */ + vuint32_t CIS12:1; /* Channel 12 Interrut Status */ + vuint32_t CIS11:1; /* Channel 11 Interrut Status */ + vuint32_t CIS10:1; /* Channel 10 Interrut Status */ + vuint32_t CIS9:1; /* Channel 9 Interrut Status */ + vuint32_t CIS8:1; /* Channel 8 Interrut Status */ + vuint32_t CIS7:1; /* Channel 7 Interrut Status */ + vuint32_t CIS6:1; /* Channel 6 Interrut Status */ + vuint32_t CIS5:1; /* Channel 5 Interrut Status */ + vuint32_t CIS4:1; /* Channel 4 Interrut Status */ + vuint32_t CIS3:1; /* Channel 3 Interrut Status */ + vuint32_t CIS2:1; /* Channel 2 Interrut Status */ + vuint32_t CIS1:1; /* Channel 1 Interrut Status */ + vuint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; /* ETPU_CISR */ + + int32_t ETPU_reserved_5[3]; + + /* offset 0x0210 */ + union { /* @baseaddress + 0x210 */ + vuint32_t R; + struct { + vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; /* ETPU_CDTRSR */ + + int32_t ETPU_reserved_6[3]; + + /* offset 0x0220 */ + union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ + vuint32_t R; + struct { + vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; /* ETPU_CIOSR */ + + int32_t ETPU_reserved_7[3]; + + /* offset 0x0230 */ + union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ + vuint32_t R; + struct { + vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; /* ETPU_CDTROSR */ + + int32_t ETPU_reserved_8[3]; + + /* offset 0x0240 */ + union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ + vuint32_t R; + struct { + vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ + vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ + vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ + vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ + vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ + vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ + vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ + vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ + vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ + vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ + vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ + vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ + vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ + vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ + vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ + vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ + vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ + vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ + vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ + vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ + vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ + vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ + vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ + vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ + vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ + vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ + vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ + vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ + vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ + vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ + vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ + vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; /* ETPU_CIER */ + + int32_t ETPU_reserved_9[3]; + + /* offset 0x0250 */ + union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ + vuint32_t R; + struct { + vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; /* ETPU_CDTRER */ + + int32_t ETPU_reserved_10[3]; + + /* offset 0x0260 */ + union { /* ETPUWDSR - eTPU Watchdog Status Register */ + vuint32_t R; + struct { + vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } WDSR_A; + + int32_t ETPU_reserved_11[7]; + + /* offset 0x0280 */ + union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ + vuint32_t R; + struct { + vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CPSSR_A; /* ETPU_CPSSR */ + + int32_t ETPU_reserved_12[3]; + + /* offset 0x0290 */ + union { /* ETPUCSSR - eTPU Channel Service Status Register */ + vuint32_t R; + struct { + vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CSSR_A; /* ETPU_CSSR */ + + int32_t ETPU_reserved_13[3]; + int32_t ETPU_reserved_14[88]; + +/***************************** Channels ********************************/ +/* Note not all devices implement all channels or even 2 engines */ +/* Each eTPU engine can implement 64 channels, however most devcies */ +/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ +/* engines per instantiation */ +/***********************************************************************/ + + struct { + union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ + vuint32_t R; + struct { + vuint32_t CIE:1; /* Channel Interruput Enable */ + vuint32_t DTRE:1; /* Data Transfer Request Enable */ + vuint32_t CPR:2; /* Channel Priority */ + vuint32_t:2; /* */ + vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ + vuint32_t ETCS:1; /* Entry Table Condition Select */ + vuint32_t:3; /* */ + vuint32_t CFS:5; /* Channel Function Select */ + vuint32_t ODIS:1; /* Output disable */ + vuint32_t OPOL:1; /* output polarity */ + vuint32_t:3; /* */ + vuint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; /* ETPU_CnCR */ + + union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ + vuint32_t R; + struct { + vuint32_t CIS:1; /* Channel Interruput Status */ + vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ + vuint32_t:6; /* */ + vuint32_t DTRS:1; /* Data Transfer Status */ + vuint32_t DTROS:1; /* Data Transfer Overflow Status */ + vuint32_t:6; /* */ + vuint32_t IPS:1; /* Input Pin State */ + vuint32_t OPS:1; /* Output Pin State */ + vuint32_t OBE:1; /* Output Pin State */ + vuint32_t:11; /* */ + vuint32_t FM1:1; /* Function mode */ + vuint32_t FM0:1; /* Function mode */ + } B; + } SCR; /* ETPU_CnSCR */ + + union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ + vuint32_t R; + struct { + vuint32_t:29; /* Host Service Request */ + vuint32_t HSR:3; /* */ + } B; + } HSRR; /* ETPU_CnHSRR */ + int32_t ETPU_reserved_18; + + } CHAN[127]; + /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ + }; /* end of ETPU_tag */ +/****************************************************************************/ +/* MODULE : XBAR */ +/****************************************************************************/ + struct XBAR_tag { + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ + + int32_t XBAR_reserverd_35[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ + + int32_t XBAR_reserverd_71[59]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ + + int32_t XBAR_reserverd_105[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ + + int32_t XBAR_reserverd_141[59]; + +/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ + + int32_t XBAR_reserverd_211[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ + + int32_t XBAR_reserverd_245[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ + + int32_t XBAR_reserverd_281[59]; + + /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ + + int32_t XBAR_reserverd_351[64]; + + /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ + + int32_t XBAR_reserverd_421[64]; + + /* Slave Port 6 not implemented @baseaddress + 0x610 */ + + int32_t XBAR_reserverd_491[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ + + int32_t XBAR_reserverd_525[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ + + int32_t XBAR_reserverd_561[59]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ + + int32_t XBAR_reserverd_564[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ + + int32_t XBAR_reserverd_567[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ + + int32_t XBAR_reserverd_570[63]; + + /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ + + int32_t XBAR_reserverd_573[64]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ + + int32_t XBAR_reserverd_576[64]; + + /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ + + int32_t XBAR_reserverd_579[64]; + + /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ + + int32_t XBAR_reserverd_582[64]; + + /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ + + }; /* end of XBAR_tag */ +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ + uint32_t ecsm_reserved1[16]; + + uint8_t ecsm_reserved3[3]; /* base + 0x40 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t ERNCR:1; /* EPRNCR */ + vuint8_t EFNCR:1; /* EPFNCR */ + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t ecsm_reserved4[3]; /* base + 0x44 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t RNCE:1; /* PRNCE */ + vuint8_t FNCE:1; /* PFNCE */ + } B; + } ESR; /* ECC Status Register */ + + /* EEGR don't exist in MPC563xM */ + uint32_t ecsm_reserved4a[2]; + + union { + vuint32_t R; + struct { + vuint32_t FEAR:32; /* PFEAR */ + } B; + } FEAR; /* Flash ECC Address Register PFEAR - 0x50 */ + + uint16_t ecsm_reserved4b; + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; /* PFEMR */ + } B; + } FEMR; /* Flash ECC Master Register PFEMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } FEAT; /* Flash ECC Attributes Register PFEAT */ + + union { + vuint32_t R; + struct { + vuint32_t FEDH:32; /* PFEDR */ + } B; + } FEDRH; /* Flash ECC Data High Register PFEDRH */ + + union { + vuint32_t R; + struct { + vuint32_t FEDL:32; /* PFEDR */ + } B; + } FEDRL; /* Flash ECC Data Low Register PFEDRL */ + + union { + vuint32_t R; + struct { + vuint32_t REAR:32; /* PREAR */ + } B; + } REAR; /* RAM ECC Address PREAR */ + + uint8_t ecsm_reserved5; + + union { + vuint8_t R; + struct { + vuint8_t PRESR:8; + } B; + } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; /* PREMR */ + } B; + } REMR; /* RAM ECC Master PREMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } REAT; /* RAM ECC Attributes Register PREAT */ + + union { + vuint32_t R; + struct { + vuint32_t REDH:32; /* PREDR */ + } B; + } REDRH; /* RAM ECC Data High Register PREDRH */ + + union { + vuint32_t R; + struct { + vuint32_t REDL:32; /* PREDR */ + } B; + } REDRL; /* RAMECC Data Low Register PREDRL */ + + }; +/****************************************************************************/ +/* MODULE : EDMA */ +/****************************************************************************/ + struct EDMA_tag { + union { + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ + vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ + vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ + vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ + vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ + vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ + vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ + vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ + vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + vuint32_t EDBG:1; /* Enable Debug */ + vuint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } CR; /* DMA Control Register DMACR @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t VLD:1; /* Logical OR of all DMAERRH */ + + vuint32_t:14; /* Reserved */ + vuint32_t ECX:1; /* (new in MPC563xM) */ + vuint32_t GPE:1; /* Group Priority Error */ + vuint32_t CPE:1; /* Channel Priority Error */ + vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ + vuint32_t SAE:1; /* Source Address Error 0 */ + vuint32_t SOE:1; /* Source Offset Error */ + vuint32_t DAE:1; /* Destination Address Error */ + vuint32_t DOE:1; /* Destination Offset Error */ + vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ + vuint32_t SBE:1; /* Source Bus Error */ + vuint32_t DBE:1; /* Destination Bus Error */ + + } B; + } ESR; /* DMAES Error Status Register */ + + uint32_t edma_reserved_erqrh; + + union { + vuint32_t R; + struct { + vuint32_t ERQ31:1; + vuint32_t ERQ30:1; + vuint32_t ERQ29:1; + vuint32_t ERQ28:1; + vuint32_t ERQ27:1; + vuint32_t ERQ26:1; + vuint32_t ERQ25:1; + vuint32_t ERQ24:1; + vuint32_t ERQ23:1; + vuint32_t ERQ22:1; + vuint32_t ERQ21:1; + vuint32_t ERQ20:1; + vuint32_t ERQ19:1; + vuint32_t ERQ18:1; + vuint32_t ERQ17:1; + vuint32_t ERQ16:1; + vuint32_t ERQ15:1; + vuint32_t ERQ14:1; + vuint32_t ERQ13:1; + vuint32_t ERQ12:1; + vuint32_t ERQ11:1; + vuint32_t ERQ10:1; + vuint32_t ERQ09:1; + vuint32_t ERQ08:1; + vuint32_t ERQ07:1; + vuint32_t ERQ06:1; + vuint32_t ERQ05:1; + vuint32_t ERQ04:1; + vuint32_t ERQ03:1; + vuint32_t ERQ02:1; + vuint32_t ERQ01:1; + vuint32_t ERQ00:1; + } B; + } ERQRL; /* DMAERQL ,DMA Enable Request Register Low */ + + uint32_t edma_reserved_eeirh; + + union { + vuint32_t R; + struct { + vuint32_t EEI31:1; + vuint32_t EEI30:1; + vuint32_t EEI29:1; + vuint32_t EEI28:1; + vuint32_t EEI27:1; + vuint32_t EEI26:1; + vuint32_t EEI25:1; + vuint32_t EEI24:1; + vuint32_t EEI23:1; + vuint32_t EEI22:1; + vuint32_t EEI21:1; + vuint32_t EEI20:1; + vuint32_t EEI19:1; + vuint32_t EEI18:1; + vuint32_t EEI17:1; + vuint32_t EEI16:1; + vuint32_t EEI15:1; + vuint32_t EEI14:1; + vuint32_t EEI13:1; + vuint32_t EEI12:1; + vuint32_t EEI11:1; + vuint32_t EEI10:1; + vuint32_t EEI09:1; + vuint32_t EEI08:1; + vuint32_t EEI07:1; + vuint32_t EEI06:1; + vuint32_t EEI05:1; + vuint32_t EEI04:1; + vuint32_t EEI03:1; + vuint32_t EEI02:1; + vuint32_t EEI01:1; + vuint32_t EEI00:1; + } B; + } EEIRL; /* DMAEEIL , DMA Enable Error Interrupt Register Low */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SERQ:7 */ + } SERQR; /* DMASERQ , DMA Set Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERQ:7 */ + } CERQR; /* DMACERQ , DMA Clear Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SEEI:7 */ + } SEEIR; /* DMASEEI , DMA Set Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CEEI:7 */ + } CEEIR; /* DMACEEI , DMA Clear Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CINT:7 */ + } CIRQR; /* DMACINT , DMA Clear Interrupt Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERR:7 */ + } CER; /* DMACERR , DMA Clear error Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SSRT:7 */ + } SSBR; /* DMASSRT , Set Start Bit Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CDNE:7 */ + } CDSBR; /* DMACDNE , Clear Done Status Bit Register */ + + uint32_t edma_reserved_irqrh; + + union { + vuint32_t R; + struct { + vuint32_t INT31:1; + vuint32_t INT30:1; + vuint32_t INT29:1; + vuint32_t INT28:1; + vuint32_t INT27:1; + vuint32_t INT26:1; + vuint32_t INT25:1; + vuint32_t INT24:1; + vuint32_t INT23:1; + vuint32_t INT22:1; + vuint32_t INT21:1; + vuint32_t INT20:1; + vuint32_t INT19:1; + vuint32_t INT18:1; + vuint32_t INT17:1; + vuint32_t INT16:1; + vuint32_t INT15:1; + vuint32_t INT14:1; + vuint32_t INT13:1; + vuint32_t INT12:1; + vuint32_t INT11:1; + vuint32_t INT10:1; + vuint32_t INT09:1; + vuint32_t INT08:1; + vuint32_t INT07:1; + vuint32_t INT06:1; + vuint32_t INT05:1; + vuint32_t INT04:1; + vuint32_t INT03:1; + vuint32_t INT02:1; + vuint32_t INT01:1; + vuint32_t INT00:1; + } B; + } IRQRL; /* DMAINTL , DMA Interrupt Request Low */ + + uint32_t edma_reserved_erh; + + union { + vuint32_t R; + struct { + vuint32_t ERR31:1; + vuint32_t ERR30:1; + vuint32_t ERR29:1; + vuint32_t ERR28:1; + vuint32_t ERR27:1; + vuint32_t ERR26:1; + vuint32_t ERR25:1; + vuint32_t ERR24:1; + vuint32_t ERR23:1; + vuint32_t ERR22:1; + vuint32_t ERR21:1; + vuint32_t ERR20:1; + vuint32_t ERR19:1; + vuint32_t ERR18:1; + vuint32_t ERR17:1; + vuint32_t ERR16:1; + vuint32_t ERR15:1; + vuint32_t ERR14:1; + vuint32_t ERR13:1; + vuint32_t ERR12:1; + vuint32_t ERR11:1; + vuint32_t ERR10:1; + vuint32_t ERR09:1; + vuint32_t ERR08:1; + vuint32_t ERR07:1; + vuint32_t ERR06:1; + vuint32_t ERR05:1; + vuint32_t ERR04:1; + vuint32_t ERR03:1; + vuint32_t ERR02:1; + vuint32_t ERR01:1; + vuint32_t ERR00:1; + } B; + } ERL; /* DMAERRL , DMA Error Low */ + + int32_t edma_reserverd_hrsh[1]; + + int32_t edma_reserverd_hrsl[1]; + + int32_t edma_reserverd_gpor[1]; + + int32_t EDMA_reserverd_223[49]; + + union { + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[64]; /* DCHPRI [32] , Channel n Priority */ + + uint32_t edma_reserved2[944]; + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + + struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITER:15; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ + vuint16_t BITER:15; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + + struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ + + struct tcd_alt1_t { + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITERLINKCH:6; + vuint16_t CITER:9; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ + vuint16_t BITERLINKCH:6; + vuint16_t BITER:9; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:18; /* Reserved */ + vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 VTES_PRC0 */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 HVEN_PRC0 */ + } B; + } MCR; /* INTC Module Configuration Register (MCR) INTC_BCR @baseaddress + 0x00 */ + int32_t INTC_reserverd_10[1]; + + union { + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t PRI:4; /* Priority */ + } B; + } CPR; /* INTC Current Priority Register for Processor 0 (CPR) INTC_CPR_PRC0 @baseaddress + 0x08 */ + + int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) INTC_CPR_PRC1 @baseaddress + 0x0c */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; /* Vector Table Base Address VTBA_PRC0 */ + vuint32_t INTVEC:9; /* Interrupt Vector INTVEC_PRC0 */ + vuint32_t:2; /* Reserved */ + } B; + } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) INTC_IACKR_PRC0 @baseaddress + 0x10 */ + + int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) INTC_IACKR_PRC1 @baseaddress + 0x14 */ + + union { + vuint32_t R; + } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) INTC_EOIR_PRC0 @baseaddress + 0x18 */ + + int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) INTC_EOIR_PRC1 @baseaddress + 0x1C */ + + union { + vuint8_t R; + struct { + vuint8_t:6; /* Reserved */ + vuint8_t SET:1; /* Set Flag bits */ + vuint8_t CLR:1; /* Clear Flag bits */ + } B; + } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) INTC_SSCIRn @baseaddress + 0x20 */ + + int32_t INTC_reserverd_32[6]; + + union { + vuint8_t R; + struct { + vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ + vuint8_t:2; /* Reserved */ + vuint8_t PRI:4; /* Priority Select */ + } B; + } PSR[512]; /* INTC Priority Select Registers (PSR) INTC_PSR @baseaddress + 0x40 */ + + }; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t ICEA0:1; + vuint32_t ICEA1:1; + vuint32_t:1; + vuint32_t ESSIE:2; + vuint32_t:1; + vuint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register EQADC_MCR */ + + int32_t EQADC_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register EQADC_NMSFR */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register EQADC_ETDFR */ + + union { + vuint32_t R; + struct { + vuint32_t CFPUSH:32; /* CF_PUSH */ + } B; + } CFPR[6]; /* CFIFO Push Registers EQADC_CFPR */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RFPOP:16; /* RF_POP */ + } B; + } RFPR[6]; /* Result FIFO Pop Registers EQADC_RFPR */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t CFEE0:1; + vuint16_t STRME0:1; + vuint16_t SSE:1; + vuint16_t CFINV:1; + vuint16_t:1; + vuint16_t MODE:4; + vuint16_t AMODE0:4; /* CFIFO0 only */ + } B; + } CFCR[6]; /* CFIFO Control Registers EQADC_CFCR */ + + uint32_t eqadc_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t NCIE:1; + vuint16_t TORIE:1; + vuint16_t PIE:1; + vuint16_t EOQIE:1; + vuint16_t CFUIE:1; + vuint16_t:1; + vuint16_t CFFE:1; + vuint16_t CFFS:1; + vuint16_t:4; + vuint16_t RFOIE:1; + vuint16_t:1; + vuint16_t RFDE:1; + vuint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers EQADC_IDCR */ + + uint32_t eqadc_reserved6; + + union { + vuint32_t R; + struct { + vuint32_t NCF:1; + vuint32_t TORF:1; + vuint32_t PF:1; + vuint32_t EOQF:1; + vuint32_t CFUF:1; + vuint32_t SSS:1; + vuint32_t CFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t CFCTR:4; + vuint32_t TNXTPTR:4; + vuint32_t RFCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers EQADC_FISR */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t TCCF:11; /* TC_CF */ + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers EQADC_CFTCR */ + + uint32_t eqadc_reserved9; + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB0 */ + vuint32_t CFS1:2; /* CFS1_TCB0 */ + vuint32_t CFS2:2; /* CFS2_TCB0 */ + vuint32_t CFS3:2; /* CFS3_TCB0 */ + vuint32_t CFS4:2; /* CFS4_TCB0 */ + vuint32_t CFS5:2; /* CFS5_TCB0 */ + vuint32_t:5; + vuint32_t LCFTCB0:4; + vuint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 EQADC_CFSSR0 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB1 */ + vuint32_t CFS1:2; /* CFS1_TCB1 */ + vuint32_t CFS2:2; /* CFS2_TCB1 */ + vuint32_t CFS3:2; /* CFS3_TCB1 */ + vuint32_t CFS4:2; /* CFS4_TCB1 */ + vuint32_t CFS5:2; /* CFS5_TCB1 */ + vuint32_t:5; + vuint32_t LCFTCB1:4; + vuint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 EQADC_CFSSR1 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TSSI */ + vuint32_t CFS1:2; /* CFS1_TSSI */ + vuint32_t CFS2:2; /* CFS2_TSSI */ + vuint32_t CFS3:2; /* CFS3_TSSI */ + vuint32_t CFS4:2; /* CFS4_TSSI */ + vuint32_t CFS5:2; /* CFS5_TSSI */ + vuint32_t:4; + vuint32_t ECBNI:1; + vuint32_t LCFTSSI:4; + vuint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 EQADC_CFSSR2 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:20; + } B; + } CFSR; /* EQADC_CFSR */ + + uint32_t eqadc_reserved11; + + union { + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t MDT:3; + vuint32_t:4; + vuint32_t BR:4; + } B; + } SSICR; /* SSI Control Register EQADC_SSICR */ + + union { + vuint32_t R; + struct { + vuint32_t RDV:1; + vuint32_t:5; + vuint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register EQADC_SSIRDR @ baseaddress + 0xB8 */ + + uint32_t eqadc_reserved11b[5]; + + uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ + /* REDLCCR is not implemented in the MPC563xM */ + + uint32_t eqadc_reserved12[11]; + + struct { + union { + vuint32_t R; + + /*B.CFIFOx_DATAw */ + + } R[4]; /*EQADC_CFxRw */ + + union { + vuint32_t R; + /*B.CFIFOx_EDATAw */ + } EDATA[4]; /*EQADC_CFxERw (new in MPC563xM) */ + + uint32_t eqadc_reserved13[8]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + vuint32_t R; + /*RFIFOx_DATAw */ + } R[4]; /*EQADC_RFxRw */ + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + /****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t PCSIS7:1; /* new in MPC563xM */ + vuint32_t PCSIS6:1; /* new in MPC563xM */ + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t DOZE:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:7; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register DSPI_MCR @baseaddress + 0x00 */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; /* SPI_TCNT */ + vuint32_t:16; + } B; + } TCR; /* DSPI Transfer Count Register DSPI_TCR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers DSPI_CTARx @baseaddress + 0x0C - 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register DSPI_SR @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; /*TCF_RE */ + vuint32_t:2; + vuint32_t EOQFRE:1; /*EQQF_RE */ + vuint32_t TFUFRE:1; /*TFUF_RE */ + vuint32_t:1; + vuint32_t TFFFRE:1; /*TFFF_RE */ + vuint32_t TFFFDIRS:1; /*TFFF_DIRS */ + vuint32_t:4; + vuint32_t RFOFRE:1; /*RFOF_RE */ + vuint32_t:1; + vuint32_t RFDFRE:1; /*RFDF_RE */ + vuint32_t RFDFDIRS:1; /*RFDF_DIRS */ + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register DSPI_RSER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t:2; + vuint32_t PCS7:1; /* new in MPC563xM */ + vuint32_t PCS6:1; /* new in MPC563xM */ + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register DSPI_PUSHR @baseaddress + 0x34 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register DSPI_POPR @baseaddress + 0x38 */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers DSPI_TXFRx @baseaddress + 0x3c - 0x78 */ + + vuint32_t DSPI_reserved_txf[12]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers DSPI_RXFRx @baseaddress + 0x7c - 0xB8 */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t:1; + vuint32_t MTOCNT:6; + vuint32_t:3; + vuint32_t TSBC:1; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:4; + vuint32_t DPCS7:1; + vuint32_t DPCS6:1; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register DSPI_DSICR @baseaddress + 0xBC */ + + union { + vuint32_t R; + struct { + vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } SDR; /* DSI Serialization Data Register DSPI_SDR @baseaddress + 0xC0 */ + + union { + vuint32_t R; + struct { + vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } ASDR; /* DSI Alternate Serialization Data Register DSPI_ASDR @baseaddress + 0xC4 */ + + union { + vuint32_t R; + struct { + vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } COMPR; /* DSI Transmit Comparison Register DSPI_COMPR @baseaddress + 0xC8 */ + + union { + vuint32_t R; + struct { + vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } DDR; /* DSI deserialization Data Register DSPI_DDR @baseaddress + 0xCC */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t TSBCNT:5; + vuint32_t:16; + vuint32_t DPCS1_7:1; + vuint32_t DPCS1_6:1; + vuint32_t DPCS1_5:1; + vuint32_t DPCS1_4:1; + vuint32_t DPCS1_3:1; + vuint32_t DPCS1_2:1; + vuint32_t DPCS1_1:1; + vuint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 DSPI_DSICR1 @baseaddress + 0xD0 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t SBR:13; + vuint32_t LOOPS:1; + vuint32_t:1; /* Reserved in MPC563xM */ + vuint32_t RSRC:1; + vuint32_t M:1; + vuint32_t WAKE:1; + vuint32_t ILT:1; + vuint32_t PE:1; + vuint32_t PT:1; + vuint32_t TIE:1; + vuint32_t TCIE:1; + vuint32_t RIE:1; + vuint32_t ILIE:1; + vuint32_t TE:1; + vuint32_t RE:1; + vuint32_t RWU:1; + vuint32_t SBK:1; + } B; + } CR1; /* Control Register 1 SCIBDH, SCIBDL, SCICR1, SCICR2 @baseaddress + 0x00 */ + + union { + vuint16_t R; + struct { + vuint16_t MDIS:1; + vuint16_t FBR:1; + vuint16_t BSTP:1; + vuint16_t IEBERR:1; /* BERIE */ + vuint16_t RXDMA:1; + vuint16_t TXDMA:1; + vuint16_t BRK13:1; /* BRCL */ + vuint16_t TXDIR:1; + vuint16_t BESM13:1; /* BESM */ + vuint16_t SBSTP:1; /* BESTP */ + vuint16_t RXPOL:1; + vuint16_t PMSK:1; + vuint16_t ORIE:1; + vuint16_t NFIE:1; + vuint16_t FEIE:1; + vuint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 SCICR3, SCICR4 @baseaddress + 0x04 */ + + union { + vuint16_t R; + struct { + vuint16_t R8:1; /* RN */ + vuint16_t T8:1; /* TN */ + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t R:4; + vuint8_t D; + } B; + } DR; /* Data Register SCIDRH, SCIDRL @baseaddress + 0x06 */ + + union { + vuint32_t R; + struct { + vuint32_t TDRE:1; + vuint32_t TC:1; + vuint32_t RDRF:1; + vuint32_t IDLE:1; + vuint32_t OR:1; + vuint32_t NF:1; + vuint32_t FE:1; + vuint32_t PF:1; + vuint32_t:3; + vuint32_t BERR:1; + vuint32_t:2; + vuint32_t TACT:1; + vuint32_t RAF:1; /* RACT */ + vuint32_t RXRDY:1; + vuint32_t TXRDY:1; + vuint32_t LWAKE:1; + vuint32_t STO:1; + vuint32_t PBERR:1; + vuint32_t CERR:1; + vuint32_t CKERR:1; + vuint32_t FRC:1; + vuint32_t:6; + vuint32_t UREQ:1; + vuint32_t OVFL:1; + } B; + } SR; /* Status Register SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t LRES:1; + vuint32_t WU:1; + vuint32_t WUD0:1; + vuint32_t WUD1:1; + vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ + vuint32_t PRTY:1; + vuint32_t LIN:1; + vuint32_t RXIE:1; + vuint32_t TXIE:1; + vuint32_t WUIE:1; + vuint32_t STIE:1; + vuint32_t PBIE:1; + vuint32_t CIE:1; + vuint32_t CKIE:1; + vuint32_t FCIE:1; + vuint32_t:6; + vuint32_t UQIE:1; + vuint32_t OFIE:1; + vuint32_t:8; + } B; + } LCR; /* LIN Control Register LINCTRL1, LINCTRL2, LINCTRL3 @baseaddress + 0x0C */ + + union { + vuint32_t R; + } LTR; /* LIN Transmit Register LINTX @baseaddress + 0x10 */ + + union { + vuint32_t R; + } LRR; /* LIN Recieve Register LINRX @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t P:16; + vuint32_t:3; + vuint32_t SYNM:1; + vuint32_t EROE:1; + vuint32_t ERFE:1; + vuint32_t ERPE:1; + vuint32_t M2:1; + vuint32_t:8; + } B; + } LPR; /* LIN CRC Polynom Register LINCRCP1, LINCRCP2, SCICR5 @baseaddress + 0x18 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_12_13_bit_tag { + union { + vuint16_t R; + struct { + vuint16_t R8:1; + vuint16_t T8:1; + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t D:12; + } B; + } DR; /* Data Register */ + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN2_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; /* new in MPC563xM */ + vuint32_t HALT:1; + vuint32_t NOTRDY:1; /* NOT_RDY */ + vuint32_t WAK_MSK:1; /* new in MPC563xM */ + vuint32_t SOFTRST:1; /* SOFT_RST */ + vuint32_t FRZACK:1; /* FRZ_ACK */ + vuint32_t SUPV:1; /* new in MPC563xM */ + vuint32_t SLF_WAK:1; /* new in MPC563xM */ + + vuint32_t WRNEN:1; /* WRN_EN */ + + vuint32_t MDISACK:1; /* LPM_ACK */ + vuint32_t WAK_SRC:1; /* new in MPC563xM */ + vuint32_t DOZE:1; /* new in MPC563xM */ + + vuint32_t SRXDIS:1; /* SRX_DIS */ + vuint32_t MBFEN:1; /* BCC */ + vuint32_t:2; + + vuint32_t LPRIO_EN:1; /* new in MPC563xM */ + vuint32_t AEN:1; /* new in MPC563xM */ + vuint32_t:2; + vuint32_t IDAM:2; /* new in MPC563xM */ + vuint32_t:2; + + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; /* BOFF_MSK */ + vuint32_t ERRMSK:1; /* ERR_MSK */ + vuint32_t CLKSRC:1; /* CLK_SRC */ + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; /* TWRN_MSK */ + vuint32_t RWRNMSK:1; /* RWRN_MSK */ + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; /* BOFF_REC */ + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; /* Control Register */ + } CR; /* CTRL */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + int32_t FLEXCAN_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; /* TWRN_INT */ + vuint32_t RWRNINT:1; /* RWRN_INT */ + vuint32_t BIT1ERR:1; /* BIT1_ERR */ + vuint32_t BIT0ERR:1; /* BIT0_ERR */ + vuint32_t ACKERR:1; /* ACK_ERR */ + vuint32_t CRCERR:1; /* CRC_ERR */ + vuint32_t FRMERR:1; /* FRM_ERR */ + vuint32_t STFERR:1; /* STF_ERR */ + vuint32_t TXWRN:1; /* TX_WRN */ + vuint32_t RXWRN:1; /* RX_WRN */ + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; /* FLT_CONF */ + vuint32_t:1; + vuint32_t BOFFINT:1; /* BOFF_INT */ + vuint32_t ERRINT:1; /* ERR_INT */ + vuint32_t WAK_INT:1; /* new in MPC563xM */ + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; /* Interruput Masks Register */ + } IMRH; /* IMASK2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; /* Interruput Masks Register */ + } IMRL; /* IMASK1 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; /* Interruput Flag Register */ + } IFRH; /* IFLAG2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; /* Interruput Flag Register */ + } IFRL; /* IFLAG1 */ + + uint32_t flexcan2_reserved2[19]; + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; /* RX Individual Mask Registers */ + } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ + + }; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : Decimation Filter (DECFIL) */ +/****************************************************************************/ + struct DECFIL_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FREN:1; + vuint32_t:1; + vuint32_t FRZ:1; + vuint32_t SRES:1; + vuint32_t:2; /* CASCD not supported in MPC563xM */ + vuint32_t IDEN:1; + vuint32_t ODEN:1; + vuint32_t ERREN:1; + vuint32_t:1; + vuint32_t FTYPE:2; + vuint32_t:1; + vuint32_t SCAL:2; + vuint32_t:1; + vuint32_t SAT:1; + vuint32_t ISEL:1; + vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ + vuint32_t DEC_RATE:4; + vuint32_t:1; /* SDIE not supported in MPC563xM */ + vuint32_t DSEL:1; + vuint32_t IBIE:1; + vuint32_t OBIE:1; + vuint32_t EDME:1; + vuint32_t TORE:1; + vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ + } B; + } MCR; /* Configuration Register DECFILTER_MCR @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t:1; + vuint32_t DEC_COUNTER:4; + vuint32_t IDFC:1; + vuint32_t ODFC:1; + vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ + vuint32_t IBIC:1; + vuint32_t OBIC:1; + vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ + vuint32_t DIVRC:1; + vuint32_t OVFC:1; + vuint32_t OVRC:1; + vuint32_t IVRC:1; + vuint32_t:6; + vuint32_t IDF:1; + vuint32_t ODF:1; + vuint32_t SDF:1; /* SDF not supported in MPC563xM */ + vuint32_t IBIF:1; + vuint32_t OBIF:1; + vuint32_t SVR:1; /* SVR not supported in MPC563xM */ + vuint32_t DIVR:1; + vuint32_t OVF:1; + vuint32_t OVR:1; + vuint32_t IVR:1; + } B; + } MSR; /* Status Register DECFILTER_MSR @baseaddress + 0x04 */ + + /* Module Extended Config.Register - not siupported on the MPC563xM DECFILTER_MXCR @baseaddress + 0x08 */ + + uint32_t decfil_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t INTAG:4; + vuint32_t:6; + vuint32_t PREFILL:1; + vuint32_t FLUSH:1; + vuint32_t INPBUF:16; + } B; + } IB; /* Interface Input Buffer DECFILTER_IB @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t OUTTAG:4; + vuint32_t OUTBUF:16; + } B; + } OB; /* Interface Output Buffer DECFILTER_OB @baseaddress + 0x14 */ + + uint32_t decfil_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t COEF:24; + } B; + } COEF[9]; /* Filter Coefficient Registers DECFILTER_COEFx @baseaddress + 0x20 - 0x40 */ + + uint32_t decfil_reserved3[13]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t TAP:24; + } B; + } TAP[8]; /* Filter TAP Registers DECFILTER_TAPx @baseaddress + 0x78 - 0x94 */ + + uint32_t decfil_reserved4[14]; + + /* 0x0D0 */ + union { + vuint16_t R; + struct { + vuint32_t:16; + vuint32_t SAMP_DATA:16; + } B; + } EDID; /* Filter EDID Registers DECFILTER_EDID @baseaddress + 0xD0 */ + + uint32_t decfil_reserved5[3]; + + /* 0x0E0 */ + uint32_t decfil_reserved6; + /* Filter FINTVAL Registers - Not supported on MPC563xM DECFILTER_FINTVAL @baseaddress + 0xE0 */ + + /* 0x0E4 */ + uint32_t decfil_reserved7; + /* Filter FINTCNT Registers - Not supported on MPC563xM DECFILTER_FINTCNT @baseaddress + 0xE4 */ + + /* 0x0E8 */ + uint32_t decfil_reserved8; + /* Filter CINTVAL Registers - Not supported on MPC563xM DECFILTER_CINTVAL @baseaddress + 0xE8 */ + + /* 0x0EC */ + uint32_t decfil_reserved9; + /* Filter CINTCNT Registers - Not supported on MPC563xM DECFILTER_CINTCNT @baseaddress + 0xEC */ + + }; +/****************************************************************************/ +/* MODULE : Periodic Interval Timer (PIT) */ +/****************************************************************************/ + struct PIT_tag { + + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t MDIS_RTI:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; /* PIT Module Control Register */ + + uint32_t pit_reserved1[59]; + + struct { + union { + vuint32_t R; /* TSVn */ + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; /* TVLn */ + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel */ + + struct { + union { + vuint32_t R; + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } TIMER[4]; /* Timer Channels */ + + }; +/****************************************************************************/ +/* MODULE : System Timer Module (STM) */ +/****************************************************************************/ + struct STM_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; /* STM Control Register STM_CR (new in MPC563xM) Offset 0x0000 */ + + union { + vuint32_t R; + } CNT; /* STM Count Register STM_CNT (new in MPC563xM) Offset Offset 0x0004 */ + + uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register STM_CCR0 (new in MPC563xM) Offset 0x0010 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register STM_CIR0 (new in MPC563xM) Offset 0x0014 */ + + union { + vuint32_t R; + } CMP0; /* STM Channel Compare Register STM_CMP0 (new in MPC563xM) Offset Offset 0x0018 */ + + uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register STM_CCR1 (new in MPC563xM) Offset 0x0020 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register STM_CIR1 (new in MPC563xM) Offset 0x0024 */ + + union { + vuint32_t R; + } CMP1; /* STM Channel Compare Register STM_CMP1 (new in MPC563xM) Offset Offset 0x0028 */ + + uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register STM_CCR2 (new in MPC563xM) Offset 0x0030 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register STM_CIR2 (new in MPC563xM) Offset 0x0034 */ + + union { + vuint32_t R; + } CMP2; /* STM Channel Compare Register STM_CMP2 (new in MPC563xM) Offset Offset 0x0038 */ + + uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register STM_CCR3 (new in MPC563xM) Offset 0x0040 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register STM_CIR3 (new in MPC563xM) Offset 0x0044 */ + + union { + vuint32_t R; + } CMP3; /* STM Channel Compare Register STM_CMP3 (new in MPC563xM) Offset Offset 0x0048 */ + + uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ + }; + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:14; + vuint32_t KEY:1; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } MCR; /*SWT_CR *//* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* Interrupt register SWT_IR */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* Timeout register SWT_TO */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + + } B; + } WN; /* Window register SWT_WN */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* Service register SWT_SR */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* Counter output register SWT_CO */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SK:16; + } B; + } SK; /* Service key register SWT_SK */ + }; +/****************************************************************************/ +/* MODULE : Power Management Controller (PMC) */ +/****************************************************************************/ + struct PMC_tag { + union { + vuint32_t R; + struct { + vuint32_t LVRER:1; /* LVIRR */ + vuint32_t LVREH:1; /* LVIHR */ + vuint32_t LVRE50:1; /* LVI5R */ + vuint32_t LVRE33:1; /* LVI3R */ + vuint32_t LVREC:1; /* LVI1R */ + vuint32_t:3; + vuint32_t LVIER:1; /* LVIRE */ + vuint32_t LVIEH:1; /* LVIHE */ + vuint32_t LVIE50:1; /* LVI5E */ + vuint32_t LVIE33:1; /* LVI3E */ + vuint32_t LVIC:1; /* LVI1E */ + vuint32_t:2; + vuint32_t TLK:1; + vuint32_t:16; + } B; + } MCR; /* Module Configuration register CFGR */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t LVDREGTRIM:4; /* LVI50TRIM */ + vuint32_t VDD33TRIM:4; /* BV33TRIM */ + vuint32_t LVD33TRIM:4; /* LVI33TRIM */ + vuint32_t VDDCTRIM:4; /* V12TRIM */ + vuint32_t LVDCTRIM:4; /* LVI33TRIM */ + } B; + } TRIMR; /* Trimming register */ + + union { + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t LVFVSTBY:1; + vuint32_t BGRDY:1; /* BGS1 */ + vuint32_t BGTS:1; /* BGS2 */ + vuint32_t:5; + vuint32_t LVFCSTBY:1; + vuint32_t:1; + vuint32_t V33DIS:1; /* 3.3V Regulator Disable V33S */ + vuint32_t LVFCR:1; /* Clear LVFR LVIRC */ + vuint32_t LVFCH:1; /* Clear LVFH LVIHC */ + vuint32_t LVFC50:1; /* Clear LVF5 LVI5 */ + vuint32_t LVFC33:1; /* Clear LVF3 LVI3 */ + vuint32_t LVFCC:1; /* Clear LVFC LVI1 */ + vuint32_t:3; + vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply LVIRF */ + vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply LVIHF */ + vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply LVI5F */ + vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply LVI3F */ + vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) LVI1F */ + vuint32_t:3; + + } B; + } SR; /* status register */ + }; +/****************************************************************************/ +/* MODULE : TSENS (Temperature Sensor) */ +/****************************************************************************/ + + struct TSENS_tag { + + union { + vuint32_t R; + struct { + vuint32_t TSCV2:16; + vuint32_t TSCV1:16; + } B; + } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TSCV3:16; + } B; + } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ + + uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ + + }; + +/* Define memories */ +/* Comments need to be moved for different memory sizes */ + +#define SRAM_START 0x40000000 + /*#define SRAM_SIZE 0xC000 48K SRAM */ + /*#define SRAM_SIZE 0x10000 64K SRAM */ +#define SRAM_SIZE 0x17800 /* 94K SRAM */ + /*#define SRAM_END 0x4000BFFF 48K SRAM */ + /*#define SRAM_END 0x4000FFFF 64K SRAM */ +#define SRAM_END 0x400177FF /* 94K SRAM */ + +#define FLASH_START 0x0 + /*#define FLASH_SIZE 0x100000 1M Flash */ +#define FLASH_SIZE 0x180000 /* 1.5M Flash */ + /*#define FLASH_END 0xFFFFF 1M Flash */ +#define FLASH_END 0x17FFFF /* 1.5M Flash */ + +/* Shadow Flash start and end address */ +#define FLASH_SHADOW_START 0x00FFC000 +#define FLASH_SHADOW_SIZE 0x4000 +#define FLASH_SHADOW_END 0x00FFFFFF + +/* Define instances of modules */ +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) +#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) +#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) +#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) + +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + +#ifdef __MWERKS__ +#pragma pop +#endif /* + */ + +#ifdef __cplusplus +} +#endif /* + */ + +#endif /* ifdef _MPC563M_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c new file mode 100644 index 000000000..f6b220c85 --- /dev/null +++ b/os/hal/platforms/SPC564Axx/hal_lld.c @@ -0,0 +1,150 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/hal_lld.c + * @brief SPC564Axx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t n; + + /* The SRAM is parked on the load/store port, for some unknown reason it + is defaulted on the instructions port and this kills performance.*/ + XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/ + + /* The DMA priority is placed above the CPU priority in order to not + starve I/O activities while the CPU is executing tight loops (FLASH + and SRAM slave ports only).*/ +#if !defined(_SPC564A70_) + XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities: + eDMA (4): 0 (highest) + Core Instructions (0): 1 + Core Data (1): 2 + EBI (7): 3 + Flexray (6): 4 */ + XBAR.MPR2.R = 0x34000021; /* SRAM slave port priorities: + eDMA (4): 0 (highest) + Core Instructions (0): 1 + Core Data (1): 2 + EBI (7): 3 + FlexRay (6): 4 */ +#else /* defined(_SPC564A70_) */ + XBAR.MPR0.R = 0x03000021; /* Flash slave port priorities: + eDMA (4): 0 (highest) + Core Instructions (0): 1 + Core Data (1): 2 + Flexray (6): 3 */ + XBAR.MPR2.R = 0x03000021; /* SRAM slave port priorities: + eDMA (4): 0 (highest) + Core Instructions (0): 1 + Core Data (1): 2 + FlexRay (6): 3 */ +#endif /* defined(_SPC564A70_) */ + + /* Decrementer timer initialized for system tick use, note, it is + initialized here because in the OSAL layer the system clock frequency + is not yet known.*/ + n = SPC5_SYSCLK / CH_FREQUENCY; + asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */ + "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ + "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ + "mtspr 340, %%r3" /* TCR register. */ + : : [n] "r" (n) : "r3"); + + /* TB counter enabled for debug and measurements.*/ + asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ + "mtspr 1008, %%r3" /* HID0 register. */ + : : : "r3"); + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); +} + +/** + * @brief SPC563 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + + /* Setting up RAM/Flash wait states and the prefetching bits.*/ + ECSM.MUDCR.R = SPC5_RAM_WS; + FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; + FLASH_A.BIUCR2.R = 0; +#if !defined(_SPC564A70_) + /* The second controller is only present in Andorra 3M or 4M.*/ + FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; + FLASH_B.BIUCR2.R = 0; +#endif /* !defined(_SPC564A70_) */ + +#if !SPC5_NO_INIT + /* PLL activation.*/ + FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */ + FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ +#if !SPC5_CLK_BYPASS + FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ + FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV; + FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD; + FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD; + while (!FMPLL.SYNSR.B.LOCK) + ; + FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ +#endif /* !SPC5_CLK_BYPASS */ +#endif /* !SPC5_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/SPC564Axx/hal_lld.h b/os/hal/platforms/SPC564Axx/hal_lld.h new file mode 100644 index 000000000..62df1df45 --- /dev/null +++ b/os/hal/platforms/SPC564Axx/hal_lld.h @@ -0,0 +1,278 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/hal_lld.h + * @brief SPC564Axx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc564a.h" +#include "spc564a_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "SPC564Axx Powertrain" + +/** + * @name ESYNCR2 register definitions + * @{ + */ +#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */ +#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */ +#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */ +#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ +/** @} */ + +/** + * @name BIUCR register definitions + * @{ + */ +#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ +#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ +#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ +#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ +#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ +#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ +#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ +#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ +#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ +#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ +#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ +#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ +#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ +#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ +#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ +#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ +#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ +#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ +#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ +#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ +#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ +#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ +#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ +#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ +#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ +#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ +#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ +#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ +#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ +#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ +#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ +#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ +#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ +#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ +#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ +#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ +#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ +#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Clock bypass. + * @note If set to @p TRUE then the PLL is not started and initialized, the + * external clock is used as-is and the other clock-related settings + * are ignored. + */ +#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__) +#define SPC5_CLK_BYPASS FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief External clock pre-divider. + * @note Must be in range 1...15. + */ +#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_CLK_PREDIV_VALUE 2 +#endif + +/** + * @brief Multiplication factor divider. + * @note Must be in range 32...96. + */ +#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__) +#define SPC5_CLK_MFD_VALUE 75 +#endif + +/** + * @brief Reduced frequency divider. + */ +#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__) +#define SPC5_CLK_RFD RFD_DIV2 +#endif + +/** + * @brief Flash buffer and prefetching settings. + * @note Please refer to the SPC564Axx reference manual about the meaning + * of the following bits, if in doubt DO NOT MODIFY IT. + * @note Do not specify the APC, WWSC, RWSC bits in this value because + * those are calculated from the system clock and ORed with this + * value. + */ +#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__) +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC564Axx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined" +#endif + +#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15) +#error "invalid SPC5_CLK_PREDIV_VALUE value specified" +#endif + +#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96) +#error "invalid SPC5_CLK_MFD_VALUE value specified" +#endif + +#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \ + (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16) +#error "invalid SPC5_CLK_RFD value specified" +#endif + +/** + * @brief PLL input divider. + */ +#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1) + +/** + * @brief PLL multiplier. + */ +#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE) + +/** + * @brief PLL output clock. + */ +#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \ + SPC5_CLK_MFD_VALUE) + +#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000) +#error "VCO frequency out of the acceptable range (256...512)" +#endif + +/** + * @brief PLL output clock. + */ +#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__) +#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1))) +#else +#define SPC5_SYSCLK SPC5_XOSC_CLK +#endif + +#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK +#error "System clock above maximum rated frequency (150MHz)" +#endif + +/** + * @brief Flash wait states are a function of the system clock. + */ +#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3) +#elif SPC5_SYSCLK <= 61000000 +#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3) +#elif SPC5_SYSCLK <= 90000000 +#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3) +#elif SPC5_SYSCLK <= 123000000 +#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3) +#else +#define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3) +#endif + +/** + * @brief RAM wait states are a function of the system clock. + */ +#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__) +#define SPC5_RAM_WS 0 +#else +#define SPC5_RAM_WS 0x40000000 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC564Axx/platform.mk b/os/hal/platforms/SPC564Axx/platform.mk new file mode 100644 index 000000000..6abcecaec --- /dev/null +++ b/os/hal/platforms/SPC564Axx/platform.mk @@ -0,0 +1,15 @@ +# List of all the SPC564Axx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC564Axx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1 diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h new file mode 100644 index 000000000..ec584abdf --- /dev/null +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -0,0 +1,172 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/spc564a_registry.h + * @brief SPC564Axx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC564A_REGISTRY_H_ +#define _SPC564A_REGISTRY_H_ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(_SPC564A70B4_) || defined(_SPC564A70L7_) +#define _SPC564A70_ +#elif defined(_SPC564A74B4_) || defined(_SPC564A74L7_) +#define _SPC564A74_ +#elif defined(_SPC564A80B4_) || defined(_SPC564A80L7_) +#define _SPC564A80_ +#else +#error "SPC564Axx platform not defined" +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC564Axx capabilities + * @{ + */ +/* DSPI attribures.*/ +#define SPC5_HAS_DSPI0 FALSE +#define SPC5_HAS_DSPI1 TRUE +#define SPC5_HAS_DSPI2 TRUE +#define SPC5_HAS_DSPI3 TRUE +#define SPC5_HAS_DSPI4 FALSE +#define SPC5_DSPI_FIFO_DEPTH 16 +#define SPC5_DSPI1_TX1_DMA_CH_ID 12 +#define SPC5_DSPI1_TX2_DMA_CH_ID 24 +#define SPC5_DSPI1_RX_DMA_CH_ID 13 +#define SPC5_DSPI2_TX1_DMA_CH_ID 14 +#define SPC5_DSPI2_TX2_DMA_CH_ID 25 +#define SPC5_DSPI2_RX_DMA_CH_ID 15 +#define SPC5_DSPI3_TX1_DMA_CH_ID 16 +#define SPC5_DSPI3_TX2_DMA_CH_ID 26 +#define SPC5_DSPI3_RX_DMA_CH_ID 17 +#define SPC5_DSPI1_EOQF_HANDLER vector132 +#define SPC5_DSPI1_EOQF_NUMBER 132 +#define SPC5_DSPI1_TFFF_HANDLER vector133 +#define SPC5_DSPI1_TFFF_NUMBER 133 +#define SPC5_DSPI2_EOQF_HANDLER vector137 +#define SPC5_DSPI2_EOQF_NUMBER 137 +#define SPC5_DSPI2_TFFF_HANDLER vector138 +#define SPC5_DSPI2_TFFF_NUMBER 138 +#define SPC5_DSPI3_EOQF_HANDLER vector142 +#define SPC5_DSPI3_EOQF_NUMBER 142 +#define SPC5_DSPI3_TFFF_HANDLER vector143 +#define SPC5_DSPI3_TFFF_NUMBER 143 +#define SPC5_DSPI1_ENABLE_CLOCK() +#define SPC5_DSPI1_DISABLE_CLOCK() +#define SPC5_DSPI2_ENABLE_CLOCK() +#define SPC5_DSPI2_DISABLE_CLOCK() +#define SPC5_DSPI3_ENABLE_CLOCK() +#define SPC5_DSPI3_DISABLE_CLOCK() + +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA TRUE +#define SPC5_EDMA_NCHANNELS 64 +#define SPC5_EDMA_HAS_MUX FALSE + +/* eQADC attributes.*/ +#define SPC5_HAS_EQADC TRUE + +/* eSCI attributes.*/ +#define SPC5_HAS_ESCIA TRUE +#define SPC5_ESCIA_HANDLER vector146 +#define SPC5_ESCIA_NUMBER 146 + +#define SPC5_HAS_ESCIB TRUE +#define SPC5_ESCIB_HANDLER vector149 +#define SPC5_ESCIB_NUMBER 149 + +#define SPC5_HAS_ESCIC TRUE +#define SPC5_ESCIC_HANDLER vector473 +#define SPC5_ESCIC_NUMBER 473 + +/* SIU attributes.*/ +#define SPC5_HAS_SIU TRUE +#define SPC5_SIU_SUPPORTS_PORTS FALSE + +/* EMIOS attributes.*/ +#define SPC5_HAS_EMIOS TRUE + +#define SPC5_EMIOS_NUM_CHANNELS 24 + +#define SPC5_EMIOS_FLAG_F0_HANDLER vector51 +#define SPC5_EMIOS_FLAG_F1_HANDLER vector52 +#define SPC5_EMIOS_FLAG_F2_HANDLER vector53 +#define SPC5_EMIOS_FLAG_F3_HANDLER vector54 +#define SPC5_EMIOS_FLAG_F4_HANDLER vector55 +#define SPC5_EMIOS_FLAG_F5_HANDLER vector56 +#define SPC5_EMIOS_FLAG_F6_HANDLER vector57 +#define SPC5_EMIOS_FLAG_F7_HANDLER vector58 +#define SPC5_EMIOS_FLAG_F8_HANDLER vector59 +#define SPC5_EMIOS_FLAG_F9_HANDLER vector60 +#define SPC5_EMIOS_FLAG_F10_HANDLER vector61 +#define SPC5_EMIOS_FLAG_F11_HANDLER vector62 +#define SPC5_EMIOS_FLAG_F12_HANDLER vector63 +#define SPC5_EMIOS_FLAG_F13_HANDLER vector64 +#define SPC5_EMIOS_FLAG_F14_HANDLER vector65 +#define SPC5_EMIOS_FLAG_F15_HANDLER vector66 +#define SPC5_EMIOS_FLAG_F16_HANDLER vector202 +#define SPC5_EMIOS_FLAG_F17_HANDLER vector203 +#define SPC5_EMIOS_FLAG_F18_HANDLER vector204 +#define SPC5_EMIOS_FLAG_F19_HANDLER vector205 +#define SPC5_EMIOS_FLAG_F20_HANDLER vector206 +#define SPC5_EMIOS_FLAG_F21_HANDLER vector207 +#define SPC5_EMIOS_FLAG_F22_HANDLER vector208 +#define SPC5_EMIOS_FLAG_F23_HANDLER vector209 +#define SPC5_EMIOS_FLAG_F0_NUMBER 51 +#define SPC5_EMIOS_FLAG_F1_NUMBER 52 +#define SPC5_EMIOS_FLAG_F2_NUMBER 53 +#define SPC5_EMIOS_FLAG_F3_NUMBER 54 +#define SPC5_EMIOS_FLAG_F4_NUMBER 55 +#define SPC5_EMIOS_FLAG_F5_NUMBER 56 +#define SPC5_EMIOS_FLAG_F6_NUMBER 57 +#define SPC5_EMIOS_FLAG_F7_NUMBER 58 +#define SPC5_EMIOS_FLAG_F8_NUMBER 59 +#define SPC5_EMIOS_FLAG_F9_NUMBER 60 +#define SPC5_EMIOS_FLAG_F10_NUMBER 61 +#define SPC5_EMIOS_FLAG_F11_NUMBER 62 +#define SPC5_EMIOS_FLAG_F12_NUMBER 63 +#define SPC5_EMIOS_FLAG_F13_NUMBER 64 +#define SPC5_EMIOS_FLAG_F14_NUMBER 65 +#define SPC5_EMIOS_FLAG_F15_NUMBER 66 +#define SPC5_EMIOS_FLAG_F16_NUMBER 202 +#define SPC5_EMIOS_FLAG_F17_NUMBER 203 +#define SPC5_EMIOS_FLAG_F18_NUMBER 204 +#define SPC5_EMIOS_FLAG_F19_NUMBER 205 +#define SPC5_EMIOS_FLAG_F20_NUMBER 206 +#define SPC5_EMIOS_FLAG_F21_NUMBER 207 +#define SPC5_EMIOS_FLAG_F22_NUMBER 208 +#define SPC5_EMIOS_FLAG_F23_NUMBER 209 + +#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \ + SPC5_EMIOS_GLOBAL_PRESCALER) +#define SPC5_EMIOS_ENABLE_CLOCK() +#define SPC5_EMIOS_DISABLE_CLOCK() +/** @} */ + +#endif /* _SPC564A_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC564Axx/typedefs.h b/os/hal/platforms/SPC564Axx/typedefs.h new file mode 100644 index 000000000..c0eccf4e8 --- /dev/null +++ b/os/hal/platforms/SPC564Axx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC564Axx/xpc564a.h b/os/hal/platforms/SPC564Axx/xpc564a.h new file mode 100644 index 000000000..24c159e13 --- /dev/null +++ b/os/hal/platforms/SPC564Axx/xpc564a.h @@ -0,0 +1,6377 @@ +/**************************************************************************/ +/* FILE NAME: MPC5644A.h COPYRIGHT(c) Freescale & STMicroelectronics */ +/* VERSION: 0.5 2010 - All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contains all of the register and bit field definitions for */ +/* MPC5644A. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 0.1 R. MORAN 10/Aug/09 Initial Alpha version. */ +/* 0.2 R. Moran 09/Nov/09 Several Updates: */ +/* - XBAR - MPR/SGPCR'3' changed to '2' */ +/* - CFCR, IDCR, CFTCR array sizes altered*/ +/* - IDIS,CASCD added to DEC_Filter MCR */ +/* - WDM fields changed in eTPU_WDTR reg */ +/* - Additional ECSM registers added */ +/* 0.3 R. Moran 14/Jan/10 Several Updates: */ +/* - Flash User Test Register implemented */ +/* - MPU.EDR[3] register removed */ +/* - Minor Loop TCD bits implemented */ +/* - Temperature Sensor implemented */ +/* - DSPI.MCR.B.PES implemented */ +/* 0.4 R. Moran 30/Mar/10 - Added DTS Module Registers */ +/* - Added Reaction Module */ +/* - eQADC REDLCCR register */ +/* - Temp Sensor TCCR0 corrected */ +/* - CFTCR definition changed */ +/* - EBI CAL_BR/OR updated */ +/* - XBAR MPR0,1,3,7 fixed master fields */ +/* - Decimation filter updated to support */ +/* Integration filter and rev2 changes */ +/* 0.5 I. Harris 25/May/10 - Updated ECSM_ESR with 1bit cor. fld */ +/* - Updated ECSM_ECR with 1bit cor. ena */ +/* - Corrected ECSM_MUDR endianness */ +/* - Corrected ECSM_MWCR ENBWCR field name*/ +/* - Updated SIU_IREEx fields */ +/* - Added EBI_MCR DBM field */ +/* - Added PBRIDGE Registers */ +/* - Added SIU EMPCR0 Register */ +/* - Included FlexCAN RXFIFO structure */ +/**************************************************************************/ + +/**************************************************************************/ +/* Example instantiation and use: */ +/* */ +/* ..B. = 1; */ +/* ..R = 0x10000000; */ +/* */ +/**************************************************************************/ + +#ifndef _MPC5644_H_ +#define _MPC5644_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + + struct EDMA_TCD_STD_tag { /* for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ + /* 00 */ + vuint32_t SADDR; /* Source Address */ + + /* 04 */ /* Transfer Attributes */ + vuint16_t SMOD:5; /* Source Address Modulo */ + vuint16_t SSIZE:3; /* Source Data Transfer Size */ + vuint16_t DMOD:5; /* Destination Address Modulo */ + vuint16_t DSIZE:3; /* Destination Data Transfer Size */ + + /* 06 */ + vint16_t SOFF; /* Signed Source Address Offset */ + + /* 08 */ + vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */ + + /* 0C */ + vint32_t SLAST; /* Last Source Address Adjustment */ + + /* 10 */ + vuint32_t DADDR; /* Destination Address */ + + /* 14 */ + vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */ + /* Linking on Minor Loop Completion */ + vuint16_t CITER:15; /* Current Major Iteration Count */ + + /* 16 */ + vint16_t DOFF; /* Signed Destination Address Offset */ + + /* 18 */ + vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or */ + /* Scatter/Gather Address (if E_SG = 1) */ + + /* 1C */ + vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */ + /* Linking on Minor Loop Complete */ + vuint16_t BITER:15; /* Starting ("Major") Iteration Count */ + + /* 1E */ /* Channel Control/Status */ + vuint16_t BWC:2; /* Bandwidth Control */ + vuint16_t MAJORLINKCH:6; /* Link Channel Number */ + vuint16_t DONE:1; /* Channel Done */ + vuint16_t ACTIVE:1; + vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link */ + vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */ + vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */ + vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */ + vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */ + vuint16_t START:1; /* Explicit Channel Start */ + }; + + + + struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ + + /* 00 */ + vuint32_t SADDR; /* Source Address */ + + /* 04 */ /* Transfer Attributes */ + vuint16_t SMOD:5; /* Source Address Modulo */ + vuint16_t SSIZE:3; /* Source Data Transfer Size */ + vuint16_t DMOD:5; /* Destination Address Modulo */ + vuint16_t DSIZE:3; /* Destination Data Transfer Size */ + + /* 06 */ + vint16_t SOFF; /* Signed Source Address Offset */ + + /* 08 */ + vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */ + + /* 0C */ + vint32_t SLAST; /* Last Source Address Adjustment */ + + /* 10 */ + vuint32_t DADDR; /* Destination Address */ + + /* 14 */ + vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */ + /* Linking on Minor Loop Completion */ + vuint16_t CITERLINKCH:6; /* Link Channel Number */ + vuint16_t CITER:9; /* Current Major Iteration Count */ + + /* 16 */ + vint16_t DOFF; /* Signed Destination Address Offset */ + + /* 18 */ + vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or */ + /* Scatter/Gather Address (if E_SG = 1) */ + + /* 1C */ + vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */ + /* Linking on Minor Loop Complete */ + vuint16_t BITERLINKCH:6; /* Link Channel Number */ + vuint16_t BITER:9; /* Starting ("Major") Iteration Count */ + + /* 1E */ /* Channel Control/Status */ + vuint16_t BWC:2; /* Bandwidth Control */ + vuint16_t MAJORLINKCH:6; /* Link Channel Number */ + vuint16_t DONE:1; /* Channel Done */ + vuint16_t ACTIVE:1; /* Channel Active */ + vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link */ + vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */ + vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */ + vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */ + vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */ + vuint16_t START:1; /* Explicit Channel Start */ + }; + + struct EDMA_TCD_alt2_tag { /* for alternate format TCDs (when EDMA.EMLM=1) */ + + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + + vuint16_t SMLOE:1; /* Source minor loop offset enable */ + vuint16_t DMLOE:1; /* Destination minor loop offset enable */ + vuint32_t MLOFF:20; /* Minor loop Offset */ + vuint16_t NBYTES:10; /* inner (“minor”) byte count */ + + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + + vuint16_t CITERE_LINK:1; + vuint16_t CITER:15; + + vint16_t DOFF; /* signed destination address offset */ + + vint32_t DLAST_SGA; + + vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ + vuint16_t BITER:15; + + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + }; + + +/****************************************************************************/ +/* MODULE : eDMA */ +/****************************************************************************/ + + struct EDMA_tag { + + union { + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t CX:1; /* Cancel Transfer */ + vuint32_t ECX:1; /* Error Cancel Transfer */ + vuint32_t GRP3PRI:2; /* Channel Group 3 Priority */ + vuint32_t GRP2PRI:2; /* Channel Group 2 Priority */ + vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + vuint32_t EMLM:1; /* Enable Minor Loop Mapping */ + vuint32_t CLM:1; /* Continuous Link Mode */ + vuint32_t HALT:1; /* Halt DMA Operations */ + vuint32_t HOE:1; /* Halt On Error */ + vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + vuint32_t EDBG:1; /* Enable Debug */ + vuint32_t:1; /* Enable Buffered Writes */ + } B; + } CR; /* DMA Control Register @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t VLD:1; /* Logical OR of all DMAERRH */ + vuint32_t:14; /* Reserved */ + vuint32_t ECX:1; /* Transfer Canceled */ + vuint32_t GPE:1; /* Group Priority Error */ + vuint32_t CPE:1; /* Channel Priority Error */ + vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ + vuint32_t SAE:1; /* Source Address Error 0 */ + vuint32_t SOE:1; /* Source Offset Error */ + vuint32_t DAE:1; /* Destination Address Error */ + vuint32_t DOE:1; /* Destination Offset Error */ + vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ + vuint32_t SBE:1; /* Source Bus Error */ + vuint32_t DBE:1; /* Destination Bus Error */ + } B; + } ESR; /* Error Status Register @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t ERQ63:1; + vuint32_t ERQ62:1; + vuint32_t ERQ61:1; + vuint32_t ERQ60:1; + vuint32_t ERQ59:1; + vuint32_t ERQ58:1; + vuint32_t ERQ57:1; + vuint32_t ERQ56:1; + vuint32_t ERQ55:1; + vuint32_t ERQ54:1; + vuint32_t ERQ53:1; + vuint32_t ERQ52:1; + vuint32_t ERQ51:1; + vuint32_t ERQ50:1; + vuint32_t ERQ49:1; + vuint32_t ERQ48:1; + vuint32_t ERQ47:1; + vuint32_t ERQ46:1; + vuint32_t ERQ45:1; + vuint32_t ERQ44:1; + vuint32_t ERQ43:1; + vuint32_t ERQ42:1; + vuint32_t ERQ41:1; + vuint32_t ERQ40:1; + vuint32_t ERQ39:1; + vuint32_t ERQ38:1; + vuint32_t ERQ37:1; + vuint32_t ERQ36:1; + vuint32_t ERQ35:1; + vuint32_t ERQ34:1; + vuint32_t ERQ33:1; + vuint32_t ERQ32:1; + } B; + } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/ + + union { + vuint32_t R; + struct { + vuint32_t ERQ31:1; + vuint32_t ERQ30:1; + vuint32_t ERQ29:1; + vuint32_t ERQ28:1; + vuint32_t ERQ27:1; + vuint32_t ERQ26:1; + vuint32_t ERQ25:1; + vuint32_t ERQ24:1; + vuint32_t ERQ23:1; + vuint32_t ERQ22:1; + vuint32_t ERQ21:1; + vuint32_t ERQ20:1; + vuint32_t ERQ19:1; + vuint32_t ERQ18:1; + vuint32_t ERQ17:1; + vuint32_t ERQ16:1; + vuint32_t ERQ15:1; + vuint32_t ERQ14:1; + vuint32_t ERQ13:1; + vuint32_t ERQ12:1; + vuint32_t ERQ11:1; + vuint32_t ERQ10:1; + vuint32_t ERQ09:1; + vuint32_t ERQ08:1; + vuint32_t ERQ07:1; + vuint32_t ERQ06:1; + vuint32_t ERQ05:1; + vuint32_t ERQ04:1; + vuint32_t ERQ03:1; + vuint32_t ERQ02:1; + vuint32_t ERQ01:1; + vuint32_t ERQ00:1; + } B; + } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/ + + union { + vuint32_t R; + struct { + + vuint32_t EEI63:1; + vuint32_t EEI62:1; + vuint32_t EEI61:1; + vuint32_t EEI60:1; + vuint32_t EEI59:1; + vuint32_t EEI58:1; + vuint32_t EEI57:1; + vuint32_t EEI56:1; + vuint32_t EEI55:1; + vuint32_t EEI54:1; + vuint32_t EEI53:1; + vuint32_t EEI52:1; + vuint32_t EEI51:1; + vuint32_t EEI50:1; + vuint32_t EEI49:1; + vuint32_t EEI48:1; + vuint32_t EEI47:1; + vuint32_t EEI46:1; + vuint32_t EEI45:1; + vuint32_t EEI44:1; + vuint32_t EEI43:1; + vuint32_t EEI42:1; + vuint32_t EEI41:1; + vuint32_t EEI40:1; + vuint32_t EEI39:1; + vuint32_t EEI38:1; + vuint32_t EEI37:1; + vuint32_t EEI36:1; + vuint32_t EEI35:1; + vuint32_t EEI34:1; + vuint32_t EEI33:1; + vuint32_t EEI32:1; + } B; + } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/ + + union { + vuint32_t R; + struct { + vuint32_t EEI31:1; + vuint32_t EEI30:1; + vuint32_t EEI29:1; + vuint32_t EEI28:1; + vuint32_t EEI27:1; + vuint32_t EEI26:1; + vuint32_t EEI25:1; + vuint32_t EEI24:1; + vuint32_t EEI23:1; + vuint32_t EEI22:1; + vuint32_t EEI21:1; + vuint32_t EEI20:1; + vuint32_t EEI19:1; + vuint32_t EEI18:1; + vuint32_t EEI17:1; + vuint32_t EEI16:1; + vuint32_t EEI15:1; + vuint32_t EEI14:1; + vuint32_t EEI13:1; + vuint32_t EEI12:1; + vuint32_t EEI11:1; + vuint32_t EEI10:1; + vuint32_t EEI09:1; + vuint32_t EEI08:1; + vuint32_t EEI07:1; + vuint32_t EEI06:1; + vuint32_t EEI05:1; + vuint32_t EEI04:1; + vuint32_t EEI03:1; + vuint32_t EEI02:1; + vuint32_t EEI01:1; + vuint32_t EEI00:1; + } B; + } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t SERQ:7; + } B; + } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t CERQ:7; + } B; + } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t SEEI:7; + } B; + } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t CEEI:7; + } B; + } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t CINT:7; + } B; + } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t CERR:7; + } B; + } CER; /* DMA Clear error Register @baseaddress + 0x1D */ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t SSB:7; + } B; + } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */ + + union { + vuint8_t R; + struct { + vuint8_t NOP:1; + vuint8_t CDSB:7; + } B; + } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */ + + union { + vuint32_t R; + struct { + vuint32_t INT63:1; + vuint32_t INT62:1; + vuint32_t INT61:1; + vuint32_t INT60:1; + vuint32_t INT59:1; + vuint32_t INT58:1; + vuint32_t INT57:1; + vuint32_t INT56:1; + vuint32_t INT55:1; + vuint32_t INT54:1; + vuint32_t INT53:1; + vuint32_t INT52:1; + vuint32_t INT51:1; + vuint32_t INT50:1; + vuint32_t INT49:1; + vuint32_t INT48:1; + vuint32_t INT47:1; + vuint32_t INT46:1; + vuint32_t INT45:1; + vuint32_t INT44:1; + vuint32_t INT43:1; + vuint32_t INT42:1; + vuint32_t INT41:1; + vuint32_t INT40:1; + vuint32_t INT39:1; + vuint32_t INT38:1; + vuint32_t INT37:1; + vuint32_t INT36:1; + vuint32_t INT35:1; + vuint32_t INT34:1; + vuint32_t INT33:1; + vuint32_t INT32:1; + } B; + } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t INT31:1; + vuint32_t INT30:1; + vuint32_t INT29:1; + vuint32_t INT28:1; + vuint32_t INT27:1; + vuint32_t INT26:1; + vuint32_t INT25:1; + vuint32_t INT24:1; + vuint32_t INT23:1; + vuint32_t INT22:1; + vuint32_t INT21:1; + vuint32_t INT20:1; + vuint32_t INT19:1; + vuint32_t INT18:1; + vuint32_t INT17:1; + vuint32_t INT16:1; + vuint32_t INT15:1; + vuint32_t INT14:1; + vuint32_t INT13:1; + vuint32_t INT12:1; + vuint32_t INT11:1; + vuint32_t INT10:1; + vuint32_t INT09:1; + vuint32_t INT08:1; + vuint32_t INT07:1; + vuint32_t INT06:1; + vuint32_t INT05:1; + vuint32_t INT04:1; + vuint32_t INT03:1; + vuint32_t INT02:1; + vuint32_t INT01:1; + vuint32_t INT00:1; + } B; + } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t ERR63:1; + vuint32_t ERR62:1; + vuint32_t ERR61:1; + vuint32_t ERR60:1; + vuint32_t ERR59:1; + vuint32_t ERR58:1; + vuint32_t ERR57:1; + vuint32_t ERR56:1; + vuint32_t ERR55:1; + vuint32_t ERR54:1; + vuint32_t ERR53:1; + vuint32_t ERR52:1; + vuint32_t ERR51:1; + vuint32_t ERR50:1; + vuint32_t ERR49:1; + vuint32_t ERR48:1; + vuint32_t ERR47:1; + vuint32_t ERR46:1; + vuint32_t ERR45:1; + vuint32_t ERR44:1; + vuint32_t ERR43:1; + vuint32_t ERR42:1; + vuint32_t ERR41:1; + vuint32_t ERR40:1; + vuint32_t ERR39:1; + vuint32_t ERR38:1; + vuint32_t ERR37:1; + vuint32_t ERR36:1; + vuint32_t ERR35:1; + vuint32_t ERR34:1; + vuint32_t ERR33:1; + vuint32_t ERR32:1; + } B; + } ERH; /* DMA Error High @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t ERR31:1; + vuint32_t ERR30:1; + vuint32_t ERR29:1; + vuint32_t ERR28:1; + vuint32_t ERR27:1; + vuint32_t ERR26:1; + vuint32_t ERR25:1; + vuint32_t ERR24:1; + vuint32_t ERR23:1; + vuint32_t ERR22:1; + vuint32_t ERR21:1; + vuint32_t ERR20:1; + vuint32_t ERR19:1; + vuint32_t ERR18:1; + vuint32_t ERR17:1; + vuint32_t ERR16:1; + vuint32_t ERR15:1; + vuint32_t ERR14:1; + vuint32_t ERR13:1; + vuint32_t ERR12:1; + vuint32_t ERR11:1; + vuint32_t ERR10:1; + vuint32_t ERR09:1; + vuint32_t ERR08:1; + vuint32_t ERR07:1; + vuint32_t ERR06:1; + vuint32_t ERR05:1; + vuint32_t ERR04:1; + vuint32_t ERR03:1; + vuint32_t ERR02:1; + vuint32_t ERR01:1; + vuint32_t ERR00:1; + } B; + } ERL; /* DMA Error Low @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t HRS63:1; + vuint32_t HRS62:1; + vuint32_t HRS61:1; + vuint32_t HRS60:1; + vuint32_t HRS59:1; + vuint32_t HRS58:1; + vuint32_t HRS57:1; + vuint32_t HRS56:1; + vuint32_t HRS55:1; + vuint32_t HRS54:1; + vuint32_t HRS53:1; + vuint32_t HRS52:1; + vuint32_t HRS51:1; + vuint32_t HRS50:1; + vuint32_t HRS49:1; + vuint32_t HRS48:1; + vuint32_t HRS47:1; + vuint32_t HRS46:1; + vuint32_t HRS45:1; + vuint32_t HRS44:1; + vuint32_t HRS43:1; + vuint32_t HRS42:1; + vuint32_t HRS41:1; + vuint32_t HRS40:1; + vuint32_t HRS39:1; + vuint32_t HRS38:1; + vuint32_t HRS37:1; + vuint32_t HRS36:1; + vuint32_t HRS35:1; + vuint32_t HRS34:1; + vuint32_t HRS33:1; + vuint32_t HRS32:1; + } B; + } HRSH; /* hardware request status high @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t HRS31:1; + vuint32_t HRS30:1; + vuint32_t HRS29:1; + vuint32_t HRS28:1; + vuint32_t HRS27:1; + vuint32_t HRS26:1; + vuint32_t HRS25:1; + vuint32_t HRS24:1; + vuint32_t HRS23:1; + vuint32_t HRS22:1; + vuint32_t HRS21:1; + vuint32_t HRS20:1; + vuint32_t HRS19:1; + vuint32_t HRS18:1; + vuint32_t HRS17:1; + vuint32_t HRS16:1; + vuint32_t HRS15:1; + vuint32_t HRS14:1; + vuint32_t HRS13:1; + vuint32_t HRS12:1; + vuint32_t HRS11:1; + vuint32_t HRS10:1; + vuint32_t HRS09:1; + vuint32_t HRS08:1; + vuint32_t HRS07:1; + vuint32_t HRS06:1; + vuint32_t HRS05:1; + vuint32_t HRS04:1; + vuint32_t HRS03:1; + vuint32_t HRS02:1; + vuint32_t HRS01:1; + vuint32_t HRS00:1; + } B; + } HRSL; /* hardware request status low @baseaddress + 0x34 */ + + uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ + + union { + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */ + + uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */ + + /* Select one of the following declarations depending on the DMA mode chosen */ + struct EDMA_TCD_STD_tag TCD[64]; /* Standard Format */ + /* struct EDMA_TCD_alt1_tag TCD[64]; */ /* CITER/BITER Link */ + /* struct EDMA_TCD_alt2_tag TCD[64]; */ /* Minor Loop Offset */ + + }; + + + +/****************************************************************************/ +/* MODULE : XBAR */ +/****************************************************************************/ + struct XBAR_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */ + vuint32_t:1; + vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:4; /* Master 2 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */ + vuint32_t:1; + vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */ + } B; + } MPR0; /* Master Priority Register for Slave port 0 (Flash) @baseaddress + 0x00 */ + + int32_t XBAR_reserved_0004[3]; /* 0x0004 - 0x000F */ + + union { + vuint32_t R; + struct { + vuint32_t RO:1; + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t:1; + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; + vuint32_t:2; + vuint32_t PCTL:2; + vuint32_t:1; + vuint32_t PARK:3; + } B; + } SGPCR0; /* Slave General Purpose Control Register 0 (Flash) @baseaddress + 0x10 */ + + int32_t XBAR_reserved_0014[59]; /* 0x0014 - 0x01FF */ + + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */ + vuint32_t:1; + vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:4; /* Master 2 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */ + vuint32_t:1; + vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */ + } B; + } MPR1; /* Master Priority Register for Slave port 1 (EBI) @baseaddress + 0x100 */ + + int32_t XBAR_reserved_0100[3]; /* 0x0100 - 0x010F */ + + union { + vuint32_t R; + struct { + vuint32_t RO:1; + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t:1; + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; + vuint32_t:2; + vuint32_t PCTL:2; + vuint32_t:1; + vuint32_t PARK:3; + } B; + } SGPCR1; /* Slave General Purpose Control Register 1 (EBI) @baseaddress + 0x110 */ + + int32_t XBAR_reserved_0114[59]; /* 0x0114 - 0x01FF */ + + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */ + vuint32_t:1; + vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:4; /* Master 2 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */ + vuint32_t:1; + vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */ + } B; + } MPR2; /* Master Priority Register for Slave port 2 (RAM) @baseaddress + 0x200 */ + + int32_t XBAR_reserved_0204[3]; /* 0x0204 - 0x020F */ + + union { + vuint32_t R; + struct { + vuint32_t RO:1; + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t:1; + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; + vuint32_t:2; + vuint32_t PCTL:2; + vuint32_t:1; + vuint32_t PARK:3; + } B; + } SGPCR2; /* Slave General Purpose Control Register 2 (RAM)@baseaddress + 0x210 */ + + int32_t XBAR_reserved_0214[59]; /* 0x0214 - 0x02FF */ + + /* Slave General Purpose Control Register 3 @baseaddress + 0x310 - not implemented */ + + int32_t XBAR_reserved_0300[64]; /* 0x0300 - 0x03FF */ + + /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ + + int32_t XBAR_reserved_0400[64]; /* 0x0400 - 0x04FF */ + + /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ + + int32_t XBAR_reserved_0500[64]; /* 0x0500 - 0x05FF */ + + /* Slave Port 6 not implemented @baseaddress + 0x610 */ + + int32_t XBAR_reserved_0600[64]; /* 0x0600 - 0x06FF */ + + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */ + vuint32_t:1; + vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:4; /* Master 2 Priority - Not implemented */ + vuint32_t:1; + vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */ + vuint32_t:1; + vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */ + } B; + } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ + + int32_t XBAR_reserved_0704[3]; /* 0x0704 - 0x070F */ + + union { + vuint32_t R; + struct { + vuint32_t RO:1; + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t:1; + vuint32_t:1; + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; + vuint32_t:2; + vuint32_t PCTL:2; + vuint32_t:1; + vuint32_t PARK:3; + } B; + } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ + + int32_t XBAR_reserved_0714[59]; /* 0x0714 - 0x07FF */ + + int32_t XBAR_reserved_0800[3584]; /* 0x0800-0x3FFF */ + + }; + + +/****************************************************************************/ +/* MODULE : PBRIDGE Peripheral Bridge */ +/****************************************************************************/ + + struct PBRIDGE_tag { + + union { /* Master Privilege Registers 0-7 @baseaddress + 0x00*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MTR0:1; /* z4 core: Master 0 Trusted for Reads */ + vuint32_t MTW0:1; /* z4 core: Master 0 Trusted for Writes */ + vuint32_t MPL0:1; /* z4 core: Master 0 Priviledge Level */ + vuint32_t:13; + vuint32_t MTR4:1; /* DMA: Master 4 Trusted for Reads */ + vuint32_t MTW4:1; /* DMA: Master 4 Trusted for Writes */ + vuint32_t MPL4:1; /* DMA: Master 4 Priviledge Level */ + vuint32_t:5; + vuint32_t MTR6:1; /* FlexRay: Master 6 Trusted for Reads */ + vuint32_t MTW6:1; /* FlexRay: Master 6 Trusted for Writes */ + vuint32_t MPL6:1; /* FlexRay: Master 6 Priviledge Level */ + vuint32_t:1; + vuint32_t MTR7:1; /* EBI: Master 7 Trusted for Reads */ + vuint32_t MTW7:1; /* EBI: Master 7 Trusted for Writes */ + vuint32_t MPL7:1; /* EBI: Master 7 Priviledge Level */ + } B; + } MPCR; + + union { /* Master Privilege Registers 8-15 @baseaddress + 0x04*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MTR0:1; /* Nexus: Master 8 Trusted for Reads */ + vuint32_t MTW0:1; /* Nexus: Master 8 Trusted for Writes */ + vuint32_t MPL0:1; /* Nexus: Master 8 Priviledge Level */ + vuint32_t:28; + } B; + } MPCR1; + + uint32_t PRIDGE_reserved0008[6]; /* 0x0008-0x001F */ + + union { /* Peripheral Access Conrol Registers 0-7 @baseaddress + 0x20*/ + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t SP1:1; /* Crossbar: Supervisor Protect */ + vuint32_t WP1:1; /* Crossbar: Write Protect */ + vuint32_t TP1:1; /* Crossbar: Trusted Protect */ + vuint32_t:9; + vuint32_t SP4:1; /* MPU: Supervisor Protect */ + vuint32_t WP4:1; /* MPU: Write Protect */ + vuint32_t TP4:1; /* MPU: Trusted Protect */ + vuint32_t:12; + } B; + } PACR0; + + union { /* Peripheral Access Conrol Registers 8-15 @baseaddress + 0x24*/ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t SP6:1; /* SWT: Supervisor Protect */ + vuint32_t WP6:1; /* SWT: Write Protect */ + vuint32_t TP6:1; /* SWT: Trusted Protect */ + vuint32_t:1; + vuint32_t SP7:1; /* STM: Supervisor Protect */ + vuint32_t WP7:1; /* STM: Write Protect */ + vuint32_t TP7:1; /* STM: Trusted Protect */ + } B; + } PACR1; + + union { /* Peripheral Access Conrol Registers 16-23 @baseaddress + 0x28*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* ECSM: Supervisor Protect */ + vuint32_t WP0:1; /* ECSM: Write Protect */ + vuint32_t TP0:1; /* ECSM: Trusted Protect */ + vuint32_t:1; + vuint32_t SP1:1; /* DMA: Supervisor Protect */ + vuint32_t WP1:1; /* DMA: Write Protect */ + vuint32_t TP1:1; /* DMA: Trusted Protect */ + vuint32_t:1; + vuint32_t SP2:1; /* INTC: Supervisor Protect */ + vuint32_t WP2:1; /* INTC: Write Protect */ + vuint32_t TP2:1; /* INTC: Trusted Protect */ + vuint32_t:20; + } B; + } PACR2; + + union { /* Peripheral Access Conrol Registers 24-31 @baseaddress + 0x2C*/ + vuint32_t R; + struct { + vuint32_t:32; + } B; + } PACR3; + + uint32_t PRIDGE_reserved0030[4]; /* 0x0030-0x003C */ + + union { /* Off-Platform Access Control Registers 0-7 @baseaddress + 0x40*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* eQADC: Supervisor Protect */ + vuint32_t WP0:1; /* eQADC: Write Protect */ + vuint32_t TP0:1; /* eQADC: Trusted Protect */ + vuint32_t:5; + vuint32_t SP2:1; /* Dec Filter A: Supervisor Protect */ + vuint32_t WP2:1; /* Dec Filter A: Write Protect */ + vuint32_t TP2:1; /* Dec Filter A: Trusted Protect */ + vuint32_t:1; + vuint32_t SP3:1; /* Dec Filter B: Supervisor Protect */ + vuint32_t WP3:1; /* Dec Filter B: Write Protect */ + vuint32_t TP3:1; /* Dec Filter B: Trusted Protect */ + vuint32_t:5; + vuint32_t SP5:1; /* DSPIB: Supervisor Protect */ + vuint32_t WP5:1; /* DSPIB: Write Protect */ + vuint32_t TP5:1; /* DSPIB: Trusted Protect */ + vuint32_t:1; + vuint32_t SP6:1; /* DSPIC: Supervisor Protect */ + vuint32_t WP6:1; /* DSPIC: Write Protect */ + vuint32_t TP6:1; /* DSPIC: Trusted Protect */ + vuint32_t:1; + vuint32_t SP7:1; /* DSPID: Supervisor Protect */ + vuint32_t WP7:1; /* DSPID: Write Protect */ + vuint32_t TP7:1; /* DSPID: Trusted Protect */ + } B; + } OPACR0; + + union { /* Off-Platform Access Control Registers 8-15 @baseaddress + 0x44*/ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t SP4:1; /* eSCIA: Supervisor Protect */ + vuint32_t WP4:1; /* eSCIA: Write Protect */ + vuint32_t TP4:1; /* eSCIA: Trusted Protect */ + vuint32_t:1; + vuint32_t SP5:1; /* eSCIB: Supervisor Protect */ + vuint32_t WP5:1; /* eSCIB: Write Protect */ + vuint32_t TP5:1; /* eSCIB: Trusted Protect */ + vuint32_t:1; + vuint32_t SP6:1; /* eSCIC: Supervisor Protect */ + vuint32_t WP6:1; /* eSCIC: Write Protect */ + vuint32_t TP6:1; /* eSCIC: Trusted Protect */ + vuint32_t:4; + } B; + } OPACR1; + + union { /* Off-Platform Access Control Registers 16-23 @baseaddress + 0x48*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* FlexCANA: Supervisor Protect */ + vuint32_t WP0:1; /* FlexCANA: Write Protect */ + vuint32_t TP0:1; /* FlexCANA: Trusted Protect */ + vuint32_t:1; + vuint32_t SP1:1; /* FlexCANB: Supervisor Protect */ + vuint32_t WP1:1; /* FlexCANB: Write Protect */ + vuint32_t TP1:1; /* FlexCANB: Trusted Protect */ + vuint32_t:1; + vuint32_t SP2:1; /* FlexCANC: Supervisor Protect */ + vuint32_t WP2:1; /* FlexCANC: Write Protect */ + vuint32_t TP2:1; /* FlexCANC: Trusted Protect */ + vuint32_t:20; + } B; + } OPACR2; + + union { /* Off-Platform Access Control Registers 24-31 @baseaddress + 0x4C*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* FlexRay: Supervisor Protect */ + vuint32_t WP0:1; /* FlexRay: Write Protect */ + vuint32_t TP0:1; /* FlexRay: Trusted Protect */ + vuint32_t:9; + vuint32_t SP3:1; /* SIM: Supervisor Protect */ + vuint32_t WP3:1; /* SIM: Write Protect */ + vuint32_t TP3:1; /* SIM: Trusted Protect */ + vuint32_t:13; + vuint32_t SP7:1; /* BAM: Supervisor Protect */ + vuint32_t WP7:1; /* BAM: Write Protect */ + vuint32_t TP7:1; /* BAM: Trusted Protect */ + } B; + } OPACR3; + + union { /* Off-Platform Access Control Registers 32-39 @baseaddress + 0x50*/ + vuint32_t R; + struct { + vuint32_t:32; + } B; + } OPACR4; + + union { /* Off-Platform Access Control Registers 40-47 @baseaddress + 0x54*/ + vuint32_t R; + struct { + vuint32_t:32; + } B; + } OPACR5; + + union { /* Off-Platform Access Control Registers 48-55 @baseaddress + 0x58*/ + vuint32_t R; + struct { + vuint32_t:32; + } B; + } OPACR6; + + union { /* Off-Platform Access Control Registers 56-63 @baseaddress + 0x5C*/ + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SP2:1; /* CRC: Supervisor Protect */ + vuint32_t WP2:1; /* CRC: Write Protect */ + vuint32_t TP2:1; /* CRC: Trusted Protect */ + vuint32_t:20; + } B; + } OPACR7; + + union { /* Off-Platform Access Control Registers 64-71 @baseaddress + 0x60*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* FMPLL: Supervisor Protect */ + vuint32_t WP0:1; /* FMPLL: Write Protect */ + vuint32_t TP0:1; /* FMPLL: Trusted Protect */ + vuint32_t:1; + vuint32_t SP1:1; /* EBI: Supervisor Protect */ + vuint32_t WP1:1; /* EBI: Write Protect */ + vuint32_t TP1:1; /* EBI: Trusted Protect */ + vuint32_t:1; + vuint32_t SP2:1; /* FlashA: Supervisor Protect */ + vuint32_t WP2:1; /* FlashA: Write Protect */ + vuint32_t TP2:1; /* FlashA: Trusted Protect */ + vuint32_t:1; + vuint32_t SP3:1; /* FlashB: Supervisor Protect */ + vuint32_t WP3:1; /* FlashB: Write Protect */ + vuint32_t TP3:1; /* FlashB: Trusted Protect */ + vuint32_t:1; + vuint32_t SP4:1; /* SIU: Supervisor Protect */ + vuint32_t WP4:1; /* SIU: Write Protect */ + vuint32_t TP4:1; /* SIU: Trusted Protect */ + vuint32_t:9; + vuint32_t SP7:1; /* DTS: Supervisor Protect */ + vuint32_t WP7:1; /* DTS: Write Protect */ + vuint32_t TP7:1; /* DTS: Trusted Protect */ + } B; + } OPACR8; + + union { /* Off-Platform Access Control Registers 72-79 @baseaddress + 0x64*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* eMIOS: Supervisor Protect */ + vuint32_t WP0:1; /* eMIOS: Write Protect */ + vuint32_t TP0:1; /* eMIOS: Trusted Protect */ + vuint32_t:25; + vuint32_t SP7:1; /* PMC: Supervisor Protect */ + vuint32_t WP7:1; /* PMC: Write Protect */ + vuint32_t TP7:1; /* PMC: Trusted Protect */ + } B; + } OPACR9; + + union { /* Off-Platform Access Control Registers 80-87 @baseaddress + 0x68*/ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SP0:1; /* eTPU2: Supervisor Protect */ + vuint32_t WP0:1; /* eTPU2: Write Protect */ + vuint32_t TP0:1; /* eTPU2: Trusted Protect */ + vuint32_t:1; + vuint32_t SP1:1; /* REACM: Supervisor Protect */ + vuint32_t WP1:1; /* REACM: Write Protect */ + vuint32_t TP1:1; /* REACM: Trusted Protect */ + vuint32_t:1; + vuint32_t SP2:1; /* eTPU PRAM: Supervisor Protect */ + vuint32_t WP2:1; /* eTPU PRAM: Write Protect */ + vuint32_t TP2:1; /* eTPU PRAM: Trusted Protect */ + vuint32_t:1; + vuint32_t SP3:1; /* eTPU PRAM mirror: Supervisor Protect */ + vuint32_t WP3:1; /* eTPU PRAM mirror: Write Protect */ + vuint32_t TP3:1; /* eTPU PRAM mirror: Trusted Protect */ + vuint32_t:1; + vuint32_t SP4:1; /* eTPU CRAM: Supervisor Protect */ + vuint32_t WP4:1; /* eTPU CRAM: Write Protect */ + vuint32_t TP4:1; /* eTPU CRAM: Trusted Protect */ + vuint32_t:12; + } B; + } OPACR10; + + union { /* Off-Platform Access Control Registers 88-95 @baseaddress + 0x6C*/ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t SP4:1; /* PIT: Supervisor Protect */ + vuint32_t WP4:1; /* PIT: Write Protect */ + vuint32_t TP4:1; /* PIT: Trusted Protect */ + vuint32_t:12; + } B; + } OPACR11; + + uint32_t PRIDGE_reserved0070[4068]; /* 0x0070-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + + struct FLASH_tag { + + union { /* Module Configuration Register @baseaddress + 0x00*/ + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t SIZE:3; + vuint32_t:1; + vuint32_t LAS:3; + vuint32_t:3; + vuint32_t MAS:1; + vuint32_t EER:1; + vuint32_t RWE:1; + vuint32_t SBC:1; + vuint32_t:1; + vuint32_t PEAS:1; + vuint32_t DONE:1; + vuint32_t PEG:1; + vuint32_t:4; + vuint32_t PGM:1; + vuint32_t PSUS:1; + vuint32_t ERS:1; + vuint32_t ESUS:1; + vuint32_t EHV:1; + } B; + } MCR; + + union { + vuint32_t R; + struct { + vuint32_t LME:1; + vuint32_t:10; + vuint32_t SLOCK:1; + vuint32_t:2; + vuint32_t MLOCK:2; + vuint32_t:6; + vuint32_t LLOCK:10; + } B; /* Low/Mid Address Space Block Locking Register @baseaddress + 0x04*/ + } LMLR; + + union { + vuint32_t R; + struct { + vuint32_t HBE:1; + vuint32_t:25; + vuint32_t HBLOCK:6; + } B; + } HLR; /* High Address Space Block Locking Register @baseaddress + 0x08*/ + + union { + vuint32_t R; + struct { + vuint32_t SLE:1; + vuint32_t:10; + vuint32_t SSLOCK:1; + vuint32_t:2; + vuint32_t SMLOCK:2; + vuint32_t:6; + vuint32_t SLLOCK:10; + } B; + } SLMLR; /* Secondary Low/Mid Block Locking Register @baseaddress + 0x0C*/ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSEL:2; + vuint32_t:6; + vuint32_t LSEL:10; + } B; + } LMSR; /* Low/Mid Address Space Block Select Register @baseaddress + 0x10*/ + + union { + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HBSEL:6; + } B; + } HSR; /* High Address Space Block Select Register @baseaddress + 0x14*/ + + union { + vuint32_t R; + struct { + vuint32_t SAD:1; + vuint32_t:13; + vuint32_t ADDR:15; + vuint32_t:3; + } B; + } AR; /* Address Register @baseaddress + 0x18*/ + + union { + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t:1; /* Reserved */ + vuint32_t:1; /* EBI Testing - Reserved */ + vuint32_t M6PFE:1; /* FlexRay */ + vuint32_t:1; /* Reserved */ + vuint32_t M4PFE:1; /* eDMA */ + vuint32_t:1; /* Reserved */ + vuint32_t:1; /* Reserved */ + vuint32_t M1PFE:1; /* z4 Core Load/Store */ + vuint32_t M0PFE:1; /* z4 Core Instruction */ + vuint32_t APC:3; + vuint32_t WWSC:2; + vuint32_t RWSC:3; + vuint32_t:1; + vuint32_t DPFEN:1; + vuint32_t:1; + vuint32_t IPFEN:1; + vuint32_t:1; + vuint32_t PFLIM:2; + vuint32_t BFEN:1; + } B; + } BIUCR; /* Bus Interface Unit Configuration Register 1 @baseaddress + 0x1C*/ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t:2; /* Reserved */ + vuint32_t:2; /* EBI Testing - Reserved */ + vuint32_t M6AP:2; /* FlexRay */ + vuint32_t:2; /* Reserved */ + vuint32_t M4AP:2; /* eDMA_A */ + vuint32_t:2; /* Reserved */ + vuint32_t:2; /* Reserved */ + vuint32_t M1AP:2; /* z4 Core Load/Store */ + vuint32_t M0AP:2; /* z4 Core Instruction */ + } B; + } BIUAPR; /*Bus Interface Unit Access Protection Register @baseaddress + 0x20*/ + + union { + vuint32_t R; + struct { + vuint32_t LBCFG:2; + vuint32_t:30; + } B; + } BIUCR2; /* Bus Interface Unit Configuration Register 2 @baseaddress + 0x24*/ + + uint32_t FLASH_reserved0028[5]; /* 0x0028-0x003B */ + + union { /* User Test 0 (UT0) register@baseaddress + 0x3C */ + vuint32_t R; + struct { + vuint32_t UTE:1; /* User test enable (Read/Clear) */ + vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ + vuint32_t:6; /* Reserved */ + vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ + vuint32_t:9; /* Reserved */ + vuint32_t:1; /* Reserved (Read/Write) */ + vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ + vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ + vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ + vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ + vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ + vuint32_t AID:1; /* Array Integrity Done (Read Only) */ + } B; + } UT0; + + union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT1; + + union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ + vuint32_t R; + struct { + vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ + } B; + } UMISR[5]; + + uint32_t FLASH_reserved005C[4073]; /* 0x005C-0x3FFF */ + }; + + + + +/****************************************************************************/ +/* MODULE : EBI */ +/****************************************************************************/ + struct CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; + vuint32_t:3; + vuint32_t PS:1; + vuint32_t:3; + vuint32_t AD_MUX:1; + vuint32_t BL:1; + vuint32_t WEBS:1; + vuint32_t TBDIP:1; + vuint32_t:1; + vuint32_t SETA:1; + vuint32_t BI:1; + vuint32_t V:1; + } B; + } BR; /* EBI Base Registers (BR) @baseaddress + 0x10 - 0x28 */ + union { + vuint32_t R; + struct { + vuint32_t AM:17; + vuint32_t:7; + vuint32_t SCY:4; + vuint32_t:1; + vuint32_t BSCY:2; + vuint32_t:1; + } B; + } OR; /* EBI Option Registers (OR) @baseaddress + 0x14 - 0x2C */ + }; + struct CAL_CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; + vuint32_t:3; + vuint32_t PS:1; + vuint32_t:3; + vuint32_t AD_MUX:1; + vuint32_t BL:1; + vuint32_t WEBS:1; + vuint32_t TBDIP:1; + vuint32_t:1; + vuint32_t SETA:1; + vuint32_t BI:1; + vuint32_t V:1; + } B; + } BR; /* EBI CAL Base Registers (CAL_BR) @baseaddress + 0x40 - 0x58 */ + union { + vuint32_t R; + struct { + vuint32_t AM:17; + vuint32_t:7; + vuint32_t SCY:4; + vuint32_t:1; + vuint32_t BSCY:2; + vuint32_t:1; + + } B; + } OR; /* EBI CAL Option Registers (CAL_OR) @baseaddress + 0x44 - 0x5C */ + }; + + + struct EBI_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ACGE:1; + vuint32_t:8; + vuint32_t MDIS:1; + vuint32_t:3; + vuint32_t D16_31:1; + vuint32_t AD_MUX:1; + vuint32_t DBM:1; + } B; + } MCR; /* EBI Module Configuration Register (MCR) @baseaddress + 0x00 */ + + uint32_t EBI_reserved0004[1]; /* 0x0004-0x0008 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t BMTF:1; + } B; + } TESR; /* EBI Transfer Error Status Register (TESR) @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t BMT:8; + vuint32_t BME:1; + vuint32_t:7; + } B; + } BMCR; /* EBI Bus Montior Control Register (BMCR) @baseaddress + 0x0C */ + + struct CS_tag CS[4]; /* EBI CS Registers (BR / OR) @baseaddress + 0x10 - 0x2C */ + + uint32_t EBI_reserved0030[4]; /* 0x0030 - 0x003C */ + + struct CAL_CS_tag CAL_CS[4]; /* EBI CAL_CS Registers (CAL_BR / CAL_OR) @baseaddress + 0x40 - 0x5C */ + }; + + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:18; /* Reserved */ + vuint32_t:1; /* Reserved */ + vuint32_t:4; /* Reserved */ + vuint32_t:1; /* Reserved */ + vuint32_t:2; /* Reserved */ + vuint32_t VTES:1; /* Vector Table Entry Size */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN:1; /* Hardware Vector Enable */ + } B; + } MCR; /* INTC Module Configuration Register (MCR) @baseaddress + 0x00 */ + + int32_t INTC_Reserved_0004[1]; /* 0x0004 - 0x0007 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t PRI:4; /* Priority */ + } B; + } CPR; /* INTC Current Priority Register (CPR) @baseaddress + 0x08 */ + + int32_t INTC_reserved_000C; /* 0x000C - 0x000F */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; /* Vector Table Base Address */ + vuint32_t INTVEC:9; /* Interrupt Vector */ + vuint32_t:2; /* Reserved */ + } B; + } IACKR; /* INTC Interrupt Acknowledge Register (IACKR) @baseaddress + 0x10 */ + + int32_t INTC_Reserved_0014; /* 0x0014 - 0x00017 */ + + union { + vuint32_t R; + struct { + vuint32_t:32; /* Reserved */ + } B; + } EOIR; /* INTC End of Interrupt Register (EOIR) @baseaddress + 0x18 */ + + int32_t INTC_Reserved_001C; /* 0x001C - 0x001F */ + + union { + vuint8_t R; + struct { + vuint8_t:6; /* Reserved */ + vuint8_t SET:1; /* Set Flag bits */ + vuint8_t CLR:1; /* Clear Flag bits */ + } B; + } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) @baseaddress + 0x20 */ + + int32_t INTC_Reserved_0028[6]; /* 0x0028 - 0x003F */ + + union { + vuint8_t R; + struct { + vuint8_t:2; /* Reserved */ + vuint8_t:2; /* Reserved */ + vuint8_t PRI:4; /* Priority Select */ + } B; + } PSR[512]; /* INTC Priority Select Registers (PSR) @baseaddress + 0x40 */ + + }; + + +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + union { + vuint32_t R; + struct { + vuint32_t S_F:1; /* Identifies the Manufacturer */ + vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) */ + vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity */ + vuint32_t TEMP_RANGE:2; /* Define maximum operating range */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t MAX_FREQ:2; /* Define maximum device speed */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V */ + vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product */ + vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ + vuint32_t:2; /* Reserved for future enhancements */ + vuint32_t EE:1; /* Indicates if Data Flash is present */ + vuint32_t:3; /* Reserved for future enhancements */ + vuint32_t FR:1; /* Indicates if Data FlexRay is present */ + } B; + } MIDR2; /* MCU ID Register 2 @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t PARTNUM:16; /* Device part number */ + vuint32_t CSP:1; /* CSP configuration */ + vuint32_t PKG:5; /* Indicate the package the die is mounted in. */ + vuint32_t:2; /* Reserved */ + vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ + } B; + } MIDR; /* MCU ID Register (MIDR) @baseaddress + 0x4 */ + + int32_t SIU_Reserved_0008; /* 0x0008 - 0x000B */ + + union { + vuint32_t R; + struct { + vuint32_t PORS:1; /* Power-On Reset Status */ + vuint32_t ERS:1; /* External Reset Status */ + vuint32_t LLRS:1; /* Loss of Lock Reset Status */ + vuint32_t LCRS:1; /* Loss of Clock Reset Status */ + vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ + vuint32_t :1; + vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status */ + vuint32_t:7; + vuint32_t SSRS:1; /* Software System Reset Status */ + vuint32_t SERF:1; /* Software External Reset Flag */ + vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ + vuint32_t:11; + vuint32_t ABR:1; /* Auto Baud Rate */ + vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ + vuint32_t RGF:1; /* RESET Glitch Flag */ + } B; + } RSR; /* Reset Status Register (SIU_RSR) @baseaddress + 0xC */ + + union { + vuint32_t R; + struct { + vuint32_t SSR:1; /* Software System Reset */ + vuint32_t SER:1; /* Software External Reset */ + vuint32_t:14; + vuint32_t:1; + vuint32_t:15; + } B; + } SRCR; /* System Reset Control Register (SRCR) @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI:1; /* Non-Maskable Interrupt Flag */ + vuint32_t:7; /* */ + vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform */ + vuint32_t:7; /* */ + vuint32_t EIF15:1; /* External Interrupt Request Flag x */ + vuint32_t EIF14:1; /* External Interrupt Request Flag x */ + vuint32_t EIF13:1; /* External Interrupt Request Flag x */ + vuint32_t EIF12:1; /* External Interrupt Request Flag x */ + vuint32_t EIF11:1; /* External Interrupt Request Flag x */ + vuint32_t EIF10:1; /* External Interrupt Request Flag x */ + vuint32_t EIF9:1; /* External Interrupt Request Flag x */ + vuint32_t EIF8:1; /* External Interrupt Request Flag x */ + vuint32_t EIF7:1; /* External Interrupt Request Flag x */ + vuint32_t EIF6:1; /* External Interrupt Request Flag x */ + vuint32_t EIF5:1; /* External Interrupt Request Flag x */ + vuint32_t EIF4:1; /* External Interrupt Request Flag x */ + vuint32_t EIF3:1; /* External Interrupt Request Flag x */ + vuint32_t EIF2:1; /* External Interrupt Request Flag x */ + vuint32_t EIF1:1; /* External Interrupt Request Flag x */ + vuint32_t EIF0:1; /* External Interrupt Request Flag x */ + } B; + } EISR; /* SIU External Interrupt Status Register (EISR) @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection */ + vuint32_t:7; + vuint32_t NMISEL0:1; /* SWT Interrupt Platform Input Selection */ + vuint32_t:7; + vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ + } B; + } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) @baseaddress + 0x18 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ + vuint32_t DIRS2:1; /* DMA/Interrupt Request Select x */ + vuint32_t DIRS1:1; /* DMA/Interrupt Request Select x */ + vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ + } B; + } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) @baseaddress + 0x1C */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t OVF15:1; /* Overrun Flag x */ + vuint32_t OVF14:1; /* Overrun Flag x */ + vuint32_t OVF13:1; /* Overrun Flag x */ + vuint32_t OVF12:1; /* Overrun Flag x */ + vuint32_t OVF11:1; /* Overrun Flag x */ + vuint32_t OVF10:1; /* Overrun Flag x */ + vuint32_t OVF9:1; /* Overrun Flag x */ + vuint32_t OVF8:1; /* Overrun Flag x */ + vuint32_t OVF7:1; /* Overrun Flag x */ + vuint32_t OVF6:1; /* Overrun Flag x */ + vuint32_t OVF5:1; /* Overrun Flag x */ + vuint32_t OVF4:1; /* Overrun Flag x */ + vuint32_t OVF3:1; /* Overrun Flag x */ + vuint32_t OVF2:1; /* Overrun Flag x */ + vuint32_t OVF1:1; /* Overrun Flag x */ + vuint32_t OVF0:1; /* Overrun Flag x */ + } B; + } OSR; /* Overrun Status Register (OSR) @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ORE15:1; /* Overrun Request Enable x */ + vuint32_t ORE14:1; /* Overrun Request Enable x */ + vuint32_t ORE13:1; /* Overrun Request Enable x */ + vuint32_t ORE12:1; /* Overrun Request Enable x */ + vuint32_t ORE11:1; /* Overrun Request Enable x */ + vuint32_t ORE10:1; /* Overrun Request Enable x */ + vuint32_t ORE9:1; /* Overrun Request Enable x */ + vuint32_t ORE8:1; /* Overrun Request Enable x */ + vuint32_t ORE7:1; /* Overrun Request Enable x */ + vuint32_t ORE6:1; /* Overrun Request Enable x */ + vuint32_t ORE5:1; /* Overrun Request Enable x */ + vuint32_t ORE4:1; /* Overrun Request Enable x */ + vuint32_t ORE3:1; /* Overrun Request Enable x */ + vuint32_t ORE2:1; /* Overrun Request Enable x */ + vuint32_t ORE1:1; /* Overrun Request Enable x */ + vuint32_t ORE0:1; /* Overrun Request Enable x */ + } B; + } ORER; /* Overrun Request Enable Register (ORER) @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x */ + vuint32_t:7; + vuint32_t NMIRE0:1; /* NMI Falling-Edge Event Enable (SWT) x */ + vuint32_t:7; + vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE7:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE6:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE5:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE2:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE1:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable (NMI Input) x */ + vuint32_t:7; + vuint32_t NMIFE0:1; /* NMI Falling-Edge Event Enable (SWT) x */ + vuint32_t:7; + vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE7:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE6:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE5:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE2:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE1:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DFL:4; /* Digital Filter Length */ + } B; + } IDFR; /* External IRQ Digital Filter Register (IDFR) @baseaddress + 0x30 */ + + int32_t SIU_Reserved_0034[3]; /* 0x0034 - 0x003F */ + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t PA:3; + vuint16_t OBE:1; + vuint16_t IBE:1; + vuint16_t DSC:2; + vuint16_t ODE:1; + vuint16_t HYS:1; + vuint16_t SRC:2; + vuint16_t WPE:1; + vuint16_t WPS:1; + } B; + } PCR[512]; /* Pad Configuration Register (PCR) @baseaddress + 0x40 */ + + int32_t SIU_Reserved_0374[112]; /* 0x0374 - 0x05FF */ + + union { + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDO:1; + } B; + } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) @baseaddress + 0x600 */ + + union { + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDI:1; + } B; + } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) @baseaddress + 0x800 */ + + union { + vuint32_t R; + struct { + vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ + vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ + vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ + vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ + vuint32_t:20; /* */ + } B; + } ETISR; /* eQADC Trigger Input Select Register (ETISR) @baseaddress + 0x900 */ + + union { + vuint32_t R; + struct { + vuint32_t ESEL15:2; /* External IRQ Input Select x */ + vuint32_t ESEL14:2; /* External IRQ Input Select x */ + vuint32_t ESEL13:2; /* External IRQ Input Select x */ + vuint32_t ESEL12:2; /* External IRQ Input Select x */ + vuint32_t ESEL11:2; /* External IRQ Input Select x */ + vuint32_t ESEL10:2; /* External IRQ Input Select x */ + vuint32_t ESEL9:2; /* External IRQ Input Select x */ + vuint32_t ESEL8:2; /* External IRQ Input Select x */ + vuint32_t ESEL7:2; /* External IRQ Input Select x */ + vuint32_t ESEL6:2; /* External IRQ Input Select x */ + vuint32_t ESEL5:2; /* External IRQ Input Select x */ + vuint32_t ESEL4:2; /* External IRQ Input Select x */ + vuint32_t ESEL3:2; /* External IRQ Input Select x */ + vuint32_t ESEL2:2; /* External IRQ Input Select x */ + vuint32_t ESEL1:2; /* External IRQ Input Select x */ + vuint32_t ESEL0:2; /* External IRQ Input Select x */ + } B; + } EIISR; /* External IRQ Input Select Register (EIISR) @baseaddress + 0x904 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SINSELB:2; /* DSPI_B Data Input Select */ + vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select */ + vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select */ + vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select */ + vuint32_t SINSELC:2; /* DSPI_C Data Input Select */ + vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select */ + vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select */ + vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select */ + vuint32_t SINSELD:2; /* DSPI_D Data Input Select */ + vuint32_t SSSELD:2; /* DSPI_D Slave Select Input Select */ + vuint32_t SCKSELD:2; /* DSPI_D Clock Input Select */ + vuint32_t TRIGSELD:2; /* DSPI_D Trigger Input Select */ + } B; + } DISR; /* DSPI Input Select Register (DISR) @baseaddress + 0x908 */ + + union { + vuint32_t R; + struct { + vuint32_t:2; /* */ + vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection */ + vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection */ + vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection */ + vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection */ + vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection */ + vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection */ + } B; + } ISEL3; /* MUX Select Register 3 (ISEL3) @baseaddress + 0x90C */ + + int32_t SIU_Reserved_0910[4]; /* 0x0910 - 0x091F */ + + union { + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t ESEL5:1; + vuint32_t:3; + vuint32_t ESEL4:1; + vuint32_t:3; + vuint32_t ESEL3:1; + vuint32_t:3; + vuint32_t ESEL2:1; + vuint32_t:3; + vuint32_t ESEL1:1; + vuint32_t:3; + vuint32_t ESEL0:1; + } B; + } ISEL8; /* MUX Select Register 8 (ISEL8) @baseaddress + 0x920 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t ETSEL0A:5; + } B; + } ISEL9; /* MUX Select Register 9(ISEL9) @baseaddress + 0x924 */ + + int32_t SIU_Reserved_0928[22]; /* 0x0928 - 0x097F */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MATCH:1; /* Compare Register Match */ + vuint32_t DISNEX:1; /* Disable Nexus */ + vuint32_t:14; + vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable */ + vuint32_t:1; + } B; + } CCR; /* Chip Configuration Register (CCR) @baseaddress + 0x980 */ + + union { + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t ENGDIV:6; + vuint32_t ENGSSE:1; + vuint32_t:3; + vuint32_t EBTS:1; + vuint32_t:1; + vuint32_t EBDF:2; + } B; + } ECCR; /* External Clock Control Register (ECCR) @baseaddress + 0x984 */ + + union { + vuint32_t R; + struct { + vuint32_t CMPAH:32; + } B; + } CARH; /* Compare A High Register (CARH) @baseaddress + 0x988 */ + + union { + vuint32_t R; + struct { + vuint32_t CMPAL:32; + } B; + } CARL; /* Compare A Low Register (CARL) @baseaddress + 0x98C */ + + union { + vuint32_t R; + struct { + vuint32_t CMPBH:32; + } B; + } CBRH; /* Compare B High Register (CBRH) @baseaddress + 0x990 */ + + union { + vuint32_t R; + struct { + vuint32_t CMPBL:32; + } B; + } CBRL; /* Compare B Low Register (CBRL) @baseaddress + 0x994 */ + + int32_t SIU_Reserved_0998[2]; /* 0x0998 - 0x099F */ + + union { + vuint32_t R; + struct { + vuint32_t:15; + vuint32_t CAN_SRC:1; /* CAN 2:1 Mode */ + vuint32_t:11; + vuint32_t BYPASS:1; /* Bypass bit */ + vuint32_t SYSCLKDIV:2; /* System Clock Divide */ + vuint32_t:2; + } B; + } SYSDIV; /* System Clock Register (SYSDIV) @baseaddress + 0x9A0 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ + vuint32_t:2; /* Reserved */ + vuint32_t:1; + vuint32_t:1; /* Reserved */ + vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ + vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ + vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ + vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSSTP:1; /* Stop mode request */ + vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ + vuint32_t:1; /* Reserved */ + vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ + vuint32_t CNBSTP:1; /* FlexCAN B stop request. When asserted, a stop request is sent to the FlexCAN B */ + vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ + vuint32_t SPIDSTP:1; /* DSPI D stop request. When asserted, a stop request is sent to the DSPI D. */ + vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ + vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ + vuint32_t:6; /* Reserved */ + vuint32_t SCICSTP:1; /* eSCI C stop request. When asserted, a stop request is sent to the eSCI C module. */ + vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ + vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ + } B; + } HLT; /* Halt Register (HLT) @baseaddress + 0x9A4 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:2; /* Reserved */ + vuint32_t:1; + vuint32_t:1; /* Reserved */ + vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ + vuint32_t:1; /* Reserved */ + vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t CNBACK:1; /* FlexCAN B stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t SPIDACK:1; /* DSPI D stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:6; /* Reserved */ + vuint32_t SCICACK:1; /* eSCI C stop acknowledge */ + vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ + } B; + } HLTACK; /* Halt Acknowledge Register (HLTACK) @baseaddress + 0x9A8 */ + + int32_t SIU_reserved09AC[2]; /* 0x09AC - 0x09B0 */ + + union { + vuint32_t R; + struct { + vuint32_t EXT_PID_EN:1; /* External PID Selection Enable */ + vuint32_t EXT_PID_SYNC0:1; /* External PID Synchronization 0 */ + vuint32_t:28; /* Reserved */ + vuint32_t EXT_PID6:1; /* EXT_PID6 */ + vuint32_t EXT_PID7:1; /* EXT_PID7 */ + } B; + } EMPCR0; /* Core MMU PID Control Register (EMPCR0) @baseaddress + 0x9B4 */ + + int32_t SIU_reserved09B8[19]; /* 0x09B8 - 0x09B0 */ + + }; + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t PREDIV:3; + vuint32_t MFD:5; + vuint32_t:1; + vuint32_t RFD:3; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t:1; + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:13; + } B; + } SYNCR; /* Synthesizer Control Register (SYNCR) @baseaddress + 0x0000 */ + + union { + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t LOLF:1; + vuint32_t LOC:1; + vuint32_t MODE:1; + vuint32_t PLLSEL:1; + vuint32_t PLLREF:1; + vuint32_t LOCKS:1; + vuint32_t LOCK:1; + vuint32_t LOCF:1; + vuint32_t:2; + } B; + } SYNSR; /* Synthesizer Status Register (SYNSR) @baseaddress + 0x0004 */ + + union { + vuint32_t R; + struct { + vuint32_t EMODE:1; + vuint32_t CLKCFG:3; + vuint32_t:8; + vuint32_t EPREDIV:4; + vuint32_t:9; + vuint32_t EMFD:7; + } B; + } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) @baseaddress + 0x0008 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:17; + vuint32_t ERFD:2; + } B; + } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) @baseaddress + 0x000C */ + + int32_t FMPLL_reserved0010[2]; /* 0x0010-0x0017 */ + + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t MODEN:1; + vuint32_t MODSEL:1; + vuint32_t MODPERIOD:13; + vuint32_t:1; + vuint32_t INCSTEP:15; + } B; + } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) @baseaddress + 0x0018 */ + }; + + +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + union { /* Processor core type */ + vuint16_t R; + } PCT; + + union { /* Platform revision */ + vuint16_t R; + } REV; + + union { /* AXBS Master Configuration */ + vuint16_t R; + } AMC; + + union { /* AXBS Slave Configuration */ + vuint16_t R; + } ASC; + + union { /* IPS Module Configuration */ + vuint32_t R; + } IMC; + + uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */ + + union { /* Miscellaneous Reset Status Register */ + vuint8_t R; + struct { + vuint8_t POR:1; + vuint8_t DIR:1; + vuint8_t SWTR:1; + vuint8_t:5; + } B; + } MRSR; + + uint8_t ECSM_reserved0010[3]; /* 0x0010-0x0012 */ + + union { /* Miscellaneous Wakeup Control */ + vuint8_t R; + struct { + vuint8_t ENBWCR:1; + vuint8_t:3; + vuint8_t PRILVL:4; + } B; + } MWCR; + + uint32_t ecsm_reserved0014[4]; /* 0x0014 - 0x0023 */ + + union { /* Miscellaneous User Defined Control */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t SWSC:1; + vuint32_t:30; + } B; + } MUDCR; + + uint32_t ecsm_reserved0028[6]; /* 0x0028 - 0x003C*/ + + uint8_t ecsm_reserved0040[3]; /* 0x0040 - 0x0042*/ + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t ER1BR:1; + vuint8_t EF1BR:1; + vuint8_t:2; + vuint8_t ERNCR:1; + vuint8_t EFNCR:1; + } B; + } ECR; /* ECC Configuration Register @baseaddress + 0x43 */ + + uint8_t ecsm_reserved0044[3]; /* 0x0044 - 0x0046*/ + + union { + vuint8_t R; + struct { + vuint8_t:2; + vuint8_t R1BC:1; + vuint8_t F1BC:1; + vuint8_t:2; + vuint8_t RNCE:1; + vuint8_t FNCE:1; + } B; + } ESR; /* ECC Status Register @baseaddress + 0x47 */ + + uint8_t ecsm_reserved0048[2]; /* 0x0048 - 0x0049*/ + + union { + vuint16_t R; + struct { + vuint16_t FRCAP:1; + vuint16_t:1; + vuint16_t FRC1BI:1; + vuint16_t FR11BI:1; + vuint16_t:2; + vuint16_t FRCNCI:1; + vuint16_t FR1NCI:1; + vuint16_t:1; + vuint16_t ERRBIT:7; + } B; + } EEGR; /* ECC Error Generation Register @baseaddress + 0x4A */ + + uint32_t ecsm_reserved004C; /* 0x004C - 0x004F*/ + + union { + vuint32_t R; + struct { + vuint32_t FEAR:32; + } B; + } FEAR; /* Flash ECC Address Register @baseaddress + 0x50 */ + + uint16_t ecsm_reserved0054; /* 0x0054 - 0x0055*/ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; + } B; + } FEMR; /* Flash ECC Master Register @baseaddress + 0x56 */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; + vuint8_t PROT1:1; + vuint8_t PROT2:1; + vuint8_t PROT3:1; + } B; + } FEAT; /* Flash ECC Attributes Register @baseaddress + 0x57 */ + + union { + vuint32_t R; + struct { + vuint32_t FEDH:32; + } B; + } FEDRH; /* Flash ECC Data High Register @baseaddress + 0x58 */ + + union { + vuint32_t R; + struct { + vuint32_t FEDL:32; + } B; + } FEDRL; /* Flash ECC Data Low Register @baseaddress + 0x5C */ + + union { + vuint32_t R; + struct { + vuint32_t REAR:32; + } B; + } REAR; /* RAM ECC Address @baseaddress + 0x60 */ + + uint8_t ecsm_reserved0064; /* 0x0064 - 0x0065*/ + + union { + vuint8_t R; + struct { + vuint8_t PRESR:8; + } B; + } PRESR; /* RAM ECC Syndrome @baseaddress + 0x65 */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; + } B; + } REMR; /* RAM ECC Master @baseaddress + 0x66 */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; + vuint8_t PROT1:1; + vuint8_t PROT2:1; + vuint8_t PROT3:1; + } B; + } REAT; /* RAM ECC Attributes Register @baseaddress + 0x67 */ + + union { + vuint32_t R; + struct { + vuint32_t REDH:32; + } B; + } REDRH; /* RAM ECC Data High Register @baseaddress + 0x68 */ + + union { + vuint32_t R; + struct { + vuint32_t REDL:32; + } B; + } REDRL; /* RAMECC Data Low Register @baseaddress + 0x6C */ + + }; + +/****************************************************************************/ +/* MODULE : System Timer Module (STM) */ +/****************************************************************************/ + struct STM_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; /* STM Control Register @baseaddress + 0x0000 */ + + union { + vuint32_t R; + } CNT; /* STM Count Register @baseaddress + 0x0004 */ + + uint32_t stm_reserved0008[2]; /* 0x0008 - 0x000F */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register @baseaddress + 0x0010 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register @baseaddress + 0x0014 */ + + union { + vuint32_t R; + struct { + vuint32_t CMP; + } B; + } CMP0; /* STM Channel Compare Register @baseaddress + 0x0018 */ + + uint32_t stm_reserved001C; /* 0x001C - 0x001F*/ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register @baseaddress + 0x0020 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register @baseaddress + 0x0024 */ + + union { + vuint32_t R; + struct { + vuint32_t CMP; + } B; + } CMP1; /* STM Channel Compare Register @baseaddress + 0x0028 */ + + uint32_t stm_reserved002C; /* 0x002C - 0x002F */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register @baseaddress + 0x0030 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register @baseaddress + 0x0034 */ + + union { + vuint32_t R; + struct { + vuint32_t CMP; + } B; + } CMP2; /* STM Channel Compare Register @baseaddress + 0x0038 */ + + uint32_t stm_reserved003C; /* 0x003C - 0x003F */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register @baseaddress + 0x0040 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register @baseaddress + 0x0044 */ + + union { + vuint32_t R; + struct { + vuint32_t CMP; + } B; + } CMP3; /* STM Channel Compare Register @baseaddress + 0x0048 */ + + uint32_t stm_reserved004C; /* 0x004C - 0x004F */ + }; + + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:14; + vuint32_t KEY:1; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } MCR; /* Module Configuration Register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* Interrupt register @baseaddress + 0x04 */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* Timeout register @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + + } B; + } WN; /* Window register @baseaddress + 0x0C */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* Service register @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* Counter output register @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SK:16; + } B; + } SK; /* Service key register @baseaddress + 0x18 */ + }; + +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t DOZEEN:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register @baseaddress + 0x04 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ + } B; + } UCDIS; /* Disable Channel (EMIOSUCDIS) @baseaddress + 0x0C */ + + int32_t EMIOS_Reserved_0010[4]; /* 0x0010 - 0x001F */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t A; + }B; + } CADR; /* Channel A Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t B; + }B; + } CBDR; /* Channel B Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t C; + }B; + } CCNTR; /* Channel Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPREN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t ALTA; + } B; + } ALTA; /* Alternate Channel A Data Register */ + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; + +/****************************************************************************/ +/* MODULE : ETPU */ +/****************************************************************************/ + struct ETPU_tag { + union { + vuint32_t R; + struct { + vuint32_t GEC:1; /* Global Exception Clear */ + vuint32_t SDMERR:1; /* */ + vuint32_t WDTOA:1; /* */ + vuint32_t WDTOB:1; /* */ + vuint32_t MGE1:1; /* */ + vuint32_t MGE2:1; /* */ + vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. */ + vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. */ + vuint32_t SCMERR:1; /* . */ + vuint32_t:2; /* */ + vuint32_t SCMSIZE:5; /* Shared Code Memory size */ + vuint32_t:4; /* */ + vuint32_t SCMMISC:1; /* SCM MISC Flag */ + vuint32_t SCMMISF:1; /* SCM MISC Flag */ + vuint32_t SCMMISEN:1; /* SCM MISC Enable */ + vuint32_t:2; /* */ + vuint32_t VIS:1; /* SCM Visability */ + vuint32_t:5; /* */ + vuint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; /* eTPU module configuration register@baseaddress + 0x00 */ + + + union { + vuint32_t R; + struct { + vuint32_t STS:1; /* Start Status bit */ + vuint32_t CTBASE:5; /* Channel Transfer Base */ + vuint32_t PBASE:10; /* Parameter Buffer Base Address */ + vuint32_t PWIDTH:1; /* Parameter Width */ + vuint32_t PARAM0:7; /* Channel Parameter 0 */ + vuint32_t WR:1; /* */ + vuint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ + + vuint32_t ETPU_reserved_0008; /* 0x0008 - 0x000B */ + + + union { + vuint32_t R; + struct { + vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. */ + } B; + } MISCCMPR; /* eTPU MISC Compare Register@baseaddress + 0x0c */ + + + union { + vuint32_t R; + struct { + vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ + } B; + } SCMOFFDATAR; /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ + + + union { + vuint32_t R; + struct { + vuint32_t FEND:1; /* Force END */ + vuint32_t MDIS:1; /* Low power Stop */ + vuint32_t:1; /* */ + vuint32_t STF:1; /* Stop Flag */ + vuint32_t:4; /* */ + vuint32_t HLTF:1; /* Halt Mode Flag */ + vuint32_t:3; /* */ + vuint32_t FCSS:1; + vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + vuint32_t CDFC:2; /* */ + vuint32_t:1; /* */ + vuint32_t ERBA:5; /* */ + vuint32_t SPPDIS:1; /* */ + vuint32_t:2; /* */ + vuint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ + + vuint32_t ETPU_reserved_0018[2]; /* 0x0018 - 0x001B */ + + union { + vuint32_t R; + struct { + vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + vuint32_t AM:2; /* Angle Mode */ + vuint32_t:3; /* */ + vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ + vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + vuint32_t TCR1CS:1; /* */ + vuint32_t:5; /* */ + vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ + + /* offset 0x0024 */ + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ + } B; + } TB1R_A; /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ + + /* offset 0x0028 */ + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ + } B; + } TB2R_A; /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ + + + union { + vuint32_t R; + struct { + vuint32_t REN1:1; /* Resource Enable TCR1 */ + vuint32_t RSC1:1; /* Resource Control TCR1 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID1:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV1:4; /* Resource Server Slot */ + vuint32_t REN2:1; /* Resource Enable TCR2 */ + vuint32_t RSC2:1; /* Resource Control TCR2 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID2:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ + + vuint32_t ETPU_reserved_0030[12]; /* 0x0030 - 0x005F */ + + + union { + vuint32_t R; + struct { + vuint32_t WDM:2; + vuint32_t:14; + vuint32_t WDCNT:16; + } B; + } WDTR_A; /* ETPU1 WDTR Register @baseaddress + 0x60 */ + + vuint32_t ETPU1_reserved_0064; /* 0x0064 - 0x0067 */ + + + union { + vuint32_t R; + struct { + vuint32_t IDLE_CNT:31; + vuint32_t ICLR:1; + } B; + } IDLE_A; /* ETPU1 IDLE Register @baseaddress + 0x68 */ + + vuint32_t ETPU_reserved_006C[101]; /* 0x006C - 0x01FF */ + + + union { + vuint32_t R; + struct { + vuint32_t CIS31:1; /* Channel 31 Interrut Status */ + vuint32_t CIS30:1; /* Channel 30 Interrut Status */ + vuint32_t CIS29:1; /* Channel 29 Interrut Status */ + vuint32_t CIS28:1; /* Channel 28 Interrut Status */ + vuint32_t CIS27:1; /* Channel 27 Interrut Status */ + vuint32_t CIS26:1; /* Channel 26 Interrut Status */ + vuint32_t CIS25:1; /* Channel 25 Interrut Status */ + vuint32_t CIS24:1; /* Channel 24 Interrut Status */ + vuint32_t CIS23:1; /* Channel 23 Interrut Status */ + vuint32_t CIS22:1; /* Channel 22 Interrut Status */ + vuint32_t CIS21:1; /* Channel 21 Interrut Status */ + vuint32_t CIS20:1; /* Channel 20 Interrut Status */ + vuint32_t CIS19:1; /* Channel 19 Interrut Status */ + vuint32_t CIS18:1; /* Channel 18 Interrut Status */ + vuint32_t CIS17:1; /* Channel 17 Interrut Status */ + vuint32_t CIS16:1; /* Channel 16 Interrut Status */ + vuint32_t CIS15:1; /* Channel 15 Interrut Status */ + vuint32_t CIS14:1; /* Channel 14 Interrut Status */ + vuint32_t CIS13:1; /* Channel 13 Interrut Status */ + vuint32_t CIS12:1; /* Channel 12 Interrut Status */ + vuint32_t CIS11:1; /* Channel 11 Interrut Status */ + vuint32_t CIS10:1; /* Channel 10 Interrut Status */ + vuint32_t CIS9:1; /* Channel 9 Interrut Status */ + vuint32_t CIS8:1; /* Channel 8 Interrut Status */ + vuint32_t CIS7:1; /* Channel 7 Interrut Status */ + vuint32_t CIS6:1; /* Channel 6 Interrut Status */ + vuint32_t CIS5:1; /* Channel 5 Interrut Status */ + vuint32_t CIS4:1; /* Channel 4 Interrut Status */ + vuint32_t CIS3:1; /* Channel 3 Interrut Status */ + vuint32_t CIS2:1; /* Channel 2 Interrut Status */ + vuint32_t CIS1:1; /* Channel 1 Interrut Status */ + vuint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ + + int32_t ETPU_reserved_0204[3]; /* 0x0204 - 0x20F */ + + union { + vuint32_t R; + struct { + vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; /* eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR) @baseaddress + 0x210 */ + + int32_t ETPU_reserved_0214[3]; /* 0x0214 - 0x021F */ + + + union { + vuint32_t R; + struct { + vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ + + int32_t ETPU_reserved_0224[3]; /* 0x0224 - 0x022F */ + + + union { + vuint32_t R; + struct { + vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ + + int32_t ETPU_reserved_0234[3]; /* 0x0234 - 0x023F */ + + + union { + vuint32_t R; + struct { + vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ + vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ + vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ + vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ + vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ + vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ + vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ + vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ + vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ + vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ + vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ + vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ + vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ + vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ + vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ + vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ + vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ + vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ + vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ + vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ + vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ + vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ + vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ + vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ + vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ + vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ + vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ + vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ + vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ + vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ + vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ + vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ + + int32_t ETPU_reserved_0244[3]; /* 0x0244 - 0x25F */ + + + union { + vuint32_t R; + struct { + vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ + + int32_t ETPU_reserved_0254[3]; /* 0x0254 - 0x025F */ + + + union { + vuint32_t R; + struct { + vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } WDSR_A; /* ETPUWDSR - eTPU Watchdog Status Register @baseaddress + 0x260 */ + + int32_t ETPU_reserved_0264[7]; /* 0x0264 - 0x027F */ + + + union { + vuint32_t R; + struct { + vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CPSSR_A; /* ETPUCPSSR - eTPU Channel Pending Service Status Register @baseaddress + 0x280 */ + + int32_t ETPU_reserved_0x0284[3]; /* 0x0284 - 0x028F */ + + + union { + vuint32_t R; + struct { + vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CSSR_A; /* ETPUCSSR - eTPU Channel Service Status Register @baseaddress + 0x290 */ + + int32_t ETPU_reserved_0294[91]; /* 0x0294 - 0x03FF */ + + +/***************************** Channels ********************************/ +/* Note not all devices implement all channels or even 2 engines */ +/* Each eTPU engine can implement 64 channels, however most devcies */ +/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ +/* engines per instantiation */ +/***********************************************************************/ + + struct { + union { + vuint32_t R; + struct { + vuint32_t CIE:1; /* Channel Interruput Enable */ + vuint32_t DTRE:1; /* Data Transfer Request Enable */ + vuint32_t CPR:2; /* Channel Priority */ + vuint32_t:2; /* */ + vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ + vuint32_t ETCS:1; /* Entry Table Condition Select */ + vuint32_t:3; /* */ + vuint32_t CFS:5; /* Channel Function Select */ + vuint32_t ODIS:1; /* Output disable */ + vuint32_t OPOL:1; /* output polarity */ + vuint32_t:3; /* */ + vuint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ + + union { + vuint32_t R; + struct { + vuint32_t CIS:1; /* Channel Interruput Status */ + vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ + vuint32_t:6; /* */ + vuint32_t DTRS:1; /* Data Transfer Status */ + vuint32_t DTROS:1; /* Data Transfer Overflow Status */ + vuint32_t:6; /* */ + vuint32_t IPS:1; /* Input Pin State */ + vuint32_t OPS:1; /* Output Pin State */ + vuint32_t OBE:1; /* Output Pin State */ + vuint32_t:11; /* */ + vuint32_t FM1:1; /* Function mode */ + vuint32_t FM0:1; /* Function mode */ + } B; + } SCR; /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ + + union { + vuint32_t R; + struct { + vuint32_t:29; /* Host Service Request */ + vuint32_t HSR:3; /* */ + } B; + } HSRR; /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ + + int32_t ETPU_reserved_0C; /* CHAN Base + 0x0C */ + + } CHAN[127]; + /**** Note: Not all channels implemented on all devices. *******/ + }; + +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t ICEA0:1; + vuint32_t ICEA1:1; + vuint32_t:1; + vuint32_t ESSIE:2; + vuint32_t:1; + vuint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + int32_t EQADC_reserved0004; /* 0x0004 - 0x0007 */ + + union { + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + vuint32_t R; + struct { + vuint32_t CFPUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RFPOP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers*/ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t CFEE0:1; + vuint16_t STRME0:1; + vuint16_t SSE:1; + vuint16_t CFINV:1; + vuint16_t:1; + vuint16_t MODE:4; + vuint16_t AMODE0:4; /* CFIFO0 only */ + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t NCIE:1; + vuint16_t TORIE:1; + vuint16_t PIE:1; + vuint16_t EOQIE:1; + vuint16_t CFUIE:1; + vuint16_t:1; + vuint16_t CFFE:1; + vuint16_t CFFS:1; + vuint16_t:4; + vuint16_t RFOIE:1; + vuint16_t:1; + vuint16_t RFDE:1; + vuint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union { + vuint32_t R; + struct { + vuint32_t NCF:1; + vuint32_t TORF:1; + vuint32_t PF:1; + vuint32_t EOQF:1; + vuint32_t CFUF:1; + vuint32_t SSS:1; + vuint32_t CFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t CFCTR:4; + vuint32_t TNXTPTR:4; + vuint32_t RFCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t TCCF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:5; + vuint32_t LCFTCB0:4; + vuint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:5; + vuint32_t LCFTCB1:4; + vuint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:4; + vuint32_t ECBNI:1; + vuint32_t LCFTSSI:4; + vuint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11; + + union { + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t MDT:3; + vuint32_t:4; + vuint32_t BR:4; + } B; + } SSICR; /* SSI Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t RDV:1; + vuint32_t:5; + vuint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register @ baseaddress + 0xB8 */ + + uint32_t eqadc_reserved11b[5]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t REDBS2:4; + vuint32_t SRV2:4; + vuint32_t REDBS1:4; + vuint32_t SRV1:4; + } B; + } REDLCCR; /* STAC Bus Clent Configuration Register @ baseaddress + 0xD0 */ + + + uint32_t eqadc_reserved12[11]; + + struct { + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } R[4]; + + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } EDATA[4]; + + uint32_t eqadc_reserved13[8]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + vuint32_t R; + struct { + vuint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + +/****************************************************************************/ +/* MODULE : Decimation Filter (DECFIL) */ +/****************************************************************************/ + struct DECFIL_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FREN:1; + vuint32_t:1; + vuint32_t FRZ:1; + vuint32_t SRES:1; + vuint32_t CASCD:2; + vuint32_t IDEN:1; + vuint32_t ODEN:1; + vuint32_t ERREN:1; + vuint32_t:1; + vuint32_t FTYPE:2; + vuint32_t:1; + vuint32_t SCAL:2; + vuint32_t IDIS:1; + vuint32_t SAT:1; + vuint32_t ISEL:1; + vuint32_t MIXM:1; + vuint32_t DEC_RATE:4; + vuint32_t SDIE:1; + vuint32_t DSEL:1; + vuint32_t IBIE:1; + vuint32_t OBIE:1; + vuint32_t EDME:1; + vuint32_t TORE:1; + vuint32_t TMODE:2; + } B; + } MCR; /* Configuration Register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t:1; + vuint32_t DEC_COUNTER:4; + vuint32_t IDFC:1; + vuint32_t ODFC:1; + vuint32_t:1; + vuint32_t IBIC:1; + vuint32_t OBIC:1; + vuint32_t:1; + vuint32_t DIVRC:1; + vuint32_t OVFC:1; + vuint32_t OVRC:1; + vuint32_t IVRC:1; + vuint32_t:6; + vuint32_t IDF:1; + vuint32_t ODF:1; + vuint32_t:1; + vuint32_t IBIF:1; + vuint32_t OBIF:1; + vuint32_t:1; + vuint32_t DIVR:1; + vuint32_t OVF:1; + vuint32_t OVR:1; + vuint32_t IVR:1; + } B; + } MSR; /* Status Register @baseaddress + 0x04 */ + + union { + vuint32_t R; + struct { + vuint32_t SDMAE:1; + vuint32_t SSIG:1; + vuint32_t SSAT:1; + vuint32_t SCSAT:1; + vuint32_t:10; + vuint32_t SRQ:1; + vuint32_t SZRO:1; + vuint32_t SISEL:1; + vuint32_t:1; + vuint32_t SZROSEL:2; + vuint32_t:2; + vuint32_t SHLTSEL:2; + vuint32_t:1; + vuint32_t SRQSEL:3; + vuint32_t:2; + vuint32_t SENSEL:2; + } B; + } MXCR; /* Extended Config Register @baseaddress + 0x8 */ + + union { + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t SDFC:1; + vuint32_t:2; + vuint32_t SSEC:1; + vuint32_t SCEC:1; + vuint32_t:1; + vuint32_t SSOVFC:1; + vuint32_t SCOVFC:1; + vuint32_t SVRC:1; + vuint32_t:7; + vuint32_t SDF:1; + vuint32_t:2; + vuint32_t SSE:1; + vuint32_t SCE:1; + vuint32_t:1; + vuint32_t SSOVF:1; + vuint32_t SCOVF:1; + vuint32_t SVR:1; + } B; + } MXSR; /* Extended Status Register @baseaddress + 0xC */ + + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t INTAG:4; + vuint32_t:6; + vuint32_t PREFILL:1; + vuint32_t FLUSH:1; + vuint32_t INPBUF:16; + } B; + } IB; /* Interface Input Buffer @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t OUTTAG:4; + vuint32_t OUTBUF:16; + } B; + } OB; /* Interface Output Buffer @baseaddress + 0x14 */ + + uint32_t decfil_reserved0018[2]; /* 0x0018 - 0x001F */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t COEF:24; + } B; + } COEF[9]; /* Filter Coefficient Registers @baseaddress + 0x20 - 0x40 */ + + uint32_t decfil_reserved0044[13]; /* 0x0044 - 0x0077 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t TAP:24; + } B; + } TAP[8]; /* Filter TAP Registers @baseaddress + 0x78 - 0x94 */ + + uint32_t decfil_reserved00D0[14]; /* 0x00D0 - 0x00D3 */ + + /* 0x0D0 */ + union { + vuint16_t R; + struct { + vuint32_t:16; + vuint32_t SAMP_DATA:16; + } B; + } EDID; /* Filter EDID Registers @baseaddress + 0xD0 */ + + uint32_t decfil_reserved00D4[3]; /* 0x00D4 - 0x00DF */ + + union { + vuint32_t R; + struct { + vuint32_t SUM_VALUE:1; + } B; + } FINTVAL; /* Final Integr. Value Register @baseaddress + 0xE0 */ + + union { + vuint32_t R; + struct { + vuint32_t COUNT:1; + } B; + } FINTCNT; /* Final Integr. Count Register @baseaddress + 0xE0 */ + + union { + vuint32_t R; + struct { + vuint32_t SUM_VALUE:1; + } B; + } CINTVAL; /* Current Integr. Value Register @baseaddress + 0xE0 */ + + union { + vuint32_t R; + struct { + vuint32_t COUNT:1; + } B; + } CINTCNT; /* Current Integr. Count Register @baseaddress + 0xE0 */ + + }; + +/****************************************************************************/ +/* MODULE : CRC */ +/****************************************************************************/ + struct CRC_tag { + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t POLY:1; + vuint32_t SWAP:1; + vuint32_t INV:1; + } B; + } CFG; /* Configuration Register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct{ + vuint32_t INP:32; + } B; + } INP; /* Input Register @baseaddress + 0x04 */ + + union { + vuint32_t R; + struct{ + vuint32_t CSTAT:32; + } B; + } CSTAT; /* Current Status Register @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t OUTP:32; + } B; + } OUTP; /* Output Register @baseaddress + 0x0C */ + }; + +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t PCSIS7:1; + vuint32_t PCSIS6:1; + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t DOZE:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:6; + vuint32_t PES:1; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register @baseaddress + 0x00 */ + + uint32_t dspi_reserved0004; /* 0x0004-0x008 */ + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; + vuint32_t:16; + } B; + } TCR; /* DSPI Transfer Count Register @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers @baseaddress + 0x0C - 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:2; + vuint32_t DPEF:1; + vuint32_t SPEF:1; + vuint32_t DDIF:1; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; + vuint32_t:2; + vuint32_t EOQFRE:1; + vuint32_t TFUFRE:1; + vuint32_t:1; + vuint32_t TFFFRE:1; + vuint32_t TFFFDIRS:1; + vuint32_t:1; + vuint32_t DPEFRE:1; + vuint32_t SPEFRE:1; + vuint32_t DDIFRE:1; + vuint32_t RFOFRE:1; + vuint32_t:1; + vuint32_t RFDFRE:1; + vuint32_t RFDFDIRS:1; + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t PE:1; + vuint32_t PP:1; + vuint32_t PCS7:1; /* new in MPC563xM */ + vuint32_t PCS6:1; /* new in MPC563xM */ + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register @baseaddress + 0x34 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register @baseaddress + 0x38 */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers @baseaddress + 0x3c - 0x78 */ + + vuint32_t DSPI_reserved_004C[12]; /* 0x004C-0x0078 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers @baseaddress + 0x7c - 0xB8 */ + + vuint32_t DSPI_reserved_008C[12]; /* 0x008C-0x00B8 */ + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t FMSZ4:1; + vuint32_t MTOCNT:6; + vuint32_t:3; + vuint32_t TSBC:1; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:4; + vuint32_t DPCS7:1; + vuint32_t DPCS6:1; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register @baseaddress + 0xBC */ + + union { + vuint32_t R; + struct { + vuint32_t SER_DATA:32; + } B; + } SDR; /* DSI Serialization Data Register @baseaddress + 0xC0 */ + + union { + vuint32_t R; + struct { + vuint32_t ASER_DATA:32; + } B; + } ASDR; /* DSI Alternate Serialization Data Register @baseaddress + 0xC4 */ + + union { + vuint32_t R; + struct { + vuint32_t COMP_DATA:32; + } B; + } COMPR; /* DSI Transmit Comparison Register @baseaddress + 0xC8 */ + + union { + vuint32_t R; + struct { + vuint32_t DESER_DATA:32; + } B; + } DDR; /* DSI deserialization Data Register @baseaddress + 0xCC */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t TSBCNT:5; + vuint32_t:16; + vuint32_t DPCS1_7:1; + vuint32_t DPCS1_6:1; + vuint32_t DPCS1_5:1; + vuint32_t DPCS1_4:1; + vuint32_t DPCS1_3:1; + vuint32_t DPCS1_2:1; + vuint32_t DPCS1_1:1; + vuint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 @baseaddress + 0xD0 */ + + }; + +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t SBR:13; + vuint32_t LOOPS:1; + vuint32_t:1; + vuint32_t RSRC:1; + vuint32_t M:1; + vuint32_t WAKE:1; + vuint32_t ILT:1; + vuint32_t PE:1; + vuint32_t PT:1; + vuint32_t TIE:1; + vuint32_t TCIE:1; + vuint32_t RIE:1; + vuint32_t ILIE:1; + vuint32_t TE:1; + vuint32_t RE:1; + vuint32_t RWU:1; + vuint32_t SBK:1; + } B; + } CR1; /* Control Register 1 @baseaddress + 0x00 */ + + union { + vuint16_t R; + struct { + vuint16_t MDIS:1; + vuint16_t FBR:1; + vuint16_t BSTP:1; + vuint16_t IEBERR:1; + vuint16_t RXDMA:1; + vuint16_t TXDMA:1; + vuint16_t BRK13:1; + vuint16_t TXDIR:1; + vuint16_t BESM13:1; + vuint16_t SBSTP:1; + vuint16_t RXPOL:1; + vuint16_t PMSK:1; + vuint16_t ORIE:1; + vuint16_t NFIE:1; + vuint16_t FEIE:1; + vuint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 @baseaddress + 0x04 */ + + union { + vuint16_t R; + struct { + vuint16_t R8:1; + vuint16_t T8:1; + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t R:4; + vuint8_t D; + } B; + } DR; /* Data Register @baseaddress + 0x06 */ + + union { + vuint32_t R; + struct { + vuint32_t TDRE:1; + vuint32_t TC:1; + vuint32_t RDRF:1; + vuint32_t IDLE:1; + vuint32_t OR:1; + vuint32_t NF:1; + vuint32_t FE:1; + vuint32_t PF:1; + vuint32_t:3; + vuint32_t BERR:1; + vuint32_t:2; + vuint32_t TACT:1; + vuint32_t RAF:1; + vuint32_t RXRDY:1; + vuint32_t TXRDY:1; + vuint32_t LWAKE:1; + vuint32_t STO:1; + vuint32_t PBERR:1; + vuint32_t CERR:1; + vuint32_t CKERR:1; + vuint32_t FRC:1; + vuint32_t:6; + vuint32_t UREQ:1; + vuint32_t OVFL:1; + } B; + } SR; /* Status Register @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t LRES:1; + vuint32_t WU:1; + vuint32_t WUD0:1; + vuint32_t WUD1:1; + vuint32_t LDBG:1; + vuint32_t DSF:1; + vuint32_t PRTY:1; + vuint32_t LIN:1; + vuint32_t RXIE:1; + vuint32_t TXIE:1; + vuint32_t WUIE:1; + vuint32_t STIE:1; + vuint32_t PBIE:1; + vuint32_t CIE:1; + vuint32_t CKIE:1; + vuint32_t FCIE:1; + vuint32_t:6; + vuint32_t UQIE:1; + vuint32_t OFIE:1; + vuint32_t:8; + } B; + } LCR; /* LIN Control Register @baseaddress + 0x0C */ + + union { + vuint32_t R; + } LTR; /* LIN Transmit Register @baseaddress + 0x10 */ + + union { + vuint32_t R; + } LRR; /* LIN Recieve Register @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t P:16; + vuint32_t:3; + vuint32_t SYNM:1; + vuint32_t EROE:1; + vuint32_t ERFE:1; + vuint32_t ERPE:1; + vuint32_t M2:1; + vuint32_t:8; + } B; + } LPR; /* LIN CRC Polynom Register @baseaddress + 0x18 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_12_13_bit_tag { + union { + vuint16_t R; + struct { + vuint16_t R8:1; + vuint16_t T8:1; + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t D:12; + } B; + } DR; /* Data Register */ + }; + +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN2_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAK_MSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t SLF_WAK:1; + + vuint32_t WRNEN:1; + + vuint32_t MDISACK:1; + vuint32_t WAK_SRC:1; + vuint32_t DOZE:1; + + vuint32_t SRXDIS:1; + vuint32_t MBFEN:1; + vuint32_t:2; + + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; /* Control Register @baseaddress + 0x04 */ + } CR; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TIMER:16; + } B; + } TIMER; /* Free Running Timer @baseaddress + 0x08 */ + + int32_t FLEXCAN_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask @baseaddress + 0x0C */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register @baseaddress + 0x18 */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t:1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t WAK_INT:1; + } B; + } ESR; /* Error and Status Register @baseaddress + 0x1C */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; /* Interruput Masks Register @baseaddress + 0x20 */ + } IMRH; + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; /* Interruput Masks Register @baseaddress + 0x24 */ + } IMRL; + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; /* Interruput Flag Register @baseaddress + 0x28 */ + } IFRH; + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; /* Interruput Flag Register @baseaddress + 0x2C */ + } IFRL; + + uint32_t flexcan2_reserved2[19]; + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; /* RX Individual Mask Registers @baseaddress + 0x0880 */ + } RXIMR[64]; + + }; /* end of FLEXCAN_tag */ + +/****************************************************************************/ +/* MODULE : Periodic Interval Timer (PIT) */ +/****************************************************************************/ + struct PIT_tag { + + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t MDIS_RTI:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; /* PIT Module Control Register @baseaddress + 0x00 */ + + uint32_t pit_reserved1[59]; + + struct { + union { + vuint32_t R; + } LDVAL; /* Timer Load Value Register @baseaddress + 0xF0 */ + + union { + vuint32_t R; + } CVAL; /* Current Timer Value Register @baseaddress + 0xF4 */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register @baseaddress + 0xF8 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel @baseaddress + 0xFC */ + + struct { + union { + vuint32_t R; + } LDVAL; /* Timer Load Value Register @baseaddress + CH + 0x0 */ + + union { + vuint32_t R; + } CVAL; /* Current Timer Value Register @baseaddress + CH + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register @baseaddress + CH + 0x8 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register @baseaddress + CH + 0xC */ + } TIMER[4]; /* Timer Channels @baseaddress + 0x100 */ + + }; + +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + vuint16_t R; + struct { + vuint16_t CHIVER:8; /* CHI Version Number */ + vuint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + vuint16_t R; + struct { + vuint16_t MEN:1; /* module enable */ + vuint16_t:1; + vuint16_t SCMD:1; /* single channel mode */ + vuint16_t CHB:1; /* channel B enable */ + vuint16_t CHA:1; /* channel A enable */ + vuint16_t SFFE:1; /* synchronization frame filter enable */ + vuint16_t:5; + vuint16_t CLKSEL:1; /* protocol engine clock source select */ + vuint16_t PRESCALE:3; /* protocol engine clock prescaler */ + vuint16_t:1; + } B; + } MCR_t; + + typedef union uSTBSCR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t STBSSEL:7; /* strobe signal select */ + vuint16_t:3; + vuint16_t ENB:1; /* strobe signal enable */ + vuint16_t:2; + vuint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t STB3EN:1; /* strobe port enable */ + vuint16_t STB2EN:1; /* strobe port enable */ + vuint16_t STB1EN:1; /* strobe port enable */ + vuint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + vuint16_t:1; + vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + typedef union uMBSSUTR { + vuint16_t R; + struct { + + vuint16_t:1; + vuint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ + vuint16_t:1; + vuint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + vuint16_t R; + vuint8_t byte[2]; + struct { + vuint16_t WME:1; /* write mode external correction command */ + vuint16_t:3; + vuint16_t EOC_AP:2; /* external offset correction application */ + vuint16_t ERC_AP:2; /* external rate correction application */ + vuint16_t BSY:1; /* command write busy / write mode command */ + vuint16_t:3; + vuint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + vuint16_t R; + struct { + vuint16_t MIF:1; /* module interrupt flag */ + vuint16_t PRIF:1; /* protocol interrupt flag */ + vuint16_t CHIF:1; /* CHI interrupt flag */ + vuint16_t WKUPIF:1; /* wakeup interrupt flag */ + vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + vuint16_t RBIF:1; /* receive message buffer interrupt flag */ + vuint16_t TBIF:1; /* transmit buffer interrupt flag */ + vuint16_t MIE:1; /* module interrupt enable */ + vuint16_t PRIE:1; /* protocol interrupt enable */ + vuint16_t CHIE:1; /* CHI interrupt enable */ + vuint16_t WKUPIE:1; /* wakeup interrupt enable */ + vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + vuint16_t RBIE:1; /* receive message buffer interrupt enable */ + vuint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + vuint16_t R; + struct { + vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + vuint16_t INTLIF:1; /* internal protocol error interrupt flag */ + vuint16_t ILCFIF:1; /* illegal protocol configuration flag */ + vuint16_t CSAIF:1; /* cold start abort interrupt flag */ + vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + vuint16_t MTXIF:1; /* media access test symbol received flag */ + vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + vuint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + vuint16_t R; + struct { + vuint16_t EMCIF:1; /* error mode changed interrupt flag */ + vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + vuint16_t:2; + vuint16_t EVTIF:1; /* even cycle table written interrupt flag */ + vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + vuint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + vuint16_t R; + struct { + vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + vuint16_t CSAIE:1; /* cold start abort interrupt enable */ + vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + vuint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + vuint16_t R; + struct { + vuint16_t EMCIE:1; /* error mode changed interrupt enable */ + vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + vuint16_t:2; + vuint16_t EVTIE:1; /* even cycle table written interrupt enable */ + vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + vuint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + vuint16_t R; + struct { + vuint16_t FRLBEF:1; /* flame lost channel B error flag */ + vuint16_t FRLAEF:1; /* frame lost channel A error flag */ + vuint16_t PCMIEF:1; /* command ignored error flag */ + vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + vuint16_t MSBEF:1; /* message buffer search error flag */ + vuint16_t MBUEF:1; /* message buffer utilization error flag */ + vuint16_t LCKEF:1; /* lock error flag */ + vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + vuint16_t SBCFEF:1; /* system bus communication failure error flag */ + vuint16_t FIDEF:1; /* frame ID error flag */ + vuint16_t DPLEF:1; /* dynamic payload length error flag */ + vuint16_t SPLEF:1; /* static payload length error flag */ + vuint16_t NMLEF:1; /* network management length error flag */ + vuint16_t NMFEF:1; /* network management frame error flag */ + vuint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + vuint16_t R; + struct { + + vuint16_t:1; + vuint16_t TBIVEC:7; /* transmit buffer interrupt vector */ + vuint16_t:1; + vuint16_t RBIVEC:7; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + vuint16_t R; + struct { + vuint16_t ERRMODE:2; /* error mode */ + vuint16_t SLOTMODE:2; /* slot mode */ + vuint16_t:1; + vuint16_t PROTSTATE:3; /* protocol state */ + vuint16_t SUBSTATE:4; /* protocol sub state */ + vuint16_t:1; + vuint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + vuint16_t R; + struct { + vuint16_t CSAA:1; /* cold start attempt abort flag */ + vuint16_t SCP:1; /* cold start path */ + vuint16_t:1; + vuint16_t REMCSAT:5; /* remanining coldstart attempts */ + vuint16_t CPN:1; /* cold start noise path */ + vuint16_t HHR:1; /* host halt request pending */ + vuint16_t FRZ:1; /* freeze occured */ + vuint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + vuint16_t R; + struct { + vuint16_t NBVB:1; /* NIT boundary violation on channel B */ + vuint16_t NSEB:1; /* NIT syntax error on channel B */ + vuint16_t STCB:1; /* symbol window transmit conflict on channel B */ + vuint16_t SBVB:1; /* symbol window boundary violation on channel B */ + vuint16_t SSEB:1; /* symbol window syntax error on channel B */ + vuint16_t MTB:1; /* media access test symbol MTS received on channel B */ + vuint16_t NBVA:1; /* NIT boundary violation on channel A */ + vuint16_t NSEA:1; /* NIT syntax error on channel A */ + vuint16_t STCA:1; /* symbol window transmit conflict on channel A */ + vuint16_t SBVA:1; /* symbol window boundary violation on channel A */ + vuint16_t SSEA:1; /* symbol window syntax error on channel A */ + vuint16_t MTA:1; /* media access test symbol MTS received on channel A */ + vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t WUB:1; /* wakeup symbol received on channel B */ + vuint16_t ABVB:1; /* aggregated boundary violation on channel B */ + vuint16_t AACB:1; /* aggregated additional communication on channel B */ + vuint16_t ACEB:1; /* aggregated content error on channel B */ + vuint16_t ASEB:1; /* aggregated syntax error on channel B */ + vuint16_t AVFB:1; /* aggregated valid frame on channel B */ + vuint16_t:2; + vuint16_t WUA:1; /* wakeup symbol received on channel A */ + vuint16_t ABVA:1; /* aggregated boundary violation on channel A */ + vuint16_t AACA:1; /* aggregated additional communication on channel A */ + vuint16_t ACEA:1; /* aggregated content error on channel A */ + vuint16_t ASEA:1; /* aggregated syntax error on channel A */ + vuint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t MIFR:1; /* module interrupt flag */ + vuint16_t PRIFR:1; /* protocol interrupt flag */ + vuint16_t CHIFR:1; /* CHI interrupt flag */ + vuint16_t WUPIFR:1; /* wakeup interrupt flag */ + vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + vuint16_t RBIFR:1; /* receive message buffer interrupt flag */ + vuint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + vuint16_t R; + struct { + vuint16_t SFEVB:4; /* sync frames channel B, even cycle */ + vuint16_t SFEVA:4; /* sync frames channel A, even cycle */ + vuint16_t SFODB:4; /* sync frames channel B, odd cycle */ + vuint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + vuint16_t R; + struct { + vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + vuint16_t CYCNUM:6; /* cycle number */ + vuint16_t ELKS:1; /* even cycle tables lock status */ + vuint16_t OLKS:1; /* odd cycle tables lock status */ + vuint16_t EVAL:1; /* even cycle tables valid */ + vuint16_t OVAL:1; /* odd cycle tables valid */ + vuint16_t:1; + vuint16_t OPT:1; /*one pair trigger */ + vuint16_t SDVEN:1; /* sync frame deviation table enable */ + vuint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t T2CFG:1; /* timer 2 configuration */ + vuint16_t T2REP:1; /* timer 2 repetitive mode */ + vuint16_t:1; + vuint16_t T2SP:1; /* timer 2 stop */ + vuint16_t T2TR:1; /* timer 2 trigger */ + vuint16_t T2ST:1; /* timer 2 state */ + vuint16_t:3; + vuint16_t T1REP:1; /* timer 1 repetitive mode */ + vuint16_t:1; + vuint16_t T1SP:1; /* timer 1 stop */ + vuint16_t T1TR:1; /* timer 1 trigger */ + vuint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + vuint16_t:2; + vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* static slot number */ + vuint16_t:1; + vuint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* selector */ + vuint16_t:1; + vuint16_t CNTCFG:2; /* counter configuration */ + vuint16_t MCY:1; /* multi cycle selection */ + vuint16_t VFR:1; /* valid frame selection */ + vuint16_t SYF:1; /* sync frame selection */ + vuint16_t NUF:1; /* null frame selection */ + vuint16_t SUF:1; /* startup frame selection */ + vuint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + vuint16_t R; + struct { + vuint16_t VFB:1; /* valid frame on channel B */ + vuint16_t SYB:1; /* valid sync frame on channel B */ + vuint16_t NFB:1; /* valid null frame on channel B */ + vuint16_t SUB:1; /* valid startup frame on channel B */ + vuint16_t SEB:1; /* syntax error on channel B */ + vuint16_t CEB:1; /* content error on channel B */ + vuint16_t BVB:1; /* boundary violation on channel B */ + vuint16_t TCB:1; /* tx conflict on channel B */ + vuint16_t VFA:1; /* valid frame on channel A */ + vuint16_t SYA:1; /* valid sync frame on channel A */ + vuint16_t NFA:1; /* valid null frame on channel A */ + vuint16_t SUA:1; /* valid startup frame on channel A */ + vuint16_t SEA:1; /* syntax error on channel A */ + vuint16_t CEA:1; /* content error on channel A */ + vuint16_t BVA:1; /* boundary violation on channel A */ + vuint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + vuint16_t R; + struct { + vuint16_t MTE:1; /* media access test symbol transmission enable */ + vuint16_t:1; + vuint16_t CYCCNTMSK:6; /* cycle counter mask */ + vuint16_t:2; + vuint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + typedef union uRSBIR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t:1; + vuint16_t SEL:2; /* selector */ + vuint16_t:4; + vuint16_t RSBIDX:8; /* receive shadow buffer index */ + } B; + } RSBIR_t; + typedef union uRFDSR { + vuint16_t R; + struct { + vuint16_t FIFODEPTH:8; /* fifo depth */ + vuint16_t:1; + vuint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + vuint16_t R; + struct { + vuint16_t WMD:1; /* write mode */ + vuint16_t IBD:1; /* interval boundary */ + vuint16_t SEL:2; /* filter number */ + vuint16_t:1; + vuint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t F3MD:1; /* filter mode */ + vuint16_t F2MD:1; /* filter mode */ + vuint16_t F1MD:1; /* filter mode */ + vuint16_t F0MD:1; /* filter mode */ + vuint16_t:4; + vuint16_t F3EN:1; /* filter enable */ + vuint16_t F2EN:1; /* filter enable */ + vuint16_t F1EN:1; /* filter enable */ + vuint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + vuint16_t R; + struct { + vuint16_t ACTION_POINT_OFFSET:6; + vuint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + vuint16_t R; + struct { + vuint16_t MINISLOT_AFTER_ACTION_POINT:6; + vuint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + vuint16_t R; + struct { + vuint16_t WAKEUP_SYMBOL_RX_LOW:6; + vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; + vuint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + vuint16_t R; + struct { + vuint16_t CAS_RX_LOW_MAX:7; + vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + vuint16_t R; + struct { + vuint16_t TSS_TRANSMITTER:4; + vuint16_t WAKEUP_SYMBOL_TX_LOW:6; + vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + vuint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_B:9; + vuint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + vuint16_t R; + struct { + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + vuint16_t R; + struct { + vuint16_t MINISLOT_EXISTS:1; + vuint16_t SYMBOL_WINDOW_EXISTS:1; + vuint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + vuint16_t R; + struct { + vuint16_t SINGLE_SLOT_ENABLED:1; + vuint16_t WAKEUP_CHANNEL:1; + vuint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + vuint16_t R; + struct { + vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; + vuint16_t KEY_SLOT_USED_FOR_SYNC:1; + vuint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + vuint16_t R; + struct { + vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + vuint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + vuint16_t R; + struct { + vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + vuint16_t R; + struct { + vuint16_t RATE_CORRECTION_OUT:11; + vuint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + vuint16_t R; + struct { + vuint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + vuint16_t R; + struct { + vuint16_t MACRO_INITIAL_OFFSET_B:7; + vuint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + vuint16_t R; + struct { + vuint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + vuint16_t R; + struct { + vuint16_t WAKEUP_PATTERN:6; + vuint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_A:9; + vuint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + vuint16_t R; + struct { + vuint16_t MICRO_INITIAL_OFFSET_B:8; + vuint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + vuint16_t R; + struct { + vuint16_t EXTERN_RATE_CORRECTION:3; + vuint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + vuint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + vuint16_t R; + struct { + vuint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + vuint16_t R; + struct { + vuint16_t CLUSTER_DRIFT_DAMPING:5; + vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + vuint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + vuint16_t R; + struct { + vuint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + vuint16_t R; + struct { + vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + vuint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + vuint16_t R; + struct { + vuint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + vuint16_t R; + struct { + vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + vuint16_t R; + struct { + vuint16_t EXTERN_OFFSET_CORRECTION:3; + vuint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MCM:1; /* message buffer commit mode */ + vuint16_t MBT:1; /* message buffer type */ + vuint16_t MTD:1; /* message buffer direction */ + vuint16_t CMT:1; /* commit for transmission */ + vuint16_t EDT:1; /* enable / disable trigger */ + vuint16_t LCKT:1; /* lock request trigger */ + vuint16_t MBIE:1; /* message buffer interrupt enable */ + vuint16_t:3; + vuint16_t DUP:1; /* data updated */ + vuint16_t DVAL:1; /* data valid */ + vuint16_t EDS:1; /* lock status */ + vuint16_t LCKS:1; /* enable / disable status */ + vuint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + vuint16_t R; + struct { + vuint16_t MTM:1; /* message buffer transmission mode */ + vuint16_t CHNLA:1; /* channel assignement */ + vuint16_t CHNLB:1; /* channel assignement */ + vuint16_t CCFE:1; /* cycle counter filter enable */ + vuint16_t CCFMSK:6; /* cycle counter filter mask */ + vuint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + union { + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t MBIDX:8; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + vuint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + vuint16_t R; + } SYSBADLR_t; + typedef union uPDAR { + vuint16_t R; + } PDAR_t; + typedef union uCASERCR { + vuint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + vuint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + vuint16_t R; + } CYCTR_t; + typedef union uMTCTR { + vuint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + vuint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + vuint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + vuint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + vuint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + vuint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + vuint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + vuint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + vuint16_t R; + } NMVR_t; + typedef union uNMVLR { + vuint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + vuint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + vuint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + vuint16_t R; + } TI2CR1_t; + typedef union uSSCR { + vuint16_t R; + } SSCR_t; + typedef union uRFSR { + vuint16_t R; + } RFSR_t; + typedef union uRFSIR { + vuint16_t R; + } RFSIR_t; + typedef union uRFARIR { + vuint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + vuint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + vuint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + vuint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + vuint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + vuint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + vuint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + vuint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + vuint16_t reserved3a[1]; /*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + vuint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + vuint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + vuint16_t:5; + vuint16_t HDCRC:11; /* Header CRC */ + vuint16_t:2; + vuint16_t CYCCNT:6; /* Cycle Count */ + vuint16_t:1; + vuint16_t PLDLEN:7; /* Payload Length */ + vuint16_t:1; + vuint16_t PPI:1; /* Payload Preamble Indicator */ + vuint16_t NUF:1; /* Null Frame Indicator */ + vuint16_t SYF:1; /* Sync Frame Indicator */ + vuint16_t SUF:1; /* Startup Frame Indicator */ + vuint16_t FID:11; /* Frame ID */ + } B; + vuint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + vuint16_t VFB:1; /* Valid Frame on channel B */ + vuint16_t SYB:1; /* Sync Frame Indicator channel B */ + vuint16_t NFB:1; /* Null Frame Indicator channel B */ + vuint16_t SUB:1; /* Startup Frame Indicator channel B */ + vuint16_t SEB:1; /* Syntax Error on channel B */ + vuint16_t CEB:1; /* Content Error on channel B */ + vuint16_t BVB:1; /* Boundary Violation on channel B */ + vuint16_t CH:1; /* Channel */ + vuint16_t VFA:1; /* Valid Frame on channel A */ + vuint16_t SYA:1; /* Sync Frame Indicator channel A */ + vuint16_t NFA:1; /* Null Frame Indicator channel A */ + vuint16_t SUA:1; /* Startup Frame Indicator channel A */ + vuint16_t SEA:1; /* Syntax Error on channel A */ + vuint16_t CEA:1; /* Content Error on channel A */ + vuint16_t BVA:1; /* Boundary Violation on channel A */ + vuint16_t:1; + } RX; + struct { + vuint16_t VFB:1; /* Valid Frame on channel B */ + vuint16_t SYB:1; /* Sync Frame Indicator channel B */ + vuint16_t NFB:1; /* Null Frame Indicator channel B */ + vuint16_t SUB:1; /* Startup Frame Indicator channel B */ + vuint16_t SEB:1; /* Syntax Error on channel B */ + vuint16_t CEB:1; /* Content Error on channel B */ + vuint16_t BVB:1; /* Boundary Violation on channel B */ + vuint16_t TCB:1; /* Tx Conflict on channel B */ + vuint16_t VFA:1; /* Valid Frame on channel A */ + vuint16_t SYA:1; /* Sync Frame Indicator channel A */ + vuint16_t NFA:1; /* Null Frame Indicator channel A */ + vuint16_t SUA:1; /* Startup Frame Indicator channel A */ + vuint16_t SEA:1; /* Syntax Error on channel A */ + vuint16_t CEA:1; /* Content Error on channel A */ + vuint16_t BVA:1; /* Boundary Violation on channel A */ + vuint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + vuint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + vuint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; + +/****************************************************************************/ +/* MODULE : Power Management Controller (PMC) */ +/****************************************************************************/ + struct PMC_tag { + union { + vuint32_t R; + struct { + vuint32_t LVRER:1; + vuint32_t LVREH:1; + vuint32_t LVRE50:1; + vuint32_t LVRE33:1; + vuint32_t LVREC:1; + vuint32_t:3; + vuint32_t LVIER:1; + vuint32_t LVIEH:1; + vuint32_t LVIE50:1; + vuint32_t LVIE33:1; + vuint32_t LVIC:1; + vuint32_t:2; + vuint32_t TLK:1; + vuint32_t:16; + } B; + } MCR; /* Module Configuration register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t LVDREGTRIM:4; + vuint32_t VDD33TRIM:4; + vuint32_t LVD33TRIM:4; + vuint32_t VDDCTRIM:4; + vuint32_t LVDCTRIM:4; + } B; + } TRIMR; /* Trimming register @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t LVFVSTBY:1; + vuint32_t BGRDY:1; + vuint32_t BGTS:1; + vuint32_t:5; + vuint32_t LVFCSTBY:1; + vuint32_t:1; + vuint32_t V33DIS:1; + vuint32_t LVFCR:1; + vuint32_t LVFCH:1; + vuint32_t LVFC50:1; + vuint32_t LVFC33:1; + vuint32_t LVFCC:1; + vuint32_t:3; + vuint32_t LVFR:1; + vuint32_t LVFH:1; + vuint32_t LVF50:1; + vuint32_t LVF33:1; + vuint32_t LVFC:1; + vuint32_t:3; + + } B; + } SR; /* status register @baseaddress + 0x00 */ + }; + +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + + struct MPU_tag { + + union { /* Module Control/Error Status Register */ + vuint32_t R; + struct { + vuint32_t SPERR:8; + vuint32_t:4; + vuint32_t HRL:4; + vuint32_t NSP:4; + vuint32_t NRGD:4; + vuint32_t:7; + vuint32_t VLD:1; + } B; + } CESR; + + uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */ + + struct { + union { /* MPU Error Address Registers */ + vuint32_t R; + struct { + vuint32_t EADDR:32; + } B; + } EAR; + + union { /* MPU Error Detail Registers */ + vuint32_t R; + struct { + vuint32_t EACD:16; + vuint32_t EPID:8; + vuint32_t EMN:4; + vuint32_t EATTR:3; + vuint32_t ERW:1; + } B; + } EDR; + } PORT[2]; + + uint32_t MPU_reserved0020[248]; /* 0x0020-0x03FF */ + + struct { + union { /* Region Descriptor n Word 0 */ + vuint32_t R; + struct { + vuint32_t SRTADDR:27; + vuint32_t:5; + } B; + } WORD0; + + union { /* Region Descriptor n Word 1 */ + vuint32_t R; + struct { + vuint32_t ENDADDR:27; + vuint32_t:5; + } B; + } WORD1; + + union { /* Region Descriptor n Word 2 */ + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t:2; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } WORD2; + + union { /* Region Descriptor n Word 3 */ + vuint32_t R; + struct { + vuint32_t PID:8; + vuint32_t PIDMASK:8; + vuint32_t:15; + vuint32_t VLD:1; + } B; + } WORD3; + } RGD[16]; + + uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */ + + union { /* Region Descriptor Alternate Access Control n */ + vuint32_t R; + struct { + vuint32_t M7RE:1; + vuint32_t M7WE:1; + vuint32_t M6RE:1; + vuint32_t M6WE:1; + vuint32_t:2; + vuint32_t M4RE:1; + vuint32_t M4WE:1; + vuint32_t M3PE:1; + vuint32_t M3SM:2; + vuint32_t M3UM:3; + vuint32_t M2PE:1; + vuint32_t M2SM:2; + vuint32_t M2UM:3; + vuint32_t M1PE:1; + vuint32_t M1SM:2; + vuint32_t M1UM:3; + vuint32_t M0PE:1; + vuint32_t M0SM:2; + vuint32_t M0UM:3; + } B; + } RGDAAC[16]; + + uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : TSENS (Temperature Sensor) */ +/****************************************************************************/ + + struct TSENS_tag { + + union { + vuint32_t R; + struct { + vuint32_t TSCV2:16; + vuint32_t TSCV1:16; + } B; + } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TSCV3:16; + } B; + } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ + + uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ + + }; + +/****************************************************************************/ +/* MODULE : DTS (Development Trigger Semaphor) */ +/****************************************************************************/ + struct DTS_tag { + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t DTS_EN:1; + }B; + } ENABLE; /* DTS Output Enable Register @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct{ + vuint32_t AD31:1; + vuint32_t AD30:1; + vuint32_t AD29:1; + vuint32_t AD28:1; + vuint32_t AD27:1; + vuint32_t AD26:1; + vuint32_t AD25:1; + vuint32_t AD24:1; + vuint32_t AD23:1; + vuint32_t AD22:1; + vuint32_t AD21:1; + vuint32_t AD20:1; + vuint32_t AD19:1; + vuint32_t AD18:1; + vuint32_t AD17:1; + vuint32_t AD16:1; + vuint32_t AD15:1; + vuint32_t AD14:1; + vuint32_t AD13:1; + vuint32_t AD12:1; + vuint32_t AD11:1; + vuint32_t AD10:1; + vuint32_t AD9:1; + vuint32_t AD8:1; + vuint32_t AD7:1; + vuint32_t AD6:1; + vuint32_t AD5:1; + vuint32_t AD4:1; + vuint32_t AD3:1; + vuint32_t AD2:1; + vuint32_t AD1:1; + vuint32_t AD0:1; + }B; + } STARTUP; /* DTS Startup Register @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t ST31:1; + vuint32_t ST30:1; + vuint32_t ST29:1; + vuint32_t ST28:1; + vuint32_t ST27:1; + vuint32_t ST26:1; + vuint32_t ST25:1; + vuint32_t ST24:1; + vuint32_t ST23:1; + vuint32_t ST22:1; + vuint32_t ST21:1; + vuint32_t ST20:1; + vuint32_t ST19:1; + vuint32_t ST18:1; + vuint32_t ST17:1; + vuint32_t ST16:1; + vuint32_t ST15:1; + vuint32_t ST14:1; + vuint32_t ST13:1; + vuint32_t ST12:1; + vuint32_t ST11:1; + vuint32_t ST10:1; + vuint32_t ST9:1; + vuint32_t ST8:1; + vuint32_t ST7:1; + vuint32_t ST6:1; + vuint32_t ST5:1; + vuint32_t ST4:1; + vuint32_t ST3:1; + vuint32_t ST2:1; + vuint32_t ST1:1; + vuint32_t ST0:1; + }B; + } SEMAPHORE; /* DTS Semaphore Register @baseaddress + 0x8 */ + + uint32_t DTS_reserved000C[16381]; /* 0x000C-0xFFFF */ + + }; + +/****************************************************************************/ +/* MODULE : REACM (Reaction Module) */ +/****************************************************************************/ + struct REACM_tag { + + union { + vuint32_t R; + struct { + vuint32_t OVRC:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t:1; + vuint32_t FREN:1; + vuint32_t TPREN:1; + vuint32_t HPREN:1; + vuint32_t GIEN:1; + vuint32_t OVREN:1; + vuint32_t:23; + } B; + } MCR; /* REACM Module Configuration @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t HPRE:12; + vuint32_t:8; + vuint32_t TPRE:8; + } B; + } TCR; /* REACM Timer Configuration @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t WREN1:1; + vuint32_t WREN0:1; + vuint32_t:12; + vuint32_t THRADC1:4; + vuint32_t:4; + vuint32_t THRADC0:4; + } B; + } THRR; /* REACM Threshold Router @baseaddress + 0x8 */ + + uint32_t REACM_reserved000C[1]; /* 0x000C-0x000F */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t ADC_TAG:4; + vuint32_t ADC_RESULT:16; + } B; + } SINR; /* REACM ADC Sensor Input Register @baseaddress + 0x10 */ + + uint32_t REACM_reserved0014[3]; /* 0x0014-0x0001F */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:26; + vuint32_t EF4:1; + vuint32_t EF3:1; + vuint32_t EF2:1; + vuint32_t EF1:1; + vuint32_t EF0:1; + } B; + } GEFR; /* REACM Global Error Flag @baseaddress + 0x20 */ + + uint32_t REACM_reserved0024[55]; /* 0x0024-0x00FF */ + + struct { + union { + vuint32_t R; + struct { + vuint32_t CHEN:2; + vuint32_t SWMC:1; + vuint32_t MAXLEN:1; + vuint32_t OCDFEN:1; + vuint32_t SCDFEN:1; + vuint32_t TAEREN:1; + vuint32_t SQEREN:1; + vuint32_t RAEREN:1; + vuint32_t:1; + vuint32_t CHOFF:1; + vuint32_t:2; + vuint32_t DOFF:3; + vuint32_t:5; + vuint32_t BSB:3; + vuint32_t:2; + vuint32_t MODULATION_ADDR:6; + } B; + } CR; /* REACM Channel n Configuration @baseaddress + 0x100 + (n*0x10) + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t MODACT:1; + vuint32_t MAXL:1; + vuint32_t OCDF:1; + vuint32_t SCDF:1; + vuint32_t TAER:1; + vuint32_t SQER:1; + vuint32_t RAER:1; + vuint32_t CHOUT:3; + vuint32_t:7; + vuint32_t MAXLC:1; + vuint32_t OCDFC:1; + vuint32_t SCDFC:1; + vuint32_t TAERC:1; + vuint32_t SQERC:1; + vuint32_t RAERC:1; + vuint32_t:1; + vuint32_t MODULATION_POINTER:6; + } B; + } SR; /* REACM Channel n Status @baseaddress + 0x100 + (n*0x10) + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t ADCR:4; + vuint32_t:12; + vuint32_t CHIR:4; + } B; + } RR; /* REACM Channel n Router @baseaddress + 0x100 + (n*0x10) + 0x8 */ + + uint32_t REACM_reserved01xC; /* 0x01xC-0x01xF */ + + } CH[6]; + + uint32_t REACM_reserved0160[104]; /* 0x0160-0x02FF */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SHARED_TIMER:16; + } B; + } STBK[16]; /* REACM Shared Timer Bank @baseaddress + 0x300 */ + + uint32_t REACM_reserved0340[16]; /* 0x0340-0x037F */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t HOLD_OFF:12; + } B; + } HOTBK[16]; /* REACM Hold-off Timer Bank @baseaddress + 0x380 */ + + uint32_t REACM_reserved03C0[16]; /* 0x03C0-0x03FF */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t THRESHOLD_VALUE:16; + } B; + } THBK[32]; /* REACM Threshold Timer Bank @baseaddress + 0x400 */ + + uint32_t REACM_reserved0480[96]; /* 0x0480-0x05FF */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ADC_MAX_LIMIT:16; + } B; + } ADCMAX; /* REACM ADC Result Max Limit Check @baseaddress + 0x600 */ + + uint32_t REACM_reserved0604[31]; /* 0x0604-0x067F */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t RANGE_PWD:12; + } B; + } RANGEPWD; /* REACM Modulation Range Pulse Width @baseaddress + 0x680 */ + + uint32_t REACM_reserved0684[15]; /* 0x0684-0x06BF */ + + union { + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t MIN_PWD:12; + } B; + } MINPWD; /* REACM Modulation Minimum Pulse Width @baseaddress + 0x6C0 */ + + uint32_t REACM_reserved06C4[15]; /* 0x06C4-0x06FF */ + + union { + vuint32_t R; + struct { + vuint32_t LOOP:1; + vuint32_t IOSS:1; + vuint32_t:1; + vuint32_t MM:2; + vuint32_t:1; + vuint32_t SM:2; + vuint32_t:1; + vuint32_t HOD:3; + vuint32_t:1; + vuint32_t LOD:3; + vuint32_t:1; + vuint32_t THRESPT:6; + vuint32_t STPT:4; + vuint32_t:1; + vuint32_t HDOFFTPT:4; + } B; + } MWBK[64]; /* REACM Modulation Control Word Bank @baseaddress + 0x700 */ + + }; + + + + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x30000 +#define SRAM_END 0x4002FFFF + +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x400000 +#define FLASH_END 0x003FFFFF + +/* Define instances of modules */ +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000) +#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) +#define DTS (*( volatile struct DTS_tag *) 0xC3F9C000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) + +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define REACM (*( volatile struct REACM_tag *) 0xC3FC7000) + +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define CRC (*( volatile struct CRC_tag *) 0xFFE68000) + +#define PBRIDGE (*( volatile struct PBRIDGE_tag *) 0xFFF00000) +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define MPU (*( volatile struct MPU_tag *) 0xFFF10000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) + +#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000) +#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF8C000) + +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#define FR (*( volatile struct FR_tag *) 0xFFFE0000) +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ifdef _MPC5644_H */ + +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. & STMicroelectronics All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor & STMicroelectronics DISCLAIMS ALL WARRANTIES WHETHER + * EXPRESS OR IMPLIED,INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR + * FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor or STMicroelectronics BE LIABLE FOR ANY + * DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF + * BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, + * OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor & STMicroelectronics assumes no responsibility + * for the maintenance and support of this software + * + ********************************************************************/ diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c new file mode 100644 index 000000000..4a3976f50 --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -0,0 +1,330 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ELxx/hal_lld.c + * @brief SPC56ELxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + uint32_t n; + + /* The system is switched to the RUN0 mode, the default for normal + operations.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Decrementer timer initialized for system tick use, note, it is + initialized here because in the OSAL layer the system clock frequency + is not yet known.*/ + n = halSPCGetSystemClock() / CH_FREQUENCY; + asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */ + "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ + "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ + "mtspr 340, %%r3" /* TCR register. */ + : : [n] "r" (n) : "r3"); + + /* TB counter enabled for debug and measurements.*/ + asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ + "mtspr 1008, %%r3" /* HID0 register. */ + : : : "r3"); + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); +} + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +halrtcnt_t hal_lld_get_counter_value(void) { + halrtcnt_t cnt; + + asm volatile ("mfspr %0, 284" : "=r" (cnt)); + return cnt; +} + +/** + * @brief SPC56ELxx early initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_early_init(void) { + + /* Waiting for IRC stabilization before attempting anything else.*/ + while (!ME.GS.B.S_IRCOSC) + ; + +#if !SPC5_NO_INIT + +#if SPC5_DISABLE_WATCHDOG + /* SWT disabled.*/ + SWT.SR.R = 0xC520; + SWT.SR.R = 0xD928; + SWT.CR.R = 0xFF00000A; +#endif + + /* Enabling peripheral bridges to allow any operation.*/ + AIPS.MPROT.R = 0x77777777; + AIPS.PACR0_7.R = 0; + AIPS.PACR8_15.R = 0; + AIPS.PACR16_23.R = 0; + AIPS.PACR24_31.R = 0; + AIPS.OPACR0_7.R = 0; + AIPS.OPACR8_15.R = 0; + AIPS.OPACR16_23.R = 0; + AIPS.OPACR24_31.R = 0; + AIPS.OPACR32_39.R = 0; + AIPS.OPACR40_47.R = 0; + AIPS.OPACR48_55.R = 0; + AIPS.OPACR56_63.R = 0; + AIPS.OPACR64_71.R = 0; + AIPS.OPACR72_79.R = 0; + AIPS.OPACR80_87.R = 0; + AIPS.OPACR88_95.R = 0; + + /* SSCM initialization. Setting up the most restrictive handling of + invalid accesses to peripherals.*/ + SSCM.ERROR.R = 3; /* PAE and RAE bits. */ + + /* FCCU CF errors clearing.*/ + FCCU.CFK.R = 0x618B7A50; + FCCU.CFS[0].R = 0xFFFFFFFF; + while (FCCU.CTRL.B.OPS != 3) + ; + FCCU.CFK.R = 0x618B7A50; + FCCU.CFS[1].R = 0xFFFFFFFF; + while (FCCU.CTRL.B.OPS != 3) + ; + + /* FCCU NCF errors clearing.*/ + FCCU.NCFK.R = 0xAB3498FE; + FCCU.NCFS[0].R = 0xFFFFFFFF; + while (FCCU.CTRL.B.OPS != 3) + ; + + /* RGM errors clearing.*/ + RGM.FES.R = 0xFFFF; + RGM.DES.R = 0xFFFF; + + /* The system must be in DRUN mode on entry, if this is not the case then + it is considered a serious anomaly.*/ + if (ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) { + SPC5_CLOCK_FAILURE_HOOK(); + } + +#if defined(SPC5_OSC_BYPASS) + /* If the board is equipped with an oscillator instead of a crystal then the + bypass must be activated.*/ + CGM.OSC_CTL.B.OSCBYP = TRUE; +#endif /* SPC5_OSC_BYPASS */ + + /* Setting the various dividers and source selectors.*/ + CGM.SC_DC0.R = SPC5_CGM_SC_DC0; + CGM.AC0_DC0_3.R = SPC5_CGM_AC0_DC0 | SPC5_CGM_AC0_DC1; + CGM.AC0_SC.R = SPC5_AUX0CLK_SRC; + CGM.AC1_DC0_3.R = SPC5_CGM_AC1_DC0; + CGM.AC1_SC.R = SPC5_AUX1CLK_SRC; + CGM.AC2_DC0_3.R = SPC5_CGM_AC2_DC0; + CGM.AC2_SC.R = SPC5_AUX2CLK_SRC; + CGM.AC3_SC.R = SPC5_FMPLL0_CLK_SRC; + CGM.AC4_SC.R = SPC5_FMPLL1_CLK_SRC; + + /* Enables the XOSC in order to check its functionality before proceeding + with the initialization.*/ + ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON; + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Initialization of the FMPLLs settings. + TODO: Add settings for the MR registers.*/ + CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF | + ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL0_NDIV_VALUE << 16); + CGM.FMPLL[0].MR.R = 0; + CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF | + ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) | + (SPC5_FMPLL1_NDIV_VALUE << 16); + CGM.FMPLL[1].MR.R = 0; + + /* Run modes initialization, note writes to the MC registers are verified + by a protection mechanism, the operation success is verified at the + end of the sequence.*/ + ME.IS.R = 8; /* Resetting I_ICONF status.*/ + ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ + ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ + ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ + ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ + ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ + ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ + ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ + ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ + ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ + if (ME.IS.B.I_ICONF) { + /* Configuration rejected.*/ + SPC5_CLOCK_FAILURE_HOOK(); + } + + /* Peripherals run and low power modes initialization.*/ + ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; + ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; + ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; + ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; + ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; + ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; + ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; + ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; + ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; + ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; + ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; + ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; + ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; + ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; + ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; + ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; + + /* CFLASH settings initialized for a maximum clock of 120MHz.*/ + CFLASH.PFCR0.B.B02_APC = 3; + CFLASH.PFCR0.B.B02_WWSC = 3; + CFLASH.PFCR0.B.B02_RWSC = 3; + + /* Switches again to DRUN mode (current mode) in order to update the + settings.*/ + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) { + SPC5_CLOCK_FAILURE_HOOK(); + } + +#endif /* !SPC5_NO_INIT */ +} + +/** + * @brief Switches the system to the specified run mode. + * + * @param[in] mode one of the possible run modes + * + * @return The operation status. + * @retval CH_SUCCESS if the switch operation has been completed. + * @retval CH_FAILED if the switch operation failed. + */ +bool_t halSPCSetRunMode(spc5_runmode_t mode) { + + /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/ + ME.IS.R = 5; + + /* Starts a transition process.*/ + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; + + /* Waits for the mode switch or an error condition.*/ + while (TRUE) { + uint32_t r = ME.IS.R; + if (r & 1) + return CH_SUCCESS; + if (r & 4) + return CH_FAILED; + } +} + +/** + * @brief Changes the clock mode of a peripheral. + * + * @param[in] n index of the @p PCTL register + * @param[in] pctl new value for the @p PCTL register + * + * @notapi + */ +void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) { + uint32_t mode; + + ME.PCTL[n].R = pctl; + mode = ME.MCTL.B.TARGET_MODE; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; + ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV; +} + +#if !SPC5_NO_INIT || defined(__DOXYGEN__) +/** + * @brief Returns the system clock under the current run mode. + * + * @return The system clock in Hertz. + */ +uint32_t halSPCGetSystemClock(void) { + uint32_t sysclk; + + sysclk = ME.GS.B.S_SYSCLK; + switch (sysclk) { + case SPC5_ME_GS_SYSCLK_IRC: + return SPC5_IRC_CLK; + case SPC5_ME_GS_SYSCLK_XOSC: + return SPC5_XOSC_CLK; + case SPC5_ME_GS_SYSCLK_FMPLL0: + return SPC5_FMPLL0_CLK; + default: + return 0; + } +} +#endif /* !SPC5_NO_INIT */ + +/** @} */ diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h new file mode 100644 index 000000000..0c3266bce --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/hal_lld.h @@ -0,0 +1,983 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ELxx/hal_lld.h + * @brief SPC56ELxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - SPC5_XOSC_CLK. + * - SPC5_OSC_BYPASS (optionally). + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "xpc56el.h" +#include "spc56el_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "SPC56ELxx Chassis and Safety" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MAX 40000000 + +/** + * @brief Minimum XOSC clock frequency. + */ +#define SPC5_XOSC_CLK_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MIN 4000000 + +/** + * @brief Maximum FMPLLs input clock frequency. + */ +#define SPC5_FMPLLIN_MAX 40000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MAX 512000000 + +/** + * @brief Maximum FMPLLs VCO clock frequency. + */ +#define SPC5_FMPLLVCO_MIN 256000000 + +/** + * @brief Maximum FMPLL0 output clock frequency. + */ +#define SPC5_FMPLL0_CLK_MAX 120000000 + +/** + * @brief Maximum FMPLL1 output clock frequency. + */ +#define SPC5_FMPLL1_CLK_MAX 120000000 + +/** + * @brief Maximum FMPLL1 1D1 output clock frequency. + */ +#define SPC5_FMPLL1_1D1_CLK_MAX 80000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/ +/** @} */ + +/** + * @name FMPLLs register bits definitions + * @{ + */ +#define SPC5_FMPLL_SRC_IRC (0U << 24) +#define SPC5_FMPLL_SRC_XOSC (1U << 24) +/** @} */ + +/** + * @name FMPLL_CR register bits definitions + * @{ + */ +#define SPC5_FMPLL_ODF_DIV2 (0U << 24) +#define SPC5_FMPLL_ODF_DIV4 (1U << 24) +#define SPC5_FMPLL_ODF_DIV8 (2U << 24) +#define SPC5_FMPLL_ODF_DIV16 (3U << 24) +/** @} */ + +/** + * @name Clock selectors used in the various GCM SC registers + * @{ + */ +#define SPC5_CGM_SS_MASK (15U << 24) +#define SPC5_CGM_SS_IRC (0U << 24) +#define SPC5_CGM_SS_XOSC (2U << 24) +#define SPC5_CGM_SS_FMPLL0 (4U << 24) +#define SPC5_CGM_SS_FMPLL1 (5U << 24) +#define SPC5_CGM_SS_FMPLL1_1D1 (8U << 24) +/** @} */ + +/** + * @name ME_GS register bits definitions + * @{ + */ +#define SPC5_ME_GS_SYSCLK_MASK (15U << 0) +#define SPC5_ME_GS_SYSCLK_IRC (0U << 0) +#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) +#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) +/** @} */ + +/** + * @name ME_ME register bits definitions + * @{ + */ +#define SPC5_ME_ME_RESET (1U << 0) +#define SPC5_ME_ME_SAFE (1U << 2) +#define SPC5_ME_ME_DRUN (1U << 3) +#define SPC5_ME_ME_RUN0 (1U << 4) +#define SPC5_ME_ME_RUN1 (1U << 5) +#define SPC5_ME_ME_RUN2 (1U << 6) +#define SPC5_ME_ME_RUN3 (1U << 7) +#define SPC5_ME_ME_HALT0 (1U << 8) +#define SPC5_ME_ME_STOP0 (1U << 10) +/** @} */ + +/** + * @name ME_xxx_MC registers bits definitions + * @{ + */ +#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) +#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_IRCON (1U << 4) +#define SPC5_ME_MC_XOSC0ON (1U << 5) +#define SPC5_ME_MC_PLL0ON (1U << 6) +#define SPC5_ME_MC_PLL1ON (1U << 7) +#define SPC5_ME_MC_FLAON_MASK ((3U << 16) | (3U << 18)) +#define SPC5_ME_MC_FLAON(n) (((n) << 16) | ((n) << 18)) +#define SPC5_ME_MC_FLAON_PD ((1U << 16) | (1U << 18)) +#define SPC5_ME_MC_FLAON_LP ((2U << 16) | (2U << 18)) +#define SPC5_ME_MC_FLAON_NORMAL ((3U << 16) | (3U << 18)) +#define SPC5_ME_MC_MVRON (1U << 20) +#define SPC5_ME_MC_PDO (1U << 23) +/** @} */ + +/** + * @name ME_MCTL register bits definitions + * @{ + */ +#define SPC5_ME_MCTL_KEY 0x5AF0U +#define SPC5_ME_MCTL_KEY_INV 0xA50FU +#define SPC5_ME_MCTL_MODE_MASK (15U << 28) +#define SPC5_ME_MCTL_MODE(n) ((n) << 28) +/** @} */ + +/** + * @name ME_RUN_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_RUN_PC_SAFE (1U << 2) +#define SPC5_ME_RUN_PC_DRUN (1U << 3) +#define SPC5_ME_RUN_PC_RUN0 (1U << 4) +#define SPC5_ME_RUN_PC_RUN1 (1U << 5) +#define SPC5_ME_RUN_PC_RUN2 (1U << 6) +#define SPC5_ME_RUN_PC_RUN3 (1U << 7) +/** @} */ + +/** + * @name ME_LP_PCx registers bits definitions + * @{ + */ +#define SPC5_ME_LP_PC_HALT0 (1U << 8) +#define SPC5_ME_LP_PC_STOP0 (1U << 10) +/** @} */ + +/** + * @name ME_PCTL registers bits definitions + * @{ + */ +#define SPC5_ME_PCTL_RUN_MASK (7U << 0) +#define SPC5_ME_PCTL_RUN(n) ((n) << 0) +#define SPC5_ME_PCTL_LP_MASK (7U << 3) +#define SPC5_ME_PCTL_LP(n) ((n) << 3) +#define SPC5_ME_PCTL_DBG (1U << 6) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC5_NO_INIT FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC5_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief Disables the watchdog on start. + */ +#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__) +#define SPC5_DISABLE_WATCHDOG TRUE +#endif + +/** + * @brief FMPLL0 Clock source. + */ +#if !defined(SPC5_FMPLL0_CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#endif + +/** + * @brief FMPLL0 IDF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_IDF_VALUE 5 +#endif + +/** + * @brief FMPLL0 NDIV divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_NDIV_VALUE 60 +#endif + +/** + * @brief FMPLL0 ODF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#endif + +/** + * @brief FMPLL1 Clock source. + */ +#if !defined(SPC5_FMPLL1_CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#endif + +/** + * @brief FMPLL1 IDF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_IDF_VALUE 5 +#endif + +/** + * @brief FMPLL1 NDIV divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_NDIV_VALUE 60 +#endif + +/** + * @brief FMPLL1 ODF divider value. + * @note The default value is calculated for XOSC=40MHz and PHI=120MHz. + */ +#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__) +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#endif + +/** + * @brief System clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_SYSCLK_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX0 clock source. + */ +#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief Motor Control clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#endif + +/** + * @brief SWG clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_SWG_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_SWG_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX1 clock source. + * @note Used by Flexray. + */ +#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief Flexray clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_FLEXRAY_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#endif + +/** + * @brief AUX2 clock source. + * @note Used by FlexCAN. + */ +#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__) +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#endif + +/** + * @brief FlexCAN clock divider value. + * @note Zero means disabled clock. + */ +#if !defined(SPC5_FLEXCAN_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#endif + +/** + * @brief Active run modes in ME_ME register. + * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there + * is no need to specify them. + */ +#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#endif + +/** + * @brief SAFE mode settings. + */ +#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#endif + +/** + * @brief DRUN mode settings. + */ +#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN0 mode settings. + */ +#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN1 mode settings. + */ +#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN2 mode settings. + */ +#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief RUN3 mode settings. + */ +#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief HALT0 mode settings. + */ +#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief STOP0 mode settings. + */ +#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#endif + +/** + * @brief Peripheral mode 0 (run mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (run mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 2 (run mode). + * @note Do not change this setting, it is expected to be the "only during + * normal run" mode. + */ +#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 3 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 4 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 5 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 6 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 7 (run mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#endif + +/** + * @brief Peripheral mode 0 (low power mode). + * @note Do not change this setting, it is expected to be the "never run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC0_BITS 0 +#endif + +/** + * @brief Peripheral mode 1 (low power mode). + * @note Do not change this setting, it is expected to be the "always run" + * mode. + */ +#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 2 (low power mode). + * @note Do not change this setting, it is expected to be the "halt only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#endif + +/** + * @brief Peripheral mode 3 (low power mode). + * @note Do not change this setting, it is expected to be the "stop only" + * mode. + */ +#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 4 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 5 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 6 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Peripheral mode 7 (low power mode). + * @note Not defined, available to application-specific modes. + */ +#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#endif + +/** + * @brief Clock initialization failure hook. + * @note The default is to stop the system and let the RTC restart it. + * @note The hook code must not return. + */ +#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC56ELxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC56ELxx_MCUCONF not defined" +#endif + +/* Check on the XOSC frequency.*/ +#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ + (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) +#error "invalid SPC5_XOSC_CLK value specified" +#endif + +/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/ +#if SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_IRC +#define SPC5_FMPLL0_INPUT_CLK SPC5_IRC_CLK +#elif SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_INPUT_CLK SPC5_XOSC_CLK +#else +#error "invalid SPC5_FMPLL0_CLK_SRC value specified" +#endif + +/* Check on SPC5_FMPLL0_IDF_VALUE.*/ +#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL0_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_NDIV_VALUE.*/ +#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL0_ODF.*/ +#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL0_ODF_VALUE 2 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL0_ODF_VALUE 4 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL0_ODF_VALUE 8 +#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL0_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL0_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL0_VCO_CLK clock point. + */ +#define SPC5_FMPLL0_VCO_CLK \ + ((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE) + +/* Check on FMPLL0 VCO output.*/ +#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL0_CLK clock point. + */ +#define SPC5_FMPLL0_CLK \ + (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE) + +/* Check on SPC5_FMPLL0_CLK.*/ +#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)" +#endif + +/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/ +#if SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_IRC +#define SPC5_FMPLL1_INPUT_CLK SPC5_IRC_CLK +#elif SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_INPUT_CLK SPC5_XOSC_CLK +#else +#error "invalid SPC5_FMPLL1_CLK_SRC value specified" +#endif + +/* Check on SPC5_FMPLL1_IDF_VALUE.*/ +#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15) +#error "invalid SPC5_FMPLL1_IDF_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL1_NDIV_VALUE.*/ +#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96) +#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified" +#endif + +/* Check on SPC5_FMPLL1_ODF.*/ +#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2) +#define SPC5_FMPLL1_ODF_VALUE 2 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4) +#define SPC5_FMPLL1_ODF_VALUE 4 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8) +#define SPC5_FMPLL1_ODF_VALUE 8 +#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16) +#define SPC5_FMPLL1_ODF_VALUE 16 +#else +#error "invalid SPC5_FMPLL1_ODF value specified" +#endif + +/** + * @brief SPC5_FMPLL1_VCO_CLK clock point. + */ +#define SPC5_FMPLL1_VCO_CLK \ + ((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE) + +/* Check on FMPLL1 VCO output.*/ +#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \ + (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX) +#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)" +#endif + +/** + * @brief SPC5_FMPLL1_CLK clock point. + */ +#define SPC5_FMPLL1_CLK \ + (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE) + +/** + * @brief SPC5_FMPLL1_1D1_CLK clock point. + */ +#define SPC5_FMPLL1_1D1_CLK \ + (SPC5_FMPLL1_VCO_CLK / 6) + +/* Check on SPC5_FMPLL1_CLK.*/ +#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK +#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)" +#endif + +/* Check on the system divider settings.*/ +#if SPC5_SYSCLK_DIVIDER_VALUE == 0 +#define SPC5_CGM_SC_DC0 0 +#elif (SPC5_SYSCLK_DIVIDER_VALUE >= 1) && (SPC5_SYSCLK_DIVIDER_VALUE <= 16) +#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_SYSCLK_DIVIDER_VALUE - 1)) +#else +#error "invalid SPC5_SYSCLK_DIVIDER_VALUE value specified" +#endif + +/** + * @brief AUX0 clock point. + */ +#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__) +#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_IRC +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC +#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_XOSC +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0 +#define SPC5_AUX0_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX0_CLK SPC5_FMPLL1_CLK +#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1 +#define SPC5_AUX0_CLK SPC5_FMPLL1_1D1_CLK +#else +#error "invalid SPC5_AUX0CLK_SRC value specified" +#endif + +/* Check on the AUX0 divider 0 settings.*/ +#if SPC5_MCONTROL_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC0_DC0 0 +#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC0_DC0 ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified" +#endif + +/* Check on the AUX0 divider 1 settings.*/ +#if SPC5_SWG_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC0_DC1 0 +#elif (SPC5_SWG_DIVIDER_VALUE >= 1) && (SPC5_SWG_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC0_DC1 ((0x80U | (SPC5_SWG_DIVIDER_VALUE - 1)) << 16) +#else +#error "invalid SPC5_SWG_DIVIDER_VALUE value specified" +#endif + +/** + * @brief Motor Control clock point. + */ +#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_MCONTROL_CLK (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE) +#else +#define SPC5_MCONTROL_CLK 0 +#endif + +/** + * @brief SWG clock point. + */ +#if (SPC5_SWG_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_SWG_CLK (SPC5_AUX0_CLK / SPC5_SWG_DIVIDER_VALUE) +#else +#define SPC5_SWG_CLK 0 +#endif + +/** + * @brief AUX1 clock point. + */ +#if (SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__) +#define SPC5_AUX1_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX1_CLK SPC5_FMPLL1_CLK +#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1 +#define SPC5_AUX1_CLK SPC5_FMPLL1_1D1_CLK +#else +#error "invalid SPC5_AUX1CLK_SRC value specified" +#endif + +/* Check on the AUX1 divider 0 settings.*/ +#if SPC5_FLEXRAY_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC1_DC0 0 +#elif (SPC5_FLEXRAY_DIVIDER_VALUE >= 1) && (SPC5_FLEXRAY_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC1_DC0 ((0x80U | (SPC5_FLEXRAY_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_FLEXRAY_DIVIDER_VALUE value specified" +#endif + +/** + * @brief Flexray clock point. + */ +#if (SPC5_FLEXRAY_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_FLEXRAY_CLK (SPC5_AUX2_CLK / SPC5_FLEXRAY_DIVIDER_VALUE) +#else +#define SPC5_FLEXRAY_CLK 0 +#endif + +/** + * @brief AUX2 clock point. + */ +#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__) +#define SPC5_AUX2_CLK SPC5_FMPLL0_CLK +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1 +#define SPC5_AUX2_CLK SPC5_FMPLL1_CLK +#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1 +#define SPC5_AUX2_CLK SPC5_FMPLL1_1D1_CLK +#else +#error "invalid SPC5_AUX2CLK_SRC value specified" +#endif + +/* Check on the AUX2 divider 0 settings.*/ +#if SPC5_FLEXCAN_DIVIDER_VALUE == 0 +#define SPC5_CGM_AC2_DC0 0 +#elif (SPC5_FLEXCAN_DIVIDER_VALUE >= 1) && (SPC5_FLEXCAN_DIVIDER_VALUE <= 16) +#define SPC5_CGM_AC2_DC0 ((0x80U | (SPC5_FLEXCAN_DIVIDER_VALUE - 1)) << 24) +#else +#error "invalid SPC5_FLEXCAN_DIVIDER_VALUE value specified" +#endif + +/** + * @brief FlexCAN clock point. + */ +#if (SPC5_FLEXCAN_DIVIDER_VALUE) != 0 || defined(__DOXYGEN) +#define SPC5_FLEXCAN_CLK (SPC5_AUX2_CLK / SPC5_FLEXCAN_DIVIDER_VALUE) +#else +#define SPC5_FLEXCAN_CLK 0 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/** + * @brief Run modes. + */ +typedef enum { + SPC5_RUNMODE_SAFE = 2, + SPC5_RUNMODE_DRUN = 3, + SPC5_RUNMODE_RUN0 = 4, + SPC5_RUNMODE_RUN1 = 5, + SPC5_RUNMODE_RUN2 = 6, + SPC5_RUNMODE_RUN3 = 7, + SPC5_RUNMODE_HALT0 = 8, + SPC5_RUNMODE_STOP0 = 10 +} spc5_runmode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Realtime counter frequency. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() (halclock_t)halSPCGetSystemClock() + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "spc5_edma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + halrtcnt_t hal_lld_get_counter_value(void); + void spc_early_init(void); + bool_t halSPCSetRunMode(spc5_runmode_t mode); + void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); +#if !SPC5_NO_INIT + uint32_t halSPCGetSystemClock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC56ELxx/platform.mk b/os/hal/platforms/SPC56ELxx/platform.mk new file mode 100644 index 000000000..07f558c7c --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/platform.mk @@ -0,0 +1,17 @@ +# List of all the SPC56ELxx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1 diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h new file mode 100644 index 000000000..6ab0ae2e2 --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -0,0 +1,292 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ELxx/spc56el_registry.h + * @brief SPC56ELxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _SPC56EL_REGISTRY_H_ +#define _SPC56EL_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SPC56ELxx capabilities + * @{ + */ +/* eDMA attributes.*/ +#define SPC5_HAS_EDMA TRUE +#define SPC5_EDMA_NCHANNELS 16 +#define SPC5_EDMA_HAS_MUX TRUE + +/* DSPI attribures.*/ +#define SPC5_HAS_DSPI0 TRUE +#define SPC5_HAS_DSPI1 TRUE +#define SPC5_HAS_DSPI2 TRUE +#define SPC5_HAS_DSPI3 FALSE +#define SPC5_HAS_DSPI4 FALSE +#define SPC5_DSPI_FIFO_DEPTH 5 +#define SPC5_DSPI0_PCTL 4 +#define SPC5_DSPI1_PCTL 5 +#define SPC5_DSPI2_PCTL 6 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_DSPI2_TX1_DMA_CH_ID 10 +#define SPC5_DSPI2_TX2_DMA_CH_ID 11 +#define SPC5_DSPI2_RX_DMA_CH_ID 12 +#define SPC5_DSPI0_TX1_DMA_DEV_ID 1 +#define SPC5_DSPI0_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI0_RX_DMA_DEV_ID 2 +#define SPC5_DSPI1_TX1_DMA_DEV_ID 3 +#define SPC5_DSPI1_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI1_RX_DMA_DEV_ID 4 +#define SPC5_DSPI2_TX1_DMA_DEV_ID 5 +#define SPC5_DSPI2_TX2_DMA_DEV_ID 0 +#define SPC5_DSPI2_RX_DMA_DEV_ID 6 +#define SPC5_DSPI0_TFFF_HANDLER vector76 +#define SPC5_DSPI0_TFFF_NUMBER 76 +#define SPC5_DSPI1_TFFF_HANDLER vector96 +#define SPC5_DSPI1_TFFF_NUMBER 96 +#define SPC5_DSPI2_TFFF_HANDLER vector116 +#define SPC5_DSPI2_TFFF_NUMBER 116 +#define SPC5_DSPI0_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL) +#define SPC5_DSPI0_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL) +#define SPC5_DSPI1_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL) +#define SPC5_DSPI1_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL) +#define SPC5_DSPI2_ENABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL) +#define SPC5_DSPI2_DISABLE_CLOCK() \ + halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL) + +/* LINFlex attributes.*/ +#define SPC5_HAS_LINFLEX0 TRUE +#define SPC5_LINFLEX0_PCTL 48 +#define SPC5_LINFLEX0_RXI_HANDLER vector79 +#define SPC5_LINFLEX0_TXI_HANDLER vector80 +#define SPC5_LINFLEX0_ERR_HANDLER vector81 +#define SPC5_LINFLEX0_RXI_NUMBER 79 +#define SPC5_LINFLEX0_TXI_NUMBER 80 +#define SPC5_LINFLEX0_ERR_NUMBER 81 +#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \ + SPC5_SYSCLK_DIVIDER_VALUE) + +#define SPC5_HAS_LINFLEX1 TRUE +#define SPC5_LINFLEX1_PCTL 49 +#define SPC5_LINFLEX1_RXI_HANDLER vector99 +#define SPC5_LINFLEX1_TXI_HANDLER vector100 +#define SPC5_LINFLEX1_ERR_HANDLER vector101 +#define SPC5_LINFLEX1_RXI_NUMBER 99 +#define SPC5_LINFLEX1_TXI_NUMBER 100 +#define SPC5_LINFLEX1_ERR_NUMBER 101 +#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \ + SPC5_SYSCLK_DIVIDER_VALUE) + +#define SPC5_HAS_LINFLEX2 FALSE + +#define SPC5_HAS_LINFLEX3 FALSE + +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_NUM_PORTS 8 +#define SPC5_SIUL_NUM_PCRS 133 +#define SPC5_SIUL_NUM_PADSELS 44 +/** @} */ + +/* FlexPWM attributes.*/ +#define SPC5_HAS_FLEXPWM0 TRUE +#define SPC5_FLEXPWM0_PCTL 41 +#define SPC5_FLEXPWM0_RF0_HANDLER vector179 +#define SPC5_FLEXPWM0_COF0_HANDLER vector180 +#define SPC5_FLEXPWM0_CAF0_HANDLER vector181 +#define SPC5_FLEXPWM0_RF1_HANDLER vector182 +#define SPC5_FLEXPWM0_COF1_HANDLER vector183 +#define SPC5_FLEXPWM0_CAF1_HANDLER vector184 +#define SPC5_FLEXPWM0_RF2_HANDLER vector185 +#define SPC5_FLEXPWM0_COF2_HANDLER vector186 +#define SPC5_FLEXPWM0_CAF2_HANDLER vector187 +#define SPC5_FLEXPWM0_RF3_HANDLER vector188 +#define SPC5_FLEXPWM0_COF3_HANDLER vector189 +#define SPC5_FLEXPWM0_CAF3_HANDLER vector190 +#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191 +#define SPC5_FLEXPWM0_REF_HANDLER vector192 +#define SPC5_FLEXPWM0_RF0_NUMBER 179 +#define SPC5_FLEXPWM0_COF0_NUMBER 180 +#define SPC5_FLEXPWM0_CAF0_NUMBER 181 +#define SPC5_FLEXPWM0_RF1_NUMBER 182 +#define SPC5_FLEXPWM0_COF1_NUMBER 183 +#define SPC5_FLEXPWM0_CAF1_NUMBER 184 +#define SPC5_FLEXPWM0_RF2_NUMBER 185 +#define SPC5_FLEXPWM0_COF2_NUMBER 186 +#define SPC5_FLEXPWM0_CAF2_NUMBER 187 +#define SPC5_FLEXPWM0_RF3_NUMBER 188 +#define SPC5_FLEXPWM0_COF3_NUMBER 189 +#define SPC5_FLEXPWM0_CAF3_NUMBER 190 +#define SPC5_FLEXPWM0_FFLAG_NUMBER 191 +#define SPC5_FLEXPWM0_REF_NUMBER 192 +#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK + +#define SPC5_HAS_FLEXPWM1 TRUE +#define SPC5_FLEXPWM1_PCTL 42 +#define SPC5_FLEXPWM1_RF0_HANDLER vector233 +#define SPC5_FLEXPWM1_COF0_HANDLER vector234 +#define SPC5_FLEXPWM1_CAF0_HANDLER vector235 +#define SPC5_FLEXPWM1_RF1_HANDLER vector236 +#define SPC5_FLEXPWM1_COF1_HANDLER vector237 +#define SPC5_FLEXPWM1_CAF1_HANDLER vector238 +#define SPC5_FLEXPWM1_RF2_HANDLER vector239 +#define SPC5_FLEXPWM1_COF2_HANDLER vector240 +#define SPC5_FLEXPWM1_CAF2_HANDLER vector241 +#define SPC5_FLEXPWM1_RF3_HANDLER vector242 +#define SPC5_FLEXPWM1_COF3_HANDLER vector243 +#define SPC5_FLEXPWM1_CAF3_HANDLER vector244 +#define SPC5_FLEXPWM1_FFLAG_HANDLER vector245 +#define SPC5_FLEXPWM1_REF_HANDLER vector246 +#define SPC5_FLEXPWM1_RF0_NUMBER 233 +#define SPC5_FLEXPWM1_COF0_NUMBER 234 +#define SPC5_FLEXPWM1_CAF0_NUMBER 235 +#define SPC5_FLEXPWM1_RF1_NUMBER 236 +#define SPC5_FLEXPWM1_COF1_NUMBER 237 +#define SPC5_FLEXPWM1_CAF1_NUMBER 238 +#define SPC5_FLEXPWM1_RF2_NUMBER 239 +#define SPC5_FLEXPWM1_COF2_NUMBER 240 +#define SPC5_FLEXPWM1_CAF2_NUMBER 241 +#define SPC5_FLEXPWM1_RF3_NUMBER 242 +#define SPC5_FLEXPWM1_COF3_NUMBER 243 +#define SPC5_FLEXPWM1_CAF3_NUMBER 244 +#define SPC5_FLEXPWM1_FFLAG_NUMBER 245 +#define SPC5_FLEXPWM1_REF_NUMBER 246 +#define SPC5_FLEXPWM1_CLK SPC5_MCONTROL_CLK + +/* eTimer attributes.*/ +#define SPC5_HAS_ETIMER0 TRUE +#define SPC5_ETIMER0_PCTL 38 +#define SPC5_ETIMER0_TC0IR_HANDLER vector157 +#define SPC5_ETIMER0_TC1IR_HANDLER vector158 +#define SPC5_ETIMER0_TC2IR_HANDLER vector159 +#define SPC5_ETIMER0_TC3IR_HANDLER vector160 +#define SPC5_ETIMER0_TC4IR_HANDLER vector161 +#define SPC5_ETIMER0_TC5IR_HANDLER vector162 +#define SPC5_ETIMER0_WTIF_HANDLER vector165 +#define SPC5_ETIMER0_RCF_HANDLER vector167 +#define SPC5_ETIMER0_TC0IR_NUMBER 157 +#define SPC5_ETIMER0_TC1IR_NUMBER 158 +#define SPC5_ETIMER0_TC2IR_NUMBER 159 +#define SPC5_ETIMER0_TC3IR_NUMBER 160 +#define SPC5_ETIMER0_TC4IR_NUMBER 161 +#define SPC5_ETIMER0_TC5IR_NUMBER 162 +#define SPC5_ETIMER0_WTIF_NUMBER 165 +#define SPC5_ETIMER0_RCF_NUMBER 167 +#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK + +#define SPC5_HAS_ETIMER1 TRUE +#define SPC5_ETIMER1_PCTL 39 +#define SPC5_ETIMER1_TC0IR_HANDLER vector168 +#define SPC5_ETIMER1_TC1IR_HANDLER vector169 +#define SPC5_ETIMER1_TC2IR_HANDLER vector170 +#define SPC5_ETIMER1_TC3IR_HANDLER vector171 +#define SPC5_ETIMER1_TC4IR_HANDLER vector172 +#define SPC5_ETIMER1_TC5IR_HANDLER vector173 +#define SPC5_ETIMER1_RCF_HANDLER vector178 +#define SPC5_ETIMER1_TC0IR_NUMBER 168 +#define SPC5_ETIMER1_TC1IR_NUMBER 169 +#define SPC5_ETIMER1_TC2IR_NUMBER 170 +#define SPC5_ETIMER1_TC3IR_NUMBER 171 +#define SPC5_ETIMER1_TC4IR_NUMBER 172 +#define SPC5_ETIMER1_TC5IR_NUMBER 173 +#define SPC5_ETIMER1_RCF_NUMBER 178 +#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK + +#define SPC5_HAS_ETIMER2 TRUE +#define SPC5_ETIMER2_PCTL 40 +#define SPC5_ETIMER2_TC0IR_HANDLER vector222 +#define SPC5_ETIMER2_TC1IR_HANDLER vector223 +#define SPC5_ETIMER2_TC2IR_HANDLER vector224 +#define SPC5_ETIMER2_TC3IR_HANDLER vector225 +#define SPC5_ETIMER2_TC4IR_HANDLER vector226 +#define SPC5_ETIMER2_TC5IR_HANDLER vector227 +#define SPC5_ETIMER2_RCF_HANDLER vector232 +#define SPC5_ETIMER2_TC0IR_NUMBER 222 +#define SPC5_ETIMER2_TC1IR_NUMBER 223 +#define SPC5_ETIMER2_TC2IR_NUMBER 224 +#define SPC5_ETIMER2_TC3IR_NUMBER 225 +#define SPC5_ETIMER2_TC4IR_NUMBER 226 +#define SPC5_ETIMER2_TC5IR_NUMBER 227 +#define SPC5_ETIMER2_RCF_NUMBER 232 +#define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 32 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 +#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL); +#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL); + +#define SPC5_HAS_FLEXCAN1 TRUE +#define SPC5_FLEXCAN1_PCTL 17 +#define SPC5_FLEXCAN1_MB 32 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER vector87 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_NUMBER 87 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92 +#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL); +#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL); +/** @} */ + +#endif /* _SPC56EL_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC56ELxx/typedefs.h b/os/hal/platforms/SPC56ELxx/typedefs.h new file mode 100644 index 000000000..ca81e4b84 --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/typedefs.h @@ -0,0 +1,27 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ELxx/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC56ELxx/xpc56el.h b/os/hal/platforms/SPC56ELxx/xpc56el.h new file mode 100644 index 000000000..5d9dfefcc --- /dev/null +++ b/os/hal/platforms/SPC56ELxx/xpc56el.h @@ -0,0 +1,20796 @@ +/****************************************************************************\ + * PROJECT : MPC5643L + * FILE : mpc5643l.h + * + * DESCRIPTION : This is the header file describing the register + * set for the named projects. + * + * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics + * + * VERSION : 1.01 + * DATE : Thu Oct 8 13:53:51 CEST 2009 + * AUTHOR : generated from IP-XACT database + * HISTORY : Preliminary release. +\****************************************************************************/ + +/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */ + +/****************************************************************************\ + * Example instantiation and use: + * + * ..B. = 1; + * ..R = 0x10000000; + * +\****************************************************************************/ + + +#ifndef _leopard_H_ /* prevents multiple inclusions of this file */ +#define _leopard_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/* #define USE_FIELD_ALIASES_CFLASH */ +/* #define USE_FIELD_ALIASES_SIUL */ +/* #define USE_FIELD_ALIASES_SSCM */ +/* #define USE_FIELD_ALIASES_ME */ +/* #define USE_FIELD_ALIASES_RGM */ +/* #define USE_FIELD_ALIASES_ADC */ +/* #define USE_FIELD_ALIASES_CTU */ +/* #define USE_FIELD_ALIASES_mcTIMER */ +/* #define USE_FIELD_ALIASES_mcPWM */ +/* #define USE_FIELD_ALIASES_LINFLEX */ +/* #define USE_FIELD_ALIASES_SPP_MCM */ +/* #define USE_FIELD_ALIASES_INTC */ +/* #define USE_FIELD_ALIASES_DSPI */ +/* #define USE_FIELD_ALIASES_FLEXCAN */ +/* #define USE_FIELD_ALIASES_FR */ + +/****************************************************************/ +/* */ +/* Global definitions and aliases */ +/* */ +/****************************************************************/ + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the _1 defines are the preferred method for programming + */ +#define AIPS_1 (*(volatile struct AIPS_tag*) 0x8FF00000UL) +#define MAX_1 (*(volatile struct MAX_tag*) 0x8FF04000UL) +#define MPU_1 (*(volatile struct MPU_tag*) 0x8FF10000UL) +#define SEMA4_1 (*(volatile struct SEMA4_tag*) 0x8FF24000UL) +#define SWT_1 (*(volatile struct SWT_tag*) 0x8FF38000UL) +#define STM_1 (*(volatile struct STM_tag*) 0x8FF3C000UL) +#define SPP_MCM_1 (*(volatile struct SPP_MCM_tag*) 0x8FF40000UL) +#define SPP_DMA2_1 (*(volatile struct SPP_DMA2_tag*) 0x8FF44000UL) +#define INTC_1 (*(volatile struct INTC_tag*) 0x8FF48000UL) + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the _DPM defines are deprecated, use _1 for + programming the corresponding blocks for new code instead. + */ +#define AIPS_DPM AIPS_1 +#define MAX_DPM MAX_1 +#define MPU_DPM MPU_1 +#define SEMA4_DPM SEMA4_1 +#define SWT_DPM SWT_1 +#define STM_DPM STM_1 +#define SPP_MCM_DPM SPP_MCM_1 +#define SPP_DMA2_DPM SPP_DMA2_1 +#define INTC_DPM INTC_1 + +/* Aliases for Pictus Module names */ +#define CAN_0 FLEXCAN_A +#define CAN_1 FLEXCAN_B +#define CTU_0 CTU +#define DFLASH CRC +#define DMAMUX DMA_CH_MUX +#define DSPI_0 DSPI_A +#define DSPI_1 DSPI_B +#define DSPI_2 DSPI_C +#define EDMA SPP_DMA2 +#define ETIMER_0 mcTIMER0 +#define ETIMER_1 mcTIMER1 +#define FLEXPWM_0 mcPWM_A +#define FLEXPWM_1 mcPWM_B +#define LINFLEX_0 LINFLEX0 +#define LINFLEX_1 LINFLEX1 +#define MCM_ SPP_MCM +#define PIT PIT_RTI +#define SIU SIUL +#define WKUP WKPU +/****************************************************************/ +/* */ +/* Module: CFLASH_SHADOW */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers NVPWD... */ + + typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + vuint32_t R; + struct { + vuint32_t PWD:32; /* PassWorD */ + } B; + } CFLASH_SHADOW_NVPWD_32B_tag; + + + /* Register layout for all registers NVSCI... */ + + typedef union { /* NVSCI - Non Volatile System Censoring Information Register */ + vuint32_t R; + struct { + vuint32_t SC:16; /* Serial Censorship Control Word */ + vuint32_t CW:16; /* Censorship Control Word */ + } B; + } CFLASH_SHADOW_NVSCI_32B_tag; + + typedef union { /* Non Volatile LML Default Value */ + vuint32_t R; + } CFLASH_SHADOW_NVLML_32B_tag; + + typedef union { /* Non Volatile HBL Default Value */ + vuint32_t R; + } CFLASH_SHADOW_NVHBL_32B_tag; + + typedef union { /* Non Volatile SLL Default Value */ + vuint32_t R; + } CFLASH_SHADOW_NVSLL_32B_tag; + + + /* Register layout for all registers NVBIU... */ + + typedef union { /* Non Volatile Bus Interface Unit Register */ + vuint32_t R; + struct { + vuint32_t BI:32; /* Bus interface Unit */ + } B; + } CFLASH_SHADOW_NVBIU_32B_tag; + + typedef union { /* NVUSRO - Non Volatile USeR Options Register */ + vuint32_t R; + struct { + vuint32_t UO:32; /* User Options */ + } B; + } CFLASH_SHADOW_NVUSRO_32B_tag; + + + typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag { + + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */ + int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4]; + + } CFLASH_SHADOW_BIU_DEFAULTS_tag; + + + typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */ + int8_t CFLASH_SHADOW_reserved_0000_C[15832]; + union { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */ + + struct { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */ + }; + + }; + union { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */ + + struct { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */ + }; + + }; + /* Non Volatile LML Default Value */ + CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DEC[4]; + /* Non Volatile HBL Default Value */ + CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DF4[4]; + /* Non Volatile SLL Default Value */ + CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DFC_C[4]; + union { + /* Register set BIU_DEFAULTS */ + CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */ + + struct { + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E04_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E0C_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E14_E1[4]; + }; + + }; + /* NVUSRO - Non Volatile USeR Options Register */ + CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */ + } CFLASH_SHADOW_tag; + + +#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL) + + + +/****************************************************************/ +/* */ +/* Module: CFLASH */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t SIZE:3; /* Array Space Size */ + vuint32_t:1; + vuint32_t LAS:3; /* Low Address Space */ + vuint32_t:3; + vuint32_t MAS:1; /* Mid Address Space Configuration */ + vuint32_t EER:1; /* ECC Event Error */ + vuint32_t RWE:1; /* Read-while-Write Event Error */ + vuint32_t SBC:1; /* Single Bit Correction */ + vuint32_t:1; + vuint32_t PEAS:1; /* Program/Erase Access Space */ + vuint32_t DONE:1; /* modify operation DONE */ + vuint32_t PEG:1; /* Program/Erase Good */ + vuint32_t:4; + vuint32_t PGM:1; /* Program Bit */ + vuint32_t PSUS:1; /* Program Suspend */ + vuint32_t ERS:1; /* Erase Bit */ + vuint32_t ESUS:1; /* Erase Suspend */ + vuint32_t EHV:1; /* Enable High Voltage */ + } B; + } CFLASH_MCR_32B_tag; + + typedef union { /* LML - Low/Mid Address Space Block Locking Register */ + vuint32_t R; + struct { + vuint32_t LME:1; /* Low/Mid Address Space Block Enable */ + vuint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t SLOCK:1; /* Shadow Address Space Block Lock */ +#else + vuint32_t TSLK:1; /* deprecated name - please avoid */ +#endif + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t MLOCK:2; /* Mid Address Space Block Lock */ +#else + vuint32_t MLK:2; /* deprecated name - please avoid */ +#endif + vuint32_t:6; + vuint32_t LLOCK:10; /* Low Address Space Block Lock */ + } B; + } CFLASH_LML_32B_tag; + + typedef union { /* HBL - High Address Space Block Locking Register */ + vuint32_t R; + struct { + vuint32_t HBE:1; /* High Address Space Block Enable */ + vuint32_t:25; + vuint32_t HLOCK:6; /* High Address Space Block Lock */ + } B; + } CFLASH_HBL_32B_tag; + + typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + vuint32_t R; + struct { + vuint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */ + vuint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */ +#else + vuint32_t STSLK:1; /* deprecated name - please avoid */ +#endif + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */ +#else + vuint32_t SMK:2; /* deprecated name - please avoid */ +#endif + vuint32_t:6; + vuint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */ + } B; + } CFLASH_SLL_32B_tag; + + typedef union { /* LMS - Low/Mid Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t MSL:2; /* Mid Address Space Block Select */ + vuint32_t:6; + vuint32_t LSL:10; /* Low Address Space Block Select */ + } B; + } CFLASH_LMS_32B_tag; + + typedef union { /* HBS - High Address Space Block Select Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t HSL:6; /* High Address Space Block Select */ + } B; + } CFLASH_HBS_32B_tag; + + typedef union { /* ADR - Address Register */ + vuint32_t R; + struct { + vuint32_t SAD:1; /* Shadow Address */ + vuint32_t:10; + vuint32_t ADDR:18; /* Address */ + vuint32_t:3; + } B; + } CFLASH_ADR_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */ +#else + vuint32_t BK0_APC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */ +#else + vuint32_t BK0_WWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */ +#else + vuint32_t BK0_RWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */ +#else + vuint32_t BK0_RWWC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */ +#else + vuint32_t BK0_RWWC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */ +#else + vuint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */ +#else + vuint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */ +#else + vuint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */ +#else + vuint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */ +#else + vuint32_t B0_P1_BFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */ +#else + vuint32_t BK0_RWWC0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */ +#else + vuint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */ +#else + vuint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */ +#else + vuint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */ +#else + vuint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */ +#else + vuint32_t B0_P0_BFE:1; /* deprecated name - please avoid */ +#endif + } B; + } CFLASH_PFCR0_32B_tag; + + + /* Register layout for all registers BIU... */ + + typedef union { /* Bus Interface Unit Register */ + vuint32_t R; + } CFLASH_BIU_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */ + vuint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */ + vuint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */ + vuint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */ + vuint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */ + vuint32_t:6; + vuint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */ + vuint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */ + vuint32_t:6; + vuint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */ +#else + vuint32_t BK1_APC:5; + vuint32_t BK1_WWSC:5; + vuint32_t BK1_RWSC:5; + vuint32_t BK1_RWWC2:1; + vuint32_t BK1_RWWC1:1; + vuint32_t:6; + vuint32_t B0_P1_BFE:1; + vuint32_t BK1_RWWC0:1; + vuint32_t:6; + vuint32_t B1_P0_BFE:1; +#endif + } B; + } CFLASH_PFCR1_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t ARBM:2; /* Arbitration Mode */ + vuint32_t M7PFD:1; /* Master x Prefetch Disable */ + vuint32_t M6PFD:1; /* Master x Prefetch Disable */ + vuint32_t M5PFD:1; /* Master x Prefetch Disable */ + vuint32_t M4PFD:1; /* Master x Prefetch Disable */ + vuint32_t M3PFD:1; /* Master x Prefetch Disable */ + vuint32_t M2PFD:1; /* Master x Prefetch Disable */ + vuint32_t M1PFD:1; /* Master x Prefetch Disable */ + vuint32_t M0PFD:1; /* Master x Prefetch Disable */ + vuint32_t M7AP:2; /* Master 7 Access Protection */ + vuint32_t M6AP:2; /* Master 6 Access Protection */ + vuint32_t M5AP:2; /* Master 5 Access Protection */ + vuint32_t M4AP:2; /* Master 4 Access Protection */ + vuint32_t M3AP:2; /* Master 3 Access Protection */ + vuint32_t M2AP:2; /* Master 2 Access Protection */ + vuint32_t M1AP:2; /* Master 1 Access Protection */ + vuint32_t M0AP:2; /* Master 0 Access Protection */ + } B; + } CFLASH_PFAPR_32B_tag; + + typedef union { /* UT0 - User Test Register */ + vuint32_t R; + struct { + vuint32_t UTE:1; /* User Test Enable */ + vuint32_t SBCE:1; /* Single Bit Correction Enable */ + vuint32_t:6; + vuint32_t DSI:8; /* Data Syndrome Input */ + vuint32_t:10; + vuint32_t MRE:1; /* Margin Read Enable */ + vuint32_t MRV:1; /* Margin Read Value */ + vuint32_t EIE:1; /* ECC Data Input Enable */ + vuint32_t AIS:1; /* Array Integrity Sequence */ + vuint32_t AIE:1; /* Array Integrity Enable */ + vuint32_t AID:1; /* Array Integrity Done */ + } B; + } CFLASH_UT0_32B_tag; + + typedef union { /* UT1 - User Test Register */ + vuint32_t R; + } CFLASH_UT1_32B_tag; + + typedef union { /* UT2 - User Test Register */ + vuint32_t R; + } CFLASH_UT2_32B_tag; + + + /* Register layout for all registers UM... */ + + typedef union { /* UM - User Multiple Input Signature Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + vuint32_t MISR:32; /* Multiple Input Signature */ +#else + vuint32_t MS:32; /* deprecated - please avoid */ +#endif + } B; + } CFLASH_UM_32B_tag; + + + /* Register layout for generated register(s) UT... */ + + typedef union { /* */ + vuint32_t R; + } CFLASH_UT_32B_tag; + + + /* Register layout for generated register(s) PFCR... */ + + typedef union { /* */ + vuint32_t R; + } CFLASH_PFCR_32B_tag; + + + + typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */ + /* MCR - Module Configuration Register */ + CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* LML - Low/Mid Address Space Block Locking Register */ + CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */ + /* HBL - High Address Space Block Locking Register */ + CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */ + /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */ + /* LMS - Low/Mid Address Space Block Select Register */ + CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */ + /* HBS - High Address Space Block Select Register */ + CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */ + /* ADR - Address Register */ + CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */ + union { + struct { + /* */ + CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */ + int8_t CFLASH_reserved_0024_E0[12]; + }; + + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */ + + struct { + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */ + CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */ + CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */ + CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */ + CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */ + }; + + struct { + int8_t CFLASH_reserved_001C_I3[8]; + CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */ + int8_t CFLASH_reserved_0028_E3[8]; + }; + + struct { + /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */ + /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */ + /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */ + int8_t CFLASH_reserved_0028_E4[8]; + }; + + }; + int8_t CFLASH_reserved_0030_C[12]; + union { + CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */ + + struct { + /* UT0 - User Test Register */ + CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */ + /* UT1 - User Test Register */ + CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */ + /* UT2 - User Test Register */ + CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */ + }; + + }; + union { + CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */ + + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */ + + struct { + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */ + CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */ + CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */ + CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */ + CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */ + }; + + }; + } CFLASH_tag; + + +#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL) + + + +/****************************************************************/ +/* */ +/* Module: SIUL */ +/* */ +/****************************************************************/ + + typedef union { /* MIDR1 - MCU ID Register #1 */ + vuint32_t R; + struct { + vuint32_t PARTNUM:16; /* MCU Part Number */ + vuint32_t CSP:1; /* CSP Package */ + vuint32_t PKG:5; /* Package Settings */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_SIUL + vuint32_t MAJOR_MASK:4; /* Major Mask Revision */ +#else + vuint32_t MAJORMASK:4; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SIUL + vuint32_t MINOR_MASK:4; /* Minor Mask Revision */ +#else + vuint32_t MINORMASK:4; /* deprecated name - please avoid */ +#endif + } B; + } SIUL_MIDR1_32B_tag; + + typedef union { /* MIDR2 - MCU ID Register #2 */ + vuint32_t R; + struct { + vuint32_t SF:1; /* Manufacturer */ + vuint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */ + vuint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */ + vuint32_t:7; +#ifndef USE_FIELD_ALIASES_SIUL + vuint32_t PARTNUM2:8; /* MCU Part Number */ +#else + vuint32_t PARTNUM:8; /* deprecated name - please avoid */ +#endif + vuint32_t TBD:1; /* Optional Bit */ + vuint32_t:2; + vuint32_t EE:1; /* Data Flash Present */ + vuint32_t:3; + vuint32_t FR:1; /* Flexray Present */ + } B; + } SIUL_MIDR2_32B_tag; + + typedef union { /* ISR - Interrupt Status Flag Register */ + vuint32_t R; + struct { + vuint32_t EIF31:1; /* External Interrupt Status Flag */ + vuint32_t EIF30:1; /* External Interrupt Status Flag */ + vuint32_t EIF29:1; /* External Interrupt Status Flag */ + vuint32_t EIF28:1; /* External Interrupt Status Flag */ + vuint32_t EIF27:1; /* External Interrupt Status Flag */ + vuint32_t EIF26:1; /* External Interrupt Status Flag */ + vuint32_t EIF25:1; /* External Interrupt Status Flag */ + vuint32_t EIF24:1; /* External Interrupt Status Flag */ + vuint32_t EIF23:1; /* External Interrupt Status Flag */ + vuint32_t EIF22:1; /* External Interrupt Status Flag */ + vuint32_t EIF21:1; /* External Interrupt Status Flag */ + vuint32_t EIF20:1; /* External Interrupt Status Flag */ + vuint32_t EIF19:1; /* External Interrupt Status Flag */ + vuint32_t EIF18:1; /* External Interrupt Status Flag */ + vuint32_t EIF17:1; /* External Interrupt Status Flag */ + vuint32_t EIF16:1; /* External Interrupt Status Flag */ + vuint32_t EIF15:1; /* External Interrupt Status Flag */ + vuint32_t EIF14:1; /* External Interrupt Status Flag */ + vuint32_t EIF13:1; /* External Interrupt Status Flag */ + vuint32_t EIF12:1; /* External Interrupt Status Flag */ + vuint32_t EIF11:1; /* External Interrupt Status Flag */ + vuint32_t EIF10:1; /* External Interrupt Status Flag */ + vuint32_t EIF9:1; /* External Interrupt Status Flag */ + vuint32_t EIF8:1; /* External Interrupt Status Flag */ + vuint32_t EIF7:1; /* External Interrupt Status Flag */ + vuint32_t EIF6:1; /* External Interrupt Status Flag */ + vuint32_t EIF5:1; /* External Interrupt Status Flag */ + vuint32_t EIF4:1; /* External Interrupt Status Flag */ + vuint32_t EIF3:1; /* External Interrupt Status Flag */ + vuint32_t EIF2:1; /* External Interrupt Status Flag */ + vuint32_t EIF1:1; /* External Interrupt Status Flag */ + vuint32_t EIF0:1; /* External Interrupt Status Flag */ + } B; + } SIUL_ISR_32B_tag; + + typedef union { /* IRER - Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t EIRE31:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE30:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE29:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE28:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE27:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE26:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE25:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE24:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE23:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE22:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE21:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE20:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE19:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE18:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE17:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE16:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE15:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE14:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE13:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE12:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE11:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE10:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE9:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE8:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE7:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE6:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE5:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE4:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE3:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE2:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE1:1; /* Enable External Interrupt Requests */ + vuint32_t EIRE0:1; /* Enable External Interrupt Requests */ + } B; + } SIUL_IRER_32B_tag; + + typedef union { /* IREER - Interrupt Rising Edge Event Enable */ + vuint32_t R; + struct { + vuint32_t IREE31:1; /* Enable rising-edge events */ + vuint32_t IREE30:1; /* Enable rising-edge events */ + vuint32_t IREE29:1; /* Enable rising-edge events */ + vuint32_t IREE28:1; /* Enable rising-edge events */ + vuint32_t IREE27:1; /* Enable rising-edge events */ + vuint32_t IREE26:1; /* Enable rising-edge events */ + vuint32_t IREE25:1; /* Enable rising-edge events */ + vuint32_t IREE24:1; /* Enable rising-edge events */ + vuint32_t IREE23:1; /* Enable rising-edge events */ + vuint32_t IREE22:1; /* Enable rising-edge events */ + vuint32_t IREE21:1; /* Enable rising-edge events */ + vuint32_t IREE20:1; /* Enable rising-edge events */ + vuint32_t IREE19:1; /* Enable rising-edge events */ + vuint32_t IREE18:1; /* Enable rising-edge events */ + vuint32_t IREE17:1; /* Enable rising-edge events */ + vuint32_t IREE16:1; /* Enable rising-edge events */ + vuint32_t IREE15:1; /* Enable rising-edge events */ + vuint32_t IREE14:1; /* Enable rising-edge events */ + vuint32_t IREE13:1; /* Enable rising-edge events */ + vuint32_t IREE12:1; /* Enable rising-edge events */ + vuint32_t IREE11:1; /* Enable rising-edge events */ + vuint32_t IREE10:1; /* Enable rising-edge events */ + vuint32_t IREE9:1; /* Enable rising-edge events */ + vuint32_t IREE8:1; /* Enable rising-edge events */ + vuint32_t IREE7:1; /* Enable rising-edge events */ + vuint32_t IREE6:1; /* Enable rising-edge events */ + vuint32_t IREE5:1; /* Enable rising-edge events */ + vuint32_t IREE4:1; /* Enable rising-edge events */ + vuint32_t IREE3:1; /* Enable rising-edge events */ + vuint32_t IREE2:1; /* Enable rising-edge events */ + vuint32_t IREE1:1; /* Enable rising-edge events */ + vuint32_t IREE0:1; /* Enable rising-edge events */ + } B; + } SIUL_IREER_32B_tag; + + typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */ + vuint32_t R; + struct { + vuint32_t IFEE31:1; /* Enable Falling Edge Events */ + vuint32_t IFEE30:1; /* Enable Falling Edge Events */ + vuint32_t IFEE29:1; /* Enable Falling Edge Events */ + vuint32_t IFEE28:1; /* Enable Falling Edge Events */ + vuint32_t IFEE27:1; /* Enable Falling Edge Events */ + vuint32_t IFEE26:1; /* Enable Falling Edge Events */ + vuint32_t IFEE25:1; /* Enable Falling Edge Events */ + vuint32_t IFEE24:1; /* Enable Falling Edge Events */ + vuint32_t IFEE23:1; /* Enable Falling Edge Events */ + vuint32_t IFEE22:1; /* Enable Falling Edge Events */ + vuint32_t IFEE21:1; /* Enable Falling Edge Events */ + vuint32_t IFEE20:1; /* Enable Falling Edge Events */ + vuint32_t IFEE19:1; /* Enable Falling Edge Events */ + vuint32_t IFEE18:1; /* Enable Falling Edge Events */ + vuint32_t IFEE17:1; /* Enable Falling Edge Events */ + vuint32_t IFEE16:1; /* Enable Falling Edge Events */ + vuint32_t IFEE15:1; /* Enable Falling Edge Events */ + vuint32_t IFEE14:1; /* Enable Falling Edge Events */ + vuint32_t IFEE13:1; /* Enable Falling Edge Events */ + vuint32_t IFEE12:1; /* Enable Falling Edge Events */ + vuint32_t IFEE11:1; /* Enable Falling Edge Events */ + vuint32_t IFEE10:1; /* Enable Falling Edge Events */ + vuint32_t IFEE9:1; /* Enable Falling Edge Events */ + vuint32_t IFEE8:1; /* Enable Falling Edge Events */ + vuint32_t IFEE7:1; /* Enable Falling Edge Events */ + vuint32_t IFEE6:1; /* Enable Falling Edge Events */ + vuint32_t IFEE5:1; /* Enable Falling Edge Events */ + vuint32_t IFEE4:1; /* Enable Falling Edge Events */ + vuint32_t IFEE3:1; /* Enable Falling Edge Events */ + vuint32_t IFEE2:1; /* Enable Falling Edge Events */ + vuint32_t IFEE1:1; /* Enable Falling Edge Events */ + vuint32_t IFEE0:1; /* Enable Falling Edge Events */ + } B; + } SIUL_IFEER_32B_tag; + + typedef union { /* IFER Interrupt Filter Enable Register */ + vuint32_t R; + struct { + vuint32_t IFE31:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE30:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE29:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE28:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE27:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE26:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE25:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE24:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE23:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE22:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE21:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE20:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE19:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE18:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE17:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE16:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE15:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE14:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE13:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE12:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE11:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE10:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE9:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE8:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE7:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE6:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE5:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE4:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE3:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE2:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE1:1; /* Enable Digital Glitch Filter */ + vuint32_t IFE0:1; /* Enable Digital Glitch Filter */ + } B; + } SIUL_IFER_32B_tag; + + + /* Register layout for all registers PCR... */ + + typedef union { /* PCR - Pad Configuration Register */ + vuint16_t R; + struct { + vuint16_t:1; +#ifndef USE_FIELD_ALIASES_SIUL + vuint16_t SMC:1; /* Safe Mode Control */ +#else + vuint16_t SME:1; /* deprecated name - please avoid */ +#endif + vuint16_t APC:1; /* Analog Pad Control */ + vuint16_t:1; + vuint16_t PA:2; /* Pad Output Assignment */ + vuint16_t OBE:1; /* Output Buffer Enable */ + vuint16_t IBE:1; /* Input Buffer Enable */ +#ifndef USE_FIELD_ALIASES_SIUL + vuint16_t DSC:2; /* Drive Strength Control */ +#else + vuint16_t DCS:2; /* deprecated name - please avoid */ +#endif + vuint16_t ODE:1; /* Open Drain Output Enable */ + vuint16_t HYS:1; /* Input Hysteresis */ + vuint16_t SRC:2; /* Slew Rate Control */ + vuint16_t WPE:1; /* Weak Pull Up/Down Enable */ + vuint16_t WPS:1; /* Weak Pull Up/Down Select */ + } B; + } SIUL_PCR_16B_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t PADSEL:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_8B_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t PADSEL0:4; /* Pad selection for pin */ + vuint32_t:4; + vuint32_t PADSEL1:4; /* Pad selection for pin */ + vuint32_t:4; + vuint32_t PADSEL2:4; /* Pad selection for pin */ + vuint32_t:4; + vuint32_t PADSEL3:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_32B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDO:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_8B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t PDO0:1; /* Pad Data Out */ + vuint32_t:7; + vuint32_t PDO1:1; /* Pad Data Out */ + vuint32_t:7; + vuint32_t PDO2:1; /* Pad Data Out */ + vuint32_t:7; + vuint32_t PDO3:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_32B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + vuint8_t R; + struct { + vuint8_t:7; + vuint8_t PDI:1; /* Pad Data In */ + } B; + } SIUL_GPDI_8B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t PDI0:1; /* Pad Data In */ + vuint32_t:7; + vuint32_t PDI1:1; /* Pad Data In */ + vuint32_t:7; + vuint32_t PDI2:1; /* Pad Data In */ + vuint32_t:7; + vuint32_t PDI3:1; /* Pad Data In */ + } B; + } SIUL_GPDI_32B_tag; + + + /* Register layout for all registers PGPDO... */ + + typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */ + vuint16_t R; + } SIUL_PGPDO_16B_tag; + + + /* Register layout for all registers PGPDI... */ + + typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */ + vuint16_t R; + } SIUL_PGPDI_16B_tag; + + + /* Register layout for all registers MPGPDO... */ + + typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + vuint32_t R; + struct { + vuint32_t MASK:16; /* Mask Field */ + vuint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ + } B; + } SIUL_MPGPDO_32B_tag; + + + /* Register layout for all registers IFMC... */ + + typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */ + } B; + } SIUL_IFMC_32B_tag; + + typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */ + } B; + } SIUL_IFCPR_32B_tag; + + + + typedef struct SIUL_struct_tag { /* start of SIUL_tag */ + int8_t SIUL_reserved_0000_C[4]; + union { + SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */ + + /* MIDR1 - MCU ID Register #1 */ + SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */ + + }; + /* MIDR2 - MCU ID Register #2 */ + SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */ + int8_t SIUL_reserved_000C[8]; + /* ISR - Interrupt Status Flag Register */ + SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */ + /* IRER - Interrupt Request Enable Register */ + SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + int8_t SIUL_reserved_001C[12]; + /* IREER - Interrupt Rising Edge Event Enable */ + SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */ + /* IFEER - Interrupt Falling-Edge Event Enable */ + SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */ + /* IFER Interrupt Filter Enable Register */ + SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */ + int8_t SIUL_reserved_0034_C[12]; + union { + /* PCR - Pad Configuration Register */ + SIUL_PCR_16B_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */ + + struct { + /* PCR - Pad Configuration Register */ + SIUL_PCR_16B_tag PCR0; /* offset: 0x0040 size: 16 bit */ + SIUL_PCR_16B_tag PCR1; /* offset: 0x0042 size: 16 bit */ + SIUL_PCR_16B_tag PCR2; /* offset: 0x0044 size: 16 bit */ + SIUL_PCR_16B_tag PCR3; /* offset: 0x0046 size: 16 bit */ + SIUL_PCR_16B_tag PCR4; /* offset: 0x0048 size: 16 bit */ + SIUL_PCR_16B_tag PCR5; /* offset: 0x004A size: 16 bit */ + SIUL_PCR_16B_tag PCR6; /* offset: 0x004C size: 16 bit */ + SIUL_PCR_16B_tag PCR7; /* offset: 0x004E size: 16 bit */ + SIUL_PCR_16B_tag PCR8; /* offset: 0x0050 size: 16 bit */ + SIUL_PCR_16B_tag PCR9; /* offset: 0x0052 size: 16 bit */ + SIUL_PCR_16B_tag PCR10; /* offset: 0x0054 size: 16 bit */ + SIUL_PCR_16B_tag PCR11; /* offset: 0x0056 size: 16 bit */ + SIUL_PCR_16B_tag PCR12; /* offset: 0x0058 size: 16 bit */ + SIUL_PCR_16B_tag PCR13; /* offset: 0x005A size: 16 bit */ + SIUL_PCR_16B_tag PCR14; /* offset: 0x005C size: 16 bit */ + SIUL_PCR_16B_tag PCR15; /* offset: 0x005E size: 16 bit */ + SIUL_PCR_16B_tag PCR16; /* offset: 0x0060 size: 16 bit */ + SIUL_PCR_16B_tag PCR17; /* offset: 0x0062 size: 16 bit */ + SIUL_PCR_16B_tag PCR18; /* offset: 0x0064 size: 16 bit */ + SIUL_PCR_16B_tag PCR19; /* offset: 0x0066 size: 16 bit */ + SIUL_PCR_16B_tag PCR20; /* offset: 0x0068 size: 16 bit */ + SIUL_PCR_16B_tag PCR21; /* offset: 0x006A size: 16 bit */ + SIUL_PCR_16B_tag PCR22; /* offset: 0x006C size: 16 bit */ + SIUL_PCR_16B_tag PCR23; /* offset: 0x006E size: 16 bit */ + SIUL_PCR_16B_tag PCR24; /* offset: 0x0070 size: 16 bit */ + SIUL_PCR_16B_tag PCR25; /* offset: 0x0072 size: 16 bit */ + SIUL_PCR_16B_tag PCR26; /* offset: 0x0074 size: 16 bit */ + SIUL_PCR_16B_tag PCR27; /* offset: 0x0076 size: 16 bit */ + SIUL_PCR_16B_tag PCR28; /* offset: 0x0078 size: 16 bit */ + SIUL_PCR_16B_tag PCR29; /* offset: 0x007A size: 16 bit */ + SIUL_PCR_16B_tag PCR30; /* offset: 0x007C size: 16 bit */ + SIUL_PCR_16B_tag PCR31; /* offset: 0x007E size: 16 bit */ + SIUL_PCR_16B_tag PCR32; /* offset: 0x0080 size: 16 bit */ + SIUL_PCR_16B_tag PCR33; /* offset: 0x0082 size: 16 bit */ + SIUL_PCR_16B_tag PCR34; /* offset: 0x0084 size: 16 bit */ + SIUL_PCR_16B_tag PCR35; /* offset: 0x0086 size: 16 bit */ + SIUL_PCR_16B_tag PCR36; /* offset: 0x0088 size: 16 bit */ + SIUL_PCR_16B_tag PCR37; /* offset: 0x008A size: 16 bit */ + SIUL_PCR_16B_tag PCR38; /* offset: 0x008C size: 16 bit */ + SIUL_PCR_16B_tag PCR39; /* offset: 0x008E size: 16 bit */ + SIUL_PCR_16B_tag PCR40; /* offset: 0x0090 size: 16 bit */ + SIUL_PCR_16B_tag PCR41; /* offset: 0x0092 size: 16 bit */ + SIUL_PCR_16B_tag PCR42; /* offset: 0x0094 size: 16 bit */ + SIUL_PCR_16B_tag PCR43; /* offset: 0x0096 size: 16 bit */ + SIUL_PCR_16B_tag PCR44; /* offset: 0x0098 size: 16 bit */ + SIUL_PCR_16B_tag PCR45; /* offset: 0x009A size: 16 bit */ + SIUL_PCR_16B_tag PCR46; /* offset: 0x009C size: 16 bit */ + SIUL_PCR_16B_tag PCR47; /* offset: 0x009E size: 16 bit */ + SIUL_PCR_16B_tag PCR48; /* offset: 0x00A0 size: 16 bit */ + SIUL_PCR_16B_tag PCR49; /* offset: 0x00A2 size: 16 bit */ + SIUL_PCR_16B_tag PCR50; /* offset: 0x00A4 size: 16 bit */ + SIUL_PCR_16B_tag PCR51; /* offset: 0x00A6 size: 16 bit */ + SIUL_PCR_16B_tag PCR52; /* offset: 0x00A8 size: 16 bit */ + SIUL_PCR_16B_tag PCR53; /* offset: 0x00AA size: 16 bit */ + SIUL_PCR_16B_tag PCR54; /* offset: 0x00AC size: 16 bit */ + SIUL_PCR_16B_tag PCR55; /* offset: 0x00AE size: 16 bit */ + SIUL_PCR_16B_tag PCR56; /* offset: 0x00B0 size: 16 bit */ + SIUL_PCR_16B_tag PCR57; /* offset: 0x00B2 size: 16 bit */ + SIUL_PCR_16B_tag PCR58; /* offset: 0x00B4 size: 16 bit */ + SIUL_PCR_16B_tag PCR59; /* offset: 0x00B6 size: 16 bit */ + SIUL_PCR_16B_tag PCR60; /* offset: 0x00B8 size: 16 bit */ + SIUL_PCR_16B_tag PCR61; /* offset: 0x00BA size: 16 bit */ + SIUL_PCR_16B_tag PCR62; /* offset: 0x00BC size: 16 bit */ + SIUL_PCR_16B_tag PCR63; /* offset: 0x00BE size: 16 bit */ + SIUL_PCR_16B_tag PCR64; /* offset: 0x00C0 size: 16 bit */ + SIUL_PCR_16B_tag PCR65; /* offset: 0x00C2 size: 16 bit */ + SIUL_PCR_16B_tag PCR66; /* offset: 0x00C4 size: 16 bit */ + SIUL_PCR_16B_tag PCR67; /* offset: 0x00C6 size: 16 bit */ + SIUL_PCR_16B_tag PCR68; /* offset: 0x00C8 size: 16 bit */ + SIUL_PCR_16B_tag PCR69; /* offset: 0x00CA size: 16 bit */ + SIUL_PCR_16B_tag PCR70; /* offset: 0x00CC size: 16 bit */ + SIUL_PCR_16B_tag PCR71; /* offset: 0x00CE size: 16 bit */ + SIUL_PCR_16B_tag PCR72; /* offset: 0x00D0 size: 16 bit */ + SIUL_PCR_16B_tag PCR73; /* offset: 0x00D2 size: 16 bit */ + SIUL_PCR_16B_tag PCR74; /* offset: 0x00D4 size: 16 bit */ + SIUL_PCR_16B_tag PCR75; /* offset: 0x00D6 size: 16 bit */ + SIUL_PCR_16B_tag PCR76; /* offset: 0x00D8 size: 16 bit */ + SIUL_PCR_16B_tag PCR77; /* offset: 0x00DA size: 16 bit */ + SIUL_PCR_16B_tag PCR78; /* offset: 0x00DC size: 16 bit */ + SIUL_PCR_16B_tag PCR79; /* offset: 0x00DE size: 16 bit */ + SIUL_PCR_16B_tag PCR80; /* offset: 0x00E0 size: 16 bit */ + SIUL_PCR_16B_tag PCR81; /* offset: 0x00E2 size: 16 bit */ + SIUL_PCR_16B_tag PCR82; /* offset: 0x00E4 size: 16 bit */ + SIUL_PCR_16B_tag PCR83; /* offset: 0x00E6 size: 16 bit */ + SIUL_PCR_16B_tag PCR84; /* offset: 0x00E8 size: 16 bit */ + SIUL_PCR_16B_tag PCR85; /* offset: 0x00EA size: 16 bit */ + SIUL_PCR_16B_tag PCR86; /* offset: 0x00EC size: 16 bit */ + SIUL_PCR_16B_tag PCR87; /* offset: 0x00EE size: 16 bit */ + SIUL_PCR_16B_tag PCR88; /* offset: 0x00F0 size: 16 bit */ + SIUL_PCR_16B_tag PCR89; /* offset: 0x00F2 size: 16 bit */ + SIUL_PCR_16B_tag PCR90; /* offset: 0x00F4 size: 16 bit */ + SIUL_PCR_16B_tag PCR91; /* offset: 0x00F6 size: 16 bit */ + SIUL_PCR_16B_tag PCR92; /* offset: 0x00F8 size: 16 bit */ + SIUL_PCR_16B_tag PCR93; /* offset: 0x00FA size: 16 bit */ + SIUL_PCR_16B_tag PCR94; /* offset: 0x00FC size: 16 bit */ + SIUL_PCR_16B_tag PCR95; /* offset: 0x00FE size: 16 bit */ + SIUL_PCR_16B_tag PCR96; /* offset: 0x0100 size: 16 bit */ + SIUL_PCR_16B_tag PCR97; /* offset: 0x0102 size: 16 bit */ + SIUL_PCR_16B_tag PCR98; /* offset: 0x0104 size: 16 bit */ + SIUL_PCR_16B_tag PCR99; /* offset: 0x0106 size: 16 bit */ + SIUL_PCR_16B_tag PCR100; /* offset: 0x0108 size: 16 bit */ + SIUL_PCR_16B_tag PCR101; /* offset: 0x010A size: 16 bit */ + SIUL_PCR_16B_tag PCR102; /* offset: 0x010C size: 16 bit */ + SIUL_PCR_16B_tag PCR103; /* offset: 0x010E size: 16 bit */ + SIUL_PCR_16B_tag PCR104; /* offset: 0x0110 size: 16 bit */ + SIUL_PCR_16B_tag PCR105; /* offset: 0x0112 size: 16 bit */ + SIUL_PCR_16B_tag PCR106; /* offset: 0x0114 size: 16 bit */ + SIUL_PCR_16B_tag PCR107; /* offset: 0x0116 size: 16 bit */ + SIUL_PCR_16B_tag PCR108; /* offset: 0x0118 size: 16 bit */ + SIUL_PCR_16B_tag PCR109; /* offset: 0x011A size: 16 bit */ + SIUL_PCR_16B_tag PCR110; /* offset: 0x011C size: 16 bit */ + SIUL_PCR_16B_tag PCR111; /* offset: 0x011E size: 16 bit */ + SIUL_PCR_16B_tag PCR112; /* offset: 0x0120 size: 16 bit */ + SIUL_PCR_16B_tag PCR113; /* offset: 0x0122 size: 16 bit */ + SIUL_PCR_16B_tag PCR114; /* offset: 0x0124 size: 16 bit */ + SIUL_PCR_16B_tag PCR115; /* offset: 0x0126 size: 16 bit */ + SIUL_PCR_16B_tag PCR116; /* offset: 0x0128 size: 16 bit */ + SIUL_PCR_16B_tag PCR117; /* offset: 0x012A size: 16 bit */ + SIUL_PCR_16B_tag PCR118; /* offset: 0x012C size: 16 bit */ + SIUL_PCR_16B_tag PCR119; /* offset: 0x012E size: 16 bit */ + SIUL_PCR_16B_tag PCR120; /* offset: 0x0130 size: 16 bit */ + SIUL_PCR_16B_tag PCR121; /* offset: 0x0132 size: 16 bit */ + SIUL_PCR_16B_tag PCR122; /* offset: 0x0134 size: 16 bit */ + SIUL_PCR_16B_tag PCR123; /* offset: 0x0136 size: 16 bit */ + SIUL_PCR_16B_tag PCR124; /* offset: 0x0138 size: 16 bit */ + SIUL_PCR_16B_tag PCR125; /* offset: 0x013A size: 16 bit */ + SIUL_PCR_16B_tag PCR126; /* offset: 0x013C size: 16 bit */ + SIUL_PCR_16B_tag PCR127; /* offset: 0x013E size: 16 bit */ + SIUL_PCR_16B_tag PCR128; /* offset: 0x0140 size: 16 bit */ + SIUL_PCR_16B_tag PCR129; /* offset: 0x0142 size: 16 bit */ + SIUL_PCR_16B_tag PCR130; /* offset: 0x0144 size: 16 bit */ + SIUL_PCR_16B_tag PCR131; /* offset: 0x0146 size: 16 bit */ + SIUL_PCR_16B_tag PCR132; /* offset: 0x0148 size: 16 bit */ + SIUL_PCR_16B_tag PCR133; /* offset: 0x014A size: 16 bit */ + SIUL_PCR_16B_tag PCR134; /* offset: 0x014C size: 16 bit */ + SIUL_PCR_16B_tag PCR135; /* offset: 0x014E size: 16 bit */ + SIUL_PCR_16B_tag PCR136; /* offset: 0x0150 size: 16 bit */ + SIUL_PCR_16B_tag PCR137; /* offset: 0x0152 size: 16 bit */ + SIUL_PCR_16B_tag PCR138; /* offset: 0x0154 size: 16 bit */ + SIUL_PCR_16B_tag PCR139; /* offset: 0x0156 size: 16 bit */ + SIUL_PCR_16B_tag PCR140; /* offset: 0x0158 size: 16 bit */ + SIUL_PCR_16B_tag PCR141; /* offset: 0x015A size: 16 bit */ + SIUL_PCR_16B_tag PCR142; /* offset: 0x015C size: 16 bit */ + SIUL_PCR_16B_tag PCR143; /* offset: 0x015E size: 16 bit */ + SIUL_PCR_16B_tag PCR144; /* offset: 0x0160 size: 16 bit */ + SIUL_PCR_16B_tag PCR145; /* offset: 0x0162 size: 16 bit */ + SIUL_PCR_16B_tag PCR146; /* offset: 0x0164 size: 16 bit */ + SIUL_PCR_16B_tag PCR147; /* offset: 0x0166 size: 16 bit */ + SIUL_PCR_16B_tag PCR148; /* offset: 0x0168 size: 16 bit */ + SIUL_PCR_16B_tag PCR149; /* offset: 0x016A size: 16 bit */ + SIUL_PCR_16B_tag PCR150; /* offset: 0x016C size: 16 bit */ + SIUL_PCR_16B_tag PCR151; /* offset: 0x016E size: 16 bit */ + SIUL_PCR_16B_tag PCR152; /* offset: 0x0170 size: 16 bit */ + SIUL_PCR_16B_tag PCR153; /* offset: 0x0172 size: 16 bit */ + SIUL_PCR_16B_tag PCR154; /* offset: 0x0174 size: 16 bit */ + SIUL_PCR_16B_tag PCR155; /* offset: 0x0176 size: 16 bit */ + SIUL_PCR_16B_tag PCR156; /* offset: 0x0178 size: 16 bit */ + SIUL_PCR_16B_tag PCR157; /* offset: 0x017A size: 16 bit */ + SIUL_PCR_16B_tag PCR158; /* offset: 0x017C size: 16 bit */ + SIUL_PCR_16B_tag PCR159; /* offset: 0x017E size: 16 bit */ + SIUL_PCR_16B_tag PCR160; /* offset: 0x0180 size: 16 bit */ + SIUL_PCR_16B_tag PCR161; /* offset: 0x0182 size: 16 bit */ + SIUL_PCR_16B_tag PCR162; /* offset: 0x0184 size: 16 bit */ + SIUL_PCR_16B_tag PCR163; /* offset: 0x0186 size: 16 bit */ + SIUL_PCR_16B_tag PCR164; /* offset: 0x0188 size: 16 bit */ + SIUL_PCR_16B_tag PCR165; /* offset: 0x018A size: 16 bit */ + SIUL_PCR_16B_tag PCR166; /* offset: 0x018C size: 16 bit */ + SIUL_PCR_16B_tag PCR167; /* offset: 0x018E size: 16 bit */ + SIUL_PCR_16B_tag PCR168; /* offset: 0x0190 size: 16 bit */ + SIUL_PCR_16B_tag PCR169; /* offset: 0x0192 size: 16 bit */ + SIUL_PCR_16B_tag PCR170; /* offset: 0x0194 size: 16 bit */ + SIUL_PCR_16B_tag PCR171; /* offset: 0x0196 size: 16 bit */ + SIUL_PCR_16B_tag PCR172; /* offset: 0x0198 size: 16 bit */ + SIUL_PCR_16B_tag PCR173; /* offset: 0x019A size: 16 bit */ + SIUL_PCR_16B_tag PCR174; /* offset: 0x019C size: 16 bit */ + SIUL_PCR_16B_tag PCR175; /* offset: 0x019E size: 16 bit */ + SIUL_PCR_16B_tag PCR176; /* offset: 0x01A0 size: 16 bit */ + SIUL_PCR_16B_tag PCR177; /* offset: 0x01A2 size: 16 bit */ + SIUL_PCR_16B_tag PCR178; /* offset: 0x01A4 size: 16 bit */ + SIUL_PCR_16B_tag PCR179; /* offset: 0x01A6 size: 16 bit */ + SIUL_PCR_16B_tag PCR180; /* offset: 0x01A8 size: 16 bit */ + SIUL_PCR_16B_tag PCR181; /* offset: 0x01AA size: 16 bit */ + SIUL_PCR_16B_tag PCR182; /* offset: 0x01AC size: 16 bit */ + SIUL_PCR_16B_tag PCR183; /* offset: 0x01AE size: 16 bit */ + SIUL_PCR_16B_tag PCR184; /* offset: 0x01B0 size: 16 bit */ + SIUL_PCR_16B_tag PCR185; /* offset: 0x01B2 size: 16 bit */ + SIUL_PCR_16B_tag PCR186; /* offset: 0x01B4 size: 16 bit */ + SIUL_PCR_16B_tag PCR187; /* offset: 0x01B6 size: 16 bit */ + SIUL_PCR_16B_tag PCR188; /* offset: 0x01B8 size: 16 bit */ + SIUL_PCR_16B_tag PCR189; /* offset: 0x01BA size: 16 bit */ + SIUL_PCR_16B_tag PCR190; /* offset: 0x01BC size: 16 bit */ + SIUL_PCR_16B_tag PCR191; /* offset: 0x01BE size: 16 bit */ + SIUL_PCR_16B_tag PCR192; /* offset: 0x01C0 size: 16 bit */ + SIUL_PCR_16B_tag PCR193; /* offset: 0x01C2 size: 16 bit */ + SIUL_PCR_16B_tag PCR194; /* offset: 0x01C4 size: 16 bit */ + SIUL_PCR_16B_tag PCR195; /* offset: 0x01C6 size: 16 bit */ + SIUL_PCR_16B_tag PCR196; /* offset: 0x01C8 size: 16 bit */ + SIUL_PCR_16B_tag PCR197; /* offset: 0x01CA size: 16 bit */ + SIUL_PCR_16B_tag PCR198; /* offset: 0x01CC size: 16 bit */ + SIUL_PCR_16B_tag PCR199; /* offset: 0x01CE size: 16 bit */ + SIUL_PCR_16B_tag PCR200; /* offset: 0x01D0 size: 16 bit */ + SIUL_PCR_16B_tag PCR201; /* offset: 0x01D2 size: 16 bit */ + SIUL_PCR_16B_tag PCR202; /* offset: 0x01D4 size: 16 bit */ + SIUL_PCR_16B_tag PCR203; /* offset: 0x01D6 size: 16 bit */ + SIUL_PCR_16B_tag PCR204; /* offset: 0x01D8 size: 16 bit */ + SIUL_PCR_16B_tag PCR205; /* offset: 0x01DA size: 16 bit */ + SIUL_PCR_16B_tag PCR206; /* offset: 0x01DC size: 16 bit */ + SIUL_PCR_16B_tag PCR207; /* offset: 0x01DE size: 16 bit */ + SIUL_PCR_16B_tag PCR208; /* offset: 0x01E0 size: 16 bit */ + SIUL_PCR_16B_tag PCR209; /* offset: 0x01E2 size: 16 bit */ + SIUL_PCR_16B_tag PCR210; /* offset: 0x01E4 size: 16 bit */ + SIUL_PCR_16B_tag PCR211; /* offset: 0x01E6 size: 16 bit */ + SIUL_PCR_16B_tag PCR212; /* offset: 0x01E8 size: 16 bit */ + SIUL_PCR_16B_tag PCR213; /* offset: 0x01EA size: 16 bit */ + SIUL_PCR_16B_tag PCR214; /* offset: 0x01EC size: 16 bit */ + SIUL_PCR_16B_tag PCR215; /* offset: 0x01EE size: 16 bit */ + SIUL_PCR_16B_tag PCR216; /* offset: 0x01F0 size: 16 bit */ + SIUL_PCR_16B_tag PCR217; /* offset: 0x01F2 size: 16 bit */ + SIUL_PCR_16B_tag PCR218; /* offset: 0x01F4 size: 16 bit */ + SIUL_PCR_16B_tag PCR219; /* offset: 0x01F6 size: 16 bit */ + SIUL_PCR_16B_tag PCR220; /* offset: 0x01F8 size: 16 bit */ + SIUL_PCR_16B_tag PCR221; /* offset: 0x01FA size: 16 bit */ + SIUL_PCR_16B_tag PCR222; /* offset: 0x01FC size: 16 bit */ + SIUL_PCR_16B_tag PCR223; /* offset: 0x01FE size: 16 bit */ + SIUL_PCR_16B_tag PCR224; /* offset: 0x0200 size: 16 bit */ + SIUL_PCR_16B_tag PCR225; /* offset: 0x0202 size: 16 bit */ + SIUL_PCR_16B_tag PCR226; /* offset: 0x0204 size: 16 bit */ + SIUL_PCR_16B_tag PCR227; /* offset: 0x0206 size: 16 bit */ + SIUL_PCR_16B_tag PCR228; /* offset: 0x0208 size: 16 bit */ + SIUL_PCR_16B_tag PCR229; /* offset: 0x020A size: 16 bit */ + SIUL_PCR_16B_tag PCR230; /* offset: 0x020C size: 16 bit */ + SIUL_PCR_16B_tag PCR231; /* offset: 0x020E size: 16 bit */ + SIUL_PCR_16B_tag PCR232; /* offset: 0x0210 size: 16 bit */ + SIUL_PCR_16B_tag PCR233; /* offset: 0x0212 size: 16 bit */ + SIUL_PCR_16B_tag PCR234; /* offset: 0x0214 size: 16 bit */ + SIUL_PCR_16B_tag PCR235; /* offset: 0x0216 size: 16 bit */ + SIUL_PCR_16B_tag PCR236; /* offset: 0x0218 size: 16 bit */ + SIUL_PCR_16B_tag PCR237; /* offset: 0x021A size: 16 bit */ + SIUL_PCR_16B_tag PCR238; /* offset: 0x021C size: 16 bit */ + SIUL_PCR_16B_tag PCR239; /* offset: 0x021E size: 16 bit */ + SIUL_PCR_16B_tag PCR240; /* offset: 0x0220 size: 16 bit */ + SIUL_PCR_16B_tag PCR241; /* offset: 0x0222 size: 16 bit */ + SIUL_PCR_16B_tag PCR242; /* offset: 0x0224 size: 16 bit */ + SIUL_PCR_16B_tag PCR243; /* offset: 0x0226 size: 16 bit */ + SIUL_PCR_16B_tag PCR244; /* offset: 0x0228 size: 16 bit */ + SIUL_PCR_16B_tag PCR245; /* offset: 0x022A size: 16 bit */ + SIUL_PCR_16B_tag PCR246; /* offset: 0x022C size: 16 bit */ + SIUL_PCR_16B_tag PCR247; /* offset: 0x022E size: 16 bit */ + SIUL_PCR_16B_tag PCR248; /* offset: 0x0230 size: 16 bit */ + SIUL_PCR_16B_tag PCR249; /* offset: 0x0232 size: 16 bit */ + SIUL_PCR_16B_tag PCR250; /* offset: 0x0234 size: 16 bit */ + SIUL_PCR_16B_tag PCR251; /* offset: 0x0236 size: 16 bit */ + SIUL_PCR_16B_tag PCR252; /* offset: 0x0238 size: 16 bit */ + SIUL_PCR_16B_tag PCR253; /* offset: 0x023A size: 16 bit */ + SIUL_PCR_16B_tag PCR254; /* offset: 0x023C size: 16 bit */ + SIUL_PCR_16B_tag PCR255; /* offset: 0x023E size: 16 bit */ + SIUL_PCR_16B_tag PCR256; /* offset: 0x0240 size: 16 bit */ + SIUL_PCR_16B_tag PCR257; /* offset: 0x0242 size: 16 bit */ + SIUL_PCR_16B_tag PCR258; /* offset: 0x0244 size: 16 bit */ + SIUL_PCR_16B_tag PCR259; /* offset: 0x0246 size: 16 bit */ + SIUL_PCR_16B_tag PCR260; /* offset: 0x0248 size: 16 bit */ + SIUL_PCR_16B_tag PCR261; /* offset: 0x024A size: 16 bit */ + SIUL_PCR_16B_tag PCR262; /* offset: 0x024C size: 16 bit */ + SIUL_PCR_16B_tag PCR263; /* offset: 0x024E size: 16 bit */ + SIUL_PCR_16B_tag PCR264; /* offset: 0x0250 size: 16 bit */ + SIUL_PCR_16B_tag PCR265; /* offset: 0x0252 size: 16 bit */ + SIUL_PCR_16B_tag PCR266; /* offset: 0x0254 size: 16 bit */ + SIUL_PCR_16B_tag PCR267; /* offset: 0x0256 size: 16 bit */ + SIUL_PCR_16B_tag PCR268; /* offset: 0x0258 size: 16 bit */ + SIUL_PCR_16B_tag PCR269; /* offset: 0x025A size: 16 bit */ + SIUL_PCR_16B_tag PCR270; /* offset: 0x025C size: 16 bit */ + SIUL_PCR_16B_tag PCR271; /* offset: 0x025E size: 16 bit */ + SIUL_PCR_16B_tag PCR272; /* offset: 0x0260 size: 16 bit */ + SIUL_PCR_16B_tag PCR273; /* offset: 0x0262 size: 16 bit */ + SIUL_PCR_16B_tag PCR274; /* offset: 0x0264 size: 16 bit */ + SIUL_PCR_16B_tag PCR275; /* offset: 0x0266 size: 16 bit */ + SIUL_PCR_16B_tag PCR276; /* offset: 0x0268 size: 16 bit */ + SIUL_PCR_16B_tag PCR277; /* offset: 0x026A size: 16 bit */ + SIUL_PCR_16B_tag PCR278; /* offset: 0x026C size: 16 bit */ + SIUL_PCR_16B_tag PCR279; /* offset: 0x026E size: 16 bit */ + SIUL_PCR_16B_tag PCR280; /* offset: 0x0270 size: 16 bit */ + SIUL_PCR_16B_tag PCR281; /* offset: 0x0272 size: 16 bit */ + SIUL_PCR_16B_tag PCR282; /* offset: 0x0274 size: 16 bit */ + SIUL_PCR_16B_tag PCR283; /* offset: 0x0276 size: 16 bit */ + SIUL_PCR_16B_tag PCR284; /* offset: 0x0278 size: 16 bit */ + SIUL_PCR_16B_tag PCR285; /* offset: 0x027A size: 16 bit */ + SIUL_PCR_16B_tag PCR286; /* offset: 0x027C size: 16 bit */ + SIUL_PCR_16B_tag PCR287; /* offset: 0x027E size: 16 bit */ + SIUL_PCR_16B_tag PCR288; /* offset: 0x0280 size: 16 bit */ + SIUL_PCR_16B_tag PCR289; /* offset: 0x0282 size: 16 bit */ + SIUL_PCR_16B_tag PCR290; /* offset: 0x0284 size: 16 bit */ + SIUL_PCR_16B_tag PCR291; /* offset: 0x0286 size: 16 bit */ + SIUL_PCR_16B_tag PCR292; /* offset: 0x0288 size: 16 bit */ + SIUL_PCR_16B_tag PCR293; /* offset: 0x028A size: 16 bit */ + SIUL_PCR_16B_tag PCR294; /* offset: 0x028C size: 16 bit */ + SIUL_PCR_16B_tag PCR295; /* offset: 0x028E size: 16 bit */ + SIUL_PCR_16B_tag PCR296; /* offset: 0x0290 size: 16 bit */ + SIUL_PCR_16B_tag PCR297; /* offset: 0x0292 size: 16 bit */ + SIUL_PCR_16B_tag PCR298; /* offset: 0x0294 size: 16 bit */ + SIUL_PCR_16B_tag PCR299; /* offset: 0x0296 size: 16 bit */ + SIUL_PCR_16B_tag PCR300; /* offset: 0x0298 size: 16 bit */ + SIUL_PCR_16B_tag PCR301; /* offset: 0x029A size: 16 bit */ + SIUL_PCR_16B_tag PCR302; /* offset: 0x029C size: 16 bit */ + SIUL_PCR_16B_tag PCR303; /* offset: 0x029E size: 16 bit */ + SIUL_PCR_16B_tag PCR304; /* offset: 0x02A0 size: 16 bit */ + SIUL_PCR_16B_tag PCR305; /* offset: 0x02A2 size: 16 bit */ + SIUL_PCR_16B_tag PCR306; /* offset: 0x02A4 size: 16 bit */ + SIUL_PCR_16B_tag PCR307; /* offset: 0x02A6 size: 16 bit */ + SIUL_PCR_16B_tag PCR308; /* offset: 0x02A8 size: 16 bit */ + SIUL_PCR_16B_tag PCR309; /* offset: 0x02AA size: 16 bit */ + SIUL_PCR_16B_tag PCR310; /* offset: 0x02AC size: 16 bit */ + SIUL_PCR_16B_tag PCR311; /* offset: 0x02AE size: 16 bit */ + SIUL_PCR_16B_tag PCR312; /* offset: 0x02B0 size: 16 bit */ + SIUL_PCR_16B_tag PCR313; /* offset: 0x02B2 size: 16 bit */ + SIUL_PCR_16B_tag PCR314; /* offset: 0x02B4 size: 16 bit */ + SIUL_PCR_16B_tag PCR315; /* offset: 0x02B6 size: 16 bit */ + SIUL_PCR_16B_tag PCR316; /* offset: 0x02B8 size: 16 bit */ + SIUL_PCR_16B_tag PCR317; /* offset: 0x02BA size: 16 bit */ + SIUL_PCR_16B_tag PCR318; /* offset: 0x02BC size: 16 bit */ + SIUL_PCR_16B_tag PCR319; /* offset: 0x02BE size: 16 bit */ + SIUL_PCR_16B_tag PCR320; /* offset: 0x02C0 size: 16 bit */ + SIUL_PCR_16B_tag PCR321; /* offset: 0x02C2 size: 16 bit */ + SIUL_PCR_16B_tag PCR322; /* offset: 0x02C4 size: 16 bit */ + SIUL_PCR_16B_tag PCR323; /* offset: 0x02C6 size: 16 bit */ + SIUL_PCR_16B_tag PCR324; /* offset: 0x02C8 size: 16 bit */ + SIUL_PCR_16B_tag PCR325; /* offset: 0x02CA size: 16 bit */ + SIUL_PCR_16B_tag PCR326; /* offset: 0x02CC size: 16 bit */ + SIUL_PCR_16B_tag PCR327; /* offset: 0x02CE size: 16 bit */ + SIUL_PCR_16B_tag PCR328; /* offset: 0x02D0 size: 16 bit */ + SIUL_PCR_16B_tag PCR329; /* offset: 0x02D2 size: 16 bit */ + SIUL_PCR_16B_tag PCR330; /* offset: 0x02D4 size: 16 bit */ + SIUL_PCR_16B_tag PCR331; /* offset: 0x02D6 size: 16 bit */ + SIUL_PCR_16B_tag PCR332; /* offset: 0x02D8 size: 16 bit */ + SIUL_PCR_16B_tag PCR333; /* offset: 0x02DA size: 16 bit */ + SIUL_PCR_16B_tag PCR334; /* offset: 0x02DC size: 16 bit */ + SIUL_PCR_16B_tag PCR335; /* offset: 0x02DE size: 16 bit */ + SIUL_PCR_16B_tag PCR336; /* offset: 0x02E0 size: 16 bit */ + SIUL_PCR_16B_tag PCR337; /* offset: 0x02E2 size: 16 bit */ + SIUL_PCR_16B_tag PCR338; /* offset: 0x02E4 size: 16 bit */ + SIUL_PCR_16B_tag PCR339; /* offset: 0x02E6 size: 16 bit */ + SIUL_PCR_16B_tag PCR340; /* offset: 0x02E8 size: 16 bit */ + SIUL_PCR_16B_tag PCR341; /* offset: 0x02EA size: 16 bit */ + SIUL_PCR_16B_tag PCR342; /* offset: 0x02EC size: 16 bit */ + SIUL_PCR_16B_tag PCR343; /* offset: 0x02EE size: 16 bit */ + SIUL_PCR_16B_tag PCR344; /* offset: 0x02F0 size: 16 bit */ + SIUL_PCR_16B_tag PCR345; /* offset: 0x02F2 size: 16 bit */ + SIUL_PCR_16B_tag PCR346; /* offset: 0x02F4 size: 16 bit */ + SIUL_PCR_16B_tag PCR347; /* offset: 0x02F6 size: 16 bit */ + SIUL_PCR_16B_tag PCR348; /* offset: 0x02F8 size: 16 bit */ + SIUL_PCR_16B_tag PCR349; /* offset: 0x02FA size: 16 bit */ + SIUL_PCR_16B_tag PCR350; /* offset: 0x02FC size: 16 bit */ + SIUL_PCR_16B_tag PCR351; /* offset: 0x02FE size: 16 bit */ + SIUL_PCR_16B_tag PCR352; /* offset: 0x0300 size: 16 bit */ + SIUL_PCR_16B_tag PCR353; /* offset: 0x0302 size: 16 bit */ + SIUL_PCR_16B_tag PCR354; /* offset: 0x0304 size: 16 bit */ + SIUL_PCR_16B_tag PCR355; /* offset: 0x0306 size: 16 bit */ + SIUL_PCR_16B_tag PCR356; /* offset: 0x0308 size: 16 bit */ + SIUL_PCR_16B_tag PCR357; /* offset: 0x030A size: 16 bit */ + SIUL_PCR_16B_tag PCR358; /* offset: 0x030C size: 16 bit */ + SIUL_PCR_16B_tag PCR359; /* offset: 0x030E size: 16 bit */ + SIUL_PCR_16B_tag PCR360; /* offset: 0x0310 size: 16 bit */ + SIUL_PCR_16B_tag PCR361; /* offset: 0x0312 size: 16 bit */ + SIUL_PCR_16B_tag PCR362; /* offset: 0x0314 size: 16 bit */ + SIUL_PCR_16B_tag PCR363; /* offset: 0x0316 size: 16 bit */ + SIUL_PCR_16B_tag PCR364; /* offset: 0x0318 size: 16 bit */ + SIUL_PCR_16B_tag PCR365; /* offset: 0x031A size: 16 bit */ + SIUL_PCR_16B_tag PCR366; /* offset: 0x031C size: 16 bit */ + SIUL_PCR_16B_tag PCR367; /* offset: 0x031E size: 16 bit */ + SIUL_PCR_16B_tag PCR368; /* offset: 0x0320 size: 16 bit */ + SIUL_PCR_16B_tag PCR369; /* offset: 0x0322 size: 16 bit */ + SIUL_PCR_16B_tag PCR370; /* offset: 0x0324 size: 16 bit */ + SIUL_PCR_16B_tag PCR371; /* offset: 0x0326 size: 16 bit */ + SIUL_PCR_16B_tag PCR372; /* offset: 0x0328 size: 16 bit */ + SIUL_PCR_16B_tag PCR373; /* offset: 0x032A size: 16 bit */ + SIUL_PCR_16B_tag PCR374; /* offset: 0x032C size: 16 bit */ + SIUL_PCR_16B_tag PCR375; /* offset: 0x032E size: 16 bit */ + SIUL_PCR_16B_tag PCR376; /* offset: 0x0330 size: 16 bit */ + SIUL_PCR_16B_tag PCR377; /* offset: 0x0332 size: 16 bit */ + SIUL_PCR_16B_tag PCR378; /* offset: 0x0334 size: 16 bit */ + SIUL_PCR_16B_tag PCR379; /* offset: 0x0336 size: 16 bit */ + SIUL_PCR_16B_tag PCR380; /* offset: 0x0338 size: 16 bit */ + SIUL_PCR_16B_tag PCR381; /* offset: 0x033A size: 16 bit */ + SIUL_PCR_16B_tag PCR382; /* offset: 0x033C size: 16 bit */ + SIUL_PCR_16B_tag PCR383; /* offset: 0x033E size: 16 bit */ + SIUL_PCR_16B_tag PCR384; /* offset: 0x0340 size: 16 bit */ + SIUL_PCR_16B_tag PCR385; /* offset: 0x0342 size: 16 bit */ + SIUL_PCR_16B_tag PCR386; /* offset: 0x0344 size: 16 bit */ + SIUL_PCR_16B_tag PCR387; /* offset: 0x0346 size: 16 bit */ + SIUL_PCR_16B_tag PCR388; /* offset: 0x0348 size: 16 bit */ + SIUL_PCR_16B_tag PCR389; /* offset: 0x034A size: 16 bit */ + SIUL_PCR_16B_tag PCR390; /* offset: 0x034C size: 16 bit */ + SIUL_PCR_16B_tag PCR391; /* offset: 0x034E size: 16 bit */ + SIUL_PCR_16B_tag PCR392; /* offset: 0x0350 size: 16 bit */ + SIUL_PCR_16B_tag PCR393; /* offset: 0x0352 size: 16 bit */ + SIUL_PCR_16B_tag PCR394; /* offset: 0x0354 size: 16 bit */ + SIUL_PCR_16B_tag PCR395; /* offset: 0x0356 size: 16 bit */ + SIUL_PCR_16B_tag PCR396; /* offset: 0x0358 size: 16 bit */ + SIUL_PCR_16B_tag PCR397; /* offset: 0x035A size: 16 bit */ + SIUL_PCR_16B_tag PCR398; /* offset: 0x035C size: 16 bit */ + SIUL_PCR_16B_tag PCR399; /* offset: 0x035E size: 16 bit */ + SIUL_PCR_16B_tag PCR400; /* offset: 0x0360 size: 16 bit */ + SIUL_PCR_16B_tag PCR401; /* offset: 0x0362 size: 16 bit */ + SIUL_PCR_16B_tag PCR402; /* offset: 0x0364 size: 16 bit */ + SIUL_PCR_16B_tag PCR403; /* offset: 0x0366 size: 16 bit */ + SIUL_PCR_16B_tag PCR404; /* offset: 0x0368 size: 16 bit */ + SIUL_PCR_16B_tag PCR405; /* offset: 0x036A size: 16 bit */ + SIUL_PCR_16B_tag PCR406; /* offset: 0x036C size: 16 bit */ + SIUL_PCR_16B_tag PCR407; /* offset: 0x036E size: 16 bit */ + SIUL_PCR_16B_tag PCR408; /* offset: 0x0370 size: 16 bit */ + SIUL_PCR_16B_tag PCR409; /* offset: 0x0372 size: 16 bit */ + SIUL_PCR_16B_tag PCR410; /* offset: 0x0374 size: 16 bit */ + SIUL_PCR_16B_tag PCR411; /* offset: 0x0376 size: 16 bit */ + SIUL_PCR_16B_tag PCR412; /* offset: 0x0378 size: 16 bit */ + SIUL_PCR_16B_tag PCR413; /* offset: 0x037A size: 16 bit */ + SIUL_PCR_16B_tag PCR414; /* offset: 0x037C size: 16 bit */ + SIUL_PCR_16B_tag PCR415; /* offset: 0x037E size: 16 bit */ + SIUL_PCR_16B_tag PCR416; /* offset: 0x0380 size: 16 bit */ + SIUL_PCR_16B_tag PCR417; /* offset: 0x0382 size: 16 bit */ + SIUL_PCR_16B_tag PCR418; /* offset: 0x0384 size: 16 bit */ + SIUL_PCR_16B_tag PCR419; /* offset: 0x0386 size: 16 bit */ + SIUL_PCR_16B_tag PCR420; /* offset: 0x0388 size: 16 bit */ + SIUL_PCR_16B_tag PCR421; /* offset: 0x038A size: 16 bit */ + SIUL_PCR_16B_tag PCR422; /* offset: 0x038C size: 16 bit */ + SIUL_PCR_16B_tag PCR423; /* offset: 0x038E size: 16 bit */ + SIUL_PCR_16B_tag PCR424; /* offset: 0x0390 size: 16 bit */ + SIUL_PCR_16B_tag PCR425; /* offset: 0x0392 size: 16 bit */ + SIUL_PCR_16B_tag PCR426; /* offset: 0x0394 size: 16 bit */ + SIUL_PCR_16B_tag PCR427; /* offset: 0x0396 size: 16 bit */ + SIUL_PCR_16B_tag PCR428; /* offset: 0x0398 size: 16 bit */ + SIUL_PCR_16B_tag PCR429; /* offset: 0x039A size: 16 bit */ + SIUL_PCR_16B_tag PCR430; /* offset: 0x039C size: 16 bit */ + SIUL_PCR_16B_tag PCR431; /* offset: 0x039E size: 16 bit */ + SIUL_PCR_16B_tag PCR432; /* offset: 0x03A0 size: 16 bit */ + SIUL_PCR_16B_tag PCR433; /* offset: 0x03A2 size: 16 bit */ + SIUL_PCR_16B_tag PCR434; /* offset: 0x03A4 size: 16 bit */ + SIUL_PCR_16B_tag PCR435; /* offset: 0x03A6 size: 16 bit */ + SIUL_PCR_16B_tag PCR436; /* offset: 0x03A8 size: 16 bit */ + SIUL_PCR_16B_tag PCR437; /* offset: 0x03AA size: 16 bit */ + SIUL_PCR_16B_tag PCR438; /* offset: 0x03AC size: 16 bit */ + SIUL_PCR_16B_tag PCR439; /* offset: 0x03AE size: 16 bit */ + SIUL_PCR_16B_tag PCR440; /* offset: 0x03B0 size: 16 bit */ + SIUL_PCR_16B_tag PCR441; /* offset: 0x03B2 size: 16 bit */ + SIUL_PCR_16B_tag PCR442; /* offset: 0x03B4 size: 16 bit */ + SIUL_PCR_16B_tag PCR443; /* offset: 0x03B6 size: 16 bit */ + SIUL_PCR_16B_tag PCR444; /* offset: 0x03B8 size: 16 bit */ + SIUL_PCR_16B_tag PCR445; /* offset: 0x03BA size: 16 bit */ + SIUL_PCR_16B_tag PCR446; /* offset: 0x03BC size: 16 bit */ + SIUL_PCR_16B_tag PCR447; /* offset: 0x03BE size: 16 bit */ + SIUL_PCR_16B_tag PCR448; /* offset: 0x03C0 size: 16 bit */ + SIUL_PCR_16B_tag PCR449; /* offset: 0x03C2 size: 16 bit */ + SIUL_PCR_16B_tag PCR450; /* offset: 0x03C4 size: 16 bit */ + SIUL_PCR_16B_tag PCR451; /* offset: 0x03C6 size: 16 bit */ + SIUL_PCR_16B_tag PCR452; /* offset: 0x03C8 size: 16 bit */ + SIUL_PCR_16B_tag PCR453; /* offset: 0x03CA size: 16 bit */ + SIUL_PCR_16B_tag PCR454; /* offset: 0x03CC size: 16 bit */ + SIUL_PCR_16B_tag PCR455; /* offset: 0x03CE size: 16 bit */ + SIUL_PCR_16B_tag PCR456; /* offset: 0x03D0 size: 16 bit */ + SIUL_PCR_16B_tag PCR457; /* offset: 0x03D2 size: 16 bit */ + SIUL_PCR_16B_tag PCR458; /* offset: 0x03D4 size: 16 bit */ + SIUL_PCR_16B_tag PCR459; /* offset: 0x03D6 size: 16 bit */ + SIUL_PCR_16B_tag PCR460; /* offset: 0x03D8 size: 16 bit */ + SIUL_PCR_16B_tag PCR461; /* offset: 0x03DA size: 16 bit */ + SIUL_PCR_16B_tag PCR462; /* offset: 0x03DC size: 16 bit */ + SIUL_PCR_16B_tag PCR463; /* offset: 0x03DE size: 16 bit */ + SIUL_PCR_16B_tag PCR464; /* offset: 0x03E0 size: 16 bit */ + SIUL_PCR_16B_tag PCR465; /* offset: 0x03E2 size: 16 bit */ + SIUL_PCR_16B_tag PCR466; /* offset: 0x03E4 size: 16 bit */ + SIUL_PCR_16B_tag PCR467; /* offset: 0x03E6 size: 16 bit */ + SIUL_PCR_16B_tag PCR468; /* offset: 0x03E8 size: 16 bit */ + SIUL_PCR_16B_tag PCR469; /* offset: 0x03EA size: 16 bit */ + SIUL_PCR_16B_tag PCR470; /* offset: 0x03EC size: 16 bit */ + SIUL_PCR_16B_tag PCR471; /* offset: 0x03EE size: 16 bit */ + SIUL_PCR_16B_tag PCR472; /* offset: 0x03F0 size: 16 bit */ + SIUL_PCR_16B_tag PCR473; /* offset: 0x03F2 size: 16 bit */ + SIUL_PCR_16B_tag PCR474; /* offset: 0x03F4 size: 16 bit */ + SIUL_PCR_16B_tag PCR475; /* offset: 0x03F6 size: 16 bit */ + SIUL_PCR_16B_tag PCR476; /* offset: 0x03F8 size: 16 bit */ + SIUL_PCR_16B_tag PCR477; /* offset: 0x03FA size: 16 bit */ + SIUL_PCR_16B_tag PCR478; /* offset: 0x03FC size: 16 bit */ + SIUL_PCR_16B_tag PCR479; /* offset: 0x03FE size: 16 bit */ + SIUL_PCR_16B_tag PCR480; /* offset: 0x0400 size: 16 bit */ + SIUL_PCR_16B_tag PCR481; /* offset: 0x0402 size: 16 bit */ + SIUL_PCR_16B_tag PCR482; /* offset: 0x0404 size: 16 bit */ + SIUL_PCR_16B_tag PCR483; /* offset: 0x0406 size: 16 bit */ + SIUL_PCR_16B_tag PCR484; /* offset: 0x0408 size: 16 bit */ + SIUL_PCR_16B_tag PCR485; /* offset: 0x040A size: 16 bit */ + SIUL_PCR_16B_tag PCR486; /* offset: 0x040C size: 16 bit */ + SIUL_PCR_16B_tag PCR487; /* offset: 0x040E size: 16 bit */ + SIUL_PCR_16B_tag PCR488; /* offset: 0x0410 size: 16 bit */ + SIUL_PCR_16B_tag PCR489; /* offset: 0x0412 size: 16 bit */ + SIUL_PCR_16B_tag PCR490; /* offset: 0x0414 size: 16 bit */ + SIUL_PCR_16B_tag PCR491; /* offset: 0x0416 size: 16 bit */ + SIUL_PCR_16B_tag PCR492; /* offset: 0x0418 size: 16 bit */ + SIUL_PCR_16B_tag PCR493; /* offset: 0x041A size: 16 bit */ + SIUL_PCR_16B_tag PCR494; /* offset: 0x041C size: 16 bit */ + SIUL_PCR_16B_tag PCR495; /* offset: 0x041E size: 16 bit */ + SIUL_PCR_16B_tag PCR496; /* offset: 0x0420 size: 16 bit */ + SIUL_PCR_16B_tag PCR497; /* offset: 0x0422 size: 16 bit */ + SIUL_PCR_16B_tag PCR498; /* offset: 0x0424 size: 16 bit */ + SIUL_PCR_16B_tag PCR499; /* offset: 0x0426 size: 16 bit */ + SIUL_PCR_16B_tag PCR500; /* offset: 0x0428 size: 16 bit */ + SIUL_PCR_16B_tag PCR501; /* offset: 0x042A size: 16 bit */ + SIUL_PCR_16B_tag PCR502; /* offset: 0x042C size: 16 bit */ + SIUL_PCR_16B_tag PCR503; /* offset: 0x042E size: 16 bit */ + SIUL_PCR_16B_tag PCR504; /* offset: 0x0430 size: 16 bit */ + SIUL_PCR_16B_tag PCR505; /* offset: 0x0432 size: 16 bit */ + SIUL_PCR_16B_tag PCR506; /* offset: 0x0434 size: 16 bit */ + SIUL_PCR_16B_tag PCR507; /* offset: 0x0436 size: 16 bit */ + SIUL_PCR_16B_tag PCR508; /* offset: 0x0438 size: 16 bit */ + SIUL_PCR_16B_tag PCR509; /* offset: 0x043A size: 16 bit */ + SIUL_PCR_16B_tag PCR510; /* offset: 0x043C size: 16 bit */ + SIUL_PCR_16B_tag PCR511; /* offset: 0x043E size: 16 bit */ + }; + + }; + int8_t SIUL_reserved_0440_C[192]; + union { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */ + + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */ + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */ + }; + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */ + SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */ + }; + + }; + union { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */ + + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */ + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */ + }; + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */ + }; + + }; + union { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */ + + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */ + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */ + }; + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */ + }; + + }; + int8_t SIUL_reserved_0A00_C[512]; + union { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */ + + struct { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */ + }; + + }; + union { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */ + + struct { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */ + }; + + }; + union { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */ + + struct { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */ + }; + + }; + int8_t SIUL_reserved_0D00_C[768]; + union { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */ + + struct { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */ + }; + + }; + /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */ + } SIUL_tag; + + +#define SIUL (*(volatile SIUL_tag *) 0xC3F90000UL) + + + +/****************************************************************/ +/* */ +/* Module: WKPU */ +/* */ +/****************************************************************/ + + typedef union { /* WKPU_NSR - NMI Status Flag Register */ + vuint32_t R; + struct { + vuint32_t NIF0:1; /* NMI Status Flag 0 */ + vuint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */ + vuint32_t:6; + vuint32_t NIF1:1; /* NMI Status Flag 1 */ + vuint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */ + vuint32_t:6; + vuint32_t NIF2:1; /* NMI Status Flag 2 */ + vuint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */ + vuint32_t:6; + vuint32_t NIF3:1; /* NMI Status Flag 3 */ + vuint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */ + vuint32_t:6; + } B; + } WKPU_NSR_32B_tag; + + typedef union { /* WKPU_NCR - NMI Configuration Register */ + vuint32_t R; + struct { + vuint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */ + vuint32_t NDSS0:2; /* NMI Desination Source Select 0 */ + vuint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */ + vuint32_t:1; + vuint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */ + vuint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */ + vuint32_t NFE0:1; /* NMI Filter Enable 0 */ + vuint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */ + vuint32_t NDSS1:2; /* NMI Desination Source Select 1 */ + vuint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */ + vuint32_t:1; + vuint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */ + vuint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */ + vuint32_t NFE1:1; /* NMI Filter Enable 1 */ + vuint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */ + vuint32_t NDSS2:2; /* NMI Desination Source Select 2 */ + vuint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */ + vuint32_t:1; + vuint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */ + vuint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */ + vuint32_t NFE2:1; /* NMI Filter Enable 2 */ + vuint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */ + vuint32_t NDSS3:2; /* NMI Desination Source Select 3 */ + vuint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */ + vuint32_t:1; + vuint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */ + vuint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */ + vuint32_t NFE3:1; /* NMI Filter Enable 3 */ + } B; + } WKPU_NCR_32B_tag; + + typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + vuint32_t R; + struct { + vuint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */ + } B; + } WKPU_WISR_32B_tag; + + typedef union { /* WKPU_IRER - Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t EIRE:32; /* Enable External Interrupt Requests */ + } B; + } WKPU_IRER_32B_tag; + + typedef union { /* WKPU_WRER - Wakeup Request Enable Register */ + vuint32_t R; + struct { + vuint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */ + } B; + } WKPU_WRER_32B_tag; + + typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIREER_32B_tag; + + typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + vuint32_t R; + struct { + vuint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIFEER_32B_tag; + + typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + vuint32_t R; + struct { + vuint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */ + } B; + } WKPU_WIFER_32B_tag; + + typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + vuint32_t R; + struct { + vuint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */ + } B; + } WKPU_WIPUER_32B_tag; + + + + typedef struct WKPU_struct_tag { /* start of WKPU_tag */ + /* WKPU_NSR - NMI Status Flag Register */ + WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */ + int8_t WKPU_reserved_0004[4]; + /* WKPU_NCR - NMI Configuration Register */ + WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */ + int8_t WKPU_reserved_000C[8]; + /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */ + /* WKPU_IRER - Interrupt Request Enable Register */ + WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + /* WKPU_WRER - Wakeup Request Enable Register */ + WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */ + int8_t WKPU_reserved_0020[8]; + /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */ + /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */ + /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */ + /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */ + } WKPU_tag; + + +#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL) + + + +/****************************************************************/ +/* */ +/* Module: SSCM */ +/* */ +/****************************************************************/ + + typedef union { /* SSCM_STATUS - System Status Register */ + vuint16_t R; + struct { + vuint16_t LSM:1; /* Lock Step Mode */ + vuint16_t:2; + vuint16_t NXEN1:1; /* Processor 1 Nexus enabled */ + vuint16_t NXEN:1; /* Processor 0 Nexus enabled */ + vuint16_t PUB:1; /* Public Serial Access Status */ + vuint16_t SEC:1; /* Security Status */ + vuint16_t:1; + vuint16_t BMODE:3; /* Device Boot Mode */ +#ifndef USE_FIELD_ALIASES_SSCM + vuint16_t VLE:1; /* Variable Length Instruction Mode */ +#else + vuint16_t DMID:1; /* deprecated name - please avoid */ +#endif + vuint16_t ABD:1; /* Autobaud detection */ + vuint16_t:3; + } B; + } SSCM_STATUS_16B_tag; + + typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */ + vuint16_t R; + struct { + vuint16_t JPIN:10; /* JTAG Part ID Number */ + vuint16_t IVLD:1; /* Instruction Flash Valid */ + vuint16_t MREV:4; /* Minor Mask Revision */ + vuint16_t DVLD:1; /* Data Flash Valid */ + } B; + } SSCM_MEMCONFIG_16B_tag; + + typedef union { /* SSCM_ERROR - Error Configuration */ + vuint16_t R; + struct { + vuint16_t:14; + vuint16_t PAE:1; /* Peripheral Bus Abort Enable */ + vuint16_t RAE:1; /* Register Bus Abort Enable */ + } B; + } SSCM_ERROR_16B_tag; + + typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */ + vuint16_t R; + struct { + vuint16_t:13; + vuint16_t DEBUG_MODE:3; /* Debug Status Port Mode */ + } B; + } SSCM_DEBUGPORT_16B_tag; + + typedef union { /* SSCM_PWCMPH - Password Comparison Register High */ + vuint32_t R; + struct { + vuint32_t PWD_HI:32; /* Password High */ + } B; + } SSCM_PWCMPH_32B_tag; + + typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */ + vuint32_t R; + struct { + vuint32_t PWD_LO:32; /* Password Low */ + } B; + } SSCM_PWCMPL_32B_tag; + + typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + vuint32_t R; + struct { + vuint32_t P2BOOT:30; /* boot location 2nd processor */ + vuint32_t DVLE:1; /* VLE mode for 2nd processor */ + vuint32_t:1; + } B; + } SSCM_DPMBOOT_32B_tag; + + typedef union { /* SSCM_DPMKEY - Boot Key Register */ + vuint32_t R; + struct { + vuint32_t KEY:32; /* Boot Control Key */ + } B; + } SSCM_DPMKEY_32B_tag; + + typedef union { /* SSCM_UOPS - User Option Status Register */ + vuint32_t R; + struct { + vuint32_t UOPT:32; /* User Option Bits */ + } B; + } SSCM_UOPS_32B_tag; + + typedef union { /* SSCM_SCTR - SSCM Control Register */ + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t TFE:1; /* Test Flash Enable */ + vuint32_t DSL:1; /* Disable Software-Controlled MBIST */ + vuint32_t DSM:1; /* Disable Software-Controlled LBIST */ + } B; + } SSCM_SCTR_32B_tag; + + typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + vuint32_t R; + struct { + vuint32_t TINFO0:32; /* General purpose TestFlash word 0 */ + } B; + } SSCM_TF_INFO0_32B_tag; + + typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + vuint32_t R; + struct { + vuint32_t TINFO1:32; /* General purpose TestFlash word 1 */ + } B; + } SSCM_TF_INFO1_32B_tag; + + typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + vuint32_t R; + struct { + vuint32_t TINFO2:32; /* General purpose TestFlash word 2 */ + } B; + } SSCM_TF_INFO2_32B_tag; + + typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + vuint32_t R; + struct { + vuint32_t TINFO3:32; /* General purpose TestFlash word */ + } B; + } SSCM_TF_INFO3_32B_tag; + + + + typedef struct SSCM_struct_tag { /* start of SSCM_tag */ + /* SSCM_STATUS - System Status Register */ + SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */ + /* SSCM_MEMCONFIG - System Memory Configuration Register */ + SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */ + int8_t SSCM_reserved_0004[2]; + /* SSCM_ERROR - Error Configuration */ + SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */ + /* SSCM_DEBUGPORT - Debug Status Port Register */ + SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */ + int8_t SSCM_reserved_000A[2]; + /* SSCM_PWCMPH - Password Comparison Register High */ + SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */ + /* SSCM_PWCMPL - Password Comparison Register Low */ + SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */ + int8_t SSCM_reserved_0014[4]; + /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */ + /* SSCM_DPMKEY - Boot Key Register */ + SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */ + /* SSCM_UOPS - User Option Status Register */ + SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */ + /* SSCM_SCTR - SSCM Control Register */ + SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */ + /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */ + /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */ + /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */ + /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */ + } SSCM_tag; + + +#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL) + + + +/****************************************************************/ +/* */ +/* Module: ME */ +/* */ +/****************************************************************/ + + typedef union { /* ME_GS - Global Status Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ME + vuint32_t S_CURRENT_MODE:4; /* Current device mode status */ +#else + vuint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */ +#endif + vuint32_t S_MTRANS:1; /* Mode transition status */ + vuint32_t:3; + vuint32_t S_PDO:1; /* Output power-down status */ + vuint32_t:2; + vuint32_t S_MVR:1; /* Main voltage regulator status */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t S_FLA:2; /* Flash availability status */ +#else + vuint32_t S_CFLA:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; + vuint32_t S_PLL1:1; /* Secondary PLL status */ + vuint32_t S_PLL0:1; /* System PLL status */ +#ifndef USE_FIELD_ALIASES_ME + vuint32_t S_XOSC:1; /* System crystal oscillator status */ +#else + vuint32_t S_OSC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t S_IRCOSC:1; /* System RC oscillator status */ +#else + vuint32_t S_RC:1; /* deprecated name - please avoid */ +#endif + vuint32_t S_SYSCLK:4; /* System clock switch status */ + } B; + } ME_GS_32B_tag; + + typedef union { /* ME_MCTL - Mode Control Register */ + vuint32_t R; + struct { + vuint32_t TARGET_MODE:4; /* Target device mode */ + vuint32_t:12; + vuint32_t KEY:16; /* Control key */ + } B; + } ME_MCTL_32B_tag; + + typedef union { /* ME_MEN - Mode Enable Register */ + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t STOP0:1; /* STOP0 mode enable */ + vuint32_t:1; + vuint32_t HALT0:1; /* HALT0 mode enable */ + vuint32_t RUN3:1; /* RUN3 mode enable */ + vuint32_t RUN2:1; /* RUN2 mode enable */ + vuint32_t RUN1:1; /* RUN1 mode enable */ + vuint32_t RUN0:1; /* RUN0 mode enable */ + vuint32_t DRUN:1; /* DRUN mode enable */ + vuint32_t SAFE:1; /* SAFE mode enable */ + vuint32_t:1; + vuint32_t RESET:1; /* RESET mode enable */ + } B; + } ME_MEN_32B_tag; + + typedef union { /* ME_IS - Interrupt Status Register */ + vuint32_t R; + struct { + vuint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t I_ICONF:1; /* Invalid mode config interrupt */ +#else + vuint32_t I_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t I_IMODE:1; /* Invalid mode interrupt */ +#else + vuint32_t I_MODE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t I_SAFE:1; /* SAFE mode interrupt */ +#else + vuint32_t I_AFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t I_MTC:1; /* Mode transition complete interrupt */ +#else + vuint32_t I_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IS_32B_tag; + + typedef union { /* ME_IM - Interrupt Mask Register */ + vuint32_t R; + struct { + vuint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t M_ICONF:1; /* Invalid mode config interrupt mask */ +#else + vuint32_t M_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t M_IMODE:1; /* Invalid mode interrupt mask */ +#else + vuint32_t M_MODE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t M_SAFE:1; /* SAFE mode interrupt mask */ +#else + vuint32_t M_AFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t M_MTC:1; /* Mode transition complete interrupt mask */ +#else + vuint32_t M_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IM_32B_tag; + + typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */ + vuint32_t R; + struct { + vuint32_t:27; + vuint32_t S_MTI:1; /* Mode Transition Illegal status */ + vuint32_t S_MRI:1; /* Mode Request Illegal status */ + vuint32_t S_DMA:1; /* Disabled Mode Access status */ + vuint32_t S_NMA:1; /* Non-existing Mode Access status */ + vuint32_t S_SEA:1; /* Safe Event Active status */ + } B; + } ME_IMTS_32B_tag; + + typedef union { /* ME_DMTS - Debug Mode Transition Status Register */ + vuint32_t R; + struct { + vuint32_t PREVIOUS_MODE:4; /* Previous Device Mode */ + vuint32_t:4; + vuint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */ + vuint32_t:2; + vuint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */ + vuint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */ + vuint32_t:2; + vuint32_t SMR:1; /* SAFE Mode Request */ + vuint32_t:1; + vuint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */ + vuint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */ + vuint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */ + vuint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */ + vuint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */ + vuint32_t:1; + vuint32_t FLASH_SC:1; /* FLASH State Change Indicator */ + vuint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */ + vuint32_t:4; + vuint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */ + vuint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */ + vuint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */ + } B; + } ME_DMTS_32B_tag; + + typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RESET_MC_32B_tag; + + typedef union { /* ME_SAFE_MC - Mode Configuration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_SAFE_MC_32B_tag; + + typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_DRUN_MC_32B_tag; + + + /* Register layout for all registers RUN_MC... */ + + typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; + vuint32_t FLAON:2; /* Code flash power-down control */ + vuint32_t:8; + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ + vuint32_t PLL0ON:1; /* System PLL control */ + vuint32_t XOSCON:1; /* System crystal oscillator control */ + vuint32_t IRCOSCON:1; /* System RC oscillator control */ + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RUN_MC_32B_tag; + + typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_HALT0_MC_32B_tag; + + typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STOP0_MC_32B_tag; + + typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t PDO:1; /* IOs output power-down control */ + vuint32_t:2; + vuint32_t MVRON:1; /* Main voltage regulator control */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t FLAON:2; /* Code flash power-down control */ +#else + vuint32_t CFLAON:2; /* deprecated name - please avoid */ +#endif + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + vuint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t PLL0ON:1; /* System PLL control */ +#else + vuint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t XOSCON:1; /* System crystal oscillator control */ +#else + vuint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + vuint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + vuint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + vuint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STANDBY0_MC_32B_tag; + + typedef union { /* ME_PS0 - Peripheral Status Register 0 */ + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t S_FLEXRAY:1; /* FlexRay status */ + vuint32_t:6; + vuint32_t S_FLEXCAN1:1; /* FlexCAN1 status */ + vuint32_t S_FLEXCAN0:1; /* FlexCAN0 status */ + vuint32_t:9; + vuint32_t S_DSPI2:1; /* DSPI2 status */ + vuint32_t S_DSPI1:1; /* DSPI1 status */ + vuint32_t S_DSPI0:1; /* DSPI0 status */ + vuint32_t:4; + } B; + } ME_PS0_32B_tag; + + typedef union { /* ME_PS1 - Peripheral Status Register 1 */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t S_SWG:1; /* SWG status */ + vuint32_t:3; + vuint32_t S_CRC:1; /* CRC status */ + vuint32_t:8; + vuint32_t S_LIN_FLEX1:1; /* LinFlex1 status */ + vuint32_t S_LIN_FLEX0:1; /* LinFlex0 status */ + vuint32_t:5; + vuint32_t S_FLEXPWM1:1; /* FlexPWM1 status */ + vuint32_t S_FLEXPWM0:1; /* FlexPWM0 status */ + vuint32_t S_ETIMER2:1; /* eTimer2 status */ + vuint32_t S_ETIMER1:1; /* eTimer1 status */ + vuint32_t S_ETIMER0:1; /* eTimer0 status */ + vuint32_t:2; + vuint32_t S_CTU:1; /* CTU status */ + vuint32_t:1; + vuint32_t S_ADC1:1; /* ADC1 status */ + vuint32_t S_ADC0:1; /* ADC0 status */ + } B; + } ME_PS1_32B_tag; + + typedef union { /* ME_PS2 - Peripheral Status Register 2 */ + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t S_PIT:1; /* PIT status */ + vuint32_t:28; + } B; + } ME_PS2_32B_tag; + + + /* Register layout for all registers RUN_PC... */ + + typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t RUN3:1; /* Peripheral control during RUN3 */ + vuint32_t RUN2:1; /* Peripheral control during RUN2 */ + vuint32_t RUN1:1; /* Peripheral control during RUN1 */ + vuint32_t RUN0:1; /* Peripheral control during RUN0 */ + vuint32_t DRUN:1; /* Peripheral control during DRUN */ + vuint32_t SAFE:1; /* Peripheral control during SAFE */ + vuint32_t TEST:1; /* Peripheral control during TEST */ + vuint32_t RESET:1; /* Peripheral control during RESET */ + } B; + } ME_RUN_PC_32B_tag; + + + /* Register layout for all registers LP_PC... */ + + typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t STOP0:1; /* Peripheral control during STOP0 */ + vuint32_t:1; + vuint32_t HALT0:1; /* Peripheral control during HALT0 */ + vuint32_t:8; + } B; + } ME_LP_PC_32B_tag; + + + /* Register layout for all registers PCTL... */ + + typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t DBG_F:1; /* Peripheral control in debug mode */ + vuint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */ + vuint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */ + } B; + } ME_PCTL_8B_tag; + + + + + /* Register layout for generated register(s) PS... */ + + typedef union { /* */ + vuint32_t R; + } ME_PS_32B_tag; + + + + + + + typedef struct ME_struct_tag { /* start of ME_tag */ + /* ME_GS - Global Status Register */ + ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */ + /* ME_MCTL - Mode Control Register */ + ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */ + union { + ME_MEN_32B_tag MER; /* deprecated - please avoid */ + + /* ME_MEN - Mode Enable Register */ + ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */ + + }; + /* ME_IS - Interrupt Status Register */ + ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */ + /* ME_IM - Interrupt Mask Register */ + ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */ + /* ME_IMTS - Invalid Mode Transition Status Register */ + ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */ + /* ME_DMTS - Debug Mode Transition Status Register */ + ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */ + int8_t ME_reserved_001C_C[4]; + union { + /* ME_RESET_MC - RESET Mode Configuration Register */ + ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */ + + ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0024_C[4]; + union { + /* ME_SAFE_MC - Mode Configuration Register */ + ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */ + + ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */ + + }; + union { + /* ME_DRUN_MC - DRUN Mode Configuration Register */ + ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */ + + ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */ + + }; + union { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */ + + ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */ + + struct { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */ + ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */ + ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */ + ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */ + }; + + }; + union { + /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */ + + ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0044_C[4]; + union { + /* ME_STOP0_MC - STOP0 Mode Configration Register */ + ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */ + + ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_004C_C[8]; + union { + /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */ + + ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0058_C[8]; + union { + ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */ + + struct { + /* ME_PS0 - Peripheral Status Register 0 */ + ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */ + /* ME_PS1 - Peripheral Status Register 1 */ + ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */ + /* ME_PS2 - Peripheral Status Register 2 */ + ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t ME_reserved_006C_C[20]; + union { + ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */ + ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + union { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */ + + struct { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */ + ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */ + ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */ + ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */ + ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */ + ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */ + ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */ + ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */ + ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */ + ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */ + ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */ + ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */ + ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */ + ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */ + ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */ + ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */ + ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */ + ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */ + ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */ + ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */ + ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */ + ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */ + ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */ + ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */ + ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */ + ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */ + ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */ + ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */ + ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */ + ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */ + ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */ + ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */ + ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */ + ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */ + ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */ + ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */ + ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */ + ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */ + ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */ + ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */ + ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */ + ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */ + ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */ + ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */ + ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */ + ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */ + ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */ + ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */ + ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */ + ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */ + ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */ + ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */ + ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */ + ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */ + ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */ + ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */ + ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */ + ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */ + ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */ + ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */ + ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */ + ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */ + ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */ + ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */ + ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */ + ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */ + ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */ + ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */ + ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */ + ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */ + ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */ + ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */ + ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */ + ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */ + ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */ + ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */ + ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */ + ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */ + ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */ + ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */ + ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */ + ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */ + ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */ + ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */ + ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */ + ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */ + ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */ + ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */ + ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */ + ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */ + ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */ + ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */ + ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */ + ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */ + ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */ + ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */ + ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */ + ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */ + ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */ + ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */ + ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */ + ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */ + ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */ + ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */ + ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */ + ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */ + ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */ + ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */ + ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */ + ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */ + ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */ + ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */ + ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */ + ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */ + ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */ + ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */ + ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */ + ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */ + ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */ + ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */ + ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */ + ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */ + ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */ + ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */ + ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */ + ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */ + ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */ + ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */ + ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */ + ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */ + ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */ + ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */ + ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */ + ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */ + ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */ + ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */ + ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */ + ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */ + ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */ + ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */ + ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */ + ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */ + ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */ + ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */ + }; + + }; + } ME_tag; + + +#define ME (*(volatile ME_tag *) 0xC3FDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: OSC */ +/* */ +/****************************************************************/ + + typedef union { /* OSC_CTL - Control Register */ + vuint32_t R; + struct { + vuint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */ + vuint32_t:7; + vuint32_t EOCV:8; /* End of Count Value */ + vuint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */ + vuint32_t:2; + vuint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */ + vuint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */ + vuint32_t:5; + vuint32_t S_OSC:1; + vuint32_t OSCON:1; } B; + } OSC_CTL_32B_tag; + + + + typedef struct OSC_struct_tag { /* start of OSC_tag */ + /* OSC_CTL - Control Register */ + OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } OSC_tag; + + +#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RC */ +/* */ +/****************************************************************/ + + typedef union { /* RC_CTL - Control Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t RCTRIM:6; /* Main RC Trimming Bits */ + vuint32_t:3; + vuint32_t RCDIV:5; /* Main RC Clock Division Factor */ + vuint32_t:2; + vuint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */ + vuint32_t:5; + } B; + } RC_CTL_32B_tag; + + + + typedef struct RC_struct_tag { /* start of RC_tag */ + /* RC_CTL - Control Register */ + RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } RC_tag; + + +#define RC (*(volatile RC_tag *) 0xC3FE0060UL) + + + +/****************************************************************/ +/* */ +/* Module: PLLD */ +/* */ +/****************************************************************/ + + typedef union { /* PLLD_CR - Control Register */ + vuint32_t R; + struct { + vuint32_t:2; + vuint32_t IDF:4; /* PLL Input Division Factor */ + vuint32_t ODF:2; /* PLL Output Division Factor */ + vuint32_t:1; + vuint32_t NDIV:7; /* PLL Loop Division Factor */ + vuint32_t:7; + vuint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */ + vuint32_t MODE:1; /* Activate 1:1 Mode */ + vuint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */ + vuint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */ + vuint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */ + vuint32_t S_LOCK:1; /* PLL has Aquired Lock */ + vuint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */ + vuint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */ + vuint32_t PLL_ON:1; /* PLL ON Bit */ + } B; + } PLLD_CR_32B_tag; + + typedef union { /* PLLD_MR - PLLD Modulation Register */ + vuint32_t R; + struct { + vuint32_t STRB_BYPASS:1; /* Strobe Bypass */ + vuint32_t:1; + vuint32_t SPRD_SEL:1; /* Spread Type Selection */ + vuint32_t MOD_PERIOD:13; /* Modulation Period */ + vuint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */ + vuint32_t INC_STEP:15; /* Increment Step */ + } B; + } PLLD_MR_32B_tag; + + + + typedef struct PLLD_struct_tag { /* start of PLLD_tag */ + /* PLLD_CR - Control Register */ + PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* PLLD_MR - PLLD Modulation Register */ + PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */ + + vuint32_t plld_reserved[6]; + } PLLD_tag; + + +#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL) +#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL) + + + +/****************************************************************/ +/* */ +/* Module: CMU */ +/* */ +/****************************************************************/ + + typedef union { /* CMU_CSR - Control Status Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SFM:1; /* Start Frequency Measure */ + vuint32_t:13; + vuint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */ + vuint32_t:5; + vuint32_t RCDIV:2; /* RCfast Clock Division Factor */ + vuint32_t CME_A:1; /* PLL_A Clock Monitor Enable */ + } B; + } CMU_CSR_32B_tag; + + typedef union { /* CMU_FDR - Frequency Display Register */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t FD:20; /* Measured Frequency Bits */ + } B; + } CMU_FDR_32B_tag; + + typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t HFREF_A:12; /* High Frequency Reference Value */ + } B; + } CMU_HFREFR_A_32B_tag; + + typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t LFREF_A:12; /* Low Frequency Reference Value */ + } B; + } CMU_LFREFR_A_32B_tag; + + typedef union { /* CMU_ISR - Interrupt Status Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */ + vuint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */ + vuint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */ + vuint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */ + } B; + } CMU_ISR_32B_tag; + + typedef union { /* CMU_IMR - Interrupt Mask Register */ + vuint32_t R; + } CMU_IMR_32B_tag; + + typedef union { /* CMU_MDR - Measurement Duration Register */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t MD:20; /* Measurment Duration Bits */ + } B; + } CMU_MDR_32B_tag; + + + + typedef struct CMU_struct_tag { /* start of CMU_tag */ + /* CMU_CSR - Control Status Register */ + CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */ + /* CMU_FDR - Frequency Display Register */ + CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */ + /* CMU_HFREFR_A - High Frequency Reference Register */ + CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */ + /* CMU_LFREFR_A - Low Frequency Reference Register */ + CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */ + /* CMU_ISR - Interrupt Status Register */ + CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + /* CMU_IMR - Interrupt Mask Register */ + CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */ + /* CMU_MDR - Measurement Duration Register */ + CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */ + } CMU_tag; + + +#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL) +#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL) +#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL) + + + +/****************************************************************/ +/* */ +/* Module: CGM */ +/* */ +/****************************************************************/ + + typedef union { /* Output Clock Enable Register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t:31; + vuint32_t EN:1; /* Clock Enable Bit */ + } B; + } CGM_OC_EN_32B_tag; + + typedef union { /* Output Clock Division Select Register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t:2; + vuint32_t SELDIV:2; /* Output Clock Division Select */ + vuint32_t SELCTL:4; /* Output Clock Source Selection Control */ + vuint32_t:24; + } B; + } CGM_OCDS_SC_32B_tag; + + typedef union { /* System Clock Select Status Register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t:4; + vuint32_t SELSTAT:4; /* System Clock Source Selection Status */ + vuint32_t:24; + } B; + } CGM_SC_SS_32B_tag; + + typedef union { /* System Clock Divider Configuration Register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t DE0:1; /* Divider 0 Enable */ + vuint32_t:3; + vuint32_t DIV0:4; /* Divider 0 Value */ + vuint32_t:24; + } B; + } CGM_SC_DC0_3_32B_tag; + + + /* Register layout for all registers SC_DC... */ + + typedef union { /* System Clock Divider Configuration Register */ + vuint8_t R; + struct { + vuint8_t DE:1; /* Divider Enable */ + vuint8_t:3; + vuint8_t DIV:4; /* Divider Division Value */ + } B; + } CGM_SC_DC_8B_tag; + + + /* Register layout for all registers AC_SC... */ + + typedef union { /* Auxiliary Clock Select Control Registers */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t:4; + vuint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */ + vuint32_t:24; + } B; + } CGM_AC_SC_32B_tag; + + + /* Register layout for all registers AC_DC0_3... */ + + typedef union { /* Auxiliary Clock Divider Configuration Registers */ + vuint32_t R; + struct { + vuint32_t DE0:1; /* Divider 0 Enable */ + vuint32_t:3; + vuint32_t DIV0:4; /* Divider 0 Value */ + vuint32_t DE1:1; /* Divider 1 Enable */ + vuint32_t:3; + vuint32_t DIV1:4; /* Divider 1 Value */ + vuint32_t:16; + } B; + } CGM_AC_DC0_3_32B_tag; + + + typedef struct CGM_AUXCLK_struct_tag { + + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */ + + } CGM_AUXCLK_tag; + + + typedef struct CGM_struct_tag { /* start of CGM_tag */ + OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */ + int8_t CGM_reserved_0004[92]; + RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */ + int8_t CGM_reserved_0064[60]; + PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */ + int8_t CGM_reserved_00E0[32]; + CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */ + CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */ + CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */ + CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */ + CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */ + CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */ + int8_t CGM_reserved_011C[4]; + CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */ + int8_t CGM_reserved_0124[4]; + CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */ + CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */ + int8_t CGM_reserved_0134[572]; + /* Output Clock Enable Register */ + CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */ + /* Output Clock Division Select Register */ + CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */ + /* System Clock Select Status Register */ + CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */ + union { + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */ + int8_t CGM_reserved_037E_E0[2]; + }; + + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */ + CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */ + int8_t CGM_reserved_037E_E1[2]; + }; + + /* System Clock Divider Configuration Register */ + CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */ + + }; + union { + /* Register set AUXCLK */ + CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */ + + struct { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */ + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */ + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */ + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */ + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */ + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */ + }; + + }; + } CGM_tag; + + +#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RGM */ +/* */ +/****************************************************************/ + + typedef union { /* Functional Event Status Register */ + vuint16_t R; + struct { + vuint16_t F_EXR:1; /* Flag for External Reset */ + vuint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */ + vuint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */ + vuint16_t F_ST_DONE:1; /* Flag for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */ +#else + vuint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + vuint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */ + vuint16_t F_PLL1:1; /* Flag for PLL1 fail */ + vuint16_t F_SWT:1; /* Flag for Software Watchdog Timer */ + vuint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */ + vuint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */ + vuint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */ + vuint16_t F_PLL0:1; /* Flag for PLL0 fail */ + vuint16_t F_CWD:1; /* Flag for Core Watchdog Reset */ + vuint16_t F_SOFT:1; /* Flag for software reset */ + vuint16_t F_CORE:1; /* Flag for core reset */ + vuint16_t F_JTAG:1; /* Flag for JTAG initiated reset */ + } B; + } RGM_FES_16B_tag; + + typedef union { /* Destructive Event Status Register */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t F_POR:1; /* Flag for Power on Reset */ +#else + vuint16_t POR:1; /* deprecated name - please avoid */ +#endif + vuint16_t:7; + vuint16_t F_COMP:1; /* Flag for comparator error */ + vuint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */ + vuint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */ + vuint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */ + vuint16_t:2; + vuint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */ +#else + vuint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DES_16B_tag; + + typedef union { /* Functional Event Reset Disable Register */ + vuint16_t R; + struct { + vuint16_t D_EXR:1; /* Disable External Pad Event Reset */ + vuint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */ + vuint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */ + vuint16_t D_ST_DONE:1; /* Disable self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */ +#else + vuint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + vuint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */ + vuint16_t D_PLL1:1; /* Disable PLL1 fail */ + vuint16_t D_SWT:1; /* Disable Software Watchdog Timer */ + vuint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */ + vuint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */ + vuint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */ + vuint16_t D_PLL0:1; /* Disable PLL0 fail */ + vuint16_t D_CWD:1; /* Disable Core Watchdog Reset */ + vuint16_t D_SOFT:1; /* Disable software reset */ + vuint16_t D_CORE:1; /* Disable core reset */ + vuint16_t D_JTAG:1; /* Disable JTAG initiated reset */ + } B; + } RGM_FERD_16B_tag; + + typedef union { /* Destructive Event Reset Disable Register */ + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t D_COMP:1; /* Disable comparator error */ + vuint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */ + vuint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */ + vuint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */ + vuint16_t:2; + vuint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */ +#else + vuint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DERD_16B_tag; + + typedef union { /* Functional Event Alternate Request Register */ + vuint16_t R; + struct { + vuint16_t:4; +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */ +#else + vuint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + vuint16_t:1; + vuint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */ + vuint16_t:1; + vuint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */ + vuint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq. + too high/low */ + vuint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */ + vuint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */ + vuint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */ + vuint16_t:3; + } B; + } RGM_FEAR_16B_tag; + + typedef union { /* Functional Event Short Sequence Register */ + vuint16_t R; + struct { + vuint16_t SS_EXR:1; /* Short Sequence for External Reset */ + vuint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */ + vuint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */ + vuint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */ +#else + vuint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + vuint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */ + vuint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */ + vuint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */ + vuint16_t:1; + vuint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */ + vuint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */ + vuint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */ + vuint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */ + vuint16_t SS_SOFT:1; /* Short Sequence for software reset */ + vuint16_t SS_CORE:1; /* Short Sequence for core reset */ + vuint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */ + } B; + } RGM_FESS_16B_tag; + + typedef union { /* Functional Bidirectional Reset Enable Register */ + vuint16_t R; + struct { + vuint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */ + vuint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */ + vuint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */ + vuint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + vuint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */ +#else + vuint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + vuint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */ + vuint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */ + vuint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */ + vuint16_t:1; + vuint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */ + vuint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */ + vuint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */ + vuint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */ + vuint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */ + vuint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */ + vuint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */ + } B; + } RGM_FBRE_16B_tag; + + + + typedef struct RGM_struct_tag { /* start of RGM_tag */ + /* Functional Event Status Register */ + RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */ + /* Destructive Event Status Register */ + RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */ + /* Functional Event Reset Disable Register */ + RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */ + /* Destructive Event Reset Disable Register */ + RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */ + int8_t RGM_reserved_0008[8]; + /* Functional Event Alternate Request Register */ + RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */ + int8_t RGM_reserved_0012[6]; + /* Functional Event Short Sequence Register */ + RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */ + int8_t RGM_reserved_001A[2]; + /* Functional Bidirectional Reset Enable Register */ + RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */ + } RGM_tag; + + +#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL) + + + +/****************************************************************/ +/* */ +/* Module: PCU */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers PCONF... */ + + typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t STBY0:1; /* Power domain control during STBY0 */ + vuint32_t:2; + vuint32_t STOP0:1; /* Power domain control during STOP0 */ + vuint32_t:1; + vuint32_t HALT0:1; /* Power domain control during HALT0 */ + vuint32_t RUN3:1; /* Power domain control during RUN3 */ + vuint32_t RUN2:1; /* Power domain control during RUN2 */ + vuint32_t RUN1:1; /* Power domain control during RUN1 */ + vuint32_t RUN0:1; /* Power domain control during RUN0 */ + vuint32_t DRUN:1; /* Power domain control during DRUN */ + vuint32_t SAFE:1; /* Power domain control during SAFE */ + vuint32_t TEST:1; /* Power domain control during TEST */ + vuint32_t RST:1; /* Power domain control during RST */ + } B; + } PCU_PCONF_32B_tag; + + typedef union { /* PCU_PSTAT - Power Domain Status Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t PD15:1; /* Power Status for Power Domain 15 */ + vuint32_t PD14:1; /* Power Status for Power Domain 14 */ + vuint32_t PD13:1; /* Power Status for Power Domain 13 */ + vuint32_t PD12:1; /* Power Status for Power Domain 12 */ + vuint32_t PD11:1; /* Power Status for Power Domain 11 */ + vuint32_t PD10:1; /* Power Status for Power Domain 10 */ + vuint32_t PD9:1; /* Power Status for Power Domain 9 */ + vuint32_t PD8:1; /* Power Status for Power Domain 8 */ + vuint32_t PD7:1; /* Power Status for Power Domain 7 */ + vuint32_t PD6:1; /* Power Status for Power Domain 6 */ + vuint32_t PD5:1; /* Power Status for Power Domain 5 */ + vuint32_t PD4:1; /* Power Status for Power Domain 4 */ + vuint32_t PD3:1; /* Power Status for Power Domain 3 */ + vuint32_t PD2:1; /* Power Status for Power Domain 2 */ + vuint32_t PD1:1; /* Power Status for Power Domain 1 */ + vuint32_t PD0:1; /* Power Status for Power Domain 0 */ + } B; + } PCU_PSTAT_32B_tag; + + + + typedef struct PCU_struct_tag { /* start of PCU_tag */ + union { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */ + + struct { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */ + PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */ + PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */ + PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */ + PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */ + PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */ + PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */ + PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */ + PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */ + PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */ + PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */ + PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */ + PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */ + PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */ + PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */ + PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */ + }; + + }; + /* PCU_PSTAT - Power Domain Status Register */ + PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */ + } PCU_tag; + + +#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL) + + + +/****************************************************************/ +/* */ +/* Module: PMUCTRL */ +/* */ +/****************************************************************/ + + typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */ + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */ + vuint32_t:6; + vuint32_t HVD_M:1; /* High Voltage Detector Main */ + vuint32_t HVD_B:1; /* High Voltage Detector Backup */ + vuint32_t:4; + vuint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATHVD_32B_tag; + + typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */ + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */ + vuint32_t:6; + vuint32_t LVD_M:1; /* Ligh Voltage Detector Main */ + vuint32_t LVD_B:1; /* Ligh Voltage Detector Backup */ + vuint32_t:4; + vuint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATLVD_32B_tag; + + typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATIREG_32B_tag; + + typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATEREG_32B_tag; + + typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */ + vuint32_t R; + struct { + vuint32_t EBMM:1; /* External Ballast Management Mode */ + vuint32_t AEBD:1; /* Automatic External Ballast Detection */ + vuint32_t ENPN:1; /* External NPN status flag */ + vuint32_t:13; + vuint32_t CTB:2; /* Configuration Trace Bits */ + vuint32_t:6; + vuint32_t CBS:4; /* Current BIST Status */ + vuint32_t CPCS:4; /* Current Pmu Configuration Status */ + } B; + } PMUCTRL_STATUS_32B_tag; + + typedef union { /* PMUCTRL_CTRL - PMU Control Register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */ + } B; + } PMUCTRL_CTRL_32B_tag; + + typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */ + vuint32_t R; + struct { + vuint32_t MF_BB:4; /* Mask Fault Bypass Balast */ + vuint32_t:28; + } B; + } PMUCTRL_MASKF_32B_tag; + + typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + vuint32_t R; + struct { + vuint32_t BB_LV:4; /* Bypass Ballast Low Voltage */ + vuint32_t:9; + vuint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */ + vuint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */ + vuint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */ + vuint32_t:13; + vuint32_t LHCF:1; /* Low High voltage detector Critical Fault */ + vuint32_t LNCF:1; /* Low voltage detector Non Critical Fault */ + vuint32_t HNCF:1; /* High voltage detector Non Critical Fault */ + } B; + } PMUCTRL_FAULT_32B_tag; + + typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */ + vuint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */ + vuint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */ + vuint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */ + vuint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */ + vuint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */ + vuint32_t:12; + vuint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */ + vuint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */ + vuint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */ + vuint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */ + } B; + } PMUCTRL_IRQS_32B_tag; + + typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */ + vuint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */ + vuint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */ + vuint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */ + vuint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */ + vuint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */ + vuint32_t:12; + vuint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */ + vuint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */ + vuint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */ + vuint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */ + } B; + } PMUCTRL_IRQE_32B_tag; + + + + typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */ + int8_t PMUCTRL_reserved_0000[4]; + /* PMUCTRL_STATHVD - PMU Status Register HVD */ + PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */ + /* PMUCTRL_STATLVD - PMU Status Register LVD */ + PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */ + int8_t PMUCTRL_reserved_000C[20]; + /* PMUCTRL_STATIREG - PMU Status Register IREG */ + PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */ + /* PMUCTRL_STATEREG - PMU Status Register EREG */ + PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */ + int8_t PMUCTRL_reserved_0028[24]; + /* PMUCTRL_STATUS - PMU Status Register STATUS */ + PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */ + /* PMUCTRL_CTRL - PMU Control Register */ + PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */ + int8_t PMUCTRL_reserved_0048[40]; + /* PMUCTRL_MASKF - PMU Mask Fault Register */ + PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */ + /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */ + /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */ + /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */ + } PMUCTRL_tag; + + +#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL) + + + +/****************************************************************/ +/* */ +/* Module: PIT_RTI */ +/* */ +/****************************************************************/ + + typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t MDIS:1; /* Module Disable. Disable the module clock */ + vuint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */ + } B; + } PIT_RTI_PITMCR_32B_tag; + + + /* Register layout for all registers LDVAL... */ + + typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */ + vuint32_t R; + struct { + vuint32_t TSV:32; /* Time Start Value Bits */ + } B; + } PIT_RTI_LDVAL_32B_tag; + + + /* Register layout for all registers CVAL... */ + + typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */ + vuint32_t R; + struct { + vuint32_t TVL:32; /* Current Timer Value Bits */ + } B; + } PIT_RTI_CVAL_32B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* PIT_RTI_TCTRL - Timer Control Register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; /* Timer Interrupt Enable Bit */ + vuint32_t TEN:1; /* Timer Enable Bit */ + } B; + } PIT_RTI_TCTRL_32B_tag; + + + /* Register layout for all registers TFLG... */ + + typedef union { /* PIT_RTI_TFLG - Timer Flag Register */ + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; /* Timer Interrupt Flag Bit */ + } B; + } PIT_RTI_TFLG_32B_tag; + + + typedef struct PIT_RTI_CHANNEL_struct_tag { + + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */ + + } PIT_RTI_CHANNEL_tag; + + + typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */ + /* PIT_RTI_PITMCR - PIT Module Control Register */ + PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */ + int8_t PIT_RTI_reserved_0004_C[252]; + union { + /* Register set CHANNEL */ + PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */ + + struct { + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */ + }; + + }; + } PIT_RTI_tag; + + +#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL) + + + +/****************************************************************/ +/* */ +/* Module: ADC */ +/* */ +/****************************************************************/ + + typedef union { /* module configuration register */ + vuint32_t R; + struct { + vuint32_t OWREN:1; /* Overwrite enable */ + vuint32_t WLSIDE:1; /* Write Left/right Alligned */ + vuint32_t MODE:1; /* One Shot/Scan Mode Selectiom */ + vuint32_t EDGLEV:1; /* edge or level selection for external start trigger */ + vuint32_t TRGEN:1; /* external trigger enable */ + vuint32_t EDGE:1; /* start trigger egde /level detection */ + vuint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */ + vuint32_t NSTART:1; /* start normal conversion */ + vuint32_t:1; + vuint32_t JTRGEN:1; /* Injectin External Trigger Enable */ + vuint32_t JEDGE:1; /* start trigger egde /level detection for injected */ + vuint32_t JSTART:1; /* injected conversion start */ + vuint32_t:2; + vuint32_t CTUEN:1; /* CTU enabaled */ + vuint32_t:8; + vuint32_t ADCLKSEL:1; /* Select which clock for device */ + vuint32_t ABORTCHAIN:1; /* abort chain conversion */ + vuint32_t ABORT:1; /* abort current conversion */ +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t ACKO:1; /* Auto Clock Off Enable */ +#else + vuint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + vuint32_t OFFREFRESH:1; /* offset phase selection */ + vuint32_t OFFCANC:1; /* offset phase cancellation selection */ + vuint32_t:2; + vuint32_t PWDN:1; /* Power Down Enable */ + } B; + } ADC_MCR_32B_tag; + + typedef union { /* module status register */ + vuint32_t R; + struct { + vuint32_t:7; + vuint32_t NSTART:1; /* normal conversion status */ + vuint32_t JABORT:1; /* Injection chain abort status */ + vuint32_t:2; + vuint32_t JSTART:1; /* Injection Start status */ + vuint32_t:3; + vuint32_t CTUSTART:1; /* ctu start status */ + vuint32_t CHADDR:7; /* which address conv is goin on */ + vuint32_t:3; +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t ACKO:1; /* Auto Clock Off Enable status */ +#else + vuint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + vuint32_t OFFREFRESH:1; /* offset refresh status */ + vuint32_t OFFCANC:1; /* offset phase cancellation status */ + vuint32_t ADCSTATUS:3; /* status of ADC FSM */ + } B; + } ADC_MSR_32B_tag; + + typedef union { /* Interrupt status register */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t OFFCANCOVR:1; /* Offset cancellation phase over */ + vuint32_t EOFFSET:1; /* error in offset refresh */ + vuint32_t EOCTU:1; /* end of CTU channel conversion */ + vuint32_t JEOC:1; /* end of injected channel conversion */ + vuint32_t JECH:1; /* end ofinjected chain conversion */ + vuint32_t EOC:1; /* end of channel conversion */ + vuint32_t ECH:1; /* end of chain conversion */ + } B; + } ADC_ISR_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 0 */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH31:1; /* Channel 31 conversion over */ +#else + vuint32_t EOC31:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH30:1; /* Channel 30 conversion over */ +#else + vuint32_t EOC30:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH29:1; /* Channel 29 conversion over */ +#else + vuint32_t EOC29:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH28:1; /* Channel 28 conversion over */ +#else + vuint32_t EOC28:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH27:1; /* Channel 27 conversion over */ +#else + vuint32_t EOC27:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH26:1; /* Channel 26 conversion over */ +#else + vuint32_t EOC26:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH25:1; /* Channel 25 conversion over */ +#else + vuint32_t EOC25:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH24:1; /* Channel 24 conversion over */ +#else + vuint32_t EOC24:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH23:1; /* Channel 23 conversion over */ +#else + vuint32_t EOC23:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH22:1; /* Channel 22 conversion over */ +#else + vuint32_t EOC22:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH21:1; /* Channel 21 conversion over */ +#else + vuint32_t EOC21:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH20:1; /* Channel 20 conversion over */ +#else + vuint32_t EOC20:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH19:1; /* Channel 19 conversion over */ +#else + vuint32_t EOC19:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH18:1; /* Channel 18 conversion over */ +#else + vuint32_t EOC18:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH17:1; /* Channel 17 conversion over */ +#else + vuint32_t EOC17:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH16:1; /* Channel 16 conversion over */ +#else + vuint32_t EOC16:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH15:1; /* Channel 15 conversion over */ +#else + vuint32_t EOC15:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH14:1; /* Channel 14 conversion over */ +#else + vuint32_t EOC14:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH13:1; /* Channel 13 conversion over */ +#else + vuint32_t EOC13:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH12:1; /* Channel 12 conversion over */ +#else + vuint32_t EOC12:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH11:1; /* Channel 11 conversion over */ +#else + vuint32_t EOC11:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH10:1; /* Channel 10 conversion over */ +#else + vuint32_t EOC10:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH9:1; /* Channel 9 conversion over */ +#else + vuint32_t EOC9:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH8:1; /* Channel 8 conversion over */ +#else + vuint32_t EOC8:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH7:1; /* Channel 7 conversion over */ +#else + vuint32_t EOC7:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH6:1; /* Channel 6 conversion over */ +#else + vuint32_t EOC6:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH5:1; /* Channel 5 conversion over */ +#else + vuint32_t EOC5:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH4:1; /* Channel 4 conversion over */ +#else + vuint32_t EOC4:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH3:1; /* Channel 3 conversion over */ +#else + vuint32_t EOC3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH2:1; /* Channel 2 conversion over */ +#else + vuint32_t EOC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH1:1; /* Channel 1 conversion over */ +#else + vuint32_t EOC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t EOC_CH0:1; /* Channel 0 conversion over */ +#else + vuint32_t EOC0:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_CEOCFR0_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t EOC_CH63:1; /* Channel 63 conversion over */ + vuint32_t EOC_CH62:1; /* Channel 62 conversion over */ + vuint32_t EOC_CH61:1; /* Channel 61 conversion over */ + vuint32_t EOC_CH60:1; /* Channel 60 conversion over */ + vuint32_t EOC_CH59:1; /* Channel 59 conversion over */ + vuint32_t EOC_CH58:1; /* Channel 58 conversion over */ + vuint32_t EOC_CH57:1; /* Channel 57 conversion over */ + vuint32_t EOC_CH56:1; /* Channel 56 conversion over */ + vuint32_t EOC_CH55:1; /* Channel 55 conversion over */ + vuint32_t EOC_CH54:1; /* Channel 54 conversion over */ + vuint32_t EOC_CH53:1; /* Channel 53 conversion over */ + vuint32_t EOC_CH52:1; /* Channel 52 conversion over */ + vuint32_t EOC_CH51:1; /* Channel 51 conversion over */ + vuint32_t EOC_CH50:1; /* Channel 50 conversion over */ + vuint32_t EOC_CH49:1; /* Channel 49 conversion over */ + vuint32_t EOC_CH48:1; /* Channel 48 conversion over */ + vuint32_t EOC_CH47:1; /* Channel 47 conversion over */ + vuint32_t EOC_CH46:1; /* Channel 46 conversion over */ + vuint32_t EOC_CH45:1; /* Channel 45 conversion over */ + vuint32_t EOC_CH44:1; /* Channel 44 conversion over */ + vuint32_t EOC_CH43:1; /* Channel 43 conversion over */ + vuint32_t EOC_CH42:1; /* Channel 42 conversion over */ + vuint32_t EOC_CH41:1; /* Channel 41 conversion over */ + vuint32_t EOC_CH40:1; /* Channel 40 conversion over */ + vuint32_t EOC_CH39:1; /* Channel 39 conversion over */ + vuint32_t EOC_CH38:1; /* Channel 38 conversion over */ + vuint32_t EOC_CH37:1; /* Channel 37 conversion over */ + vuint32_t EOC_CH36:1; /* Channel 36 conversion over */ + vuint32_t EOC_CH35:1; /* Channel 35 conversion over */ + vuint32_t EOC_CH34:1; /* Channel 34 conversion over */ + vuint32_t EOC_CH33:1; /* Channel 33 conversion over */ + vuint32_t EOC_CH32:1; /* Channel 32 conversion over */ + } B; + } ADC_CEOCFR1_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t EOC_CH95:1; /* Channel 95 conversion over */ + vuint32_t EOC_CH94:1; /* Channel 94 conversion over */ + vuint32_t EOC_CH93:1; /* Channel 93 conversion over */ + vuint32_t EOC_CH92:1; /* Channel 92 conversion over */ + vuint32_t EOC_CH91:1; /* Channel 91 conversion over */ + vuint32_t EOC_CH90:1; /* Channel 90 conversion over */ + vuint32_t EOC_CH89:1; /* Channel 89 conversion over */ + vuint32_t EOC_CH88:1; /* Channel 88 conversion over */ + vuint32_t EOC_CH87:1; /* Channel 87 conversion over */ + vuint32_t EOC_CH86:1; /* Channel 86 conversion over */ + vuint32_t EOC_CH85:1; /* Channel 85 conversion over */ + vuint32_t EOC_CH84:1; /* Channel 84 conversion over */ + vuint32_t EOC_CH83:1; /* Channel 83 conversion over */ + vuint32_t EOC_CH82:1; /* Channel 82 conversion over */ + vuint32_t EOC_CH81:1; /* Channel 81 conversion over */ + vuint32_t EOC_CH80:1; /* Channel 80 conversion over */ + vuint32_t EOC_CH79:1; /* Channel 79 conversion over */ + vuint32_t EOC_CH78:1; /* Channel 78 conversion over */ + vuint32_t EOC_CH77:1; /* Channel 77 conversion over */ + vuint32_t EOC_CH76:1; /* Channel 76 conversion over */ + vuint32_t EOC_CH75:1; /* Channel 75 conversion over */ + vuint32_t EOC_CH74:1; /* Channel 74 conversion over */ + vuint32_t EOC_CH73:1; /* Channel 73 conversion over */ + vuint32_t EOC_CH72:1; /* Channel 72 conversion over */ + vuint32_t EOC_CH71:1; /* Channel 71 conversion over */ + vuint32_t EOC_CH70:1; /* Channel 70 conversion over */ + vuint32_t EOC_CH69:1; /* Channel 69 conversion over */ + vuint32_t EOC_CH68:1; /* Channel 68 conversion over */ + vuint32_t EOC_CH67:1; /* Channel 67 conversion over */ + vuint32_t EOC_CH66:1; /* Channel 66 conversion over */ + vuint32_t EOC_CH65:1; /* Channel 65 conversion over */ + vuint32_t EOC_CH64:1; /* Channel 64 conversion over */ + } B; + } ADC_CEOCFR2_32B_tag; + + typedef union { /* interrupt mask register */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */ + vuint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */ + vuint32_t MSKEOCTU:1; /* mask bit for EOCTU */ + vuint32_t MSKJEOC:1; /* mask bit for JEOC */ + vuint32_t MSKJECH:1; /* mask bit for JECH */ + vuint32_t MSKEOC:1; /* mask bit for EOC */ + vuint32_t MSKECH:1; /* mask bit for ECH */ + } B; + } ADC_IMR_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */ + vuint32_t R; + struct { + vuint32_t CIM31:1; /* Channel 31 mask register */ + vuint32_t CIM30:1; /* Channel 30 mask register */ + vuint32_t CIM29:1; /* Channel 29 mask register */ + vuint32_t CIM28:1; /* Channel 28 mask register */ + vuint32_t CIM27:1; /* Channel 27 mask register */ + vuint32_t CIM26:1; /* Channel 26 mask register */ + vuint32_t CIM25:1; /* Channel 25 mask register */ + vuint32_t CIM24:1; /* Channel 24 mask register */ + vuint32_t CIM23:1; /* Channel 23 mask register */ + vuint32_t CIM22:1; /* Channel 22 mask register */ + vuint32_t CIM21:1; /* Channel 21 mask register */ + vuint32_t CIM20:1; /* Channel 20 mask register */ + vuint32_t CIM19:1; /* Channel 19 mask register */ + vuint32_t CIM18:1; /* Channel 18 mask register */ + vuint32_t CIM17:1; /* Channel 17 mask register */ + vuint32_t CIM16:1; /* Channel 16 mask register */ + vuint32_t CIM15:1; /* Channel 15 mask register */ + vuint32_t CIM14:1; /* Channel 14 mask register */ + vuint32_t CIM13:1; /* Channel 13 mask register */ + vuint32_t CIM12:1; /* Channel 12 mask register */ + vuint32_t CIM11:1; /* Channel 11 mask register */ + vuint32_t CIM10:1; /* Channel 10 mask register */ + vuint32_t CIM9:1; /* Channel 9 mask register */ + vuint32_t CIM8:1; /* Channel 8 mask register */ + vuint32_t CIM7:1; /* Channel 7 mask register */ + vuint32_t CIM6:1; /* Channel 6 mask register */ + vuint32_t CIM5:1; /* Channel 5 mask register */ + vuint32_t CIM4:1; /* Channel 4 mask register */ + vuint32_t CIM3:1; /* Channel 3 mask register */ + vuint32_t CIM2:1; /* Channel 2 mask register */ + vuint32_t CIM1:1; /* Channel 1 mask register */ + vuint32_t CIM0:1; /* Channel 0 mask register */ + } B; + } ADC_CIMR0_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t CIM63:1; /* Channel 63 mask register */ + vuint32_t CIM62:1; /* Channel 62 mask register */ + vuint32_t CIM61:1; /* Channel 61 mask register */ + vuint32_t CIM60:1; /* Channel 60 mask register */ + vuint32_t CIM59:1; /* Channel 59 mask register */ + vuint32_t CIM58:1; /* Channel 58 mask register */ + vuint32_t CIM57:1; /* Channel 57 mask register */ + vuint32_t CIM56:1; /* Channel 56 mask register */ + vuint32_t CIM55:1; /* Channel 55 mask register */ + vuint32_t CIM54:1; /* Channel 54 mask register */ + vuint32_t CIM53:1; /* Channel 53 mask register */ + vuint32_t CIM52:1; /* Channel 52 mask register */ + vuint32_t CIM51:1; /* Channel 51 mask register */ + vuint32_t CIM50:1; /* Channel 50 mask register */ + vuint32_t CIM49:1; /* Channel 49 mask register */ + vuint32_t CIM48:1; /* Channel 48 mask register */ + vuint32_t CIM47:1; /* Channel 47 mask register */ + vuint32_t CIM46:1; /* Channel 46 mask register */ + vuint32_t CIM45:1; /* Channel 45 mask register */ + vuint32_t CIM44:1; /* Channel 44 mask register */ + vuint32_t CIM43:1; /* Channel 43 mask register */ + vuint32_t CIM42:1; /* Channel 42 mask register */ + vuint32_t CIM41:1; /* Channel 41 mask register */ + vuint32_t CIM40:1; /* Channel 40 mask register */ + vuint32_t CIM39:1; /* Channel 39 mask register */ + vuint32_t CIM38:1; /* Channel 38 mask register */ + vuint32_t CIM37:1; /* Channel 37 mask register */ + vuint32_t CIM36:1; /* Channel 36 mask register */ + vuint32_t CIM35:1; /* Channel 35 mask register */ + vuint32_t CIM34:1; /* Channel 34 mask register */ + vuint32_t CIM33:1; /* Channel 33 mask register */ + vuint32_t CIM32:1; /* Channel 32 mask register */ + } B; + } ADC_CIMR1_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t CIM95:1; /* Channel 95 mask register */ + vuint32_t CIM94:1; /* Channel 94 mask register */ + vuint32_t CIM93:1; /* Channel 93 mask register */ + vuint32_t CIM92:1; /* Channel 92 mask register */ + vuint32_t CIM91:1; /* Channel 91 mask register */ + vuint32_t CIM90:1; /* Channel 90 mask register */ + vuint32_t CIM89:1; /* Channel 89 mask register */ + vuint32_t CIM88:1; /* Channel 88 mask register */ + vuint32_t CIM87:1; /* Channel 87 mask register */ + vuint32_t CIM86:1; /* Channel 86 mask register */ + vuint32_t CIM85:1; /* Channel 85 mask register */ + vuint32_t CIM84:1; /* Channel 84 mask register */ + vuint32_t CIM83:1; /* Channel 83 mask register */ + vuint32_t CIM82:1; /* Channel 82 mask register */ + vuint32_t CIM81:1; /* Channel 81 mask register */ + vuint32_t CIM80:1; /* Channel 80 mask register */ + vuint32_t CIM79:1; /* Channel 79 mask register */ + vuint32_t CIM78:1; /* Channel 78 mask register */ + vuint32_t CIM77:1; /* Channel 77 mask register */ + vuint32_t CIM76:1; /* Channel 76 mask register */ + vuint32_t CIM75:1; /* Channel 75 mask register */ + vuint32_t CIM74:1; /* Channel 74 mask register */ + vuint32_t CIM73:1; /* Channel 73 mask register */ + vuint32_t CIM72:1; /* Channel 72 mask register */ + vuint32_t CIM71:1; /* Channel 71 mask register */ + vuint32_t CIM70:1; /* Channel 70 mask register */ + vuint32_t CIM69:1; /* Channel 69 mask register */ + vuint32_t CIM68:1; /* Channel 68 mask register */ + vuint32_t CIM67:1; /* Channel 67 mask register */ + vuint32_t CIM66:1; /* Channel 66 mask register */ + vuint32_t CIM65:1; /* Channel 65 mask register */ + vuint32_t CIM64:1; /* Channel 64 mask register */ + } B; + } ADC_CIMR2_32B_tag; + + typedef union { /* Watchdog Threshold interrupt status register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */ + vuint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */ + vuint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */ + vuint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */ + vuint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */ + vuint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */ + vuint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */ + vuint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTISR_32B_tag; + + typedef union { /* Watchdog interrupt MASK register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */ + vuint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */ + vuint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */ + vuint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */ + vuint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */ + vuint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */ + vuint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */ + vuint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTIMR_32B_tag; + + typedef union { /* DMAE register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t DCLR:1; /* DMA clear sequence enable */ + vuint32_t DMAEN:1; /* DMA global enable */ + } B; + } ADC_DMAE_32B_tag; + + typedef union { /* DMA REGISTER 0 */ + vuint32_t R; + struct { + vuint32_t DMA31:1; /* Channel 31 DMA Enable */ + vuint32_t DMA30:1; /* Channel 30 DMA Enable */ + vuint32_t DMA29:1; /* Channel 29 DMA Enable */ + vuint32_t DMA28:1; /* Channel 28 DMA Enable */ + vuint32_t DMA27:1; /* Channel 27 DMA Enable */ + vuint32_t DMA26:1; /* Channel 26 DMA Enable */ + vuint32_t DMA25:1; /* Channel 25 DMA Enable */ + vuint32_t DMA24:1; /* Channel 24 DMA Enable */ + vuint32_t DMA23:1; /* Channel 23 DMA Enable */ + vuint32_t DMA22:1; /* Channel 22 DMA Enable */ + vuint32_t DMA21:1; /* Channel 21 DMA Enable */ + vuint32_t DMA20:1; /* Channel 20 DMA Enable */ + vuint32_t DMA19:1; /* Channel 19 DMA Enable */ + vuint32_t DMA18:1; /* Channel 18 DMA Enable */ + vuint32_t DMA17:1; /* Channel 17 DMA Enable */ + vuint32_t DMA16:1; /* Channel 16 DMA Enable */ + vuint32_t DMA15:1; /* Channel 15 DMA Enable */ + vuint32_t DMA14:1; /* Channel 14 DMA Enable */ + vuint32_t DMA13:1; /* Channel 13 DMA Enable */ + vuint32_t DMA12:1; /* Channel 12 DMA Enable */ + vuint32_t DMA11:1; /* Channel 11 DMA Enable */ + vuint32_t DMA10:1; /* Channel 10 DMA Enable */ + vuint32_t DMA9:1; /* Channel 9 DMA Enable */ + vuint32_t DMA8:1; /* Channel 8 DMA Enable */ + vuint32_t DMA7:1; /* Channel 7 DMA Enable */ + vuint32_t DMA6:1; /* Channel 6 DMA Enable */ + vuint32_t DMA5:1; /* Channel 5 DMA Enable */ + vuint32_t DMA4:1; /* Channel 4 DMA Enable */ + vuint32_t DMA3:1; /* Channel 3 DMA Enable */ + vuint32_t DMA2:1; /* Channel 2 DMA Enable */ + vuint32_t DMA1:1; /* Channel 1 DMA Enable */ + vuint32_t DMA0:1; /* Channel 0 DMA Enable */ + } B; + } ADC_DMAR0_32B_tag; + + typedef union { /* DMA REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t DMA63:1; /* Channel 63 DMA Enable */ + vuint32_t DMA62:1; /* Channel 62 DMA Enable */ + vuint32_t DMA61:1; /* Channel 61 DMA Enable */ + vuint32_t DMA60:1; /* Channel 60 DMA Enable */ + vuint32_t DMA59:1; /* Channel 59 DMA Enable */ + vuint32_t DMA58:1; /* Channel 58 DMA Enable */ + vuint32_t DMA57:1; /* Channel 57 DMA Enable */ + vuint32_t DMA56:1; /* Channel 56 DMA Enable */ + vuint32_t DMA55:1; /* Channel 55 DMA Enable */ + vuint32_t DMA54:1; /* Channel 54 DMA Enable */ + vuint32_t DMA53:1; /* Channel 53 DMA Enable */ + vuint32_t DMA52:1; /* Channel 52 DMA Enable */ + vuint32_t DMA51:1; /* Channel 51 DMA Enable */ + vuint32_t DMA50:1; /* Channel 50 DMA Enable */ + vuint32_t DMA49:1; /* Channel 49 DMA Enable */ + vuint32_t DMA48:1; /* Channel 48 DMA Enable */ + vuint32_t DMA47:1; /* Channel 47 DMA Enable */ + vuint32_t DMA46:1; /* Channel 46 DMA Enable */ + vuint32_t DMA45:1; /* Channel 45 DMA Enable */ + vuint32_t DMA44:1; /* Channel 44 DMA Enable */ + vuint32_t DMA43:1; /* Channel 43 DMA Enable */ + vuint32_t DMA42:1; /* Channel 42 DMA Enable */ + vuint32_t DMA41:1; /* Channel 41 DMA Enable */ + vuint32_t DMA40:1; /* Channel 40 DMA Enable */ + vuint32_t DMA39:1; /* Channel 39 DMA Enable */ + vuint32_t DMA38:1; /* Channel 38 DMA Enable */ + vuint32_t DMA37:1; /* Channel 37 DMA Enable */ + vuint32_t DMA36:1; /* Channel 36 DMA Enable */ + vuint32_t DMA35:1; /* Channel 35 DMA Enable */ + vuint32_t DMA34:1; /* Channel 34 DMA Enable */ + vuint32_t DMA33:1; /* Channel 33 DMA Enable */ + vuint32_t DMA32:1; /* Channel 32 DMA Enable */ + } B; + } ADC_DMAR1_32B_tag; + + typedef union { /* DMA REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t DMA95:1; /* Channel 95 DMA Enable */ + vuint32_t DMA94:1; /* Channel 94 DMA Enable */ + vuint32_t DMA93:1; /* Channel 93 DMA Enable */ + vuint32_t DMA92:1; /* Channel 92 DMA Enable */ + vuint32_t DMA91:1; /* Channel 91 DMA Enable */ + vuint32_t DMA90:1; /* Channel 90 DMA Enable */ + vuint32_t DMA89:1; /* Channel 89 DMA Enable */ + vuint32_t DMA88:1; /* Channel 88 DMA Enable */ + vuint32_t DMA87:1; /* Channel 87 DMA Enable */ + vuint32_t DMA86:1; /* Channel 86 DMA Enable */ + vuint32_t DMA85:1; /* Channel 85 DMA Enable */ + vuint32_t DMA84:1; /* Channel 84 DMA Enable */ + vuint32_t DMA83:1; /* Channel 83 DMA Enable */ + vuint32_t DMA82:1; /* Channel 82 DMA Enable */ + vuint32_t DMA81:1; /* Channel 81 DMA Enable */ + vuint32_t DMA80:1; /* Channel 80 DMA Enable */ + vuint32_t DMA79:1; /* Channel 79 DMA Enable */ + vuint32_t DMA78:1; /* Channel 78 DMA Enable */ + vuint32_t DMA77:1; /* Channel 77 DMA Enable */ + vuint32_t DMA76:1; /* Channel 76 DMA Enable */ + vuint32_t DMA75:1; /* Channel 75 DMA Enable */ + vuint32_t DMA74:1; /* Channel 74 DMA Enable */ + vuint32_t DMA73:1; /* Channel 73 DMA Enable */ + vuint32_t DMA72:1; /* Channel 72 DMA Enable */ + vuint32_t DMA71:1; /* Channel 71 DMA Enable */ + vuint32_t DMA70:1; /* Channel 70 DMA Enable */ + vuint32_t DMA69:1; /* Channel 69 DMA Enable */ + vuint32_t DMA68:1; /* Channel 68 DMA Enable */ + vuint32_t DMA67:1; /* Channel 67 DMA Enable */ + vuint32_t DMA66:1; /* Channel 66 DMA Enable */ + vuint32_t DMA65:1; /* Channel 65 DMA Enable */ + vuint32_t DMA64:1; /* Channel 64 DMA Enable */ + } B; + } ADC_DMAR2_32B_tag; + + + /* Register layout for all registers TRC... */ + + typedef union { /* Threshold Control register C */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t THREN:1; /* Threshold enable */ + vuint32_t THRINV:1; /* invert the output pin */ + vuint32_t THROP:1; /* output pin register */ + vuint32_t:6; + vuint32_t THRCH:7; /* Choose channel for threshold register */ + } B; + } ADC_TRC_32B_tag; + + + /* Register layout for all registers THRHLR... */ + + typedef union { /* Upper Threshold register */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR_32B_tag; + + + /* Register layout for all registers THRALT... */ + + typedef union { /* alternate Upper Threshold register */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t THRH:10; /* high threshold value s */ + vuint32_t:6; + vuint32_t THRL:10; /* low threshold value s */ + } B; + } ADC_THRALT_32B_tag; + + typedef union { /* PRESAMPLING CONTROL REGISTER */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */ + vuint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */ + vuint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */ +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t PRECONV:1; /* Presampled value */ +#else + vuint32_t PREONCE:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_PSCR_32B_tag; + + typedef union { /* Presampling Register 0 */ + vuint32_t R; + struct { + vuint32_t PRES31:1; /* Channel 31 Presampling Enable */ + vuint32_t PRES30:1; /* Channel 30 Presampling Enable */ + vuint32_t PRES29:1; /* Channel 29 Presampling Enable */ + vuint32_t PRES28:1; /* Channel 28 Presampling Enable */ + vuint32_t PRES27:1; /* Channel 27 Presampling Enable */ + vuint32_t PRES26:1; /* Channel 26 Presampling Enable */ + vuint32_t PRES25:1; /* Channel 25 Presampling Enable */ + vuint32_t PRES24:1; /* Channel 24 Presampling Enable */ + vuint32_t PRES23:1; /* Channel 23 Presampling Enable */ + vuint32_t PRES22:1; /* Channel 22 Presampling Enable */ + vuint32_t PRES21:1; /* Channel 21 Presampling Enable */ + vuint32_t PRES20:1; /* Channel 20 Presampling Enable */ + vuint32_t PRES19:1; /* Channel 19 Presampling Enable */ + vuint32_t PRES18:1; /* Channel 18 Presampling Enable */ + vuint32_t PRES17:1; /* Channel 17 Presampling Enable */ + vuint32_t PRES16:1; /* Channel 16 Presampling Enable */ + vuint32_t PRES15:1; /* Channel 15 Presampling Enable */ + vuint32_t PRES14:1; /* Channel 14 Presampling Enable */ + vuint32_t PRES13:1; /* Channel 13 Presampling Enable */ + vuint32_t PRES12:1; /* Channel 12 Presampling Enable */ + vuint32_t PRES11:1; /* Channel 11 Presampling Enable */ + vuint32_t PRES10:1; /* Channel 10 Presampling Enable */ + vuint32_t PRES9:1; /* Channel 9 Presampling Enable */ + vuint32_t PRES8:1; /* Channel 8 Presampling Enable */ + vuint32_t PRES7:1; /* Channel 7 Presampling Enable */ + vuint32_t PRES6:1; /* Channel 6 Presampling Enable */ + vuint32_t PRES5:1; /* Channel 5 Presampling Enable */ + vuint32_t PRES4:1; /* Channel 4 Presampling Enable */ + vuint32_t PRES3:1; /* Channel 3 Presampling Enable */ + vuint32_t PRES2:1; /* Channel 2 Presampling Enable */ + vuint32_t PRES1:1; /* Channel 1presampling Enable */ + vuint32_t PRES0:1; /* Channel 0 Presampling Enable */ + } B; + } ADC_PSR0_32B_tag; + + typedef union { /* Presampling REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t PRES63:1; /* Channel 63 Presampling Enable */ + vuint32_t PRES62:1; /* Channel 62 Presampling Enable */ + vuint32_t PRES61:1; /* Channel 61 Presampling Enable */ + vuint32_t PRES60:1; /* Channel 60 Presampling Enable */ + vuint32_t PRES59:1; /* Channel 59 Presampling Enable */ + vuint32_t PRES58:1; /* Channel 58 Presampling Enable */ + vuint32_t PRES57:1; /* Channel 57 Presampling Enable */ + vuint32_t PRES56:1; /* Channel 56 Presampling Enable */ + vuint32_t PRES55:1; /* Channel 55 Presampling Enable */ + vuint32_t PRES54:1; /* Channel 54 Presampling Enable */ + vuint32_t PRES53:1; /* Channel 53 Presampling Enable */ + vuint32_t PRES52:1; /* Channel 52 Presampling Enable */ + vuint32_t PRES51:1; /* Channel 51 Presampling Enable */ + vuint32_t PRES50:1; /* Channel 50 Presampling Enable */ + vuint32_t PRES49:1; /* Channel 49 Presampling Enable */ + vuint32_t PRES48:1; /* Channel 48 Presampling Enable */ + vuint32_t PRES47:1; /* Channel 47 Presampling Enable */ + vuint32_t PRES46:1; /* Channel 46 Presampling Enable */ + vuint32_t PRES45:1; /* Channel 45 Presampling Enable */ + vuint32_t PRES44:1; /* Channel 44 Presampling Enable */ + vuint32_t PRES43:1; /* Channel 43 Presampling Enable */ + vuint32_t PRES42:1; /* Channel 42 Presampling Enable */ + vuint32_t PRES41:1; /* Channel 41 Presampling Enable */ + vuint32_t PRES40:1; /* Channel 40 Presampling Enable */ + vuint32_t PRES39:1; /* Channel 39 Presampling Enable */ + vuint32_t PRES38:1; /* Channel 38 Presampling Enable */ + vuint32_t PRES37:1; /* Channel 37 Presampling Enable */ + vuint32_t PRES36:1; /* Channel 36 Presampling Enable */ + vuint32_t PRES35:1; /* Channel 35 Presampling Enable */ + vuint32_t PRES34:1; /* Channel 34 Presampling Enable */ + vuint32_t PRES33:1; /* Channel 33 Presampling Enable */ + vuint32_t PRES32:1; /* Channel 32 Presampling Enable */ + } B; + } ADC_PSR1_32B_tag; + + typedef union { /* Presampling REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t PRES95:1; /* Channel 95 Presampling Enable */ + vuint32_t PRES94:1; /* Channel 94 Presampling Enable */ + vuint32_t PRES93:1; /* Channel 93 Presampling Enable */ + vuint32_t PRES92:1; /* Channel 92 Presampling Enable */ + vuint32_t PRES91:1; /* Channel 91 Presampling Enable */ + vuint32_t PRES90:1; /* Channel 90 Presampling Enable */ + vuint32_t PRES89:1; /* Channel 89 Presampling Enable */ + vuint32_t PRES88:1; /* Channel 88 Presampling Enable */ + vuint32_t PRES87:1; /* Channel 87 Presampling Enable */ + vuint32_t PRES86:1; /* Channel 86 Presampling Enable */ + vuint32_t PRES85:1; /* Channel 85 Presampling Enable */ + vuint32_t PRES84:1; /* Channel 84 Presampling Enable */ + vuint32_t PRES83:1; /* Channel 83 Presampling Enable */ + vuint32_t PRES82:1; /* Channel 82 Presampling Enable */ + vuint32_t PRES81:1; /* Channel 81 Presampling Enable */ + vuint32_t PRES80:1; /* Channel 80 Presampling Enable */ + vuint32_t PRES79:1; /* Channel 79 Presampling Enable */ + vuint32_t PRES78:1; /* Channel 78 Presampling Enable */ + vuint32_t PRES77:1; /* Channel 77 Presampling Enable */ + vuint32_t PRES76:1; /* Channel 76 Presampling Enable */ + vuint32_t PRES75:1; /* Channel 75 Presampling Enable */ + vuint32_t PRES74:1; /* Channel 74 Presampling Enable */ + vuint32_t PRES73:1; /* Channel 73 Presampling Enable */ + vuint32_t PRES72:1; /* Channel 72 Presampling Enable */ + vuint32_t PRES71:1; /* Channel 71 Presampling Enable */ + vuint32_t PRES70:1; /* Channel 70 Presampling Enable */ + vuint32_t PRES69:1; /* Channel 69 Presampling Enable */ + vuint32_t PRES68:1; /* Channel 68 Presampling Enable */ + vuint32_t PRES67:1; /* Channel 67 Presampling Enable */ + vuint32_t PRES66:1; /* Channel 66 Presampling Enable */ + vuint32_t PRES65:1; /* Channel 65 Presampling Enable */ + vuint32_t PRES64:1; /* Channel 64 Presampling Enable */ + } B; + } ADC_PSR2_32B_tag; + + + /* Register layout for all registers CTR... */ + + typedef union { /* conversion timing register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */ + vuint32_t:1; + vuint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */ + vuint32_t:1; + vuint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */ + vuint32_t:1; +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */ +#else + vuint32_t INPSAMP:8; +#endif + } B; + } ADC_CTR_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */ + vuint32_t R; + struct { + vuint32_t CH31:1; /* Channel 31 Normal Sampling Enable */ + vuint32_t CH30:1; /* Channel 30 Normal Sampling Enable */ + vuint32_t CH29:1; /* Channel 29 Normal Sampling Enable */ + vuint32_t CH28:1; /* Channel 28 Normal Sampling Enable */ + vuint32_t CH27:1; /* Channel 27 Normal Sampling Enable */ + vuint32_t CH26:1; /* Channel 26 Normal Sampling Enable */ + vuint32_t CH25:1; /* Channel 25 Normal Sampling Enable */ + vuint32_t CH24:1; /* Channel 24 Normal Sampling Enable */ + vuint32_t CH23:1; /* Channel 23 Normal Sampling Enable */ + vuint32_t CH22:1; /* Channel 22 Normal Sampling Enable */ + vuint32_t CH21:1; /* Channel 21 Normal Sampling Enable */ + vuint32_t CH20:1; /* Channel 20 Normal Sampling Enable */ + vuint32_t CH19:1; /* Channel 19 Normal Sampling Enable */ + vuint32_t CH18:1; /* Channel 18 Normal Sampling Enable */ + vuint32_t CH17:1; /* Channel 17 Normal Sampling Enable */ + vuint32_t CH16:1; /* Channel 16 Normal Sampling Enable */ + vuint32_t CH15:1; /* Channel 15 Normal Sampling Enable */ + vuint32_t CH14:1; /* Channel 14 Normal Sampling Enable */ + vuint32_t CH13:1; /* Channel 13 Normal Sampling Enable */ + vuint32_t CH12:1; /* Channel 12 Normal Sampling Enable */ + vuint32_t CH11:1; /* Channel 11 Normal Sampling Enable */ + vuint32_t CH10:1; /* Channel 10 Normal Sampling Enable */ + vuint32_t CH9:1; /* Channel 9 Normal Sampling Enable */ + vuint32_t CH8:1; /* Channel 8 Normal Sampling Enable */ + vuint32_t CH7:1; /* Channel 7 Normal Sampling Enable */ + vuint32_t CH6:1; /* Channel 6 Normal Sampling Enable */ + vuint32_t CH5:1; /* Channel 5 Normal Sampling Enable */ + vuint32_t CH4:1; /* Channel 4 Normal Sampling Enable */ + vuint32_t CH3:1; /* Channel 3 Normal Sampling Enable */ + vuint32_t CH2:1; /* Channel 2 Normal Sampling Enable */ + vuint32_t CH1:1; /* Channel 1 Normal Sampling Enable */ + vuint32_t CH0:1; /* Channel 0 Normal Sampling Enable */ + } B; + } ADC_NCMR0_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t CH63:1; /* Channel 63 Normal Sampling Enable */ + vuint32_t CH62:1; /* Channel 62 Normal Sampling Enable */ + vuint32_t CH61:1; /* Channel 61 Normal Sampling Enable */ + vuint32_t CH60:1; /* Channel 60 Normal Sampling Enable */ + vuint32_t CH59:1; /* Channel 59 Normal Sampling Enable */ + vuint32_t CH58:1; /* Channel 58 Normal Sampling Enable */ + vuint32_t CH57:1; /* Channel 57 Normal Sampling Enable */ + vuint32_t CH56:1; /* Channel 56 Normal Sampling Enable */ + vuint32_t CH55:1; /* Channel 55 Normal Sampling Enable */ + vuint32_t CH54:1; /* Channel 54 Normal Sampling Enable */ + vuint32_t CH53:1; /* Channel 53 Normal Sampling Enable */ + vuint32_t CH52:1; /* Channel 52 Normal Sampling Enable */ + vuint32_t CH51:1; /* Channel 51 Normal Sampling Enable */ + vuint32_t CH50:1; /* Channel 50 Normal Sampling Enable */ + vuint32_t CH49:1; /* Channel 49 Normal Sampling Enable */ + vuint32_t CH48:1; /* Channel 48 Normal Sampling Enable */ + vuint32_t CH47:1; /* Channel 47 Normal Sampling Enable */ + vuint32_t CH46:1; /* Channel 46 Normal Sampling Enable */ + vuint32_t CH45:1; /* Channel 45 Normal Sampling Enable */ + vuint32_t CH44:1; /* Channel 44 Normal Sampling Enable */ + vuint32_t CH43:1; /* Channel 43 Normal Sampling Enable */ + vuint32_t CH42:1; /* Channel 42 Normal Sampling Enable */ + vuint32_t CH41:1; /* Channel 41 Normal Sampling Enable */ + vuint32_t CH40:1; /* Channel 40 Normal Sampling Enable */ + vuint32_t CH39:1; /* Channel 39 Normal Sampling Enable */ + vuint32_t CH38:1; /* Channel 38 Normal Sampling Enable */ + vuint32_t CH37:1; /* Channel 37 Normal Sampling Enable */ + vuint32_t CH36:1; /* Channel 36 Normal Sampling Enable */ + vuint32_t CH35:1; /* Channel 35 Normal Sampling Enable */ + vuint32_t CH34:1; /* Channel 34 Normal Sampling Enable */ + vuint32_t CH33:1; /* Channel 33 Normal Sampling Enable */ + vuint32_t CH32:1; /* Channel 32 Normal Sampling Enable */ + } B; + } ADC_NCMR1_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t CH95:1; /* Channel 95 Normal Sampling Enable */ + vuint32_t CH94:1; /* Channel 94 Normal Sampling Enable */ + vuint32_t CH93:1; /* Channel 93 Normal Sampling Enable */ + vuint32_t CH92:1; /* Channel 92 Normal Sampling Enable */ + vuint32_t CH91:1; /* Channel 91 Normal Sampling Enable */ + vuint32_t CH90:1; /* Channel 90 Normal Sampling Enable */ + vuint32_t CH89:1; /* Channel 89 Normal Sampling Enable */ + vuint32_t CH88:1; /* Channel 88 Normal Sampling Enable */ + vuint32_t CH87:1; /* Channel 87 Normal Sampling Enable */ + vuint32_t CH86:1; /* Channel 86 Normal Sampling Enable */ + vuint32_t CH85:1; /* Channel 85 Normal Sampling Enable */ + vuint32_t CH84:1; /* Channel 84 Normal Sampling Enable */ + vuint32_t CH83:1; /* Channel 83 Normal Sampling Enable */ + vuint32_t CH82:1; /* Channel 82 Normal Sampling Enable */ + vuint32_t CH81:1; /* Channel 81 Normal Sampling Enable */ + vuint32_t CH80:1; /* Channel 80 Normal Sampling Enable */ + vuint32_t CH79:1; /* Channel 79 Normal Sampling Enable */ + vuint32_t CH78:1; /* Channel 78 Normal Sampling Enable */ + vuint32_t CH77:1; /* Channel 77 Normal Sampling Enable */ + vuint32_t CH76:1; /* Channel 76 Normal Sampling Enable */ + vuint32_t CH75:1; /* Channel 75 Normal Sampling Enable */ + vuint32_t CH74:1; /* Channel 74 Normal Sampling Enable */ + vuint32_t CH73:1; /* Channel 73 Normal Sampling Enable */ + vuint32_t CH72:1; /* Channel 72 Normal Sampling Enable */ + vuint32_t CH71:1; /* Channel 71 Normal Sampling Enable */ + vuint32_t CH70:1; /* Channel 70 Normal Sampling Enable */ + vuint32_t CH69:1; /* Channel 69 Normal Sampling Enable */ + vuint32_t CH68:1; /* Channel 68 Normal Sampling Enable */ + vuint32_t CH67:1; /* Channel 67 Normal Sampling Enable */ + vuint32_t CH66:1; /* Channel 66 Normal Sampling Enable */ + vuint32_t CH65:1; /* Channel 65 Normal Sampling Enable */ + vuint32_t CH64:1; /* Channel 64 Normal Sampling Enable */ + } B; + } ADC_NCMR2_32B_tag; + + typedef union { /* Injected Conversion Mask Register 0 */ + vuint32_t R; + struct { + vuint32_t CH31:1; /* Channel 31 Injected Sampling Enable */ + vuint32_t CH30:1; /* Channel 30 Injected Sampling Enable */ + vuint32_t CH29:1; /* Channel 29 Injected Sampling Enable */ + vuint32_t CH28:1; /* Channel 28 Injected Sampling Enable */ + vuint32_t CH27:1; /* Channel 27 Injected Sampling Enable */ + vuint32_t CH26:1; /* Channel 26 Injected Sampling Enable */ + vuint32_t CH25:1; /* Channel 25 Injected Sampling Enable */ + vuint32_t CH24:1; /* Channel 24 Injected Sampling Enable */ + vuint32_t CH23:1; /* Channel 23 Injected Sampling Enable */ + vuint32_t CH22:1; /* Channel 22 Injected Sampling Enable */ + vuint32_t CH21:1; /* Channel 21 Injected Sampling Enable */ + vuint32_t CH20:1; /* Channel 20 Injected Sampling Enable */ + vuint32_t CH19:1; /* Channel 19 Injected Sampling Enable */ + vuint32_t CH18:1; /* Channel 18 Injected Sampling Enable */ + vuint32_t CH17:1; /* Channel 17 Injected Sampling Enable */ + vuint32_t CH16:1; /* Channel 16 Injected Sampling Enable */ + vuint32_t CH15:1; /* Channel 15 Injected Sampling Enable */ + vuint32_t CH14:1; /* Channel 14 Injected Sampling Enable */ + vuint32_t CH13:1; /* Channel 13 Injected Sampling Enable */ + vuint32_t CH12:1; /* Channel 12 Injected Sampling Enable */ + vuint32_t CH11:1; /* Channel 11 Injected Sampling Enable */ + vuint32_t CH10:1; /* Channel 10 Injected Sampling Enable */ + vuint32_t CH9:1; /* Channel 9 Injected Sampling Enable */ + vuint32_t CH8:1; /* Channel 8 Injected Sampling Enable */ + vuint32_t CH7:1; /* Channel 7 Injected Sampling Enable */ + vuint32_t CH6:1; /* Channel 6 Injected Sampling Enable */ + vuint32_t CH5:1; /* Channel 5 Injected Sampling Enable */ + vuint32_t CH4:1; /* Channel 4 Injected Sampling Enable */ + vuint32_t CH3:1; /* Channel 3 Injected Sampling Enable */ + vuint32_t CH2:1; /* Channel 2 Injected Sampling Enable */ + vuint32_t CH1:1; /* Channel 1 injected Sampling Enable */ + vuint32_t CH0:1; /* Channel 0 injected Sampling Enable */ + } B; + } ADC_JCMR0_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t CH63:1; /* Channel 63 Injected Sampling Enable */ + vuint32_t CH62:1; /* Channel 62 Injected Sampling Enable */ + vuint32_t CH61:1; /* Channel 61 Injected Sampling Enable */ + vuint32_t CH60:1; /* Channel 60 Injected Sampling Enable */ + vuint32_t CH59:1; /* Channel 59 Injected Sampling Enable */ + vuint32_t CH58:1; /* Channel 58 Injected Sampling Enable */ + vuint32_t CH57:1; /* Channel 57 Injected Sampling Enable */ + vuint32_t CH56:1; /* Channel 56 Injected Sampling Enable */ + vuint32_t CH55:1; /* Channel 55 Injected Sampling Enable */ + vuint32_t CH54:1; /* Channel 54 Injected Sampling Enable */ + vuint32_t CH53:1; /* Channel 53 Injected Sampling Enable */ + vuint32_t CH52:1; /* Channel 52 Injected Sampling Enable */ + vuint32_t CH51:1; /* Channel 51 Injected Sampling Enable */ + vuint32_t CH50:1; /* Channel 50 Injected Sampling Enable */ + vuint32_t CH49:1; /* Channel 49 Injected Sampling Enable */ + vuint32_t CH48:1; /* Channel 48 Injected Sampling Enable */ + vuint32_t CH47:1; /* Channel 47 Injected Sampling Enable */ + vuint32_t CH46:1; /* Channel 46 Injected Sampling Enable */ + vuint32_t CH45:1; /* Channel 45 Injected Sampling Enable */ + vuint32_t CH44:1; /* Channel 44 Injected Sampling Enable */ + vuint32_t CH43:1; /* Channel 43 Injected Sampling Enable */ + vuint32_t CH42:1; /* Channel 42 Injected Sampling Enable */ + vuint32_t CH41:1; /* Channel 41 Injected Sampling Enable */ + vuint32_t CH40:1; /* Channel 40 Injected Sampling Enable */ + vuint32_t CH39:1; /* Channel 39 Injected Sampling Enable */ + vuint32_t CH38:1; /* Channel 38 Injected Sampling Enable */ + vuint32_t CH37:1; /* Channel 37 Injected Sampling Enable */ + vuint32_t CH36:1; /* Channel 36 Injected Sampling Enable */ + vuint32_t CH35:1; /* Channel 35 Injected Sampling Enable */ + vuint32_t CH34:1; /* Channel 34 Injected Sampling Enable */ + vuint32_t CH33:1; /* Channel 33 Injected Sampling Enable */ + vuint32_t CH32:1; /* Channel 32 Injected Sampling Enable */ + } B; + } ADC_JCMR1_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t CH95:1; /* Channel 95 Injected Sampling Enable */ + vuint32_t CH94:1; /* Channel 94 Injected Sampling Enable */ + vuint32_t CH93:1; /* Channel 93 Injected Sampling Enable */ + vuint32_t CH92:1; /* Channel 92 Injected Sampling Enable */ + vuint32_t CH91:1; /* Channel 91 Injected Sampling Enable */ + vuint32_t CH90:1; /* Channel 90 Injected Sampling Enable */ + vuint32_t CH89:1; /* Channel 89 Injected Sampling Enable */ + vuint32_t CH88:1; /* Channel 88 Injected Sampling Enable */ + vuint32_t CH87:1; /* Channel 87 Injected Sampling Enable */ + vuint32_t CH86:1; /* Channel 86 Injected Sampling Enable */ + vuint32_t CH85:1; /* Channel 85 Injected Sampling Enable */ + vuint32_t CH84:1; /* Channel 84 Injected Sampling Enable */ + vuint32_t CH83:1; /* Channel 83 Injected Sampling Enable */ + vuint32_t CH82:1; /* Channel 82 Injected Sampling Enable */ + vuint32_t CH81:1; /* Channel 81 Injected Sampling Enable */ + vuint32_t CH80:1; /* Channel 80 Injected Sampling Enable */ + vuint32_t CH79:1; /* Channel 79 Injected Sampling Enable */ + vuint32_t CH78:1; /* Channel 78 Injected Sampling Enable */ + vuint32_t CH77:1; /* Channel 77 Injected Sampling Enable */ + vuint32_t CH76:1; /* Channel 76 Injected Sampling Enable */ + vuint32_t CH75:1; /* Channel 75 Injected Sampling Enable */ + vuint32_t CH74:1; /* Channel 74 Injected Sampling Enable */ + vuint32_t CH73:1; /* Channel 73 Injected Sampling Enable */ + vuint32_t CH72:1; /* Channel 72 Injected Sampling Enable */ + vuint32_t CH71:1; /* Channel 71 Injected Sampling Enable */ + vuint32_t CH70:1; /* Channel 70 Injected Sampling Enable */ + vuint32_t CH69:1; /* Channel 69 Injected Sampling Enable */ + vuint32_t CH68:1; /* Channel 68 Injected Sampling Enable */ + vuint32_t CH67:1; /* Channel 67 Injected Sampling Enable */ + vuint32_t CH66:1; /* Channel 66 Injected Sampling Enable */ + vuint32_t CH65:1; /* Channel 65 Injected Sampling Enable */ + vuint32_t CH64:1; /* Channel 64 Injected Sampling Enable */ + } B; + } ADC_JCMR2_32B_tag; + + typedef union { /* Offset Word Regsiter */ + vuint32_t R; + struct { + vuint32_t:15; + vuint32_t OFFSETLOAD:1; /* load_offset */ + vuint32_t:8; +#ifndef USE_FIELD_ALIASES_ADC + vuint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */ +#else + vuint32_t OFFSETWORD:8; +#endif + } B; + } ADC_OFFWR_32B_tag; + + typedef union { /* Decode Signal Delay Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t DSD:8; /* take into account the settling time of the external mux */ + } B; + } ADC_DSDR_32B_tag; + + typedef union { /* Power Down Dealy Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */ + } B; + } ADC_PDEDR_32B_tag; + + + /* Register layout for all registers CDR... */ + + typedef union { /* CHANNEL DATA REGS */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t VALID:1; /* validity of data */ + vuint32_t OVERW:1; /* overwrite data */ + vuint32_t RESULT:2; /* reflects mode conversion */ + vuint32_t:6; + vuint32_t CDATA:10; /* Channel 0 converted data */ + } B; + } ADC_CDR_32B_tag; + + typedef union { /* Upper Threshold register 4 is not contiguous to 3 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR4_32B_tag; + + typedef union { /* Upper Threshold register 5 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR5_32B_tag; + + typedef union { /* Upper Threshold register 6 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR6_32B_tag; + + typedef union { /* Upper Threshold register 7 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR7_32B_tag; + + typedef union { /* Upper Threshold register 8 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR8_32B_tag; + + typedef union { /* Upper Threshold register 9 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR9_32B_tag; + + typedef union { /* Upper Threshold register 10 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR10_32B_tag; + + typedef union { /* Upper Threshold register 11 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR11_32B_tag; + + typedef union { /* Upper Threshold register 12 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR12_32B_tag; + + typedef union { /* Upper Threshold register 13 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR13_32B_tag; + + typedef union { /* Upper Threshold register 14 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR14_32B_tag; + + typedef union { /* Upper Threshold register 15 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* high threshold value s */ + vuint32_t:4; + vuint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR15_32B_tag; + + + /* Register layout for all registers CWSELR... */ + + typedef union { /* Channel Watchdog Select register */ + vuint32_t R; + struct { + vuint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */ + vuint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */ + vuint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */ + vuint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */ + vuint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */ + vuint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */ + vuint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */ + vuint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */ + } B; + } ADC_CWSELR_32B_tag; + + + /* Register layout for all registers CWENR... */ + + typedef union { /* Channel Watchdog Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + vuint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + } B; + } ADC_CWENR_32B_tag; + + + /* Register layout for all registers AWORR... */ + + typedef union { /* Analog Watchdog Out of Range Register */ + vuint32_t R; + struct { + vuint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */ + vuint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */ + vuint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */ + vuint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */ + vuint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */ + vuint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */ + vuint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */ + vuint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */ + vuint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */ + vuint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */ + vuint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */ + vuint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */ + vuint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */ + vuint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */ + vuint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */ + vuint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */ + vuint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */ + vuint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */ + vuint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */ + vuint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */ + vuint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */ + vuint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */ + vuint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */ + vuint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */ + vuint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */ + vuint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */ + vuint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */ + vuint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */ + vuint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */ + vuint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */ + vuint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */ + vuint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */ + } B; + } ADC_AWORR_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */ + vuint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */ + vuint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */ + vuint32_t:5; + vuint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */ + vuint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */ + } B; + } ADC_STCR1_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t SERR:1; /* Error fault injection bit (write only) */ + vuint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */ + vuint32_t:1; + vuint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */ + vuint32_t:4; + vuint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */ + vuint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */ + vuint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */ + vuint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */ + vuint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */ + vuint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */ + vuint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */ + vuint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */ + vuint32_t:3; + vuint32_t EN:1; /* Self testing channel enable */ + vuint32_t:4; + vuint32_t FMA_C:1; /* Fault mapping for the algorithm C */ + vuint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */ + vuint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */ + } B; + } ADC_STCR2_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */ + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t ALG:2; /* Algorithm scheduling */ + vuint32_t:8; + } B; + } ADC_STCR3_32B_tag; + + typedef union { /* SELF TEST BAUD RATE REGISTER */ + vuint32_t R; + struct { + vuint32_t:13; + vuint32_t WDT:3; /* Watchdog timer value */ + vuint32_t:8; + vuint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */ + } B; + } ADC_STBRR_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t WDTERR:1; /* Watchdog timer error */ + vuint32_t OVERWR:1; /* Overwrite error */ + vuint32_t ST_EOC:1; /* Self test EOC bit */ + vuint32_t:4; + vuint32_t WDG_EOA_C:1; /* Algorithm C completed without error */ + vuint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */ + vuint32_t WDG_EOA_S:1; /* Algorithm S completed without error */ + vuint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */ + vuint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */ + vuint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */ + vuint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */ + vuint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */ + vuint32_t:1; + vuint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */ + vuint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */ + } B; + } ADC_STSR1_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t OVFL:1; /* Overflow bit */ + vuint32_t:3; + vuint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */ + vuint32_t:4; + vuint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */ + } B; + } ADC_STSR2_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 3 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */ + vuint32_t:4; + vuint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */ + } B; + } ADC_STSR3_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 4 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */ + vuint32_t:4; + vuint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */ + } B; + } ADC_STSR4_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 1 */ + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t VALID:1; /* Valid data */ + vuint32_t OVERWR:1; /* Overwrite data */ + vuint32_t:6; + vuint32_t TCDATA:12; /* Test channel converted data */ + } B; + } ADC_STDR1_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */ + vuint32_t VALID:1; /* Valid data */ + vuint32_t OVERWR:1; /* Overwrite data */ + vuint32_t:6; + vuint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */ + } B; + } ADC_STDR2_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + vuint32_t R; + struct { + vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */ + vuint32_t:2; + vuint32_t THRH:12; /* High threshold value for channel 0 */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for channel 0 */ + } B; + } ADC_STAW0R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + vuint32_t R; + struct { + vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + vuint32_t:3; + vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1AR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1BR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + vuint32_t R; + struct { + vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + vuint32_t:19; + vuint32_t THRL:12; /* Low threshold value for channel */ + } B; + } ADC_STAW2R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + vuint32_t R; + struct { + vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */ + vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */ + vuint32_t:2; + vuint32_t THRH:12; /* High threshold value for channel 3 */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for channel 3 */ + } B; + } ADC_STAW3R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + vuint32_t R; + struct { + vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */ + vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */ + vuint32_t:2; + vuint32_t THRH:12; /* High threshold value for channel 4 */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for channel 4 */ + } B; + } ADC_STAW4R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t THRH:12; /* High threshold value for algorithm C */ + vuint32_t:4; + vuint32_t THRL:12; /* Low threshold value for algorithm C */ + } B; + } ADC_STAW5R_32B_tag; + + + + typedef struct ADC_struct_tag { /* start of ADC_tag */ + /* module configuration register */ + ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* module status register */ + ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */ + int8_t ADC_reserved_0008[8]; + /* Interrupt status register */ + ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + union { + ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */ + + struct { + /* CHANNEL PENDING REGISTER 0 */ + ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */ + /* CHANNEL PENDING REGISTER 1 */ + ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */ + /* CHANNEL PENDING REGISTER 2 */ + ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */ + }; + + }; + /* interrupt mask register */ + ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */ + union { + ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */ + + struct { + /* CHANNEL INTERRUPT MASK REGISTER 0 */ + ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 1 */ + ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 2 */ + ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */ + }; + + }; + /* Watchdog Threshold interrupt status register */ + ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */ + /* Watchdog interrupt MASK register */ + ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */ + int8_t ADC_reserved_0038[8]; + /* DMAE register */ + ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */ + union { + ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */ + + struct { + /* DMA REGISTER 0 */ + ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */ + /* DMA REGISTER 1 */ + ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */ + /* DMA REGISTER 2 */ + ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */ + }; + + }; + union { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */ + + struct { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */ + ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */ + ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */ + ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */ + }; + + }; + union { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */ + + struct { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */ + }; + + }; + union { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */ + + struct { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */ + ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */ + ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */ + ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */ + }; + + }; + /* PRESAMPLING CONTROL REGISTER */ + ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */ + union { + ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */ + + struct { + /* Presampling Register 0 */ + ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */ + /* Presampling REGISTER 1 */ + ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */ + /* Presampling REGISTER 2 */ + ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_0090_C[4]; + union { + /* conversion timing register */ + ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */ + + struct { + /* conversion timing register */ + ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */ + ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */ + ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00A0_C[4]; + union { + ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */ + + struct { + /* NORMAL CONVERSION MASK REGISTER 0 */ + ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 1 */ + ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 2 */ + ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00B0_C[4]; + union { + ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */ + + struct { + /* Injected Conversion Mask Register 0 */ + ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 1 */ + ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 2 */ + ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* Offset Word Regsiter */ + ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */ + /* Decode Signal Delay Register */ + ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */ + /* Power Down Dealy Register */ + ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */ + int8_t ADC_reserved_00CC_C[52]; + union { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */ + + struct { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */ + ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */ + ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */ + ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */ + ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */ + ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */ + ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */ + ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */ + ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */ + ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */ + ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */ + ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */ + ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */ + ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */ + ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */ + ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */ + ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */ + ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */ + ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */ + ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */ + ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */ + ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */ + ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */ + ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */ + ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */ + ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */ + ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */ + ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */ + ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */ + ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */ + ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */ + ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */ + ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */ + ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */ + ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */ + ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */ + ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */ + ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */ + ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */ + ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */ + ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */ + ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */ + ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */ + ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */ + ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */ + ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */ + ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */ + ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */ + ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */ + ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */ + ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */ + ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */ + ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */ + ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */ + ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */ + ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */ + ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */ + ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */ + ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */ + ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */ + ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */ + ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */ + ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */ + ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */ + ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */ + ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */ + ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */ + ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */ + ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */ + ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */ + ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */ + ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */ + ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */ + ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */ + ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */ + ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */ + ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */ + ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */ + ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */ + ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */ + ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */ + ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */ + ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */ + ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */ + ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */ + ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */ + ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */ + ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */ + ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */ + ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */ + ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */ + ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */ + ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */ + ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */ + ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */ + ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */ + }; + + }; + /* Upper Threshold register 4 is not contiguous to 3 */ + ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */ + /* Upper Threshold register 5 */ + ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */ + /* Upper Threshold register 6 */ + ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */ + /* Upper Threshold register 7 */ + ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */ + /* Upper Threshold register 8 */ + ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */ + /* Upper Threshold register 9 */ + ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */ + /* Upper Threshold register 10 */ + ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */ + /* Upper Threshold register 11 */ + ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */ + /* Upper Threshold register 12 */ + ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */ + /* Upper Threshold register 13 */ + ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */ + /* Upper Threshold register 14 */ + ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */ + /* Upper Threshold register 15 */ + ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */ + union { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */ + + struct { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */ + }; + + }; + union { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */ + + struct { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */ + ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */ + ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02EC_C[4]; + union { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */ + + struct { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */ + ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */ + ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02FC[68]; + /* SELF TEST CONFIGURATION REGISTER 1 */ + ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 2 */ + ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 3 */ + ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */ + /* SELF TEST BAUD RATE REGISTER */ + ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */ + /* SELF TEST STATUS REGISTER 1 */ + ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */ + /* SELF TEST STATUS REGISTER 2 */ + ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */ + /* SELF TEST STATUS REGISTER 3 */ + ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */ + /* SELF TEST STATUS REGISTER 4 */ + ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */ + int8_t ADC_reserved_0360[16]; + /* SELF TEST DATA REGISTER 1 */ + ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */ + /* SELF TEST DATA REGISTER 2 */ + ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */ + int8_t ADC_reserved_0378[8]; + /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */ + } ADC_tag; + + +#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL) +#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL) + + + +/****************************************************************/ +/* */ +/* Module: CTU */ +/* */ +/****************************************************************/ + + typedef union { /* Trigger Generator Subunit Input Selection register */ + vuint32_t R; + struct { + vuint32_t I15_FE:1; /* ext_signal Falling Edge */ + vuint32_t I15_RE:1; /* ext_signal Rising Edge */ + vuint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */ + vuint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */ + vuint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */ + vuint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */ + vuint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */ + vuint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */ + vuint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */ + vuint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */ + vuint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */ + vuint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */ + vuint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */ + vuint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */ + vuint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */ + vuint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */ + vuint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */ + vuint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */ + vuint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */ + vuint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */ + vuint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */ + vuint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */ + vuint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */ + vuint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */ + vuint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */ + vuint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */ + vuint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */ + vuint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */ + vuint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */ + vuint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */ + vuint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */ + vuint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */ + } B; + } CTU_TGSISR_32B_tag; + + typedef union { /* Trigger Generator Subunit Control Register */ + vuint16_t R; + struct { + vuint16_t:7; +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t ET_TM:1; /* Toggle Mode Enable */ +#else + vuint16_t ETTM:1; /* deprecated name - please avoid */ +#endif + vuint16_t PRES:2; /* TGS Prescaler Selection */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */ +#else + vuint16_t MRSSM:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t TGS_M:1; /* Trigger Generator Subunit Mode */ +#else + vuint16_t TGSM:1; /* deprecated name - please avoid */ +#endif + } B; + } CTU_TGSCR_16B_tag; + + typedef union { /* */ + vuint16_t R; + } CTU_TCR_16B_tag; + + typedef union { /* TGS Counter Compare Register */ + vuint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + vuint16_t TGSCCV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCCR_16B_tag; + + typedef union { /* TGS Counter Reload Register */ + vuint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + vuint16_t TGSCRV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCRR_16B_tag; + + typedef union { /* Commands List Control Register 1 */ + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T3INDEX:5; /* Trigger 3 First Command address */ + vuint32_t:3; + vuint32_t T2INDEX:5; /* Trigger 2 First Command address */ + vuint32_t:3; + vuint32_t T1INDEX:5; /* Trigger 1 First Command address */ + vuint32_t:3; + vuint32_t T0INDEX:5; /* Trigger 0 First Command address */ + } B; + } CTU_CLCR1_32B_tag; + + typedef union { /* Commands List Control Register 2 */ + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t T7INDEX:5; /* Trigger 7 First Command address */ + vuint32_t:3; + vuint32_t T6INDEX:5; /* Trigger 6 First Command address */ + vuint32_t:3; + vuint32_t T5INDEX:5; /* Trigger 5 First Command address */ + vuint32_t:3; + vuint32_t T4INDEX:5; /* Trigger 4 First Command address */ + } B; + } CTU_CLCR2_32B_tag; + + typedef union { /* Trigger Handler Control Register 1 */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t T3_E:1; /* Trigger 3 enable */ + vuint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */ + vuint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */ + vuint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */ + vuint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */ + vuint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */ + vuint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */ + vuint32_t:1; + vuint32_t T2_E:1; /* Trigger 2 enable */ + vuint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */ + vuint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */ + vuint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */ + vuint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */ + vuint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */ + vuint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */ + vuint32_t:1; + vuint32_t T1_E:1; /* Trigger 1 enable */ + vuint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */ + vuint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */ + vuint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */ + vuint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */ + vuint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */ + vuint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */ + vuint32_t:1; + vuint32_t T0_E:1; /* Trigger 0 enable */ + vuint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */ + vuint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */ + vuint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */ + vuint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */ + vuint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */ + vuint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */ + } B; + } CTU_THCR1_32B_tag; + + typedef union { /* Trigger Handler Control Register 2 */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t T7_E:1; /* Trigger 7 enable */ + vuint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */ + vuint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */ + vuint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */ + vuint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */ + vuint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */ + vuint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */ + vuint32_t:1; + vuint32_t T6_E:1; /* Trigger 6 enable */ + vuint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */ + vuint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */ + vuint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */ + vuint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */ + vuint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */ + vuint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */ + vuint32_t:1; + vuint32_t T5_E:1; /* Trigger 5 enable */ + vuint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */ + vuint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */ + vuint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */ + vuint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */ + vuint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */ + vuint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */ + vuint32_t:1; + vuint32_t T4_E:1; /* Trigger 4 enable */ + vuint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */ + vuint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */ + vuint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */ + vuint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */ + vuint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */ + vuint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */ + } B; + } CTU_THCR2_32B_tag; + + + /* Register layout for all registers CLR_DCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + vuint16_t R; + struct { + vuint16_t CIR:1; /* Command Interrupt Request */ + vuint16_t LC:1; /* Last Command */ + vuint16_t CMS:1; /* Conversion Mode Selection */ + vuint16_t FIFO:3; /* FIFO for ADC A/B */ + vuint16_t:1; + vuint16_t CHB:4; /* ADC unit B channel number */ + vuint16_t:1; + vuint16_t CHA:4; /* ADC unit A channel number */ + } B; + } CTU_CLR_DCM_16B_tag; + + + /* Register layout for all registers CLR_SCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + vuint16_t R; + struct { + vuint16_t CIR:1; /* Command Interrupt Request */ + vuint16_t LC:1; /* Last Command */ + vuint16_t CMS:1; /* Conversion Mode Selection */ + vuint16_t FIFO:3; /* FIFO for ADC A/B */ + vuint16_t:4; + vuint16_t SU:1; /* Selection ADC Unit */ + vuint16_t:1; + vuint16_t CH:4; /* ADC unit channel number */ + } B; + } CTU_CLR_SCM_16B_tag; + + + /* Register layout for all registers CLR... */ + + + typedef union { /* Control Register */ + vuint16_t R; + struct { + vuint16_t EMPTY_CLR7:1; /* Empty Clear 7 */ + vuint16_t EMPTY_CLR6:1; /* Empty Clear 6 */ + vuint16_t EMPTY_CLR5:1; /* Empty Clear 5 */ + vuint16_t EMPTY_CLR4:1; /* Empty Clear 4 */ + vuint16_t EMPTY_CLR3:1; /* Empty Clear 3 */ + vuint16_t EMPTY_CLR2:1; /* Empty Clear 2 */ + vuint16_t EMPTY_CLR1:1; /* Empty Clear 1 */ + vuint16_t EMPTY_CLR0:1; /* Empty Clear 0 */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */ +#else + vuint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */ +#else + vuint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */ +#else + vuint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */ +#else + vuint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */ +#else + vuint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */ +#else + vuint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */ +#else + vuint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */ +#else + vuint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */ +#endif + } B; + } CTU_CR_16B_tag; + + typedef union { /* Control Register FIFO */ + vuint32_t R; + struct { + vuint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */ + vuint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */ + vuint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */ + vuint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */ + vuint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */ + } B; + } CTU_FCR_32B_tag; + + typedef union { /* Threshold 1 Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD3:8; /* Threshlod FIFO 3 */ +#else + vuint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD2:8; /* Threshlod FIFO 2 */ +#else + vuint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD1:8; /* Threshlod FIFO 1 */ +#else + vuint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD0:8; /* Threshlod FIFO 0 */ +#else + vuint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */ +#endif + } B; + } CTU_TH1_32B_tag; + + typedef union { /* Threshold 2 Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD7:8; /* Threshlod FIFO 7 */ +#else + vuint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD6:8; /* Threshlod FIFO 6 */ +#else + vuint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD5:8; /* Threshlod FIFO 5 */ +#else + vuint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint32_t TRESHOLD4:8; /* Threshlod FIFO 4 */ +#else + vuint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */ +#endif + } B; + } CTU_TH2_32B_tag; + + typedef union { /* Status Register */ + vuint32_t R; + struct { + vuint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */ + vuint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */ + vuint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */ + vuint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */ + vuint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */ + vuint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */ + vuint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */ + vuint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */ + vuint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */ + vuint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */ + vuint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */ + vuint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */ + vuint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */ + vuint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */ + vuint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */ + vuint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */ + vuint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */ + vuint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */ + } B; + } CTU_STS_32B_tag; + + + /* Register layout for all registers FR... */ + + typedef union { /* FIFO Right Aligned register */ + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t ADC:1; /* ADC Unit */ + vuint32_t N_CH:4; /* Number Channel */ + vuint32_t:4; + vuint32_t DATA:12; /* Data Fifo */ + } B; + } CTU_FR_32B_tag; + + + /* Register layout for all registers FL... */ + + typedef union { /* FIFO Left Aligned register */ + vuint32_t R; + struct { + vuint32_t:11; + vuint32_t ADC:1; /* ADC Unit */ + vuint32_t N_CH:4; /* Number Channel */ + vuint32_t:1; + vuint32_t DATA:12; /* Data Fifo */ + vuint32_t:3; + } B; + } CTU_FL_32B_tag; + + typedef union { /* CTU Error Flag Register */ + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t CS:1; /* Counter Status */ + vuint16_t ET_OE:1; /* ExtTrigger Generation Overrun */ + vuint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */ + vuint16_t T4_OE:1; /* Timer4 Generation Overrun */ + vuint16_t T3_OE:1; /* Timer3 Generation Overrun */ + vuint16_t T2_OE:1; /* Timer2 Generation Overrun */ + vuint16_t T1_OE:1; /* Timer1 Generation Overrun */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t ADC_OE:1; /* ADC Command Generation Overrun */ +#else + vuint16_t ADCOE:1; /* ADC Command Generation Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t TGS_OSM:1; /* TGS Overrun */ +#else + vuint16_t TGSOSM:1; /* TGS Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_O:1; /* MRS Overrun */ +#else + vuint16_t MRSO:1; /* TGS Overrun */ +#endif + vuint16_t ICE:1; /* Invalid Command Error */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t SM_TO:1; /* Trigger Overrun */ +#else + vuint16_t SMTO:1; /* Trigger Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_RE:1; /* MRS Reload Error */ +#else + vuint16_t MRSRE:1; /* MRS Reload Error */ +#endif + } B; + } CTU_CTUEFR_16B_tag; + + typedef union { /* CTU Interrupt Flag Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t S_E_B:1; /* Slice time OK */ + vuint16_t S_E_A:1; /* Slice time OK */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t ADC_I:1; /* ADC Command Interrupt Flag */ +#else + vuint16_t ADC:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T7_I:1; /* Trigger 7 Interrupt Flag */ +#else + vuint16_t T7:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T6_I:1; /* Trigger 6 Interrupt Flag */ +#else + vuint16_t T6:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T5_I:1; /* Trigger 5 Interrupt Flag */ +#else + vuint16_t T5:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T4_I:1; /* Trigger 4 Interrupt Flag */ +#else + vuint16_t T4:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T3_I:1; /* Trigger 3 Interrupt Flag */ +#else + vuint16_t T3:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T2_I:1; /* Trigger 2 Interrupt Flag */ +#else + vuint16_t T2:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T1_I:1; /* Trigger 1 Interrupt Flag */ +#else + vuint16_t T1:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T0_I:1; /* Trigger 0 Interrupt Flag */ +#else + vuint16_t T0:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_I:1; /* MRS Interrupt Flag */ +#else + vuint16_t MRS:1; +#endif + } B; + } CTU_CTUIFR_16B_tag; + + typedef union { /* CTU Interrupt/DMA Register */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T7_I:1; /* Trigger 7 Interrupt Enable */ +#else + vuint16_t T7IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T6_I:1; /* Trigger 6 Interrupt Enable */ +#else + vuint16_t T6IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T5_I:1; /* Trigger 5 Interrupt Enable */ +#else + vuint16_t T5IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T4_I:1; /* Trigger 4 Interrupt Enable */ +#else + vuint16_t T4IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T3_I:1; /* Trigger 3 Interrupt Enable */ +#else + vuint16_t T3IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T2_I:1; /* Trigger 2 Interrupt Enable */ +#else + vuint16_t T2IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T1_I:1; /* Trigger 1 Interrupt Enable */ +#else + vuint16_t T1IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T0_I:1; /* Trigger 0 Interrupt Enable */ +#else + vuint16_t T0IE:1; +#endif + vuint16_t:2; + vuint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */ + vuint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */ + vuint16_t DMA_DE:1; /* DMA and gre bit */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_DMAE:1; /* DMA Transfer Enable */ +#else + vuint16_t MRSDMAE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_IE:1; /* MRS Interrupt Enable */ +#else + vuint16_t MRSIE:1; +#endif + vuint16_t IEE:1; /* Interrupt Error Enable */ + } B; + } CTU_CTUIR_16B_tag; + + typedef union { /* Control On-Time Register */ + vuint16_t R; + struct { + vuint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */ +#else + vuint16_t COTR:8; +#endif + } B; + } CTU_COTR_16B_tag; + + typedef union { /* CTU Control Register */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T7_SG:1; /* Trigger 7 Software Generated */ +#else + vuint16_t T7SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T6_SG:1; /* Trigger 6 Software Generated */ +#else + vuint16_t T6SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T5_SG:1; /* Trigger 5 Software Generated */ +#else + vuint16_t T5SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T4_SG:1; /* Trigger 4 Software Generated */ +#else + vuint16_t T4SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T3_SG:1; /* Trigger 3 Software Generated */ +#else + vuint16_t T3SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T2_SG:1; /* Trigger 2 Software Generated */ +#else + vuint16_t T2SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T1_SG:1; /* Trigger 1 Software Generated */ +#else + vuint16_t T1SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t T0_SG:1; /* Trigger 0 Software Generated */ +#else + vuint16_t T0SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */ +#else + vuint16_t CTUADCRESET:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t CTU_ODIS:1; /* CTU Output Disable */ +#else + vuint16_t CTUODIS:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t FILTER_EN:1; /* Synchronize Filter Register value */ +#else + vuint16_t FILTERENABLE:1; +#endif + vuint16_t CGRE:1; /* Clear GRE */ + vuint16_t FGRE:1; /* GRE Flag */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t MRS_SG:1; /* MRS Software Generated */ +#else + vuint16_t MRSSG:1; +#endif + vuint16_t GRE:1; /* General Reload Enable */ +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t TGSISR_RE:1; /* TGSISR Reload Enable */ +#else + vuint16_t TGSISRRE:1; +#endif + } B; + } CTU_CTUCR_16B_tag; + + typedef union { /* CTU Digital Filter Register */ + vuint16_t R; + struct { + vuint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + vuint16_t FILTER_VALUE:8; /* Filter Value */ +#else + vuint16_t FILTERVALUE:8; /* deprecated name - please avoid */ +#endif + } B; + } CTU_FILTER_16B_tag; + + typedef union { /* CTU Expected A Value Register */ + vuint16_t R; + struct { + vuint16_t EXPECTED_A_VALUE:16; /* Expected A Value */ + } B; + } CTU_EXPECTED_A_16B_tag; + + typedef union { /* CTU Expected B Value Register */ + vuint16_t R; + struct { + vuint16_t EXPECTED_B_VALUE:16; /* Expected B Value */ + } B; + } CTU_EXPECTED_B_16B_tag; + + typedef union { /* CTU Counter Range Register */ + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */ + } B; + } CTU_CNT_RANGE_16B_tag; + + + /* Register layout for generated register(s) FRA... */ + + typedef union { /* */ + vuint32_t R; + } CTU_FRA_32B_tag; + + + /* Register layout for generated register(s) FLA... */ + + typedef union { /* */ + vuint32_t R; + } CTU_FLA_32B_tag; + + + + typedef struct CTU_struct_tag { /* start of CTU_tag */ + /* Trigger Generator Subunit Input Selection register */ + CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */ + /* Trigger Generator Subunit Control Register */ + CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */ + union { + CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */ + + struct { + CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */ + CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */ + CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */ + CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */ + CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */ + CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */ + CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */ + CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */ + }; + + }; + /* TGS Counter Compare Register */ + CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */ + /* TGS Counter Reload Register */ + CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */ + int8_t CTU_reserved_001A[2]; + /* Commands List Control Register 1 */ + CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */ + /* Commands List Control Register 2 */ + CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */ + /* Trigger Handler Control Register 1 */ + CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */ + /* Trigger Handler Control Register 2 */ + CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */ + union { + /* Command List Register. View: BIT13, BIT9 */ + CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */ + }; + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */ + }; + + }; + int8_t CTU_reserved_005C[16]; + /* Control Register */ + CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */ + int8_t CTU_reserved_006E[2]; + /* Control Register FIFO */ + CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */ + /* Threshold 1 Register */ + CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */ + /* Threshold 2 Register */ + CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */ + union { + /* Status Register */ + CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */ + + CTU_STS_32B_tag STATUS; /* deprecated - please avoid */ + + }; + union { + CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */ + CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */ + CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */ + CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */ + CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */ + CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */ + CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */ + CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */ + CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */ + CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */ + CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */ + CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */ + CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */ + CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */ + CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* CTU Error Flag Register */ + CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */ + /* CTU Interrupt Flag Register */ + CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */ + /* CTU Interrupt/DMA Register */ + CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */ + /* Control On-Time Register */ + CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */ + /* CTU Control Register */ + CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */ + union { + /* CTU Digital Filter Register */ + CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */ + + CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */ + + }; + /* CTU Expected A Value Register */ + CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */ + + /* CTU Expected B Value Register */ + CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */ + /* CTU Counter Range Register */ + CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */ + } CTU_tag; + + +#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcTIMER */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers COMP1... */ + + typedef union { /* Compare Register 1 */ + vuint16_t R; + struct { + vuint16_t COMP1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP1_16B_tag; + + + /* Register layout for all registers COMP2... */ + + typedef union { /* Compare Register 2 */ + vuint16_t R; + struct { + vuint16_t COMP2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP2_16B_tag; + + + /* Register layout for all registers CAPT1... */ + + typedef union { /* Capture Register 1 */ + vuint16_t R; + struct { + vuint16_t CAPT1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT1_16B_tag; + + + /* Register layout for all registers CAPT2... */ + + typedef union { /* Capture Register 2 */ + vuint16_t R; + struct { + vuint16_t CAPT2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT2_16B_tag; + + + /* Register layout for all registers LOAD... */ + + typedef union { /* Load Register */ + vuint16_t R; + struct { + vuint16_t LOAD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_LOAD_16B_tag; + + + /* Register layout for all registers HOLD... */ + + typedef union { /* Hold Register */ + vuint16_t R; + struct { + vuint16_t HOLD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_HOLD_16B_tag; + + + /* Register layout for all registers CNTR... */ + + typedef union { /* Counter Register */ + vuint16_t R; + struct { + vuint16_t CNTR:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CNTR_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + vuint16_t R; + struct { + vuint16_t CNTMODE:3; /* Count Mode */ + vuint16_t PRISRC:5; /* Primary Count Source */ + vuint16_t ONCE:1; /* Count Once */ + vuint16_t LENGTH:1; /* Count Length */ + vuint16_t DIR:1; /* Count Direction */ + vuint16_t SECSRC:5; /* Secondary Count Source */ + } B; + } mcTIMER_CTRL1_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control Register 2 */ + vuint16_t R; + struct { + vuint16_t OEN:1; /* Output Enable */ + vuint16_t RDNT:1; /* Redundant Channel Enable */ + vuint16_t INPUT:1; /* External Input Signal */ + vuint16_t VAL:1; /* Forced OFLAG Value */ + vuint16_t FORCE:1; /* Force the OFLAG output */ + vuint16_t COFRC:1; /* Co-channel OFLAG Force */ + vuint16_t COINIT:2; /* Co-channel Initialization */ + vuint16_t SIPS:1; /* Secondary Source Input Polarity Select */ + vuint16_t PIPS:1; /* Primary Source Input Polarity Select */ + vuint16_t OPS:1; /* Output Polarity Select */ + vuint16_t MSTR:1; /* Master Mode */ + vuint16_t OUTMODE:4; /* Output Mode */ + } B; + } mcTIMER_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL3... */ + + typedef union { /* Control Register 3 */ + vuint16_t R; + struct { + vuint16_t STPEN:1; /* Stop Action Enable */ + vuint16_t ROC:2; /* Reload On Capture */ + vuint16_t FMODE:1; /* Fault Safing Mode */ + vuint16_t FDIS:4; /* Fault Disable Mask */ + vuint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */ + vuint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */ + vuint16_t DBGEN:2; /* Debug Actions Enable */ + } B; + } mcTIMER_CTRL3_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t WDF:1; /* Watchdog Time-out Flag */ + vuint16_t RCF:1; /* Redundant Channel Flag */ + vuint16_t ICF2:1; /* Input Capture 2 Flag */ + vuint16_t ICF1:1; /* Input Capture 1 Flag */ + vuint16_t IEHF:1; /* Input Edge High Flag */ + vuint16_t IELF:1; /* Input Edge Low Flag */ + vuint16_t TOF:1; /* Timer Overflow Flag */ + vuint16_t TCF2:1; /* Timer Compare 2 Flag */ + vuint16_t TCF1:1; /* Timer Compare 1 Flag */ + vuint16_t TCF:1; /* Timer Compare Flag */ + } B; + } mcTIMER_STS_16B_tag; + + + /* Register layout for all registers INTDMA... */ + + typedef union { /* Interrupt and DMA Enable Register */ + vuint16_t R; + struct { + vuint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */ + vuint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */ + vuint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */ + vuint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */ + vuint16_t:2; + vuint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */ + vuint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */ + vuint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */ + vuint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */ + vuint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */ + vuint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */ + vuint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */ + vuint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */ + vuint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */ + vuint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */ + } B; + } mcTIMER_INTDMA_16B_tag; + + + /* Register layout for all registers CMPLD1... */ + + typedef union { /* Comparator Load Register 1 */ + vuint16_t R; + struct { + vuint16_t CMPLD1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD1_16B_tag; + + + /* Register layout for all registers CMPLD2... */ + + typedef union { /* Comparator Load Register 2 */ + vuint16_t R; + struct { + vuint16_t CMPLD2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD2_16B_tag; + + + /* Register layout for all registers CCCTRL... */ + + typedef union { /* Compare and Capture Control Register */ + vuint16_t R; + struct { + vuint16_t CLC2:3; /* Compare Load Control 2 */ + vuint16_t CLC1:3; /* Compare Load Control 1 */ + vuint16_t CMPMODE:2; /* Compare Mode */ + vuint16_t CPT2MODE:2; /* Capture 2 Mode Control */ + vuint16_t CPT1MODE:2; /* Capture 1 Mode Control */ + vuint16_t CFWM:2; /* Capture FIFO Water Mark */ + vuint16_t ONESHOT:1; /* One Shot Capture Mode */ + vuint16_t ARM:1; /* Arm Capture */ + } B; + } mcTIMER_CCCTRL_16B_tag; + + + /* Register layout for all registers FILT... */ + + typedef union { /* Input Filter Register */ + vuint16_t R; + struct { + vuint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + vuint16_t FILT_CNT:3; /* Input Filter Sample Count */ +#else + vuint16_t FILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + vuint16_t FILT_PER:8; /* Input Filter Sample Period */ +#else + vuint16_t FILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FILT_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + vuint16_t R; + struct { + vuint16_t WDTOL:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOL_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + vuint16_t R; + struct { + vuint16_t WDTOH:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOH_16B_tag; + + typedef union { /* Fault Control Register */ + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t FTEST:1; /* Fault Test */ + vuint16_t FIE:4; /* Fault Interrupt Enable */ + vuint16_t:4; + vuint16_t FLVL:4; /* Fault Active Logic Level */ + } B; + } mcTIMER_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t FFPIN:4; /* Filtered Fault Pin */ + vuint16_t:4; + vuint16_t FFLAG:4; /* Fault Flag */ + } B; + } mcTIMER_FSTS_16B_tag; + + typedef union { /* Fault Filter Registers */ + vuint16_t R; + struct { + vuint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + vuint16_t FFPIN:3; /* Fault Filter Sample Count */ +#else + vuint16_t FFILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + vuint16_t FFILT_PER:8; /* Fault Filter Sample Period */ +#else + vuint16_t FFILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FFILT_16B_tag; + + typedef union { /* Channel Enable Registers */ + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t ENBL:8; /* Timer Channel Enable */ + } B; + } mcTIMER_ENBL_16B_tag; + + typedef union { /* DMA Request 0 Select Registers */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t DREQ0V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ0_16B_tag; + + typedef union { /* DMA Request 1 Select Registers */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t DREQ1V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ1_16B_tag; + + typedef union { /* DMA Request 2 Select Registers */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t DREQ2V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ2_16B_tag; + + typedef union { /* DMA Request 3 Select Registers */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t DREQ3V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ3_16B_tag; + + + /* Register layout for generated register(s) DREQ... */ + + typedef union { /* */ + vuint16_t R; + } mcTIMER_DREQ_16B_tag; + + + typedef struct mcTIMER_CHANNEL_struct_tag { + + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */ + union { + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */ + mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */ + /* Status Register */ + mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */ + + } mcTIMER_CHANNEL_tag; + + + typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */ + union { + /* Register set CHANNEL */ + mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */ + + struct { + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */ + }; + + }; + int8_t mcTIMER_reserved_00C0[64]; + /* Watchdog Time-out Register */ + mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */ + /* Watchdog Time-out Register */ + mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */ + /* Fault Control Register */ + mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */ + /* Fault Status Register */ + mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */ + /* Fault Filter Registers */ + mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */ + int8_t mcTIMER_reserved_010A[2]; + /* Channel Enable Registers */ + mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */ + int8_t mcTIMER_reserved_010E_C[2]; + union { + mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */ + + struct { + /* DMA Request 0 Select Registers */ + mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */ + /* DMA Request 1 Select Registers */ + mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */ + /* DMA Request 2 Select Registers */ + mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */ + /* DMA Request 3 Select Registers */ + mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */ + }; + + }; + } mcTIMER_tag; + + +#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL) +#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL) +#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcPWM */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CNT... */ + + typedef union { /* Counter Register */ + vuint16_t R; + } mcPWM_CNT_16B_tag; + + + /* Register layout for all registers INIT... */ + + typedef union { /* Initial Counter Register */ + vuint16_t R; + } mcPWM_INIT_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control 2 Register */ + vuint16_t R; + struct { + vuint16_t DBGEN:1; /* Debug Enable */ + vuint16_t WAITEN:1; /* Wait Enable */ + vuint16_t INDEP:1; /* Independent or Complementary Pair Operation */ +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t PWM23_INIT:1; /* PWM23 Initial Value */ +#else + vuint16_t PWMA_INIT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t PWM45_INIT:1; /* PWM23 Initial Value */ +#else + vuint16_t PWMB_INIT:1; /* deprecated name - please avoid */ +#endif + vuint16_t PWMX_INIT:1; /* PWMX Initial Value */ + vuint16_t INIT_SEL:2; /* Initialization Control Select */ + vuint16_t FRCEN:1; /* Force Initialization enable */ + vuint16_t FORCE:1; /* Force Initialization */ + vuint16_t FORCE_SEL:3; /* Force Source Select */ + vuint16_t RELOAD_SEL:1; /* Reload Source Select */ + vuint16_t CLK_SEL:2; /* Clock Source Select */ + } B; + } mcPWM_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + vuint16_t R; + struct { + vuint16_t LDFQ:4; /* Load Frequency */ + vuint16_t HALF:1; /* Half Cycle Reload */ + vuint16_t FULL:1; /* Full Cycle Reload */ + vuint16_t DT:2; /* Deadtime */ + vuint16_t:1; + vuint16_t PRSC:3; /* Prescaler */ + vuint16_t:1; + vuint16_t LDMOD:1; /* Load Mode Select */ + vuint16_t:1; +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t DBL_EN:1; /* Double Switching Enable */ +#else + vuint16_t DBLEN:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_CTRL1_16B_tag; + + + /* Register layout for all registers VAL_0... */ + + typedef union { /* Value Register 0 */ + vuint16_t R; + } mcPWM_VAL_0_16B_tag; + + + /* Register layout for all registers VAL_1... */ + + typedef union { /* Value Register 1 */ + vuint16_t R; + } mcPWM_VAL_1_16B_tag; + + + /* Register layout for all registers VAL_2... */ + + typedef union { /* Value Register 2 */ + vuint16_t R; + } mcPWM_VAL_2_16B_tag; + + + /* Register layout for all registers VAL_3... */ + + typedef union { /* Value Register 3 */ + vuint16_t R; + } mcPWM_VAL_3_16B_tag; + + + /* Register layout for all registers VAL_4... */ + + typedef union { /* Value Register 4 */ + vuint16_t R; + } mcPWM_VAL_4_16B_tag; + + + /* Register layout for all registers VAL_5... */ + + typedef union { /* Value Register 5 */ + vuint16_t R; + } mcPWM_VAL_5_16B_tag; + + + /* Register layout for all registers FRACA... */ + + typedef union { /* Fractional Delay Register A */ + vuint16_t R; + struct { + vuint16_t FRACA_EN:1; /* Fractional Delay Enable */ + vuint16_t:10; + vuint16_t FRACA_DLY:5; /* Fractional Delay Value */ + } B; + } mcPWM_FRACA_16B_tag; + + + /* Register layout for all registers FRACB... */ + + typedef union { /* Fractional Delay Register B */ + vuint16_t R; + struct { + vuint16_t FRACA_EN:1; /* Fractional Delay Enable */ + vuint16_t:10; + vuint16_t FRACA_DLY:5; /* Fractional Delay Value */ + } B; + } mcPWM_FRACB_16B_tag; + + + /* Register layout for all registers OCTRL... */ + + typedef union { /* Output Control Register */ + vuint16_t R; + struct { + vuint16_t PWMA_IN:1; /* PWMA Input */ + vuint16_t PWMB_IN:1; /* PWMB Input */ + vuint16_t PWMX_IN:1; /* PWMX Input */ + vuint16_t:2; + vuint16_t POLA:1; /* PWMA Output Polarity */ + vuint16_t POLB:1; /* PWMB Output Polarity */ + vuint16_t POLX:1; /* PWMX Output Polarity */ + vuint16_t:2; + vuint16_t PWMAFS:2; /* PWMA Fault State */ + vuint16_t PWMBFS:2; /* PWMB Fault State */ + vuint16_t PWMXFS:2; /* PWMX Fault State */ + } B; + } mcPWM_OCTRL_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t RUF:1; /* Registers Updated Flag */ + vuint16_t REF:1; /* Reload Error Flag */ + vuint16_t RF:1; /* Reload Flag */ + vuint16_t CFA1:1; /* Capture Flag A1 */ + vuint16_t CFA0:1; /* Capture Flag A0 */ + vuint16_t CFB1:1; /* Capture Flag B1 */ + vuint16_t CFB0:1; /* Capture Flag B0 */ + vuint16_t CFX1:1; /* Capture Flag X1 */ + vuint16_t CFX0:1; /* Capture Flag X0 */ + vuint16_t CMPF:6; /* Compare Flags */ + } B; + } mcPWM_STS_16B_tag; + + + /* Register layout for all registers INTEN... */ + + typedef union { /* Interrupt Enable Registers */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t REIE:1; /* Reload Error Interrupt Enable */ + vuint16_t RIE:1; /* Reload Interrupt Enable */ + vuint16_t CA1IE:1; /* Capture A1 Interrupt Enable */ + vuint16_t CA0IE:1; /* Capture A0 Interrupt Enable */ + vuint16_t CB1IE:1; /* Capture B1 Interrupt Enable */ + vuint16_t CB0IE:1; /* Capture B0 Interrupt Enable */ + vuint16_t CX1IE:1; /* Capture X1 Interrupt Enable */ + vuint16_t CX0IE:1; /* Capture X0 Interrupt Enable */ + vuint16_t CMPIE:6; /* Compare Interrupt Enables */ + } B; + } mcPWM_INTEN_16B_tag; + + + /* Register layout for all registers DMAEN... */ + + typedef union { /* DMA Enable Registers */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t VALDE:1; /* Value Register DMA Enable */ + vuint16_t FAND:1; /* FIFO Watermark AND Control */ + vuint16_t CAPTDE:2; /* Capture DMA Enable Source Select */ + vuint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */ + vuint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */ + vuint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */ + vuint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */ + vuint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */ + vuint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */ + } B; + } mcPWM_DMAEN_16B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* Output Trigger Control Registers */ + vuint16_t R; + struct { + vuint16_t:10; + vuint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */ + } B; + } mcPWM_TCTRL_16B_tag; + + + /* Register layout for all registers DISMAP... */ + + typedef union { /* Fault Disable Mapping Registers */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t DISX:4; /* PWMX Fault Disable Mask */ + vuint16_t DISB:4; /* PWMB Fault Disable Mask */ + vuint16_t DISA:4; /* PWMA Fault Disable Mask */ + } B; + } mcPWM_DISMAP_16B_tag; + + + /* Register layout for all registers DTCNT0... */ + + typedef union { /* Deadtime Count Register 0 */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t DTCNT0:11; /* Deadtime Count Register 0 */ + } B; + } mcPWM_DTCNT0_16B_tag; + + + /* Register layout for all registers DTCNT1... */ + + typedef union { /* Deadtime Count Register 1 */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t DTCNT1:11; /* Deadtime Count Register 1 */ + } B; + } mcPWM_DTCNT1_16B_tag; + + + /* Register layout for all registers CAPTCTRLA... */ + + typedef union { /* Capture Control A Register */ + vuint16_t R; + struct { + vuint16_t CA1CNT:3; /* Capture A1 FIFO Word Count */ + vuint16_t CA0CNT:3; /* Capture A0 FIFO Word Count */ + vuint16_t CFAWM:2; /* Capture A FIFOs Water Mark */ + vuint16_t EDGCNTAEN:1; /* Edge Counter A Enable */ + vuint16_t INPSELA:1; /* Input Select A */ + vuint16_t EDGA1:2; /* Edge A 1 */ + vuint16_t EDGA0:2; /* Edge A 0 */ + vuint16_t ONESHOTA:1; /* One Shot Mode A */ + vuint16_t ARMA:1; /* Arm A */ + } B; + } mcPWM_CAPTCTRLA_16B_tag; + + + /* Register layout for all registers CAPTCMPA... */ + + typedef union { /* Capture Compare A Register */ + vuint16_t R; + struct { + vuint16_t EDGCNTA:8; /* Edge Counter A */ + vuint16_t EDGCMPA:8; /* Edge Compare A */ + } B; + } mcPWM_CAPTCMPA_16B_tag; + + + /* Register layout for all registers CAPTCTRLB... */ + + typedef union { /* Capture Control B Register */ + vuint16_t R; + struct { + vuint16_t CB1CNT:3; /* Capture B1 FIFO Word Count */ + vuint16_t CB0CNT:3; /* Capture B0 FIFO Word Count */ + vuint16_t CFBWM:2; /* Capture B FIFOs Water Mark */ + vuint16_t EDGCNTBEN:1; /* Edge Counter B Enable */ + vuint16_t INPSELB:1; /* Input Select B */ + vuint16_t EDGB1:2; /* Edge B 1 */ + vuint16_t EDGB0:2; /* Edge B 0 */ + vuint16_t ONESHOTB:1; /* One Shot Mode B */ + vuint16_t ARMB:1; /* Arm B */ + } B; + } mcPWM_CAPTCTRLB_16B_tag; + + + /* Register layout for all registers CAPTCMPB... */ + + typedef union { /* Capture Compare B Register */ + vuint16_t R; + struct { + vuint16_t EDGCNTB:8; /* Edge Counter B */ + vuint16_t EDGCMPB:8; /* Edge Compare B */ + } B; + } mcPWM_CAPTCMPB_16B_tag; + + + /* Register layout for all registers CAPTCTRLX... */ + + typedef union { /* Capture Control X Register */ + vuint16_t R; + struct { + vuint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */ + vuint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */ + vuint16_t CFXWM:2; /* Capture X FIFOs Water Mark */ +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t EDGCNTXEN:1; /* Edge Counter X Enable */ +#else + vuint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t INPSELX:1; /* Input Select X */ +#else + vuint16_t INP_SELX:1; /* deprecated name - please avoid */ +#endif + vuint16_t EDGX1:2; /* Edge X 1 */ + vuint16_t EDGX0:2; /* Edge X 0 */ + vuint16_t ONESHOTX:1; /* One Shot Mode X */ + vuint16_t ARMX:1; /* Arm X */ + } B; + } mcPWM_CAPTCTRLX_16B_tag; + + + /* Register layout for all registers CAPTCMPX... */ + + typedef union { /* Capture Compare X Register */ + vuint16_t R; + struct { + vuint16_t EDGCNTX:8; /* Edge Counter X */ + vuint16_t EDGCMPX:8; /* Edge Compare X */ + } B; + } mcPWM_CAPTCMPX_16B_tag; + + + /* Register layout for all registers CVAL0... */ + + typedef union { /* Capture Value 0 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL0:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL0_16B_tag; + + + /* Register layout for all registers CVAL0CYC... */ + + typedef union { /* Capture Value 0 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */ + } B; + } mcPWM_CVAL0CYC_16B_tag; + + + /* Register layout for all registers CVAL1... */ + + typedef union { /* Capture Value 1 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL1:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL1_16B_tag; + + + /* Register layout for all registers CVAL1CYC... */ + + typedef union { /* Capture Value 1 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */ + } B; + } mcPWM_CVAL1CYC_16B_tag; + + + /* Register layout for all registers CVAL2... */ + + typedef union { /* Capture Value 2 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL2:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL2_16B_tag; + + + /* Register layout for all registers CVAL2CYC... */ + + typedef union { /* Capture Value 2 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL2CYC:4; /* Capture Value 2 Cycle */ + } B; + } mcPWM_CVAL2CYC_16B_tag; + + + /* Register layout for all registers CVAL3... */ + + typedef union { /* Capture Value 3 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL3:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL3_16B_tag; + + + /* Register layout for all registers CVAL3CYC... */ + + typedef union { /* Capture Value 3 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */ + } B; + } mcPWM_CVAL3CYC_16B_tag; + + + /* Register layout for all registers CVAL4... */ + + typedef union { /* Capture Value 4 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL4:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL4_16B_tag; + + + /* Register layout for all registers CVAL4CYC... */ + + typedef union { /* Capture Value 4 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */ + } B; + } mcPWM_CVAL4CYC_16B_tag; + + + /* Register layout for all registers CVAL5... */ + + typedef union { /* Capture Value 5 Register */ + vuint16_t R; + struct { + vuint16_t CAPTVAL5:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL5_16B_tag; + + + /* Register layout for all registers CVAL5CYC... */ + + typedef union { /* Capture Value 5 Cycle Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */ + } B; + } mcPWM_CVAL5CYC_16B_tag; + + typedef union { /* Output Enable Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t PWMA_EN:4; /* PWMA Output Enables */ + vuint16_t PWMB_EN:4; /* PWMB Output Enables */ + vuint16_t PWMX_EN:4; /* PWMX Output Enables */ + } B; + } mcPWM_OUTEN_16B_tag; + + typedef union { /* Mask Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t MASKA:4; /* PWMA Masks */ + vuint16_t MASKB:4; /* PWMB Masks */ + vuint16_t MASKX:4; /* PWMX Masks */ + } B; + } mcPWM_MASK_16B_tag; + + typedef union { /* Software Controlled Output Register */ + vuint16_t R; + struct { + vuint16_t:8; +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT23_3:1; /* Software Controlled Output 23_3 */ +#else + vuint16_t OUTA_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT45_3:1; /* Software Controlled Output 45_3 */ +#else + vuint16_t OUTB_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT23_2:1; /* Software Controlled Output 23_2 */ +#else + vuint16_t OUTA_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT45_2:1; /* Software Controlled Output 45_2 */ +#else + vuint16_t OUTB_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT23_1:1; /* Software Controlled Output 23_1 */ +#else + vuint16_t OUTA_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT45_1:1; /* Software Controlled Output 45_1 */ +#else + vuint16_t OUTB_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT23_0:1; /* Software Controlled Output 23_0 */ +#else + vuint16_t OUTA_0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t OUT45_0:1; /* Software Controlled Output 45_0 */ +#else + vuint16_t OUTB_0:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_SWCOUT_16B_tag; + + typedef union { /* Deadtime Source Select Register */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL23_3:2; /* PWM23_3 Control Select */ +#else + vuint16_t SELA_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL45_3:2; /* PWM45_3 Control Select */ +#else + vuint16_t SELB_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL23_2:2; /* PWM23_2 Control Select */ +#else + vuint16_t SELA_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL45_2:2; /* PWM45_2 Control Select */ +#else + vuint16_t SELB_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL23_1:2; /* PWM23_1 Control Select */ +#else + vuint16_t SELA_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL45_1:2; /* PWM45_1 Control Select */ +#else + vuint16_t SELB_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL23_0:2; /* PWM23_0 Control Select */ +#else + vuint16_t SELA_0:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t SEL45_0:2; /* PWM45_0 Control Select */ +#else + vuint16_t SELB_0:2; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_DTSRCSEL_16B_tag; + + typedef union { /* Master Control Register */ + vuint16_t R; + struct { + vuint16_t IPOL:4; /* Current Polarity */ + vuint16_t RUN:4; /* Run */ +#ifndef USE_FIELD_ALIASES_mcPWM + vuint16_t CLOK:4; /* Clear Load Okay */ +#else + vuint16_t CLDOK:4; /* deprecated name - please avoid */ +#endif + vuint16_t LDOK:4; /* Load Okay */ + } B; + } mcPWM_MCTRL_16B_tag; + + typedef union { /* Fault Control Register */ + vuint16_t R; + struct { + vuint16_t FLVL:4; /* Fault Level */ + vuint16_t FAUTO:4; /* Automatic Fault Clearing */ + vuint16_t FSAFE:4; /* Fault Safety Mode */ + vuint16_t FIE:4; /* Fault Interrupt Enables */ + } B; + } mcPWM_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t FTEST:1; /* Fault Test */ + vuint16_t FFPIN:4; /* Filtered Fault Pins */ + vuint16_t:4; + vuint16_t FFLAG:4; /* Fault Flags */ + } B; + } mcPWM_FSTS_16B_tag; + + typedef union { /* Fault Filter Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FILT_CNT:3; /* Fault Filter Count */ + vuint16_t FILT_PER:8; /* Fault Filter Period */ + } B; + } mcPWM_FFILT_16B_tag; + + + /* Register layout for generated register(s) VAL... */ + + typedef union { /* */ + vuint16_t R; + } mcPWM_VAL_16B_tag; + + + typedef struct mcPWM_SUBMOD_struct_tag { + + /* Counter Register */ + mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */ + union { + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */ + mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Value Register 0 */ + + union { + + struct { + + mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */ + + }; + + mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */ + + }; + /* Fractional Delay Register A */ + mcPWM_FRACA_16B_tag FRACA; /* relative offset: 0x0014 */ + /* Fractional Delay Register B */ + mcPWM_FRACB_16B_tag FRACB; /* relative offset: 0x0016 */ + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */ + /* Status Register */ + mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */ + /* Capture Control A Register */ + mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA; /* relative offset: 0x0028 */ + union { + /* Capture Compare A Register */ + mcPWM_CAPTCMPA_16B_tag CAPTCMPA; /* relative offset: 0x002A */ + mcPWM_CAPTCMPA_16B_tag CAPTCOMPA; /* deprecated - please avoid */ + }; + /* Capture Control B Register */ + mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB; /* relative offset: 0x002C */ + union { + /* Capture Compare B Register */ + mcPWM_CAPTCMPB_16B_tag CAPTCMPB; /* relative offset: 0x002E */ + mcPWM_CAPTCMPB_16B_tag CAPTCOMPB; /* deprecated - please avoid */ + }; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */ + union { + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */ + mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */ + }; + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */ + union { + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */ + mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */ + }; + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */ + union { + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */ + mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */ + }; + /* Capture Value 2 Register */ + mcPWM_CVAL2_16B_tag CVAL2; /* relative offset: 0x003C */ + union { + /* Capture Value 2 Cycle Register */ + mcPWM_CVAL2CYC_16B_tag CVAL2CYC; /* relative offset: 0x003E */ + mcPWM_CVAL2CYC_16B_tag CVAL2C; /* deprecated - please avoid */ + }; + /* Capture Value 3 Register */ + mcPWM_CVAL3_16B_tag CVAL3; /* relative offset: 0x0040 */ + union { + /* Capture Value 3 Cycle Register */ + mcPWM_CVAL3CYC_16B_tag CVAL3CYC; /* relative offset: 0x0042 */ + mcPWM_CVAL3CYC_16B_tag CVAL3C; /* deprecated - please avoid */ + }; + /* Capture Value 4 Register */ + mcPWM_CVAL4_16B_tag CVAL4; /* relative offset: 0x0044 */ + union { + /* Capture Value 4 Cycle Register */ + mcPWM_CVAL4CYC_16B_tag CVAL4CYC; /* relative offset: 0x0046 */ + mcPWM_CVAL4CYC_16B_tag CVAL4C; /* deprecated - please avoid */ + }; + /* Capture Value 5 Register */ + mcPWM_CVAL5_16B_tag CVAL5; /* relative offset: 0x0048 */ + union { + /* Capture Value 5 Cycle Register */ + mcPWM_CVAL5CYC_16B_tag CVAL5CYC; /* relative offset: 0x004A */ + mcPWM_CVAL5CYC_16B_tag CVAL5C; /* deprecated - please avoid */ + }; + int8_t mcPWM_SUBMOD_reserved_004C[4]; + + } mcPWM_SUBMOD_tag; + + + typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */ + union { + /* Register set SUBMOD */ + mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */ + + struct { + /* Counter Register */ + mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */ + /* Fractional Delay Register A */ + mcPWM_FRACA_16B_tag FRACA0; /* offset: 0x0014 size: 16 bit */ + /* Fractional Delay Register B */ + mcPWM_FRACB_16B_tag FRACB0; /* offset: 0x0016 size: 16 bit */ + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */ + /* Capture Control A Register */ + mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA0; /* offset: 0x0028 size: 16 bit */ + /* Capture Compare A Register */ + mcPWM_CAPTCMPA_16B_tag CAPTCMPA0; /* offset: 0x002A size: 16 bit */ + /* Capture Control B Register */ + mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB0; /* offset: 0x002C size: 16 bit */ + /* Capture Compare B Register */ + mcPWM_CAPTCMPB_16B_tag CAPTCMPB0; /* offset: 0x002E size: 16 bit */ + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */ + /* Capture Value 2 Register */ + mcPWM_CVAL2_16B_tag CVAL20; /* offset: 0x003C size: 16 bit */ + /* Capture Value 2 Cycle Register */ + mcPWM_CVAL2CYC_16B_tag CVAL2CYC0; /* offset: 0x003E size: 16 bit */ + /* Capture Value 3 Register */ + mcPWM_CVAL3_16B_tag CVAL30; /* offset: 0x0040 size: 16 bit */ + /* Capture Value 3 Cycle Register */ + mcPWM_CVAL3CYC_16B_tag CVAL3CYC0; /* offset: 0x0042 size: 16 bit */ + /* Capture Value 4 Register */ + mcPWM_CVAL4_16B_tag CVAL40; /* offset: 0x0044 size: 16 bit */ + /* Capture Value 4 Cycle Register */ + mcPWM_CVAL4CYC_16B_tag CVAL4CYC0; /* offset: 0x0046 size: 16 bit */ + /* Capture Value 5 Register */ + mcPWM_CVAL5_16B_tag CVAL50; /* offset: 0x0048 size: 16 bit */ + /* Capture Value 5 Cycle Register */ + mcPWM_CVAL5CYC_16B_tag CVAL5CYC0; /* offset: 0x004A size: 16 bit */ + int8_t mcPWM_reserved_004C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */ + /* Fractional Delay Register A */ + mcPWM_FRACA_16B_tag FRACA1; /* offset: 0x0064 size: 16 bit */ + /* Fractional Delay Register B */ + mcPWM_FRACB_16B_tag FRACB1; /* offset: 0x0066 size: 16 bit */ + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */ + /* Capture Control A Register */ + mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA1; /* offset: 0x0078 size: 16 bit */ + /* Capture Compare A Register */ + mcPWM_CAPTCMPA_16B_tag CAPTCMPA1; /* offset: 0x007A size: 16 bit */ + /* Capture Control B Register */ + mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB1; /* offset: 0x007C size: 16 bit */ + /* Capture Compare B Register */ + mcPWM_CAPTCMPB_16B_tag CAPTCMPB1; /* offset: 0x007E size: 16 bit */ + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */ + /* Capture Value 2 Register */ + mcPWM_CVAL2_16B_tag CVAL21; /* offset: 0x008C size: 16 bit */ + /* Capture Value 2 Cycle Register */ + mcPWM_CVAL2CYC_16B_tag CVAL2CYC1; /* offset: 0x008E size: 16 bit */ + /* Capture Value 3 Register */ + mcPWM_CVAL3_16B_tag CVAL31; /* offset: 0x0090 size: 16 bit */ + /* Capture Value 3 Cycle Register */ + mcPWM_CVAL3CYC_16B_tag CVAL3CYC1; /* offset: 0x0092 size: 16 bit */ + /* Capture Value 4 Register */ + mcPWM_CVAL4_16B_tag CVAL41; /* offset: 0x0094 size: 16 bit */ + /* Capture Value 4 Cycle Register */ + mcPWM_CVAL4CYC_16B_tag CVAL4CYC1; /* offset: 0x0096 size: 16 bit */ + /* Capture Value 5 Register */ + mcPWM_CVAL5_16B_tag CVAL51; /* offset: 0x0098 size: 16 bit */ + /* Capture Value 5 Cycle Register */ + mcPWM_CVAL5CYC_16B_tag CVAL5CYC1; /* offset: 0x009A size: 16 bit */ + int8_t mcPWM_reserved_009C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */ + /* Fractional Delay Register A */ + mcPWM_FRACA_16B_tag FRACA2; /* offset: 0x00B4 size: 16 bit */ + /* Fractional Delay Register B */ + mcPWM_FRACB_16B_tag FRACB2; /* offset: 0x00B6 size: 16 bit */ + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */ + /* Capture Control A Register */ + mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA2; /* offset: 0x00C8 size: 16 bit */ + /* Capture Compare A Register */ + mcPWM_CAPTCMPA_16B_tag CAPTCMPA2; /* offset: 0x00CA size: 16 bit */ + /* Capture Control B Register */ + mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB2; /* offset: 0x00CC size: 16 bit */ + /* Capture Compare B Register */ + mcPWM_CAPTCMPB_16B_tag CAPTCMPB2; /* offset: 0x00CE size: 16 bit */ + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */ + /* Capture Value 2 Register */ + mcPWM_CVAL2_16B_tag CVAL22; /* offset: 0x00DC size: 16 bit */ + /* Capture Value 2 Cycle Register */ + mcPWM_CVAL2CYC_16B_tag CVAL2CYC2; /* offset: 0x00DE size: 16 bit */ + /* Capture Value 3 Register */ + mcPWM_CVAL3_16B_tag CVAL32; /* offset: 0x00E0 size: 16 bit */ + /* Capture Value 3 Cycle Register */ + mcPWM_CVAL3CYC_16B_tag CVAL3CYC2; /* offset: 0x00E2 size: 16 bit */ + /* Capture Value 4 Register */ + mcPWM_CVAL4_16B_tag CVAL42; /* offset: 0x00E4 size: 16 bit */ + /* Capture Value 4 Cycle Register */ + mcPWM_CVAL4CYC_16B_tag CVAL4CYC2; /* offset: 0x00E6 size: 16 bit */ + /* Capture Value 5 Register */ + mcPWM_CVAL5_16B_tag CVAL52; /* offset: 0x00E8 size: 16 bit */ + /* Capture Value 5 Cycle Register */ + mcPWM_CVAL5CYC_16B_tag CVAL5CYC2; /* offset: 0x00EA size: 16 bit */ + int8_t mcPWM_reserved_00EC_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */ + /* Fractional Delay Register A */ + mcPWM_FRACA_16B_tag FRACA3; /* offset: 0x0104 size: 16 bit */ + /* Fractional Delay Register B */ + mcPWM_FRACB_16B_tag FRACB3; /* offset: 0x0106 size: 16 bit */ + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */ + /* Capture Control A Register */ + mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA3; /* offset: 0x0118 size: 16 bit */ + /* Capture Compare A Register */ + mcPWM_CAPTCMPA_16B_tag CAPTCMPA3; /* offset: 0x011A size: 16 bit */ + /* Capture Control B Register */ + mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB3; /* offset: 0x011C size: 16 bit */ + /* Capture Compare B Register */ + mcPWM_CAPTCMPB_16B_tag CAPTCMPB3; /* offset: 0x011E size: 16 bit */ + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */ + /* Capture Value 2 Register */ + mcPWM_CVAL2_16B_tag CVAL23; /* offset: 0x012C size: 16 bit */ + /* Capture Value 2 Cycle Register */ + mcPWM_CVAL2CYC_16B_tag CVAL2CYC3; /* offset: 0x012E size: 16 bit */ + /* Capture Value 3 Register */ + mcPWM_CVAL3_16B_tag CVAL33; /* offset: 0x0130 size: 16 bit */ + /* Capture Value 3 Cycle Register */ + mcPWM_CVAL3CYC_16B_tag CVAL3CYC3; /* offset: 0x0132 size: 16 bit */ + /* Capture Value 4 Register */ + mcPWM_CVAL4_16B_tag CVAL43; /* offset: 0x0134 size: 16 bit */ + /* Capture Value 4 Cycle Register */ + mcPWM_CVAL4CYC_16B_tag CVAL4CYC3; /* offset: 0x0136 size: 16 bit */ + /* Capture Value 5 Register */ + mcPWM_CVAL5_16B_tag CVAL53; /* offset: 0x0138 size: 16 bit */ + /* Capture Value 5 Cycle Register */ + mcPWM_CVAL5CYC_16B_tag CVAL5CYC3; /* offset: 0x013A size: 16 bit */ + int8_t mcPWM_reserved_013C_E2[4]; + }; + + }; + /* Output Enable Register */ + mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */ + /* Mask Register */ + mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */ + /* Software Controlled Output Register */ + mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */ + /* Deadtime Source Select Register */ + mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */ + /* Master Control Register */ + mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */ + int8_t mcPWM_reserved_014A[2]; + /* Fault Control Register */ + mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */ + /* Fault Status Register */ + mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */ + /* Fault Filter Register */ + mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */ + } mcPWM_tag; + + +#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL) +#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL) + + + +/****************************************************************/ +/* */ +/* Module: LINFLEX */ +/* */ +/****************************************************************/ + + typedef union { /* LIN Control Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CCD:1; /* Checksum Calculation Disable */ + vuint32_t CFD:1; /* Checksum Field Disable */ + vuint32_t LASE:1; /* LIN Auto Synchronization Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t AUTOWU:1; /* Auto Wake Up */ +#else + vuint32_t AWUM:1; /* deprecated name - please avoid */ +#endif + vuint32_t MBL:4; /* Master Break Length */ + vuint32_t BF:1; /* By-Pass Filter */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t SLFM:1; /* Selftest Mode */ +#else + vuint32_t SFTM:1; /* deprecated name - please avoid */ +#endif + vuint32_t LBKM:1; /* Loopback Mode */ + vuint32_t MME:1; /* Master Mode Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t SSBL:1; /* Slave Mode Synch Break Length */ +#else + vuint32_t SSDT:1; /* deprecated name - please avoid */ +#endif + vuint32_t RBLM:1; /* Receiver Buffer Locked Mode */ + vuint32_t SLEEP:1; /* Sleep Mode Request */ + vuint32_t INIT:1; /* Initialization Mode Request */ + } B; + } LINFLEX_LINCR1_32B_tag; + + typedef union { /* LIN Interrupt Enable Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */ + vuint32_t OCIE:1; /* Output Compare Interrupt Enable */ + vuint32_t BEIE:1; /* Bit Error Interrupt Enable */ + vuint32_t CEIE:1; /* Checksum Error Interrupt Enable */ + vuint32_t HEIE:1; /* Header Error Interrupt Enable */ + vuint32_t:2; + vuint32_t FEIE:1; /* Frame Error Interrupt Enable */ + vuint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */ + vuint32_t LSIE:1; /* LIN State Interrupt Enable */ + vuint32_t WUIE:1; /* Wakeup Interrupt Enable */ + vuint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */ +#else + vuint32_t DBEIE:1; /* deprecated name - please avoid */ +#endif + vuint32_t DRIE:1; /* Data Reception complete Interrupt Enable */ + vuint32_t DTIE:1; /* Data Transmitted Interrupt Enable */ + vuint32_t HRIE:1; /* Header Received Interrupt Enable */ + } B; + } LINFLEX_LINIER_32B_tag; + + typedef union { /* LIN Status Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t LINS:4; /* LIN State */ + vuint32_t:2; + vuint32_t RMB:1; /* Release Message Buffer */ + vuint32_t:1; +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t RXBUSY:1; /* Receiver Busy Flag */ +#else + vuint32_t RBSY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t RDI:1; /* LIN Receive Signal */ +#else + vuint32_t RPS:1; /* deprecated name - please avoid */ +#endif + vuint32_t WUF:1; /* Wake Up Flag */ + vuint32_t DBFF:1; /* Data Buffer Full Flag */ + vuint32_t DBEF:1; /* Data Buffer Empty Flag */ + vuint32_t DRF:1; /* Data Reception Completed Flag */ + vuint32_t DTF:1; /* Data Transmission Completed Flag */ + vuint32_t HRF:1; /* Header Received Flag */ + } B; + } LINFLEX_LINSR_32B_tag; + + typedef union { /* LIN Error Status Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZF:1; /* Stuck at Zero Flag */ + vuint32_t OCF:1; /* Output Compare Flag */ + vuint32_t BEF:1; /* Bit Error Flag */ + vuint32_t CEF:1; /* Checksum Error Flag */ + vuint32_t SFEF:1; /* Sync Field Error Flag */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t SDEF:1; /* Sync Delimiter Error Flag */ +#else + vuint32_t BDEF:1; /* deprecated name - please avoid */ +#endif + vuint32_t IDPEF:1; /* ID Parity Error Flag */ + vuint32_t FEF:1; /* Framing Error Flag */ + vuint32_t BOF:1; /* Buffer Overrun Flag */ + vuint32_t:6; + vuint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_LINESR_32B_tag; + + typedef union { /* UART Mode Control Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */ + vuint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */ + vuint32_t RFBM:1; /* RX FIFO/ Buffer Mode */ + vuint32_t TFBM:1; /* TX FIFO/ Buffer Mode */ + vuint32_t WL1:1; /* Word Length in UART mode - bit 1 */ + vuint32_t PC1:1; /* Parity Check - bit 1 */ + vuint32_t RXEN:1; /* Receiver Enable */ + vuint32_t TXEN:1; /* Transmitter Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t PC0:1; /* Parity Check - bit 0 */ +#else + vuint32_t OP:1; /* deprecated name - please avoid */ +#endif + vuint32_t PCE:1; /* Parity Control Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t WL0:1; /* Word Length in UART Mode - bit 0 */ +#else + vuint32_t WL:1; /* deprecated name - please avoid */ +#endif + vuint32_t UART:1; /* UART Mode */ + } B; + } LINFLEX_UARTCR_32B_tag; + + typedef union { /* UART Mode Status Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SZF:1; /* Stuck at Zero Flag */ + vuint32_t OCF:1; /* Output Compare Flag */ + vuint32_t PE:4; /* Parity Error Flag */ + vuint32_t RMB:1; /* Release Message Buffer */ + vuint32_t FEF:1; /* Framing Error Flag */ + vuint32_t BOF:1; /* Buffer Overrun Flag */ + vuint32_t RDI:1; /* Receiver Data Input Signal */ + vuint32_t WUF:1; /* Wakeup Flag */ + vuint32_t:1; + vuint32_t TO:1; /* Time Out */ +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */ +#else + vuint32_t DRF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */ +#else + vuint32_t DTF:1; /* deprecated name - please avoid */ +#endif + vuint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_UARTSR_32B_tag; + + typedef union { /* LIN Time-Out Control Status Register */ + vuint32_t R; + struct { + vuint32_t:21; +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t MODE:1; /* Time-out Counter Mode */ +#else + vuint32_t LTOM:1; /* deprecated name - please avoid */ +#endif + vuint32_t IOT:1; /* Idle on Timeout */ + vuint32_t TOCE:1; /* Time-Out Counter Enable */ + vuint32_t CNT:8; /* Counter Value */ + } B; + } LINFLEX_LINTCSR_32B_tag; + + typedef union { /* LIN Output Compare Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t OC2:8; /* Output Compare Value 2 */ + vuint32_t OC1:8; /* Output Compare Value 1 */ + } B; + } LINFLEX_LINOCR_32B_tag; + + typedef union { /* LIN Time-Out Control Register */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t RTO:4; /* Response Time-Out Value */ + vuint32_t:1; + vuint32_t HTO:7; /* Header Time-Out Value */ + } B; + } LINFLEX_LINTOCR_32B_tag; + + typedef union { /* LIN Fractional Baud Rate Register */ + vuint32_t R; + struct { + vuint32_t:28; +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t FBR:4; /* Fractional Baud Rates */ +#else + vuint32_t DIV_F:4; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINFBRR_32B_tag; + + typedef union { /* LIN Integer Baud Rate Register */ + vuint32_t R; + struct { + vuint32_t:13; +#ifndef USE_FIELD_ALIASES_LINFLEX + vuint32_t IBR:19; /* Integer Baud Rates */ +#else + vuint32_t DIV_M:19; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINIBRR_32B_tag; + + typedef union { /* LIN Checksum Field Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t CF:8; /* Checksum Bits */ + } B; + } LINFLEX_LINCFR_32B_tag; + + typedef union { /* LIN Control Register 2 */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t IOBE:1; /* Idle on Bit Error */ + vuint32_t IOPE:1; /* Idle on Identifier Parity Error */ + vuint32_t WURQ:1; /* Wakeup Generate Request */ + vuint32_t DDRQ:1; /* Data Discard Request */ + vuint32_t DTRQ:1; /* Data Transmission Request */ + vuint32_t ABRQ:1; /* Abort Request */ + vuint32_t HTRQ:1; /* Header Transmission Request */ + vuint32_t:8; + } B; + } LINFLEX_LINCR2_32B_tag; + + typedef union { /* Buffer Identifier Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; /* Data Field Length */ + vuint32_t DIR:1; /* Direction */ + vuint32_t CCS:1; /* Classic Checksum */ + vuint32_t:2; + vuint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_BIDR_32B_tag; + + typedef union { /* Buffer Data Register Least Significant */ + vuint32_t R; + struct { + vuint32_t DATA3:8; /* Data3 */ + vuint32_t DATA2:8; /* Data2 */ + vuint32_t DATA1:8; /* Data1 */ + vuint32_t DATA0:8; /* Data0 */ + } B; + } LINFLEX_BDRL_32B_tag; + + typedef union { /* Buffer Data Register Most Significant */ + vuint32_t R; + struct { + vuint32_t DATA7:8; /* Data7 */ + vuint32_t DATA6:8; /* Data6 */ + vuint32_t DATA5:8; /* Data5 */ + vuint32_t DATA4:8; /* Data4 */ + } B; + } LINFLEX_BDRM_32B_tag; + + typedef union { /* Identifier Filter Enable Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t FACT:8; /* Filter Active */ + } B; + } LINFLEX_IFER_32B_tag; + + typedef union { /* Identifier Filter Match Index */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFMI_IFMI:4; /* Filter Match Index */ + } B; + } LINFLEX_IFMI_32B_tag; + + typedef union { /* Identifier Filter Mode Register */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t IFM:4; /* Filter Mode */ + } B; + } LINFLEX_IFMR_32B_tag; + + + /* Register layout for all registers IFCR... */ + + typedef union { /* Identifier Filter Control Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DFL:6; /* Data Field Length */ + vuint32_t DIR:1; /* Direction */ + vuint32_t CCS:1; /* Classic Checksum */ + vuint32_t:2; + vuint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_IFCR_32B_tag; + + typedef union { /* Global Control Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t TDFBM:1; /* Transmit Data First Bit MSB */ + vuint32_t RDFBM:1; /* Received Data First Bit MSB */ + vuint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */ + vuint32_t RDLIS:1; /* Received Data Level Inversion Selection */ + vuint32_t STOP:1; /* 1/2 stop bit configuration */ + vuint32_t SR:1; /* Soft Reset */ + } B; + } LINFLEX_GCR_32B_tag; + + typedef union { /* UART Preset Time Out Register */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t PTO:12; /* Preset Time Out */ + } B; + } LINFLEX_UARTPTO_32B_tag; + + typedef union { /* UART Current Time Out Register */ + vuint32_t R; + struct { + vuint32_t:20; + vuint32_t CTO:12; /* Current Time Out */ + } B; + } LINFLEX_UARTCTO_32B_tag; + + typedef union { /* DMA TX Enable Register */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t DTE:15; /* DMA Tx channel Enable */ + } B; + } LINFLEX_DMATXE_32B_tag; + + typedef union { /* DMA RX Enable Register */ + vuint32_t R; + struct { + vuint32_t:17; + vuint32_t DRE:15; /* DMA Rx channel Enable */ + } B; + } LINFLEX_DMARXE_32B_tag; + + + + typedef struct LINFLEX_tag{ /* start of LINFLEX_tag */ + /* LIN Control Register */ + LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */ + /* LIN Interrupt Enable Register */ + LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */ + /* LIN Status Register */ + LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */ + /* LIN Error Status Register */ + LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */ + /* UART Mode Control Register */ + LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */ + /* UART Mode Status Register */ + LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */ + /* LIN Time-Out Control Status Register */ + LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */ + /* LIN Output Compare Register */ + LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */ + /* LIN Time-Out Control Register */ + LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */ + /* LIN Fractional Baud Rate Register */ + LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */ + /* LIN Integer Baud Rate Register */ + LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */ + /* LIN Checksum Field Register */ + LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */ + /* LIN Control Register 2 */ + LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */ + /* Buffer Identifier Register */ + LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */ + /* Buffer Data Register Least Significant */ + LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */ + /* Buffer Data Register Most Significant */ + LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */ + /* Identifier Filter Enable Register */ + LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */ + /* Identifier Filter Match Index */ + LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */ + /* Identifier Filter Mode Register */ + LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */ + union { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t LINFLEX_reserved_006C[32]; + /* Global Control Register */ + LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */ + /* UART Preset Time Out Register */ + LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */ + /* UART Current Time Out Register */ + LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */ + /* DMA TX Enable Register */ + LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */ + /* DMA RX Enable Register */ + LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */ + } LINFLEX_tag; + + +#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL) +#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL) + + + +/****************************************************************/ +/* */ +/* Module: CRC */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CFG... */ + + typedef union { /* CRC_CFG - CRC Configuration register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + struct { + vuint32_t:29; + vuint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */ + vuint32_t SWAP:1; /* SWAP selection */ + vuint32_t INV:1; /* INV selection */ + } B; + } CRC_CFG_32B_tag; + + + /* Register layout for all registers INP... */ + + typedef union { /* CRC_INP - CRC Input register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + } CRC_INP_32B_tag; + + + /* Register layout for all registers CSTAT... */ + + typedef union { /* CRC_STATUS - CRC Status register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + } CRC_CSTAT_32B_tag; + + + /* Register layout for all registers OUTP... */ + + typedef union { /* CRC_STATUS - CRC OUTPUT register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint16_t HALF[2]; /* individual halfwords can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + } CRC_OUTP_32B_tag; + + + typedef struct CRC_CNTX_struct_tag { + + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP; /* relative offset: 0x0004 */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */ + + } CRC_CNTX_tag; + + + typedef struct CRC_struct_tag { /* start of CRC_tag */ + union { + /* Register set CNTX */ + CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */ + + struct { + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */ + }; + + }; + } CRC_tag; + + +#define CRC (*(volatile CRC_tag *) 0xFFE68000UL) + + + +/****************************************************************/ +/* */ +/* Module: FCCU */ +/* */ +/****************************************************************/ + + typedef union { /* FCCU Control Register */ + vuint32_t R; + struct { + vuint32_t:23; + vuint32_t NVML:1; /* NVM configuration loaded */ + vuint32_t OPS:2; /* Operation status */ + vuint32_t:1; + vuint32_t OPR:5; /* Operation run */ + } B; + } FCCU_CTRL_32B_tag; + + typedef union { /* FCCU CTRL Key Register */ + vuint32_t R; + } FCCU_CTRLK_32B_tag; + + typedef union { /* FCCU Configuration Register */ + vuint32_t R; + struct { + vuint32_t:10; + vuint32_t RCCE1:1; /* RCC1 enable */ + vuint32_t RCCE0:1; /* RCC0 enable */ + vuint32_t SMRT:4; /* Safe Mode Request Timer */ + vuint32_t:4; + vuint32_t CM:1; /* Config mode */ + vuint32_t SM:1; /* Switching mode */ + vuint32_t PS:1; /* Polarity Selection */ + vuint32_t FOM:3; /* Fault Output Mode Selection */ + vuint32_t FOP:6; /* Fault Output Prescaler */ + } B; + } FCCU_CFG_32B_tag; + + typedef union { /* FCCU CF Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t CFC31:1; /* CF 31 configuration */ + vuint32_t CFC30:1; /* CF 30 configuration */ + vuint32_t CFC29:1; /* CF 29 configuration */ + vuint32_t CFC28:1; /* CF 28 configuration */ + vuint32_t CFC27:1; /* CF 27 configuration */ + vuint32_t CFC26:1; /* CF 26 configuration */ + vuint32_t CFC25:1; /* CF 25 configuration */ + vuint32_t CFC24:1; /* CF 24 configuration */ + vuint32_t CFC23:1; /* CF 23 configuration */ + vuint32_t CFC22:1; /* CF 22 configuration */ + vuint32_t CFC21:1; /* CF 21 configuration */ + vuint32_t CFC20:1; /* CF 20 configuration */ + vuint32_t CFC19:1; /* CF 19 configuration */ + vuint32_t CFC18:1; /* CF 18 configuration */ + vuint32_t CFC17:1; /* CF 17 configuration */ + vuint32_t CFC16:1; /* CF 16 configuration */ + vuint32_t CFC15:1; /* CF 15 configuration */ + vuint32_t CFC14:1; /* CF 14 configuration */ + vuint32_t CFC13:1; /* CF 13 configuration */ + vuint32_t CFC12:1; /* CF 12 configuration */ + vuint32_t CFC11:1; /* CF 11 configuration */ + vuint32_t CFC10:1; /* CF 10 configuration */ + vuint32_t CFC9:1; /* CF 9 configuration */ + vuint32_t CFC8:1; /* CF 8 configuration */ + vuint32_t CFC7:1; /* CF 7 configuration */ + vuint32_t CFC6:1; /* CF 6 configuration */ + vuint32_t CFC5:1; /* CF 5 configuration */ + vuint32_t CFC4:1; /* CF 4 configuration */ + vuint32_t CFC3:1; /* CF 3 configuration */ + vuint32_t CFC2:1; /* CF 2 configuration */ + vuint32_t CFC1:1; /* CF 1 configuration */ + vuint32_t CFC0:1; /* CF 0 configuration */ + } B; + } FCCU_CF_CFG0_32B_tag; + + typedef union { /* FCCU CF Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t CFC63:1; /* CF 63 configuration */ + vuint32_t CFC62:1; /* CF 62 configuration */ + vuint32_t CFC61:1; /* CF 61 configuration */ + vuint32_t CFC60:1; /* CF 60 configuration */ + vuint32_t CFC59:1; /* CF 59 configuration */ + vuint32_t CFC58:1; /* CF 58 configuration */ + vuint32_t CFC57:1; /* CF 57 configuration */ + vuint32_t CFC56:1; /* CF 56 configuration */ + vuint32_t CFC55:1; /* CF 55 configuration */ + vuint32_t CFC54:1; /* CF 54 configuration */ + vuint32_t CFC53:1; /* CF 53 configuration */ + vuint32_t CFC52:1; /* CF 52 configuration */ + vuint32_t CFC51:1; /* CF 51 configuration */ + vuint32_t CFC50:1; /* CF 50 configuration */ + vuint32_t CFC49:1; /* CF 49 configuration */ + vuint32_t CFC48:1; /* CF 48 configuration */ + vuint32_t CFC47:1; /* CF 47 configuration */ + vuint32_t CFC46:1; /* CF 46 configuration */ + vuint32_t CFC45:1; /* CF 45 configuration */ + vuint32_t CFC44:1; /* CF 44 configuration */ + vuint32_t CFC43:1; /* CF 43 configuration */ + vuint32_t CFC42:1; /* CF 42 configuration */ + vuint32_t CFC41:1; /* CF 41 configuration */ + vuint32_t CFC40:1; /* CF 40 configuration */ + vuint32_t CFC39:1; /* CF 39 configuration */ + vuint32_t CFC38:1; /* CF 38 configuration */ + vuint32_t CFC37:1; /* CF 37 configuration */ + vuint32_t CFC36:1; /* CF 36 configuration */ + vuint32_t CFC35:1; /* CF 35 configuration */ + vuint32_t CFC34:1; /* CF 34 configuration */ + vuint32_t CFC33:1; /* CF 33 configuration */ + vuint32_t CFC32:1; /* CF 32 configuration */ + } B; + } FCCU_CF_CFG1_32B_tag; + + typedef union { /* FCCU CF Configuration Register 2 */ + vuint32_t R; + struct { + vuint32_t CFC95:1; /* CF 95 configuration */ + vuint32_t CFC94:1; /* CF 94 configuration */ + vuint32_t CFC93:1; /* CF 93 configuration */ + vuint32_t CFC92:1; /* CF 92 configuration */ + vuint32_t CFC91:1; /* CF 91 configuration */ + vuint32_t CFC90:1; /* CF 90 configuration */ + vuint32_t CFC89:1; /* CF 89 configuration */ + vuint32_t CFC88:1; /* CF 88 configuration */ + vuint32_t CFC87:1; /* CF 87 configuration */ + vuint32_t CFC86:1; /* CF 86 configuration */ + vuint32_t CFC85:1; /* CF 85 configuration */ + vuint32_t CFC84:1; /* CF 84 configuration */ + vuint32_t CFC83:1; /* CF 83 configuration */ + vuint32_t CFC82:1; /* CF 82 configuration */ + vuint32_t CFC81:1; /* CF 81 configuration */ + vuint32_t CFC80:1; /* CF 80 configuration */ + vuint32_t CFC79:1; /* CF 79 configuration */ + vuint32_t CFC78:1; /* CF 78 configuration */ + vuint32_t CFC77:1; /* CF 77 configuration */ + vuint32_t CFC76:1; /* CF 76 configuration */ + vuint32_t CFC75:1; /* CF 75 configuration */ + vuint32_t CFC74:1; /* CF 74 configuration */ + vuint32_t CFC73:1; /* CF 73 configuration */ + vuint32_t CFC72:1; /* CF 72 configuration */ + vuint32_t CFC71:1; /* CF 71 configuration */ + vuint32_t CFC70:1; /* CF 70 configuration */ + vuint32_t CFC69:1; /* CF 69 configuration */ + vuint32_t CFC68:1; /* CF 68 configuration */ + vuint32_t CFC67:1; /* CF 67 configuration */ + vuint32_t CFC66:1; /* CF 66 configuration */ + vuint32_t CFC65:1; /* CF 65 configuration */ + vuint32_t CFC64:1; /* CF 64 configuration */ + } B; + } FCCU_CF_CFG2_32B_tag; + + typedef union { /* FCCU CF Configuration Register 3 */ + vuint32_t R; + struct { + vuint32_t CFC127:1; /* CF 127 configuration */ + vuint32_t CFC126:1; /* CF 126 configuration */ + vuint32_t CFC125:1; /* CF 125 configuration */ + vuint32_t CFC124:1; /* CF 124 configuration */ + vuint32_t CFC123:1; /* CF 123 configuration */ + vuint32_t CFC122:1; /* CF 122 configuration */ + vuint32_t CFC121:1; /* CF 121 configuration */ + vuint32_t CFC120:1; /* CF 120 configuration */ + vuint32_t CFC119:1; /* CF 119 configuration */ + vuint32_t CFC118:1; /* CF 118 configuration */ + vuint32_t CFC117:1; /* CF 117 configuration */ + vuint32_t CFC116:1; /* CF 116 configuration */ + vuint32_t CFC115:1; /* CF 115 configuration */ + vuint32_t CFC114:1; /* CF 114 configuration */ + vuint32_t CFC113:1; /* CF 113 configuration */ + vuint32_t CFC112:1; /* CF 112 configuration */ + vuint32_t CFC111:1; /* CF 111 configuration */ + vuint32_t CFC110:1; /* CF 110 configuration */ + vuint32_t CFC109:1; /* CF 109 configuration */ + vuint32_t CFC108:1; /* CF 108 configuration */ + vuint32_t CFC107:1; /* CF 107 configuration */ + vuint32_t CFC106:1; /* CF 106 configuration */ + vuint32_t CFC105:1; /* CF 105 configuration */ + vuint32_t CFC104:1; /* CF 104 configuration */ + vuint32_t CFC103:1; /* CF 103 configuration */ + vuint32_t CFC102:1; /* CF 102 configuration */ + vuint32_t CFC101:1; /* CF 101 configuration */ + vuint32_t CFC100:1; /* CF 100 configuration */ + vuint32_t CFC99:1; /* CF 99 configuration */ + vuint32_t CFC98:1; /* CF 98 configuration */ + vuint32_t CFC97:1; /* CF 97 configuration */ + vuint32_t CFC96:1; /* CF 96 configuration */ + } B; + } FCCU_CF_CFG3_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t NCFC31:1; /* NCF 31 configuration */ + vuint32_t NCFC30:1; /* NCF 30 configuration */ + vuint32_t NCFC29:1; /* NCF 29 configuration */ + vuint32_t NCFC28:1; /* NCF 28 configuration */ + vuint32_t NCFC27:1; /* NCF 27 configuration */ + vuint32_t NCFC26:1; /* NCF 26 configuration */ + vuint32_t NCFC25:1; /* NCF 25 configuration */ + vuint32_t NCFC24:1; /* NCF 24 configuration */ + vuint32_t NCFC23:1; /* NCF 23 configuration */ + vuint32_t NCFC22:1; /* NCF 22 configuration */ + vuint32_t NCFC21:1; /* NCF 21 configuration */ + vuint32_t NCFC20:1; /* NCF 20 configuration */ + vuint32_t NCFC19:1; /* NCF 19 configuration */ + vuint32_t NCFC18:1; /* NCF 18 configuration */ + vuint32_t NCFC17:1; /* NCF 17 configuration */ + vuint32_t NCFC16:1; /* NCF 16 configuration */ + vuint32_t NCFC15:1; /* NCF 15 configuration */ + vuint32_t NCFC14:1; /* NCF 14 configuration */ + vuint32_t NCFC13:1; /* NCF 13 configuration */ + vuint32_t NCFC12:1; /* NCF 12 configuration */ + vuint32_t NCFC11:1; /* NCF 11 configuration */ + vuint32_t NCFC10:1; /* NCF 10 configuration */ + vuint32_t NCFC9:1; /* NCF 9 configuration */ + vuint32_t NCFC8:1; /* NCF 8 configuration */ + vuint32_t NCFC7:1; /* NCF 7 configuration */ + vuint32_t NCFC6:1; /* NCF 6 configuration */ + vuint32_t NCFC5:1; /* NCF 5 configuration */ + vuint32_t NCFC4:1; /* NCF 4 configuration */ + vuint32_t NCFC3:1; /* NCF 3 configuration */ + vuint32_t NCFC2:1; /* NCF 2 configuration */ + vuint32_t NCFC1:1; /* NCF 1 configuration */ + vuint32_t NCFC0:1; /* NCF 0 configuration */ + } B; + } FCCU_NCF_CFG0_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t NCFC63:1; /* NCF 63 configuration */ + vuint32_t NCFC62:1; /* NCF 62 configuration */ + vuint32_t NCFC61:1; /* NCF 61 configuration */ + vuint32_t NCFC60:1; /* NCF 60 configuration */ + vuint32_t NCFC59:1; /* NCF 59 configuration */ + vuint32_t NCFC58:1; /* NCF 58 configuration */ + vuint32_t NCFC57:1; /* NCF 57 configuration */ + vuint32_t NCFC56:1; /* NCF 56 configuration */ + vuint32_t NCFC55:1; /* NCF 55 configuration */ + vuint32_t NCFC54:1; /* NCF 54 configuration */ + vuint32_t NCFC53:1; /* NCF 53 configuration */ + vuint32_t NCFC52:1; /* NCF 52 configuration */ + vuint32_t NCFC51:1; /* NCF 51 configuration */ + vuint32_t NCFC50:1; /* NCF 50 configuration */ + vuint32_t NCFC49:1; /* NCF 49 configuration */ + vuint32_t NCFC48:1; /* NCF 48 configuration */ + vuint32_t NCFC47:1; /* NCF 47 configuration */ + vuint32_t NCFC46:1; /* NCF 46 configuration */ + vuint32_t NCFC45:1; /* NCF 45 configuration */ + vuint32_t NCFC44:1; /* NCF 44 configuration */ + vuint32_t NCFC43:1; /* NCF 43 configuration */ + vuint32_t NCFC42:1; /* NCF 42 configuration */ + vuint32_t NCFC41:1; /* NCF 41 configuration */ + vuint32_t NCFC40:1; /* NCF 40 configuration */ + vuint32_t NCFC39:1; /* NCF 39 configuration */ + vuint32_t NCFC38:1; /* NCF 38 configuration */ + vuint32_t NCFC37:1; /* NCF 37 configuration */ + vuint32_t NCFC36:1; /* NCF 36 configuration */ + vuint32_t NCFC35:1; /* NCF 35 configuration */ + vuint32_t NCFC34:1; /* NCF 34 configuration */ + vuint32_t NCFC33:1; /* NCF 33 configuration */ + vuint32_t NCFC32:1; /* NCF 32 configuration */ + } B; + } FCCU_NCF_CFG1_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 2 */ + vuint32_t R; + struct { + vuint32_t NCFC95:1; /* NCF 95 configuration */ + vuint32_t NCFC94:1; /* NCF 94 configuration */ + vuint32_t NCFC93:1; /* NCF 93 configuration */ + vuint32_t NCFC92:1; /* NCF 92 configuration */ + vuint32_t NCFC91:1; /* NCF 91 configuration */ + vuint32_t NCFC90:1; /* NCF 90 configuration */ + vuint32_t NCFC89:1; /* NCF 89 configuration */ + vuint32_t NCFC88:1; /* NCF 88 configuration */ + vuint32_t NCFC87:1; /* NCF 87 configuration */ + vuint32_t NCFC86:1; /* NCF 86 configuration */ + vuint32_t NCFC85:1; /* NCF 85 configuration */ + vuint32_t NCFC84:1; /* NCF 84 configuration */ + vuint32_t NCFC83:1; /* NCF 83 configuration */ + vuint32_t NCFC82:1; /* NCF 82 configuration */ + vuint32_t NCFC81:1; /* NCF 81 configuration */ + vuint32_t NCFC80:1; /* NCF 80 configuration */ + vuint32_t NCFC79:1; /* NCF 79 configuration */ + vuint32_t NCFC78:1; /* NCF 78 configuration */ + vuint32_t NCFC77:1; /* NCF 77 configuration */ + vuint32_t NCFC76:1; /* NCF 76 configuration */ + vuint32_t NCFC75:1; /* NCF 75 configuration */ + vuint32_t NCFC74:1; /* NCF 74 configuration */ + vuint32_t NCFC73:1; /* NCF 73 configuration */ + vuint32_t NCFC72:1; /* NCF 72 configuration */ + vuint32_t NCFC71:1; /* NCF 71 configuration */ + vuint32_t NCFC70:1; /* NCF 70 configuration */ + vuint32_t NCFC69:1; /* NCF 69 configuration */ + vuint32_t NCFC68:1; /* NCF 68 configuration */ + vuint32_t NCFC67:1; /* NCF 67 configuration */ + vuint32_t NCFC66:1; /* NCF 66 configuration */ + vuint32_t NCFC65:1; /* NCF 65 configuration */ + vuint32_t NCFC64:1; /* NCF 64 configuration */ + } B; + } FCCU_NCF_CFG2_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 3 */ + vuint32_t R; + struct { + vuint32_t NCFC127:1; /* NCF 127 configuration */ + vuint32_t NCFC126:1; /* NCF 126 configuration */ + vuint32_t NCFC125:1; /* NCF 125 configuration */ + vuint32_t NCFC124:1; /* NCF 124 configuration */ + vuint32_t NCFC123:1; /* NCF 123 configuration */ + vuint32_t NCFC122:1; /* NCF 122 configuration */ + vuint32_t NCFC121:1; /* NCF 121 configuration */ + vuint32_t NCFC120:1; /* NCF 120 configuration */ + vuint32_t NCFC119:1; /* NCF 119 configuration */ + vuint32_t NCFC118:1; /* NCF 118 configuration */ + vuint32_t NCFC117:1; /* NCF 117 configuration */ + vuint32_t NCFC116:1; /* NCF 116 configuration */ + vuint32_t NCFC115:1; /* NCF 115 configuration */ + vuint32_t NCFC114:1; /* NCF 114 configuration */ + vuint32_t NCFC113:1; /* NCF 113 configuration */ + vuint32_t NCFC112:1; /* NCF 112 configuration */ + vuint32_t NCFC111:1; /* NCF 111 configuration */ + vuint32_t NCFC110:1; /* NCF 110 configuration */ + vuint32_t NCFC109:1; /* NCF 109 configuration */ + vuint32_t NCFC108:1; /* NCF 108 configuration */ + vuint32_t NCFC107:1; /* NCF 107 configuration */ + vuint32_t NCFC106:1; /* NCF 106 configuration */ + vuint32_t NCFC105:1; /* NCF 105 configuration */ + vuint32_t NCFC104:1; /* NCF 104 configuration */ + vuint32_t NCFC103:1; /* NCF 103 configuration */ + vuint32_t NCFC102:1; /* NCF 102 configuration */ + vuint32_t NCFC101:1; /* NCF 101 configuration */ + vuint32_t NCFC100:1; /* NCF 100 configuration */ + vuint32_t NCFC99:1; /* NCF 99 configuration */ + vuint32_t NCFC98:1; /* NCF 98 configuration */ + vuint32_t NCFC97:1; /* NCF 97 configuration */ + vuint32_t NCFC96:1; /* NCF 96 configuration */ + } B; + } FCCU_NCF_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t CFSC15:2; /* CF 15 state configuration */ + vuint32_t CFSC14:2; /* CF 14 state configuration */ + vuint32_t CFSC13:2; /* CF 13 state configuration */ + vuint32_t CFSC12:2; /* CF 12 state configuration */ + vuint32_t CFSC11:2; /* CF 11 state configuration */ + vuint32_t CFSC10:2; /* CF 10 state configuration */ + vuint32_t CFSC9:2; /* CF 9 state configuration */ + vuint32_t CFSC8:2; /* CF 8 state configuration */ + vuint32_t CFSC7:2; /* CF 7 state configuration */ + vuint32_t CFSC6:2; /* CF 6 state configuration */ + vuint32_t CFSC5:2; /* CF 5 state configuration */ + vuint32_t CFSC4:2; /* CF 4 state configuration */ + vuint32_t CFSC3:2; /* CF 3 state configuration */ + vuint32_t CFSC2:2; /* CF 2 state configuration */ + vuint32_t CFSC1:2; /* CF 1 state configuration */ + vuint32_t CFSC0:2; /* CF 0 state configuration */ + } B; + } FCCU_CFS_CFG0_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t CFSC31:2; /* CF 31 state configuration */ + vuint32_t CFSC30:2; /* CF 30 state configuration */ + vuint32_t CFSC29:2; /* CF 29 state configuration */ + vuint32_t CFSC28:2; /* CF 28 state configuration */ + vuint32_t CFSC27:2; /* CF 27 state configuration */ + vuint32_t CFSC26:2; /* CF 26 state configuration */ + vuint32_t CFSC25:2; /* CF 25 state configuration */ + vuint32_t CFSC24:2; /* CF 24 state configuration */ + vuint32_t CFSC23:2; /* CF 23 state configuration */ + vuint32_t CFSC22:2; /* CF 22 state configuration */ + vuint32_t CFSC21:2; /* CF 21 state configuration */ + vuint32_t CFSC20:2; /* CF 20 state configuration */ + vuint32_t CFSC19:2; /* CF 19 state configuration */ + vuint32_t CFSC18:2; /* CF 18 state configuration */ + vuint32_t CFSC17:2; /* CF 17 state configuration */ + vuint32_t CFSC16:2; /* CF 16 state configuration */ + } B; + } FCCU_CFS_CFG1_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 2 */ + vuint32_t R; + struct { + vuint32_t CFSC47:2; /* CF 47 state configuration */ + vuint32_t CFSC46:2; /* CF 46 state configuration */ + vuint32_t CFSC45:2; /* CF 45 state configuration */ + vuint32_t CFSC44:2; /* CF 44 state configuration */ + vuint32_t CFSC43:2; /* CF 43 state configuration */ + vuint32_t CFSC42:2; /* CF 42 state configuration */ + vuint32_t CFSC41:2; /* CF 41 state configuration */ + vuint32_t CFSC40:2; /* CF 40 state configuration */ + vuint32_t CFSC39:2; /* CF 39 state configuration */ + vuint32_t CFSC38:2; /* CF 38 state configuration */ + vuint32_t CFSC37:2; /* CF 37 state configuration */ + vuint32_t CFSC36:2; /* CF 36 state configuration */ + vuint32_t CFSC35:2; /* CF 35 state configuration */ + vuint32_t CFSC34:2; /* CF 34 state configuration */ + vuint32_t CFSC33:2; /* CF 33 state configuration */ + vuint32_t CFSC32:2; /* CF 32 state configuration */ + } B; + } FCCU_CFS_CFG2_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 3 */ + vuint32_t R; + struct { + vuint32_t CFSC63:2; /* CF 63 state configuration */ + vuint32_t CFSC62:2; /* CF 62 state configuration */ + vuint32_t CFSC61:2; /* CF 61 state configuration */ + vuint32_t CFSC60:2; /* CF 60 state configuration */ + vuint32_t CFSC59:2; /* CF 59 state configuration */ + vuint32_t CFSC58:2; /* CF 58 state configuration */ + vuint32_t CFSC57:2; /* CF 57 state configuration */ + vuint32_t CFSC56:2; /* CF 56 state configuration */ + vuint32_t CFSC55:2; /* CF 55 state configuration */ + vuint32_t CFSC54:2; /* CF 54 state configuration */ + vuint32_t CFSC53:2; /* CF 53 state configuration */ + vuint32_t CFSC52:2; /* CF 52 state configuration */ + vuint32_t CFSC51:2; /* CF 51 state configuration */ + vuint32_t CFSC50:2; /* CF 50 state configuration */ + vuint32_t CFSC49:2; /* CF 49 state configuration */ + vuint32_t CFSC48:2; /* CF 48 state configuration */ + } B; + } FCCU_CFS_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 4 */ + vuint32_t R; + struct { + vuint32_t CFSC79:2; /* CF 79 state configuration */ + vuint32_t CFSC78:2; /* CF 78 state configuration */ + vuint32_t CFSC77:2; /* CF 77 state configuration */ + vuint32_t CFSC76:2; /* CF 76 state configuration */ + vuint32_t CFSC75:2; /* CF 75 state configuration */ + vuint32_t CFSC74:2; /* CF 74 state configuration */ + vuint32_t CFSC73:2; /* CF 73 state configuration */ + vuint32_t CFSC72:2; /* CF 72 state configuration */ + vuint32_t CFSC71:2; /* CF 71 state configuration */ + vuint32_t CFSC70:2; /* CF 70 state configuration */ + vuint32_t CFSC69:2; /* CF 69 state configuration */ + vuint32_t CFSC68:2; /* CF 68 state configuration */ + vuint32_t CFSC67:2; /* CF 67 state configuration */ + vuint32_t CFSC66:2; /* CF 66 state configuration */ + vuint32_t CFSC65:2; /* CF 65 state configuration */ + vuint32_t CFSC64:2; /* CF 64 state configuration */ + } B; + } FCCU_CFS_CFG4_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 5 */ + vuint32_t R; + struct { + vuint32_t CFSC95:2; /* CF 95 state configuration */ + vuint32_t CFSC94:2; /* CF 94 state configuration */ + vuint32_t CFSC93:2; /* CF 93 state configuration */ + vuint32_t CFSC92:2; /* CF 92 state configuration */ + vuint32_t CFSC91:2; /* CF 91 state configuration */ + vuint32_t CFSC90:2; /* CF 90 state configuration */ + vuint32_t CFSC89:2; /* CF 89 state configuration */ + vuint32_t CFSC88:2; /* CF 88 state configuration */ + vuint32_t CFSC87:2; /* CF 87 state configuration */ + vuint32_t CFSC86:2; /* CF 86 state configuration */ + vuint32_t CFSC85:2; /* CF 85 state configuration */ + vuint32_t CFSC84:2; /* CF 84 state configuration */ + vuint32_t CFSC83:2; /* CF 83 state configuration */ + vuint32_t CFSC82:2; /* CF 82 state configuration */ + vuint32_t CFSC81:2; /* CF 81 state configuration */ + vuint32_t CFSC80:2; /* CF 80 state configuration */ + } B; + } FCCU_CFS_CFG5_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 6 */ + vuint32_t R; + struct { + vuint32_t CFSC111:2; /* CF 111 state configuration */ + vuint32_t CFSC110:2; /* CF 110 state configuration */ + vuint32_t CFSC109:2; /* CF 109 state configuration */ + vuint32_t CFSC108:2; /* CF 108 state configuration */ + vuint32_t CFSC107:2; /* CF 107 state configuration */ + vuint32_t CFSC106:2; /* CF 106 state configuration */ + vuint32_t CFSC105:2; /* CF 105 state configuration */ + vuint32_t CFSC104:2; /* CF 104 state configuration */ + vuint32_t CFSC103:2; /* CF 103 state configuration */ + vuint32_t CFSC102:2; /* CF 102 state configuration */ + vuint32_t CFSC101:2; /* CF 101 state configuration */ + vuint32_t CFSC100:2; /* CF 100 state configuration */ + vuint32_t CFSC99:2; /* CF 99 state configuration */ + vuint32_t CFSC98:2; /* CF 98 state configuration */ + vuint32_t CFSC97:2; /* CF 97 state configuration */ + vuint32_t CFSC96:2; /* CF 96 state configuration */ + } B; + } FCCU_CFS_CFG6_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 7 */ + vuint32_t R; + struct { + vuint32_t CFSC127:2; /* CF 127 state configuration */ + vuint32_t CFSC126:2; /* CF 126 state configuration */ + vuint32_t CFSC125:2; /* CF 125 state configuration */ + vuint32_t CFSC124:2; /* CF 124 state configuration */ + vuint32_t CFSC123:2; /* CF 123 state configuration */ + vuint32_t CFSC122:2; /* CF 122 state configuration */ + vuint32_t CFSC121:2; /* CF 121 state configuration */ + vuint32_t CFSC120:2; /* CF 120 state configuration */ + vuint32_t CFSC119:2; /* CF 119 state configuration */ + vuint32_t CFSC118:2; /* CF 118 state configuration */ + vuint32_t CFSC117:2; /* CF 117 state configuration */ + vuint32_t CFSC116:2; /* CF 116 state configuration */ + vuint32_t CFSC115:2; /* CF 115 state configuration */ + vuint32_t CFSC114:2; /* CF 114 state configuration */ + vuint32_t CFSC113:2; /* CF 113 state configuration */ + vuint32_t CFSC112:2; /* CF 112 state configuration */ + } B; + } FCCU_CFS_CFG7_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 0 */ + vuint32_t R; + struct { + vuint32_t NCFSC15:2; /* NCF 15 state configuration */ + vuint32_t NCFSC14:2; /* NCF 14 state configuration */ + vuint32_t NCFSC13:2; /* NCF 13 state configuration */ + vuint32_t NCFSC12:2; /* NCF 12 state configuration */ + vuint32_t NCFSC11:2; /* NCF 11 state configuration */ + vuint32_t NCFSC10:2; /* NCF 10 state configuration */ + vuint32_t NCFSC9:2; /* NCF 9 state configuration */ + vuint32_t NCFSC8:2; /* NCF 8 state configuration */ + vuint32_t NCFSC7:2; /* NCF 7 state configuration */ + vuint32_t NCFSC6:2; /* NCF 6 state configuration */ + vuint32_t NCFSC5:2; /* NCF 5 state configuration */ + vuint32_t NCFSC4:2; /* NCF 4 state configuration */ + vuint32_t NCFSC3:2; /* NCF 3 state configuration */ + vuint32_t NCFSC2:2; /* NCF 2 state configuration */ + vuint32_t NCFSC1:2; /* NCF 1 state configuration */ + vuint32_t NCFSC0:2; /* NCF 0 state configuration */ + } B; + } FCCU_NCFS_CFG0_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 1 */ + vuint32_t R; + struct { + vuint32_t NCFSC31:2; /* NCF 31 state configuration */ + vuint32_t NCFSC30:2; /* NCF 30 state configuration */ + vuint32_t NCFSC29:2; /* NCF 29 state configuration */ + vuint32_t NCFSC28:2; /* NCF 28 state configuration */ + vuint32_t NCFSC27:2; /* NCF 27 state configuration */ + vuint32_t NCFSC26:2; /* NCF 26 state configuration */ + vuint32_t NCFSC25:2; /* NCF 25 state configuration */ + vuint32_t NCFSC24:2; /* NCF 24 state configuration */ + vuint32_t NCFSC23:2; /* NCF 23 state configuration */ + vuint32_t NCFSC22:2; /* NCF 22 state configuration */ + vuint32_t NCFSC21:2; /* NCF 21 state configuration */ + vuint32_t NCFSC20:2; /* NCF 20 state configuration */ + vuint32_t NCFSC19:2; /* NCF 19 state configuration */ + vuint32_t NCFSC18:2; /* NCF 18 state configuration */ + vuint32_t NCFSC17:2; /* NCF 17 state configuration */ + vuint32_t NCFSC16:2; /* NCF 16 state configuration */ + } B; + } FCCU_NCFS_CFG1_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 2 */ + vuint32_t R; + struct { + vuint32_t NCFSC47:2; /* NCF 47 state configuration */ + vuint32_t NCFSC46:2; /* NCF 46 state configuration */ + vuint32_t NCFSC45:2; /* NCF 45 state configuration */ + vuint32_t NCFSC44:2; /* NCF 44 state configuration */ + vuint32_t NCFSC43:2; /* NCF 43 state configuration */ + vuint32_t NCFSC42:2; /* NCF 42 state configuration */ + vuint32_t NCFSC41:2; /* NCF 41 state configuration */ + vuint32_t NCFSC40:2; /* NCF 40 state configuration */ + vuint32_t NCFSC39:2; /* NCF 39 state configuration */ + vuint32_t NCFSC38:2; /* NCF 38 state configuration */ + vuint32_t NCFSC37:2; /* NCF 37 state configuration */ + vuint32_t NCFSC36:2; /* NCF 36 state configuration */ + vuint32_t NCFSC35:2; /* NCF 35 state configuration */ + vuint32_t NCFSC34:2; /* NCF 34 state configuration */ + vuint32_t NCFSC33:2; /* NCF 33 state configuration */ + vuint32_t NCFSC32:2; /* NCF 32 state configuration */ + } B; + } FCCU_NCFS_CFG2_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 3 */ + vuint32_t R; + struct { + vuint32_t NCFSC63:2; /* NCF 63 state configuration */ + vuint32_t NCFSC62:2; /* NCF 62 state configuration */ + vuint32_t NCFSC61:2; /* NCF 61 state configuration */ + vuint32_t NCFSC60:2; /* NCF 60 state configuration */ + vuint32_t NCFSC59:2; /* NCF 59 state configuration */ + vuint32_t NCFSC58:2; /* NCF 58 state configuration */ + vuint32_t NCFSC57:2; /* NCF 57 state configuration */ + vuint32_t NCFSC56:2; /* NCF 56 state configuration */ + vuint32_t NCFSC55:2; /* NCF 55 state configuration */ + vuint32_t NCFSC54:2; /* NCF 54 state configuration */ + vuint32_t NCFSC53:2; /* NCF 53 state configuration */ + vuint32_t NCFSC52:2; /* NCF 52 state configuration */ + vuint32_t NCFSC51:2; /* NCF 51 state configuration */ + vuint32_t NCFSC50:2; /* NCF 50 state configuration */ + vuint32_t NCFSC49:2; /* NCF 49 state configuration */ + vuint32_t NCFSC48:2; /* NCF 48 state configuration */ + } B; + } FCCU_NCFS_CFG3_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 4 */ + vuint32_t R; + struct { + vuint32_t NCFSC79:2; /* NCF 79 state configuration */ + vuint32_t NCFSC78:2; /* NCF 78 state configuration */ + vuint32_t NCFSC77:2; /* NCF 77 state configuration */ + vuint32_t NCFSC76:2; /* NCF 76 state configuration */ + vuint32_t NCFSC75:2; /* NCF 75 state configuration */ + vuint32_t NCFSC74:2; /* NCF 74 state configuration */ + vuint32_t NCFSC73:2; /* NCF 73 state configuration */ + vuint32_t NCFSC72:2; /* NCF 72 state configuration */ + vuint32_t NCFSC71:2; /* NCF 71 state configuration */ + vuint32_t NCFSC70:2; /* NCF 70 state configuration */ + vuint32_t NCFSC69:2; /* NCF 69 state configuration */ + vuint32_t NCFSC68:2; /* NCF 68 state configuration */ + vuint32_t NCFSC67:2; /* NCF 67 state configuration */ + vuint32_t NCFSC66:2; /* NCF 66 state configuration */ + vuint32_t NCFSC65:2; /* NCF 65 state configuration */ + vuint32_t NCFSC64:2; /* NCF 64 state configuration */ + } B; + } FCCU_NCFS_CFG4_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 5 */ + vuint32_t R; + struct { + vuint32_t NCFSC95:2; /* NCF 95 state configuration */ + vuint32_t NCFSC94:2; /* NCF 94 state configuration */ + vuint32_t NCFSC93:2; /* NCF 93 state configuration */ + vuint32_t NCFSC92:2; /* NCF 92 state configuration */ + vuint32_t NCFSC91:2; /* NCF 91 state configuration */ + vuint32_t NCFSC90:2; /* NCF 90 state configuration */ + vuint32_t NCFSC89:2; /* NCF 89 state configuration */ + vuint32_t NCFSC88:2; /* NCF 88 state configuration */ + vuint32_t NCFSC87:2; /* NCF 87 state configuration */ + vuint32_t NCFSC86:2; /* NCF 86 state configuration */ + vuint32_t NCFSC85:2; /* NCF 85 state configuration */ + vuint32_t NCFSC84:2; /* NCF 84 state configuration */ + vuint32_t NCFSC83:2; /* NCF 83 state configuration */ + vuint32_t NCFSC82:2; /* NCF 82 state configuration */ + vuint32_t NCFSC81:2; /* NCF 81 state configuration */ + vuint32_t NCFSC80:2; /* NCF 80 state configuration */ + } B; + } FCCU_NCFS_CFG5_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 6 */ + vuint32_t R; + struct { + vuint32_t NCFSC111:2; /* NCF 111 state configuration */ + vuint32_t NCFSC110:2; /* NCF 110 state configuration */ + vuint32_t NCFSC109:2; /* NCF 109 state configuration */ + vuint32_t NCFSC108:2; /* NCF 108 state configuration */ + vuint32_t NCFSC107:2; /* NCF 107 state configuration */ + vuint32_t NCFSC106:2; /* NCF 106 state configuration */ + vuint32_t NCFSC105:2; /* NCF 105 state configuration */ + vuint32_t NCFSC104:2; /* NCF 104 state configuration */ + vuint32_t NCFSC103:2; /* NCF 103 state configuration */ + vuint32_t NCFSC102:2; /* NCF 102 state configuration */ + vuint32_t NCFSC101:2; /* NCF 101 state configuration */ + vuint32_t NCFSC100:2; /* NCF 100 state configuration */ + vuint32_t NCFSC99:2; /* NCF 99 state configuration */ + vuint32_t NCFSC98:2; /* NCF 98 state configuration */ + vuint32_t NCFSC97:2; /* NCF 97 state configuration */ + vuint32_t NCFSC96:2; /* NCF 96 state configuration */ + } B; + } FCCU_NCFS_CFG6_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 7 */ + vuint32_t R; + struct { + vuint32_t NCFSC127:2; /* NCF 127 state configuration */ + vuint32_t NCFSC126:2; /* NCF 126 state configuration */ + vuint32_t NCFSC125:2; /* NCF 125 state configuration */ + vuint32_t NCFSC124:2; /* NCF 124 state configuration */ + vuint32_t NCFSC123:2; /* NCF 123 state configuration */ + vuint32_t NCFSC122:2; /* NCF 122 state configuration */ + vuint32_t NCFSC121:2; /* NCF 121 state configuration */ + vuint32_t NCFSC120:2; /* NCF 120 state configuration */ + vuint32_t NCFSC119:2; /* NCF 119 state configuration */ + vuint32_t NCFSC118:2; /* NCF 118 state configuration */ + vuint32_t NCFSC117:2; /* NCF 117 state configuration */ + vuint32_t NCFSC116:2; /* NCF 116 state configuration */ + vuint32_t NCFSC115:2; /* NCF 115 state configuration */ + vuint32_t NCFSC114:2; /* NCF 114 state configuration */ + vuint32_t NCFSC113:2; /* NCF 113 state configuration */ + vuint32_t NCFSC112:2; /* NCF 112 state configuration */ + } B; + } FCCU_NCFS_CFG7_32B_tag; + + typedef union { /* FCCU CF Status Register 0 */ + vuint32_t R; + struct { + vuint32_t CFS31:1; /* CF 31 status */ + vuint32_t CFS30:1; /* CF 30 status */ + vuint32_t CFS29:1; /* CF 29 status */ + vuint32_t CFS28:1; /* CF 28 status */ + vuint32_t CFS27:1; /* CF 27 status */ + vuint32_t CFS26:1; /* CF 26 status */ + vuint32_t CFS25:1; /* CF 25 status */ + vuint32_t CFS24:1; /* CF 24 status */ + vuint32_t CFS23:1; /* CF 23 status */ + vuint32_t CFS22:1; /* CF 22 status */ + vuint32_t CFS21:1; /* CF 21 status */ + vuint32_t CFS20:1; /* CF 20 status */ + vuint32_t CFS19:1; /* CF 19 status */ + vuint32_t CFS18:1; /* CF 18 status */ + vuint32_t CFS17:1; /* CF 17 status */ + vuint32_t CFS16:1; /* CF 16 status */ + vuint32_t CFS15:1; /* CF 15 status */ + vuint32_t CFS14:1; /* CF 14 status */ + vuint32_t CFS13:1; /* CF 13 status */ + vuint32_t CFS12:1; /* CF 12 status */ + vuint32_t CFS11:1; /* CF 11 status */ + vuint32_t CFS10:1; /* CF 10 status */ + vuint32_t CFS9:1; /* CF 9 status */ + vuint32_t CFS8:1; /* CF 8 status */ + vuint32_t CFS7:1; /* CF 7 status */ + vuint32_t CFS6:1; /* CF 6 status */ + vuint32_t CFS5:1; /* CF 5 status */ + vuint32_t CFS4:1; /* CF 4 status */ + vuint32_t CFS3:1; /* CF 3 status */ + vuint32_t CFS2:1; /* CF 2 status */ + vuint32_t CFS1:1; /* CF 1 status */ + vuint32_t CFS0:1; /* CF 0 status */ + } B; + } FCCU_CFS0_32B_tag; + + typedef union { /* FCCU CF Status Register 1 */ + vuint32_t R; + struct { + vuint32_t CFS63:1; /* CF 63 status */ + vuint32_t CFS62:1; /* CF 62 status */ + vuint32_t CFS61:1; /* CF 61 status */ + vuint32_t CFS60:1; /* CF 60 status */ + vuint32_t CFS59:1; /* CF 59 status */ + vuint32_t CFS58:1; /* CF 58 status */ + vuint32_t CFS57:1; /* CF 57 status */ + vuint32_t CFS56:1; /* CF 56 status */ + vuint32_t CFS55:1; /* CF 55 status */ + vuint32_t CFS54:1; /* CF 54 status */ + vuint32_t CFS53:1; /* CF 53 status */ + vuint32_t CFS52:1; /* CF 52 status */ + vuint32_t CFS51:1; /* CF 51 status */ + vuint32_t CFS50:1; /* CF 50 status */ + vuint32_t CFS49:1; /* CF 49 status */ + vuint32_t CFS48:1; /* CF 48 status */ + vuint32_t CFS47:1; /* CF 47 status */ + vuint32_t CFS46:1; /* CF 46 status */ + vuint32_t CFS45:1; /* CF 45 status */ + vuint32_t CFS44:1; /* CF 44 status */ + vuint32_t CFS43:1; /* CF 43 status */ + vuint32_t CFS42:1; /* CF 42 status */ + vuint32_t CFS41:1; /* CF 41 status */ + vuint32_t CFS40:1; /* CF 40 status */ + vuint32_t CFS39:1; /* CF 39 status */ + vuint32_t CFS38:1; /* CF 38 status */ + vuint32_t CFS37:1; /* CF 37 status */ + vuint32_t CFS36:1; /* CF 36 status */ + vuint32_t CFS35:1; /* CF 35 status */ + vuint32_t CFS34:1; /* CF 34 status */ + vuint32_t CFS33:1; /* CF 33 status */ + vuint32_t CFS32:1; /* CF 32 status */ + } B; + } FCCU_CFS1_32B_tag; + + typedef union { /* FCCU CF Status Register 2 */ + vuint32_t R; + struct { + vuint32_t CFS95:1; /* CF 95 status */ + vuint32_t CFS94:1; /* CF 94 status */ + vuint32_t CFS93:1; /* CF 93 status */ + vuint32_t CFS92:1; /* CF 92 status */ + vuint32_t CFS91:1; /* CF 91 status */ + vuint32_t CFS90:1; /* CF 90 status */ + vuint32_t CFS89:1; /* CF 89 status */ + vuint32_t CFS88:1; /* CF 88 status */ + vuint32_t CFS87:1; /* CF 87 status */ + vuint32_t CFS86:1; /* CF 86 status */ + vuint32_t CFS85:1; /* CF 85 status */ + vuint32_t CFS84:1; /* CF 84 status */ + vuint32_t CFS83:1; /* CF 83 status */ + vuint32_t CFS82:1; /* CF 82 status */ + vuint32_t CFS81:1; /* CF 81 status */ + vuint32_t CFS80:1; /* CF 80 status */ + vuint32_t CFS79:1; /* CF 79 status */ + vuint32_t CFS78:1; /* CF 78 status */ + vuint32_t CFS77:1; /* CF 77 status */ + vuint32_t CFS76:1; /* CF 76 status */ + vuint32_t CFS75:1; /* CF 75 status */ + vuint32_t CFS74:1; /* CF 74 status */ + vuint32_t CFS73:1; /* CF 73 status */ + vuint32_t CFS72:1; /* CF 72 status */ + vuint32_t CFS71:1; /* CF 71 status */ + vuint32_t CFS70:1; /* CF 70 status */ + vuint32_t CFS69:1; /* CF 69 status */ + vuint32_t CFS68:1; /* CF 68 status */ + vuint32_t CFS67:1; /* CF 67 status */ + vuint32_t CFS66:1; /* CF 66 status */ + vuint32_t CFS65:1; /* CF 65 status */ + vuint32_t CFS64:1; /* CF 64 status */ + } B; + } FCCU_CFS2_32B_tag; + + typedef union { /* FCCU CF Status Register 3 */ + vuint32_t R; + struct { + vuint32_t CFS127:1; /* CF 127 status */ + vuint32_t CFS126:1; /* CF 126 status */ + vuint32_t CFS125:1; /* CF 125 status */ + vuint32_t CFS124:1; /* CF 124 status */ + vuint32_t CFS123:1; /* CF 123 status */ + vuint32_t CFS122:1; /* CF 122 status */ + vuint32_t CFS121:1; /* CF 121 status */ + vuint32_t CFS120:1; /* CF 120 status */ + vuint32_t CFS119:1; /* CF 119 status */ + vuint32_t CFS118:1; /* CF 118 status */ + vuint32_t CFS117:1; /* CF 117 status */ + vuint32_t CFS116:1; /* CF 116 status */ + vuint32_t CFS115:1; /* CF 115 status */ + vuint32_t CFS114:1; /* CF 114 status */ + vuint32_t CFS113:1; /* CF 113 status */ + vuint32_t CFS112:1; /* CF 112 status */ + vuint32_t CFS111:1; /* CF 111 status */ + vuint32_t CFS110:1; /* CF 110 status */ + vuint32_t CFS109:1; /* CF 109 status */ + vuint32_t CFS108:1; /* CF 108 status */ + vuint32_t CFS107:1; /* CF 107 status */ + vuint32_t CFS106:1; /* CF 106 status */ + vuint32_t CFS105:1; /* CF 105 status */ + vuint32_t CFS104:1; /* CF 104 status */ + vuint32_t CFS103:1; /* CF 103 status */ + vuint32_t CFS102:1; /* CF 102 status */ + vuint32_t CFS101:1; /* CF 101 status */ + vuint32_t CFS100:1; /* CF 100 status */ + vuint32_t CFS99:1; /* CF 99 status */ + vuint32_t CFS98:1; /* CF 98 status */ + vuint32_t CFS97:1; /* CF 97 status */ + vuint32_t CFS96:1; /* CF 96 status */ + } B; + } FCCU_CFS3_32B_tag; + + typedef union { /* FCCU_CFK - FCCU CF Key Register */ + vuint32_t R; + } FCCU_CFK_32B_tag; + + typedef union { /* FCCU NCF Status Register 0 */ + vuint32_t R; + struct { + vuint32_t NCFS31:1; /* NCF 31 status */ + vuint32_t NCFS30:1; /* NCF 30 status */ + vuint32_t NCFS29:1; /* NCF 29 status */ + vuint32_t NCFS28:1; /* NCF 28 status */ + vuint32_t NCFS27:1; /* NCF 27 status */ + vuint32_t NCFS26:1; /* NCF 26 status */ + vuint32_t NCFS25:1; /* NCF 25 status */ + vuint32_t NCFS24:1; /* NCF 24 status */ + vuint32_t NCFS23:1; /* NCF 23 status */ + vuint32_t NCFS22:1; /* NCF 22 status */ + vuint32_t NCFS21:1; /* NCF 21 status */ + vuint32_t NCFS20:1; /* NCF 20 status */ + vuint32_t NCFS19:1; /* NCF 19 status */ + vuint32_t NCFS18:1; /* NCF 18 status */ + vuint32_t NCFS17:1; /* NCF 17 status */ + vuint32_t NCFS16:1; /* NCF 16 status */ + vuint32_t NCFS15:1; /* NCF 15 status */ + vuint32_t NCFS14:1; /* NCF 14 status */ + vuint32_t NCFS13:1; /* NCF 13 status */ + vuint32_t NCFS12:1; /* NCF 12 status */ + vuint32_t NCFS11:1; /* NCF 11 status */ + vuint32_t NCFS10:1; /* NCF 10 status */ + vuint32_t NCFS9:1; /* NCF 9 status */ + vuint32_t NCFS8:1; /* NCF 8 status */ + vuint32_t NCFS7:1; /* NCF 7 status */ + vuint32_t NCFS6:1; /* NCF 6 status */ + vuint32_t NCFS5:1; /* NCF 5 status */ + vuint32_t NCFS4:1; /* NCF 4 status */ + vuint32_t NCFS3:1; /* NCF 3 status */ + vuint32_t NCFS2:1; /* NCF 2 status */ + vuint32_t NCFS1:1; /* NCF 1 status */ + vuint32_t NCFS0:1; /* NCF 0 status */ + } B; + } FCCU_NCFS0_32B_tag; + + typedef union { /* FCCU NCF Status Register 1 */ + vuint32_t R; + struct { + vuint32_t NCFS63:1; /* NCF 63 status */ + vuint32_t NCFS62:1; /* NCF 62 status */ + vuint32_t NCFS61:1; /* NCF 61 status */ + vuint32_t NCFS60:1; /* NCF 60 status */ + vuint32_t NCFS59:1; /* NCF 59 status */ + vuint32_t NCFS58:1; /* NCF 58 status */ + vuint32_t NCFS57:1; /* NCF 57 status */ + vuint32_t NCFS56:1; /* NCF 56 status */ + vuint32_t NCFS55:1; /* NCF 55 status */ + vuint32_t NCFS54:1; /* NCF 54 status */ + vuint32_t NCFS53:1; /* NCF 53 status */ + vuint32_t NCFS52:1; /* NCF 52 status */ + vuint32_t NCFS51:1; /* NCF 51 status */ + vuint32_t NCFS50:1; /* NCF 50 status */ + vuint32_t NCFS49:1; /* NCF 49 status */ + vuint32_t NCFS48:1; /* NCF 48 status */ + vuint32_t NCFS47:1; /* NCF 47 status */ + vuint32_t NCFS46:1; /* NCF 46 status */ + vuint32_t NCFS45:1; /* NCF 45 status */ + vuint32_t NCFS44:1; /* NCF 44 status */ + vuint32_t NCFS43:1; /* NCF 43 status */ + vuint32_t NCFS42:1; /* NCF 42 status */ + vuint32_t NCFS41:1; /* NCF 41 status */ + vuint32_t NCFS40:1; /* NCF 40 status */ + vuint32_t NCFS39:1; /* NCF 39 status */ + vuint32_t NCFS38:1; /* NCF 38 status */ + vuint32_t NCFS37:1; /* NCF 37 status */ + vuint32_t NCFS36:1; /* NCF 36 status */ + vuint32_t NCFS35:1; /* NCF 35 status */ + vuint32_t NCFS34:1; /* NCF 34 status */ + vuint32_t NCFS33:1; /* NCF 33 status */ + vuint32_t NCFS32:1; /* NCF 32 status */ + } B; + } FCCU_NCFS1_32B_tag; + + typedef union { /* FCCU NCF Status Register 2 */ + vuint32_t R; + struct { + vuint32_t NCFS95:1; /* NCF 95 status */ + vuint32_t NCFS94:1; /* NCF 94 status */ + vuint32_t NCFS93:1; /* NCF 93 status */ + vuint32_t NCFS92:1; /* NCF 92 status */ + vuint32_t NCFS91:1; /* NCF 91 status */ + vuint32_t NCFS90:1; /* NCF 90 status */ + vuint32_t NCFS89:1; /* NCF 89 status */ + vuint32_t NCFS88:1; /* NCF 88 status */ + vuint32_t NCFS87:1; /* NCF 87 status */ + vuint32_t NCFS86:1; /* NCF 86 status */ + vuint32_t NCFS85:1; /* NCF 85 status */ + vuint32_t NCFS84:1; /* NCF 84 status */ + vuint32_t NCFS83:1; /* NCF 83 status */ + vuint32_t NCFS82:1; /* NCF 82 status */ + vuint32_t NCFS81:1; /* NCF 81 status */ + vuint32_t NCFS80:1; /* NCF 80 status */ + vuint32_t NCFS79:1; /* NCF 79 status */ + vuint32_t NCFS78:1; /* NCF 78 status */ + vuint32_t NCFS77:1; /* NCF 77 status */ + vuint32_t NCFS76:1; /* NCF 76 status */ + vuint32_t NCFS75:1; /* NCF 75 status */ + vuint32_t NCFS74:1; /* NCF 74 status */ + vuint32_t NCFS73:1; /* NCF 73 status */ + vuint32_t NCFS72:1; /* NCF 72 status */ + vuint32_t NCFS71:1; /* NCF 71 status */ + vuint32_t NCFS70:1; /* NCF 70 status */ + vuint32_t NCFS69:1; /* NCF 69 status */ + vuint32_t NCFS68:1; /* NCF 68 status */ + vuint32_t NCFS67:1; /* NCF 67 status */ + vuint32_t NCFS66:1; /* NCF 66 status */ + vuint32_t NCFS65:1; /* NCF 65 status */ + vuint32_t NCFS64:1; /* NCF 64 status */ + } B; + } FCCU_NCFS2_32B_tag; + + typedef union { /* FCCU NCF Status Register 3 */ + vuint32_t R; + struct { + vuint32_t NCFS127:1; /* NCF 127 status */ + vuint32_t NCFS126:1; /* NCF 126 status */ + vuint32_t NCFS125:1; /* NCF 125 status */ + vuint32_t NCFS124:1; /* NCF 124 status */ + vuint32_t NCFS123:1; /* NCF 123 status */ + vuint32_t NCFS122:1; /* NCF 122 status */ + vuint32_t NCFS121:1; /* NCF 121 status */ + vuint32_t NCFS120:1; /* NCF 120 status */ + vuint32_t NCFS119:1; /* NCF 119 status */ + vuint32_t NCFS118:1; /* NCF 118 status */ + vuint32_t NCFS117:1; /* NCF 117 status */ + vuint32_t NCFS116:1; /* NCF 116 status */ + vuint32_t NCFS115:1; /* NCF 115 status */ + vuint32_t NCFS114:1; /* NCF 114 status */ + vuint32_t NCFS113:1; /* NCF 113 status */ + vuint32_t NCFS112:1; /* NCF 112 status */ + vuint32_t NCFS111:1; /* NCF 111 status */ + vuint32_t NCFS110:1; /* NCF 110 status */ + vuint32_t NCFS109:1; /* NCF 109 status */ + vuint32_t NCFS108:1; /* NCF 108 status */ + vuint32_t NCFS107:1; /* NCF 107 status */ + vuint32_t NCFS106:1; /* NCF 106 status */ + vuint32_t NCFS105:1; /* NCF 105 status */ + vuint32_t NCFS104:1; /* NCF 104 status */ + vuint32_t NCFS103:1; /* NCF 103 status */ + vuint32_t NCFS102:1; /* NCF 102 status */ + vuint32_t NCFS101:1; /* NCF 101 status */ + vuint32_t NCFS100:1; /* NCF 100 status */ + vuint32_t NCFS99:1; /* NCF 99 status */ + vuint32_t NCFS98:1; /* NCF 98 status */ + vuint32_t NCFS97:1; /* NCF 97 status */ + vuint32_t NCFS96:1; /* NCF 96 status */ + } B; + } FCCU_NCFS3_32B_tag; + + typedef union { /* FCCU_NCFK - FCCU NCF Key Register */ + vuint32_t R; + } FCCU_NCFK_32B_tag; + + typedef union { /* FCCU NCF Enable Register 0 */ + vuint32_t R; + struct { + vuint32_t NCFE31:1; /* NCF 31 enable */ + vuint32_t NCFE30:1; /* NCF 30 enable */ + vuint32_t NCFE29:1; /* NCF 29 enable */ + vuint32_t NCFE28:1; /* NCF 28 enable */ + vuint32_t NCFE27:1; /* NCF 27 enable */ + vuint32_t NCFE26:1; /* NCF 26 enable */ + vuint32_t NCFE25:1; /* NCF 25 enable */ + vuint32_t NCFE24:1; /* NCF 24 enable */ + vuint32_t NCFE23:1; /* NCF 23 enable */ + vuint32_t NCFE22:1; /* NCF 22 enable */ + vuint32_t NCFE21:1; /* NCF 21 enable */ + vuint32_t NCFE20:1; /* NCF 20 enable */ + vuint32_t NCFE19:1; /* NCF 19 enable */ + vuint32_t NCFE18:1; /* NCF 18 enable */ + vuint32_t NCFE17:1; /* NCF 17 enable */ + vuint32_t NCFE16:1; /* NCF 16 enable */ + vuint32_t NCFE15:1; /* NCF 15 enable */ + vuint32_t NCFE14:1; /* NCF 14 enable */ + vuint32_t NCFE13:1; /* NCF 13 enable */ + vuint32_t NCFE12:1; /* NCF 12 enable */ + vuint32_t NCFE11:1; /* NCF 11 enable */ + vuint32_t NCFE10:1; /* NCF 10 enable */ + vuint32_t NCFE9:1; /* NCF 9 enable */ + vuint32_t NCFE8:1; /* NCF 8 enable */ + vuint32_t NCFE7:1; /* NCF 7 enable */ + vuint32_t NCFE6:1; /* NCF 6 enable */ + vuint32_t NCFE5:1; /* NCF 5 enable */ + vuint32_t NCFE4:1; /* NCF 4 enable */ + vuint32_t NCFE3:1; /* NCF 3 enable */ + vuint32_t NCFE2:1; /* NCF 2 enable */ + vuint32_t NCFE1:1; /* NCF 1 enable */ + vuint32_t NCFE0:1; /* NCF 0 enable */ + } B; + } FCCU_NCFE0_32B_tag; + + typedef union { /* FCCU NCF Enable Register 1 */ + vuint32_t R; + struct { + vuint32_t NCFE63:1; /* NCF 63 enable */ + vuint32_t NCFE62:1; /* NCF 62 enable */ + vuint32_t NCFE61:1; /* NCF 61 enable */ + vuint32_t NCFE60:1; /* NCF 60 enable */ + vuint32_t NCFE59:1; /* NCF 59 enable */ + vuint32_t NCFE58:1; /* NCF 58 enable */ + vuint32_t NCFE57:1; /* NCF 57 enable */ + vuint32_t NCFE56:1; /* NCF 56 enable */ + vuint32_t NCFE55:1; /* NCF 55 enable */ + vuint32_t NCFE54:1; /* NCF 54 enable */ + vuint32_t NCFE53:1; /* NCF 53 enable */ + vuint32_t NCFE52:1; /* NCF 52 enable */ + vuint32_t NCFE51:1; /* NCF 51 enable */ + vuint32_t NCFE50:1; /* NCF 50 enable */ + vuint32_t NCFE49:1; /* NCF 49 enable */ + vuint32_t NCFE48:1; /* NCF 48 enable */ + vuint32_t NCFE47:1; /* NCF 47 enable */ + vuint32_t NCFE46:1; /* NCF 46 enable */ + vuint32_t NCFE45:1; /* NCF 45 enable */ + vuint32_t NCFE44:1; /* NCF 44 enable */ + vuint32_t NCFE43:1; /* NCF 43 enable */ + vuint32_t NCFE42:1; /* NCF 42 enable */ + vuint32_t NCFE41:1; /* NCF 41 enable */ + vuint32_t NCFE40:1; /* NCF 40 enable */ + vuint32_t NCFE39:1; /* NCF 39 enable */ + vuint32_t NCFE38:1; /* NCF 38 enable */ + vuint32_t NCFE37:1; /* NCF 37 enable */ + vuint32_t NCFE36:1; /* NCF 36 enable */ + vuint32_t NCFE35:1; /* NCF 35 enable */ + vuint32_t NCFE34:1; /* NCF 34 enable */ + vuint32_t NCFE33:1; /* NCF 33 enable */ + vuint32_t NCFE32:1; /* NCF 32 enable */ + } B; + } FCCU_NCFE1_32B_tag; + + typedef union { /* FCCU NCF Enable Register 2 */ + vuint32_t R; + struct { + vuint32_t NCFE95:1; /* NCF 95 enable */ + vuint32_t NCFE94:1; /* NCF 94 enable */ + vuint32_t NCFE93:1; /* NCF 93 enable */ + vuint32_t NCFE92:1; /* NCF 92 enable */ + vuint32_t NCFE91:1; /* NCF 91 enable */ + vuint32_t NCFE90:1; /* NCF 90 enable */ + vuint32_t NCFE89:1; /* NCF 89 enable */ + vuint32_t NCFE88:1; /* NCF 88 enable */ + vuint32_t NCFE87:1; /* NCF 87 enable */ + vuint32_t NCFE86:1; /* NCF 86 enable */ + vuint32_t NCFE85:1; /* NCF 85 enable */ + vuint32_t NCFE84:1; /* NCF 84 enable */ + vuint32_t NCFE83:1; /* NCF 83 enable */ + vuint32_t NCFE82:1; /* NCF 82 enable */ + vuint32_t NCFE81:1; /* NCF 81 enable */ + vuint32_t NCFE80:1; /* NCF 80 enable */ + vuint32_t NCFE79:1; /* NCF 79 enable */ + vuint32_t NCFE78:1; /* NCF 78 enable */ + vuint32_t NCFE77:1; /* NCF 77 enable */ + vuint32_t NCFE76:1; /* NCF 76 enable */ + vuint32_t NCFE75:1; /* NCF 75 enable */ + vuint32_t NCFE74:1; /* NCF 74 enable */ + vuint32_t NCFE73:1; /* NCF 73 enable */ + vuint32_t NCFE72:1; /* NCF 72 enable */ + vuint32_t NCFE71:1; /* NCF 71 enable */ + vuint32_t NCFE70:1; /* NCF 70 enable */ + vuint32_t NCFE69:1; /* NCF 69 enable */ + vuint32_t NCFE68:1; /* NCF 68 enable */ + vuint32_t NCFE67:1; /* NCF 67 enable */ + vuint32_t NCFE66:1; /* NCF 66 enable */ + vuint32_t NCFE65:1; /* NCF 65 enable */ + vuint32_t NCFE64:1; /* NCF 64 enable */ + } B; + } FCCU_NCFE2_32B_tag; + + typedef union { /* FCCU NCF Enable Register 3 */ + vuint32_t R; + struct { + vuint32_t NCFE127:1; /* NCF 127 enable */ + vuint32_t NCFE126:1; /* NCF 126 enable */ + vuint32_t NCFE125:1; /* NCF 125 enable */ + vuint32_t NCFE124:1; /* NCF 124 enable */ + vuint32_t NCFE123:1; /* NCF 123 enable */ + vuint32_t NCFE122:1; /* NCF 122 enable */ + vuint32_t NCFE121:1; /* NCF 121 enable */ + vuint32_t NCFE120:1; /* NCF 120 enable */ + vuint32_t NCFE119:1; /* NCF 119 enable */ + vuint32_t NCFE118:1; /* NCF 118 enable */ + vuint32_t NCFE117:1; /* NCF 117 enable */ + vuint32_t NCFE116:1; /* NCF 116 enable */ + vuint32_t NCFE115:1; /* NCF 115 enable */ + vuint32_t NCFE114:1; /* NCF 114 enable */ + vuint32_t NCFE113:1; /* NCF 113 enable */ + vuint32_t NCFE112:1; /* NCF 112 enable */ + vuint32_t NCFE111:1; /* NCF 111 enable */ + vuint32_t NCFE110:1; /* NCF 110 enable */ + vuint32_t NCFE109:1; /* NCF 109 enable */ + vuint32_t NCFE108:1; /* NCF 108 enable */ + vuint32_t NCFE107:1; /* NCF 107 enable */ + vuint32_t NCFE106:1; /* NCF 106 enable */ + vuint32_t NCFE105:1; /* NCF 105 enable */ + vuint32_t NCFE104:1; /* NCF 104 enable */ + vuint32_t NCFE103:1; /* NCF 103 enable */ + vuint32_t NCFE102:1; /* NCF 102 enable */ + vuint32_t NCFE101:1; /* NCF 101 enable */ + vuint32_t NCFE100:1; /* NCF 100 enable */ + vuint32_t NCFE99:1; /* NCF 99 enable */ + vuint32_t NCFE98:1; /* NCF 98 enable */ + vuint32_t NCFE97:1; /* NCF 97 enable */ + vuint32_t NCFE96:1; /* NCF 96 enable */ + } B; + } FCCU_NCFE3_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 0 */ + vuint32_t R; + struct { + vuint32_t NCFTOE31:1; /* NCF 31 time-out enable */ + vuint32_t NCFTOE30:1; /* NCF 30 time-out enable */ + vuint32_t NCFTOE29:1; /* NCF 29 time-out enable */ + vuint32_t NCFTOE28:1; /* NCF 28 time-out enable */ + vuint32_t NCFTOE27:1; /* NCF 27 time-out enable */ + vuint32_t NCFTOE26:1; /* NCF 26 time-out enable */ + vuint32_t NCFTOE25:1; /* NCF 25 time-out enable */ + vuint32_t NCFTOE24:1; /* NCF 24 time-out enable */ + vuint32_t NCFTOE23:1; /* NCF 23 time-out enable */ + vuint32_t NCFTOE22:1; /* NCF 22 time-out enable */ + vuint32_t NCFTOE21:1; /* NCF 21 time-out enable */ + vuint32_t NCFTOE20:1; /* NCF 20 time-out enable */ + vuint32_t NCFTOE19:1; /* NCF 19 time-out enable */ + vuint32_t NCFTOE18:1; /* NCF 18 time-out enable */ + vuint32_t NCFTOE17:1; /* NCF 17 time-out enable */ + vuint32_t NCFTOE16:1; /* NCF 16 time-out enable */ + vuint32_t NCFTOE15:1; /* NCF 15 time-out enable */ + vuint32_t NCFTOE14:1; /* NCF 14 time-out enable */ + vuint32_t NCFTOE13:1; /* NCF 13 time-out enable */ + vuint32_t NCFTOE12:1; /* NCF 12 time-out enable */ + vuint32_t NCFTOE11:1; /* NCF 11 time-out enable */ + vuint32_t NCFTOE10:1; /* NCF 10 time-out enable */ + vuint32_t NCFTOE9:1; /* NCF 9 time-out enable */ + vuint32_t NCFTOE8:1; /* NCF 8 time-out enable */ + vuint32_t NCFTOE7:1; /* NCF 7 time-out enable */ + vuint32_t NCFTOE6:1; /* NCF 6 time-out enable */ + vuint32_t NCFTOE5:1; /* NCF 5 time-out enable */ + vuint32_t NCFTOE4:1; /* NCF 4 time-out enable */ + vuint32_t NCFTOE3:1; /* NCF 3 time-out enable */ + vuint32_t NCFTOE2:1; /* NCF 2 time-out enable */ + vuint32_t NCFTOE1:1; /* NCF 1 time-out enable */ + vuint32_t NCFTOE0:1; /* NCF 0 time-out enable */ + } B; + } FCCU_NCF_TOE0_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 1 */ + vuint32_t R; + struct { + vuint32_t NCFTOE63:1; /* NCF 63 time-out enable */ + vuint32_t NCFTOE62:1; /* NCF 62 time-out enable */ + vuint32_t NCFTOE61:1; /* NCF 61 time-out enable */ + vuint32_t NCFTOE60:1; /* NCF 60 time-out enable */ + vuint32_t NCFTOE59:1; /* NCF 59 time-out enable */ + vuint32_t NCFTOE58:1; /* NCF 58 time-out enable */ + vuint32_t NCFTOE57:1; /* NCF 57 time-out enable */ + vuint32_t NCFTOE56:1; /* NCF 56 time-out enable */ + vuint32_t NCFTOE55:1; /* NCF 55 time-out enable */ + vuint32_t NCFTOE54:1; /* NCF 54 time-out enable */ + vuint32_t NCFTOE53:1; /* NCF 53 time-out enable */ + vuint32_t NCFTOE52:1; /* NCF 52 time-out enable */ + vuint32_t NCFTOE51:1; /* NCF 51 time-out enable */ + vuint32_t NCFTOE50:1; /* NCF 50 time-out enable */ + vuint32_t NCFTOE49:1; /* NCF 49 time-out enable */ + vuint32_t NCFTOE48:1; /* NCF 48 time-out enable */ + vuint32_t NCFTOE47:1; /* NCF 47 time-out enable */ + vuint32_t NCFTOE46:1; /* NCF 46 time-out enable */ + vuint32_t NCFTOE45:1; /* NCF 45 time-out enable */ + vuint32_t NCFTOE44:1; /* NCF 44 time-out enable */ + vuint32_t NCFTOE43:1; /* NCF 43 time-out enable */ + vuint32_t NCFTOE42:1; /* NCF 42 time-out enable */ + vuint32_t NCFTOE41:1; /* NCF 41 time-out enable */ + vuint32_t NCFTOE40:1; /* NCF 40 time-out enable */ + vuint32_t NCFTOE39:1; /* NCF 39 time-out enable */ + vuint32_t NCFTOE38:1; /* NCF 38 time-out enable */ + vuint32_t NCFTOE37:1; /* NCF 37 time-out enable */ + vuint32_t NCFTOE36:1; /* NCF 36 time-out enable */ + vuint32_t NCFTOE35:1; /* NCF 35 time-out enable */ + vuint32_t NCFTOE34:1; /* NCF 34 time-out enable */ + vuint32_t NCFTOE33:1; /* NCF 33 time-out enable */ + vuint32_t NCFTOE32:1; /* NCF 32 time-out enable */ + } B; + } FCCU_NCF_TOE1_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 2 */ + vuint32_t R; + struct { + vuint32_t NCFTOE95:1; /* NCF 95 time-out enable */ + vuint32_t NCFTOE94:1; /* NCF 94 time-out enable */ + vuint32_t NCFTOE93:1; /* NCF 93 time-out enable */ + vuint32_t NCFTOE92:1; /* NCF 92 time-out enable */ + vuint32_t NCFTOE91:1; /* NCF 91 time-out enable */ + vuint32_t NCFTOE90:1; /* NCF 90 time-out enable */ + vuint32_t NCFTOE89:1; /* NCF 89 time-out enable */ + vuint32_t NCFTOE88:1; /* NCF 88 time-out enable */ + vuint32_t NCFTOE87:1; /* NCF 87 time-out enable */ + vuint32_t NCFTOE86:1; /* NCF 86 time-out enable */ + vuint32_t NCFTOE85:1; /* NCF 85 time-out enable */ + vuint32_t NCFTOE84:1; /* NCF 84 time-out enable */ + vuint32_t NCFTOE83:1; /* NCF 83 time-out enable */ + vuint32_t NCFTOE82:1; /* NCF 82 time-out enable */ + vuint32_t NCFTOE81:1; /* NCF 81 time-out enable */ + vuint32_t NCFTOE80:1; /* NCF 80 time-out enable */ + vuint32_t NCFTOE79:1; /* NCF 79 time-out enable */ + vuint32_t NCFTOE78:1; /* NCF 78 time-out enable */ + vuint32_t NCFTOE77:1; /* NCF 77 time-out enable */ + vuint32_t NCFTOE76:1; /* NCF 76 time-out enable */ + vuint32_t NCFTOE75:1; /* NCF 75 time-out enable */ + vuint32_t NCFTOE74:1; /* NCF 74 time-out enable */ + vuint32_t NCFTOE73:1; /* NCF 73 time-out enable */ + vuint32_t NCFTOE72:1; /* NCF 72 time-out enable */ + vuint32_t NCFTOE71:1; /* NCF 71 time-out enable */ + vuint32_t NCFTOE70:1; /* NCF 70 time-out enable */ + vuint32_t NCFTOE69:1; /* NCF 69 time-out enable */ + vuint32_t NCFTOE68:1; /* NCF 68 time-out enable */ + vuint32_t NCFTOE67:1; /* NCF 67 time-out enable */ + vuint32_t NCFTOE66:1; /* NCF 66 time-out enable */ + vuint32_t NCFTOE65:1; /* NCF 65 time-out enable */ + vuint32_t NCFTOE64:1; /* NCF 64 time-out enable */ + } B; + } FCCU_NCF_TOE2_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 3 */ + vuint32_t R; + struct { + vuint32_t NCFTOE127:1; /* NCF 127 time-out enable */ + vuint32_t NCFTOE126:1; /* NCF 126 time-out enable */ + vuint32_t NCFTOE125:1; /* NCF 125 time-out enable */ + vuint32_t NCFTOE124:1; /* NCF 124 time-out enable */ + vuint32_t NCFTOE123:1; /* NCF 123 time-out enable */ + vuint32_t NCFTOE122:1; /* NCF 122 time-out enable */ + vuint32_t NCFTOE121:1; /* NCF 121 time-out enable */ + vuint32_t NCFTOE120:1; /* NCF 120 time-out enable */ + vuint32_t NCFTOE119:1; /* NCF 119 time-out enable */ + vuint32_t NCFTOE118:1; /* NCF 118 time-out enable */ + vuint32_t NCFTOE117:1; /* NCF 117 time-out enable */ + vuint32_t NCFTOE116:1; /* NCF 116 time-out enable */ + vuint32_t NCFTOE115:1; /* NCF 115 time-out enable */ + vuint32_t NCFTOE114:1; /* NCF 114 time-out enable */ + vuint32_t NCFTOE113:1; /* NCF 113 time-out enable */ + vuint32_t NCFTOE112:1; /* NCF 112 time-out enable */ + vuint32_t NCFTOE111:1; /* NCF 111 time-out enable */ + vuint32_t NCFTOE110:1; /* NCF 110 time-out enable */ + vuint32_t NCFTOE109:1; /* NCF 109 time-out enable */ + vuint32_t NCFTOE108:1; /* NCF 108 time-out enable */ + vuint32_t NCFTOE107:1; /* NCF 107 time-out enable */ + vuint32_t NCFTOE106:1; /* NCF 106 time-out enable */ + vuint32_t NCFTOE105:1; /* NCF 105 time-out enable */ + vuint32_t NCFTOE104:1; /* NCF 104 time-out enable */ + vuint32_t NCFTOE103:1; /* NCF 103 time-out enable */ + vuint32_t NCFTOE102:1; /* NCF 102 time-out enable */ + vuint32_t NCFTOE101:1; /* NCF 101 time-out enable */ + vuint32_t NCFTOE100:1; /* NCF 100 time-out enable */ + vuint32_t NCFTOE99:1; /* NCF 99 time-out enable */ + vuint32_t NCFTOE98:1; /* NCF 98 time-out enable */ + vuint32_t NCFTOE97:1; /* NCF 97 time-out enable */ + vuint32_t NCFTOE96:1; /* NCF 96 time-out enable */ + } B; + } FCCU_NCF_TOE3_32B_tag; + + typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + vuint32_t R; + } FCCU_NCF_TO_32B_tag; + + typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t TO:3; /* Configuration time-out */ + } B; + } FCCU_CFG_TO_32B_tag; + + typedef union { /* FCCU_EINOUT - FCCU IO Control Register */ + vuint32_t R; + struct { + vuint32_t:26; + vuint32_t EIN1:1; /* Error input 1 */ + vuint32_t EIN0:1; /* Error input 0 */ + vuint32_t:2; + vuint32_t EOUT1:1; /* Error out 1 */ + vuint32_t EOUT0:1; /* Error out 0 */ + } B; + } FCCU_EINOUT_32B_tag; + + typedef union { /* FCCU_STAT - FCCU Status Register */ + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t STATUS:3; /* FCCU status */ + } B; + } FCCU_STAT_32B_tag; + + typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */ + } B; + } FCCU_NAFS_32B_tag; + + typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */ + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t AFFS_SRC:2; /* Fault source */ + vuint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */ + } B; + } FCCU_AFFS_32B_tag; + + typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */ + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t NFFS_SRC:2; /* Fault source */ + vuint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */ + } B; + } FCCU_NFFS_32B_tag; + + typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */ + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */ + } B; + } FCCU_FAFS_32B_tag; + + typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */ + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t RCCS1:1; /* RCC1 Status */ + vuint32_t RCCS0:1; /* RCC0 Status */ + } B; + } FCCU_SCFS_32B_tag; + + typedef union { /* FCCU_CFF - FCCU CF Fake Register */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t FCFC:7; /* Fake critical fault code */ + } B; + } FCCU_CFF_32B_tag; + + typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */ + vuint32_t R; + struct { + vuint32_t:25; + vuint32_t FNCFC:7; /* Fake non-critical fault code */ + } B; + } FCCU_NCFF_32B_tag; + + typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t NMI_STAT:1; /* NMI Interrupt Status */ + vuint32_t ALRM_STAT:1; /* Alarm Interrupt Status */ + vuint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */ + } B; + } FCCU_IRQ_STAT_32B_tag; + + typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */ + } B; + } FCCU_IRQ_EN_32B_tag; + + typedef union { /* FCCU_XTMR - FCCU XTMR Register */ + vuint32_t R; + struct { + vuint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */ + } B; + } FCCU_XTMR_32B_tag; + + typedef union { /* FCCU_MCS - FCCU MCS Register */ + vuint32_t R; + struct { + vuint32_t VL3:1; /* Valid */ + vuint32_t FS3:1; /* Fault Status */ + vuint32_t:2; + vuint32_t MCS3:4; /* Magic Carpet oldest state */ + vuint32_t VL2:1; /* Valid */ + vuint32_t FS2:1; /* Fault Status */ + vuint32_t:2; + vuint32_t MCS2:4; /* Magic Carpet previous-previous state */ + vuint32_t VL1:1; /* Valid */ + vuint32_t FS1:1; /* Fault Status */ + vuint32_t:2; + vuint32_t MCS1:4; /* Magic Carpet previous state */ + vuint32_t VL0:1; /* Valid */ + vuint32_t FS0:1; /* Fault Status */ + vuint32_t:2; + vuint32_t MCS0:4; /* Magic Carpet latest state */ + } B; + } FCCU_MCS_32B_tag; + + + /* Register layout for generated register(s) CF_CFG... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_CF_CFG_32B_tag; + + + /* Register layout for generated register(s) NCF_CFG... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_NCF_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS_CFG... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_CFS_CFG_32B_tag; + + + /* Register layout for generated register(s) NCFS_CFG... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_NCFS_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_CFS_32B_tag; + + + /* Register layout for generated register(s) NCFS... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_NCFS_32B_tag; + + + /* Register layout for generated register(s) NCFE... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_NCFE_32B_tag; + + + /* Register layout for generated register(s) NCF_TOE... */ + + typedef union { /* */ + vuint32_t R; + } FCCU_NCF_TOE_32B_tag; + + + + typedef struct FCCU_struct_tag { /* start of FCCU_tag */ + /* FCCU Control Register */ + FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* FCCU CTRL Key Register */ + FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */ + /* FCCU Configuration Register */ + FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */ + union { + FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */ + + struct { + /* FCCU CF Configuration Register 0 */ + FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */ + /* FCCU CF Configuration Register 1 */ + FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */ + /* FCCU CF Configuration Register 2 */ + FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */ + /* FCCU CF Configuration Register 3 */ + FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */ + + struct { + /* FCCU NCF Configuration Register 0 */ + FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */ + /* FCCU NCF Configuration Register 1 */ + FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */ + /* FCCU NCF Configuration Register 2 */ + FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */ + /* FCCU NCF Configuration Register 3 */ + FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */ + + struct { + /* FCCU CFS Configuration Register 0 */ + FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */ + /* FCCU CFS Configuration Register 1 */ + FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */ + /* FCCU CFS Configuration Register 2 */ + FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */ + /* FCCU CFS Configuration Register 3 */ + FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */ + /* FCCU CFS Configuration Register 4 */ + FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */ + /* FCCU CFS Configuration Register 5 */ + FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */ + /* FCCU CFS Configuration Register 6 */ + FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */ + /* FCCU CFS Configuration Register 7 */ + FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */ + }; + + }; + union { + FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* FCCU NCFS Configuration Register 0 */ + FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */ + /* FCCU NCFS Configuration Register 1 */ + FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */ + /* FCCU NCFS Configuration Register 2 */ + FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */ + /* FCCU NCFS Configuration Register 3 */ + FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */ + /* FCCU NCFS Configuration Register 4 */ + FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */ + /* FCCU NCFS Configuration Register 5 */ + FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */ + /* FCCU NCFS Configuration Register 6 */ + FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */ + /* FCCU NCFS Configuration Register 7 */ + FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */ + + struct { + /* FCCU CF Status Register 0 */ + FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */ + /* FCCU CF Status Register 1 */ + FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */ + /* FCCU CF Status Register 2 */ + FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */ + /* FCCU CF Status Register 3 */ + FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */ + }; + + }; + /* FCCU_CFK - FCCU CF Key Register */ + FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */ + union { + FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */ + + struct { + /* FCCU NCF Status Register 0 */ + FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */ + /* FCCU NCF Status Register 1 */ + FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */ + /* FCCU NCF Status Register 2 */ + FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */ + /* FCCU NCF Status Register 3 */ + FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */ + }; + + }; + /* FCCU_NCFK - FCCU NCF Key Register */ + FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */ + union { + FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */ + + struct { + /* FCCU NCF Enable Register 0 */ + FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */ + /* FCCU NCF Enable Register 1 */ + FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */ + /* FCCU NCF Enable Register 2 */ + FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */ + /* FCCU NCF Enable Register 3 */ + FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */ + + struct { + /* FCCU NCF Time-out Enable Register 0 */ + FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 1 */ + FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 2 */ + FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */ + /* FCCU NCF Time-out Enable Register 3 */ + FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */ + }; + + }; + /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */ + /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */ + /* FCCU_EINOUT - FCCU IO Control Register */ + FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */ + /* FCCU_STAT - FCCU Status Register */ + FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */ + /* FCCU_NAFS - FCCU NA Freeze Status Register */ + FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */ + /* FCCU_AFFS - FCCU AF Freeze Status Register */ + FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */ + /* FCCU_NFFS - FCCU NF Freeze Status Register */ + FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */ + /* FCCU_FAFS - FCCU FA Freeze Status Register */ + FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */ + /* FCCU_SCFS - FCCU SC Freeze Status Register */ + FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */ + /* FCCU_CFF - FCCU CF Fake Register */ + FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */ + /* FCCU_NCFF - FCCU NCF Fake Register */ + FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */ + /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */ + /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */ + /* FCCU_XTMR - FCCU XTMR Register */ + FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */ + /* FCCU_MCS - FCCU MCS Register */ + FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */ + } FCCU_tag; + + +#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SGENDIG */ +/* */ +/****************************************************************/ + + typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */ + vuint32_t R; + struct { + vuint32_t LDOS:1; /* Operation Status */ + vuint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */ + vuint32_t:2; + vuint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */ + vuint32_t:5; + vuint32_t S0H1:1; /* Operation Status */ + vuint32_t PDS:1; /* Operation Status */ + vuint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */ + } B; + } SGENDIG_CTRL_32B_tag; + + typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t SERR:1; /* Sine wave generator Error bit */ + vuint32_t:3; + vuint32_t FERR:1; /* Sine wave generator Force Error bit */ + vuint32_t:19; + } B; + } SGENDIG_IRQE_32B_tag; + + + + typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */ + /* SGENDIG_CTRL - SGENDIG Control Register */ + SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */ + } SGENDIG_tag; + + +#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL) + + + +/****************************************************************/ +/* */ +/* Module: AIPS */ +/* */ +/****************************************************************/ + + typedef union { /* MPROT - Master Privilege Registers */ + vuint32_t R; + struct { + vuint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */ + vuint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */ + vuint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */ + vuint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */ + vuint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */ + vuint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */ + vuint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */ + vuint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */ + vuint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */ + vuint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */ + vuint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */ + vuint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */ + vuint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */ + vuint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */ + vuint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */ + vuint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */ + vuint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */ + vuint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */ + vuint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */ + vuint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */ + vuint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */ + vuint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */ + vuint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */ + vuint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */ + vuint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */ + vuint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */ + vuint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */ + vuint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */ + vuint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */ + vuint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */ + vuint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */ + vuint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */ + } B; + } AIPS_MPROT_32B_tag; + + typedef union { /* PACR0_7 - Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t PACR0_BW:1; /* Buffer Writes */ + vuint32_t PACR0_SP:1; /* Supervisor Protect */ + vuint32_t PACR0_WP:1; /* Write Protect */ + vuint32_t PACR0_TP:1; /* Trusted Protect */ + vuint32_t PACR1_BW:1; /* Buffer Writes */ + vuint32_t PACR1_SP:1; /* Supervisor Protect */ + vuint32_t PACR1_WP:1; /* Write Protect */ + vuint32_t PACR1_TP:1; /* Trusted Protect */ + vuint32_t PACR2_BW:1; /* Buffer Writes */ + vuint32_t PACR2_SP:1; /* Supervisor Protect */ + vuint32_t PACR2_WP:1; /* Write Protect */ + vuint32_t PACR2_TP:1; /* Trusted Protect */ + vuint32_t PACR3_BW:1; /* Buffer Writes */ + vuint32_t PACR3_SP:1; /* Supervisor Protect */ + vuint32_t PACR3_WP:1; /* Write Protect */ + vuint32_t PACR3_TP:1; /* Trusted Protect */ + vuint32_t PACR4_BW:1; /* Buffer Writes */ + vuint32_t PACR4_SP:1; /* Supervisor Protect */ + vuint32_t PACR4_WP:1; /* Write Protect */ + vuint32_t PACR4_TP:1; /* Trusted Protect */ + vuint32_t PACR5_BW:1; /* Buffer Writes */ + vuint32_t PACR5_SP:1; /* Supervisor Protect */ + vuint32_t PACR5_WP:1; /* Write Protect */ + vuint32_t PACR5_TP:1; /* Trusted Protect */ + vuint32_t PACR6_BW:1; /* Buffer Writes */ + vuint32_t PACR6_SP:1; /* Supervisor Protect */ + vuint32_t PACR6_WP:1; /* Write Protect */ + vuint32_t PACR6_TP:1; /* Trusted Protect */ + vuint32_t PACR7_BW:1; /* Buffer Writes */ + vuint32_t PACR7_SP:1; /* Supervisor Protect */ + vuint32_t PACR7_WP:1; /* Write Protect */ + vuint32_t PACR7_TP:1; /* Trusted Protect */ + } B; + } AIPS_PACR0_7_32B_tag; + + typedef union { /* PACR8_15 - Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t PACR8_BW:1; /* Buffer Writes */ + vuint32_t PACR8_SP:1; /* Supervisor Protect */ + vuint32_t PACR8_WP:1; /* Write Protect */ + vuint32_t PACR8_TP:1; /* Trusted Protect */ + vuint32_t PACR9_BW:1; /* Buffer Writes */ + vuint32_t PACR9_SP:1; /* Supervisor Protect */ + vuint32_t PACR9_WP:1; /* Write Protect */ + vuint32_t PACR9_TP:1; /* Trusted Protect */ + vuint32_t PACR10_BW:1; /* Buffer Writes */ + vuint32_t PACR10_SP:1; /* Supervisor Protect */ + vuint32_t PACR10_WP:1; /* Write Protect */ + vuint32_t PACR10_TP:1; /* Trusted Protect */ + vuint32_t PACR11_BW:1; /* Buffer Writes */ + vuint32_t PACR11_SP:1; /* Supervisor Protect */ + vuint32_t PACR11_WP:1; /* Write Protect */ + vuint32_t PACR11_TP:1; /* Trusted Protect */ + vuint32_t PACR12_BW:1; /* Buffer Writes */ + vuint32_t PACR12_SP:1; /* Supervisor Protect */ + vuint32_t PACR12_WP:1; /* Write Protect */ + vuint32_t PACR12_TP:1; /* Trusted Protect */ + vuint32_t PACR13_BW:1; /* Buffer Writes */ + vuint32_t PACR13_SP:1; /* Supervisor Protect */ + vuint32_t PACR13_WP:1; /* Write Protect */ + vuint32_t PACR13_TP:1; /* Trusted Protect */ + vuint32_t PACR14_BW:1; /* Buffer Writes */ + vuint32_t PACR14_SP:1; /* Supervisor Protect */ + vuint32_t PACR14_WP:1; /* Write Protect */ + vuint32_t PACR14_TP:1; /* Trusted Protect */ + vuint32_t PACR15_BW:1; /* Buffer Writes */ + vuint32_t PACR15_SP:1; /* Supervisor Protect */ + vuint32_t PACR15_WP:1; /* Write Protect */ + vuint32_t PACR15_TP:1; /* Trusted Protect */ + } B; + } AIPS_PACR8_15_32B_tag; + + typedef union { /* PACR16_23 - Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t PACR16_BW:1; /* Buffer Writes */ + vuint32_t PACR16_SP:1; /* Supervisor Protect */ + vuint32_t PACR16_WP:1; /* Write Protect */ + vuint32_t PACR16_TP:1; /* Trusted Protect */ + vuint32_t PACR17_BW:1; /* Buffer Writes */ + vuint32_t PACR17_SP:1; /* Supervisor Protect */ + vuint32_t PACR17_WP:1; /* Write Protect */ + vuint32_t PACR17_TP:1; /* Trusted Protect */ + vuint32_t PACR18_BW:1; /* Buffer Writes */ + vuint32_t PACR18_SP:1; /* Supervisor Protect */ + vuint32_t PACR18_WP:1; /* Write Protect */ + vuint32_t PACR18_TP:1; /* Trusted Protect */ + vuint32_t PACR19_BW:1; /* Buffer Writes */ + vuint32_t PACR19_SP:1; /* Supervisor Protect */ + vuint32_t PACR19_WP:1; /* Write Protect */ + vuint32_t PACR19_TP:1; /* Trusted Protect */ + vuint32_t PACR20_BW:1; /* Buffer Writes */ + vuint32_t PACR20_SP:1; /* Supervisor Protect */ + vuint32_t PACR20_WP:1; /* Write Protect */ + vuint32_t PACR20_TP:1; /* Trusted Protect */ + vuint32_t PACR21_BW:1; /* Buffer Writes */ + vuint32_t PACR21_SP:1; /* Supervisor Protect */ + vuint32_t PACR21_WP:1; /* Write Protect */ + vuint32_t PACR21_TP:1; /* Trusted Protect */ + vuint32_t PACR22_BW:1; /* Buffer Writes */ + vuint32_t PACR22_SP:1; /* Supervisor Protect */ + vuint32_t PACR22_WP:1; /* Write Protect */ + vuint32_t PACR22_TP:1; /* Trusted Protect */ + vuint32_t PACR23_BW:1; /* Buffer Writes */ + vuint32_t PACR23_SP:1; /* Supervisor Protect */ + vuint32_t PACR23_WP:1; /* Write Protect */ + vuint32_t PACR23_TP:1; /* Trusted Protect */ + } B; + } AIPS_PACR16_23_32B_tag; + + typedef union { /* PACR24_31 - Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t PACR24_BW:1; /* Buffer Writes */ + vuint32_t PACR24_SP:1; /* Supervisor Protect */ + vuint32_t PACR24_WP:1; /* Write Protect */ + vuint32_t PACR24_TP:1; /* Trusted Protect */ + vuint32_t PACR25_BW:1; /* Buffer Writes */ + vuint32_t PACR25_SP:1; /* Supervisor Protect */ + vuint32_t PACR25_WP:1; /* Write Protect */ + vuint32_t PACR25_TP:1; /* Trusted Protect */ + vuint32_t PACR26_BW:1; /* Buffer Writes */ + vuint32_t PACR26_SP:1; /* Supervisor Protect */ + vuint32_t PACR26_WP:1; /* Write Protect */ + vuint32_t PACR26_TP:1; /* Trusted Protect */ + vuint32_t PACR27_BW:1; /* Buffer Writes */ + vuint32_t PACR27_SP:1; /* Supervisor Protect */ + vuint32_t PACR27_WP:1; /* Write Protect */ + vuint32_t PACR27_TP:1; /* Trusted Protect */ + vuint32_t PACR28_BW:1; /* Buffer Writes */ + vuint32_t PACR28_SP:1; /* Supervisor Protect */ + vuint32_t PACR28_WP:1; /* Write Protect */ + vuint32_t PACR28_TP:1; /* Trusted Protect */ + vuint32_t PACR29_BW:1; /* Buffer Writes */ + vuint32_t PACR29_SP:1; /* Supervisor Protect */ + vuint32_t PACR29_WP:1; /* Write Protect */ + vuint32_t PACR29_TP:1; /* Trusted Protect */ + vuint32_t PACR30_BW:1; /* Buffer Writes */ + vuint32_t PACR30_SP:1; /* Supervisor Protect */ + vuint32_t PACR30_WP:1; /* Write Protect */ + vuint32_t PACR30_TP:1; /* Trusted Protect */ + vuint32_t PACR31_BW:1; /* Buffer Writes */ + vuint32_t PACR31_SP:1; /* Supervisor Protect */ + vuint32_t PACR31_WP:1; /* Write Protect */ + vuint32_t PACR31_TP:1; /* Trusted Protect */ + } B; + } AIPS_PACR24_31_32B_tag; + + typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR0_BW:1; /* Buffer Writes */ + vuint32_t OPACR0_SP:1; /* Supervisor Protect */ + vuint32_t OPACR0_WP:1; /* Write Protect */ + vuint32_t OPACR0_TP:1; /* Trusted Protect */ + vuint32_t OPACR1_BW:1; /* Buffer Writes */ + vuint32_t OPACR1_SP:1; /* Supervisor Protect */ + vuint32_t OPACR1_WP:1; /* Write Protect */ + vuint32_t OPACR1_TP:1; /* Trusted Protect */ + vuint32_t OPACR2_BW:1; /* Buffer Writes */ + vuint32_t OPACR2_SP:1; /* Supervisor Protect */ + vuint32_t OPACR2_WP:1; /* Write Protect */ + vuint32_t OPACR2_TP:1; /* Trusted Protect */ + vuint32_t OPACR3_BW:1; /* Buffer Writes */ + vuint32_t OPACR3_SP:1; /* Supervisor Protect */ + vuint32_t OPACR3_WP:1; /* Write Protect */ + vuint32_t OPACR3_TP:1; /* Trusted Protect */ + vuint32_t OPACR4_BW:1; /* Buffer Writes */ + vuint32_t OPACR4_SP:1; /* Supervisor Protect */ + vuint32_t OPACR4_WP:1; /* Write Protect */ + vuint32_t OPACR4_TP:1; /* Trusted Protect */ + vuint32_t OPACR5_BW:1; /* Buffer Writes */ + vuint32_t OPACR5_SP:1; /* Supervisor Protect */ + vuint32_t OPACR5_WP:1; /* Write Protect */ + vuint32_t OPACR5_TP:1; /* Trusted Protect */ + vuint32_t OPACR6_BW:1; /* Buffer Writes */ + vuint32_t OPACR6_SP:1; /* Supervisor Protect */ + vuint32_t OPACR6_WP:1; /* Write Protect */ + vuint32_t OPACR6_TP:1; /* Trusted Protect */ + vuint32_t OPACR7_BW:1; /* Buffer Writes */ + vuint32_t OPACR7_SP:1; /* Supervisor Protect */ + vuint32_t OPACR7_WP:1; /* Write Protect */ + vuint32_t OPACR7_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR0_7_32B_tag; + + typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR8_BW:1; /* Buffer Writes */ + vuint32_t OPACR8_SP:1; /* Supervisor Protect */ + vuint32_t OPACR8_WP:1; /* Write Protect */ + vuint32_t OPACR8_TP:1; /* Trusted Protect */ + vuint32_t OPACR9_BW:1; /* Buffer Writes */ + vuint32_t OPACR9_SP:1; /* Supervisor Protect */ + vuint32_t OPACR9_WP:1; /* Write Protect */ + vuint32_t OPACR9_TP:1; /* Trusted Protect */ + vuint32_t OPACR10_BW:1; /* Buffer Writes */ + vuint32_t OPACR10_SP:1; /* Supervisor Protect */ + vuint32_t OPACR10_WP:1; /* Write Protect */ + vuint32_t OPACR10_TP:1; /* Trusted Protect */ + vuint32_t OPACR11_BW:1; /* Buffer Writes */ + vuint32_t OPACR11_SP:1; /* Supervisor Protect */ + vuint32_t OPACR11_WP:1; /* Write Protect */ + vuint32_t OPACR11_TP:1; /* Trusted Protect */ + vuint32_t OPACR12_BW:1; /* Buffer Writes */ + vuint32_t OPACR12_SP:1; /* Supervisor Protect */ + vuint32_t OPACR12_WP:1; /* Write Protect */ + vuint32_t OPACR12_TP:1; /* Trusted Protect */ + vuint32_t OPACR13_BW:1; /* Buffer Writes */ + vuint32_t OPACR13_SP:1; /* Supervisor Protect */ + vuint32_t OPACR13_WP:1; /* Write Protect */ + vuint32_t OPACR13_TP:1; /* Trusted Protect */ + vuint32_t OPACR14_BW:1; /* Buffer Writes */ + vuint32_t OPACR14_SP:1; /* Supervisor Protect */ + vuint32_t OPACR14_WP:1; /* Write Protect */ + vuint32_t OPACR14_TP:1; /* Trusted Protect */ + vuint32_t OPACR15_BW:1; /* Buffer Writes */ + vuint32_t OPACR15_SP:1; /* Supervisor Protect */ + vuint32_t OPACR15_WP:1; /* Write Protect */ + vuint32_t OPACR15_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR8_15_32B_tag; + + typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR16_BW:1; /* Buffer Writes */ + vuint32_t OPACR16_SP:1; /* Supervisor Protect */ + vuint32_t OPACR16_WP:1; /* Write Protect */ + vuint32_t OPACR16_TP:1; /* Trusted Protect */ + vuint32_t OPACR17_BW:1; /* Buffer Writes */ + vuint32_t OPACR17_SP:1; /* Supervisor Protect */ + vuint32_t OPACR17_WP:1; /* Write Protect */ + vuint32_t OPACR17_TP:1; /* Trusted Protect */ + vuint32_t OPACR18_BW:1; /* Buffer Writes */ + vuint32_t OPACR18_SP:1; /* Supervisor Protect */ + vuint32_t OPACR18_WP:1; /* Write Protect */ + vuint32_t OPACR18_TP:1; /* Trusted Protect */ + vuint32_t OPACR19_BW:1; /* Buffer Writes */ + vuint32_t OPACR19_SP:1; /* Supervisor Protect */ + vuint32_t OPACR19_WP:1; /* Write Protect */ + vuint32_t OPACR19_TP:1; /* Trusted Protect */ + vuint32_t OPACR20_BW:1; /* Buffer Writes */ + vuint32_t OPACR20_SP:1; /* Supervisor Protect */ + vuint32_t OPACR20_WP:1; /* Write Protect */ + vuint32_t OPACR20_TP:1; /* Trusted Protect */ + vuint32_t OPACR21_BW:1; /* Buffer Writes */ + vuint32_t OPACR21_SP:1; /* Supervisor Protect */ + vuint32_t OPACR21_WP:1; /* Write Protect */ + vuint32_t OPACR21_TP:1; /* Trusted Protect */ + vuint32_t OPACR22_BW:1; /* Buffer Writes */ + vuint32_t OPACR22_SP:1; /* Supervisor Protect */ + vuint32_t OPACR22_WP:1; /* Write Protect */ + vuint32_t OPACR22_TP:1; /* Trusted Protect */ + vuint32_t OPACR23_BW:1; /* Buffer Writes */ + vuint32_t OPACR23_SP:1; /* Supervisor Protect */ + vuint32_t OPACR23_WP:1; /* Write Protect */ + vuint32_t OPACR23_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR16_23_32B_tag; + + typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR24_BW:1; /* Buffer Writes */ + vuint32_t OPACR24_SP:1; /* Supervisor Protect */ + vuint32_t OPACR24_WP:1; /* Write Protect */ + vuint32_t OPACR24_TP:1; /* Trusted Protect */ + vuint32_t OPACR25_BW:1; /* Buffer Writes */ + vuint32_t OPACR25_SP:1; /* Supervisor Protect */ + vuint32_t OPACR25_WP:1; /* Write Protect */ + vuint32_t OPACR25_TP:1; /* Trusted Protect */ + vuint32_t OPACR26_BW:1; /* Buffer Writes */ + vuint32_t OPACR26_SP:1; /* Supervisor Protect */ + vuint32_t OPACR26_WP:1; /* Write Protect */ + vuint32_t OPACR26_TP:1; /* Trusted Protect */ + vuint32_t OPACR27_BW:1; /* Buffer Writes */ + vuint32_t OPACR27_SP:1; /* Supervisor Protect */ + vuint32_t OPACR27_WP:1; /* Write Protect */ + vuint32_t OPACR27_TP:1; /* Trusted Protect */ + vuint32_t OPACR28_BW:1; /* Buffer Writes */ + vuint32_t OPACR28_SP:1; /* Supervisor Protect */ + vuint32_t OPACR28_WP:1; /* Write Protect */ + vuint32_t OPACR28_TP:1; /* Trusted Protect */ + vuint32_t OPACR29_BW:1; /* Buffer Writes */ + vuint32_t OPACR29_SP:1; /* Supervisor Protect */ + vuint32_t OPACR29_WP:1; /* Write Protect */ + vuint32_t OPACR29_TP:1; /* Trusted Protect */ + vuint32_t OPACR30_BW:1; /* Buffer Writes */ + vuint32_t OPACR30_SP:1; /* Supervisor Protect */ + vuint32_t OPACR30_WP:1; /* Write Protect */ + vuint32_t OPACR30_TP:1; /* Trusted Protect */ + vuint32_t OPACR31_BW:1; /* Buffer Writes */ + vuint32_t OPACR31_SP:1; /* Supervisor Protect */ + vuint32_t OPACR31_WP:1; /* Write Protect */ + vuint32_t OPACR31_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR24_31_32B_tag; + + typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR32_BW:1; /* Buffer Writes */ + vuint32_t OPACR32_SP:1; /* Supervisor Protect */ + vuint32_t OPACR32_WP:1; /* Write Protect */ + vuint32_t OPACR32_TP:1; /* Trusted Protect */ + vuint32_t OPACR33_BW:1; /* Buffer Writes */ + vuint32_t OPACR33_SP:1; /* Supervisor Protect */ + vuint32_t OPACR33_WP:1; /* Write Protect */ + vuint32_t OPACR33_TP:1; /* Trusted Protect */ + vuint32_t OPACR34_BW:1; /* Buffer Writes */ + vuint32_t OPACR34_SP:1; /* Supervisor Protect */ + vuint32_t OPACR34_WP:1; /* Write Protect */ + vuint32_t OPACR34_TP:1; /* Trusted Protect */ + vuint32_t OPACR35_BW:1; /* Buffer Writes */ + vuint32_t OPACR35_SP:1; /* Supervisor Protect */ + vuint32_t OPACR35_WP:1; /* Write Protect */ + vuint32_t OPACR35_TP:1; /* Trusted Protect */ + vuint32_t OPACR36_BW:1; /* Buffer Writes */ + vuint32_t OPACR36_SP:1; /* Supervisor Protect */ + vuint32_t OPACR36_WP:1; /* Write Protect */ + vuint32_t OPACR36_TP:1; /* Trusted Protect */ + vuint32_t OPACR37_BW:1; /* Buffer Writes */ + vuint32_t OPACR37_SP:1; /* Supervisor Protect */ + vuint32_t OPACR37_WP:1; /* Write Protect */ + vuint32_t OPACR37_TP:1; /* Trusted Protect */ + vuint32_t OPACR38_BW:1; /* Buffer Writes */ + vuint32_t OPACR38_SP:1; /* Supervisor Protect */ + vuint32_t OPACR38_WP:1; /* Write Protect */ + vuint32_t OPACR38_TP:1; /* Trusted Protect */ + vuint32_t OPACR39_BW:1; /* Buffer Writes */ + vuint32_t OPACR39_SP:1; /* Supervisor Protect */ + vuint32_t OPACR39_WP:1; /* Write Protect */ + vuint32_t OPACR39_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR32_39_32B_tag; + + typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR40_BW:1; /* Buffer Writes */ + vuint32_t OPACR40_SP:1; /* Supervisor Protect */ + vuint32_t OPACR40_WP:1; /* Write Protect */ + vuint32_t OPACR40_TP:1; /* Trusted Protect */ + vuint32_t OPACR41_BW:1; /* Buffer Writes */ + vuint32_t OPACR41_SP:1; /* Supervisor Protect */ + vuint32_t OPACR41_WP:1; /* Write Protect */ + vuint32_t OPACR41_TP:1; /* Trusted Protect */ + vuint32_t OPACR42_BW:1; /* Buffer Writes */ + vuint32_t OPACR42_SP:1; /* Supervisor Protect */ + vuint32_t OPACR42_WP:1; /* Write Protect */ + vuint32_t OPACR42_TP:1; /* Trusted Protect */ + vuint32_t OPACR43_BW:1; /* Buffer Writes */ + vuint32_t OPACR43_SP:1; /* Supervisor Protect */ + vuint32_t OPACR43_WP:1; /* Write Protect */ + vuint32_t OPACR43_TP:1; /* Trusted Protect */ + vuint32_t OPACR44_BW:1; /* Buffer Writes */ + vuint32_t OPACR44_SP:1; /* Supervisor Protect */ + vuint32_t OPACR44_WP:1; /* Write Protect */ + vuint32_t OPACR44_TP:1; /* Trusted Protect */ + vuint32_t OPACR45_BW:1; /* Buffer Writes */ + vuint32_t OPACR45_SP:1; /* Supervisor Protect */ + vuint32_t OPACR45_WP:1; /* Write Protect */ + vuint32_t OPACR45_TP:1; /* Trusted Protect */ + vuint32_t OPACR46_BW:1; /* Buffer Writes */ + vuint32_t OPACR46_SP:1; /* Supervisor Protect */ + vuint32_t OPACR46_WP:1; /* Write Protect */ + vuint32_t OPACR46_TP:1; /* Trusted Protect */ + vuint32_t OPACR47_BW:1; /* Buffer Writes */ + vuint32_t OPACR47_SP:1; /* Supervisor Protect */ + vuint32_t OPACR47_WP:1; /* Write Protect */ + vuint32_t OPACR47_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR40_47_32B_tag; + + typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR48_BW:1; /* Buffer Writes */ + vuint32_t OPACR48_SP:1; /* Supervisor Protect */ + vuint32_t OPACR48_WP:1; /* Write Protect */ + vuint32_t OPACR48_TP:1; /* Trusted Protect */ + vuint32_t OPACR49_BW:1; /* Buffer Writes */ + vuint32_t OPACR49_SP:1; /* Supervisor Protect */ + vuint32_t OPACR49_WP:1; /* Write Protect */ + vuint32_t OPACR49_TP:1; /* Trusted Protect */ + vuint32_t OPACR50_BW:1; /* Buffer Writes */ + vuint32_t OPACR50_SP:1; /* Supervisor Protect */ + vuint32_t OPACR50_WP:1; /* Write Protect */ + vuint32_t OPACR50_TP:1; /* Trusted Protect */ + vuint32_t OPACR51_BW:1; /* Buffer Writes */ + vuint32_t OPACR51_SP:1; /* Supervisor Protect */ + vuint32_t OPACR51_WP:1; /* Write Protect */ + vuint32_t OPACR51_TP:1; /* Trusted Protect */ + vuint32_t OPACR52_BW:1; /* Buffer Writes */ + vuint32_t OPACR52_SP:1; /* Supervisor Protect */ + vuint32_t OPACR52_WP:1; /* Write Protect */ + vuint32_t OPACR52_TP:1; /* Trusted Protect */ + vuint32_t OPACR53_BW:1; /* Buffer Writes */ + vuint32_t OPACR53_SP:1; /* Supervisor Protect */ + vuint32_t OPACR53_WP:1; /* Write Protect */ + vuint32_t OPACR53_TP:1; /* Trusted Protect */ + vuint32_t OPACR54_BW:1; /* Buffer Writes */ + vuint32_t OPACR54_SP:1; /* Supervisor Protect */ + vuint32_t OPACR54_WP:1; /* Write Protect */ + vuint32_t OPACR54_TP:1; /* Trusted Protect */ + vuint32_t OPACR55_BW:1; /* Buffer Writes */ + vuint32_t OPACR55_SP:1; /* Supervisor Protect */ + vuint32_t OPACR55_WP:1; /* Write Protect */ + vuint32_t OPACR55_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR48_55_32B_tag; + + typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR56_BW:1; /* Buffer Writes */ + vuint32_t OPACR56_SP:1; /* Supervisor Protect */ + vuint32_t OPACR56_WP:1; /* Write Protect */ + vuint32_t OPACR56_TP:1; /* Trusted Protect */ + vuint32_t OPACR57_BW:1; /* Buffer Writes */ + vuint32_t OPACR57_SP:1; /* Supervisor Protect */ + vuint32_t OPACR57_WP:1; /* Write Protect */ + vuint32_t OPACR57_TP:1; /* Trusted Protect */ + vuint32_t OPACR58_BW:1; /* Buffer Writes */ + vuint32_t OPACR58_SP:1; /* Supervisor Protect */ + vuint32_t OPACR58_WP:1; /* Write Protect */ + vuint32_t OPACR58_TP:1; /* Trusted Protect */ + vuint32_t OPACR59_BW:1; /* Buffer Writes */ + vuint32_t OPACR59_SP:1; /* Supervisor Protect */ + vuint32_t OPACR59_WP:1; /* Write Protect */ + vuint32_t OPACR59_TP:1; /* Trusted Protect */ + vuint32_t OPACR60_BW:1; /* Buffer Writes */ + vuint32_t OPACR60_SP:1; /* Supervisor Protect */ + vuint32_t OPACR60_WP:1; /* Write Protect */ + vuint32_t OPACR60_TP:1; /* Trusted Protect */ + vuint32_t OPACR61_BW:1; /* Buffer Writes */ + vuint32_t OPACR61_SP:1; /* Supervisor Protect */ + vuint32_t OPACR61_WP:1; /* Write Protect */ + vuint32_t OPACR61_TP:1; /* Trusted Protect */ + vuint32_t OPACR62_BW:1; /* Buffer Writes */ + vuint32_t OPACR62_SP:1; /* Supervisor Protect */ + vuint32_t OPACR62_WP:1; /* Write Protect */ + vuint32_t OPACR62_TP:1; /* Trusted Protect */ + vuint32_t OPACR63_BW:1; /* Buffer Writes */ + vuint32_t OPACR63_SP:1; /* Supervisor Protect */ + vuint32_t OPACR63_WP:1; /* Write Protect */ + vuint32_t OPACR63_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR56_63_32B_tag; + + typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR64_BW:1; /* Buffer Writes */ + vuint32_t OPACR64_SP:1; /* Supervisor Protect */ + vuint32_t OPACR64_WP:1; /* Write Protect */ + vuint32_t OPACR64_TP:1; /* Trusted Protect */ + vuint32_t OPACR65_BW:1; /* Buffer Writes */ + vuint32_t OPACR65_SP:1; /* Supervisor Protect */ + vuint32_t OPACR65_WP:1; /* Write Protect */ + vuint32_t OPACR65_TP:1; /* Trusted Protect */ + vuint32_t OPACR66_BW:1; /* Buffer Writes */ + vuint32_t OPACR66_SP:1; /* Supervisor Protect */ + vuint32_t OPACR66_WP:1; /* Write Protect */ + vuint32_t OPACR66_TP:1; /* Trusted Protect */ + vuint32_t OPACR67_BW:1; /* Buffer Writes */ + vuint32_t OPACR67_SP:1; /* Supervisor Protect */ + vuint32_t OPACR67_WP:1; /* Write Protect */ + vuint32_t OPACR67_TP:1; /* Trusted Protect */ + vuint32_t OPACR68_BW:1; /* Buffer Writes */ + vuint32_t OPACR68_SP:1; /* Supervisor Protect */ + vuint32_t OPACR68_WP:1; /* Write Protect */ + vuint32_t OPACR68_TP:1; /* Trusted Protect */ + vuint32_t OPACR69_BW:1; /* Buffer Writes */ + vuint32_t OPACR69_SP:1; /* Supervisor Protect */ + vuint32_t OPACR69_WP:1; /* Write Protect */ + vuint32_t OPACR69_TP:1; /* Trusted Protect */ + vuint32_t OPACR70_BW:1; /* Buffer Writes */ + vuint32_t OPACR70_SP:1; /* Supervisor Protect */ + vuint32_t OPACR70_WP:1; /* Write Protect */ + vuint32_t OPACR70_TP:1; /* Trusted Protect */ + vuint32_t OPACR71_BW:1; /* Buffer Writes */ + vuint32_t OPACR71_SP:1; /* Supervisor Protect */ + vuint32_t OPACR71_WP:1; /* Write Protect */ + vuint32_t OPACR71_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR64_71_32B_tag; + + typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR72_BW:1; /* Buffer Writes */ + vuint32_t OPACR72_SP:1; /* Supervisor Protect */ + vuint32_t OPACR72_WP:1; /* Write Protect */ + vuint32_t OPACR72_TP:1; /* Trusted Protect */ + vuint32_t OPACR73_BW:1; /* Buffer Writes */ + vuint32_t OPACR73_SP:1; /* Supervisor Protect */ + vuint32_t OPACR73_WP:1; /* Write Protect */ + vuint32_t OPACR73_TP:1; /* Trusted Protect */ + vuint32_t OPACR74_BW:1; /* Buffer Writes */ + vuint32_t OPACR74_SP:1; /* Supervisor Protect */ + vuint32_t OPACR74_WP:1; /* Write Protect */ + vuint32_t OPACR74_TP:1; /* Trusted Protect */ + vuint32_t OPACR75_BW:1; /* Buffer Writes */ + vuint32_t OPACR75_SP:1; /* Supervisor Protect */ + vuint32_t OPACR75_WP:1; /* Write Protect */ + vuint32_t OPACR75_TP:1; /* Trusted Protect */ + vuint32_t OPACR76_BW:1; /* Buffer Writes */ + vuint32_t OPACR76_SP:1; /* Supervisor Protect */ + vuint32_t OPACR76_WP:1; /* Write Protect */ + vuint32_t OPACR76_TP:1; /* Trusted Protect */ + vuint32_t OPACR77_BW:1; /* Buffer Writes */ + vuint32_t OPACR77_SP:1; /* Supervisor Protect */ + vuint32_t OPACR77_WP:1; /* Write Protect */ + vuint32_t OPACR77_TP:1; /* Trusted Protect */ + vuint32_t OPACR78_BW:1; /* Buffer Writes */ + vuint32_t OPACR78_SP:1; /* Supervisor Protect */ + vuint32_t OPACR78_WP:1; /* Write Protect */ + vuint32_t OPACR78_TP:1; /* Trusted Protect */ + vuint32_t OPACR79_BW:1; /* Buffer Writes */ + vuint32_t OPACR79_SP:1; /* Supervisor Protect */ + vuint32_t OPACR79_WP:1; /* Write Protect */ + vuint32_t OPACR79_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR72_79_32B_tag; + + typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR80_BW:1; /* Buffer Writes */ + vuint32_t OPACR80_SP:1; /* Supervisor Protect */ + vuint32_t OPACR80_WP:1; /* Write Protect */ + vuint32_t OPACR80_TP:1; /* Trusted Protect */ + vuint32_t OPACR81_BW:1; /* Buffer Writes */ + vuint32_t OPACR81_SP:1; /* Supervisor Protect */ + vuint32_t OPACR81_WP:1; /* Write Protect */ + vuint32_t OPACR81_TP:1; /* Trusted Protect */ + vuint32_t OPACR82_BW:1; /* Buffer Writes */ + vuint32_t OPACR82_SP:1; /* Supervisor Protect */ + vuint32_t OPACR82_WP:1; /* Write Protect */ + vuint32_t OPACR82_TP:1; /* Trusted Protect */ + vuint32_t OPACR83_BW:1; /* Buffer Writes */ + vuint32_t OPACR83_SP:1; /* Supervisor Protect */ + vuint32_t OPACR83_WP:1; /* Write Protect */ + vuint32_t OPACR83_TP:1; /* Trusted Protect */ + vuint32_t OPACR84_BW:1; /* Buffer Writes */ + vuint32_t OPACR84_SP:1; /* Supervisor Protect */ + vuint32_t OPACR84_WP:1; /* Write Protect */ + vuint32_t OPACR84_TP:1; /* Trusted Protect */ + vuint32_t OPACR85_BW:1; /* Buffer Writes */ + vuint32_t OPACR85_SP:1; /* Supervisor Protect */ + vuint32_t OPACR85_WP:1; /* Write Protect */ + vuint32_t OPACR85_TP:1; /* Trusted Protect */ + vuint32_t OPACR86_BW:1; /* Buffer Writes */ + vuint32_t OPACR86_SP:1; /* Supervisor Protect */ + vuint32_t OPACR86_WP:1; /* Write Protect */ + vuint32_t OPACR86_TP:1; /* Trusted Protect */ + vuint32_t OPACR87_BW:1; /* Buffer Writes */ + vuint32_t OPACR87_SP:1; /* Supervisor Protect */ + vuint32_t OPACR87_WP:1; /* Write Protect */ + vuint32_t OPACR87_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR80_87_32B_tag; + + typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + vuint32_t R; + struct { + vuint32_t OPACR88_BW:1; /* Buffer Writes */ + vuint32_t OPACR88_SP:1; /* Supervisor Protect */ + vuint32_t OPACR88_WP:1; /* Write Protect */ + vuint32_t OPACR88_TP:1; /* Trusted Protect */ + vuint32_t OPACR89_BW:1; /* Buffer Writes */ + vuint32_t OPACR89_SP:1; /* Supervisor Protect */ + vuint32_t OPACR89_WP:1; /* Write Protect */ + vuint32_t OPACR89_TP:1; /* Trusted Protect */ + vuint32_t OPACR90_BW:1; /* Buffer Writes */ + vuint32_t OPACR90_SP:1; /* Supervisor Protect */ + vuint32_t OPACR90_WP:1; /* Write Protect */ + vuint32_t OPACR90_TP:1; /* Trusted Protect */ + vuint32_t OPACR91_BW:1; /* Buffer Writes */ + vuint32_t OPACR91_SP:1; /* Supervisor Protect */ + vuint32_t OPACR91_WP:1; /* Write Protect */ + vuint32_t OPACR91_TP:1; /* Trusted Protect */ + vuint32_t OPACR92_BW:1; /* Buffer Writes */ + vuint32_t OPACR92_SP:1; /* Supervisor Protect */ + vuint32_t OPACR92_WP:1; /* Write Protect */ + vuint32_t OPACR92_TP:1; /* Trusted Protect */ + vuint32_t OPACR93_BW:1; /* Buffer Writes */ + vuint32_t OPACR93_SP:1; /* Supervisor Protect */ + vuint32_t OPACR93_WP:1; /* Write Protect */ + vuint32_t OPACR93_TP:1; /* Trusted Protect */ + vuint32_t OPACR94_BW:1; /* Buffer Writes */ + vuint32_t OPACR94_SP:1; /* Supervisor Protect */ + vuint32_t OPACR94_WP:1; /* Write Protect */ + vuint32_t OPACR94_TP:1; /* Trusted Protect */ + vuint32_t OPACR95_BW:1; /* Buffer Writes */ + vuint32_t OPACR95_SP:1; /* Supervisor Protect */ + vuint32_t OPACR95_WP:1; /* Write Protect */ + vuint32_t OPACR95_TP:1; /* Trusted Protect */ + } B; + } AIPS_OPACR88_95_32B_tag; + + + + typedef struct AIPS_struct_tag { /* start of AIPS_tag */ + /* MPROT - Master Privilege Registers */ + AIPS_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */ + int8_t AIPS_reserved_0004[28]; + /* PACR0_7 - Peripheral Access Control Registers */ + AIPS_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */ + /* PACR8_15 - Peripheral Access Control Registers */ + AIPS_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */ + /* PACR16_23 - Peripheral Access Control Registers */ + AIPS_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */ + /* PACR24_31 - Peripheral Access Control Registers */ + AIPS_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */ + int8_t AIPS_reserved_0030[16]; + /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */ + /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */ + /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */ + /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */ + /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */ + /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */ + /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */ + /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */ + /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */ + /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */ + /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */ + /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + AIPS_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */ + } AIPS_tag; + + +#define AIPS (*(volatile AIPS_tag *) 0xFFF00000UL) + + + +/****************************************************************/ +/* */ +/* Module: MAX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers MPR... */ + + typedef union { /* Master Priority Register for slave port n */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t MSTR_7:3; /* Master 7 Priority */ + vuint32_t:1; + vuint32_t MSTR_6:3; /* Master 6 Priority */ + vuint32_t:1; + vuint32_t MSTR_5:3; /* Master 5 Priority */ + vuint32_t:1; + vuint32_t MSTR_4:3; /* Master 4 Priority */ + vuint32_t:1; + vuint32_t MSTR_3:3; /* Master 3 Priority */ + vuint32_t:1; + vuint32_t MSTR_2:3; /* Master 2 Priority */ + vuint32_t:1; + vuint32_t MSTR_1:3; /* Master 1 Priority */ + vuint32_t:1; + vuint32_t MSTR_0:3; /* Master 0 Priority */ + } B; + } MAX_MPR_32B_tag; + + + /* Register layout for all registers AMPR matches xxx */ + + + /* Register layout for all registers SGPCR... */ + + typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t HPE5:1; /* High Priority Enable */ + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t HPE3:1; /* High Priority Enable */ + vuint32_t HPE2:1; /* High Priority Enable */ + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; + vuint32_t PARK:3; /* Park */ + } B; + } MAX_SGPCR_32B_tag; + + + /* Register layout for all registers ASGPCR... */ + + typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t HLP:1; /* Halt Low Priority */ + vuint32_t:6; + vuint32_t HPE7:1; /* High Priority Enable */ + vuint32_t HPE6:1; /* High Priority Enable */ + vuint32_t HPE5:1; /* High Priority Enable */ + vuint32_t HPE4:1; /* High Priority Enable */ + vuint32_t HPE3:1; /* High Priority Enable */ + vuint32_t HPE2:1; /* High Priority Enable */ + vuint32_t HPE1:1; /* High Priority Enable */ + vuint32_t HPE0:1; /* High Priority Enable */ + vuint32_t:6; + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; + vuint32_t PARK:3; /* Park */ + } B; + } MAX_ASGPCR_32B_tag; + + + /* Register layout for all registers MGPCR... */ + + typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */ + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MAX_MGPCR_32B_tag; + + + typedef struct MAX_SLAVE_PORT_struct_tag { + + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */ + int8_t MAX_SLAVE_PORT_reserved_0008[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */ + int8_t MAX_SLAVE_PORT_reserved_0018[232]; + + } MAX_SLAVE_PORT_tag; + + typedef struct MAX_MASTER_PORT_struct_tag { + + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */ + int8_t MAX_MASTER_PORT_reserved_0004[252]; + + } MAX_MASTER_PORT_tag; + + + typedef struct MAX_struct_tag { /* start of MAX_tag */ + union { + /* Register set SLAVE_PORT */ + MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */ + + struct { + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */ + int8_t MAX_reserved_0008_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */ + int8_t MAX_reserved_0018_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */ + int8_t MAX_reserved_0108_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */ + int8_t MAX_reserved_0118_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */ + int8_t MAX_reserved_0208_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */ + int8_t MAX_reserved_0218_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */ + int8_t MAX_reserved_0308_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */ + int8_t MAX_reserved_0318_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */ + int8_t MAX_reserved_0408_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */ + int8_t MAX_reserved_0418_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */ + int8_t MAX_reserved_0508_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */ + int8_t MAX_reserved_0518_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */ + int8_t MAX_reserved_0608_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */ + int8_t MAX_reserved_0618_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */ + int8_t MAX_reserved_0708_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */ + int8_t MAX_reserved_0718_E1[232]; + }; + + }; + union { + /* Register set MASTER_PORT */ + MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */ + + struct { + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */ + int8_t MAX_reserved_0804_I1[252]; + MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */ + int8_t MAX_reserved_0904_I1[252]; + MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */ + int8_t MAX_reserved_0A04_I1[252]; + MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */ + int8_t MAX_reserved_0B04_I1[252]; + MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */ + int8_t MAX_reserved_0C04_I1[252]; + MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */ + int8_t MAX_reserved_0D04_I1[252]; + MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */ + int8_t MAX_reserved_0E04_I1[252]; + MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */ + int8_t MAX_reserved_0F04_E1[252]; + }; + + }; + } MAX_tag; + + +#define MAX (*(volatile MAX_tag *) 0xFFF04000UL) + + + +/****************************************************************/ +/* */ +/* Module: MPU */ +/* */ +/****************************************************************/ + + typedef union { /* MPU_CESR - MPU Control/Error Status Register */ + vuint32_t R; + struct { + vuint32_t SPERR:8; /* Slave Port n Error */ + vuint32_t:4; + vuint32_t HRL:4; /* Hardware Revision Level */ + vuint32_t NSP:4; /* Number of Slave Ports */ + vuint32_t NRGD:4; /* Number of Region Descriptors */ + vuint32_t:7; + vuint32_t VLD:1; /* Valid bit */ + } B; + } MPU_CESR_32B_tag; + + + /* Register layout for all registers EAR... */ + + typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */ + vuint32_t R; + struct { + vuint32_t EADDR:32; /* Error Address */ + } B; + } MPU_EAR_32B_tag; + + + /* Register layout for all registers EDR... */ + + typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + vuint32_t R; + struct { + vuint32_t EACD:16; /* Error Access Control Detail */ + vuint32_t EPID:8; /* Error Process Identification */ + vuint32_t EMN:4; /* Error Master Number */ + vuint32_t EATTR:3; /* Error Attributes */ + vuint32_t ERW:1; /* Error Read/Write */ + } B; + } MPU_EDR_32B_tag; + + + /* Register layout for all registers RGD_WORD0... */ + + typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */ + vuint32_t R; + struct { + vuint32_t SRTADDR:27; /* Start Address */ + vuint32_t:5; + } B; + } MPU_RGD_WORD0_32B_tag; + + + /* Register layout for all registers RGD_WORD1... */ + + typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */ + vuint32_t R; + struct { + vuint32_t ENDADDR:27; /* End Address */ + vuint32_t:5; + } B; + } MPU_RGD_WORD1_32B_tag; + + + /* Register layout for all registers RGD_WORD2... */ + + typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */ + vuint32_t R; + struct { + vuint32_t M7RE:1; /* Bus Master 7 Read Enable */ + vuint32_t M7WE:1; /* Bus Master 7 Write Enable */ + vuint32_t M6RE:1; /* Bus Master 6 Read Enable */ + vuint32_t M6WE:1; /* Bus Master 7 Write Enable */ + vuint32_t M5RE:1; /* Bus Master 5 Read Enable */ + vuint32_t M5WE:1; /* Bus Master 5 Write Enable */ + vuint32_t M4RE:1; /* Bus Master 4 Read Enable */ + vuint32_t M4WE:1; /* Bus Master 4 Write Enable */ + vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGD_WORD2_32B_tag; + + + /* Register layout for all registers RGD_WORD3... */ + + typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */ + vuint32_t R; + struct { + vuint32_t PID:8; /* Process Identifier */ + vuint32_t PIDMASK:8; /* Process Identifier Mask */ + vuint32_t:15; + vuint32_t VLD:1; /* Valid */ + } B; + } MPU_RGD_WORD3_32B_tag; + + + /* Register layout for all registers RGDAAC... */ + + typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + vuint32_t R; + struct { + vuint32_t M7RE:1; /* Bus Master 7 Read Enable */ + vuint32_t M7WE:1; /* Bus Master 7 Write Enable */ + vuint32_t M6RE:1; /* Bus Master 6 Read Enable */ + vuint32_t M6WE:1; /* Bus Master 7 Write Enable */ + vuint32_t M5RE:1; /* Bus Master 5 Read Enable */ + vuint32_t M5WE:1; /* Bus Master 5 Write Enable */ + vuint32_t M4RE:1; /* Bus Master 4 Read Enable */ + vuint32_t M4WE:1; /* Bus Master 4 Write Enable */ + vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGDAAC_32B_tag; + + + typedef struct MPU_SLAVE_PORT_struct_tag { + + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */ + + } MPU_SLAVE_PORT_tag; + + typedef struct MPU_REGION_struct_tag { + + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */ + + } MPU_REGION_tag; + + + typedef struct MPU_struct_tag { /* start of MPU_tag */ + /* MPU_CESR - MPU Control/Error Status Register */ + MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */ + int8_t MPU_reserved_0004_C[12]; + union { + /* Register set SLAVE_PORT */ + MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */ + + struct { + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0030_C[976]; + union { + /* Register set REGION */ + MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */ + + struct { + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0500_C[768]; + union { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */ + + struct { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */ + }; + + }; + } MPU_tag; + + +#define MPU (*(volatile MPU_tag *) 0xFFF10000UL) + + + +/****************************************************************/ +/* */ +/* Module: SEMA4 */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers GATE... */ + + typedef union { /* SEMA4_GATEn - Semephores Gate Register */ + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t GTFSM:2; /* Gate Finite State machine */ + } B; + } SEMA4_GATE_8B_tag; + + typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + vuint16_t R; + struct { + vuint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP0INE_16B_tag; + + typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + vuint16_t R; + struct { + vuint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP1INE_16B_tag; + + typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + vuint16_t R; + struct { + vuint16_t GN:16; /* Gate 0 Notification */ + } B; + } SEMA4_CP0NTF_16B_tag; + + typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + vuint16_t R; + struct { + vuint16_t GN:16; /* Gate 1 Notification */ + } B; + } SEMA4_CP1NTF_16B_tag; + + typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t RSTGSM:2; /* Reset Gate Finite State Machine */ + vuint16_t RSTGDP:7; /* Reset Gate Data Pattern */ + vuint16_t RSTGMS:3; /* Reset Gate Bus Master */ + vuint16_t RSTGTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTGT_16B_tag; + + typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t RSTNSM:2; /* Reset Gate Finite State Machine */ + vuint16_t RSTNDP:7; /* Reset Gate Data Pattern */ + vuint16_t RSTNMS:3; /* Reset Gate Bus Master */ + vuint16_t RSTNTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTNTF_16B_tag; + + + + typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */ + union { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */ + SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */ + SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */ + SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */ + SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */ + SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */ + SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */ + SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */ + SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */ + SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */ + SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */ + SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */ + SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */ + SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */ + SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */ + SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */ + }; + + }; + int8_t SEMA4_reserved_0010[48]; + /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */ + int8_t SEMA4_reserved_0042[6]; + /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */ + int8_t SEMA4_reserved_004A[54]; + /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */ + int8_t SEMA4_reserved_0082[6]; + /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */ + int8_t SEMA4_reserved_008A[118]; + /* SEMA4_RSTGT - Semaphores Reset Gate */ + SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */ + int8_t SEMA4_reserved_0102[2]; + /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */ + } SEMA4_tag; + + +#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL) + + + +/****************************************************************/ +/* */ +/* Module: SWT */ +/* */ +/****************************************************************/ + + typedef union { /* SWT_CR - Control Register */ + vuint32_t R; + struct { + vuint32_t MAP0:1; /* Master Acces Protection for Master 0 */ + vuint32_t MAP1:1; /* Master Acces Protection for Master 1 */ + vuint32_t MAP2:1; /* Master Acces Protection for Master 2 */ + vuint32_t MAP3:1; /* Master Acces Protection for Master 3 */ + vuint32_t MAP4:1; /* Master Acces Protection for Master 4 */ + vuint32_t MAP5:1; /* Master Acces Protection for Master 5 */ + vuint32_t MAP6:1; /* Master Acces Protection for Master 6 */ + vuint32_t MAP7:1; /* Master Acces Protection for Master 7 */ + vuint32_t:14; + vuint32_t KEY:1; /* Keyed Service Mode */ + vuint32_t RIA:1; /* Reset on Invalid Access */ + vuint32_t WND:1; /* Window Mode */ + vuint32_t ITR:1; /* Interrupt Then Reset */ + vuint32_t HLK:1; /* Hard Lock */ + vuint32_t SLK:1; /* Soft Lock */ + vuint32_t CSL:1; /* Clock Selection */ + vuint32_t STP:1; /* Stop Mode Control */ + vuint32_t FRZ:1; /* Debug Mode Control */ + vuint32_t WEN:1; /* Watchdog Enabled */ + } B; + } SWT_CR_32B_tag; + + typedef union { /* SWT_IR - SWT Interrupt Register */ + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; /* Time Out Interrupt Flag */ + } B; + } SWT_IR_32B_tag; + + typedef union { /* SWT_TO - SWT Time-Out Register */ + vuint32_t R; + struct { + vuint32_t WTO:32; /* Watchdog Time Out Period */ + } B; + } SWT_TO_32B_tag; + + typedef union { /* SWT_WN - SWT Window Register */ + vuint32_t R; + struct { + vuint32_t WST:32; /* Watchdog Time Out Period */ + } B; + } SWT_WN_32B_tag; + + typedef union { /* SWT_SR - SWT Service Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; /* Watchdog Service Code */ + } B; + } SWT_SR_32B_tag; + + typedef union { /* SWT_CO - SWT Counter Output Register */ + vuint32_t R; + struct { + vuint32_t CNT:32; /* Watchdog Count */ + } B; + } SWT_CO_32B_tag; + + typedef union { /* SWT_SK - SWT Service Key Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SERVICEKEY:16; /* Service Key */ + } B; + } SWT_SK_32B_tag; + + + + typedef struct SWT_struct_tag { /* start of SWT_tag */ + /* SWT_CR - Control Register */ + SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* SWT_IR - SWT Interrupt Register */ + SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */ + /* SWT_TO - SWT Time-Out Register */ + SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */ + /* SWT_WN - SWT Window Register */ + SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */ + /* SWT_SR - SWT Service Register */ + SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */ + /* SWT_CO - SWT Counter Output Register */ + SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */ + /* SWT_SK - SWT Service Key Register */ + SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */ + } SWT_tag; + + +#define SWT (*(volatile SWT_tag *) 0xFFF38000UL) + + + +/****************************************************************/ +/* */ +/* Module: STM */ +/* */ +/****************************************************************/ + + typedef union { /* STM_CR - Control Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; /* Counter Prescaler */ + vuint32_t:6; + vuint32_t FRZ:1; /* Freeze Control */ + vuint32_t TEN:1; /* Timer Counter Enabled */ + } B; + } STM_CR_32B_tag; + + typedef union { /* STM_CNT - STM Count Register */ + vuint32_t R; + } STM_CNT_32B_tag; + + + /* Register layout for all registers CCR... */ + + typedef union { /* STM_CCRn - STM Channel Control Register */ + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; /* Channel Enable */ + } B; + } STM_CCR_32B_tag; + + + /* Register layout for all registers CIR... */ + + typedef union { /* STM_CIRn - STM Channel Interrupt Register */ + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; /* Channel Interrupt Flag */ + } B; + } STM_CIR_32B_tag; + + + /* Register layout for all registers CMP... */ + + typedef union { /* STM_CMPn - STM Channel Compare Register */ + vuint32_t R; + } STM_CMP_32B_tag; + + + typedef struct STM_CHANNEL_struct_tag { + + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */ + int8_t STM_CHANNEL_reserved_000C[4]; + + } STM_CHANNEL_tag; + + + typedef struct STM_struct_tag { /* start of STM_tag */ + union { + STM_CR_32B_tag CR0; /* deprecated - please avoid */ + + /* STM_CR - Control Register */ + STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + + }; + union { + STM_CNT_32B_tag CNT0; /* deprecated - please avoid */ + + /* STM_CNT - STM Count Register */ + STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */ + + }; + int8_t STM_reserved_0008_C[8]; + union { + /* Register set CHANNEL */ + STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */ + + struct { + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */ + int8_t STM_reserved_001C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */ + int8_t STM_reserved_002C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */ + int8_t STM_reserved_003C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */ + int8_t STM_reserved_004C_E1[4]; + }; + + }; + } STM_tag; + + +#define STM (*(volatile STM_tag *) 0xFFF3C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_MCM */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_MCM_PCT - Processor Core Type */ + vuint16_t R; + struct { + vuint16_t PCTYPE:16; /* Processor Core Type */ + } B; + } SPP_MCM_PCT_16B_tag; + + typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + vuint16_t R; + struct { + vuint16_t PLREVISION:16; /* Platform Revision */ + } B; + } SPP_MCM_PLREV_16B_tag; + + typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + vuint32_t R; + struct { + vuint32_t PMC:32; /* IPS Module Configuration */ + } B; + } SPP_MCM_IOPMC_32B_tag; + + typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + vuint8_t R; + struct { + vuint8_t POR:1; /* Power on Reset */ +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t OFPLR:1; /* Off-Platform Reset */ +#else + vuint8_t DIR:1; /* deprecated name - please avoid */ +#endif + vuint8_t:6; + } B; + } SPP_MCM_MRSR_8B_tag; + + typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + vuint8_t R; + struct { + vuint8_t ENBWCR:1; /* Enable WCR */ + vuint8_t:3; + vuint8_t PRILVL:4; /* Interrupt Priority Level */ + } B; + } SPP_MCM_MWCR_8B_tag; + + typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + vuint8_t R; + struct { + vuint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */ + vuint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */ + vuint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */ + vuint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */ + vuint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */ + vuint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */ + vuint8_t:2; + } B; + } SPP_MCM_MIR_8B_tag; + + typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + vuint32_t R; + struct { + vuint32_t MUSERDCR:32; /* User Defined Control Register */ + } B; + } SPP_MCM_MUDCR_32B_tag; + + typedef union { /* SPP_MCM_ECR - ECC Configuration Register */ + vuint8_t R; + struct { + vuint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */ +#else + vuint8_t ER1BR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */ +#else + vuint8_t EF1BR:1; /* deprecated name - please avoid */ +#endif + vuint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */ +#else + vuint8_t ERNCR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */ +#else + vuint8_t EFNCR:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ECR_8B_tag; + + typedef union { /* SPP_MCM_ESR - ECC Status Register */ + vuint8_t R; + struct { + vuint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t PR1BC:1; /* Platform RAM 1-bit Correction */ +#else + vuint8_t R1BC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */ +#else + vuint8_t F1BC:1; /* deprecated name - please avoid */ +#endif + vuint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */ +#else + vuint8_t RNCE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */ +#else + vuint8_t FNCE:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ESR_8B_tag; + + typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */ + vuint16_t R; + struct { + vuint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */ + vuint16_t:1; + vuint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */ + vuint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */ + vuint16_t:2; + vuint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */ + vuint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */ + vuint16_t:1; + vuint16_t ERRBIT:7; /* Error Bit Position */ + } B; + } SPP_MCM_EEGR_16B_tag; + + typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + vuint32_t R; + } SPP_MCM_PFEAR_32B_tag; + + typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + vuint8_t R; + } SPP_MCM_PFEMR_8B_tag; + + typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + vuint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t F_WRITE:1; /* AMBA-AHBH Write */ +#else + vuint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t F_SIZE:3; /* AMBA-AHBH Size */ +#else + vuint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t F_PROTECT:4; /* AMBA-AHBH PROT */ +#else + vuint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PFEAT_8B_tag; + + typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + vuint32_t R; + } SPP_MCM_PFEDRH_32B_tag; + + typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + vuint32_t R; + } SPP_MCM_PFEDR_32B_tag; + + typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + vuint32_t R; + } SPP_MCM_PREAR_32B_tag; + + typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + vuint8_t R; + } SPP_MCM_PRESR_8B_tag; + + typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + vuint8_t R; + struct { + vuint8_t:4; +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t PR_EMR:4; /* Platform RAM ECC Master Number */ +#else + vuint8_t REMR:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREMR_8B_tag; + + typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + vuint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t R_WRITE:1; /* AMBA-AHBH Write */ +#else + vuint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t R_SIZE:3; /* AMBA-AHBH Size */ +#else + vuint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + vuint8_t R_PROTECT:4; /* AMBA-AHBH PROT */ +#else + vuint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREAT_8B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + vuint32_t R; + } SPP_MCM_PREDRH_32B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + vuint32_t R; + } SPP_MCM_PREDR_32B_tag; + + + + typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */ + /* SPP_MCM_PCT - Processor Core Type */ + SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */ + union { + SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */ + + /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */ + + }; + int8_t SPP_MCM_reserved_0004_C[4]; + union { + SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */ + + /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_000C[3]; + /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */ + int8_t SPP_MCM_reserved_0010[3]; + /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */ + int8_t SPP_MCM_reserved_0014[11]; + /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */ + int8_t SPP_MCM_reserved_0020[4]; + /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */ + int8_t SPP_MCM_reserved_0028[27]; + /* SPP_MCM_ECR - ECC Configuration Register */ + SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */ + int8_t SPP_MCM_reserved_0044[3]; + /* SPP_MCM_ESR - ECC Status Register */ + SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */ + int8_t SPP_MCM_reserved_0048[2]; + /* SPP_MCM_EEGR - ECC Error Generation Register */ + SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */ + int8_t SPP_MCM_reserved_004C_C[4]; + union { + /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */ + + SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */ + + }; + int8_t SPP_MCM_reserved_0054_C[2]; + union { + /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */ + + SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */ + + }; + union { + /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */ + + SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */ + + }; + /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */ + union { + /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */ + + SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */ + + }; + union { + SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */ + + /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_0064_C; + union { + SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */ + + /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */ + + }; + union { + SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */ + + /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */ + + }; + union { + SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */ + + /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */ + + }; + /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */ + union { + SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */ + + /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */ + + }; + } SPP_MCM_tag; + + +#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_DMA2 */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_DMA2_DMACR - DMA Control Register */ + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t CX:1; /* Cancel Transfer */ + vuint32_t ECX:1; /* Error Cancel Transfer */ + vuint32_t GRP3PRI:2; /* Channel Group 3 Priority */ + vuint32_t GRP2PRI:2; /* Channel Group 2 Priority */ + vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + vuint32_t EMLM:1; /* Enable Minor Loop Mapping */ + vuint32_t CLM:1; /* Continuous Link Mode */ + vuint32_t HALT:1; /* Halt DMA Operations */ + vuint32_t HOE:1; /* Halt on Error */ + vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + vuint32_t EDBG:1; /* Enable Debug */ + vuint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } SPP_DMA2_DMACR_32B_tag; + + typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */ + vuint32_t R; + struct { + vuint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */ + vuint32_t:14; + vuint32_t ECX:1; /* Transfer Cancelled */ + vuint32_t GPE:1; /* Group Priority Error */ + vuint32_t CPE:1; /* Channel Priority Error */ + vuint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */ + vuint32_t SAE:1; /* Source Address Error */ + vuint32_t SOE:1; /* Source Offset Error */ + vuint32_t DAE:1; /* Destination Address Error */ + vuint32_t DOE:1; /* Destination Offset Error */ + vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ + vuint32_t SBE:1; /* Source Bus Error */ + vuint32_t DBE:1; /* Destination Bus Error */ + } B; + } SPP_DMA2_DMAES_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + vuint32_t R; + struct { + vuint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + vuint32_t R; + struct { + vuint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQL_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + vuint32_t R; + struct { + vuint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIH_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + vuint32_t R; + struct { + vuint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIL_32B_tag; + + typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SERQ:7; /* Set Enable Request */ + } B; + } SPP_DMA2_DMASERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CERQ:7; /* Clear Enable Request */ + } B; + } SPP_DMA2_DMACERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SEEI:7; /* Set Enable Error Interrupt */ + } B; + } SPP_DMA2_DMASEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CEEI:7; /* Clear Enable Error Interrupt */ + } B; + } SPP_DMA2_DMACEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CINT:7; /* Clear Interrupt Request */ + } B; + } SPP_DMA2_DMACINT_8B_tag; + + typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CERR:7; /* Clear Error Indicator */ + } B; + } SPP_DMA2_DMACERR_8B_tag; + + typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t SSRT:7; /* Set START Bit */ + } B; + } SPP_DMA2_DMASSRT_8B_tag; + + typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + vuint8_t R; + struct { + vuint8_t:1; + vuint8_t CDNE:7; /* Clear DONE Status Bit */ + } B; + } SPP_DMA2_DMACDNE_8B_tag; + + typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + vuint32_t R; + struct { + vuint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTH_32B_tag; + + typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + vuint32_t R; + struct { + vuint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTL_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */ + vuint32_t R; + struct { + vuint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */ + vuint32_t R; + struct { + vuint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRL_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + vuint32_t R; + struct { + vuint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSH_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + vuint32_t R; + struct { + vuint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSL_32B_tag; + + typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + vuint32_t R; + struct { + vuint32_t GPOR:32; /* DMA General Purpose Output */ + } B; + } SPP_DMA2_DMAGPOR_32B_tag; + + + /* Register layout for all registers DCHPRI... */ + + typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + vuint8_t R; + struct { + vuint8_t ECP:1; /* Enable Channel Preemption */ + vuint8_t DPA:1; /* Disable Preempt Ability */ + vuint8_t GRPPRI:2; /* Channel n Current Group Priority */ + vuint8_t CHPRI:4; /* Channel n Arbitration Priority */ + } B; + } SPP_DMA2_DCHPRI_8B_tag; + + + /* Register layout for all registers TCDWORD0_... */ + + typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */ + vuint32_t R; + struct { + vuint32_t SADDR:32; /* Source Address */ + } B; + } SPP_DMA2_TCDWORD0__32B_tag; + + + /* Register layout for all registers TCDWORD4_... */ + + typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + vuint32_t R; + struct { + vuint32_t SMOD:5; /* Source Address Modulo */ + vuint32_t SSIZE:3; /* Source Data Transfer Size */ + vuint32_t DMOD:5; /* Destination Address Module */ + vuint32_t DSIZE:3; /* Destination Data Transfer Size */ + vuint32_t SOFF:16; /* Source Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD4__32B_tag; + + + /* Register layout for all registers TCDWORD8_... */ + + typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */ + vuint32_t R; + struct { + vuint32_t SMLOE:1; /* Source Minor Loop Offset Enable */ + vuint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */ + vuint32_t MLOFF:20; /* Minor Loop Offset */ + vuint32_t NBYTES:10; /* Inner Minor byte transfer Count */ + } B; + } SPP_DMA2_TCDWORD8__32B_tag; + + + /* Register layout for all registers TCDWORD12_... */ + + typedef union { /* SPP_DMA2_TCDn Word3 - slast */ + vuint32_t R; + struct { + vuint32_t SLAST:32; /* Last Source Address Adjustment */ + } B; + } SPP_DMA2_TCDWORD12__32B_tag; + + + /* Register layout for all registers TCDWORD16_... */ + + typedef union { /* SPP_DMA2_TCDn Word4 - daddr */ + vuint32_t R; + struct { + vuint32_t DADDR:32; /* Destination Address */ + } B; + } SPP_DMA2_TCDWORD16__32B_tag; + + + /* Register layout for all registers TCDWORD20_... */ + + typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + vuint32_t R; + struct { + vuint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */ + vuint32_t CITER_LINKCH:6; /* Link Channel Number */ + vuint32_t CITER:9; /* Current Major Iteration Count */ + vuint32_t DOFF:16; /* Destination Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD20__32B_tag; + + + /* Register layout for all registers TCDWORD24_... */ + + typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */ + vuint32_t R; + struct { + vuint32_t DLAST_SGA:32; /* Last destination address adjustment */ + } B; + } SPP_DMA2_TCDWORD24__32B_tag; + + + /* Register layout for all registers TCDWORD28_... */ + + typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */ + vuint32_t R; + struct { + vuint32_t BITER:16; /* Enable Channel to Channel linking on minor loop complete */ + vuint32_t BWC:2; /* Bandwidth Control */ + vuint32_t MAJOR_LINKCH:6; /* Link Channel Number */ + vuint32_t DONE:1; /* channel done */ + vuint32_t ACTIVE:1; /* Channel Active */ + vuint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */ + vuint32_t E_SG:1; /* Enable Scatter/Gather Processing */ + vuint32_t D_REQ:1; /* Disable Request */ + vuint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */ + vuint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */ + vuint32_t START:1; /* Channel Start */ + } B; + } SPP_DMA2_TCDWORD28__32B_tag; + + + typedef struct SPP_DMA2_CHANNEL_struct_tag { + + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */ + + } SPP_DMA2_CHANNEL_tag; + + + typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */ + /* SPP_DMA2_DMACR - DMA Control Register */ + SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */ + /* SPP_DMA2_DMAES - DMA Error Status Register */ + SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */ + /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */ + /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */ + /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */ + /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */ + /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */ + /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */ + /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */ + /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */ + /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */ + /* SPP_DMA2_DMACERR - DMA Clear Error */ + SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */ + /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */ + /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */ + /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */ + /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */ + /* SPP_DMA2_DMAERRH - DMA Error Register */ + SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */ + /* SPP_DMA2_DMAERRL - DMA Error Register */ + SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */ + /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */ + /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */ + /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */ + int8_t SPP_DMA2_reserved_003C_C[196]; + union { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */ + + struct { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */ + }; + + }; + int8_t SPP_DMA2_reserved_0140_C[3776]; + union { + /* Register set CHANNEL */ + SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */ + + struct { + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */ + }; + + }; + } SPP_DMA2_tag; + + +#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL) + + + +/****************************************************************/ +/* */ +/* Module: INTC */ +/* */ +/****************************************************************/ + + typedef union { /* BCR - Block Configuration Register */ + vuint32_t R; + struct { + vuint32_t:18; + vuint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */ + vuint32_t:4; + vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */ + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_INTC + vuint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */ +#else + vuint32_t VTES:1; /* deprecated name - please avoid */ +#endif + vuint32_t:4; +#ifndef USE_FIELD_ALIASES_INTC + vuint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */ +#else + vuint32_t HVEN:1; /* deprecated name - please avoid */ +#endif + } B; + } INTC_BCR_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 0 */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC0_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 1 */ + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC1_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_INTC + vuint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */ +#else + vuint32_t VTBA:21; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_INTC + vuint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */ +#else + vuint32_t INTVEC:9; /* deprecated name - please avoid */ +#endif + vuint32_t:2; + } B; + } INTC_IACKR_PRC0_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + vuint32_t R; + struct { + vuint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */ + vuint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */ + vuint32_t:2; + } B; + } INTC_IACKR_PRC1_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 0 */ + vuint32_t R; + } INTC_EOIR_PRC0_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 1 */ + vuint32_t R; + } INTC_EOIR_PRC1_32B_tag; + + + /* Register layout for all registers SSCIR... */ + + typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t SET:1; /* Set Flag bit */ + vuint8_t CLR:1; /* Clear Flag bit */ + } B; + } INTC_SSCIR_8B_tag; + + typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t SET0:1; /* Set Flag 0 bit */ + vuint32_t CLR0:1; /* Clear Flag 0 bit */ + vuint32_t:6; + vuint32_t SET1:1; /* Set Flag 1 bit */ + vuint32_t CLR1:1; /* Clear Flag 1 bit */ + vuint32_t:6; + vuint32_t SET2:1; /* Set Flag 2 bit */ + vuint32_t CLR2:1; /* Clear Flag 2 bit */ + vuint32_t:6; + vuint32_t SET3:1; /* Set Flag 3 bit */ + vuint32_t CLR3:1; /* Clear Flag 3 bit */ + } B; + } INTC_SSCIR0_3_32B_tag; + + typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t SET4:1; /* Set Flag 4 bit */ + vuint32_t CLR4:1; /* Clear Flag 4 bit */ + vuint32_t:6; + vuint32_t SET5:1; /* Set Flag 5 bit */ + vuint32_t CLR5:1; /* Clear Flag 5 bit */ + vuint32_t:6; + vuint32_t SET6:1; /* Set Flag 6 bit */ + vuint32_t CLR6:1; /* Clear Flag 6 bit */ + vuint32_t:6; + vuint32_t SET7:1; /* Set Flag 7 bit */ + vuint32_t CLR7:1; /* Clear Flag 7 bit */ + } B; + } INTC_SSCIR4_7_32B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0-511 - Priority Select Registers */ + vuint8_t R; + struct { + vuint8_t PRC_SEL:2; /* Processor Select */ + vuint8_t:2; + vuint8_t PRI:4; /* Priority Select */ + } B; + } INTC_PSR_8B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */ + vuint32_t R; + struct { + vuint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */ + vuint32_t:2; + vuint32_t PRI0:4; /* Priority Select - Entry 0 */ + vuint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */ + vuint32_t:2; + vuint32_t PRI1:4; /* Priority Select - Entry 1 */ + vuint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */ + vuint32_t:2; + vuint32_t PRI2:4; /* Priority Select - Entry 2 */ + vuint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */ + vuint32_t:2; + vuint32_t PRI3:4; /* Priority Select - Entry 3 */ + } B; + } INTC_PSR_32B_tag; + + + + typedef struct INTC_struct_tag { /* start of INTC_tag */ + union { + INTC_BCR_32B_tag MCR; /* deprecated - please avoid */ + + /* BCR - Block Configuration Register */ + INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */ + + }; + int8_t INTC_reserved_0004_C[4]; + union { + /* CPR - Current Priority Register - Processor 0 */ + INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */ + + INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */ + + }; + /* CPR - Current Priority Register - Processor 1 */ + INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */ + union { + /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */ + + INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */ + + }; + /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */ + union { + /* EOIR- End of Interrupt Register - Processor 0 */ + INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */ + + INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */ + + }; + /* EOIR- End of Interrupt Register - Processor 1 */ + INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */ + union { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */ + + struct { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */ + }; + + struct { + /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */ + /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */ + }; + + }; + int8_t INTC_reserved_0028_C[24]; + union { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */ + + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */ + + struct { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */ + INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */ + INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */ + INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */ + INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */ + INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */ + INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */ + INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */ + INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */ + INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */ + INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */ + INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */ + INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */ + INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */ + INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */ + INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */ + INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */ + INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */ + INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */ + INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */ + INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */ + INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */ + INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */ + INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */ + INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */ + INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */ + INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */ + INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */ + INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */ + INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */ + INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */ + INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */ + INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */ + INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */ + INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */ + INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */ + INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */ + INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */ + INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */ + INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */ + INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */ + INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */ + INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */ + INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */ + INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */ + INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */ + INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */ + INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */ + INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */ + INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */ + INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */ + INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */ + INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */ + INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */ + INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */ + INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */ + INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */ + INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */ + INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */ + INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */ + INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */ + INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */ + INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */ + INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */ + INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */ + INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */ + INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */ + INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */ + INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */ + INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */ + INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */ + INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */ + INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */ + INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */ + INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */ + INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */ + INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */ + INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */ + INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */ + INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */ + INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */ + INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */ + INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */ + INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */ + INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */ + INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */ + INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */ + INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */ + INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */ + INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */ + INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */ + INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */ + INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */ + INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */ + INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */ + INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */ + INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */ + INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */ + INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */ + INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */ + INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */ + INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */ + INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */ + INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */ + INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */ + INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */ + INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */ + INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */ + INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */ + INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */ + INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */ + INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */ + INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */ + INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */ + INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */ + INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */ + INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */ + INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */ + INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */ + INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */ + INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */ + INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */ + INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */ + INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */ + INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */ + INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */ + INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */ + INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */ + }; + + struct { + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */ + INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */ + INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */ + INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */ + INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */ + INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */ + INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */ + INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */ + INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */ + INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */ + INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */ + INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */ + INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */ + INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */ + INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */ + INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */ + INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */ + INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */ + INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */ + INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */ + INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */ + INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */ + INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */ + INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */ + INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */ + INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */ + INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */ + INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */ + INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */ + INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */ + INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */ + INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */ + INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */ + INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */ + INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */ + INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */ + INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */ + INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */ + INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */ + INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */ + INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */ + INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */ + INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */ + INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */ + INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */ + INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */ + INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */ + INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */ + INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */ + INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */ + INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */ + INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */ + INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */ + INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */ + INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */ + INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */ + INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */ + INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */ + INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */ + INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */ + INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */ + INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */ + INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */ + INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */ + INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */ + INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */ + INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */ + INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */ + INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */ + INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */ + INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */ + INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */ + INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */ + INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */ + INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */ + INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */ + INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */ + INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */ + INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */ + INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */ + INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */ + INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */ + INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */ + INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */ + INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */ + INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */ + INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */ + INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */ + INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */ + INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */ + INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */ + INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */ + INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */ + INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */ + INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */ + INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */ + INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */ + INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */ + INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */ + INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */ + INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */ + INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */ + INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */ + INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */ + INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */ + INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */ + INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */ + INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */ + INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */ + INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */ + INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */ + INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */ + INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */ + INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */ + INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */ + INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */ + INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */ + INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */ + INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */ + INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */ + INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */ + INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */ + INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */ + INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */ + INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */ + INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */ + INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */ + INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */ + INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */ + INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */ + INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */ + INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */ + INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */ + INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */ + INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */ + INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */ + INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */ + INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */ + INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */ + INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */ + INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */ + INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */ + INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */ + INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */ + INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */ + INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */ + INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */ + INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */ + INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */ + INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */ + INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */ + INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */ + INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */ + INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */ + INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */ + INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */ + INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */ + INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */ + INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */ + INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */ + INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */ + INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */ + INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */ + INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */ + INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */ + INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */ + INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */ + INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */ + INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */ + INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */ + INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */ + INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */ + INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */ + INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */ + INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */ + INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */ + INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */ + INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */ + INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */ + INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */ + INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */ + INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */ + INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */ + INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */ + INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */ + INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */ + INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */ + INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */ + INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */ + INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */ + INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */ + INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */ + INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */ + INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */ + INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */ + INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */ + INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */ + INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */ + INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */ + INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */ + INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */ + INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */ + INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */ + INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */ + INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */ + INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */ + INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */ + INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */ + INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */ + INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */ + INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */ + INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */ + INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */ + INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */ + INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */ + INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */ + INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */ + INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */ + INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */ + INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */ + INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */ + INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */ + INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */ + INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */ + INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */ + INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */ + INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */ + INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */ + INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */ + INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */ + INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */ + INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */ + INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */ + INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */ + INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */ + INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */ + INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */ + INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */ + INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */ + INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */ + INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */ + INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */ + INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */ + INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */ + INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */ + INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */ + INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */ + INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */ + INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */ + INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */ + INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */ + INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */ + INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */ + INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */ + INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */ + INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */ + INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */ + INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */ + INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */ + INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */ + INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */ + INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */ + INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */ + INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */ + INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */ + INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */ + INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */ + INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */ + INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */ + INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */ + INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */ + INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */ + INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */ + INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */ + INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */ + INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */ + INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */ + INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */ + INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */ + INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */ + INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */ + INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */ + INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */ + INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */ + INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */ + INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */ + INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */ + INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */ + INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */ + INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */ + INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */ + INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */ + INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */ + INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */ + INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */ + INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */ + INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */ + INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */ + INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */ + INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */ + INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */ + INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */ + INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */ + INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */ + INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */ + INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */ + INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */ + INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */ + INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */ + INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */ + INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */ + INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */ + INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */ + INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */ + INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */ + INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */ + INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */ + INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */ + INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */ + INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */ + INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */ + INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */ + INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */ + INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */ + INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */ + INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */ + INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */ + INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */ + INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */ + INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */ + INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */ + INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */ + INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */ + INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */ + INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */ + INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */ + INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */ + INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */ + INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */ + INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */ + INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */ + INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */ + INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */ + INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */ + INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */ + INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */ + INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */ + INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */ + INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */ + INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */ + INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */ + INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */ + INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */ + INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */ + INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */ + INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */ + INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */ + INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */ + INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */ + INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */ + INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */ + INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */ + INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */ + INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */ + INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */ + INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */ + INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */ + INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */ + INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */ + INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */ + INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */ + INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */ + INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */ + INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */ + INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */ + INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */ + INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */ + INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */ + INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */ + INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */ + INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */ + INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */ + INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */ + INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */ + INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */ + INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */ + INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */ + INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */ + INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */ + INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */ + INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */ + INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */ + INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */ + INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */ + INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */ + INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */ + INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */ + INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */ + INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */ + INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */ + INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */ + INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */ + INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */ + INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */ + INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */ + INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */ + INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */ + INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */ + INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */ + INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */ + INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */ + INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */ + INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */ + INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */ + INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */ + INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */ + INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */ + INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */ + INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */ + INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */ + INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */ + INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */ + INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */ + INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */ + INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */ + INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */ + INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */ + INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */ + INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */ + INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */ + INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */ + INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */ + INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */ + INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */ + INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */ + INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */ + INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */ + INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */ + INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */ + INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */ + INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */ + INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */ + INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */ + INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */ + INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */ + INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */ + INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */ + INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */ + INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */ + INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */ + INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */ + INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */ + INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */ + INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */ + INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */ + INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */ + INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */ + INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */ + INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */ + INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */ + INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */ + INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */ + INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */ + INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */ + INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */ + INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */ + INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */ + INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */ + INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */ + INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */ + INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */ + INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */ + INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */ + INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */ + INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */ + INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */ + INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */ + INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */ + INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */ + INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */ + INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */ + INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */ + INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */ + INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */ + INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */ + INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */ + INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */ + INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */ + INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */ + INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */ + INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */ + INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */ + INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */ + INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */ + INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */ + INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */ + INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */ + INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */ + INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */ + INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */ + INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */ + INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */ + INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */ + INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */ + INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */ + INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */ + INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */ + INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */ + INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */ + INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */ + INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */ + INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */ + }; + + }; + } INTC_tag; + + +#define INTC (*(volatile INTC_tag *) 0xFFF48000UL) + + + +/****************************************************************/ +/* */ +/* Module: DSPI */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t MSTR:1; /* Master/Slave mode select */ + vuint32_t CONT_SCKE:1; /* Continuous SCK Enable */ + vuint32_t DCONF:2; /* DSPI Configuration */ + vuint32_t FRZ:1; /* Freeze */ + vuint32_t MTFE:1; /* Modified Timing Format Enable */ + vuint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */ + vuint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */ + vuint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */ + vuint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */ + vuint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */ + vuint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */ + vuint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */ + vuint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */ + vuint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */ + vuint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */ + vuint32_t DOZE:1; /* Doze Enable */ + vuint32_t MDIS:1; /* Module Disable */ + vuint32_t DIS_TXF:1; /* Disable Transmit FIFO */ + vuint32_t DIS_RXF:1; /* Disable Receive FIFO */ + vuint32_t CLR_TXF:1; /* Clear TX FIFO */ + vuint32_t CLR_RXF:1; /* Clear RX FIFO */ + vuint32_t SMPL_PT:2; /* Sample Point */ + vuint32_t:7; + vuint32_t HALT:1; /* Halt */ + } B; + } DSPI_MCR_32B_tag; + + typedef union { /* TCR - Transfer Count Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t SPI_TCNT:16; /* SPI Transfer Counter */ +#else + vuint32_t TCNT:16; /* deprecated name - please avoid */ +#endif + vuint32_t:16; + } B; + } DSPI_TCR_32B_tag; + + + /* Register layout for all registers CTAR... */ + + typedef union { /* CTAR0-7 - Clock and Transfer Attribute Registers */ + vuint32_t R; + struct { + vuint32_t DBR:1; /* Double Baud Rate */ + vuint32_t FMSZ:4; /* Frame Size */ + vuint32_t CPOL:1; /* Clock Polarity */ + vuint32_t CPHA:1; /* Clock Phase */ + vuint32_t LSBFE:1; /* LSB First Enable */ + vuint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */ + vuint32_t PASC:2; /* After SCK Delay Prescaler */ + vuint32_t PDT:2; /* Delay after Transfer Prescaler */ + vuint32_t PBR:2; /* Baud Rate Prescaler */ + vuint32_t CSSCK:4; /* PCS to SCK Delay Scaler */ + vuint32_t ASC:4; /* After SCK Delay Scaler */ + vuint32_t DT:4; /* Delay after Transfer Scaler */ + vuint32_t BR:4; /* Baud Rate Scaler */ + } B; + } DSPI_CTAR_32B_tag; + + typedef union { /* SR - Status Register */ + vuint32_t R; + struct { + vuint32_t TCF:1; /* Transfer Complete Flag */ + vuint32_t TXRXS:1; /* TX & RX Status */ + vuint32_t:1; + vuint32_t EOQF:1; /* End of queue Flag */ + vuint32_t TFUF:1; /* Transmit FIFO Underflow Flag */ + vuint32_t:1; + vuint32_t TFFF:1; /* Transmit FIFO FIll Flag */ + vuint32_t:5; + vuint32_t RFOF:1; /* Receive FIFO Overflow Flag */ + vuint32_t:1; + vuint32_t RFDF:1; /* Receive FIFO Drain Flag */ + vuint32_t:1; + vuint32_t TXCTR:4; /* TX FIFO Counter */ + vuint32_t TXNXTPTR:4; /* Transmit Next Pointer */ + vuint32_t RXCTR:4; /* RX FIFO Counter */ + vuint32_t POPNXTPTR:4; /* Pop Next Pointer */ + } B; + } DSPI_SR_32B_tag; + + typedef union { /* RSER - DMA/Interrupt Request Register */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t TCF_RE:1; /* Transmission Complete Request Enable */ +#else + vuint32_t TCFRE:1; /* deprecated name - please avoid */ +#endif + vuint32_t:2; +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t EOQF_RE:1; /* DSPI Finished Request Enable */ +#else + vuint32_t EOQFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */ +#else + vuint32_t TFUFRE:1; /* deprecated name - please avoid */ +#endif + vuint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */ +#else + vuint32_t TFFFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */ +#else + vuint32_t TFFFDIRS:1; /* deprecated name - please avoid */ +#endif + vuint32_t:4; +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */ +#else + vuint32_t RFOFRE:1; /* deprecated name - please avoid */ +#endif + vuint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */ +#else + vuint32_t RFDFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */ +#else + vuint32_t RFDFDIRS:1; /* deprecated name - please avoid */ +#endif + vuint32_t:16; + } B; + } DSPI_RSER_32B_tag; + + typedef union { /* PUSHR - PUSH TX FIFO Register */ + vuint32_t R; + struct { + vuint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */ + vuint32_t CTAS:3; /* Clock and Transfer Attributes Select */ + vuint32_t EOQ:1; /* End of Queue */ + vuint32_t CTCNT:1; /* Clear SPI_TCNT */ + vuint32_t:2; + vuint32_t PCS7:1; /* Peripheral Chip Select 7 */ + vuint32_t PCS6:1; /* Peripheral Chip Select 6 */ + vuint32_t PCS5:1; /* Peripheral Chip Select 5 */ + vuint32_t PCS4:1; /* Peripheral Chip Select 4 */ + vuint32_t PCS3:1; /* Peripheral Chip Select 3 */ + vuint32_t PCS2:1; /* Peripheral Chip Select 2 */ + vuint32_t PCS1:1; /* Peripheral Chip Select 1 */ + vuint32_t PCS0:1; /* Peripheral Chip Select 0 */ + vuint32_t TXDATA:16; /* Transmit Data */ + } B; + } DSPI_PUSHR_32B_tag; + + typedef union { /* POPR - POP RX FIFO Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; /* Receive Data */ + } B; + } DSPI_POPR_32B_tag; + + + /* Register layout for all registers TXFR... */ + + typedef union { /* Transmit FIFO Registers */ + vuint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t FIFO_TXCMD:16; /* Transmit Command */ +#else + vuint32_t TXCMD:16; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t FIFO_TXDATA:16; /* Transmit Data */ +#else + vuint32_t TXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_TXFR_32B_tag; + + + /* Register layout for all registers RXFR... */ + + typedef union { /* Receive FIFO Registers */ + vuint32_t R; + struct { + vuint32_t:16; +#ifndef USE_FIELD_ALIASES_DSPI + vuint32_t FIFO_RXDATA:16; /* Transmit Data */ +#else + vuint32_t RXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_RXFR_32B_tag; + + typedef union { /* DSICR - DSI Configuration Register */ + vuint32_t R; + struct { + vuint32_t MTOE:1; /* Multiple Transfer Operation Enable */ + vuint32_t:1; + vuint32_t MTOCNT:6; /* Multiple Transfer Operation Count */ + vuint32_t:4; + vuint32_t TXSS:1; /* Transmit Data Source Select */ + vuint32_t TPOL:1; /* Trigger Polarity */ + vuint32_t TRRE:1; /* Trigger Reception Enable */ + vuint32_t CID:1; /* Change in Data Transfer Enable */ + vuint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */ + vuint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */ + vuint32_t:4; + vuint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */ + vuint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */ + vuint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */ + vuint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */ + vuint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */ + vuint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */ + vuint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */ + vuint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */ + } B; + } DSPI_DSICR_32B_tag; + + typedef union { /* SDR - DSI Serialization Data Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SER_DATA:16; /* Serialized Data */ + } B; + } DSPI_SDR_32B_tag; + + typedef union { /* ASDR - DSI Alternate Serialization Data Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t ASER_DATA:16; /* Alternate Serialized Data */ + } B; + } DSPI_ASDR_32B_tag; + + typedef union { /* COMPR - DSI Transmit Comparison Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t COMP_DATA:16; /* Compare Data */ + } B; + } DSPI_COMPR_32B_tag; + + typedef union { /* DDR - DSI Deserialization Data Register */ + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t DESER_DATA:16; /* Deserialized Data */ + } B; + } DSPI_DDR_32B_tag; + + typedef union { /* DSICR1 - DSI Configuration Register 1 */ + vuint32_t R; + } DSPI_DSICR1_32B_tag; + + + + typedef struct DSPI_struct_tag { /* start of DSPI_tag */ + /* MCR - Module Configuration Register */ + DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + int8_t DSPI_reserved_0004[4]; + /* TCR - Transfer Count Register */ + DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */ + union { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */ + + struct { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */ + }; + + }; + /* SR - Status Register */ + DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */ + /* RSER - DMA/Interrupt Request Register */ + DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */ + /* PUSHR - PUSH TX FIFO Register */ + DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */ + /* POPR - POP RX FIFO Register */ + DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */ + union { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */ + + struct { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */ + DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0050_C[44]; + union { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */ + + struct { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */ + DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0090[44]; + /* DSICR - DSI Configuration Register */ + DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */ + /* SDR - DSI Serialization Data Register */ + DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */ + /* ASDR - DSI Alternate Serialization Data Register */ + DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */ + /* COMPR - DSI Transmit Comparison Register */ + DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */ + /* DDR - DSI Deserialization Data Register */ + DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */ + /* DSICR1 - DSI Configuration Register 1 */ + DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */ + } DSPI_tag; + + +#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL) +#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL) + + + +/****************************************************************/ +/* */ +/* Module: FLEXCAN */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + vuint32_t R; + struct { + vuint32_t MDIS:1; /* Module Disable */ + vuint32_t FRZ:1; /* Freeze Enable */ + vuint32_t FEN:1; /* FIFO Enable */ + vuint32_t HALT:1; /* Halt Flexcan */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t NOT_RDY:1; /* Flexcan Not Ready */ +#else + vuint32_t NOTRDY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */ +#else + vuint32_t WAKMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t SOFT_RST:1; /* Soft Reset */ +#else + vuint32_t SOFTRST:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */ +#else + vuint32_t FRZACK:1; /* deprecated name - please avoid */ +#endif + vuint32_t SUPV:1; /* Supervisor Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t SLF_WAK:1; /* Self Wake Up */ +#else + vuint32_t SLFWAK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t WRN_EN:1; /* Warning Interrupt Enable */ +#else + vuint32_t WRNEN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */ +#else + vuint32_t LPMACK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t WAK_SRC:1; /* Wake Up Source */ +#else + vuint32_t WAKSRC:1; /* deprecated name - please avoid */ +#endif + vuint32_t DOZE:1; /* Doze Mode Enable */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t SRX_DIS:1; /* Self Reception Disable */ +#else + vuint32_t SRXDIS:1; /* deprecated name - please avoid */ +#endif + vuint32_t BCC:1; /* Backwards Compatibility Configuration */ + vuint32_t:2; + vuint32_t LPRIO_EN:1; /* Local Priority Enable */ + vuint32_t AEN:1; /* Abort Enable */ + vuint32_t:2; + vuint32_t IDAM:2; /* ID Acceptance Mode */ + vuint32_t:2; + vuint32_t MAXMB:6; /* Maximum Number of Message Buffers */ + } B; + } FLEXCAN_MCR_32B_tag; + + typedef union { /* CTRL - Control Register */ + vuint32_t R; + struct { + vuint32_t PRESDIV:8; /* Prescaler Divsion Factor */ + vuint32_t RJW:2; /* Resync Jump Width */ + vuint32_t PSEG1:3; /* Phase Segment 1 */ + vuint32_t PSEG2:3; /* Phase Segment 2 */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BOFF_MSK:1; /* Bus Off Mask */ +#else + vuint32_t BOFFMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t ERR_MSK:1; /* Error Mask */ +#else + vuint32_t ERRMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t CLK_SRC:1; /* CAN Engine Clock Source */ +#else + vuint32_t CLKSRC:1; /* deprecated name - please avoid */ +#endif + vuint32_t LPB:1; /* Loop Back */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */ +#else + vuint32_t TWRNMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */ +#else + vuint32_t RWRNMSK:1; /* deprecated name - please avoid */ +#endif + vuint32_t:2; + vuint32_t SMP:1; /* Sampling Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BOFF_REC:1; /* Bus Off Recovery Mode */ +#else + vuint32_t BOFFREC:1; /* deprecated name - please avoid */ +#endif + vuint32_t TSYN:1; /* Timer Sync Mode */ + vuint32_t LBUF:1; /* Lowest Buffer Transmitted First */ + vuint32_t LOM:1; /* Listen-Only Mode */ + vuint32_t PROPSEG:3; /* Propagation Segment */ + } B; + } FLEXCAN_CTRL_32B_tag; + + typedef union { /* TIMER - Free Running Timer */ + vuint32_t R; + } FLEXCAN_TIMER_32B_tag; + + typedef union { /* RXGMASK - Rx Global Mask Register */ + vuint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + vuint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RXGMASK_32B_tag; + + typedef union { /* RX14MASK - Rx 14 Mask Register */ + vuint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + vuint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX14MASK_32B_tag; + + typedef union { /* RX15MASK - Rx 15 Mask Register */ + vuint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + vuint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX15MASK_32B_tag; + + typedef union { /* ECR - Error Counter Register */ + vuint32_t R; + struct { + vuint32_t:16; +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */ +#else + vuint32_t RXECNT:8; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */ +#else + vuint32_t TXECNT:8; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ECR_32B_tag; + + typedef union { /* ESR - Error and Status Register */ + vuint32_t R; + struct { + vuint32_t:14; +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */ +#else + vuint32_t TWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */ +#else + vuint32_t RWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BIT1_ERR:1; /* Bit 1 Error */ +#else + vuint32_t BIT1ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BIT0_ERR:1; /* Bit 0 Error */ +#else + vuint32_t BIT0ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t ACK_ERR:1; /* Acknowledge Error */ +#else + vuint32_t ACKERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */ +#else + vuint32_t CRCERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t FRM_ERR:1; /* Form Error */ +#else + vuint32_t FRMERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t STF_ERR:1; /* Stuffing Error */ +#else + vuint32_t STFERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t TX_WRN:1; /* Tx Error Counter */ +#else + vuint32_t TXWRN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t RX_WRN:1; /* Rx Error Counter */ +#else + vuint32_t RXWRN:1; /* deprecated name - please avoid */ +#endif + vuint32_t IDLE:1; /* CAN bus Idle State */ + vuint32_t TXRX:1; /* Current Flexcan Status */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t FLT_CONF:2; /* Fault Confinement State */ +#else + vuint32_t FLTCONF:2; /* deprecated name - please avoid */ +#endif + vuint32_t:1; +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BOFF_INT:1; /* Bus Off Interrupt */ +#else + vuint32_t BOFFINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t ERR_INT:1; /* Error Interrupt */ +#else + vuint32_t ERRINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t WAK_INT:1; /* Wake-Up Interrupt */ +#else + vuint32_t WAKINT:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ESR_32B_tag; + + typedef union { /* IMASK2 - Interrupt Masks 2 Register */ + vuint32_t R; + struct { + vuint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */ + vuint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */ + vuint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */ + vuint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */ + vuint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */ + vuint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */ + vuint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */ + vuint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */ + vuint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */ + vuint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */ + vuint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */ + vuint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */ + vuint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */ + vuint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */ + vuint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */ + vuint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */ + vuint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */ + vuint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */ + vuint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */ + vuint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */ + vuint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */ + vuint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */ + vuint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */ + vuint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */ + vuint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */ + vuint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */ + vuint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */ + vuint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */ + vuint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */ + vuint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */ + vuint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */ + vuint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */ + } B; + } FLEXCAN_IMASK2_32B_tag; + + typedef union { /* IMASK1 - Interrupt Masks 1 Register */ + vuint32_t R; + struct { + vuint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */ + vuint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */ + vuint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */ + vuint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */ + vuint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */ + vuint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */ + vuint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */ + vuint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */ + vuint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */ + vuint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */ + vuint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */ + vuint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */ + vuint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */ + vuint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */ + vuint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */ + vuint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */ + vuint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */ + vuint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */ + vuint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */ + vuint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */ + vuint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */ + vuint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */ +#else + vuint32_t BUF09M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */ +#else + vuint32_t BUF08M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */ +#else + vuint32_t BUF07M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */ +#else + vuint32_t BUF06M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */ +#else + vuint32_t BUF05M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */ +#else + vuint32_t BUF04M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */ +#else + vuint32_t BUF03M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */ +#else + vuint32_t BUF02M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */ +#else + vuint32_t BUF01M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */ +#else + vuint32_t BUF00M:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IMASK1_32B_tag; + + typedef union { /* IFLAG2 - Interrupt Flags 2 Register */ + vuint32_t R; + struct { + vuint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */ + vuint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */ + vuint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */ + vuint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */ + vuint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */ + vuint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */ + vuint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */ + vuint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */ + vuint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */ + vuint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */ + vuint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */ + vuint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */ + vuint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */ + vuint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */ + vuint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */ + vuint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */ + vuint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */ + vuint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */ + vuint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */ + vuint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */ + vuint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */ + vuint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */ + vuint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */ + vuint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */ + vuint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */ + vuint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */ + vuint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */ + vuint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */ + vuint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */ + vuint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */ + vuint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */ + vuint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */ + } B; + } FLEXCAN_IFLAG2_32B_tag; + + typedef union { /* IFLAG1 - Interrupt Flags 1 Register */ + vuint32_t R; + struct { + vuint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */ + vuint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */ + vuint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */ + vuint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */ + vuint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */ + vuint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */ + vuint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */ + vuint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */ + vuint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */ + vuint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */ + vuint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */ + vuint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */ + vuint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */ + vuint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */ + vuint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */ + vuint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */ + vuint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */ + vuint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */ + vuint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */ + vuint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */ + vuint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */ + vuint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */ +#else + vuint32_t BUF09I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */ +#else + vuint32_t BUF08I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */ +#else + vuint32_t BUF07I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */ +#else + vuint32_t BUF06I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */ +#else + vuint32_t BUF05I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */ +#else + vuint32_t BUF04I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */ +#else + vuint32_t BUF03I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */ +#else + vuint32_t BUF02I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */ +#else + vuint32_t BUF01I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + vuint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */ +#else + vuint32_t BUF00I:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IFLAG1_32B_tag; + + + /* Register layout for all registers MSG_CS... */ + + typedef union { /* Message Buffer Control and Status */ + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; /* Message Buffer Code */ + vuint32_t:1; + vuint32_t SRR:1; /* Substitute Remote Request */ + vuint32_t IDE:1; /* ID Extended Bit */ + vuint32_t RTR:1; /* Remote Transmission Request */ + vuint32_t LENGTH:4; /* Length of Data in Bytes */ + vuint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */ + } B; + } FLEXCAN_MSG_CS_32B_tag; + + + /* Register layout for all registers MSG_ID... */ + + typedef union { /* Message Buffer Identifier Field */ + vuint32_t R; + struct { + vuint32_t PRIO:3; /* Local Priority */ + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } FLEXCAN_MSG_ID_32B_tag; + + + /* Register layout for all registers MSG_BYTE0_3... */ + + typedef union { /* Message Buffer Data Register */ + vuint32_t R; + vuint8_t BYTE[4]; /* individual bytes can be accessed */ + vuint32_t WORD; /* individual words can be accessed */ + } FLEXCAN_MSG_DATA_32B_tag; + + typedef union { + vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + vuint32_t R[2]; /* Data buffer in words (32 bits) */ + } FLEXCAN_MSG_DATA2_32B_tag; + + /* Register layout for all registers MSG_BYTE4_7 matches xxx */ + + + /* Register layout for all registers RXIMR... */ + + typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + vuint32_t R; + } FLEXCAN_RXIMR_32B_tag; + + + typedef struct FLEXCAN_MB_struct_tag { + + union { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */ + FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */ + }; + union { + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */ + FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */ + }; + union { /* Message Buffer Data Register */ + + struct { + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */ + }; + + FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */ + + }; + + } FLEXCAN_MB_tag; + + + typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */ + /* MCR - Module Configuration Register */ + FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + union { + /* CTRL - Control Register */ + FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */ + + FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */ + + }; + /* TIMER - Free Running Timer */ + FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */ + int8_t FLEXCAN_reserved_000C[4]; + /* RXGMASK - Rx Global Mask Register */ + FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */ + /* RX14MASK - Rx 14 Mask Register */ + FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */ + /* RX15MASK - Rx 15 Mask Register */ + FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */ + /* ECR - Error Counter Register */ + FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */ + /* ESR - Error and Status Register */ + FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */ + union { + FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */ + + /* IMASK2 - Interrupt Masks 2 Register */ + FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */ + + }; + union { + FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */ + + /* IMASK1 - Interrupt Masks 1 Register */ + FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */ + + /* IFLAG2 - Interrupt Flags 2 Register */ + FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */ + + /* IFLAG1 - Interrupt Flags 1 Register */ + FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */ + + }; + int8_t FLEXCAN_reserved_0034_C[76]; + union { + /* Register set MB */ + FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */ + + /* Alias name for MB */ + FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */ + + struct { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */ + }; + + }; + int8_t FLEXCAN_reserved_0480_C[1024]; + union { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */ + + struct { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */ + }; + + }; + } FLEXCAN_tag; + + +#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL) +#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL) + + + +/****************************************************************/ +/* */ +/* Module: DMA_CH_MUX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CHCONFIG... */ + + typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */ + vuint8_t R; + struct { + vuint8_t ENBL:1; /* DMA Channel Enable */ + vuint8_t TRIG:1; /* DMA Channel Trigger Enable */ + vuint8_t SOURCE:6; /* DMA Channel Source */ + } B; + } DMA_CH_MUX_CHCONFIG_8B_tag; + + + + typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */ + union { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */ + }; + + }; + } DMA_CH_MUX_tag; + + +#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: FR */ +/* */ +/****************************************************************/ + + typedef union { /* Module Version Number */ + vuint16_t R; + struct { + vuint16_t CHIVER:8; /* VERSION NUMBER OF CHI */ + vuint16_t PEVER:8; /* VERSION NUMBER OF PE */ + } B; + } FR_MVR_16B_tag; + + typedef union { /* Module Configuration Register */ + vuint16_t R; + struct { + vuint16_t MEN:1; /* Module Enable */ + vuint16_t SBFF:1; /* System Bus Failure Freeze */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SCM:1; /* single channel device mode */ +#else + vuint16_t SCMD:1; /* deprecated name - please avoid */ +#endif + vuint16_t CHB:1; /* Channel B enable */ + vuint16_t CHA:1; /* channel A enable */ + vuint16_t SFFE:1; /* Sync. frame filter Enable */ + vuint16_t ECCE:1; /* ECC Functionlity Enable */ + vuint16_t TMODER:1; /* Functional Test mode */ + vuint16_t FUM:1; /* FIFO Update Mode */ + vuint16_t FAM:1; /* FIFO Address Mode */ + vuint16_t:1; + vuint16_t CLKSEL:1; /* Protocol Engine clock source select */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t BITRATE:3; /* Bus bit rate */ +#else + vuint16_t PRESCALE:3; /* deprecated name - please avoid */ +#endif + vuint16_t:1; + } B; + } FR_MCR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */ + vuint16_t R; + struct { + vuint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */ + } B; + } FR_SYMBADHR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */ + vuint16_t R; + struct { + vuint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */ + vuint16_t:4; + } B; + } FR_SYMBADLR_16B_tag; + + typedef union { /* STROBE SIGNAL CONTROL REGISTER */ + vuint16_t R; + struct { + vuint16_t WMD:1; /* DEFINES WRITE MODE OF REG */ + vuint16_t:3; + vuint16_t SEL:4; /* STROBE SIGNSL SELECT */ + vuint16_t:3; + vuint16_t ENB:1; /* STROBE SIGNAL ENABLE */ + vuint16_t:2; + vuint16_t STBPSEL:2; /* STROBE PORT SELECT */ + } B; + } FR_STBSCR_16B_tag; + + typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */ + vuint16_t:1; + vuint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */ + } B; + } FR_MBDSR_16B_tag; + + typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */ + vuint16_t:2; + vuint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */ + } B; + } FR_MBSSUTR_16B_tag; + + typedef union { /* PE DRAM ACCESS REGISTER */ + vuint16_t R; + struct { + vuint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */ + vuint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */ + vuint16_t DAD:1; /* PE DRAM ACCESS DONE */ + } B; + } FR_PEDRAR_16B_tag; + + typedef union { /* PE DRAM DATA REGISTER */ + vuint16_t R; + struct { + vuint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */ + } B; + } FR_PEDRDR_16B_tag; + + typedef union { /* PROTOCOL OPERATION CONTROL REG */ + vuint16_t R; + struct { + vuint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */ + vuint16_t:3; + vuint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */ + vuint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */ + vuint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */ + vuint16_t:3; + vuint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */ + } B; + } FR_POCR_16B_tag; + + typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + vuint16_t R; + struct { + vuint16_t MIF:1; /* MODULE INTERRUPT FLAG */ + vuint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */ + vuint16_t CHIF:1; /* CHI INTERRUPT FLAG */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */ +#else + vuint16_t WKUPIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */ +#else + vuint16_t FNEBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */ +#else + vuint16_t FNEAIF:1; /* deprecated name - please avoid */ +#endif + vuint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */ + vuint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */ + vuint16_t MIE:1; /* MODULE INTERRUPT ENABLE */ + vuint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */ + vuint16_t CHIE:1; /* CHI INTERRUPT ENABLE */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */ +#else + vuint16_t WKUPIE:1; /* deprecated name - please avoid */ +#endif + vuint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */ + vuint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */ + vuint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */ + vuint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */ + } B; + } FR_GIFER_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + vuint16_t FATLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + vuint16_t INTLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */ +#else + vuint16_t ILCFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */ +#else + vuint16_t CSAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */ +#else + vuint16_t MRCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */ +#else + vuint16_t MOCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */ +#else + vuint16_t CCLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */ +#else + vuint16_t MXSIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */ +#else + vuint16_t MTXIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */ +#else + vuint16_t LTXBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */ +#else + vuint16_t LTXAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */ +#else + vuint16_t TBVBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */ +#else + vuint16_t TBVAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */ +#else + vuint16_t TI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */ +#else + vuint16_t TI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */ +#else + vuint16_t CYSIF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIFR0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */ +#else + vuint16_t EMCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */ +#else + vuint16_t IPCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */ +#else + vuint16_t PECFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */ +#else + vuint16_t PSCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */ +#else + vuint16_t SSI3IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */ +#else + vuint16_t SSI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */ +#else + vuint16_t SSI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */ +#else + vuint16_t SSI0IF:1; /* deprecated name - please avoid */ +#endif + vuint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + vuint16_t EVTIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + vuint16_t ODTIF:1; /* deprecated name - please avoid */ +#endif + vuint16_t:4; + } B; + } FR_PIFR1_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + vuint16_t FATLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + vuint16_t INTLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */ +#else + vuint16_t ILCFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */ +#else + vuint16_t CSAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */ +#else + vuint16_t MRCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */ +#else + vuint16_t MOCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */ +#else + vuint16_t CCLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */ +#else + vuint16_t MXSIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */ +#else + vuint16_t MTXIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */ +#else + vuint16_t LTXBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */ +#else + vuint16_t LTXAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */ +#else + vuint16_t TBVBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */ +#else + vuint16_t TBVAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */ +#else + vuint16_t TI2IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */ +#else + vuint16_t TI1IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */ +#else + vuint16_t CYSIE:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIER0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */ +#else + vuint16_t EMCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */ +#else + vuint16_t IPCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */ +#else + vuint16_t PECFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */ +#else + vuint16_t PSCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */ +#else + vuint16_t SSI3IE:1; + vuint16_t SSI2IE:1; + vuint16_t SSI1IE:1; + vuint16_t SSI0IE:1; +#endif + + vuint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + vuint16_t EVTIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + vuint16_t ODTIE:1; /* deprecated name - please avoid */ +#endif + vuint16_t:4; + } B; + } FR_PIER1_16B_tag; + + typedef union { /* CHI ERROR FLAG REGISTER */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */ +#else + vuint16_t FRLBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */ +#else + vuint16_t FRLAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */ +#else + vuint16_t PCMIEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */ +#else + vuint16_t FOVBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */ +#else + vuint16_t FOVAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */ +#else + vuint16_t MSBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */ +#else + vuint16_t MBUEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LCK_EF:1; /* LOCK ERROR FLAG */ +#else + vuint16_t LCKEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */ +#else + vuint16_t DBLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */ +#else + vuint16_t SBCFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FID_EF:1; /* FRAME ID ERROR FLAG */ +#else + vuint16_t FIDEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */ +#else + vuint16_t DPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */ +#else + vuint16_t SPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */ +#else + vuint16_t NMLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */ +#else + vuint16_t NMFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */ +#else + vuint16_t ILSAEF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CHIERFR_16B_tag; + + typedef union { /* Message Buffer Interrupt Vector Register */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */ + vuint16_t:2; + vuint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */ + } B; + } FR_MBIVEC_16B_tag; + + typedef union { /* Channel A Status Error Counter Register */ + vuint16_t R; + struct { + vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CASERCR_16B_tag; + + typedef union { /* Channel B Status Error Counter Register */ + vuint16_t R; + struct { + vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CBSERCR_16B_tag; + + typedef union { /* Protocol Status Register 0 */ + vuint16_t R; + struct { + vuint16_t ERRMODE:2; /* Error Mode */ + vuint16_t SLOTMODE:2; /* Slot Mode */ + vuint16_t:1; + vuint16_t PROTSTATE:3; /* Protocol State */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t STARTUPSTATE:4; /* Startup State */ +#else + vuint16_t SUBSTATE:4; /* deprecated name - please avoid */ +#endif + vuint16_t WAKEUPSTATE:4; /* Wakeup Status */ + } B; + } FR_PSR0_16B_tag; + + typedef union { /* Protocol Status Register 1 */ + vuint16_t R; + struct { + vuint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CSP:1; /* Leading Coldstart Path */ +#else + vuint16_t SCP:1; /* deprecated name - please avoid */ +#endif + vuint16_t:1; + vuint16_t REMCSAT:5; /* Remaining Coldstart Attempts */ + vuint16_t CPN:1; /* Leading Coldstart Path Noise */ + vuint16_t HHR:1; /* Host Halt Request Pending */ + vuint16_t FRZ:1; /* Freeze Occurred */ + vuint16_t APTAC:5; /* Allow Passive to Active Counter */ + } B; + } FR_PSR1_16B_tag; + + typedef union { /* Protocol Status Register 2 */ + vuint16_t R; + struct { + vuint16_t NBVB:1; /* NIT Boundary Violation on Channel B */ + vuint16_t NSEB:1; /* NIT Syntax Error on Channel B */ + vuint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */ +#else + vuint16_t SBVB:1; /* deprecated name - please avoid */ +#endif + vuint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */ + vuint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */ + vuint16_t NBVA:1; /* NIT Boundary Violation on Channel A */ + vuint16_t NSEA:1; /* NIT Syntax Error on Channel A */ + vuint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */ + vuint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */ + vuint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */ + vuint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */ + vuint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */ + } B; + } FR_PSR2_16B_tag; + + typedef union { /* Protocol Status Register 3 */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t WUB:1; /* Wakeup Symbol Received on Channel B */ + vuint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */ + vuint16_t AACB:1; /* Aggregated Additional Communication on Channel B */ + vuint16_t ACEB:1; /* Aggregated Content Error on Channel B */ + vuint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */ + vuint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */ + vuint16_t:2; + vuint16_t WUA:1; /* Wakeup Symbol Received on Channel A */ + vuint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */ + vuint16_t AACA:1; /* Aggregated Additional Communication on Channel A */ + vuint16_t ACEA:1; /* Aggregated Content Error on Channel A */ + vuint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */ + vuint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */ + } B; + } FR_PSR3_16B_tag; + + typedef union { /* Macrotick Counter Register */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t MTCT:14; /* Macrotick Counter */ + } B; + } FR_MTCTR_16B_tag; + + typedef union { /* Cycle Counter Register */ + vuint16_t R; + struct { + vuint16_t:10; + vuint16_t CYCCNT:6; /* Cycle Counter */ + } B; + } FR_CYCTR_16B_tag; + + typedef union { /* Slot Counter Channel A Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */ + } B; + } FR_SLTCTAR_16B_tag; + + typedef union { /* Slot Counter Channel B Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */ + } B; + } FR_SLTCTBR_16B_tag; + + typedef union { /* Rate Correction Value Register */ + vuint16_t R; + struct { + vuint16_t RATECORR:16; /* Rate Correction Value */ + } B; + } FR_RTCORVR_16B_tag; + + typedef union { /* Offset Correction Value Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t OFFSETCORR:10; /* Offset Correction Value */ + } B; + } FR_OFCORVR_16B_tag; + + typedef union { /* Combined Interrupt Flag Register */ + vuint16_t R; + struct { + vuint16_t:8; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MIF:1; /* Module Interrupt Flag */ +#else + vuint16_t MIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t PRIF:1; /* Protocol Interrupt Flag */ +#else + vuint16_t PRIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CHIF:1; /* CHI Interrupt Flag */ +#else + vuint16_t CHIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t WUPIF:1; /* Wakeup Interrupt Flag */ +#else + vuint16_t WUPIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */ +#else + vuint16_t FNEBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */ +#else + vuint16_t FNEAIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */ +#else + vuint16_t RBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */ +#else + vuint16_t TBIFR:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CIFR_16B_tag; + + typedef union { /* System Memory Access Time-Out Register */ + vuint16_t R; + struct { + vuint16_t:8; + vuint16_t TIMEOUT:8; /* Time-Out */ + } B; + } FR_SYMATOR_16B_tag; + + typedef union { /* Sync Frame Counter Register */ + vuint16_t R; + struct { + vuint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */ + vuint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */ + vuint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */ + vuint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */ + } B; + } FR_SFCNTR_16B_tag; + + typedef union { /* Sync Frame Table Offset Register */ + vuint16_t R; + struct { + vuint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */ + vuint16_t:1; + } B; + } FR_SFTOR_16B_tag; + + typedef union { /* Sync Frame Table Configuration, Control, Status Register */ + vuint16_t R; + struct { + vuint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */ + vuint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */ + vuint16_t CYCNUM:6; /* Cycle Number */ + vuint16_t ELKS:1; /* Even Cycle Tables Lock Status */ + vuint16_t OLKS:1; /* Odd Cycle Tables Lock Status */ + vuint16_t EVAL:1; /* Even Cycle Tables Valid */ + vuint16_t OVAL:1; /* Odd Cycle Tables Valid */ + vuint16_t:1; + vuint16_t OPT:1; /* One Pair Trigger */ + vuint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t SIVEN:1; /* Sync Frame ID Table Enable */ +#else + vuint16_t SIDEN:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_SFTCCSR_16B_tag; + + typedef union { /* Sync Frame ID Rejection Filter */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t SYNFRID:10; /* Sync Frame Rejection ID */ + } B; + } FR_SFIDRFR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Value Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t FVAL:10; /* Filter Value */ + } B; + } FR_SFIDAFVR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Mask Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t FMSK:10; /* Filter Mask */ + } B; + } FR_SFIDAFMR_16B_tag; + + typedef union { /* Network Management Vector Register0 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR0_16B_tag; + + typedef union { /* Network Management Vector Register1 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR1_16B_tag; + + typedef union { /* Network Management Vector Register2 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR2_16B_tag; + + typedef union { /* Network Management Vector Register3 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR3_16B_tag; + + typedef union { /* Network Management Vector Register4 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR4_16B_tag; + + typedef union { /* Network Management Vector Register5 */ + vuint16_t R; + struct { + vuint16_t NMVP_15_8:8; /* Network Management Vector Part */ + vuint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR5_16B_tag; + + typedef union { /* Network Management Vector Length Register */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t NMVL:4; /* Network Management Vector Length */ + } B; + } FR_NMVLR_16B_tag; + + typedef union { /* Timer Configuration and Control Register */ + vuint16_t R; + struct { + vuint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t T2_CFG:1; /* Timer T2 Configuration */ +#else + vuint16_t T2CFG:1; /* Timer T2 Configuration */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t T2_REP:1; /* Timer T2 Repetitive Mode */ +#else + vuint16_t T2REP:1; /* Timer T2 Configuration */ +#endif + vuint16_t:1; + vuint16_t T2SP:1; /* Timer T2 Stop */ + vuint16_t T2TR:1; /* Timer T2 Trigger */ + vuint16_t T2ST:1; /* Timer T2 State */ + vuint16_t:3; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t T1_REP:1; /* Timer T1 Repetitive Mode */ +#else + vuint16_t T1REP:1; +#endif + vuint16_t:1; + vuint16_t T1SP:1; /* Timer T1 Stop */ + vuint16_t T1TR:1; /* Timer T1 Trigger */ + vuint16_t T1ST:1; /* Timer T1 State */ + } B; + } FR_TICCR_16B_tag; + + typedef union { /* Timer 1 Cycle Set Register */ + vuint16_t R; + struct { + vuint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */ +#else + vuint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */ +#endif + vuint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */ +#else + vuint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */ +#endif + } B; + } FR_TI1CYSR_16B_tag; + + typedef union { /* Timer 1 Macrotick Offset Register */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */ + } B; + } FR_TI1MTOR_16B_tag; + + typedef union { /* Timer 2 Configuration Register 0 */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */ + vuint16_t:2; + vuint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */ + } B; + } FR_TI2CR0_16B_tag; + + typedef union { /* Timer 2 Configuration Register 1 */ + vuint16_t R; + struct { + vuint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */ + } B; + } FR_TI2CR1_16B_tag; + + typedef union { /* Slot Status Selection Register */ + vuint16_t R; + struct { + vuint16_t WMD:1; /* Write Mode */ + vuint16_t:1; + vuint16_t SEL:2; /* Selector */ + vuint16_t:1; + vuint16_t SLOTNUMBER:11; /* Slot Number */ + } B; + } FR_SSSR_16B_tag; + + typedef union { /* Slot Status Counter Condition Register */ + vuint16_t R; + struct { + vuint16_t WMD:1; /* Write Mode */ + vuint16_t:1; + vuint16_t SEL:2; /* Selector */ + vuint16_t:1; + vuint16_t CNTCFG:2; /* Counter Configuration */ + vuint16_t MCY:1; /* Multi Cycle Selection */ + vuint16_t VFR:1; /* Valid Frame Restriction */ + vuint16_t SYF:1; /* Sync Frame Restriction */ + vuint16_t NUF:1; /* Null Frame Restriction */ + vuint16_t SUF:1; /* Startup Frame Restriction */ + vuint16_t STATUSMASK:4; /* Slot Status Mask */ + } B; + } FR_SSCCR_16B_tag; + + typedef union { /* Slot Status Register0 */ + vuint16_t R; + struct { + vuint16_t VFB:1; /* Valid Frame on Channel B */ + vuint16_t SYB:1; /* Sync Frame Indicator Channel B */ + vuint16_t NFB:1; /* Null Frame Indicator Channel B */ + vuint16_t SUB:1; /* Startup Frame Indicator Channel B */ + vuint16_t SEB:1; /* Syntax Error on Channel B */ + vuint16_t CEB:1; /* Content Error on Channel B */ + vuint16_t BVB:1; /* Boundary Violation on Channel B */ + vuint16_t TCB:1; /* Transmission Conflict on Channel B */ + vuint16_t VFA:1; /* Valid Frame on Channel A */ + vuint16_t SYA:1; /* Sync Frame Indicator Channel A */ + vuint16_t NFA:1; /* Null Frame Indicator Channel A */ + vuint16_t SUA:1; /* Startup Frame Indicator Channel A */ + vuint16_t SEA:1; /* Syntax Error on Channel A */ + vuint16_t CEA:1; /* Content Error on Channel A */ + vuint16_t BVA:1; /* Boundary Violation on Channel A */ + vuint16_t TCA:1; /* Transmission Conflict on Channel A */ + } B; + } FR_SSR_16B_tag; + + + + typedef union { /* Slot Status Counter Register0 */ + vuint16_t R; + struct { + vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR0_16B_tag; + + typedef union { /* Slot Status Counter Register1 */ + vuint16_t R; + struct { + vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR1_16B_tag; + + typedef union { /* Slot Status Counter Register2 */ + vuint16_t R; + struct { + vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR2_16B_tag; + + typedef union { /* Slot Status Counter Register3 */ + vuint16_t R; + struct { + vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR3_16B_tag; + + typedef union { /* MTS A Configuration Register */ + vuint16_t R; + struct { + vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + vuint16_t:1; + vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + vuint16_t:2; + vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSACFR_16B_tag; + + typedef union { /* MTS B Configuration Register */ + vuint16_t R; + struct { + vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + vuint16_t:1; + vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + vuint16_t:2; + vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSBCFR_16B_tag; + + typedef union { /* Receive Shadow Buffer Index Register */ + vuint16_t R; + struct { + vuint16_t WMD:1; /* Write Mode */ + vuint16_t:1; + vuint16_t SEL:2; /* Selector */ + vuint16_t:5; + vuint16_t RSBIDX:7; /* Receive Shadow Buffer Index */ + } B; + } FR_RSBIR_16B_tag; + + typedef union { /* Receive FIFO Watermark and Selection Register */ + vuint16_t R; + struct { + vuint16_t WM:8; /* Watermark Value */ + vuint16_t:7; + vuint16_t SEL:1; /* Select */ + } B; + } FR_RFWMSR_16B_tag; + + typedef union { /* Receive FIFO Start Index Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t SIDX:10; /* Start Index */ + } B; + } FR_RF_RFSIR_16B_tag; + + typedef union { /* Receive FIFO Depth and Size Register */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t FIFO_DEPTH:8; /* FIFO Depth */ +#else + vuint16_t FIFODEPTH:8; /* deprecated name - please avoid */ +#endif + vuint16_t:1; +#ifndef USE_FIELD_ALIASES_FR + vuint16_t ENTRY_SIZE:7; /* Entry Size */ +#else + vuint16_t ENTRYSIZE:7; /* deprecated name - please avoid */ +#endif + } B; + } FR_RFDSR_16B_tag; + + typedef union { /* Receive FIFO A Read Index Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFARIR_16B_tag; + + typedef union { /* Receive FIFO B Read Index Register */ + vuint16_t R; + struct { + vuint16_t:6; + vuint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFBRIR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */ + vuint16_t R; + struct { + vuint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */ + } B; + } FR_RFMIDAFVR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */ + vuint16_t R; + struct { + vuint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */ + } B; + } FR_RFMIDAFMR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */ + } B; + } FR_RFFIDRFVR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */ + } B; + } FR_RFFIDRFMR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Configuration Register */ + vuint16_t R; + struct { + vuint16_t WMD:1; /* Write Mode */ + vuint16_t IBD:1; /* Interval Boundary */ + vuint16_t SEL:2; /* Filter Selector */ + vuint16_t:1; + vuint16_t SID:11; /* Slot ID */ + } B; + } FR_RFRFCFR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Control Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t F3MD:1; /* Range Filter 3 Mode */ + vuint16_t F2MD:1; /* Range Filter 2 Mode */ + vuint16_t F1MD:1; /* Range Filter 1 Mode */ + vuint16_t F0MD:1; /* Range Filter 0 Mode */ + vuint16_t:4; + vuint16_t F3EN:1; /* Range Filter 3 Enable */ + vuint16_t F2EN:1; /* Range Filter 2 Enable */ + vuint16_t F1EN:1; /* Range Filter 1 Enable */ + vuint16_t F0EN:1; /* Range Filter 0 Enable */ + } B; + } FR_RFRFCTR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel A Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */ + } B; + } FR_LDTXSLAR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel B Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */ + } B; + } FR_LDTXSLBR_16B_tag; + + typedef union { /* Protocol Configuration Register 0 */ + vuint16_t R; + struct { + vuint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */ + vuint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */ + } B; + } FR_PCR0_16B_tag; + + typedef union { /* Protocol Configuration Register 1 */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */ + } B; + } FR_PCR1_16B_tag; + + typedef union { /* Protocol Configuration Register 2 */ + vuint16_t R; + struct { + vuint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */ + vuint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */ + } B; + } FR_PCR2_16B_tag; + + typedef union { /* Protocol Configuration Register 3 */ + vuint16_t R; + struct { + vuint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */ +#else + vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */ +#endif + vuint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */ + } B; + } FR_PCR3_16B_tag; + + typedef union { /* Protocol Configuration Register 4 */ + vuint16_t R; + struct { + vuint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */ + vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */ + } B; + } FR_PCR4_16B_tag; + + typedef union { /* Protocol Configuration Register 5 */ + vuint16_t R; + struct { + vuint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */ + vuint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */ + vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */ + } B; + } FR_PCR5_16B_tag; + + typedef union { /* Protocol Configuration Register 6 */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */ +#else + vuint16_t MICRO_INITIAL_OFFSET_A:7; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR6_16B_tag; + + typedef union { /* Protocol Configuration Register 7 */ + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */ + vuint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */ + } B; + } FR_PCR7_16B_tag; + + typedef union { /* Protocol Configuration Register 8 */ + vuint16_t R; + struct { + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */ + vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */ + vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */ + } B; + } FR_PCR8_16B_tag; + + typedef union { /* Protocol Configuration Register 9 */ + vuint16_t R; + struct { + vuint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */ + vuint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */ + vuint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */ + } B; + } FR_PCR9_16B_tag; + + typedef union { /* Protocol Configuration Register 10 */ + vuint16_t R; + struct { + vuint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */ + vuint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */ + vuint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */ + } B; + } FR_PCR10_16B_tag; + + typedef union { /* Protocol Configuration Register 11 */ + vuint16_t R; + struct { + vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */ + vuint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */ + vuint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */ + } B; + } FR_PCR11_16B_tag; + + typedef union { /* Protocol Configuration Register 12 */ + vuint16_t R; + struct { + vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */ + vuint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */ + } B; + } FR_PCR12_16B_tag; + + typedef union { /* Protocol Configuration Register 13 */ + vuint16_t R; + struct { + vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */ + vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */ + } B; + } FR_PCR13_16B_tag; + + typedef union { /* Protocol Configuration Register 14 */ + vuint16_t R; + struct { + vuint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */ +#else + vuint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR14_16B_tag; + + typedef union { /* Protocol Configuration Register 15 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */ +#else + vuint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR15_16B_tag; + + typedef union { /* Protocol Configuration Register 16 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */ +#else + vuint16_t MICRO_INITIAL_OFFSET_B:7; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + vuint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR16_16B_tag; + + typedef union { /* Protocol Configuration Register 17 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + vuint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR17_16B_tag; + + typedef union { /* Protocol Configuration Register 18 */ + vuint16_t R; + struct { + vuint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */ + vuint16_t KEY_SLOT_ID:10; /* pKeySlotId */ + } B; + } FR_PCR18_16B_tag; + + typedef union { /* Protocol Configuration Register 19 */ + vuint16_t R; + struct { + vuint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */ + vuint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */ + } B; + } FR_PCR19_16B_tag; + + typedef union { /* Protocol Configuration Register 20 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MACRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */ +#else + vuint16_t MICRO_INITIAL_OFFSET_B:8; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MACRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */ +#else + vuint16_t MICRO_INITIAL_OFFSET_A:8; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR20_16B_tag; + + typedef union { /* Protocol Configuration Register 21 */ + vuint16_t R; + struct { + vuint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */ + vuint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */ + } B; + } FR_PCR21_16B_tag; + + typedef union { /* Protocol Configuration Register 22 */ + vuint16_t R; + struct { + vuint16_t R:1; /* Reserved bit */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */ +#else + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */ +#else + vuint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR22_16B_tag; + + typedef union { /* Protocol Configuration Register 23 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */ +#else + vuint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR23_16B_tag; + + typedef union { /* Protocol Configuration Register 24 */ + vuint16_t R; + struct { + vuint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */ + vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */ +#else + vuint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR24_16B_tag; + + typedef union { /* Protocol Configuration Register 25 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */ +#else + vuint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR25_16B_tag; + + typedef union { /* Protocol Configuration Register 26 */ + vuint16_t R; + struct { + vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */ + vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */ +#else + vuint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR26_16B_tag; + + typedef union { /* Protocol Configuration Register 27 */ + vuint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + vuint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */ +#else + vuint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR27_16B_tag; + + typedef union { /* Protocol Configuration Register 28 */ + vuint16_t R; + struct { + vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */ + vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */ + } B; + } FR_PCR28_16B_tag; + + typedef union { /* Protocol Configuration Register 29 */ + vuint16_t R; + struct { + vuint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */ + vuint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */ + } B; + } FR_PCR29_16B_tag; + + typedef union { /* Protocol Configuration Register 30 */ + vuint16_t R; + struct { + vuint16_t:12; + vuint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */ + } B; + } FR_PCR30_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address High Register */ + vuint16_t R; + struct { + vuint16_t SMBA_31_16:16; /* System Memory Base Address */ + } B; + } FR_RFSYMBHADR_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address Low Register */ + vuint16_t R; + struct { + vuint16_t:4; + vuint16_t SMBA_15_4:12; /* System Memory Base Address */ + } B; + } FR_RFSYMBLADR_16B_tag; + + typedef union { /* Receive FIFO Periodic Timer Register */ + vuint16_t R; + struct { + vuint16_t:2; + vuint16_t PTD:14; /* Periodic Timer Duration */ + } B; + } FR_RFPTR_16B_tag; + + typedef union { /* Receive FIFO Fill Level and Pop Count Register */ + vuint16_t R; + struct { + vuint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */ + vuint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */ + } B; + } FR_RFFLPCR_16B_tag; + + typedef union { /* ECC Error Interrupt Flag and Enable Register */ + vuint16_t R; + struct { + vuint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */ + vuint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */ + vuint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */ + vuint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */ + vuint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */ + vuint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */ + vuint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */ + vuint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */ + vuint16_t:4; + vuint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */ + vuint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */ + vuint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */ + vuint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */ + } B; + } FR_EEIFER_16B_tag; + + typedef union { /* ECC Error Report and Injection Control Register */ + vuint16_t R; + struct { + vuint16_t BSY:1; /* Register Update Busy */ + vuint16_t:5; + vuint16_t ERS:2; /* Error Report Select */ + vuint16_t:3; + vuint16_t ERM:1; /* Error Report Mode */ + vuint16_t:2; + vuint16_t EIM:1; /* Error Injection Mode */ + vuint16_t EIE:1; /* Error Injection Enable */ + } B; + } FR_EERICR_16B_tag; + + typedef union { /* ECC Error Report Adress Register */ + vuint16_t R; + struct { + vuint16_t MID:1; /* Memory Identifier */ + vuint16_t BANK:3; /* Memory Bank */ + vuint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EERAR_16B_tag; + + typedef union { /* ECC Error Report Data Register */ + vuint16_t R; + struct { + vuint16_t DATA:16; /* Data */ + } B; + } FR_EERDR_16B_tag; + + typedef union { /* ECC Error Report Code Register */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t CODE:5; /* Code */ + } B; + } FR_EERCR_16B_tag; + + typedef union { /* ECC Error Injection Address Register */ + vuint16_t R; + struct { + vuint16_t MID:1; /* Memory Identifier */ + vuint16_t BANK:3; /* Memory Bank */ + vuint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EEIAR_16B_tag; + + typedef union { /* ECC Error Injection Data Register */ + vuint16_t R; + struct { + vuint16_t DATA:16; /* Data */ + } B; + } FR_EEIDR_16B_tag; + + typedef union { /* ECC Error Injection Code Register */ + vuint16_t R; + struct { + vuint16_t:11; + vuint16_t CODE:5; /* Code */ + } B; + } FR_EEICR_16B_tag; + + + /* Register layout for all registers MBCCSR... */ + + typedef union { /* Message Buffer Configuration Control Status Register */ + vuint16_t R; + struct { + vuint16_t:1; + vuint16_t MCM:1; /* Message Buffer Commit Mode */ + vuint16_t MBT:1; /* Message Buffer Type */ + vuint16_t MTD:1; /* Message Buffer Transfer Direction */ + vuint16_t CMT:1; /* Commit for Transmission */ + vuint16_t EDT:1; /* Enable/Disable Trigger */ + vuint16_t LCKT:1; /* Lock/Unlock Trigger */ + vuint16_t MBIE:1; /* Message Buffer Interrupt Enable */ + vuint16_t:3; + vuint16_t DUP:1; /* Data Updated */ + vuint16_t DVAL:1; /* DataValid */ + vuint16_t EDS:1; /* Enable/Disable Status */ + vuint16_t LCKS:1; /* LockStatus */ + vuint16_t MBIF:1; /* Message Buffer Interrupt Flag */ + } B; + } FR_MBCCSR_16B_tag; + + + /* Register layout for all registers MBCCFR... */ + + typedef union { /* Message Buffer Cycle Counter Filter Register */ + vuint16_t R; + struct { + vuint16_t MTM:1; /* Message Buffer Transmission Mode */ +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CHA:1; /* Channel Assignment */ +#else + vuint16_t CHNLA:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + vuint16_t CHB:1; /* Channel Assignment */ +#else + vuint16_t CHNLB:1; /* deprecated name - please avoid */ +#endif + vuint16_t CCFE:1; /* Cycle Counter Filtering Enable */ + vuint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */ + vuint16_t CCFVAL:6; /* Cycle Counter Filtering Value */ + } B; + } FR_MBCCFR_16B_tag; + + + /* Register layout for all registers MBFIDR... */ + + typedef union { /* Message Buffer Frame ID Register */ + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t FID:11; /* Frame ID */ + } B; + } FR_MBFIDR_16B_tag; + + + /* Register layout for all registers MBIDXR... */ + + typedef union { /* Message Buffer Index Register */ + vuint16_t R; + struct { + vuint16_t:9; + vuint16_t MBIDX:7; /* Message Buffer Index */ + } B; + } FR_MBIDXR_16B_tag; + + + /* Register layout for generated register(s) NMVR... */ + + typedef union { /* */ + vuint16_t R; + } FR_NMVR_16B_tag; + + + + + /* Register layout for generated register(s) SSCR... */ + + typedef union { /* */ + vuint16_t R; + } FR_SSCR_16B_tag; + + + typedef struct FR_MB_struct_tag { + + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */ + + } FR_MB_tag; + + + typedef struct FR_struct_tag { /* start of FR_tag */ + /* Module Version Number */ + FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */ + /* Module Configuration Register */ + FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */ + union { + FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD HIGH REG */ + FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */ + + }; + union { + FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD LOW REG */ + FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */ + + }; + /* STROBE SIGNAL CONTROL REGISTER */ + FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */ + int8_t FR_reserved_000A[2]; + /* MESSAGE BUFFER DATA SIZE REGISTER */ + FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */ + /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */ + union { + /* PE DRAM ACCESS REGISTER */ + FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */ + + FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */ + + }; + union { + /* PE DRAM DATA REGISTER */ + FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */ + + FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */ + + }; + /* PROTOCOL OPERATION CONTROL REG */ + FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */ + /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */ + /* CHI ERROR FLAG REGISTER */ + FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */ + /* Message Buffer Interrupt Vector Register */ + FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */ + /* Channel A Status Error Counter Register */ + FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */ + /* Channel B Status Error Counter Register */ + FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */ + /* Protocol Status Register 0 */ + FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */ + /* Protocol Status Register 1 */ + FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */ + /* Protocol Status Register 2 */ + FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */ + /* Protocol Status Register 3 */ + FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */ + /* Macrotick Counter Register */ + FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */ + /* Cycle Counter Register */ + FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */ + /* Slot Counter Channel A Register */ + FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */ + /* Slot Counter Channel B Register */ + FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */ + /* Rate Correction Value Register */ + FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */ + /* Offset Correction Value Register */ + FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */ + union { + FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */ + + /* Combined Interrupt Flag Register */ + FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */ + + }; + /* System Memory Access Time-Out Register */ + FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */ + /* Sync Frame Counter Register */ + FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */ + /* Sync Frame Table Offset Register */ + FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */ + /* Sync Frame Table Configuration, Control, Status Register */ + FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */ + /* Sync Frame ID Rejection Filter */ + FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Value Register */ + FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Mask Register */ + FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */ + union { + FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */ + + struct { + /* Network Management Vector Register0 */ + FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */ + /* Network Management Vector Register1 */ + FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */ + /* Network Management Vector Register2 */ + FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */ + /* Network Management Vector Register3 */ + FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */ + /* Network Management Vector Register4 */ + FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */ + /* Network Management Vector Register5 */ + FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */ + }; + + }; + /* Network Management Vector Length Register */ + FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */ + /* Timer Configuration and Control Register */ + FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */ + /* Timer 1 Cycle Set Register */ + FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */ + union { + /* Timer 1 Macrotick Offset Register */ + FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */ + + FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */ + + }; + /* Timer 2 Configuration Register 0 */ + FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */ + /* Timer 2 Configuration Register 1 */ + FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */ + /* Slot Status Selection Register */ + FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */ + /* Slot Status Counter Condition Register */ + FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */ + union { + FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */ + + struct { + /* Slot Status Register0 */ + FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */ + /* Slot Status Register1 */ + FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */ + /* Slot Status Register2 */ + FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */ + /* Slot Status Register3 */ + FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */ + /* Slot Status Register4 */ + FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */ + /* Slot Status Register5 */ + FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */ + /* Slot Status Register6 */ + FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */ + /* Slot Status Register7 */ + FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */ + }; + + }; + union { + FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */ + + struct { + /* Slot Status Counter Register0 */ + FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */ + /* Slot Status Counter Register1 */ + FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */ + /* Slot Status Counter Register2 */ + FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */ + /* Slot Status Counter Register3 */ + FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */ + }; + + }; + /* MTS A Configuration Register */ + FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */ + /* MTS B Configuration Register */ + FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */ + /* Receive Shadow Buffer Index Register */ + FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */ + union { + /* Receive FIFO Watermark and Selection Register */ + FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */ + + FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */ + + }; + union { + FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */ + + /* Receive FIFO Start Index Register */ + FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */ + + }; + /* Receive FIFO Depth and Size Register */ + FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */ + /* Receive FIFO A Read Index Register */ + FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */ + /* Receive FIFO B Read Index Register */ + FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */ + /* Receive FIFO Message ID Acceptance Filter Value Register */ + FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */ + union { + /* Receive FIFO Message ID Acceptance Filter Mask Register */ + FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */ + + FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */ + + }; + /* Receive FIFO Frame ID Rejection Filter Value Register */ + FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */ + /* Receive FIFO Frame ID Rejection Filter Mask Register */ + FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */ + /* Receive FIFO Range Filter Configuration Register */ + FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */ + /* Receive FIFO Range Filter Control Register */ + FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */ + /* Last Dynamic Transmit Slot Channel A Register */ + FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */ + /* Last Dynamic Transmit Slot Channel B Register */ + FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */ + /* Protocol Configuration Register 0 */ + FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */ + /* Protocol Configuration Register 1 */ + FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */ + /* Protocol Configuration Register 2 */ + FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */ + /* Protocol Configuration Register 3 */ + FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */ + /* Protocol Configuration Register 4 */ + FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */ + /* Protocol Configuration Register 5 */ + FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */ + /* Protocol Configuration Register 6 */ + FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */ + /* Protocol Configuration Register 7 */ + FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */ + /* Protocol Configuration Register 8 */ + FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */ + /* Protocol Configuration Register 9 */ + FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */ + /* Protocol Configuration Register 10 */ + FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */ + /* Protocol Configuration Register 11 */ + FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */ + /* Protocol Configuration Register 12 */ + FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */ + /* Protocol Configuration Register 13 */ + FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */ + /* Protocol Configuration Register 14 */ + FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */ + /* Protocol Configuration Register 15 */ + FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */ + /* Protocol Configuration Register 16 */ + FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */ + /* Protocol Configuration Register 17 */ + FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */ + /* Protocol Configuration Register 18 */ + FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */ + /* Protocol Configuration Register 19 */ + FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */ + /* Protocol Configuration Register 20 */ + FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */ + /* Protocol Configuration Register 21 */ + FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */ + /* Protocol Configuration Register 22 */ + FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */ + /* Protocol Configuration Register 23 */ + FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */ + /* Protocol Configuration Register 24 */ + FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */ + /* Protocol Configuration Register 25 */ + FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */ + /* Protocol Configuration Register 26 */ + FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */ + /* Protocol Configuration Register 27 */ + FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */ + /* Protocol Configuration Register 28 */ + FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */ + /* Protocol Configuration Register 29 */ + FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */ + /* Protocol Configuration Register 30 */ + FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */ + int8_t FR_reserved_00DE[10]; + /* Receive FIFO System Memory Base Address High Register */ + FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */ + /* Receive FIFO System Memory Base Address Low Register */ + FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */ + /* Receive FIFO Periodic Timer Register */ + FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */ + /* Receive FIFO Fill Level and Pop Count Register */ + FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */ + /* ECC Error Interrupt Flag and Enable Register */ + FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */ + /* ECC Error Report and Injection Control Register */ + FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */ + /* ECC Error Report Adress Register */ + FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */ + /* ECC Error Report Data Register */ + FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */ + /* ECC Error Report Code Register */ + FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */ + /* ECC Error Injection Address Register */ + FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */ + /* ECC Error Injection Data Register */ + FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */ + /* ECC Error Injection Code Register */ + FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */ + union { + /* Register set MB */ + FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */ + + struct { + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */ + }; + + }; + } FR_tag; + + +#define FR (*(volatile FR_tag *) 0xFFFE0000UL) + + + + + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* _leopard_H_*/ +/* End of file */ + diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h new file mode 100644 index 000000000..4c6105e15 --- /dev/null +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h @@ -0,0 +1,448 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DSPI_v1/spc5_dspi.h + * @brief SPC5xx DSPI header file. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPC5_DSPI_H_ +#define _SPC5_DSPI_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name MCR register definitions + * @{ + */ +#define SPC5_MCR_MSTR (1U << 31) +#define SPC5_MCR_CONT_SCKE (1U << 30) +#define SPC5_MCR_DCONF_MASK (3U << 28) +#define SPC5_MCR_FRZ (1U << 27) +#define SPC5_MCR_MTFE (1U << 26) +#define SPC5_MCR_PCSSE (1U << 25) +#define SPC5_MCR_ROOE (1U << 24) +#define SPC5_MCR_PCSIS7 (1U << 23) +#define SPC5_MCR_PCSIS6 (1U << 22) +#define SPC5_MCR_PCSIS5 (1U << 21) +#define SPC5_MCR_PCSIS4 (1U << 20) +#define SPC5_MCR_PCSIS3 (1U << 19) +#define SPC5_MCR_PCSIS2 (1U << 18) +#define SPC5_MCR_PCSIS1 (1U << 17) +#define SPC5_MCR_PCSIS0 (1U << 16) +#define SPC5_MCR_DOZE (1U << 15) +#define SPC5_MCR_MDIS (1U << 14) +#define SPC5_MCR_DIS_TXF (1U << 13) +#define SPC5_MCR_DIS_RXF (1U << 12) +#define SPC5_MCR_CLR_TXF (1U << 11) +#define SPC5_MCR_CLR_RXF (1U << 10) +#define SPC5_MCR_SMPL_PT_MASK (3U << 8) +#define SPC5_MCR_SMPL_PT(n) ((n) << 8) +#define SPC5_MCR_FCPCS (1U << 2) +#define SPC5_MCR_PES (1U << 1) +#define SPC5_MCR_HALT (1U << 0) +/** @} */ + +/** + * @name RSER register definitions + * @{ + */ +#define SPC5_RSER_TCF_RE (1U << 31) +#define SPC5_RSER_DSITCF_RE (1U << 29) +#define SPC5_RSER_EOQF_RE (1U << 28) +#define SPC5_RSER_TFUF_RE (1U << 27) +#define SPC5_RSER_SPITCF_RE (1U << 26) +#define SPC5_RSER_TFFF_RE (1U << 25) +#define SPC5_RSER_TFFF_DIRS (1U << 24) +#define SPC5_RSER_DPEF_RE (1U << 22) +#define SPC5_RSER_SPEF_RE (1U << 21) +#define SPC5_RSER_DDIF_RE (1U << 20) +#define SPC5_RSER_RFOF_RE (1U << 19) +#define SPC5_RSER_RFDF_RE (1U << 17) +#define SPC5_RSER_RFDF_DIRS (1U << 16) +/** @} */ + +/** + * @name CTAR registers definitions + * @{ + */ +#define SPC5_CTAR_DBR (1U << 31) +#define SPC5_CTAR_FMSZ_MASK (15U << 27) +#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27) +#define SPC5_CTAR_CPOL (1U << 26) +#define SPC5_CTAR_CPHA (1U << 25) +#define SPC5_CTAR_LSBFE (1U << 24) +#define SPC5_CTAR_PCSSCK_MASK (3U << 22) +#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22) +#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22) +#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22) +#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22) +#define SPC5_CTAR_PASC_MASK (3U << 20) +#define SPC5_CTAR_PASC_PRE1 (0U << 20) +#define SPC5_CTAR_PASC_PRE3 (1U << 20) +#define SPC5_CTAR_PASC_PRE5 (2U << 20) +#define SPC5_CTAR_PASC_PRE7 (3U << 20) +#define SPC5_CTAR_PDT_MASK (3U << 18) +#define SPC5_CTAR_PDT_PRE1 (0U << 18) +#define SPC5_CTAR_PDT_PRE3 (1U << 18) +#define SPC5_CTAR_PDT_PRE5 (2U << 18) +#define SPC5_CTAR_PDT_PRE7 (3U << 18) +#define SPC5_CTAR_PBR_MASK (3U << 16) +#define SPC5_CTAR_PBR_PRE2 (0U << 16) +#define SPC5_CTAR_PBR_PRE3 (1U << 16) +#define SPC5_CTAR_PBR_PRE5 (2U << 16) +#define SPC5_CTAR_PBR_PRE7 (3U << 16) +#define SPC5_CTAR_CSSCK_MASK (15U << 12) +#define SPC5_CTAR_CSSCK_DIV2 (0U << 12) +#define SPC5_CTAR_CSSCK_DIV4 (1U << 12) +#define SPC5_CTAR_CSSCK_DIV6 (2U << 12) +#define SPC5_CTAR_CSSCK_DIV8 (3U << 12) +#define SPC5_CTAR_CSSCK_DIV16 (4U << 12) +#define SPC5_CTAR_CSSCK_DIV32 (5U << 12) +#define SPC5_CTAR_CSSCK_DIV64 (6U << 12) +#define SPC5_CTAR_CSSCK_DIV128 (7U << 12) +#define SPC5_CTAR_CSSCK_DIV256 (8U << 12) +#define SPC5_CTAR_CSSCK_DIV512 (9U << 12) +#define SPC5_CTAR_CSSCK_DIV1024 (10U << 12) +#define SPC5_CTAR_CSSCK_DIV2048 (11U << 12) +#define SPC5_CTAR_CSSCK_DIV4096 (12U << 12) +#define SPC5_CTAR_CSSCK_DIV8192 (13U << 12) +#define SPC5_CTAR_CSSCK_DIV16384 (14U << 12) +#define SPC5_CTAR_CSSCK_DIV32768 (15U << 12) +#define SPC5_CTAR_ASC_MASK (15U << 8) +#define SPC5_CTAR_ASC_DIV2 (0U << 8) +#define SPC5_CTAR_ASC_DIV4 (1U << 8) +#define SPC5_CTAR_ASC_DIV6 (2U << 8) +#define SPC5_CTAR_ASC_DIV8 (3U << 8) +#define SPC5_CTAR_ASC_DIV16 (4U << 8) +#define SPC5_CTAR_ASC_DIV32 (5U << 8) +#define SPC5_CTAR_ASC_DIV64 (6U << 8) +#define SPC5_CTAR_ASC_DIV128 (7U << 8) +#define SPC5_CTAR_ASC_DIV256 (8U << 8) +#define SPC5_CTAR_ASC_DIV512 (9U << 8) +#define SPC5_CTAR_ASC_DIV1024 (10U << 8) +#define SPC5_CTAR_ASC_DIV2048 (11U << 8) +#define SPC5_CTAR_ASC_DIV4096 (12U << 8) +#define SPC5_CTAR_ASC_DIV8192 (13U << 8) +#define SPC5_CTAR_ASC_DIV16384 (14U << 8) +#define SPC5_CTAR_ASC_DIV32768 (15U << 8) +#define SPC5_CTAR_DT_MASK (15U << 4) +#define SPC5_CTAR_DT_DIV2 (0U << 4) +#define SPC5_CTAR_DT_DIV4 (1U << 4) +#define SPC5_CTAR_DT_DIV6 (2U << 4) +#define SPC5_CTAR_DT_DIV8 (3U << 4) +#define SPC5_CTAR_DT_DIV16 (4U << 4) +#define SPC5_CTAR_DT_DIV32 (5U << 4) +#define SPC5_CTAR_DT_DIV64 (6U << 4) +#define SPC5_CTAR_DT_DIV128 (7U << 4) +#define SPC5_CTAR_DT_DIV256 (8U << 4) +#define SPC5_CTAR_DT_DIV512 (9U << 4) +#define SPC5_CTAR_DT_DIV1024 (10U << 4) +#define SPC5_CTAR_DT_DIV2048 (11U << 4) +#define SPC5_CTAR_DT_DIV4096 (12U << 4) +#define SPC5_CTAR_DT_DIV8192 (13U << 4) +#define SPC5_CTAR_DT_DIV16384 (14U << 4) +#define SPC5_CTAR_DT_DIV32768 (15U << 4) +#define SPC5_CTAR_BR_MASK (15U << 0) +#define SPC5_CTAR_BR_DIV2 (0U << 0) +#define SPC5_CTAR_BR_DIV4 (1U << 0) +#define SPC5_CTAR_BR_DIV6 (2U << 0) +#define SPC5_CTAR_BR_DIV8 (3U << 0) +#define SPC5_CTAR_BR_DIV16 (4U << 0) +#define SPC5_CTAR_BR_DIV32 (5U << 0) +#define SPC5_CTAR_BR_DIV64 (6U << 0) +#define SPC5_CTAR_BR_DIV128 (7U << 0) +#define SPC5_CTAR_BR_DIV256 (8U << 0) +#define SPC5_CTAR_BR_DIV512 (9U << 0) +#define SPC5_CTAR_BR_DIV1024 (10U << 0) +#define SPC5_CTAR_BR_DIV2048 (11U << 0) +#define SPC5_CTAR_BR_DIV4096 (12U << 0) +#define SPC5_CTAR_BR_DIV8192 (13U << 0) +#define SPC5_CTAR_BR_DIV16384 (14U << 0) +#define SPC5_CTAR_BR_DIV32768 (15U << 0) +/** @} */ + +/** + * @name PUSHR register definitions + * @{ + */ +#define SPC5_PUSHR_CONT (1U << 31) +#define SPC5_PUSHR_CTAS_MASK (3U << 28) +#define SPC5_PUSHR_CTAS(n) ((n) << 29) +#define SPC5_PUSHR_EOQ (1U << 27) +#define SPC5_PUSHR_CTCNT (1U << 26) +#define SPC5_PUSHR_MASC (1U << 25) +#define SPC5_PUSHR_MCSC (1U << 24) +#define SPC5_PUSHR_PCS_MASK (255U << 16) +#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16) +#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +struct spc5_dspi { + union { + vuint32_t R; + struct { + vuint32_t MSTR :1; + vuint32_t CONT_SCKE :1; + vuint32_t DCONF :2; + vuint32_t FRZ :1; + vuint32_t MTFE :1; + vuint32_t PCSSE :1; + vuint32_t ROOE :1; + vuint32_t PCSIS7 :1; + vuint32_t PCSIS6 :1; + vuint32_t PCSIS5 :1; + vuint32_t PCSIS4 :1; + vuint32_t PCSIS3 :1; + vuint32_t PCSIS2 :1; + vuint32_t PCSIS1 :1; + vuint32_t PCSIS0 :1; + vuint32_t :1; + vuint32_t MDIS :1; + vuint32_t DIS_TXF :1; + vuint32_t DIS_RXF :1; + vuint32_t CLR_TXF :1; + vuint32_t CLR_RXF :1; + vuint32_t SMPL_PT :2; + vuint32_t :7; + vuint32_t HALT :1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT :16; + vuint32_t :16; + } B; + } TCR; + + union { + vuint32_t R; + struct { + vuint32_t DBR :1; + vuint32_t FMSZ :4; + vuint32_t CPOL :1; + vuint32_t CPHA :1; + vuint32_t LSBFE :1; + vuint32_t PCSSCK :2; + vuint32_t PASC :2; + vuint32_t PDT :2; + vuint32_t PBR :2; + vuint32_t CSSCK :4; + vuint32_t ASC :4; + vuint32_t DT :4; + vuint32_t BR :4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union { + vuint32_t R; + struct { + vuint32_t TCF :1; + vuint32_t TXRXS :1; + vuint32_t :1; + vuint32_t EOQF :1; + vuint32_t TFUF :1; + vuint32_t :1; + vuint32_t TFFF :1; + vuint32_t :5; + vuint32_t RFOF :1; + vuint32_t :1; + vuint32_t RFDF :1; + vuint32_t :1; + vuint32_t TXCTR :4; + vuint32_t TXNXTPTR :4; + vuint32_t RXCTR :4; + vuint32_t POPNXTPTR :4; + } B; + } SR; /* Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE :1; + vuint32_t :2; + vuint32_t EOQFRE :1; + vuint32_t TFUFRE :1; + vuint32_t :1; + vuint32_t TFFFRE :1; + vuint32_t TFFFDIRS :1; + vuint32_t :4; + vuint32_t RFOFRE :1; + vuint32_t :1; + vuint32_t RFDFRE :1; + vuint32_t RFDFDIRS :1; + vuint32_t :16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union { + vuint32_t R; + struct { + vuint32_t CONT :1; + vuint32_t CTAS :3; + vuint32_t EOQ :1; + vuint32_t CTCNT :1; + vuint32_t :2; + vuint32_t PCS7 :1; + vuint32_t PCS6 :1; + vuint32_t PCS5 :1; + vuint32_t PCS4 :1; + vuint32_t PCS3 :1; + vuint32_t PCS2 :1; + vuint32_t PCS1 :1; + vuint32_t PCS0 :1; + vuint32_t TXDATA :16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t RXDATA :16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD :16; + vuint32_t TXDATA :16; + } B; + } TXFR[5]; /* Transmit FIFO Registers */ + + vuint32_t DSPI_reserved_txf[11]; + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t RXDATA :16; + } B; + } RXFR[5]; /* Receive FIFO Registers */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE :1; + vuint32_t :1; + vuint32_t MTOCNT :6; + vuint32_t :4; + vuint32_t TXSS :1; + vuint32_t TPOL :1; + vuint32_t TRRE :1; + vuint32_t CID :1; + vuint32_t DCONT :1; + vuint32_t DSICTAS :3; + vuint32_t :6; + vuint32_t DPCS5 :1; + vuint32_t DPCS4 :1; + vuint32_t DPCS3 :1; + vuint32_t DPCS2 :1; + vuint32_t DPCS1 :1; + vuint32_t DPCS0 :1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t SER_DATA :16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t ASER_DATA :16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t COMP_DATA :16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + vuint32_t R; + struct { + vuint32_t :16; + vuint32_t DESER_DATA :16; + } B; + } DDR; /* DSI deserialization Data Register */ + +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name DSPI units references + * @{ + */ +#if SPC5_HAS_DSPI0 || defined(__DOXYGEN__) +#define SPC5_DSPI0 (*(struct spc5_dspi *)0xFFF90000U) +#endif + +#if SPC5_HAS_DSPI1 || defined(__DOXYGEN__) +#define SPC5_DSPI1 (*(struct spc5_dspi *)0xFFF94000U) +#endif + +#if SPC5_HAS_DSPI2 || defined(__DOXYGEN__) +#define SPC5_DSPI2 (*(struct spc5_dspi *)0xFFF98000U) +#endif + +#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__) +#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U) +#endif + +#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__) +#define SPC5_DSPI4 (*(struct spc5_dspi *)0x8FFA0000U) +#endif +/** @} */ + +#endif /* _SPC5_DSPI_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c new file mode 100644 index 000000000..f5db08a75 --- /dev/null +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c @@ -0,0 +1,1218 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/DSPI_v1/spi_lld.c + * @brief SPC5xx SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/* Some forward declarations.*/ +static void spi_serve_rx_irq(edma_channel_t channel, void *p); +static void spi_serve_tx_irq(edma_channel_t channel, void *p); +static void spi_serve_dma_error_irq(edma_channel_t channel, + void *p, + uint32_t esr); + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/* Excluded PUSHR bits.*/ +#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \ + SPC5_PUSHR_EOQ | \ + SPC5_PUSHR_TXDATA_MASK) + +#define DSPI_POPR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 3) +#define DSPI_POPR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 2) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SPID1 driver identifier. + */ +#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** + * @brief SPID2 driver identifier. + */ +#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** + * @brief SPID3 driver identifier. + */ +#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/** + * @brief SPID4 driver identifier. + */ +#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__) +SPIDriver SPID4; +#endif + +/** + * @brief SPID5 driver identifier. + */ +#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__) +SPIDriver SPID5; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for DSPI0 TX1. + */ +static const edma_channel_config_t spi_dspi0_tx1_dma_config = { + SPC5_DSPI0_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI0_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1 +}; + +/** + * @brief DMA configuration for DSPI0 TX2. + */ +static const edma_channel_config_t spi_dspi0_tx2_dma_config = { + SPC5_DSPI0_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1 +}; + +/** + * @brief DMA configuration for DSPI0 RX. + */ +static const edma_channel_config_t spi_dspi0_rx_dma_config = { + SPC5_DSPI0_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI0_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1 +}; +#endif /* SPC5_SPI_USE_DSPI0 */ + +#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for DSPI1 TX1. + */ +static const edma_channel_config_t spi_dspi1_tx1_dma_config = { + SPC5_DSPI1_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI1_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2 +}; + +/** + * @brief DMA configuration for DSPI1 TX2. + */ +static const edma_channel_config_t spi_dspi1_tx2_dma_config = { + SPC5_DSPI1_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2 +}; + +/** + * @brief DMA configuration for DSPI1 RX. + */ +static const edma_channel_config_t spi_dspi1_rx_dma_config = { + SPC5_DSPI1_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI1_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2 +}; +#endif /* SPC5_SPI_USE_DSPI1 */ + +#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for DSPI2 TX1. + */ +static const edma_channel_config_t spi_dspi2_tx1_dma_config = { + SPC5_DSPI2_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI2_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3 +}; + +/** + * @brief DMA configuration for DSPI2 TX2. + */ +static const edma_channel_config_t spi_dspi2_tx2_dma_config = { + SPC5_DSPI2_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3 +}; + +/** + * @brief DMA configuration for DSPI2 RX. + */ +static const edma_channel_config_t spi_dspi2_rx_dma_config = { + SPC5_DSPI2_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI2_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3 +}; +#endif /* SPC5_SPI_USE_DSPI2 */ + +#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for DSPI3 TX1. + */ +static const edma_channel_config_t spi_dspi3_tx1_dma_config = { + SPC5_DSPI3_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI3_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4 +}; + +/** + * @brief DMA configuration for DSPI3 TX2. + */ +static const edma_channel_config_t spi_dspi3_tx2_dma_config = { + SPC5_DSPI3_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4 +}; + +/** + * @brief DMA configuration for DSPI3 RX. + */ +static const edma_channel_config_t spi_dspi3_rx_dma_config = { + SPC5_DSPI3_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI3_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4 +}; +#endif /* SPC5_SPI_USE_DSPI3 */ + +#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for DSPI4 TX1. + */ +static const edma_channel_config_t spi_dspi4_tx1_dma_config = { + SPC5_DSPI4_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI4_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5 +}; + +/** + * @brief DMA configuration for DSPI4 TX2. + */ +static const edma_channel_config_t spi_dspi4_tx2_dma_config = { + SPC5_DSPI4_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5 +}; + +/** + * @brief DMA configuration for DSPI4 RX. + */ +static const edma_channel_config_t spi_dspi4_rx_dma_config = { + SPC5_DSPI4_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI4_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5 +}; +#endif /* SPC5_SPI_USE_DSPI4 */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Starts reception using DMA ignoring the received data. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * + * @notapi + */ +static void spi_start_dma_rx_ignore(SPIDriver *spip, size_t n) { + static uint32_t datasink; + + edmaChannelSetup(spip->rx_channel, /* channel. */ + DSPI_POPR8_ADDRESS(spip), /* src. */ + &datasink, /* dst. */ + 0, /* soff, do not advance. */ + 0, /* doff, do not advance. */ + 0, /* ssize, 16 bits transfers.*/ + 0, /* dsize, 16 bits transfers.*/ + 1, /* nbytes, always one. */ + n, /* iter. */ + 0, /* slast. */ + 0, /* dlast. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/ + + edmaChannelStart(spip->rx_channel); +} + +/** + * @brief Starts reception using DMA for frames up to 8 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +static void spi_start_dma_rx8(SPIDriver *spip, + size_t n, + uint8_t *rxbuf) { + + edmaChannelSetup(spip->rx_channel, /* channel. */ + DSPI_POPR8_ADDRESS(spip), /* src. */ + rxbuf, /* dst. */ + 0, /* soff, do not advance. */ + 1, /* doff, advance by one. */ + 0, /* ssize, 8 bits transfers. */ + 0, /* dsize, 8 bits transfers. */ + 1, /* nbytes, always one. */ + n, /* iter. */ + 0, /* slast. */ + 0, /* dlast. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/ + + edmaChannelStart(spip->rx_channel); +} + +/** + * @brief Starts reception using DMA for frames up to 16 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +static void spi_start_dma_rx16(SPIDriver *spip, + size_t n, + uint16_t *rxbuf) { + + edmaChannelSetup(spip->rx_channel, /* channel. */ + DSPI_POPR16_ADDRESS(spip), /* src. */ + rxbuf, /* dst. */ + 0, /* soff, do not advance. */ + 2, /* doff, advance by two. */ + 1, /* ssize, 16 bits transfers.*/ + 1, /* dsize, 16 bits transfers.*/ + 2, /* nbytes, always two. */ + n, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */ + + edmaChannelStart(spip->rx_channel); +} + +/** + * @brief Starts transmission using DMA for frames up to 8 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * + * @notapi + */ +static void spi_start_dma_tx_ignore(SPIDriver *spip, size_t n) { + + /* Preparing the TX intermediate buffer with the fixed part.*/ + spip->tx_intbuf = spip->config->pushr | (uint32_t)0xFFFF; + + /* The first frame is pushed by the CPU, then the DMA is activated to + send the following frames. This should reduce latency on the operation + start.*/ + spip->dspi->PUSHR.R = spip->tx_last = spip->tx_intbuf; + + /* Setting up TX1 DMA TCD parameters for 32 bits transfers.*/ + edmaChannelSetup(spip->tx1_channel, /* channel. */ + &spip->tx_intbuf, /* src. */ + &spip->dspi->PUSHR.R, /* dst. */ + 0, /* soff, do not advance. */ + 0, /* doff, do not advance. */ + 2, /* ssize, 32 bits transfers.*/ + 2, /* dsize, 32 bits transfers.*/ + 4, /* nbytes, always four. */ + n - 2, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */ + + /* Starting TX1 DMA channel.*/ + edmaChannelStart(spip->tx1_channel); +} + +/** + * @brief Starts transmission using DMA for frames up to 8 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +static void spi_start_dma_tx8(SPIDriver *spip, + size_t n, + const uint8_t *txbuf) { + + /* Preparing the TX intermediate buffer with the fixed part.*/ + spip->tx_intbuf = spip->config->pushr; + + /* The first frame is pushed by the CPU, then the DMA is activated to + send the following frames. This should reduce latency on the operation + start.*/ + spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf; + + /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/ + edmaChannelSetupLinked( + spip->tx1_channel, /* channel. */ + spip->tx2_channel, /* linkch. */ + txbuf + 1, /* src. */ + ((const uint8_t *)&spip->tx_intbuf) + 3, /* dst. */ + 1, /* soff, advance by 1. */ + 0, /* doff, do not advance. */ + 0, /* ssize, 8 bits transfers. */ + 0, /* dsize, 8 bits transfers. */ + 1, /* nbytes, always one. */ + n - 2, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ); /* mode. */ + + /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/ + edmaChannelSetup(spip->tx2_channel, /* channel. */ + &spip->tx_intbuf, /* src. */ + &spip->dspi->PUSHR.R, /* dst. */ + 0, /* soff, do not advance. */ + 0, /* doff, do not advance. */ + 2, /* ssize, 32 bits transfers.*/ + 2, /* dsize, 32 bits transfers.*/ + 4, /* nbytes, always four. */ + n - 2, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */ + + /* The last frame will be pushed by the TX DMA operation completion + callback.*/ + spip->tx_last = txbuf[n - 1]; + + /* Starting TX DMA channels.*/ + edmaChannelStart(spip->tx2_channel); + edmaChannelStart(spip->tx1_channel); +} + +/** + * @brief Starts transmission using DMA for frames up to 16 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +static void spi_start_dma_tx16(SPIDriver *spip, + size_t n, + const uint16_t *txbuf) { + + /* Preparing the TX intermediate buffer with the fixed part.*/ + spip->tx_intbuf = spip->config->pushr; + + /* The first frame is pushed by the CPU, then the DMA is activated to + send the following frames. This should reduce latency on the operation + start.*/ + spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf; + + /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/ + edmaChannelSetupLinked( + spip->tx1_channel, /* channel. */ + spip->tx2_channel, /* linkch. */ + txbuf + 1, /* src. */ + ((const uint8_t *)&spip->tx_intbuf) + 2, /* dst. */ + 1, /* soff, advance by 1. */ + 0, /* doff, do not advance. */ + 1, /* ssize, 16 bits transfers.*/ + 1, /* dsize, 16 bits transfers.*/ + 1, /* nbytes, always one. */ + n - 2, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ); /* mode. */ + + /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/ + edmaChannelSetup(spip->tx2_channel, /* channel. */ + &spip->tx_intbuf, /* src. */ + &spip->dspi->PUSHR.R, /* dst. */ + 0, /* soff, do not advance. */ + 0, /* doff, do not advance. */ + 2, /* ssize, 32 bits transfers.*/ + 2, /* dsize, 32 bits transfers.*/ + 4, /* nbytes, always four. */ + n - 2, /* iter. */ + 0, /* slast, no source adjust. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */ + + /* The last frame will be pushed by the TX DMA operation completion + callback.*/ + spip->tx_last = txbuf[n - 1]; + + /* Starting TX DMA channels.*/ + edmaChannelStart(spip->tx2_channel); + edmaChannelStart(spip->tx1_channel); +} + +/** + * @brief Starts idle bits using FIFO pre-filling. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * + * @notapi + */ +static void spi_tx_prefill_ignore(SPIDriver *spip, size_t n) { + uint32_t cmd = spip->config->pushr; + + do { + if (--n == 0) { + spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)0xFFFF) & + ~SPC5_PUSHR_CONT; + break; + } + spip->dspi->PUSHR.R = cmd | (uint32_t)0xFFFF; + } while (TRUE); +} + +/** + * @brief Starts transmission using FIFO pre-filling for frames up to 8 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +static void spi_tx_prefill8(SPIDriver *spip, + size_t n, + const uint8_t *txbuf) { + uint32_t cmd = spip->config->pushr; + + do { + if (--n == 0) { + spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf) & + ~SPC5_PUSHR_CONT; + break; + } + spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf; + txbuf++; + } while (TRUE); +} + +/** + * @brief Starts transmission using FIFO pre-filling for frames up to 16 bits. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +static void spi_tx_prefill16(SPIDriver *spip, + size_t n, + const uint16_t *txbuf) { + uint32_t cmd = spip->config->pushr; + + do { + if (--n == 0) { + spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf; + break; + } + spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf; + txbuf++; + } while (TRUE); +} + +/** + * @brief Shared RX DMA events service routine. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * + * @notapi + */ +static void spi_serve_rx_irq(edma_channel_t channel, void *p) { + SPIDriver *spip = (SPIDriver *)p; + + /* Clearing RX channel state.*/ + edmaChannelStop(channel); + + /* Stops the DSPI and clears the queues.*/ + spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF; + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared TX1/TX2 DMA events service routine. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * + * @notapi + */ +static void spi_serve_tx_irq(edma_channel_t channel, void *p) { + SPIDriver *spip = (SPIDriver *)p; + + (void)channel; + + /* Clearing TX channels state.*/ + edmaChannelStop(spip->tx1_channel); + edmaChannelStop(spip->tx2_channel); + + /* If the TX FIFO is full then the push of the last frame is delagated to + an interrupt handler else it is performed immediately. Both conditions + can be true depending on the SPI speed and ISR latency.*/ + if (spip->dspi->SR.B.TFFF) { + spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + } + else { + spip->dspi->RSER.B.TFFFDIRS = 0; + } +} + +/** + * @brief Shared ISR for DMA error events. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * @param[in] esr content of the ESR register + * + * @notapi + */ +static void spi_serve_dma_error_irq(edma_channel_t channel, + void *p, + uint32_t esr) { + SPIDriver *spip = (SPIDriver *)p; + + (void)channel; + (void)esr; + + /* Stops the DSPI and clears the queues.*/ + spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF; + + edmaChannelStop(spip->tx1_channel); + edmaChannelStop(spip->tx2_channel); + edmaChannelStop(spip->rx_channel); + + SPC5_SPI_DMA_ERROR_HOOK(spip); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__) +#if !defined(SPC5_DSPI0_TFFF_HANDLER) +#error "SPC5_DSPI0_TFFF_HANDLER not defined" +#endif +/** + * @brief DSPI0 TFFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + + /* Interrupt served and back to DMA mode.*/ + SPC5_DSPI0.RSER.B.TFFFDIRS = 1; + SPC5_DSPI0.SR.B.TFFF = 1; + + /* Pushing last frame.*/ + SPC5_DSPI0.PUSHR.R = (SPID1.config->pushr | SPID1.tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_SPI_USE_DSPI0 */ + +#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__) +#if !defined(SPC5_DSPI1_TFFF_HANDLER) +#error "SPC5_DSPI1_TFFF_HANDLER not defined" +#endif +/** + * @brief DSPI1 TFFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + + /* Interrupt served and back to DMA mode.*/ + SPC5_DSPI1.RSER.B.TFFFDIRS = 1; + SPC5_DSPI1.SR.B.TFFF = 1; + + /* Pushing last frame.*/ + SPC5_DSPI1.PUSHR.R = (SPID2.config->pushr | SPID2.tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_SPI_USE_DSPI1 */ + +#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__) +#if !defined(SPC5_DSPI2_TFFF_HANDLER) +#error "SPC5_DSPI2_TFFF_HANDLER not defined" +#endif +/** + * @brief DSPI2 TFFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + + /* Interrupt served and back to DMA mode.*/ + SPC5_DSPI2.RSER.B.TFFFDIRS = 1; + SPC5_DSPI2.SR.B.TFFF = 1; + + /* Pushing last frame.*/ + SPC5_DSPI2.PUSHR.R = (SPID3.config->pushr | SPID3.tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_SPI_USE_DSPI2 */ + +#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__) +#if !defined(SPC5_DSPI3_TFFF_HANDLER) +#error "SPC5_DSPI3_TFFF_HANDLER not defined" +#endif +/** + * @brief DSPI3 TFFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + + /* Interrupt served and back to DMA mode.*/ + SPC5_DSPI3.RSER.B.TFFFDIRS = 1; + SPC5_DSPI3.SR.B.TFFF = 1; + + /* Pushing last frame.*/ + SPC5_DSPI3.PUSHR.R = (SPID4.config->pushr | SPID4.tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_SPI_USE_DSPI3 */ + +#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__) +#if !defined(SPC5_DSPI4_TFFF_HANDLER) +#error "SPC5_DSPI4_TFFF_HANDLER not defined" +#endif +/** + * @brief DSPI4 TFFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_DSPI4_TFFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + + /* Interrupt served and back to DMA mode.*/ + SPC5_DSPI4.RSER.B.TFFFDIRS = 1; + SPC5_DSPI4.SR.B.TFFF = 1; + + /* Pushing last frame.*/ + SPC5_DSPI4.PUSHR.R = (SPID5.config->pushr | SPID5.tx_last | SPC5_PUSHR_EOQ) & + ~SPC5_PUSHR_CONT; + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_SPI_USE_DSPI4 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if SPC5_SPI_USE_DSPI0 + /* Driver initialization.*/ + spiObjectInit(&SPID1); + SPC5_DSPI0_ENABLE_CLOCK(); + SPID1.dspi = &SPC5_DSPI0; + SPID1.tx1_channel = EDMA_ERROR; + SPID1.tx2_channel = EDMA_ERROR; + SPID1.rx_channel = EDMA_ERROR; + SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS | + SPC5_SPI_DSPI0_MCR; + INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO; +#endif /* SPC5_SPI_USE_DSPI0 */ + +#if SPC5_SPI_USE_DSPI1 + /* Driver initialization.*/ + SPC5_DSPI1_ENABLE_CLOCK(); + spiObjectInit(&SPID2); + SPID2.dspi = &SPC5_DSPI1; + SPID2.tx1_channel = EDMA_ERROR; + SPID2.tx2_channel = EDMA_ERROR; + SPID2.rx_channel = EDMA_ERROR; + SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS | + SPC5_SPI_DSPI1_MCR; + INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO; +#endif /* SPC5_SPI_USE_DSPI1 */ + +#if SPC5_SPI_USE_DSPI2 + /* Driver initialization.*/ + spiObjectInit(&SPID3); + SPC5_DSPI2_ENABLE_CLOCK(); + SPID3.dspi = &SPC5_DSPI2; + SPID3.tx1_channel = EDMA_ERROR; + SPID3.tx2_channel = EDMA_ERROR; + SPID3.rx_channel = EDMA_ERROR; + SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS | + SPC5_SPI_DSPI2_MCR; + INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO; +#endif /* SPC5_SPI_USE_DSPI2 */ + +#if SPC5_SPI_USE_DSPI3 + /* Driver initialization.*/ + spiObjectInit(&SPID4); + SPC5_DSPI3_ENABLE_CLOCK(); + SPID4.dspi = &SPC5_DSPI3; + SPID4.tx1_channel = EDMA_ERROR; + SPID4.tx2_channel = EDMA_ERROR; + SPID4.rx_channel = EDMA_ERROR; + SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS | + SPC5_SPI_DSPI3_MCR; + INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO; +#endif /* SPC5_SPI_USE_DSPI3 */ + +#if SPC5_SPI_USE_DSPI4 + /* Driver initialization.*/ + spiObjectInit(&SPID5); + SPC5_DSPI4_ENABLE_CLOCK(); + SPID5.dspi = &SPC5_DSPI4; + SPID5.tx1_channel = EDMA_ERROR; + SPID5.tx2_channel = EDMA_ERROR; + SPID5.rx_channel = EDMA_ERROR; + SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS | + SPC5_SPI_DSPI4_MCR; + INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO; +#endif /* SPC5_SPI_USE_DSPI4 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0, + "spi_lld_start(), #1", "invalid PUSHR bits specified"); + + if (spip->state == SPI_STOP) { + /* Enables the peripheral.*/ + +#if SPC5_SPI_USE_DSPI0 + if (&SPID1 == spip) { + spip->tx1_channel = edmaChannelAllocate(&spi_dspi0_tx1_dma_config); + spip->tx2_channel = edmaChannelAllocate(&spi_dspi0_tx2_dma_config); + spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config); + } +#endif /* SPC5_SPI_USE_DSPI0 */ + +#if SPC5_SPI_USE_DSPI1 + if (&SPID2 == spip) { + spip->tx1_channel = edmaChannelAllocate(&spi_dspi1_tx1_dma_config); + spip->tx2_channel = edmaChannelAllocate(&spi_dspi1_tx2_dma_config); + spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config); + } +#endif /* SPC5_SPI_USE_DSPI1 */ + +#if SPC5_SPI_USE_DSPI2 + if (&SPID3 == spip) { + spip->tx1_channel = edmaChannelAllocate(&spi_dspi2_tx1_dma_config); + spip->tx2_channel = edmaChannelAllocate(&spi_dspi2_tx2_dma_config); + spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config); + } +#endif /* SPC5_SPI_USE_DSPI2 */ + +#if SPC5_SPI_USE_DSPI3 + if (&SPID4 == spip) { + spip->tx1_channel = edmaChannelAllocate(&spi_dspi3_tx1_dma_config); + spip->tx2_channel = edmaChannelAllocate(&spi_dspi3_tx2_dma_config); + spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config); + } +#endif /* SPC5_SPI_USE_DSPI3 */ + +#if SPC5_SPI_USE_DSPI4 + if (&SPID5 == spip) { + spip->tx1_channel = edmaChannelAllocate(&spi_dspi4_tx1_dma_config); + spip->tx2_channel = edmaChannelAllocate(&spi_dspi4_tx2_dma_config); + spip->rx_channel = edmaChannelAllocate(&spi_dspi4_rx_dma_config); + } +#endif /* SPC5_SPI_USE_DSPI5 */ + + chDbgAssert((spip->tx1_channel != EDMA_ERROR) && + (spip->tx2_channel != EDMA_ERROR) && + (spip->rx_channel != EDMA_ERROR), + "spi_lld_start(), #2", "channel cannot be allocated"); + } + + /* Configures the peripheral.*/ + spip->dspi->MCR.B.MDIS = 0; + spip->dspi->CTAR[0].R = spip->config->ctar0; + spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS | + SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS; + spip->dspi->SR.R = spip->dspi->SR.R; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state == SPI_READY) { + /* Releases the allocated EDMA channels.*/ + edmaChannelRelease(spip->tx1_channel); + edmaChannelRelease(spip->tx2_channel); + edmaChannelRelease(spip->rx_channel); + + /* Resets the peripheral.*/ + spip->dspi->CTAR[0].R = 0; + spip->dspi->RSER.R = 0; + spip->dspi->SR.R = spip->dspi->SR.R; + spip->dspi->MCR.R |= SPC5_MCR_HALT | + SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF; + spip->dspi->MCR.B.MDIS = 1; + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + /* Starting transfer.*/ + spip->dspi->SR.R = spip->dspi->SR.R; + spip->dspi->MCR.B.HALT = 0; + + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx_ignore(spip, n); + + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill_ignore(spip, n); + } + else { + spi_start_dma_tx_ignore(spip, n); + } +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + /* Starting transfer.*/ + spip->dspi->SR.R = spip->dspi->SR.R; + spip->dspi->MCR.B.HALT = 0; + + /* DMAs require a different setup depending on the frame size.*/ + if (spip->dspi->CTAR[0].B.FMSZ < 8) { + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx8(spip, n, rxbuf); + + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill8(spip, n, txbuf); + } + else { + spi_start_dma_tx8(spip, n, txbuf); + } + } + else { + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx16(spip, n, rxbuf); + + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill16(spip, n, txbuf); + } + else { + spi_start_dma_tx16(spip, n, txbuf); + } + } +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + /* Starting transfer.*/ + spip->dspi->SR.R = spip->dspi->SR.R; + spip->dspi->MCR.B.HALT = 0; + + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx_ignore(spip, n); + + /* DMAs require a different setup depending on the frame size.*/ + if (spip->dspi->CTAR[0].B.FMSZ < 8) { + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill8(spip, n, txbuf); + } + else { + spi_start_dma_tx8(spip, n, txbuf); + } + } + else { + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill16(spip, n, txbuf); + } + else { + spi_start_dma_tx16(spip, n, txbuf); + } + } +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + /* Starting transfer.*/ + spip->dspi->SR.R = spip->dspi->SR.R; + spip->dspi->MCR.B.HALT = 0; + + /* DMAs require a different setup depending on the frame size.*/ + if (spip->dspi->CTAR[0].B.FMSZ < 8) { + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx8(spip, n, rxbuf); + } + else { + /* Setting up the RX DMA channel.*/ + spi_start_dma_rx16(spip, n, rxbuf); + } + + if (n <= SPC5_DSPI_FIFO_DEPTH) { + /* If the total transfer size is smaller than the TX FIFO size then + the whole transmitted data is pushed here and the TX DMA is not + activated.*/ + spi_tx_prefill_ignore(spip, n); + } + else { + spi_start_dma_tx_ignore(spip, n); + } +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + uint32_t popr; + + spip->dspi->MCR.B.HALT = 0; + spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr | + (uint32_t)frame) & ~SPC5_PUSHR_CONT; + while (!spip->dspi->SR.B.RFDF) + ; + popr = spip->dspi->POPR.R; + spip->dspi->MCR.B.HALT = 1; + return (uint16_t)popr; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h new file mode 100644 index 000000000..b79e13a8e --- /dev/null +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h @@ -0,0 +1,532 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/DSPI_v1/spi_lld.h + * @brief SPC5xx SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +#include "spc5_dspi.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPID1 driver enable switch. + * @details If set to @p TRUE the support for DSPI0 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI0) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI0 FALSE +#endif + +/** + * @brief SPID2 driver enable switch. + * @details If set to @p TRUE the support for DSPI1 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI1 FALSE +#endif + +/** + * @brief SPID3 driver enable switch. + * @details If set to @p TRUE the support for DSPI2 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI2) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI2 FALSE +#endif + +/** + * @brief SPID4 driver enable switch. + * @details If set to @p TRUE the support for DSPI3 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI3) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI3 FALSE +#endif + +/** + * @brief SPID5 driver enable switch. + * @details If set to @p TRUE the support for DSPI4 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI4 FALSE +#endif + +/** + * @brief DSPI0 MCR PCS defaults. + */ +#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#endif + +/** + * @brief DSPI1 MCR PCS defaults. + */ +#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#endif + +/** + * @brief DSP2 MCR PCS defaults. + */ +#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#endif + +/** + * @brief DSPI3 MCR PCS defaults. + */ +#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#endif + +/** + * @brief DSPI4 MCR PCS defaults. + */ +#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#endif + +/** + * @brief DSPI0 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI0_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI1 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI1_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI2 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI2_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI3 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI3_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI4 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#endif + +/** + * @brief SPI DMA error hook. + */ +#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief DSPI0 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI1 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI2 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI3 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI4 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#endif + +/** + * @brief DSPI0 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI0_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief DSPI0 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI0_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief DSPI1 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI1_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief DSPI1 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI1_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief DSPI2 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI2_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief DSPI2 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI2_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief DSPI3 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI3_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief DSPI3 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI3_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief DSPI4 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI4_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief DSPI4 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SPI_DSPI4_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPC5_SPI_USE_DSPI0 && !SPC5_HAS_DSPI0 +#error "DSPI0 not present in the selected device" +#endif + +#if SPC5_SPI_USE_DSPI1 && !SPC5_HAS_DSPI1 +#error "DSPI1 not present in the selected device" +#endif + +#if SPC5_SPI_USE_DSPI2 && !SPC5_HAS_DSPI2 +#error "DSPI2 not present in the selected device" +#endif + +#if SPC5_SPI_USE_DSPI3 && !SPC5_HAS_DSPI3 +#error "DSPI3 not present in the selected device" +#endif + +#if SPC5_SPI_USE_DSPI4 && !SPC5_HAS_DSPI4 +#error "DSPI4 not present in the selected device" +#endif + +#if !SPC5_SPI_USE_DSPI0 && !SPC5_SPI_USE_DSPI1 && \ + !SPC5_SPI_USE_DSPI2 && !SPC5_SPI_USE_DSPI3 && \ + !SPC5_SPI_USE_DSPI4 +#error "SPI driver activated but no DSPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Operation complete callback. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief DSPI CTAR0 value for this session. + */ + uint32_t ctar0; + /** + * @brief DSPI PUSHR command for this session. + * @note Only CTAR0 can be referenced, the other CTARs are not + * initialized. The data part must be left to zero. + */ + uint32_t pushr; +} SPIConfig; + +/** + * @brief Structure representing an SPI driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the DSPI registers block. + */ + struct spc5_dspi *dspi; + /** + * @brief EDMA channel used for data memory to memory copy. + */ + edma_channel_t tx1_channel; + /** + * @brief EDMA channel used for transmit. + */ + edma_channel_t tx2_channel; + /** + * @brief EDMA channel used for receive. + */ + edma_channel_t rx_channel; + /** + * @brief Last frame of a transmission sequence. + */ + uint32_t tx_last; + /** + * @brief TX intermediate buffer. + * @note This field is written by the TX1 DMA channel and read by the + * TX2 DMA channel. + */ + uint32_t tx_intbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_SPI_USE_DSPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if SPC5_SPI_USE_DSPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if SPC5_SPI_USE_DSPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#if SPC5_SPI_USE_DSPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID4; +#endif + +#if SPC5_SPI_USE_DSPI4 && !defined(__DOXYGEN__) +extern SPIDriver SPID5; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c new file mode 100644 index 000000000..7aad4027f --- /dev/null +++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c @@ -0,0 +1,1402 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/spc5_edma.c + * @brief EDMA helper driver code. + * + * @addtogroup SPC5xx_EDMA + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if SPC5_HAS_EDMA + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES}; +#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__) +static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES}; +#endif +#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__) +static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES}; +static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES}; +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Configurations for the various EDMA channels. + */ +static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EDMA (channels 0..31) error interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector10) { + edma_channel_t channel; + uint32_t erl, esr = SPC5_EDMA.ESR.R; + + CH_IRQ_PROLOGUE(); + + /* Scanning for errors.*/ + channel = 0; + while (((erl = SPC5_EDMA.ERL.R) != 0) && + (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) { + if ((erl & (1U << channel)) != 0) { + /* Error flag cleared.*/ + SPC5_EDMA.CER.R = channel; + + /* If the channel is not associated then the error is simply discarded + else the error callback is invoked.*/ + if ((channels[channel] != NULL) && + (channels[channel]->dma_error_func != NULL)) + channels[channel]->dma_error_func(channel, + channels[channel]->dma_param, + esr); + channel++; + } + } + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 0 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector11) { + + CH_IRQ_PROLOGUE(); + + if (channels[0] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 0; + channels[0]->dma_func(0, channels[0]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 1 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector12) { + + CH_IRQ_PROLOGUE(); + + if (channels[1] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 1; + channels[1]->dma_func(1, channels[1]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 2 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector13) { + + CH_IRQ_PROLOGUE(); + + if (channels[2] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 2; + channels[2]->dma_func(2, channels[2]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 3 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector14) { + + CH_IRQ_PROLOGUE(); + + if (channels[3] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 3; + channels[3]->dma_func(3, channels[3]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 4 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector15) { + + CH_IRQ_PROLOGUE(); + + if (channels[4] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 4; + channels[4]->dma_func(4, channels[4]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 5 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector16) { + + CH_IRQ_PROLOGUE(); + + if (channels[5] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 5; + channels[5]->dma_func(5, channels[5]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 6 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector17) { + + CH_IRQ_PROLOGUE(); + + if (channels[6] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 6; + channels[6]->dma_func(6, channels[6]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 7 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector18) { + + CH_IRQ_PROLOGUE(); + + if (channels[7] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 7; + channels[7]->dma_func(7, channels[7]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 8 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector19) { + + CH_IRQ_PROLOGUE(); + + if (channels[8] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 8; + channels[8]->dma_func(8, channels[8]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 9 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector20) { + + CH_IRQ_PROLOGUE(); + + if (channels[9] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 9; + channels[9]->dma_func(9, channels[9]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 10 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector21) { + + CH_IRQ_PROLOGUE(); + + if (channels[10] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 10; + channels[10]->dma_func(10, channels[10]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 11 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector22) { + + CH_IRQ_PROLOGUE(); + + if (channels[11] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 11; + channels[11]->dma_func(11, channels[11]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 12 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector23) { + + CH_IRQ_PROLOGUE(); + + if (channels[12] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 12; + channels[12]->dma_func(12, channels[12]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 13 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector24) { + + CH_IRQ_PROLOGUE(); + + if (channels[13] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 13; + channels[13]->dma_func(13, channels[13]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 14 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector25) { + + CH_IRQ_PROLOGUE(); + + if (channels[14] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 14; + channels[14]->dma_func(14, channels[14]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 15 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector26) { + + CH_IRQ_PROLOGUE(); + + if (channels[15] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 15; + channels[15]->dma_func(15, channels[15]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__) +/** + * @brief EDMA channel 16 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector27) { + + CH_IRQ_PROLOGUE(); + + if (channels[16] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 16; + channels[16]->dma_func(16, channels[16]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 17 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector28) { + + CH_IRQ_PROLOGUE(); + + if (channels[17] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 17; + channels[17]->dma_func(17, channels[17]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 18 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector29) { + + CH_IRQ_PROLOGUE(); + + if (channels[18] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 18; + channels[18]->dma_func(18, channels[18]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 19 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector30) { + + CH_IRQ_PROLOGUE(); + + if (channels[19] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 19; + channels[19]->dma_func(19, channels[19]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 20 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector31) { + + CH_IRQ_PROLOGUE(); + + if (channels[20] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 20; + channels[20]->dma_func(20, channels[20]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 21 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector32) { + + CH_IRQ_PROLOGUE(); + + if (channels[21] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 21; + channels[21]->dma_func(21, channels[21]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 22 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector33) { + + CH_IRQ_PROLOGUE(); + + if (channels[22] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 22; + channels[22]->dma_func(22, channels[22]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 23 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector34) { + + CH_IRQ_PROLOGUE(); + + if (channels[23] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 23; + channels[23]->dma_func(23, channels[23]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 24 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector35) { + + CH_IRQ_PROLOGUE(); + + if (channels[24] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 24; + channels[24]->dma_func(24, channels[24]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 25 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector36) { + + CH_IRQ_PROLOGUE(); + + if (channels[25] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 25; + channels[25]->dma_func(25, channels[25]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 26 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector37) { + + CH_IRQ_PROLOGUE(); + + if (channels[26] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 26; + channels[26]->dma_func(26, channels[26]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 27 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector38) { + + CH_IRQ_PROLOGUE(); + + if (channels[27] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 27; + channels[27]->dma_func(27, channels[27]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 28 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector39) { + + CH_IRQ_PROLOGUE(); + + if (channels[28] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 28; + channels[28]->dma_func(28, channels[28]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 29 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector40) { + + CH_IRQ_PROLOGUE(); + + if (channels[29] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 29; + channels[29]->dma_func(29, channels[29]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 30 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector41) { + + CH_IRQ_PROLOGUE(); + + if (channels[30] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 30; + channels[30]->dma_func(30, channels[30]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 31 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector42) { + + CH_IRQ_PROLOGUE(); + + if (channels[31] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 31; + channels[31]->dma_func(31, channels[31]->dma_param); + + CH_IRQ_EPILOGUE(); +} +#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__) +/** + * @brief EDMA (channels 32..64) error interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector210) { + edma_channel_t channel; + uint32_t erh, esr = SPC5_EDMA.ESR.R; + + CH_IRQ_PROLOGUE(); + + /* Scanning for errors.*/ + channel = 32; + while (((erh = SPC5_EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) { + + if ((erh & (1U << (channel - 32))) != 0) { + /* Error flag cleared.*/ + SPC5_EDMA.CER.R = channel; + + /* If the channel is not associated then the error is simply discarded + else the error callback is invoked.*/ + if ((channels[channel] != NULL) && + (channels[channel]->dma_error_func != NULL)) + channels[channel]->dma_error_func(channel, + channels[channel]->dma_param, + esr); + channel++; + } + } + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 32 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector211) { + + CH_IRQ_PROLOGUE(); + + if (channels[32] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 32; + channels[32]->dma_func(32, channels[32]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 33 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector212) { + + CH_IRQ_PROLOGUE(); + + if (channels[33] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 33; + channels[33]->dma_func(33, channels[33]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 34 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector213) { + + CH_IRQ_PROLOGUE(); + + if (channels[34] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 34; + channels[34]->dma_func(34, channels[34]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 35 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector214) { + + CH_IRQ_PROLOGUE(); + + if (channels[35] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 35; + channels[35]->dma_func(35, channels[35]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 36 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector215) { + + CH_IRQ_PROLOGUE(); + + if (channels[36] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 36; + channels[36]->dma_func(36, channels[36]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 37 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector216) { + + CH_IRQ_PROLOGUE(); + + if (channels[37] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 37; + channels[37]->dma_func(37, channels[37]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 38 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector217) { + + CH_IRQ_PROLOGUE(); + + if (channels[38] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 38; + channels[38]->dma_func(38, channels[38]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 39 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector218) { + + CH_IRQ_PROLOGUE(); + + if (channels[39] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 39; + channels[39]->dma_func(39, channels[39]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 40 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector219) { + + CH_IRQ_PROLOGUE(); + + if (channels[40] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 40; + channels[40]->dma_func(40, channels[40]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 41 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector220) { + + CH_IRQ_PROLOGUE(); + + if (channels[41] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 41; + channels[41]->dma_func(41, channels[41]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 42 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector221) { + + CH_IRQ_PROLOGUE(); + + if (channels[42] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 42; + channels[42]->dma_func(42, channels[42]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 43 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector222) { + + CH_IRQ_PROLOGUE(); + + if (channels[43] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 43; + channels[43]->dma_func(43, channels[43]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 44 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector223) { + + CH_IRQ_PROLOGUE(); + + if (channels[44] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 44; + channels[44]->dma_func(44, channels[44]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 45 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector224) { + + CH_IRQ_PROLOGUE(); + + if (channels[45] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 45; + channels[45]->dma_func(45, channels[45]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 46 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector225) { + + CH_IRQ_PROLOGUE(); + + if (channels[46] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 46; + channels[46]->dma_func(46, channels[46]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 47 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector226) { + + CH_IRQ_PROLOGUE(); + + if (channels[47] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 47; + channels[47]->dma_func(47, channels[47]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 48 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector227) { + + CH_IRQ_PROLOGUE(); + + if (channels[48] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 48; + channels[48]->dma_func(48, channels[48]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 49 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector228) { + + CH_IRQ_PROLOGUE(); + + if (channels[49] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 49; + channels[49]->dma_func(49, channels[49]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 50 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector229) { + + CH_IRQ_PROLOGUE(); + + if (channels[50] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 50; + channels[50]->dma_func(50, channels[50]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 51 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector230) { + + CH_IRQ_PROLOGUE(); + + if (channels[51] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 51; + channels[51]->dma_func(51, channels[51]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 52 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector231) { + + CH_IRQ_PROLOGUE(); + + if (channels[52] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 52; + channels[52]->dma_func(52, channels[52]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 53 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector232) { + + CH_IRQ_PROLOGUE(); + + if (channels[53] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 53; + channels[53]->dma_func(53, channels[53]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 54 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector233) { + + CH_IRQ_PROLOGUE(); + + if (channels[54] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 54; + channels[54]->dma_func(54, channels[54]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 55 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector234) { + + CH_IRQ_PROLOGUE(); + + if (channels[55] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 55; + channels[55]->dma_func(55, channels[55]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 56 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector235) { + + CH_IRQ_PROLOGUE(); + + if (channels[56] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 56; + channels[56]->dma_func(56, channels[56]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 57 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector236) { + + CH_IRQ_PROLOGUE(); + + if (channels[57] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 57; + channels[57]->dma_func(57, channels[57]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 58 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector237) { + + CH_IRQ_PROLOGUE(); + + if (channels[58] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 58; + channels[58]->dma_func(58, channels[58]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 59 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector238) { + + CH_IRQ_PROLOGUE(); + + if (channels[59] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 59; + channels[59]->dma_func(59, channels[59]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 60 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector239) { + + CH_IRQ_PROLOGUE(); + + if (channels[60] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 60; + channels[60]->dma_func(60, channels[60]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 61 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector240) { + + CH_IRQ_PROLOGUE(); + + if (channels[61] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 61; + channels[61]->dma_func(61, channels[61]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 62 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector241) { + + CH_IRQ_PROLOGUE(); + + if (channels[62] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 62; + channels[62]->dma_func(62, channels[62]->dma_param); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EDMA channel 63 interrupt. + * + * @isr + */ +CH_IRQ_HANDLER(vector242) { + + CH_IRQ_PROLOGUE(); + + if (channels[63] == NULL) { + SPC5_EDMA_ERROR_HANDLER(); + } + SPC5_EDMA.CIRQR.R = 63; + channels[63]->dma_func(63, channels[63]->dma_param); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_EDMA_NCHANNELS > 32 */ +#endif /* SPC5_EDMA_NCHANNELS > 16 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EDMA driver initialization. + * + * @special + */ +void edmaInit(void) { + unsigned i; + + SPC5_EDMA.CR.R = SPC5_EDMA_CR_SETTING; + SPC5_EDMA.ERQRL.R = 0x00000000; + SPC5_EDMA.EEIRL.R = 0x00000000; + SPC5_EDMA.IRQRL.R = 0xFFFFFFFF; + SPC5_EDMA.ERL.R = 0xFFFFFFFF; +#if SPC5_EDMA_NCHANNELS > 32 + SPC5_EDMA.ERQRH.R = 0x00000000; + SPC5_EDMA.EEIRH.R = 0x00000000; + SPC5_EDMA.IRQRH.R = 0xFFFFFFFF; + SPC5_EDMA.ERH.R = 0xFFFFFFFF; +#endif + /* Initializing all the channels with a different priority withing the + channels group.*/ + for (i = 0; i < 16; i++) { + SPC5_EDMA.CPR[i].R = g0[i]; +#if SPC5_EDMA_NCHANNELS > 16 + SPC5_EDMA.CPR[i + 16].R = g1[i]; +#endif +#if SPC5_EDMA_NCHANNELS > 32 + SPC5_EDMA.CPR[i + 32].R = g2[i]; + SPC5_EDMA.CPR[i + 48].R = g3[i]; +#endif + } + + /* Error interrupt source.*/ + INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO; + +#if defined(SPC5_EDMA_MUX_PCTL) + /* DMA MUX PCTL setup, only if required.*/ + halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL); +#endif +} + +/** + * @brief EDMA channel allocation. + * + * @param[in] ccfg channel configuration + * @return The channel number. + * @retval EDMA_ERROR if the channel cannot be allocated. + * + * @special + */ +edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) { + + chDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16), + "edmaChannelAllocate"); + + /* If the channel is already taken then an error is returned.*/ + if (channels[ccfg->dma_channel] != NULL) + return EDMA_ERROR; /* Already taken. */ + +#if SPC5_EDMA_HAS_MUX + /* Programming the MUX.*/ + SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 | + ccfg->dma_periph); +#endif /* !SPC5_EDMA_HAS_MUX */ + + /* Associating the configuration to the channel.*/ + channels[ccfg->dma_channel] = ccfg; + + /* If an error callback is defined then the error interrupt source is + enabled for the channel.*/ + if (ccfg->dma_error_func != NULL) + SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel; + + /* Setting up IRQ priority for the selected channel.*/ + INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio; + + return ccfg->dma_channel; +} + +/** + * @brief EDMA channel release. + * + * @param[in] channel the channel number + * + * @special + */ +void edmaChannelRelease(edma_channel_t channel) { + + chDbgCheck((channel >= 0) && (channel < SPC5_EDMA_NCHANNELS), + "edmaChannelAllocate"); + chDbgAssert(channels[channel] != NULL, + "edmaChannelRelease(), #1", + "not allocated"); + + /* Enforcing a stop.*/ + edmaChannelStop(channel); + +#if SPC5_EDMA_HAS_MUX + /* Disabling the MUX slot.*/ + SPC5_DMAMUX.CHCONFIG[channel].R = 0; +#endif + + /* Clearing ISR sources for the channel.*/ + SPC5_EDMA.CIRQR.R = channel; + SPC5_EDMA.CEEIR.R = channel; + SPC5_EDMA.CER.R = channel; + + /* The channels is flagged as available.*/ + channels[channel] = NULL; +} + +#endif /* SPC5_HAS_EDMA */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h new file mode 100644 index 000000000..e66574e4a --- /dev/null +++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h @@ -0,0 +1,1004 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/spc5_edma.h + * @brief EDMA helper driver header. + * + * @addtogroup SPC5xx_EDMA + * @{ + */ + +#ifndef _SPC5_EDMA_H_ +#define _SPC5_EDMA_H_ + +#if SPC5_HAS_EDMA + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief EDMA channel allocation error. + */ +#define EDMA_ERROR -1 + +/** + * @name EDMA CR register definitions + * @{ + */ +#define EDMA_CR_CX (1U << 17) +#define EDMA_CR_ECX (1U << 16) +#define EDMA_CR_GRP3PRI_MASK (3U << 14) +#define EDMA_CR_GRP3PRI(n) ((n) << 14) +#define EDMA_CR_GRP2PRI_MASK (3U << 12) +#define EDMA_CR_GRP2PRI(n) ((n) << 12) +#define EDMA_CR_GRP1PRI_MASK (3U << 10) +#define EDMA_CR_GRP1PRI(n) ((n) << 10) +#define EDMA_CR_GRP0PRI_MASK (3U << 8) +#define EDMA_CR_GRP0PRI(n) ((n) << 8) +#define EDMA_CR_EMLM (1U << 7) +#define EDMA_CR_CLM (1U << 6) +#define EDMA_CR_HALT (1U << 5) +#define EDMA_CR_HOE (1U << 4) +#define EDMA_CR_ERGA (1U << 3) +#define EDMA_CR_ERCA (1U << 2) +#define EDMA_CR_EDBG (1U << 1) +#define EDMA_CR_EBW (1U << 0) +/** @} */ + +/** + * @name EDMA mode constants + * @{ + */ +#define EDMA_TCD_MODE_START (1U << 0) +#define EDMA_TCD_MODE_INT_END (1U << 1) +#define EDMA_TCD_MODE_INT_HALF (1U << 2) +#define EDMA_TCD_MODE_DREQ (1U << 3) +#define EDMA_TCD_MODE_SG (1U << 4) +#define EDMA_TCD_MODE_MELINK (1U << 5) +#define EDMA_TCD_MODE_ACTIVE (1U << 6) +#define EDMA_TCD_MODE_DONE (1U << 7) +#define EDMA_TCD_MODE_MLINKCH_MASK (63U << 8) +#define EDMA_TCD_MODE_MLINKCH(n) ((uint32_t)(n) << 8) +#define EDMA_TCD_MODE_BWC_MASK (3U << 14) +#define EDMA_TCD_MODE_BWC(n) ((uint32_t)(n) << 14) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Default EDMA CR register initialization. + */ +#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__) +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#endif + +/** + * @brief Static priorities for channels group 0. + */ +#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 1. + */ +#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 2. + */ +#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 3. + */ +#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief EDMA error handler IRQ priority. + */ +#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#endif + +/** + * @brief EDMA peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_EDMA_MUX_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief EDMA critical error handler, must not return. + */ +#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__) +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of and eDMA channel number. + */ +typedef int32_t edma_channel_t; + +/** + * @brief Type of an eDMA TCD. + */ +typedef struct { + union { + uint32_t word[8]; + }; +} edma_tcd_t; + +/** + * @brief Type of an eDMA peripheral. + */ +typedef struct { + + union { + vuint32_t R; + struct { + vuint32_t :14; + vuint32_t CX :1; + vuint32_t ECX :1; + vuint32_t GRP3PRI :2; + vuint32_t GRP2PRI :2; + vuint32_t GRP1PRI :2; + vuint32_t GRP0PRI :2; + vuint32_t EMLM :1; + vuint32_t CLM :1; + vuint32_t HALT :1; + vuint32_t HOE :1; + vuint32_t ERGA :1; + vuint32_t ERCA :1; + vuint32_t EDBG :1; + vuint32_t :1; + } B; + } CR; /* DMA Control Register @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t VLD :1; + vuint32_t :14; + vuint32_t ECX :1; + vuint32_t GPE :1; + vuint32_t CPE :1; + vuint32_t ERRCHN :6; + vuint32_t SAE :1; + vuint32_t SOE :1; + vuint32_t DAE :1; + vuint32_t DOE :1; + vuint32_t NCE :1; + vuint32_t SGE :1; + vuint32_t SBE :1; + vuint32_t DBE :1; + } B; + } ESR; /* Error Status Register @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t ERQ63 :1; + vuint32_t ERQ62 :1; + vuint32_t ERQ61 :1; + vuint32_t ERQ60 :1; + vuint32_t ERQ59 :1; + vuint32_t ERQ58 :1; + vuint32_t ERQ57 :1; + vuint32_t ERQ56 :1; + vuint32_t ERQ55 :1; + vuint32_t ERQ54 :1; + vuint32_t ERQ53 :1; + vuint32_t ERQ52 :1; + vuint32_t ERQ51 :1; + vuint32_t ERQ50 :1; + vuint32_t ERQ49 :1; + vuint32_t ERQ48 :1; + vuint32_t ERQ47 :1; + vuint32_t ERQ46 :1; + vuint32_t ERQ45 :1; + vuint32_t ERQ44 :1; + vuint32_t ERQ43 :1; + vuint32_t ERQ42 :1; + vuint32_t ERQ41 :1; + vuint32_t ERQ40 :1; + vuint32_t ERQ39 :1; + vuint32_t ERQ38 :1; + vuint32_t ERQ37 :1; + vuint32_t ERQ36 :1; + vuint32_t ERQ35 :1; + vuint32_t ERQ34 :1; + vuint32_t ERQ33 :1; + vuint32_t ERQ32 :1; + } B; + } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/ + + union { + vuint32_t R; + struct { + vuint32_t ERQ31 :1; + vuint32_t ERQ30 :1; + vuint32_t ERQ29 :1; + vuint32_t ERQ28 :1; + vuint32_t ERQ27 :1; + vuint32_t ERQ26 :1; + vuint32_t ERQ25 :1; + vuint32_t ERQ24 :1; + vuint32_t ERQ23 :1; + vuint32_t ERQ22 :1; + vuint32_t ERQ21 :1; + vuint32_t ERQ20 :1; + vuint32_t ERQ19 :1; + vuint32_t ERQ18 :1; + vuint32_t ERQ17 :1; + vuint32_t ERQ16 :1; + vuint32_t ERQ15 :1; + vuint32_t ERQ14 :1; + vuint32_t ERQ13 :1; + vuint32_t ERQ12 :1; + vuint32_t ERQ11 :1; + vuint32_t ERQ10 :1; + vuint32_t ERQ09 :1; + vuint32_t ERQ08 :1; + vuint32_t ERQ07 :1; + vuint32_t ERQ06 :1; + vuint32_t ERQ05 :1; + vuint32_t ERQ04 :1; + vuint32_t ERQ03 :1; + vuint32_t ERQ02 :1; + vuint32_t ERQ01 :1; + vuint32_t ERQ00 :1; + } B; + } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/ + + union { + vuint32_t R; + struct { + + vuint32_t EEI63 :1; + vuint32_t EEI62 :1; + vuint32_t EEI61 :1; + vuint32_t EEI60 :1; + vuint32_t EEI59 :1; + vuint32_t EEI58 :1; + vuint32_t EEI57 :1; + vuint32_t EEI56 :1; + vuint32_t EEI55 :1; + vuint32_t EEI54 :1; + vuint32_t EEI53 :1; + vuint32_t EEI52 :1; + vuint32_t EEI51 :1; + vuint32_t EEI50 :1; + vuint32_t EEI49 :1; + vuint32_t EEI48 :1; + vuint32_t EEI47 :1; + vuint32_t EEI46 :1; + vuint32_t EEI45 :1; + vuint32_t EEI44 :1; + vuint32_t EEI43 :1; + vuint32_t EEI42 :1; + vuint32_t EEI41 :1; + vuint32_t EEI40 :1; + vuint32_t EEI39 :1; + vuint32_t EEI38 :1; + vuint32_t EEI37 :1; + vuint32_t EEI36 :1; + vuint32_t EEI35 :1; + vuint32_t EEI34 :1; + vuint32_t EEI33 :1; + vuint32_t EEI32 :1; + } B; + } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/ + + union { + vuint32_t R; + struct { + vuint32_t EEI31 :1; + vuint32_t EEI30 :1; + vuint32_t EEI29 :1; + vuint32_t EEI28 :1; + vuint32_t EEI27 :1; + vuint32_t EEI26 :1; + vuint32_t EEI25 :1; + vuint32_t EEI24 :1; + vuint32_t EEI23 :1; + vuint32_t EEI22 :1; + vuint32_t EEI21 :1; + vuint32_t EEI20 :1; + vuint32_t EEI19 :1; + vuint32_t EEI18 :1; + vuint32_t EEI17 :1; + vuint32_t EEI16 :1; + vuint32_t EEI15 :1; + vuint32_t EEI14 :1; + vuint32_t EEI13 :1; + vuint32_t EEI12 :1; + vuint32_t EEI11 :1; + vuint32_t EEI10 :1; + vuint32_t EEI09 :1; + vuint32_t EEI08 :1; + vuint32_t EEI07 :1; + vuint32_t EEI06 :1; + vuint32_t EEI05 :1; + vuint32_t EEI04 :1; + vuint32_t EEI03 :1; + vuint32_t EEI02 :1; + vuint32_t EEI01 :1; + vuint32_t EEI00 :1; + } B; + } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t SERQ :7; + } B; + } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t CERQ :7; + } B; + } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t SEEI :7; + } B; + } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t CEEI :7; + } B; + } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t CINT :7; + } B; + } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t CERR :7; + } B; + } CER; /* DMA Clear error Register @baseaddress + 0x1D */ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t SSB :7; + } B; + } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */ + + union { + vuint8_t R; + struct { + vuint8_t NOP :1; + vuint8_t CDSB :7; + } B; + } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */ + + union { + vuint32_t R; + struct { + vuint32_t INT63 :1; + vuint32_t INT62 :1; + vuint32_t INT61 :1; + vuint32_t INT60 :1; + vuint32_t INT59 :1; + vuint32_t INT58 :1; + vuint32_t INT57 :1; + vuint32_t INT56 :1; + vuint32_t INT55 :1; + vuint32_t INT54 :1; + vuint32_t INT53 :1; + vuint32_t INT52 :1; + vuint32_t INT51 :1; + vuint32_t INT50 :1; + vuint32_t INT49 :1; + vuint32_t INT48 :1; + vuint32_t INT47 :1; + vuint32_t INT46 :1; + vuint32_t INT45 :1; + vuint32_t INT44 :1; + vuint32_t INT43 :1; + vuint32_t INT42 :1; + vuint32_t INT41 :1; + vuint32_t INT40 :1; + vuint32_t INT39 :1; + vuint32_t INT38 :1; + vuint32_t INT37 :1; + vuint32_t INT36 :1; + vuint32_t INT35 :1; + vuint32_t INT34 :1; + vuint32_t INT33 :1; + vuint32_t INT32 :1; + } B; + } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t INT31 :1; + vuint32_t INT30 :1; + vuint32_t INT29 :1; + vuint32_t INT28 :1; + vuint32_t INT27 :1; + vuint32_t INT26 :1; + vuint32_t INT25 :1; + vuint32_t INT24 :1; + vuint32_t INT23 :1; + vuint32_t INT22 :1; + vuint32_t INT21 :1; + vuint32_t INT20 :1; + vuint32_t INT19 :1; + vuint32_t INT18 :1; + vuint32_t INT17 :1; + vuint32_t INT16 :1; + vuint32_t INT15 :1; + vuint32_t INT14 :1; + vuint32_t INT13 :1; + vuint32_t INT12 :1; + vuint32_t INT11 :1; + vuint32_t INT10 :1; + vuint32_t INT09 :1; + vuint32_t INT08 :1; + vuint32_t INT07 :1; + vuint32_t INT06 :1; + vuint32_t INT05 :1; + vuint32_t INT04 :1; + vuint32_t INT03 :1; + vuint32_t INT02 :1; + vuint32_t INT01 :1; + vuint32_t INT00 :1; + } B; + } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t ERR63 :1; + vuint32_t ERR62 :1; + vuint32_t ERR61 :1; + vuint32_t ERR60 :1; + vuint32_t ERR59 :1; + vuint32_t ERR58 :1; + vuint32_t ERR57 :1; + vuint32_t ERR56 :1; + vuint32_t ERR55 :1; + vuint32_t ERR54 :1; + vuint32_t ERR53 :1; + vuint32_t ERR52 :1; + vuint32_t ERR51 :1; + vuint32_t ERR50 :1; + vuint32_t ERR49 :1; + vuint32_t ERR48 :1; + vuint32_t ERR47 :1; + vuint32_t ERR46 :1; + vuint32_t ERR45 :1; + vuint32_t ERR44 :1; + vuint32_t ERR43 :1; + vuint32_t ERR42 :1; + vuint32_t ERR41 :1; + vuint32_t ERR40 :1; + vuint32_t ERR39 :1; + vuint32_t ERR38 :1; + vuint32_t ERR37 :1; + vuint32_t ERR36 :1; + vuint32_t ERR35 :1; + vuint32_t ERR34 :1; + vuint32_t ERR33 :1; + vuint32_t ERR32 :1; + } B; + } ERH; /* DMA Error High @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t ERR31 :1; + vuint32_t ERR30 :1; + vuint32_t ERR29 :1; + vuint32_t ERR28 :1; + vuint32_t ERR27 :1; + vuint32_t ERR26 :1; + vuint32_t ERR25 :1; + vuint32_t ERR24 :1; + vuint32_t ERR23 :1; + vuint32_t ERR22 :1; + vuint32_t ERR21 :1; + vuint32_t ERR20 :1; + vuint32_t ERR19 :1; + vuint32_t ERR18 :1; + vuint32_t ERR17 :1; + vuint32_t ERR16 :1; + vuint32_t ERR15 :1; + vuint32_t ERR14 :1; + vuint32_t ERR13 :1; + vuint32_t ERR12 :1; + vuint32_t ERR11 :1; + vuint32_t ERR10 :1; + vuint32_t ERR09 :1; + vuint32_t ERR08 :1; + vuint32_t ERR07 :1; + vuint32_t ERR06 :1; + vuint32_t ERR05 :1; + vuint32_t ERR04 :1; + vuint32_t ERR03 :1; + vuint32_t ERR02 :1; + vuint32_t ERR01 :1; + vuint32_t ERR00 :1; + } B; + } ERL; /* DMA Error Low @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t HRS63 :1; + vuint32_t HRS62 :1; + vuint32_t HRS61 :1; + vuint32_t HRS60 :1; + vuint32_t HRS59 :1; + vuint32_t HRS58 :1; + vuint32_t HRS57 :1; + vuint32_t HRS56 :1; + vuint32_t HRS55 :1; + vuint32_t HRS54 :1; + vuint32_t HRS53 :1; + vuint32_t HRS52 :1; + vuint32_t HRS51 :1; + vuint32_t HRS50 :1; + vuint32_t HRS49 :1; + vuint32_t HRS48 :1; + vuint32_t HRS47 :1; + vuint32_t HRS46 :1; + vuint32_t HRS45 :1; + vuint32_t HRS44 :1; + vuint32_t HRS43 :1; + vuint32_t HRS42 :1; + vuint32_t HRS41 :1; + vuint32_t HRS40 :1; + vuint32_t HRS39 :1; + vuint32_t HRS38 :1; + vuint32_t HRS37 :1; + vuint32_t HRS36 :1; + vuint32_t HRS35 :1; + vuint32_t HRS34 :1; + vuint32_t HRS33 :1; + vuint32_t HRS32 :1; + } B; + } HRSH; /* hardware request status high @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t HRS31 :1; + vuint32_t HRS30 :1; + vuint32_t HRS29 :1; + vuint32_t HRS28 :1; + vuint32_t HRS27 :1; + vuint32_t HRS26 :1; + vuint32_t HRS25 :1; + vuint32_t HRS24 :1; + vuint32_t HRS23 :1; + vuint32_t HRS22 :1; + vuint32_t HRS21 :1; + vuint32_t HRS20 :1; + vuint32_t HRS19 :1; + vuint32_t HRS18 :1; + vuint32_t HRS17 :1; + vuint32_t HRS16 :1; + vuint32_t HRS15 :1; + vuint32_t HRS14 :1; + vuint32_t HRS13 :1; + vuint32_t HRS12 :1; + vuint32_t HRS11 :1; + vuint32_t HRS10 :1; + vuint32_t HRS09 :1; + vuint32_t HRS08 :1; + vuint32_t HRS07 :1; + vuint32_t HRS06 :1; + vuint32_t HRS05 :1; + vuint32_t HRS04 :1; + vuint32_t HRS03 :1; + vuint32_t HRS02 :1; + vuint32_t HRS01 :1; + vuint32_t HRS00 :1; + } B; + } HRSL; /* hardware request status low @baseaddress + 0x34 */ + + uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ + + union { + vuint8_t R; + struct { + vuint8_t ECP :1; + vuint8_t DPA :1; + vuint8_t GRPPRI :2; + vuint8_t CHPRI :4; + } B; + } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */ + + uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */ + + edma_tcd_t TCD[64]; +} edma_t; + +#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__) +/** + * @brief Type of a DMA-MUX peripheral. + */ +typedef struct { + union { + vuint8_t R; + struct { + vuint8_t ENBL:1; + vuint8_t TRIG:1; + vuint8_t SOURCE:6; + } B; + } CHCONFIG[SPC5_EDMA_NCHANNELS]; +} dma_mux_t; +#endif /* SPC5_EDMA_HAS_MUX */ + +/** + * @brief DMA callback type. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + */ +typedef void (*edma_callback_t)(edma_channel_t channel, void *p); + +/** + * @brief DMA error callback type. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * @param[in] esr content of the ESR register + */ +typedef void (*edma_error_callback_t)(edma_channel_t channel, + void *p, + uint32_t esr); + +/** + * @brief Type of an EDMA channel configuration structure. + */ +typedef struct { + edma_channel_t dma_channel; /**< @brief Channel to be allocated.*/ +#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__) + uint8_t dma_periph; /**< @brief Peripheral to be + associated to the channel. */ +#endif + uint8_t dma_irq_prio; /**< @brief IRQ priority level for + this channel. */ + edma_callback_t dma_func; /**< @brief Channel callback, + can be NULL if not required. */ + edma_error_callback_t dma_error_func; /**< @brief Channel error callback, + can be NULL if not required. */ + void *dma_param; /**< @brief Channel callback param. */ +} edma_channel_config_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Peripherals references + * + * @{ + */ +#if SPC5_HAS_EDMA || defined(__DOXYGEN__) +#define SPC5_EDMA (*(edma_t *)0xFFF44000U) +#endif + +#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__) +#define SPC5_DMAMUX (*(dma_mux_t *)0xFFFDC000UL) +#endif +/** @} */ + +/** + * @brief Returns the TCD address associated to a channel. + * + * @param[in] channel the channel number + * @return A pointer to an @p edma_tcd_t structure. + * + * @api + */ +#define edmaGetTCD(channel) ((edma_tcd_t *)&SPC5_EDMA.TCD[channel]) + +/** + * @brief Sets the word 0 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] src the source address + * + * @api + */ +#define edmaTCDSetWord0(tcdp, src) \ + ((tcdp)->word[0] = (uint32_t)(src)) + +/** + * @brief Sets the word 1 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] ssize the source width + * @param[in] dst the destination width + * @param[in] soff the source increment value + * + * @api + */ +#define edmaTCDSetWord1(tcdp, ssize, dsize, soff) \ + ((tcdp)->word[1] = (((uint32_t)(ssize) << 24) | \ + ((uint32_t)(dsize) << 16) | \ + ((uint32_t)(soff) << 0))) + +/** + * @brief Sets the word 2 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] nbytes the inner counter value + * + * @api + */ +#define edmaTCDSetWord2(tcdp, nbytes) \ + ((tcdp)->word[2] = (uint32_t)(nbytes)) + +/** + * @brief Sets the word 3 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] slast the adjustment value + * + * @api + */ +#define edmaTCDSetWord3(tcdp, slast) \ + ((tcdp)->word[3] = (uint32_t)(slast)) + +/** + * @brief Sets the word 4 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] dst the destination address + * + * @api + */ +#define edmaTCDSetWord4(tcdp, dst) \ + ((tcdp)->word[4] = (uint32_t)(dst)) + +/** + * @brief Sets the word 5 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] citer the current outer counter value + * @param[in] doff the destination increment value + * + * @api + */ +#define edmaTCDSetWord5(tcdp, citer, doff) \ + ((tcdp)->word[5] = (((uint32_t)(citer) << 16) | \ + ((uint32_t)(doff) << 0))) + +/** + * @brief Sets the word 5 fields into a TCD. + * @note Transfers are limited to 512 operations using this modality + * (citer parameter). + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] linkch channel linked on minor loop counter + * @param[in] citer the current outer counter value + * @param[in] doff the destination increment value + * + * @api + */ +#define edmaTCDSetWord5Linked(tcdp, linkch, citer, doff) \ + ((tcdp)->word[5] = (((uint32_t)0x80000000) | \ + ((uint32_t)(linkch) << 25) | \ + ((uint32_t)(citer) << 16) | \ + ((uint32_t)(doff) << 0))) + +/** + * @brief Sets the word 6 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] dlast the adjustment value + * + * @api + */ +#define edmaTCDSetWord6(tcdp, dlast) \ + ((tcdp)->word[6] = (uint32_t)(dlast)) + +/** + * @brief Sets the word 7 fields into a TCD. + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] biter the base outer counter value + * @param[in] mode the mode value + * + * @api + */ +#define edmaTCDSetWord7(tcdp, biter, mode) \ + ((tcdp)->word[7] = (((uint32_t)(biter) << 16) | \ + ((uint32_t)(mode) << 0))) + +/** + * @brief Sets the word 7 fields into a TCD. + * @note Transfers are limited to 512 operations using this modality + * (biter parameter). + * + * @param[in] tcdp pointer to an @p edma_tcd_t structure + * @param[in] linkch channel linked on minor loop counter + * @param[in] biter the base outer counter value + * @param[in] mode the mode value + * + * @api + */ +#define edmaTCDSetWord7Linked(tcdp, linkch, biter, mode) \ + ((tcdp)->word[7] = (((uint32_t)0x80000000) | \ + ((uint32_t)(linkch) << 25) | \ + ((uint32_t)(biter) << 16) | \ + ((uint32_t)(mode) << 0))) + +/** + * @brief Starts or restarts an EDMA channel. + * + * @param[in] channel the channel number + * + * @api + */ +#define edmaChannelStart(channel) (SPC5_EDMA.SERQR.R = (channel)) + +/** + * @brief Stops an EDMA channel. + * + * @param[in] channel the channel number + * + * @api + */ +#define edmaChannelStop(channel) { \ + SPC5_EDMA.CERQR.R = (channel); \ + SPC5_EDMA.CDSBR.R = (channel); \ +} + +/** + * @brief EDMA channel setup. + * + * @param[in] channel eDMA channel number + * @param[in] src source address + * @param[in] dst destination address + * @param[in] soff source address offset + * @param[in] doff destination address offset + * @param[in] ssize source transfer size + * @param[in] dsize destination transfer size + * @param[in] nbytes minor loop count + * @param[in] iter major loop count + * @param[in] dlast last destination address adjustment + * @param[in] slast last source address adjustment + * @param[in] mode LSW of TCD register 7 + * + * @api + */ +#define edmaChannelSetup(channel, src, dst, soff, doff, ssize, dsize, \ + nbytes, iter, slast, dlast, mode) { \ + edma_tcd_t *tcdp = edmaGetTCD(channel); \ + edmaTCDSetWord0(tcdp, src); \ + edmaTCDSetWord1(tcdp, ssize, dsize, soff); \ + edmaTCDSetWord2(tcdp, nbytes); \ + edmaTCDSetWord3(tcdp, slast); \ + edmaTCDSetWord4(tcdp, dst); \ + edmaTCDSetWord5(tcdp, iter, doff); \ + edmaTCDSetWord6(tcdp, dlast); \ + edmaTCDSetWord7(tcdp, iter, mode); \ +} + +/** + * @brief EDMA channel setup with linked channel on both minor and major + * loop counters. + * @note Transfers are limited to 512 operations using this modality + * (iter parameter). + * + * @param[in] channel eDMA channel number + * @param[in] linkch channel linked on minor loop counter + * @param[in] src source address + * @param[in] dst destination address + * @param[in] soff source address offset + * @param[in] doff destination address offset + * @param[in] ssize source transfer size + * @param[in] dsize destination transfer size + * @param[in] nbytes minor loop count + * @param[in] iter major loop count + * @param[in] dlast last destination address adjustment + * @param[in] slast last source address adjustment + * @param[in] mode LSW of TCD register 7 + * + * @api + */ +#define edmaChannelSetupLinked(channel, linkch, src, dst, soff, \ + doff, ssize, dsize, nbytes, iter, \ + slast, dlast, mode) { \ + edma_tcd_t *tcdp = edmaGetTCD(channel); \ + edmaTCDSetWord0(tcdp, src); \ + edmaTCDSetWord1(tcdp, ssize, dsize, soff); \ + edmaTCDSetWord2(tcdp, nbytes); \ + edmaTCDSetWord3(tcdp, slast); \ + edmaTCDSetWord4(tcdp, dst); \ + edmaTCDSetWord5Linked(tcdp, linkch, iter, doff); \ + edmaTCDSetWord6(tcdp, dlast); \ + edmaTCDSetWord7Linked(tcdp, linkch, iter, (mode) | \ + EDMA_TCD_MODE_MELINK | \ + EDMA_TCD_MODE_MLINKCH(linkch)); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void edmaInit(void); + edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg); + void edmaChannelRelease(edma_channel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* SPC5_HAS_EDMA */ + +#endif /* _SPC5_EDMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c new file mode 100644 index 000000000..cb479fa1b --- /dev/null +++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c @@ -0,0 +1,744 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/EQADC_v1/adc_lld.c + * @brief SPC5xx low level ADC driver code. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/* Some forward declarations.*/ +static void adc_serve_rfifo_irq(edma_channel_t channel, void *p); +static void adc_serve_dma_error_irq(edma_channel_t channel, + void *p, + uint32_t esr); + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Calibration constant. + * @details Ideal conversion result for 75%(VRH - VRL) minus 2. + */ +#define ADC_IDEAL_RES75_2 12286 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ADCD1 driver identifier. + */ +#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** + * @brief ADCD2 driver identifier. + */ +#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/** + * @brief ADCD3 driver identifier. + */ +#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/** + * @brief ADCD4 driver identifier. + */ +#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__) +ADCDriver ADCD4; +#endif + +/** + * @brief ADCD5 driver identifier. + */ +#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__) +ADCDriver ADCD5; +#endif + +/** + * @brief ADCD6 driver identifier. + */ +#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__) +ADCDriver ADCD6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Number of active ADC FIFOs. + */ +static uint32_t adc_active_fifos; + +/** + * @brief Static setup for input resistors. + */ +static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR; + +#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO0. + */ +static const edma_channel_config_t adc_cfifo0_dma_config = { + 0, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD1 +}; + +/** + * @brief DMA configuration for EQADC RFIFO0. + */ +static const edma_channel_config_t adc_rfifo0_dma_config = { + 1, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD1 +}; +#endif /* SPC5_ADC_USE_ADC0_Q0 */ + +#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO1. + */ +static const edma_channel_config_t adc_cfifo1_dma_config = { + 2, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD2 +}; + +/** + * @brief DMA configuration for EQADC RFIFO1. + */ +static const edma_channel_config_t adc_rfifo1_dma_config = { + 3, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD2 +}; +#endif /* SPC5_ADC_USE_ADC0_Q1 */ + +#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO2. + */ +static const edma_channel_config_t adc_cfifo2_dma_config = { + 4, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD3 +}; + +/** + * @brief DMA configuration for EQADC RFIFO2. + */ +static const edma_channel_config_t adc_rfifo2_dma_config = { + 5, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD3 +}; +#endif /* SPC5_ADC_USE_ADC0_Q2 */ + +#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO3. + */ +static const edma_channel_config_t adc_cfifo3_dma_config = { + 6, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD4 +}; + +/** + * @brief DMA configuration for EQADC RFIFO3. + */ +static const edma_channel_config_t adc_rfifo3_dma_config = { + 7, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD4 +}; +#endif /* SPC5_ADC_USE_ADC1_Q3 */ + +#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO4. + */ +static const edma_channel_config_t adc_cfifo4_dma_config = { + 8, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD5 +}; + +/** + * @brief DMA configuration for EQADC RFIFO4. + */ +static const edma_channel_config_t adc_rfifo4_dma_config = { + 9, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD5 +}; +#endif /* SPC5_ADC_USE_ADC1_Q4 */ + +#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__) +/** + * @brief DMA configuration for EQADC CFIFO5. + */ +static const edma_channel_config_t adc_cfifo5_dma_config = { + 10, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, + NULL, adc_serve_dma_error_irq, &ADCD6 +}; + +/** + * @brief DMA configuration for EQADC RFIFO5. + */ +static const edma_channel_config_t adc_rfifo5_dma_config = { + 11, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, + adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD6 +}; +#endif /* SPC5_ADC_USE_ADC1_Q5 */ + +/*===========================================================================*/ +/* Driver local functions and macros. */ +/*===========================================================================*/ + +/** + * @brief Unsigned two's complement. + * + * @param[in] n the value to be complemented + * + * @notapi + */ +#define CPL2(n) ((~(uint32_t)(n)) + 1) + +/** + * @brief Address of a CFIFO push register. + * + * @param[in] fifo the FIFO identifier + * + * @notapi + */ +#define CFIFO_PUSH_ADDR(fifo) ((uint32_t *)(&EQADC.CFPR[fifo].R)) + +/** + * @brief Address of a RFIFO pop register. + * + * @param[in] fifo the FIFO identifier + * + * @notapi + */ +#define RFIFO_POP_ADDR(fifo) (((uint16_t *)&EQADC.RFPR[fifo].R) + 1) + +/** + * @brief Enables a CFIFO. + * + * @param[in] fifo the FIFO identifier + * @param[in] cfcr CFCR register value + * @param[in] idcr IDCR register value + * + * @notapi + */ +static void cfifo_enable(adcfifo_t fifo, uint16_t cfcr, uint16_t idcr) { + + EQADC.CFCR[fifo].R = cfcr; + EQADC.IDCR[fifo].R = idcr; +} + +/** + * @brief Disables a CFIFO and the associated resources. + * + * @param[in] fifo the FIFO identifier + * + * @notapi + */ +static void cfifo_disable(adcfifo_t fifo) { + + /* Disables the CFIFO.*/ + EQADC.CFCR[fifo].R = EQADC_CFCR_MODE_DISABLED; + + /* Disables Interrupts and DMAs of the CFIFO.*/ + EQADC.IDCR[fifo].R = 0; + + /* Waits for the CFIFO to become idle.*/ + while ((EQADC.CFSR.R & (0xC0000000 >> (fifo * 2))) != 0) + ; + + /* Invalidates the CFIFO.*/ + EQADC.CFCR[fifo].R = EQADC_CFCR_CFINV | EQADC_CFCR_MODE_DISABLED; + + /* Clears all Interrupts and eDMA flags for the CFIFO.*/ + EQADC.FISR[fifo].R = EQADC_FISR_CLEAR_MASK; + + /* Clears the Tx Count Registers for the CFIFO.*/ + EQADC.CFTCR[fifo].R = 0; +} + +/** + * @brief Pushes a command into the CFIFO0. + * + * @param[in] cmd the command + * + * @notapi + */ +static void cfifo0_push_command(adccommand_t cmd) { + + while (EQADC.FISR[0].B.CFCTR >= 4) + ; + EQADC.CFPR[0].R = cmd; +} + +/** + * @brief Waits until the RFIFO0 contains the specified number of entries. + * + * @param[in] n number of entries + * + * @notapi + */ +static void cfifo0_wait_rfifo(uint32_t n) { + + while (EQADC.FISR[0].B.RFCTR < n) + ; + EQADC.FISR[0].R = EQADC_FISR_CLEAR_MASK; +} + +/** + * @brief Reads a sample from the RFIFO0. + * + * @notapi + */ +#define rfifo0_get_value() (EQADC.RFPR[0].R) + +/** + * @brief Writes an internal ADC register. + * + * @param[in] adc the ADC unit + * @param[in] reg the register index + * @param[in] value value to be written into the register + * + * @notapi + */ +#define adc_write_register(adc, reg, value) \ + cfifo0_push_command(EQADC_RW_WRITE | (adc) | EQADC_RW_REG_ADDR(reg) | \ + EQADC_RW_VALUE(value)) + + +/** + * @brief Enables both ADCs. + * + * @notapi + */ +static void adc_enable(void) { + + /* Both ADCs must be enabled because this sentence in the reference manual: + "Both ADC0 and ADC1 of an eQADC module pair must be enabled before + calibrating or using either ADC0 or ADC1 of the pair. Failure to + enable both ADC0 and ADC1 of the pair can result in inaccurate + conversions.".*/ + adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR, + SPC5_ADC_CR_CLK_PS | ADC_CR_EN); + adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR, + SPC5_ADC_CR_CLK_PS | ADC_CR_EN); +} + +/** + * @brief Disables both ADCs. + * + * @notapi + */ +static void adc_disable(void) { + + adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR, + SPC5_ADC_CR_CLK_PS); + adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR, + SPC5_ADC_CR_CLK_PS); +} + +/** + * @brief Calibrates an ADC unit. + * + * @param[in] adc the ADC unit + * + * @notapi + */ +static void adc_calibrate(uint32_t adc) { + uint16_t res25, res75; + uint32_t gcc, occ; + + /* Starts the calibration, write command messages to sample 25% and + 75% VREF.*/ + cfifo0_push_command(0x00002C00 | adc); /* Vref 25%.*/ + cfifo0_push_command(0x00002B00 | adc); /* Vref 75%.*/ + cfifo0_wait_rfifo(2); + + /* Reads the results and compute calibration register values.*/ + res25 = rfifo0_get_value(); + res75 = rfifo0_get_value(); + + gcc = 0x08000000UL / ((uint32_t)res75 - (uint32_t)res25); + occ = (uint32_t)ADC_IDEAL_RES75_2 - ((gcc * (uint32_t)res75) >> 14); + + /* Loads the gain and offset values (default configuration, 12 bits).*/ + adc_write_register(adc, ADC_REG_GCCR, gcc); + adc_write_register(adc, ADC_REG_OCCR, occ & 0xFFFF); + + /* Loads gain and offset values (alternate configuration 1, 10 bits).*/ + adc_write_register(adc, ADC_REG_AC1GCCR, gcc); + adc_write_register(adc, ADC_REG_AC1OCCR, occ & 0xFFFF); + + /* Loads gain and offset values (alternate configuration 1, 8 bits).*/ + adc_write_register(adc, ADC_REG_AC2GCCR, gcc); + adc_write_register(adc, ADC_REG_AC2OCCR, occ & 0xFFFF); +} + +/** + * @brief Calibrates an ADC unit. + * + * @param[in] adc the ADC unit + * + * @notapi + */ +static void adc_setup_resistors(uint32_t adc) { + unsigned i; + + for (i = 0; i < 8; i++) + adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]); +} + +/** + * @brief Shared ISR for RFIFO DMA events. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * + * @notapi + */ +static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) { + ADCDriver *adcp = (ADCDriver *)p; + edma_tcd_t *tcdp = edmaGetTCD(channel); + + if (adcp->grpp != NULL) { + if ((tcdp->word[5] >> 16) != (tcdp->word[7] >> 16)) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + else { + /* Re-starting DMA channels if in circular mode.*/ + if (adcp->grpp->circular) { + edmaChannelStart(adcp->rfifo_channel); + edmaChannelStart(adcp->cfifo_channel); + } + + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } +} + +/** + * @brief Shared ISR for CFIFO/RFIFO DMA error events. + * + * @param[in] channel the channel number + * @param[in] p parameter for the registered function + * @param[in] esr content of the ESR register + * + * @notapi + */ +static void adc_serve_dma_error_irq(edma_channel_t channel, + void *p, + uint32_t esr) { + ADCDriver *adcp = (ADCDriver *)p; + + (void)channel; + (void)esr; + + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + + /* FIFOs initially all not in use.*/ + adc_active_fifos = 0; + +#if SPC5_ADC_USE_ADC0_Q0 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.cfifo_channel = EDMA_ERROR; + ADCD1.rfifo_channel = EDMA_ERROR; + ADCD1.fifo = ADC_FIFO_0; +#endif /* SPC5_ADC_USE_EQADC_Q0 */ + +#if SPC5_ADC_USE_ADC0_Q1 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD2.cfifo_channel = EDMA_ERROR; + ADCD2.rfifo_channel = EDMA_ERROR; + ADCD2.fifo = ADC_FIFO_1; +#endif /* SPC5_ADC_USE_EQADC_Q1 */ + +#if SPC5_ADC_USE_ADC0_Q2 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD3.cfifo_channel = EDMA_ERROR; + ADCD3.rfifo_channel = EDMA_ERROR; + ADCD3.fifo = ADC_FIFO_2; +#endif /* SPC5_ADC_USE_EQADC_Q2 */ + +#if SPC5_ADC_USE_ADC1_Q3 + /* Driver initialization.*/ + adcObjectInit(&ADCD4); + ADCD4.cfifo_channel = EDMA_ERROR; + ADCD4.rfifo_channel = EDMA_ERROR; + ADCD4.fifo = ADC_FIFO_3; +#endif /* SPC5_ADC_USE_ADC1_Q3 */ + +#if SPC5_ADC_USE_ADC1_Q4 + /* Driver initialization.*/ + adcObjectInit(&ADCD5); + ADCD5.cfifo_channel = EDMA_ERROR; + ADCD5.rfifo_channel = EDMA_ERROR; + ADCD5.fifo = ADC_FIFO_4; +#endif /* SPC5_ADC_USE_ADC1_Q4 */ + +#if SPC5_ADC_USE_ADC1_Q5 + /* Driver initialization.*/ + adcObjectInit(&ADCD6); + ADCD6.cfifo_channel = EDMA_ERROR; + ADCD6.rfifo_channel = EDMA_ERROR; + ADCD6.fifo = ADC_FIFO_5; +#endif /* SPC5_ADC_USE_ADC1_Q5 */ + + /* Temporarily enables CFIFO0 for calibration and initialization.*/ + cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0); + adc_enable(); + + /* Calibration of both ADC units, programming alternate configs + one and two for 10 and 8 bits operations, setting up pull up/down + resistors.*/ +#if SPC5_ADC_USE_ADC0 + adc_calibrate(EQADC_RW_BN_ADC0); + adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS); + adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS); + adc_setup_resistors(EQADC_RW_BN_ADC0); +#endif +#if SPC5_ADC_USE_ADC1 + adc_calibrate(EQADC_RW_BN_ADC1); + adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS); + adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS); + adc_setup_resistors(EQADC_RW_BN_ADC1); +#endif + + /* ADCs disabled until the driver is started by the application.*/ + adc_disable(); + cfifo_disable(ADC_FIFO_0); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + chDbgAssert(adc_active_fifos < 6, "adc_lld_start(), #1", "too many FIFOs"); + + if (adcp->state == ADC_STOP) { + /* Enables the peripheral.*/ +#if SPC5_ADC_USE_ADC0_Q0 + if (&ADCD1 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo0_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo0_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC0_Q0 */ + +#if SPC5_ADC_USE_ADC0_Q1 + if (&ADCD2 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo1_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo1_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC0_Q1 */ + +#if SPC5_ADC_USE_ADC0_Q2 + if (&ADCD3 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo2_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo2_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC0_Q2 */ + +#if SPC5_ADC_USE_ADC1_Q3 + if (&ADCD4 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo3_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo3_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC1_Q3 */ + +#if SPC5_ADC_USE_ADC1_Q4 + if (&ADCD5 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo4_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo4_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC1_Q4 */ + +#if SPC5_ADC_USE_ADC1_Q5 + if (&ADCD6 == adcp) { + adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo5_dma_config); + adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo5_dma_config); + adc_active_fifos++; + } +#endif /* SPC5_ADC_USE_ADC1_Q5 */ + + /* If this is the first FIFO activated then the ADC is enabled.*/ + if (adc_active_fifos == 1) + adc_enable(); + } + + chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) && + (adcp->rfifo_channel != EDMA_ERROR), + "adc_lld_start(), #2", "channel cannot be allocated"); +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + chDbgAssert(adc_active_fifos < 6, "adc_lld_stop(), #1", "too many FIFOs"); + + if (adcp->state == ADC_READY) { + /* Resets the peripheral.*/ + + /* Releases the allocated EDMA channels.*/ + edmaChannelRelease(adcp->cfifo_channel); + edmaChannelRelease(adcp->rfifo_channel); + + /* If it is the last active FIFO then the ADC is disable too.*/ + if (--adc_active_fifos == 0) + adc_disable(); + } +} + +/** + * @brief Starts an ADC conversion. + * @note Because an HW constraint the number of rows in the samples + * array must not be greater than the preconfigured value in + * the conversion group. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t bitoff; + + chDbgAssert(adcp->grpp->num_iterations >= adcp->depth, + "adc_lld_start_conversion(), #1", "too many elements"); + + /* Setting up CFIFO TCD parameters.*/ + edmaChannelSetup(adcp->cfifo_channel, /* channel. */ + adcp->grpp->commands, /* src. */ + CFIFO_PUSH_ADDR(adcp->fifo), /* dst. */ + 4, /* soff, advance by 4. */ + 0, /* doff, do not advance. */ + 2, /* ssize, 32 bits transfers.*/ + 2, /* dsize, 32 bits transfers.*/ + 4, /* nbytes, always four. */ + (uint32_t)adcp->grpp->num_channels * + (uint32_t)adcp->depth, /* iter. */ + CPL2((uint32_t)adcp->grpp->num_channels * + (uint32_t)adcp->depth * + sizeof(adccommand_t)), /* slast. */ + 0, /* dlast, no dest.adjust. */ + EDMA_TCD_MODE_DREQ); /* mode. */ + + /* Setting up RFIFO TCD parameters.*/ + edmaChannelSetup(adcp->rfifo_channel, /* channel. */ + RFIFO_POP_ADDR(adcp->fifo), /* src. */ + adcp->samples, /* dst. */ + 0, /* soff, do not advance. */ + 2, /* doff, advance by two. */ + 1, /* ssize, 16 bits transfers.*/ + 1, /* dsize, 16 bits transfers.*/ + 2, /* nbytes, always two. */ + (uint32_t)adcp->grpp->num_channels * + (uint32_t)adcp->depth, /* iter. */ + 0, /* slast, no source adjust. */ + CPL2((uint32_t)adcp->grpp->num_channels * + (uint32_t)adcp->depth * + sizeof(adcsample_t)), /* dlast. */ + EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END | + ((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0));/* mode.*/ + + /* HW triggers setup.*/ + bitoff = 20 + ((uint32_t)adcp->fifo * 2); + SIU.ETISR.R = (SIU.ETISR.R & ~(3U << bitoff)) | + (adcp->grpp->tsel << bitoff); + bitoff = (uint32_t)adcp->fifo * 5; + SIU.ISEL3.R = (SIU.ISEL3.R & ~(31U << bitoff)) | + (adcp->grpp->etsel << bitoff); + + /* Starting DMA channels.*/ + edmaChannelStart(adcp->rfifo_channel); + edmaChannelStart(adcp->cfifo_channel); + + /* Enabling CFIFO, conversion starts.*/ + cfifo_enable(adcp->fifo, adcp->grpp->cfcr, + EQADC_IDCR_CFFE | EQADC_IDCR_CFFS | + EQADC_IDCR_RFDE | EQADC_IDCR_RFDS); +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + /* Stopping DMA channels.*/ + edmaChannelStop(adcp->cfifo_channel); + edmaChannelStop(adcp->rfifo_channel); + + /* Disabling CFIFO.*/ + cfifo_disable(adcp->fifo); +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h new file mode 100644 index 000000000..6be4ca5d4 --- /dev/null +++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h @@ -0,0 +1,663 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/EQADC_v1/adc_lld.c + * @brief SPC5xx low level ADC driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Analog channel identifiers + * @{ + */ +#define ADC_CHN_AN0 0U +#define ADC_CHN_AN1 1U +#define ADC_CHN_AN2 2U +#define ADC_CHN_AN3 3U +#define ADC_CHN_AN4 4U +#define ADC_CHN_AN5 5U +#define ADC_CHN_AN6 6U +#define ADC_CHN_AN7 7U +#define ADC_CHN_AN8 8U +#define ADC_CHN_AN9 9U +#define ADC_CHN_AN10 10U +#define ADC_CHN_AN11 11U +#define ADC_CHN_AN12 12U +#define ADC_CHN_AN13 13U +#define ADC_CHN_AN14 14U +#define ADC_CHN_AN15 15U +#define ADC_CHN_AN16 16U +#define ADC_CHN_AN17 17U +#define ADC_CHN_AN18 18U +#define ADC_CHN_AN19 19U +#define ADC_CHN_AN20 20U +#define ADC_CHN_AN21 21U +#define ADC_CHN_AN22 22U +#define ADC_CHN_AN23 23U +#define ADC_CHN_AN24 24U +#define ADC_CHN_AN25 25U +#define ADC_CHN_AN26 26U +#define ADC_CHN_AN27 27U +#define ADC_CHN_AN28 28U +#define ADC_CHN_AN29 29U +#define ADC_CHN_AN30 30U +#define ADC_CHN_AN31 31U +#define ADC_CHN_AN32 32U +#define ADC_CHN_AN33 33U +#define ADC_CHN_AN34 34U +#define ADC_CHN_AN35 35U +#define ADC_CHN_AN36 36U +#define ADC_CHN_AN37 37U +#define ADC_CHN_AN38 38U +#define ADC_CHN_AN39 39U +#define ADC_CHN_VRH 40U +#define ADC_CHN_VRL 41U +#define ADC_CHN_VREF50 42U +#define ADC_CHN_VREF75 43U +#define ADC_CHN_VREF25 44U +#define ADC_CHN_BANDGAP 45U +#define ADC_CHN_DAN0 96U +#define ADC_CHN_DAN1 97U +#define ADC_CHN_DAN2 98U +#define ADC_CHN_DAN3 99U +#define ADC_CHN_TEMP_SENSOR 128U +#define ADC_CHN_SPARE 129U +/** @} */ + +/** + * @name Internal registers indexes + * @{ + */ +#define ADC_REG_CR 0x1 +#define ADC_REG_TSCR 0x2 +#define ADC_REG_TBCR 0x3 +#define ADC_REG_GCCR 0x4 +#define ADC_REG_OCCR 0x5 +#define ADC_REG_AC1GCCR 0x31 +#define ADC_REG_AC1OCCR 0x32 +#define ADC_REG_AC2GCCR 0x35 +#define ADC_REG_AC2OCCR 0x36 +#define ADC_REG_AC1CR 0x30 +#define ADC_REG_AC2CR 0x34 +#define ADC_REG_AC3CR 0x38 +#define ADC_REG_AC4CR 0x3C +#define ADC_REG_AC5CR 0x40 +#define ADC_REG_AC6CR 0x44 +#define ADC_REG_AC7CR 0x48 +#define ADC_REG_AC8CR 0x4C +#define ADC_REG_PUDCR(n) (0x70 + (n)) +#define ADC_REG_PUDCR0 0x70UL +#define ADC_REG_PUDCR1 0x71UL +#define ADC_REG_PUDCR2 0x72UL +#define ADC_REG_PUDCR3 0x73UL +#define ADC_REG_PUDCR4 0x74UL +#define ADC_REG_PUDCR5 0x75UL +#define ADC_REG_PUDCR6 0x76UL +#define ADC_REG_PUDCR7 0x77UL +/** @} */ + +/** + * @name EQADC IDCR registers definitions + * @{ + */ +#define EQADC_IDCR_NCIE (1U << 15) +#define EQADC_IDCR_TORIE (1U << 14) +#define EQADC_IDCR_PIE (1U << 13) +#define EQADC_IDCR_EOQIE (1U << 12) +#define EQADC_IDCR_CFUIE (1U << 11) +#define EQADC_IDCR_CFFE (1U << 9) +#define EQADC_IDCR_CFFS (1U << 8) +#define EQADC_IDCR_RFOIE (1U << 3) +#define EQADC_IDCR_RFDE (1U << 1) +#define EQADC_IDCR_RFDS (1U << 0) +/** @} */ + +/** + * @name EQADC CFCR registers definitions + * @{ + */ +#define EQADC_CFCR_CFEEE0 (1U << 12) +#define EQADC_CFCR_STRME0 (1U << 11) +#define EQADC_CFCR_SSE (1U << 10) +#define EQADC_CFCR_CFINV (1U << 9) +#define EQADC_CFCR_MODE_MASK (15U << 4) +#define EQADC_CFCR_MODE(n) ((n) << 4) +#define EQADC_CFCR_MODE_DISABLED EQADC_CFCR_MODE(0) +#define EQADC_CFCR_MODE_SWSS EQADC_CFCR_MODE(1) +#define EQADC_CFCR_MODE_HWSS_LL EQADC_CFCR_MODE(2) +#define EQADC_CFCR_MODE_HWSS_HL EQADC_CFCR_MODE(3) +#define EQADC_CFCR_MODE_HWSS_FE EQADC_CFCR_MODE(4) +#define EQADC_CFCR_MODE_HWSS_RE EQADC_CFCR_MODE(5) +#define EQADC_CFCR_MODE_HWSS_BE EQADC_CFCR_MODE(6) +#define EQADC_CFCR_MODE_SWCS EQADC_CFCR_MODE(9) +#define EQADC_CFCR_MODE_HWCS_LL EQADC_CFCR_MODE(10) +#define EQADC_CFCR_MODE_HWCS_HL EQADC_CFCR_MODE(11) +#define EQADC_CFCR_MODE_HWCS_FE EQADC_CFCR_MODE(12) +#define EQADC_CFCR_MODE_HWCS_RE EQADC_CFCR_MODE(13) +#define EQADC_CFCR_MODE_HWCS_BE EQADC_CFCR_MODE(14) +#define EQADC_CFCR_AMODE0_MASK (15U << 0) +#define EQADC_CFCR_AMODE0(n) ((n) << 0) +/** @} */ + +/** + * @name EQADC FISR registers definitions + * @{ + */ +#define EQADC_FISR_POPNXTPTR_MASK (15U << 0) +#define EQADC_FISR_RFCTR_MASK (15U << 4) +#define EQADC_FISR_TNXTPTR_MASK (15U << 8) +#define EQADC_FISR_CFCTR_MASK (15U << 12) +#define EQADC_FISR_RFDF (1U << 17) +#define EQADC_FISR_RFOF (1U << 19) +#define EQADC_FISR_CFFF (1U << 25) +#define EQADC_FISR_SSS (1U << 26) +#define EQADC_FISR_CFUF (1U << 27) +#define EQADC_FISR_EOQF (1U << 28) +#define EQADC_FISR_PF (1U << 29) +#define EQADC_FISR_TORF (1U << 30) +#define EQADC_FISR_NCF (1U << 31) +#define EQADC_FISR_CLEAR_MASK (EQADC_FISR_NCF | EQADC_FISR_TORF | \ + EQADC_FISR_PF | EQADC_FISR_EOQF | \ + EQADC_FISR_CFUF | EQADC_FISR_RFOF | \ + EQADC_FISR_RFDF) +/** @} */ + +/** + * @name EQADC conversion/configuration commands + * @{ + */ +#define EQADC_CONV_CONFIG_STD (0U << 0) /**< @brief Alt.config.1. */ +#define EQADC_CONV_CONFIG_SEL1 (8U << 0) /**< @brief Alt.config.1. */ +#define EQADC_CONV_CONFIG_SEL2 (9U << 0) /**< @brief Alt.config.2. */ +#define EQADC_CONV_CONFIG_SEL3 (10U << 0) /**< @brief Alt.config.3. */ +#define EQADC_CONV_CONFIG_SEL4 (11U << 0) /**< @brief Alt.config.4. */ +#define EQADC_CONV_CONFIG_SEL5 (12U << 0) /**< @brief Alt.config.5. */ +#define EQADC_CONV_CONFIG_SEL6 (13U << 0) /**< @brief Alt.config.6. */ +#define EQADC_CONV_CONFIG_SEL7 (14U << 0) /**< @brief Alt.config.7. */ +#define EQADC_CONV_CONFIG_SEL8 (15U << 0) /**< @brief Alt.config.8. */ +#define EQADC_CONV_CHANNEL_MASK (255U << 8) /**< @brief Channel number mask.*/ +#define EQADC_CONV_CHANNEL(n) ((n) << 8) /**< @brief Channel number. */ +#define EQADC_CONV_FMT_RJU (0U << 16) /**< @brief Unsigned samples. */ +#define EQADC_CONV_FMT_RJS (1U << 16) /**< @brief Signed samples. */ +#define EQADC_CONV_TSR (1U << 17) /**< @brief Time stamp request. */ +#define EQADC_CONV_LST_MASK (3U << 18) /**< @brief Sample time. */ +#define EQADC_CONV_LST_2 (0U << 18) /**< @brief 2 clock cycles. */ +#define EQADC_CONV_LST_8 (1U << 18) /**< @brief 8 clock cycles. */ +#define EQADC_CONV_LST_64 (2U << 18) /**< @brief 64 clock cycles. */ +#define EQADC_CONV_LST_128 (3U << 18) /**< @brief 128 clock cycles. */ +#define EQADC_CONV_MSG_MASK (15U << 20) /**< @brief Message mask. */ +#define EQADC_CONV_MSG_RFIFO(n) ((n) << 20) /**< @brief Result in RFIFO0..5.*/ +#define EQADC_CONV_MSG_NULL (6U << 20) /**< @brief Null message. */ +#define EQADC_CONV_CAL (1U << 24) /**< @brief Calibrated result. */ +#define EQADC_CONV_BN_MASK (1U << 25) /**< @brief Buffer number mask. */ +#define EQADC_CONV_BN_ADC0 (0U << 25) /**< @brief ADC0 selection. */ +#define EQADC_CONV_BN_ADC1 (1U << 25) /**< @brief ADC1 selection. */ +#define EQADC_CONV_REP (1U << 29) /**< @brief Repeat loop flag. */ +#define EQADC_CONV_PAUSE (1U << 30) /**< @brief Pause flag. */ +#define EQADC_CONV_EOQ (1U << 31) /**< @brief End of queue flag. */ +/** @} */ + +/** + * @name EQADC read/write commands + * @{ + */ +#define EQADC_RW_REG_ADDR_MASK (255U << 0) +#define EQADC_RW_REG_ADDR(n) ((n) << 0) +#define EQADC_RW_VALUE_MASK (0xFFFF << 8) +#define EQADC_RW_VALUE(n) ((n) << 8) +#define EQADC_RW_WRITE (0U << 24) +#define EQADC_RW_READ (1U << 24) +#define EQADC_RW_BN_ADC0 (0U << 25) +#define EQADC_RW_BN_ADC1 (1U << 25) +#define EQADC_RW_REP (1U << 29) +#define EQADC_RW_PAUSE (1U << 30) +#define EQADC_RW_EOQ (1U << 31) +/** @} */ + +/** + * @name ADC CR register definitions + * @{ + */ +#define ADC_CR_CLK_PS_MASK (31U << 0) +#define ADC_CR_CLK_PS(n) ((((n) >> 1) - 1) | ((n) & 1 ? ADC_CR_ODD_PS\ + : 0)) +#define ADC_CR_CLK_SEL (1U << 5) +#define ADC_CR_CLK_DTY (1U << 6) +#define ADC_CR_ODD_PS (1U << 7) +#define ADC_CR_TBSEL_MASK (3U << 8) +#define ADC_CR_TBSEL(n) ((n) << 8) +#define ADC_CR_EMUX (1U << 11) +#define ADC_CR_EN (1U << 15) +/** @} */ + +/** + * @name ADC AxCR registers definitions + * @{ + */ +#define ADC_ACR_PRE_GAIN_MASK (3U << 0) +#define ADC_ACR_PRE_GAIN_X1 (0U << 0) +#define ADC_ACR_PRE_GAIN_X2 (1U << 0) +#define ADC_ACR_PRE_GAIN_X4 (2U << 0) +#define ADC_ACR_RESSEL_MASK (3U << 6) +#define ADC_ACR_RESSEL_12BITS (0U << 6) +#define ADC_ACR_RESSEL_10BITS (1U << 6) +#define ADC_ACR_RESSEL_8BITS (2U << 6) +/** @} */ + +/** + * @name ADC PUDCRx registers definitions + * @{ + */ +#define ADC_PUDCR_NONE 0x0000 +#define ADC_PUDCR_UP_200K 0x1100 +#define ADC_PUDCR_UP_100K 0x1200 +#define ADC_PUDCR_UP_5K 0x1300 +#define ADC_PUDCR_DOWN_200K 0x2100 +#define ADC_PUDCR_DOWN_100K 0x2200 +#define ADC_PUDCR_DOWN_5K 0x2300 +#define ADC_PUDCR_UP_DOWN_200K 0x3100 +#define ADC_PUDCR_UP_DOWN_100K 0x3200 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADCD1 driver enable switch. + * @details If set to @p TRUE the support for ADC0 queue 0 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC0_Q0) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#endif + +/** + * @brief ADCD2 driver enable switch. + * @details If set to @p TRUE the support for ADC0 queue 1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC0_Q1) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#endif + +/** + * @brief ADCD3 driver enable switch. + * @details If set to @p TRUE the support for ADC0 queue 2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC0_Q2) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#endif + +/** + * @brief ADCD4 driver enable switch. + * @details If set to @p TRUE the support for ADC1 queue 3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC1_Q3) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#endif + +/** + * @brief ADCD5 driver enable switch. + * @details If set to @p TRUE the support for ADC1 queue 4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC1_Q4) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#endif + +/** + * @brief ADCD6 driver enable switch. + * @details If set to @p TRUE the support for ADC1 queue 5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ADC_USE_ADC1_Q5) || defined(__DOXYGEN__) +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#endif + +/** + * @brief EQADC CFIFO0 and RFIFO0 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC CFIFO1 and RFIFO1 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO1_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC CFIFO2 and RFIFO2 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC CFIFO3 and RFIFO3 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO3_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC CFIFO4 and RFIFO4 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO4_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC CFIFO5 and RFIFO5 DMA IRQ priority. + */ +#if !defined(SPC5_ADC0_FIFO5_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#endif + +/** + * @brief EQADC clock prescaler value. + */ +#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__) +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#endif + +/** + * @brief Initialization value for PUDCRx registers. + */ +#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EQADC +#error "EQADC not present in the selected device" +#endif + +#define SPC5_ADC_USE_ADC0 (SPC5_ADC_USE_ADC0_Q0 || \ + SPC5_ADC_USE_ADC0_Q1 || \ + SPC5_ADC_USE_ADC0_Q2) +#define SPC5_ADC_USE_ADC1 (SPC5_ADC_USE_ADC1_Q3 || \ + SPC5_ADC_USE_ADC1_Q4 || \ + SPC5_ADC_USE_ADC1_Q5) + +#if !SPC5_ADC_USE_ADC0 && !SPC5_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*! + * @brief FIFO unit numeric IDs. + */ +typedef enum { + ADC_FIFO_0 = 0, + ADC_FIFO_1 = 1, + ADC_FIFO_2 = 2, + ADC_FIFO_3 = 3, + ADC_FIFO_4 = 4, + ADC_FIFO_5 = 5 +} adcfifo_t; + +/** + * @brief ADC command data type. + */ +typedef uint32_t adccommand_t; + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief Initialization value for CFCR register. + */ + uint16_t cfcr; + /** + * @brief SIU ETISR.TSEL value for this queue; + */ + uint8_t tsel; + /** + * @brief SIU ISEL3.ETSEL value for this queue; + */ + uint8_t etsel; + /** + * @brief Number of command iterations stored in @p commands. + * @note The total number of array elements must be @p num_channels * + * @p num_iterations. + * @note This fields is the upper limit of the parameter @p n that can + * be passed to the functions @p adcConvert() and + * @p adcStartConversion(). + */ + uint32_t num_iterations; + /** + * @brief Pointer to an array of low level EQADC commands to be pushed + * into the CFIFO during a conversion. + */ + const adccommand_t *commands; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note Empty in this implementation can be ignored. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief CFIFO/RFIFO used by this instance. + */ + adcfifo_t fifo; + /** + * @brief EDMA channel used for the CFIFO. + */ + edma_channel_t cfifo_channel; + /** + * @brief EDMA channel used for the RFIFO. + */ + edma_channel_t rfifo_channel; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_ADC_USE_ADC0_Q0 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if SPC5_ADC_USE_ADC0_Q1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#if SPC5_ADC_USE_ADC0_Q2 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#if SPC5_ADC_USE_ADC1_Q3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD4; +#endif + +#if SPC5_ADC_USE_ADC1_Q4 && !defined(__DOXYGEN__) +extern ADCDriver ADCD5; +#endif + +#if SPC5_ADC_USE_ADC1_Q5 && !defined(__DOXYGEN__) +extern ADCDriver ADCD6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c new file mode 100644 index 000000000..3257927c6 --- /dev/null +++ b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c @@ -0,0 +1,296 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/ESCI_v1/serial_lld.c + * @brief SPC5xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A serial driver identifier. + */ +#if SPC5_USE_ESCIA || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief eSCI-B serial driver identifier. + */ +#if SPC5_USE_ESCIB || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + SD_MODE_NORMAL | SD_MODE_PARITY_NONE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief eSCI initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void esci_init(SerialDriver *sdp, const SerialConfig *config) { + volatile struct ESCI_tag *escip = sdp->escip; + uint8_t mode = config->sc_mode; + + escip->CR2.R = 0; /* MDIS off. */ + escip->CR1.R = 0; + escip->LCR.R = 0; + escip->CR1.B.SBR = SPC5_SYSCLK / (16 * config->sc_speed); + if (mode & SD_MODE_LOOPBACK) + escip->CR1.B.LOOPS = 1; + switch (mode & SD_MODE_PARITY_MASK) { + case SD_MODE_PARITY_ODD: + escip->CR1.B.PT = 1; + case SD_MODE_PARITY_EVEN: + escip->CR1.B.PE = 1; + escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ + default: + ; + } + escip->LPR.R = 0; + escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ + escip->CR2.R = 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ +} + +/** + * @brief eSCI de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] escip pointer to an eSCI I/O block + */ +static void esci_deinit(volatile struct ESCI_tag *escip) { + + escip->LPR.R = 0; + escip->SR.R = 0xFFFFFFFF; + escip->CR1.R = 0; + escip->CR2.R = 0x8000; /* MDIS on. */ +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr eSCI SR register value + */ +static void set_error(SerialDriver *sdp, uint32_t sr) { + flagsmask_t sts = 0; + + if (sr & 0x08000000) + sts |= SD_OVERRUN_ERROR; + if (sr & 0x04000000) + sts |= SD_NOISE_ERROR; + if (sr & 0x02000000) + sts |= SD_FRAMING_ERROR; + if (sr & 0x01000000) + sts |= SD_PARITY_ERROR; +/* if (sr & 0x00000000) + sts |= SD_BREAK_DETECTED;*/ + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void serve_interrupt(SerialDriver *sdp) { + volatile struct ESCI_tag *escip = sdp->escip; + + uint32_t sr = escip->SR.R; + escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ + if (sr & 0x0F000000) /* OR | NF | FE | PF. */ + set_error(sdp, sr); + if (sr & 0x20000000) { /* RDRF. */ + chSysLockFromIsr(); + sdIncomingDataI(sdp, escip->DR.B.D); + chSysUnlockFromIsr(); + } + if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + escip->CR1.B.TIE = 0; + } + else { + ESCI_A.SR.B.TDRE = 1; + escip->DR.R = (uint16_t)b; + } + chSysUnlockFromIsr(); + } +} + +#if SPC5_USE_ESCIA || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (ESCI_A.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + ESCI_A.SR.B.TDRE = 1; + ESCI_A.CR1.B.TIE = 1; + ESCI_A.DR.R = (uint16_t)b; + } + } +} +#endif + +#if SPC5_USE_ESCIB || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (ESCI_B.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + ESCI_B.SR.B.TDRE = 1; + ESCI_B.CR1.B.TIE = 1; + ESCI_B.DR.R = (uint16_t)b; + } + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_USE_ESCIA || defined(__DOXYGEN__) +#if !defined(SPC5_ESCIA_HANDLER) +#error "SPC5_ESCIA_HANDLER not defined" +#endif +/** + * @brief eSCI-A interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ESCIA_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_USE_ESCIB || defined(__DOXYGEN__) +#if !defined(SPC5_ESCIB_HANDLER) +#error "SPC5_ESCIB_HANDLER not defined" +#endif +/** + * @brief eSCI-B interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ESCIB_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if SPC5_USE_ESCIA + sdObjectInit(&SD1, NULL, notify1); + SD1.escip = &ESCI_A; + ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[SPC5_ESCIA_NUMBER].R = SPC5_ESCIA_PRIORITY; +#endif + +#if SPC5_USE_ESCIB + sdObjectInit(&SD2, NULL, notify2); + SD2.escip = &ESCI_B; + ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[SPC5_ESCIB_NUMBER].R = SPC5_ESCIB_PRIORITY; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + esci_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) + esci_deinit(sdp->escip); +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h new file mode 100644 index 000000000..b8b29fb99 --- /dev/null +++ b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h @@ -0,0 +1,170 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/ESCI_v1/serial_lld.c + * @brief SPC5xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Serial port modes + * @{ + */ +#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ + +#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ +#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A driver enable switch. + * @details If set to @p TRUE the support for eSCI-A is included. + * @note The default is @p TRUE. + */ +#if !defined(SPC5_USE_ESCIA) || defined(__DOXYGEN__) +#define SPC5_USE_ESCIA TRUE +#endif + +/** + * @brief eSCI-B driver enable switch. + * @details If set to @p TRUE the support for eSCI-B is included. + * @note The default is @p TRUE. + */ +#if !defined(SPC5_USE_ESCIB) || defined(__DOXYGEN__) +#define SPC5_USE_ESCIB TRUE +#endif + +/** + * @brief eSCI-A interrupt priority level setting. + */ +#if !defined(SPC_ESCIA_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_ESCIA_PRIORITY 8 +#endif + +/** + * @brief eSCI-B interrupt priority level setting. + */ +#if !defined(SPC_ESCIB_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_ESCIB_PRIORITY 8 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPC5_USE_ESCIA && !SPC5_HAS_ESCIA +#error "eSCI-A not present in the selected device" +#endif + +#if SPC5_USE_ESCIB && !SPC5_HAS_ESCIB +#error "eSCI-B not present in the selected device" +#endif + +#if !SPC5_USE_ESCIA && !SPC5_USE_ESCIB +#error "SERIAL driver activated but no eSCI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the volatile eSCI registers block.*/ \ + volatile struct ESCI_tag *escip; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_USE_ESCIA && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if SPC5_USE_ESCIB && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c new file mode 100644 index 000000000..b20cc1334 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c @@ -0,0 +1,1667 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexCAN_v1/can_lld.c + * @brief SPC5xx CAN subsystem low level driver source. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief CAN1 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/** @brief CAN2 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__) +CANDriver CAND2; +#endif + +/** @brief CAN3 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__) +CANDriver CAND3; +#endif + +/** @brief CAN4 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__) +CANDriver CAND4; +#endif + +/** @brief CAN5 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__) +CANDriver CAND5; +#endif + +/** @brief CAN6 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__) +CANDriver CAND6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Common TX ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_tx_handler(CANDriver *canp) { + uint32_t iflag1, iflag2; + + iflag1 = canp->flexcan->IFRL.R; + iflag2 = canp->flexcan->IFRH.R; + /* No more events until a message is transmitted.*/ + canp->flexcan->IFRL.R |= iflag1 & 0xFFFFFF00; + canp->flexcan->IFRH.R |= canp->flexcan->IFRH.R & 0xFFFFFFFF; + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->txsem) < 0) + chSemSignalI(&canp->txsem); + +#if SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 32) + if(&CAND1 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 64) + if(&CAND1 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 32) + if(&CAND2 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 64) + if(&CAND2 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 32) + if(&CAND3 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 64) + if(&CAND3 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 32) + if(&CAND4 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 64) + if(&CAND4 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 32) + if(&CAND5 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 64) + if(&CAND5 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 32) + if(&CAND6 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + } +#elif SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 64) + if(&CAND6 == canp) { + chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00)); + } +#endif + + chSysUnlockFromIsr(); +} + +/** + * @brief Common RX ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_rx_handler(CANDriver *canp) { + uint32_t iflag1; + + iflag1 = canp->flexcan->IFRL.R; + if ((iflag1 & 0x000000FF) != 0) { + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->rxsem) < 0) + chSemSignalI(&canp->rxsem); + chEvtBroadcastFlagsI(&canp->rxfull_event, iflag1 & 0x000000FF); + chSysUnlockFromIsr(); + + /* Release the mailbox.*/ + canp->flexcan->IFRL.R |= iflag1 & 0x000000FF; + } +} + +/** + * @brief Common error ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_err_handler(CANDriver *canp) { + + uint32_t esr = canp->flexcan->ESR.R; + flagsmask_t flags = 0; + + /* Error event.*/ + if ((esr & CAN_ESR_TWRN_INT) || (esr & CAN_ESR_RWRN_INT)) { + canp->flexcan->ESR.B.TXWRN = 1U; + canp->flexcan->ESR.B.RXWRN = 1U; + flags |= CAN_LIMIT_WARNING; + } + + if (esr & CAN_ESR_BOFF_INT) { + canp->flexcan->ESR.B.BOFFINT = 1U; + flags |= CAN_BUS_OFF_ERROR; + } + + if (esr & CAN_ESR_ERR_INT) { + canp->flexcan->ESR.B.ERRINT = 1U; + flags |= CAN_FRAMING_ERROR; + } + chSysLockFromIsr(); + chEvtBroadcastFlagsI(&canp->error_event, flags); + chSysUnlockFromIsr(); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__) +/** + * @brief CAN1 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER) { + + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN0_MB == 64) +/** + * @brief CAN1 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN0 */ + +#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__) +/** + * @brief CAN2 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN1_MB == 64) +/** + * @brief CAN2 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN2 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN2 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN1 */ + +#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__) +/** + * @brief CAN3 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN2_MB == 64) +/** + * @brief CAN3 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN3 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN3 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN2 */ + +#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__) +/** + * @brief CAN4 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN3_MB == 64) +/** + * @brief CAN4 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN4 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN4 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN3 */ + +#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__) +/** + * @brief CAN5 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN4_MB == 64) +/** + * @brief CAN5 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN5 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN5 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN4 */ + +#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__) +/** + * @brief CAN6 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN5_MB == 64) +/** + * @brief CAN6 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN6 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN6 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN5 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if SPC5_CAN_USE_FLEXCAN0 + /* Driver initialization.*/ + canObjectInit(&CAND1); + CAND1.flexcan = &SPC5_FLEXCAN_0; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + /* Driver initialization.*/ + canObjectInit(&CAND2); + CAND2.flexcan = &SPC5_FLEXCAN_1; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + /* Driver initialization.*/ + canObjectInit(&CAND3); + CAND3.flexcan = &SPC5_FLEXCAN_2; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + /* Driver initialization.*/ + canObjectInit(&CAND4); + CAND4.flexcan = &SPC5_FLEXCAN_3; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + /* Driver initialization.*/ + canObjectInit(&CAND5); + CAND5.flexcan = &SPC5_FLEXCAN_4; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + /* Driver initialization.*/ + canObjectInit(&CAND6); + CAND6.flexcan = &SPC5_FLEXCAN_5; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; +#endif +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + uint8_t mb_index = 0, id = 0; + + /* Clock activation.*/ +#if SPC5_CAN_USE_FLEXCAN0 + /* Set peripheral clock mode.*/ + if(&CAND1 == canp) + SPC5_FLEXCAN0_ENABLE_CLOCK(); +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + /* Set peripheral clock mode.*/ + if(&CAND2 == canp) + SPC5_FLEXCAN1_ENABLE_CLOCK(); +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + /* Set peripheral clock mode.*/ + if(&CAND3 == canp) + SPC5_FLEXCAN2_ENABLE_CLOCK(); +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + /* Set peripheral clock mode.*/ + if(&CAND4 == canp) + SPC5_FLEXCAN3_ENABLE_CLOCK(); +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + /* Set peripheral clock mode.*/ + if(&CAND5 == canp) + SPC5_FLEXCAN4_ENABLE_CLOCK(); +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + /* Set peripheral clock mode.*/ + if(&CAND6 == canp) + SPC5_FLEXCAN5_ENABLE_CLOCK(); +#endif + + /* Entering initialization mode. */ + canp->state = CAN_STARTING; + canp->flexcan->CR.R |= CAN_CTRL_CLK_SRC; + canp->flexcan->MCR.R &= ~CAN_MCR_MDIS; + + /* + * Individual filtering per MB, disable frame self reception, + * disable the FIFO, enable SuperVisor mode. + */ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN0_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN1_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN2_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN3_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN4_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN5_MB - 1); +#endif + + canp->flexcan->CR.R |= CAN_CTRL_TSYN | CAN_CTRL_RJW(3); + + /* TX MB initialization.*/ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN0_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN1_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN2_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN3_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN4_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN5_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif + + /* Unlock Message buffers.*/ + (void) canp->flexcan->TIMER.R; + + /* MCR initialization.*/ + canp->flexcan->MCR.R |= canp->config->mcr; + + /* CTRL initialization.*/ + canp->flexcan->CR.R |= canp->config->ctrl; + + /* Interrupt sources initialization.*/ + canp->flexcan->MCR.R |= CAN_MCR_WRN_EN; + + canp->flexcan->CR.R |= CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK | + CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK; + +#if !SPC5_CAN_USE_FILTERS + /* RX MB initialization.*/ + for(mb_index = 0; mb_index < CAN_RX_MAILBOXES; mb_index++) { + canp->flexcan->BUF[mb_index].CS.B.CODE = 0U; + if(mb_index < 4) { + canp->flexcan->BUF[mb_index].CS.B.IDE = 0U; + } + else { + canp->flexcan->BUF[mb_index].CS.B.IDE = 1U; + } + canp->flexcan->BUF[mb_index].ID.R = 0U; + canp->flexcan->BUF[mb_index].CS.B.CODE = 4U; + } + + /* Receive all.*/ + canp->flexcan->RXGMASK.R = 0x00000000; +#else + for (id = 0; id < CAN_RX_MAILBOXES; id++) { + canp->flexcan->BUF[id].CS.B.CODE = 0U; + if (canp->config->RxFilter[id].scale) { + canp->flexcan->BUF[id].CS.B.IDE = 1U; + canp->flexcan->BUF[id].ID.R = canp->config->RxFilter[id].register1; + } + else { + canp->flexcan->BUF[id].CS.B.IDE = 0U; + canp->flexcan->BUF[id].ID.B.STD_ID = canp->config->RxFilter[id].register1; + canp->flexcan->BUF[id].ID.B.EXT_ID = 0U; + } + /* RX MB initialization.*/ + canp->flexcan->BUF[id].CS.B.CODE = 4U; + } + canp->flexcan->RXGMASK.R = 0x0FFFFFFF; +#endif + + /* Enable MBs interrupts.*/ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + if(SPC5_FLEXCAN0_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN0_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + if(SPC5_FLEXCAN1_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN1_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + if(SPC5_FLEXCAN2_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN2_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + if(SPC5_FLEXCAN3_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN3_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + if(SPC5_FLEXCAN4_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN4_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + if(SPC5_FLEXCAN5_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN5_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif + + /* CAN BUS synchronization.*/ + canp->flexcan->MCR.B.HALT = 0; +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { + + /* Disable Interrupt sources.*/ + canp->flexcan->MCR.R &= ~CAN_MCR_WRN_EN; + canp->flexcan->CR.R &= ~(CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK | + CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK); + canp->flexcan->IMRL.R = 0x00000000; + + canp->flexcan->MCR.R &= ~CAN_MCR_MDIS; + +#if SPC5_CAN_USE_FLEXCAN0 + /* Set peripheral clock mode.*/ + if(&CAND1 == canp) + SPC5_FLEXCAN0_DISABLE_CLOCK(); + +#endif +#if SPC5_CAN_USE_FLEXCAN1 + /* Set peripheral clock mode.*/ + if(&CAND2 == canp) + SPC5_FLEXCAN1_DISABLE_CLOCK(); +#endif +#if SPC5_CAN_USE_FLEXCAN2 + /* Set peripheral clock mode.*/ + if(&CAND3 == canp) + SPC5_FLEXCAN2_DISABLE_CLOCK(); +#endif +#if SPC5_CAN_USE_FLEXCAN3 + /* Set peripheral clock mode.*/ + if(&CAND4 == canp) + SPC5_FLEXCAN3_DISABLE_CLOCK(); +#endif +#if SPC5_CAN_USE_FLEXCAN4 + /* Set peripheral clock mode.*/ + if(&CAND5 == canp) + SPC5_FLEXCAN4_DISABLE_CLOCK(); +#endif +#if SPC5_CAN_USE_FLEXCAN5 + /* Set peripheral clock mode.*/ + if(&CAND6 == canp) + SPC5_FLEXCAN5_DISABLE_CLOCK(); +#endif + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + + uint8_t mbid = 0; + + if(mailbox == CAN_ANY_MAILBOX) { +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif + } + else { + return canp->flexcan->BUF[mailbox + 7].CS.B.CODE == 0x08; + } + return FALSE; +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp) { + + CAN_TxMailBox_TypeDef *tmbp = NULL; + uint8_t mbid = 0; + + /* Pointer to a free transmission mailbox.*/ + if (mailbox == CAN_ANY_MAILBOX) { +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif + } + else { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mailbox + 7]; + } + + /* Preparing the message.*/ + if (ctfp->IDE) { + tmbp->CS.B.IDE = 1U; + tmbp->CS.B.RTR = 0U; + tmbp->ID.R = ctfp->EID; + } + else { + tmbp->CS.B.IDE = 0U; + tmbp->CS.B.RTR = 0U; + tmbp->ID.R = ctfp->SID << 18; + } + tmbp->CS.B.LENGTH = ctfp->LENGTH; + tmbp->DATA[0] = ctfp->data32[0]; + tmbp->DATA[1] = ctfp->data32[1]; + tmbp->CS.B.CODE = 0x0C; +} + +/** + * + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ + +bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + + uint8_t mbid = 0; + bool_t mb_status = FALSE; + + switch (mailbox) { + case CAN_ANY_MAILBOX: + for (mbid = 0; mbid < CAN_RX_MAILBOXES; mbid++) { + if(canp->flexcan->BUF[mbid].CS.B.CODE == 2U) { + mb_status = TRUE; + } + } + return mb_status; + case 1: + return (canp->flexcan->BUF[0].CS.B.CODE == 2U); + case 2: + return (canp->flexcan->BUF[1].CS.B.CODE == 2U); + case 3: + return (canp->flexcan->BUF[2].CS.B.CODE == 2U); + case 4: + return (canp->flexcan->BUF[3].CS.B.CODE == 2U); + case 5: + return (canp->flexcan->BUF[4].CS.B.CODE == 2U); + case 6: + return (canp->flexcan->BUF[5].CS.B.CODE == 2U); + case 7: + return (canp->flexcan->BUF[6].CS.B.CODE == 2U); + case 8: + return (canp->flexcan->BUF[7].CS.B.CODE == 2U); + default: + return FALSE; + } +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp) { + + uint32_t mbid = 0, index = 0; + + if(mailbox != CAN_ANY_MAILBOX) { + mbid = mailbox; + } + else { + for (index = 0; index < CAN_RX_MAILBOXES; index++) { + if(canp->flexcan->BUF[index].CS.B.CODE == 2U) { + mbid = index; + break; + } + } + } + + /* Lock the RX MB.*/ + (void) canp->flexcan->BUF[mbid].CS.B.CODE; + + /* Fetches the message.*/ + crfp->data32[0] = canp->flexcan->BUF[mbid].DATA.W[0]; + crfp->data32[1] = canp->flexcan->BUF[mbid].DATA.W[1]; + + /* Decodes the various fields in the RX frame.*/ + crfp->RTR = canp->flexcan->BUF[mbid].CS.B.RTR; + crfp->IDE = canp->flexcan->BUF[mbid].CS.B.IDE; + if (crfp->IDE) + crfp->EID = canp->flexcan->BUF[mbid].ID.B.EXT_ID; + else + crfp->SID = canp->flexcan->BUF[mbid].ID.B.STD_ID; + crfp->LENGTH = canp->flexcan->BUF[mbid].CS.B.LENGTH; + crfp->TIME = canp->flexcan->BUF[mbid].CS.B.TIMESTAMP; + + /* Unlock the RX MB.*/ + (void) canp->flexcan->TIMER.R; + + /* Reconfigure the RX MB in empty status.*/ + canp->flexcan->BUF[mbid].CS.B.CODE = 4U; +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + + /*canp->can->MCR |= CAN_MCR_SLEEP;*/ +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + + /*canp->can->MCR &= ~CAN_MCR_SLEEP;*/ +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h new file mode 100644 index 000000000..ad67c97da --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h @@ -0,0 +1,520 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexCAN_v1/can_lld.h + * @brief SPC5xx CAN subsystem low level driver header. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +#include "spc5_flexcan.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with an automatic wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP FALSE + +/** + * @brief This implementation supports 24 transmit mailboxes. + */ +#define CAN_TX_MAILBOXES 24 + +/** + * @brief This implementation supports one FIFO receive mailbox. + */ +#define CAN_RX_MAILBOXES 8 + +/** + * @brief This implementation supports eight FIFO receive filters. + */ +#define SPC5_CAN_MAX_FILTERS 8 + +/** + * @brief Enable filters. + */ +#define SPC5_CAN_FILTER_ON 1 + +/** + * @brief Disable filters. + */ +#define SPC5_CAN_FILTER_OFF 0 +/** + * @name CAN registers helper macros + * @{ + */ +#define CAN_MCR_MAXMB(n) (n) +#define CAN_MCR_AEN (1 << 12) +#define CAN_MCR_LPRIO_EN (1 << 13) +#define CAN_MCR_BCC (1 << 16) +#define CAN_MCR_SRX_DIS (1 << 17) +#define CAN_MCR_LPM_ACK (1 << 20) +#define CAN_MCR_WRN_EN (1 << 21) +#define CAN_MCR_SUPV (1 << 23) +#define CAN_MCR_FRZ_ACK (1 << 24) +#define CAN_MCR_WAK_MSK (1 << 26) +#define CAN_MCR_NOT_RDY (1 << 27) +#define CAN_MCR_HALT (1 << 28) +#define CAN_MCR_FEN (1 << 29) +#define CAN_MCR_FRZ (1 << 30) +#define CAN_MCR_MDIS (1 << 31) + +#define CAN_CTRL_PROPSEG(n) (n) +#define CAN_CTRL_LOM (1 << 3) +#define CAN_CTRL_TSYN (1 << 5) +#define CAN_CTRL_BOFF_REC (1 << 6) +#define CAN_CTRL_SMP (1 << 7) +#define CAN_CTRL_RWRN_MSK (1 << 10) +#define CAN_CTRL_TWRN_MSK (1 << 11) +#define CAN_CTRL_LPB (1 << 12) +#define CAN_CTRL_CLK_SRC (1 << 13) +#define CAN_CTRL_ERR_MSK (1 << 14) +#define CAN_CTRL_BOFF_MSK (1 << 15) +#define CAN_CTRL_PSEG2(n) ((n) << 16) +#define CAN_CTRL_PSEG1(n) ((n) << 19) +#define CAN_CTRL_RJW(n) ((n) << 22) +#define CAN_CTRL_PRESDIV(n) ((n) << 24) + +#define CAN_IDE_STD 0 /**< @brief Standard id. */ +#define CAN_IDE_EXT 1 /**< @brief Extended id. */ + +#define CAN_RTR_DATA 0 /**< @brief Data frame. */ +#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ + +#define CAN_ESR_ERR_INT (1 << 1) +#define CAN_ESR_BOFF_INT (1 << 2) +#define CAN_ESR_TWRN_INT (1 << 14) +#define CAN_ESR_RWRN_INT (1 << 15) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for CAN1 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN0) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN0 FALSE +#endif + +/** + * @brief CAN2 driver enable switch. + * @details If set to @p TRUE the support for CAN2 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN1) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#endif + +/** + * @brief CAN3 driver enable switch. + * @details If set to @p TRUE the support for CAN3 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN2) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN2 FALSE +#endif + +/** + * @brief CAN4 driver enable switch. + * @details If set to @p TRUE the support for CAN4 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN3) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN3 FALSE +#endif + +/** + * @brief CAN5 driver enable switch. + * @details If set to @p TRUE the support for CAN5 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN4) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN4 FALSE +#endif + +/** + * @brief CAN6 driver enable switch. + * @details If set to @p TRUE the support for CAN6 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN5) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN5 FALSE +#endif + +/** + * @brief CAN1 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN2 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN3 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN4 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN3_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN5 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN4_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN6 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN5_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN filters enable setting. + */ +#if !defined(SPC5_CAN_USE_FILTERS) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FILTERS FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 && !SPC5_HAS_FLEXCAN0 +#error "CAN1 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN1 && !SPC5_HAS_FLEXCAN1 +#error "CAN2 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN2 && !SPC5_HAS_FLEXCAN2 +#error "CAN3 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN3 && !SPC5_HAS_FLEXCAN3 +#error "CAN4 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN4 && !SPC5_HAS_FLEXCAN4 +#error "CAN5 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN5 && !SPC5_HAS_FLEXCAN5 +#error "CAN6 not present in the selected device" +#endif + +#if !SPC5_CAN_USE_FLEXCAN0 && !SPC5_CAN_USE_FLEXCAN1 \ + && !SPC5_CAN_USE_FLEXCAN2 && !SPC5_CAN_USE_FLEXCAN3 \ + && !SPC5_CAN_USE_FLEXCAN4 && !SPC5_CAN_USE_FLEXCAN5 +#error "CAN driver activated but no CAN peripheral assigned" +#endif + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a transmission mailbox index. + */ +typedef uint32_t canmbx_t; + +/** + * @brief CAN TX MB structure. + */ +typedef struct { + union { + vuint32_t R; + struct { + vuint8_t:4; + vuint8_t CODE:4; + vuint8_t:1; + vuint8_t SRR:1; + vuint8_t IDE:1; + vuint8_t RTR:1; + vuint8_t LENGTH:4; + vuint16_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint8_t PRIO:3; + vuint32_t ID:29; + } B; + } ID; + vuint32_t DATA[2]; /* Data buffer in words (32 bits) */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t LENGTH:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint16_t TIME; /**< @brief Time stamp. */ + }; + struct { + uint8_t LENGTH:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Refer to the SPC5 reference manual for info about filters. + */ +typedef struct { + /** + * @brief Filter scale. + * @note This bit represents the EXT bit associated to this + * filter (0=standard ID mode, 1=extended ID mode). + */ + uint32_t scale:1; + /** + * @brief Filter register (identifier). + */ + uint32_t register1; +} CANFilter; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CAN MCR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t mcr; + /** + * @brief CAN CTRL register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t ctrl; +#if SPC5_CAN_USE_FILTERS + /** + * @brief CAN filters structure. + */ + CANFilter RxFilter[CAN_RX_MAILBOXES]; +#endif +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p chReceive() when listening to this event. + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + * @note The flags associated to the listeners will indicate which + * receive mailboxes become non-empty. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the listeners will indicate which + * transmit mailboxes become empty. + * + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + * @note The flags associated to the listeners will indicate the + * error(s) that have occurred. + */ + EventSource error_event; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CAN registers. + */ + volatile struct spc5_flexcan *flexcan; +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 && !defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#if SPC5_CAN_USE_FLEXCAN1 && !defined(__DOXYGEN__) +extern CANDriver CAND2; +#endif + +#if SPC5_CAN_USE_FLEXCAN2 && !defined(__DOXYGEN__) +extern CANDriver CAND3; +#endif + +#if SPC5_CAN_USE_FLEXCAN3 && !defined(__DOXYGEN__) +extern CANDriver CAND4; +#endif + +#if SPC5_CAN_USE_FLEXCAN4 && !defined(__DOXYGEN__) +extern CANDriver CAND5; +#endif + +#if SPC5_CAN_USE_FLEXCAN5 && !defined(__DOXYGEN__) +extern CANDriver CAND6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_is_tx_empty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *crfp); + bool_t can_lld_is_rx_nonempty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h new file mode 100644 index 000000000..580f78827 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h @@ -0,0 +1,442 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file FlexCAN_v1/spc5_flexcan.h + * @brief SPC5xx FlexCAN header file. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _SPC5_FLEXCAN_H_ +#define _SPC5_FLEXCAN_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief SPC5 FlexCAN registers block. + * @note Redefined from the SPC5 headers because the non uniform + * declaration of the SubModules registers among the various + * sub-families. + */ +struct FLEXCAN_BUFFER_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + +}; /* end of FLEXCAN_BUF_t */ + +struct FLEXCAN_RXFIFO_BUFFER_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + +}; /* end of FLEXCAN_RXFIFO_t */ + +struct spc5_flexcan { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAKMSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t SLFWAK:1; + vuint32_t WRNEN:1; + vuint32_t LPMACK:1; + vuint32_t WAKSRC:1; + vuint32_t:1; + vuint32_t SRXDIS:1; + vuint32_t BCC:1; + vuint32_t:2; + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t:1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */ + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUFFER_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_BUFFER_t RXFIFO; + struct FLEXCAN_BUFFER_t BUF[56];*/ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of FLEXCAN_tag */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name FlexCAN units references + * @{ + */ +#if SPC5_HAS_FLEXCAN0 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_0 (*(volatile struct spc5_flexcan *)0xFFFC0000UL) +#endif + +#if SPC5_HAS_FLEXCAN1 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_1 (*(volatile struct spc5_flexcan *)0xFFFC4000UL) +#endif + +#if SPC5_HAS_FLEXCAN2 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_2 (*(volatile struct spc5_flexcan *)0xFFFC8000UL) +#endif + +#if SPC5_HAS_FLEXCAN3 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_3 (*(volatile struct spc5_flexcan *)0xFFFCC000UL) +#endif + +#if SPC5_HAS_FLEXCAN4 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_4 (*(volatile struct spc5_flexcan *)0xFFFD0000UL) +#endif + +#if SPC5_HAS_FLEXCAN5 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_5 (*(volatile struct spc5_flexcan *)0xFFFD4000UL) +#endif +/** @} */ + +#endif /* _SPC5_FLEXCAN_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c new file mode 100644 index 000000000..7a92b1044 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c @@ -0,0 +1,1776 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexPWM_v1/pwm_lld.c + * @brief SPC5xx low level PWM driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. + */ +#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TIM2 when enabled. + */ +#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TIM3 when enabled. + */ +#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TIM4 when enabled. + */ +#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the timer TIM5 when enabled. + */ +#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD6 driver identifier. + * @note The driver PWMD6 allocates the timer TIM6 when enabled. + */ +#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__) +PWMDriver PWMD6; +#endif + +/** + * @brief PWMD7 driver identifier. + * @note The driver PWMD7 allocates the timer TIM7 when enabled. + */ +#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__) +PWMDriver PWMD7; +#endif + +/** + * @brief PWMD8 driver identifier. + * @note The driver PWMD8 allocates the timer TIM8 when enabled. + */ +#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__) +PWMDriver PWMD8; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Number of active FlexPWM0 submodules. + */ +static uint32_t flexpwm_active_submodules0; + +/** + * @brief Number of active FlexPWM1 submodules. + */ +static uint32_t flexpwm_active_submodules1; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Configures and activates the PWM peripheral submodule. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] sid PWM submodule identifier + * + * @notapi + */ +void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) { + pwmcnt_t pwmperiod; + uint32_t psc; + + /* Clears Status Register.*/ + pwmp->flexpwmp->SUB[sid].STS.R = 0xFFFF; + + /* Clears LDOK and initializes the registers.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid; + + /* Setting PWM clock frequency and submodule prescaler.*/ + psc = SPC5_FLEXPWM0_CLK / pwmp->config->frequency; + + chDbgAssert((psc <= 0xFFFF) && + (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) && + ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) || + (psc == 16) || (psc == 32) || + (psc == 64) || (psc == 128)), + "pwm_lld_start_submodule(), #1", "invalid frequency"); + + switch (psc) { + case 1: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_1; + break; + case 2: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_2; + break; + case 4: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_4; + break; + case 8: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_8; + break; + case 16: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_16; + break; + case 32: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_32; + break; + case 64: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_64; + break; + case 128: + pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_128; + break; + } + + /* Disables PWM FAULT function. */ + pwmp->flexpwmp->SUB[sid].DISMAP.R = 0; + pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 1U; + + /* Sets PWM period.*/ + pwmperiod = pwmp->period; + pwmp->flexpwmp->SUB[sid].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[sid].VAL[0].R = 0; + pwmp->flexpwmp->SUB[sid].VAL[1].R = pwmperiod / 2; + + /* Sets the submodule channels.*/ + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting reloads.*/ + pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 0; + pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 1; + + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + case PWM_ALIGN_CENTER: + /* Setting reloads.*/ + pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 1; + pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 0; + break; + default: + ; + } + + /* Polarities setup.*/ + switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1; + + /* Enables CHA mask and CHA.*/ + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid; + + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 0; + + /* Enables CHA mask and CHA.*/ + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid; + + break; + case PWM_OUTPUT_DISABLED: + /* Enables CHA mask.*/ + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + + break; + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1; + + /* Enables CHB mask and CHB.*/ + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid; + + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 0; + + /* Enables CHB mask and CHB.*/ + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid; + + break; + case PWM_OUTPUT_DISABLED: + /* Enables CHB mask.*/ + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + + break; + default: + ; + } + + /* Complementary output setup.*/ + switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW, + "pwm_lld_start_submodule(), #2", + "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW"); + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1; + pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0; + pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid; + break; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH, + "pwm_lld_start_submodule(), #3", + "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH"); + pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0; + pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid; + break; + default: + ; + } + + switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW, + "pwm_lld_start_submodule(), #4", + "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW"); + pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0; + pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (1U << sid); + pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1; + pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid; + break; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH, + "pwm_lld_start_submodule(), #5", + "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH"); + pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0; + pwmp->flexpwmp->MCTRL.B.IPOL |= 1U << sid; + pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid; + break; + default: + ; + } + + /* Sets the INIT and MASK registers.*/ + pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U; + + /* Updates SMOD registers and starts SMOD.*/ + pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid; + pwmp->flexpwmp->MCTRL.B.RUN |= 1U << sid; +} + +/** + * @brief Enables a PWM channel of a submodule. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * @param[in] sid PWM submodule id + * + * @notapi + */ +void pwm_lld_enable_submodule_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width, uint8_t sid) { + pwmcnt_t pwmperiod; + int16_t nwidth; + pwmperiod = pwmp->period; + nwidth = width - (pwmperiod / 2); + + /* Clears LDOK.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid; + + /* Active the width interrupt.*/ + if (channel == 0) { + if (pwmp->config->channels[0].callback != NULL) { + if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 0) { + pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x08; + } + } + + /* Sets the channel width.*/ + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + if (nwidth >= 0) + pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth; + else + pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U; + break; + case PWM_ALIGN_CENTER: + pwmp->flexpwmp->SUB[sid].VAL[3].R = width / 2; + pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(width / 2) + 1U; + break; + default: + ; + } + + /* Removes the channel mask if it is necessary.*/ + if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) == 1) + pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid); + + if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) { + pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid); + } + } + /* Active the width interrupt.*/ + else if (channel == 1) { + if (pwmp->config->channels[1].callback != NULL) { + if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 0) { + pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x20; + } + } + /* Sets the channel width.*/ + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + if (nwidth >= 0) + pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth; + else + pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U; + break; + case PWM_ALIGN_CENTER: + pwmp->flexpwmp->SUB[sid].VAL[5].R = width / 2; + pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(width / 2) + 1U; + break; + default: + ; + } + + /* Removes the channel mask if it is necessary.*/ + if ((pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1) + pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid); + + if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) { + pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid); + } + } + + /* Active the periodic interrupt.*/ + if (pwmp->flexpwmp->SUB[sid].INTEN.B.RIE != 1U) { + if (pwmp->config->callback != NULL) { + pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 1; + } + } + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U; + + /* Forces reload of the VALUE registers.*/ + pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid; +} + +/** + * @brief Disables a PWM channel of a submodule. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] sid PWM submodule id + * + * @notapi + */ +void pwm_lld_disable_submodule_channel(PWMDriver *pwmp, + pwmchannel_t channel, + uint8_t sid) { + + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid; + + /* Disable the width interrupt.*/ + if (channel == 0) { + if (pwmp->config->channels[0].callback != NULL) { + if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 1) { + pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x37; + } + } + + /* Active the channel mask.*/ + if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) { + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + } + else + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + } + /* Disable the width interrupt.*/ + else if (channel == 1) { + if (pwmp->config->channels[1].callback != NULL) { + if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 1) { + pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x1F; + } + } + + /* Active the channel mask.*/ + if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) { + pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid; + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + } + else + pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid; + } + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U; + + /* Disable RIE interrupt to prevent reload interrupt.*/ + if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) && + (pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1) { + pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 0; + + /* Clear the reload flag.*/ + pwmp->flexpwmp->SUB[sid].STS.B.RF = 1U; + } + + pwmp->flexpwmp->MCTRL.B.LDOK |= (1U << sid); +} + +/** + * @brief Common SMOD0...SMOD7 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint16_t sr; + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[0].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[1].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[2].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R; + if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08; + pwmp->config->channels[0].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20; + pwmp->config->channels[1].callback(pwmp); + } + if ((sr & SPC5_FLEXPWM_STS_RF) != 0) { + pwmp->flexpwmp->SUB[3].STS.B.RF = 1U; + pwmp->config->callback(pwmp); + } + } +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM0_RF0_HANDLER) +#error "SPC5_FLEXPWM0_RF0_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD0 RF0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM0_COF0_HANDLER) +#error "SPC5_FLEXPWM0_COF0_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD0 COF0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM0_RF1_HANDLER) +#error "SPC5_FLEXPWM0_RF1_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD1 RF1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM0_COF1_HANDLER) +#error "SPC5_FLEXPWM0_COF1_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD1 COF1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM0_RF2_HANDLER) +#error "SPC5_FLEXPWM0_RF2_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD2 RF2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM0_COF2_HANDLER) +#error "SPC5_FLEXPWM0_COF2_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD2 COF2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM0_RF3_HANDLER) +#error "SPC5_FLEXPWM0_RF3_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD1 RF3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM0_COF3_HANDLER) +#error "SPC5_FLEXPWM0_COF3_HANDLER not defined" +#endif +/** + * @brief FlexPWM0-SMOD1 COF3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM1_RF0_HANDLER) +#error "SPC5_FLEXPWM0_RF1_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD0 RF0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM1_COF0_HANDLER) +#error "SPC5_FLEXPWM1_COF0_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD0 COF0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM1_RF1_HANDLER) +#error "SPC5_FLEXPWM1_RF1_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD1 RF1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD6); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM1_COF1_HANDLER) +#error "SPC5_FLEXPWM1_COF1_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD1 COF1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD6); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM1_RF2_HANDLER) +#error "SPC5_FLEXPWM1_RF2_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD2 RF2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD7); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM1_COF2_HANDLER) +#error "SPC5_FLEXPWM1_COF2_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD2 COF2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD7); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__) +#if !defined(SPC5_FLEXPWM1_RF3_HANDLER) +#error "SPC5_FLEXPWM1_RF3_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD3 RF3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD8); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_FLEXPWM1_COF3_HANDLER) +#error "SPC5_FLEXPWM1_COF3_HANDLER not defined" +#endif +/** + * @brief FlexPWM1-SMOD3 COF3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD8); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + + /* FlexPWM initially all not in use.*/ + flexpwm_active_submodules0 = 0; + flexpwm_active_submodules1 = 0; + +#if (SPC5_PWM_USE_SMOD0) + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.flexpwmp = &SPC5_FLEXPWM_0; + INTC.PSR[SPC5_FLEXPWM0_RF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_COF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_CAF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD1) + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.flexpwmp = &SPC5_FLEXPWM_0; + INTC.PSR[SPC5_FLEXPWM0_RF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_COF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_CAF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD2) + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.flexpwmp = &SPC5_FLEXPWM_0; + INTC.PSR[SPC5_FLEXPWM0_RF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_COF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_CAF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD3) + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.flexpwmp = &SPC5_FLEXPWM_0; + INTC.PSR[SPC5_FLEXPWM0_RF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_COF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_CAF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY; + INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD4) + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.flexpwmp = &SPC5_FLEXPWM_1; + INTC.PSR[SPC5_FLEXPWM1_RF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_COF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_CAF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD5) + /* Driver initialization.*/ + pwmObjectInit(&PWMD6); + PWMD6.flexpwmp = &SPC5_FLEXPWM_1; + INTC.PSR[SPC5_FLEXPWM1_RF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_COF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_CAF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD6) + /* Driver initialization.*/ + pwmObjectInit(&PWMD7); + PWMD7.flexpwmp = &SPC5_FLEXPWM_1; + INTC.PSR[SPC5_FLEXPWM1_RF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_COF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_CAF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY; +#endif + +#if (SPC5_PWM_USE_SMOD7) + /* Driver initialization.*/ + pwmObjectInit(&PWMD8); + PWMD8.flexpwmp = &SPC5_FLEXPWM_1; + INTC.PSR[SPC5_FLEXPWM1_RF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_COF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_CAF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY; + INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + chDbgAssert(flexpwm_active_submodules0 < 5, + "pwm_lld_start(), #1", "too many submodules"); + chDbgAssert(flexpwm_active_submodules1 < 5, + "pwm_lld_start(), #2", "too many submodules"); + + if (pwmp->state == PWM_STOP) { +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + flexpwm_active_submodules0++; + } +#endif /* SPC5_PWM_USE_SMOD0 */ + +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + flexpwm_active_submodules0++; + } +#endif /* SPC5_PWM_USE_SMOD1 */ + +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + flexpwm_active_submodules0++; + } +#endif /* SPC5_PWM_USE_SMOD2 */ + +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + flexpwm_active_submodules0++; + } +#endif /* SPC5_PWM_USE_SMOD3 */ + +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + flexpwm_active_submodules1++; + } +#endif /* SPC5_PWM_USE_SMOD4 */ + +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + flexpwm_active_submodules1++; + } +#endif /* SPC5_PWM_USE_SMOD5 */ + +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + flexpwm_active_submodules1++; + } +#endif /* SPC5_PWM_USE_SMOD6 */ + +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + flexpwm_active_submodules1++; + } +#endif /* SPC5_PWM_USE_SMOD7 */ + + /** + * If this is the first FlexPWM0 submodule + * activated then the FlexPWM0 is enabled. + */ +#if SPC5_PWM_USE_FLEXPWM0 + /* Set Peripheral Clock.*/ + if (flexpwm_active_submodules0 == 1) { + halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL, + SPC5_PWM_FLEXPWM0_START_PCTL); + } +#endif + +#if SPC5_PWM_USE_FLEXPWM1 + /* Set Peripheral Clock.*/ + if (flexpwm_active_submodules1 == 1) { + halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL, + SPC5_PWM_FLEXPWM1_START_PCTL); + } +#endif + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + pwm_lld_start_submodule(pwmp, 0); + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + pwm_lld_start_submodule(pwmp, 1); + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + pwm_lld_start_submodule(pwmp, 2); + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + pwm_lld_start_submodule(pwmp, 3); + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + pwm_lld_start_submodule(pwmp, 0); + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + pwm_lld_start_submodule(pwmp, 1); + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + pwm_lld_start_submodule(pwmp, 2); + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + pwm_lld_start_submodule(pwmp, 3); + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[0].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xE; + pwmp->flexpwmp->MASK.B.MASKB &= 0xE; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[1].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xD; + pwmp->flexpwmp->MASK.B.MASKB &= 0xD; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[2].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xB; + pwmp->flexpwmp->MASK.B.MASKB &= 0xB; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[3].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0x7; + pwmp->flexpwmp->MASK.B.MASKB &= 0x7; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[0].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xE; + pwmp->flexpwmp->MASK.B.MASKB &= 0xE; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[1].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xD; + pwmp->flexpwmp->MASK.B.MASKB &= 0xD; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[2].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0xB; + pwmp->flexpwmp->MASK.B.MASKB &= 0xB; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U; + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + /* Disable the interrupts.*/ + pwmp->flexpwmp->SUB[3].INTEN.R = 0; + + /* Disable the submodule.*/ + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; + + /* Active the submodule masks.*/ + pwmp->flexpwmp->MASK.B.MASKA &= 0x7; + pwmp->flexpwmp->MASK.B.MASKB &= 0x7; + + /* Sets the MASK registers.*/ + pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U; + pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U; + } +#endif + } +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + chDbgAssert(flexpwm_active_submodules0 < 5, + "pwm_lld_stop(), #1", "too many submodules"); + chDbgAssert(flexpwm_active_submodules1 < 5, + "pwm_lld_stop(), #2", "too many submodules"); + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + flexpwm_active_submodules0--; + } +#endif /* SPC5_PWM_USE_SMOD0 */ + +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + flexpwm_active_submodules0--; + } +#endif /* SPC5_PWM_USE_SMOD1 */ + +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + flexpwm_active_submodules0--; + } +#endif /* SPC5_PWM_USE_SMOD2 */ + +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + flexpwm_active_submodules0--; + } +#endif /* SPC5_PWM_USE_SMOD3 */ + +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + flexpwm_active_submodules1--; + } +#endif /* SPC5_PWM_USE_SMOD4 */ + +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + flexpwm_active_submodules1--; + } +#endif /* SPC5_PWM_USE_SMOD5 */ + +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + flexpwm_active_submodules1--; + } +#endif /* SPC5_PWM_USE_SMOD6 */ + +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + flexpwm_active_submodules1--; + } +#endif /* SPC5_PWM_USE_SMOD7 */ + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; + pwmp->flexpwmp->SUB[0].INTEN.R = 0; + pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xE; + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; + pwmp->flexpwmp->SUB[1].INTEN.R = 0; + pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xD; + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; + pwmp->flexpwmp->SUB[2].INTEN.R = 0; + pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xB; + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; + pwmp->flexpwmp->SUB[3].INTEN.R = 0; + pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0x7; + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; + pwmp->flexpwmp->SUB[0].INTEN.R = 0; + pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xE; + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; + pwmp->flexpwmp->SUB[1].INTEN.R = 0; + pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xD; + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; + pwmp->flexpwmp->SUB[2].INTEN.R = 0; + pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0xB; + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + /* SMOD stop.*/ + pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; + pwmp->flexpwmp->SUB[3].INTEN.R = 0; + pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF; + pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; + pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; + + pwmp->flexpwmp->MCTRL.B.RUN &= 0x7; + } +#endif + +#if SPC5_PWM_USE_FLEXPWM0 + /* Disable peripheral clock if there is not an activated module.*/ + if (flexpwm_active_submodules0 == 0) { + halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL, + SPC5_PWM_FLEXPWM0_STOP_PCTL); + } +#endif + +#if SPC5_PWM_USE_FLEXPWM1 + /* Disable peripheral clock if there is not an activated module.*/ + if (flexpwm_active_submodules1 == 0) { + halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL, + SPC5_PWM_FLEXPWM1_STOP_PCTL); + } +#endif + + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 0); + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 1); + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 2); + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 3); + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 0); + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 1); + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 2); + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + pwm_lld_enable_submodule_channel(pwmp, channel, width, 3); + } +#endif +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 0); + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 1); + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 2); + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 3); + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 0); + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 1); + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 2); + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + pwm_lld_disable_submodule_channel(pwmp, channel, 3); + } +#endif +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + + pwmcnt_t pwmperiod = period; +#if SPC5_PWM_USE_SMOD0 + if (&PWMD1 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[0].VAL[0].R = 0; + pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 1U; + } +#endif +#if SPC5_PWM_USE_SMOD1 + if (&PWMD2 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[1].VAL[0].R = 0; + pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 2U; + } +#endif +#if SPC5_PWM_USE_SMOD2 + if (&PWMD3 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[2].VAL[0].R = 0; + pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 4U; + } +#endif +#if SPC5_PWM_USE_SMOD3 + if (&PWMD4 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[3].VAL[0].R = 0; + pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 8U; + } +#endif +#if SPC5_PWM_USE_SMOD4 + if (&PWMD5 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[0].VAL[0].R = 0; + pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 1U; + } +#endif +#if SPC5_PWM_USE_SMOD5 + if (&PWMD6 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[1].VAL[0].R = 0; + pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 2U; + } +#endif +#if SPC5_PWM_USE_SMOD6 + if (&PWMD7 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[2].VAL[0].R = 0; + pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 4U; + } +#endif +#if SPC5_PWM_USE_SMOD7 + if (&PWMD8 == pwmp) { + pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; + + /* Setting PWM period.*/ + pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[3].VAL[0].R = 0; + pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2; + + switch (pwmp->config->mode & PWM_ALIGN_MASK) { + case PWM_ALIGN_EDGE: + /* Setting active front of PWM channels.*/ + pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U; + pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U; + break; + default: + ; + } + pwmp->flexpwmp->MCTRL.B.LDOK |= 8U; + } +#endif +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h new file mode 100644 index 000000000..ea9acb7cd --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h @@ -0,0 +1,475 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexPWM_v1/pwm_lld.h + * @brief SPC5xx low level PWM driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_flexpwm.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name STS register bits definitions + * @{ + */ +#define SPC5_FLEXPWM_STS_CMPF0 (1U << 0) +#define SPC5_FLEXPWM_STS_CMPF1 (1U << 1) +#define SPC5_FLEXPWM_STS_CMPF2 (1U << 2) +#define SPC5_FLEXPWM_STS_CMPF3 (1U << 3) +#define SPC5_FLEXPWM_STS_CMPF4 (1U << 4) +#define SPC5_FLEXPWM_STS_CMPF5 (1U << 5) +#define SPC5_FLEXPWM_STS_CFX0 (1U << 6) +#define SPC5_FLEXPWM_STS_CFX1 (1U << 7) +#define SPC5_FLEXPWM_STS_RF (1U << 12) +#define SPC5_FLEXPWM_STS_REF (1U << 13) +#define SPC5_FLEXPWM_STS_RUF (1U << 14) +/** @} */ + +/** + * @name PSC values definition + * @{ + */ +#define SPC5_FLEXPWM_PSC_1 0U +#define SPC5_FLEXPWM_PSC_2 1U +#define SPC5_FLEXPWM_PSC_4 2U +#define SPC5_FLEXPWM_PSC_8 3U +#define SPC5_FLEXPWM_PSC_16 4U +#define SPC5_FLEXPWM_PSC_32 5U +#define SPC5_FLEXPWM_PSC_64 6U +#define SPC5_FLEXPWM_PSC_128 7U +/** @} */ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 2 + +/** + * @brief Complementary output modes mask. + * @note This is an SPC5-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an SPC5-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an SPC5-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an SPC5-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 + +/** + * @brief Alignment mode mask. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_MASK 0x01 + +/** + * @brief Edge-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_EDGE 0x00 + +/** + * @brief Center-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_CENTER 0x01 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD0) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD0 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD1) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD1 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD2) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD2 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD3) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD3 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD0_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD0_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD1_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD2_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD2_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD3_PRIORITY 7 +#endif + +/** + * @brief FlexPWM-0 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_PWM_FLEXPWM0_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief FlexPWM-0 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_PWM_FLEXPWM0_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD4) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD4 FALSE +#endif + +/** + * @brief PWMD6 driver enable switch. + * @details If set to @p TRUE the support for PWMD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD5) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD5 FALSE +#endif + +/** + * @brief PWMD7 driver enable switch. + * @details If set to @p TRUE the support for PWMD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD6) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD6 FALSE +#endif + +/** + * @brief PWMD8 driver enable switch. + * @details If set to @p TRUE the support for PWMD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_SMOD7) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_SMOD7 FALSE +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD4_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD4_PRIORITY 7 +#endif + +/** + * @brief PWMD6 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD5_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD5_PRIORITY 7 +#endif + +/** + * @brief PWMD7 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD6_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD6_PRIORITY 7 +#endif + +/** + * @brief PWMD8 interrupt priority level setting. + */ +#if !defined(SPC5_PWM_SMOD7_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_PWM_SMOD7_PRIORITY 7 +#endif + +/** + * @brief FlexPWM-1 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_PWM_FLEXPWM1_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief FlexPWM-1 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_PWM_FLEXPWM1_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#define SPC5_PWM_USE_FLEXPWM0 (SPC5_PWM_USE_SMOD0 || \ + SPC5_PWM_USE_SMOD1 || \ + SPC5_PWM_USE_SMOD2 || \ + SPC5_PWM_USE_SMOD3) + +#define SPC5_PWM_USE_FLEXPWM1 (SPC5_PWM_USE_SMOD4 || \ + SPC5_PWM_USE_SMOD5 || \ + SPC5_PWM_USE_SMOD6 || \ + SPC5_PWM_USE_SMOD7) + +#if !SPC5_HAS_FLEXPWM0 && SPC5_PWM_USE_FLEXPWM0 +#error "FlexPWM0 not present in the selected device" +#endif + +#if !SPC5_HAS_FLEXPWM1 && SPC5_PWM_USE_FLEXPWM1 +#error "FlexPWM1 not present in the selected device" +#endif + +#if !SPC5_PWM_USE_FLEXPWM0 && !SPC5_PWM_USE_FLEXPWM1 +#error "PWM driver activated but no PWM peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief PWM functional mode. + */ + pwmmode_t mode; +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @Pointer to the volatile FlexPWM registers block. + */ + volatile struct spc5_flexpwm *flexpwmp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_SMOD0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if SPC5_PWM_USE_SMOD1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if SPC5_PWM_USE_SMOD2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if SPC5_PWM_USE_SMOD3 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if SPC5_PWM_USE_SMOD4 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if SPC5_PWM_USE_SMOD5 && !defined(__DOXYGEN__) +extern PWMDriver PWMD6; +#endif + +#if SPC5_PWM_USE_SMOD6 && !defined(__DOXYGEN__) +extern PWMDriver PWMD7; +#endif + +#if SPC5_PWM_USE_SMOD7 && !defined(__DOXYGEN__) +extern PWMDriver PWMD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h new file mode 100644 index 000000000..5be53d949 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h @@ -0,0 +1,491 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexPWM_v1/spc5_flexpwm.h + * @brief SPC5xx FlexPWM header file. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _SPC5_FLEXPWM_H_ +#define _SPC5_FLEXPWM_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief SPC5 FlexPWM registers block. + * @note Redefined from the SPC5 headers because the non uniform + * declaration of the SubModules registers among the various + * sub-families. + */ +struct spc5_flexpwm_submodule { + + union { + vuint16_t R; + } CNT; /* Counter Register */ + + union { + vuint16_t R; + } INIT; /* Initial Count Register */ + + union { + vuint16_t R; + struct { + vuint16_t DBGEN :1; + vuint16_t WAITEN :1; + vuint16_t INDEP :1; + vuint16_t PWMA_INIT :1; + vuint16_t PWMB_INIT :1; + vuint16_t PWMX_INIT :1; + vuint16_t INIT_SEL :2; + vuint16_t FRCEN :1; + vuint16_t FORCE :1; + vuint16_t FORCE_SEL :3; + vuint16_t RELOAD_SEL :1; + vuint16_t CLK_SEL :2; + } B; + } CTRL2; /* Control 2 Register */ + + union { + vuint16_t R; + struct { + vuint16_t LDFQ :4; + vuint16_t HALF :1; + vuint16_t FULL :1; + vuint16_t DT :2; + vuint16_t :1; + vuint16_t PRSC :3; + vuint16_t :3; + vuint16_t DBLEN :1; + } B; + } CTRL; /* Control Register */ + + union { + vuint16_t R; + } VAL[6]; /* Value Register 0->5 */ + + union { + vuint16_t R; + struct { + vuint16_t FRACAEN :1; + vuint16_t :10; + vuint16_t FRACADLY :5; + } B; + } FRACA; /* Fractional Delay Register A */ + + union { + vuint16_t R; + struct { + vuint16_t FRACBEN :1; + vuint16_t :10; + vuint16_t FRACBDLY :5; + } B; + } FRACB; /* Fractional Delay Register B */ + + union { + vuint16_t R; + struct { + vuint16_t PWMA_IN :1; + vuint16_t PWMB_IN :1; + vuint16_t PWMX_IN :1; + vuint16_t :2; + vuint16_t POLA :1; + vuint16_t POLB :1; + vuint16_t POLX :1; + vuint16_t :2; + vuint16_t PWMAFS :2; + vuint16_t PWMBFS :2; + vuint16_t PWMXFS :2; + } B; + } OCTRL; /* Output Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t :1; + vuint16_t RUF :1; + vuint16_t REF :1; + vuint16_t RF :1; + vuint16_t CFA1 :1; + vuint16_t CFA0 :1; + vuint16_t CFB1 :1; + vuint16_t CFB0 :1; + vuint16_t CFX1 :1; + vuint16_t CFX0 :1; + vuint16_t CMPF :6; + } B; + } STS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t :2; + vuint16_t REIE :1; + vuint16_t RIE :1; + vuint16_t :4; + vuint16_t CX1IE :1; + vuint16_t CX0IE :1; + vuint16_t CMPIE :6; + } B; + } INTEN; /* Interrupt Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t :6; + vuint16_t VALDE :1; + vuint16_t FAND :1; + vuint16_t CAPTDE :2; + vuint16_t CA1DE :1; + vuint16_t CA0DE :1; + vuint16_t CB1DE :1; + vuint16_t CB0DE :1; + vuint16_t CX1DE :1; + vuint16_t CX0DE :1; + } B; + } DMAEN; /* DMA Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t :10; + vuint16_t OUT_TRIG_EN :6; + } B; + } TCTRL; /* Output Trigger Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t :4; + vuint16_t DISX :4; + vuint16_t DISB :4; + vuint16_t DISA :4; + } B; + } DISMAP; /* Fault Disable Mapping Register */ + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t DTCNT0 :11; + } B; + } DTCNT0; /* Deadtime Count Register 0 */ + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t DTCNT1 :11; + } B; + } DTCNT1; /* Deadtime Count Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CA1CNT :3; + vuint16_t CA0CNT :3; + vuint16_t CFAWM :2; + vuint16_t EDGCNTAEN :1; + vuint16_t INPSELA :1; + vuint16_t EDGA1 :2; + vuint16_t EDGA0 :2; + vuint16_t ONESHOTA :1; + vuint16_t ARMA :1; + } B; + } CAPTCTRLA; /* Capture Control Register A */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTA :8; + vuint16_t EDGCMPA :8; + } B; + } CAPTCOMPA; /* Capture Compare Register A */ + + union { + vuint16_t R; + struct { + vuint16_t CB1CNT :3; + vuint16_t CB0CNT :3; + vuint16_t CFBWM :2; + vuint16_t EDGCNTBEN :1; + vuint16_t INPSELB :1; + vuint16_t EDGB1 :2; + vuint16_t EDGB0 :2; + vuint16_t ONESHOTB :1; + vuint16_t ARMB :1; + } B; + } CAPTCTRLB; /* Capture Control Register B */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTB :8; + vuint16_t EDGCMPB :8; + } B; + } CAPTCOMPB; /* Capture Compare Register B */ + + union { + vuint16_t R; + struct { + vuint16_t CX1CNT :3; + vuint16_t CX0CNT :3; + vuint16_t CFXWM :2; + vuint16_t EDGCNTX_EN :1; + vuint16_t INP_SELX :1; + vuint16_t EDGX1 :2; + vuint16_t EDGX0 :2; + vuint16_t ONESHOTX :1; + vuint16_t ARMX :1; + } B; + } CAPTCTRLX; /* Capture Control Register B */ + + union { + vuint16_t R; + struct { + vuint16_t EDGCNTX :8; + vuint16_t EDGCMPX :8; + } B; + } CAPTCOMPX; /* Capture Compare Register X */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL0 :16; + } B; + } CVAL0; /* Capture Value 0 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL0CYC :4; + } B; + } CVAL0C; /* Capture Value 0 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL1 :16; + } B; + } CVAL1; /* Capture Value 1 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL1CYC :4; + } B; + } CVAL1C; /* Capture Value 1 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL2 :16; + } B; + } CVAL2; /* Capture Value 2 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL2CYC :4; + } B; + } CVAL2C; /* Capture Value 2 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL3 :16; + } B; + } CVAL3; /* Capture Value 3 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL3CYC :4; + } B; + } CVAL3C; /* Capture Value 3 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL4 :16; + } B; + } CVAL4; /* Capture Value 4 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL4CYC :4; + } B; + } CVAL4C; /* Capture Value 4 Cycle Register */ + + union { + vuint16_t R; + struct { + vuint16_t CAPTVAL5 :16; + } B; + } CVAL5; /* Capture Value 5 Register */ + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t CVAL5CYC :4; + } B; + } CVAL5C; /* Capture Value 5 Cycle Register */ + + uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */ + +}; +/* end of FLEXPWM_SUB_tag */ + +struct spc5_flexpwm { + + struct spc5_flexpwm_submodule SUB[4]; + + union { + vuint16_t R; + struct { + vuint16_t :4; + vuint16_t PWMA_EN :4; + vuint16_t PWMB_EN :4; + vuint16_t PWMX_EN :4; + } B; + } OUTEN; /* Output Enable Register */ + + union { + vuint16_t R; + struct { + vuint16_t :4; + vuint16_t MASKA :4; + vuint16_t MASKB :4; + vuint16_t MASKX :4; + } B; + } MASK; /* Output Mask Register */ + + union { + vuint16_t R; + struct { + vuint16_t :8; + vuint16_t OUTA_3 :1; + vuint16_t OUTB_3 :1; + vuint16_t OUTA_2 :1; + vuint16_t OUTB_2 :1; + vuint16_t OUTA_1 :1; + vuint16_t OUTB_1 :1; + vuint16_t OUTA_0 :1; + vuint16_t OUTB_0 :1; + } B; + } SWCOUT; /* Software Controlled Output Register */ + + union { + vuint16_t R; + struct { + vuint16_t SELA_3 :2; + vuint16_t SELB_3 :2; + vuint16_t SELA_2 :2; + vuint16_t SELB_2 :2; + vuint16_t SELA_1 :2; + vuint16_t SELB_1 :2; + vuint16_t SELA_0 :2; + vuint16_t SELB_0 :2; + } B; + } DTSRCSEL; /* Deadtime Source Select Register */ + + union { + vuint16_t R; + struct { + vuint16_t IPOL :4; + vuint16_t RUN :4; + vuint16_t CLDOK :4; + vuint16_t LDOK :4; + } B; + } MCTRL; /* Master Control Register */ + + int16_t FLEXPWM_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t FLVL :4; + vuint16_t FAUTO :4; + vuint16_t FSAFE :4; + vuint16_t FIE :4; + } B; + } FCTRL; /* Fault Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t FTEST :1; + vuint16_t FFPIN :4; + vuint16_t :4; + vuint16_t FFLAG :4; + } B; + } FSTS; /* Fault Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t FILT_CNT :3; + vuint16_t FILT_PER :8; + } B; + } FFILT; /* Fault FilterRegister */ + +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name FlexPWM units references + * @{ + */ +#if SPC5_HAS_FLEXPWM0 || defined(__DOXYGEN__) +#define SPC5_FLEXPWM_0 (*(volatile struct spc5_flexpwm *)0xFFE24000UL) +#endif + +#if SPC5_HAS_FLEXPWM1 || defined(__DOXYGEN__) +#define SPC5_FLEXPWM_1 (*(volatile struct spc5_flexpwm *)0xFFE28000UL) +#endif +/** @} */ + +#endif /* _SPC5_FLEXPWM_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c new file mode 100644 index 000000000..71247b236 --- /dev/null +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c @@ -0,0 +1,602 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/LINFlex_v1/serial_lld.c + * @brief SPC5xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief LIINFlex-0 serial driver identifier. + */ +#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief LIINFlex-1 serial driver identifier. + */ +#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief LIINFlex-2 serial driver identifier. + */ +#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** + * @brief LIINFlex-3 serial driver identifier. + */ +#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + SD_MODE_8BITS_PARITY_NONE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief LINFlex initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) { + uint32_t div; + volatile struct spc5_linflex *linflexp = sdp->linflexp; + + /* Enters the configuration mode.*/ + linflexp->LINCR1.R = 1; /* INIT bit. */ + + /* Configures the LINFlex in UART mode with all the required + parameters.*/ + linflexp->UARTCR.R = SPC5_UARTCR_UART; /* UART mode FIRST. */ + linflexp->UARTCR.R = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode; + div = SPC5_LINFLEX0_CLK / config->speed; + linflexp->LINFBRR.R = (uint16_t)(div & 15); /* Fractional divider. */ + linflexp->LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */ + linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/ + linflexp->LINIER.R = SPC5_LINIER_DTIE | SPC5_LINIER_DRIE | + SPC5_LINIER_BOIE | SPC5_LINIER_FEIE | + SPC5_LINIER_SZIE; /* Interrupts enabled. */ + + /* Leaves the configuration mode.*/ + linflexp->LINCR1.R = 0; +} + +/** + * @brief LINFlex de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] linflexp pointer to a LINFlex I/O block + */ +static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) { + + /* Enters the configuration mode.*/ + linflexp->LINCR1.R = 1; /* INIT bit. */ + + /* Resets the LINFlex registers.*/ + linflexp->LINFBRR.R = 0; /* Fractional divider. */ + linflexp->LINIBRR.R = 0; /* Integer divider. */ + linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/ + linflexp->UARTCR.R = SPC5_UARTCR_UART; + linflexp->LINIER.R = 0; /* Interrupts disabled. */ + + /* Leaves the configuration mode.*/ + linflexp->LINCR1.R = 0; +} + +/** + * @brief Common RXI IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void spc5xx_serve_rxi_interrupt(SerialDriver *sdp) { + flagsmask_t sts = 0; + uint16_t sr = sdp->linflexp->UARTSR.R; + + sdp->linflexp->UARTSR.R = SPC5_UARTSR_NF | SPC5_UARTSR_DRF | + SPC5_UARTSR_PE0; + if (sr & SPC5_UARTSR_NF) + sts |= SD_NOISE_ERROR; + if (sr & SPC5_UARTSR_PE0) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + if (sts) + chnAddFlagsI(sdp, sts); + if (sr & SPC5_UARTSR_DRF) { + sdIncomingDataI(sdp, sdp->linflexp->BDRM.B.DATA4); + sdp->linflexp->UARTSR.R = SPC5_UARTSR_RMB; + } + chSysUnlockFromIsr(); +} + +/** + * @brief Common TXI IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void spc5xx_serve_txi_interrupt(SerialDriver *sdp) { + msg_t b; + + sdp->linflexp->UARTSR.R = SPC5_UARTSR_DTF; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + sdp->linflexp->UARTCR.B.TXEN = 0; + } + else + sdp->linflexp->BDRL.B.DATA0 = b; + chSysUnlockFromIsr(); +} + +/** + * @brief Common ERR IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void spc5xx_serve_err_interrupt(SerialDriver *sdp) { + flagsmask_t sts = 0; + uint16_t sr = sdp->linflexp->UARTSR.R; + + sdp->linflexp->UARTSR.R = SPC5_UARTSR_BOF | SPC5_UARTSR_FEF | + SPC5_UARTSR_SZF; + if (sr & SPC5_UARTSR_BOF) + sts |= SD_OVERRUN_ERROR; + if (sr & SPC5_UARTSR_FEF) + sts |= SD_FRAMING_ERROR; + if (sr & SPC5_UARTSR_SZF) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (!SD1.linflexp->UARTCR.B.TXEN) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + SD1.linflexp->UARTCR.B.TXEN = 1; + SD1.linflexp->BDRL.B.DATA0 = b; + } + } +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (!SD2.linflexp->UARTCR.B.TXEN) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + SD2.linflexp->UARTCR.B.TXEN = 1; + SD2.linflexp->BDRL.B.DATA0 = b; + } + } +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + if (!SD3.linflexp->UARTCR.B.TXEN) { + msg_t b = sdRequestDataI(&SD3); + if (b != Q_EMPTY) { + SD3.linflexp->UARTCR.B.TXEN = 1; + SD3.linflexp->BDRL.B.DATA0 = b; + } + } +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__) +static void notify4(GenericQueue *qp) { + + (void)qp; + if (!SD4.linflexp->UARTCR.B.TXEN) { + msg_t b = sdRequestDataI(&SD4); + if (b != Q_EMPTY) { + SD4.linflexp->UARTCR.B.TXEN = 1; + SD4.linflexp->BDRL.B.DATA0 = b; + } + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__) +#if !defined(SPC5_LINFLEX0_RXI_HANDLER) +#error "SPC5_LINFLEX0_RXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-0 RXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX0_RXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_rxi_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX0_TXI_HANDLER) +#error "SPC5_LINFLEX0_TXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-0 TXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX0_TXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_txi_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX0_ERR_HANDLER) +#error "SPC5_LINFLEX0_ERR_HANDLER not defined" +#endif +/** + * @brief LINFlex-0 ERR interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX0_ERR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_err_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__) +#if !defined(SPC5_LINFLEX1_RXI_HANDLER) +#error "SPC5_LINFLEX1_RXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-1 RXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX1_RXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_rxi_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX1_TXI_HANDLER) +#error "SPC5_LINFLEX1_TXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-1 TXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX1_TXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_txi_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX1_ERR_HANDLER) +#error "SPC5_LINFLEX1_ERR_HANDLER not defined" +#endif +/** + * @brief LINFlex-1 ERR interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_err_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__) +#if !defined(SPC5_LINFLEX2_RXI_HANDLER) +#error "SPC5_LINFLEX2_RXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-2 RXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_rxi_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX2_TXI_HANDLER) +#error "SPC5_LINFLEX2_TXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-2 TXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_txi_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX2_ERR_HANDLER) +#error "SPC5_LINFLEX2_ERR_HANDLER not defined" +#endif +/** + * @brief LINFlex-2 ERR interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_err_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__) +#if !defined(SPC5_LINFLEX3_RXI_HANDLER) +#error "SPC5_LINFLEX3_RXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-3 RXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_rxi_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX3_TXI_HANDLER) +#error "SPC5_LINFLEX3_TXI_HANDLER not defined" +#endif +/** + * @brief LINFlex-3 TXI interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_txi_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_LINFLEX3_ERR_HANDLER) +#error "SPC5_LINFLEX3_ERR_HANDLER not defined" +#endif +/** + * @brief LINFlex-3 ERR interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + spc5xx_serve_err_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if SPC5_SERIAL_USE_LINFLEX0 + sdObjectInit(&SD1, NULL, notify1); + SD1.linflexp = &SPC5_LINFLEX0; + INTC.PSR[SPC5_LINFLEX0_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY; + INTC.PSR[SPC5_LINFLEX0_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY; + INTC.PSR[SPC5_LINFLEX0_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY; +#endif + +#if SPC5_SERIAL_USE_LINFLEX1 + sdObjectInit(&SD2, NULL, notify2); + SD2.linflexp = &SPC5_LINFLEX1; + INTC.PSR[SPC5_LINFLEX1_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY; + INTC.PSR[SPC5_LINFLEX1_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY; + INTC.PSR[SPC5_LINFLEX1_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY; +#endif + +#if SPC5_SERIAL_USE_LINFLEX2 + sdObjectInit(&SD3, NULL, notify3); + SD3.linflexp = &SPC5_LINFLEX2; + INTC.PSR[SPC5_LINFLEX2_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY; + INTC.PSR[SPC5_LINFLEX2_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY; + INTC.PSR[SPC5_LINFLEX2_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY; +#endif + +#if SPC5_SERIAL_USE_LINFLEX3 + sdObjectInit(&SD4, NULL, notify4); + SD4.linflexp = &SPC5_LINFLEX3; + INTC.PSR[SPC5_LINFLEX3_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY; + INTC.PSR[SPC5_LINFLEX3_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY; + INTC.PSR[SPC5_LINFLEX3_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if SPC5_SERIAL_USE_LINFLEX0 + if (&SD1 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, + SPC5_SERIAL_LINFLEX0_START_PCTL); + } +#endif +#if SPC5_SERIAL_USE_LINFLEX1 + if (&SD2 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, + SPC5_SERIAL_LINFLEX1_START_PCTL); + } +#endif +#if SPC5_SERIAL_USE_LINFLEX2 + if (&SD3 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL, + SPC5_SERIAL_LINFLEX2_START_PCTL); + } +#endif +#if SPC5_SERIAL_USE_LINFLEX3 + if (&SD4 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL, + SPC5_SERIAL_LINFLEX3_START_PCTL); + } +#endif + } + spc5_linflex_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + spc5_linflex_deinit(sdp->linflexp); + +#if SPC5_SERIAL_USE_LINFLEX0 + if (&SD1 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, + SPC5_SERIAL_LINFLEX0_STOP_PCTL); + return; + } +#endif +#if SPC5_SERIAL_USE_LINFLEX1 + if (&SD2 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, + SPC5_SERIAL_LINFLEX1_STOP_PCTL); + return; + } +#endif +#if SPC5_SERIAL_USE_LINFLEX2 + if (&SD3 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL, + SPC5_SERIAL_LINFLEX2_STOP_PCTL); + return; + } +#endif +#if SPC5_SERIAL_USE_LINFLEX3 + if (&SD4 == sdp) { + halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL, + SPC5_SERIAL_LINFLEX3_STOP_PCTL); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h new file mode 100644 index 000000000..cbd446b86 --- /dev/null +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h @@ -0,0 +1,302 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/LINFlex_v1/serial_lld.h + * @brief SPC5xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +#include "spc5_linflex.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Serial driver allowable modes + * @{ + */ +#define SD_MODE_8BITS_PARITY_NONE (SPC5_UARTCR_WL) +#define SD_MODE_8BITS_PARITY_EVEN (SPC5_UARTCR_WL | \ + SPC5_UARTCR_PCE) +#define SD_MODE_8BITS_PARITY_ODD (SPC5_UARTCR_WL | \ + SPC5_UARTCR_PCE | \ + SPC5_UARTCR_OP) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief LINFlex-0 driver enable switch. + * @details If set to @p TRUE the support for LINFlex-0 is included. + */ +#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__) +#define SPC5_SERIAL_USE_LINFLEX0 FALSE +#endif + +/** + * @brief LINFlex-1 driver enable switch. + * @details If set to @p TRUE the support for LINFlex-1 is included. + */ +#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__) +#define SPC5_SERIAL_USE_LINFLEX1 FALSE +#endif + +/** + * @brief LINFlex-2 driver enable switch. + * @details If set to @p TRUE the support for LINFlex-2 is included. + */ +#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__) +#define SPC5_SERIAL_USE_LINFLEX2 FALSE +#endif + +/** + * @brief LINFlex-3 driver enable switch. + * @details If set to @p TRUE the support for LINFlex-3 is included. + */ +#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__) +#define SPC5_SERIAL_USE_LINFLEX3 FALSE +#endif + +/** + * @brief LINFlex-0 interrupt priority level setting. + */ +#if !defined(SPC5_SERIAL_LINFLEX0_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#endif + +/** + * @brief LINFlex-1 interrupt priority level setting. + */ +#if !defined(SPC5_SERIAL_LINFLEX1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#endif + +/** + * @brief LINFlex-2 interrupt priority level setting. + */ +#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX2_PRIORITY 8 +#endif + +/** + * @brief LINFlex-3 interrupt priority level setting. + */ +#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX3_PRIORITY 8 +#endif + +/** + * @brief LINFlex-0 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX0_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief LINFlex-0 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX0_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief LINFlex-1 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX1_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief LINFlex-1 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX1_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief LINFlex-2 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief LINFlex-2 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief LINFlex-3 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief LINFlex-3 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_SERIAL_LINFLEX3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPC5_SERIAL_USE_LINFLEX0 && !SPC5_HAS_LINFLEX0 +#error "LINFlex-0 not present in the selected device" +#endif + +#if SPC5_SERIAL_USE_LINFLEX1 && !SPC5_HAS_LINFLEX1 +#error "LINFlex-1 not present in the selected device" +#endif + +#if SPC5_SERIAL_USE_LINFLEX2 && !SPC5_HAS_LINFLEX2 +#error "LINFlex-2 not present in the selected device" +#endif + +#if SPC5_SERIAL_USE_LINFLEX3 && !SPC5_HAS_LINFLEX3 +#error "LINFlex-3 not present in the selected device" +#endif + +#if !SPC5_SERIAL_USE_LINFLEX0 && !SPC5_SERIAL_USE_LINFLEX1 && \ + !SPC5_SERIAL_USE_LINFLEX2 && !SPC5_SERIAL_USE_LINFLEX3 +#error "SERIAL driver activated but no LINFlex peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Mode flags. + */ + uint8_t mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the volatile LINFlex registers block.*/ \ + volatile struct spc5_linflex *linflexp; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_SERIAL_USE_LINFLEX0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if SPC5_SERIAL_USE_LINFLEX1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if SPC5_SERIAL_USE_LINFLEX2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#if SPC5_SERIAL_USE_LINFLEX3 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h new file mode 100644 index 000000000..28e7575c4 --- /dev/null +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h @@ -0,0 +1,510 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/spc5_linflex.h + * @brief LINFlex helper driver header. + * + * @addtogroup SPC5xx_LINFLEX + * @{ + */ + +#ifndef _SPC5_LINFLEX_H_ +#define _SPC5_LINFLEX_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name LINIER register bits definitions + * @{ + */ +#define SPC5_LINIER_HRIE (1U << 0) +#define SPC5_LINIER_DTIE (1U << 1) +#define SPC5_LINIER_DRIE (1U << 2) +#define SPC5_LINIER_DBEIE (1U << 3) +#define SPC5_LINIER_DBFIE (1U << 4) +#define SPC5_LINIER_WUIE (1U << 5) +#define SPC5_LINIER_LSIE (1U << 6) +#define SPC5_LINIER_BOIE (1U << 7) +#define SPC5_LINIER_FEIE (1U << 8) +#define SPC5_LINIER_HEIE (1U << 11) +#define SPC5_LINIER_CEIE (1U << 12) +#define SPC5_LINIER_BEIE (1U << 13) +#define SPC5_LINIER_OCIE (1U << 14) +#define SPC5_LINIER_SZIE (1U << 15) +/** @} */ + +/** + * @name UARTSR register bits definitions + * @{ + */ +#define SPC5_UARTSR_NF (1U << 0) +#define SPC5_UARTSR_DTF (1U << 1) +#define SPC5_UARTSR_DRF (1U << 2) +#define SPC5_UARTSR_WUF (1U << 5) +#define SPC5_UARTSR_RPS (1U << 6) +#define SPC5_UARTSR_BOF (1U << 7) +#define SPC5_UARTSR_FEF (1U << 8) +#define SPC5_UARTSR_RMB (1U << 9) +#define SPC5_UARTSR_PE0 (1U << 10) +#define SPC5_UARTSR_PE1 (1U << 11) +#define SPC5_UARTSR_PE2 (1U << 12) +#define SPC5_UARTSR_PE3 (1U << 13) +#define SPC5_UARTSR_OCF (1U << 14) +#define SPC5_UARTSR_SZF (1U << 15) +/** @} */ + +/** + * @name UARTCR register bits definitions + * @{ + */ +#define SPC5_UARTCR_UART (1U << 0) +#define SPC5_UARTCR_WL (1U << 1) +#define SPC5_UARTCR_PCE (1U << 2) +#define SPC5_UARTCR_OP (1U << 3) +#define SPC5_UARTCR_TXEN (1U << 4) +#define SPC5_UARTCR_RXEN (1U << 5) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + + +struct spc5_linflex { + + int16_t LINFLEX_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t CCD :1; + vuint16_t CFD :1; + vuint16_t LASE :1; + vuint16_t AWUM :1; + vuint16_t MBL :4; + vuint16_t BF :1; + vuint16_t SFTM :1; + vuint16_t LBKM :1; + vuint16_t MME :1; + vuint16_t SBDT :1; + vuint16_t RBLM :1; + vuint16_t SLEEP :1; + vuint16_t INIT :1; + } B; + } LINCR1; + + int16_t LINFLEX_reserved2; + + union { + vuint16_t R; + struct { + vuint16_t SZIE :1; + vuint16_t OCIE :1; + vuint16_t BEIE :1; + vuint16_t CEIE :1; + vuint16_t HEIE :1; + vuint16_t :2; + vuint16_t FEIE :1; + vuint16_t BOIE :1; + vuint16_t LSIE :1; + vuint16_t WUIE :1; + vuint16_t DBFIE :1; + vuint16_t DBEIE :1; + vuint16_t DRIE :1; + vuint16_t DTIE :1; + vuint16_t HRIE :1; + } B; + } LINIER; + + int16_t LINFLEX_reserved3; + + union { + vuint16_t R; + struct { + vuint16_t LINS :4; + vuint16_t :2; + vuint16_t RMB :1; + vuint16_t :1; + vuint16_t RBSY :1; + vuint16_t RPS :1; + vuint16_t WUF :1; + vuint16_t DBFF :1; + vuint16_t DBEF :1; + vuint16_t DRF :1; + vuint16_t DTF :1; + vuint16_t HRF :1; + } B; + } LINSR; + + int16_t LINFLEX_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t SZF :1; + vuint16_t OCF :1; + vuint16_t BEF :1; + vuint16_t CEF :1; + vuint16_t SFEF :1; + vuint16_t BDEF :1; + vuint16_t IDPEF :1; + vuint16_t FEF :1; + vuint16_t BOF :1; + vuint16_t :6; + vuint16_t NF :1; + } B; + } LINESR; + + int16_t LINFLEX_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t :1; + vuint16_t TDFL :2; + vuint16_t :1; + vuint16_t RDFL :2; + vuint16_t :4; + vuint16_t RXEN :1; + vuint16_t TXEN :1; + vuint16_t OP :1; + vuint16_t PCE :1; + vuint16_t WL :1; + vuint16_t UART :1; + } B; + } UARTCR; + + int16_t LINFLEX_reserved6; + + union { + vuint16_t R; + struct { + vuint16_t SZF :1; + vuint16_t OCF :1; + vuint16_t PE :4; + vuint16_t RMB :1; + vuint16_t FEF :1; + vuint16_t BOF :1; + vuint16_t RPS :1; + vuint16_t WUF :1; + vuint16_t :2; + vuint16_t DRF :1; + vuint16_t DTF :1; + vuint16_t NF :1; + } B; + } UARTSR; + + int16_t LINFLEX_reserved7; + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t LTOM :1; + vuint16_t IOT :1; + vuint16_t TOCE :1; + vuint16_t CNT :8; + } B; + } LINTCSR; + + int16_t LINFLEX_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t OC2 :8; + vuint16_t OC1 :8; + } B; + } LINOCR; + + int16_t LINFLEX_reserved9; + + union { + vuint16_t R; + struct { + vuint16_t :4; + vuint16_t RTO :4; + vuint16_t :1; + vuint16_t HTO :7; + } B; + } LINTOCR; + + int16_t LINFLEX_reserved10; + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t DIV_F :4; + } B; + } LINFBRR; + + int16_t LINFLEX_reserved11; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DIV_M :13; + } B; + } LINIBRR; + + int16_t LINFLEX_reserved12; + + union { + vuint16_t R; + struct { + vuint16_t :8; + vuint16_t CF :8; + } B; + } LINCFR; + + int16_t LINFLEX_reserved13; + + union { + vuint16_t R; + struct { + vuint16_t :1; + vuint16_t IOBE :1; + vuint16_t IOPE :1; + vuint16_t WURQ :1; + vuint16_t DDRQ :1; + vuint16_t DTRQ :1; + vuint16_t ABRQ :1; + vuint16_t HTRQ :1; + vuint16_t :8; + } B; + } LINCR2; + + int16_t LINFLEX_reserved14; + + union { + vuint16_t R; + struct { + vuint16_t DFL :6; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } BIDR; + + union { + vuint32_t R; + struct { + vuint32_t DATA3 :8; + vuint32_t DATA2 :8; + vuint32_t DATA1 :8; + vuint32_t DATA0 :8; + } B; + } BDRL; + + union { + vuint32_t R; + struct { + vuint32_t DATA7 :8; + vuint32_t DATA6 :8; + vuint32_t DATA5 :8; + vuint32_t DATA4 :8; + } B; + } BDRM; + + int16_t LINFLEX_reserved15; + + union { + vuint16_t R; + struct { + vuint16_t :8; + vuint16_t FACT :8; + } B; + } IFER; + + int16_t LINFLEX_reserved16; + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t IFMI :4; + } B; + } IFMI; + + int16_t LINFLEX_reserved17; + + union { + vuint16_t R; + struct { + vuint16_t :12; + vuint16_t IFM :4; + } B; + } IFMR; + + int16_t LINFLEX_reserved18; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR0; + + int16_t LINFLEX_reserved19; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR1; + + int16_t LINFLEX_reserved20; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR2; + + int16_t LINFLEX_reserved21; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR3; + + int16_t LINFLEX_reserved22; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR4; + + int16_t LINFLEX_reserved23; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR5; + + int16_t LINFLEX_reserved24; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR6; + + int16_t LINFLEX_reserved25; + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t DFL :3; + vuint16_t DIR :1; + vuint16_t CCS :1; + vuint16_t :2; + vuint16_t ID :6; + } B; + } IFCR7; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** + * @name LINFlex units references + * @{ + */ +#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__) +#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE40000UL) +#endif + +#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__) +#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE44000UL) +#endif + +#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__) +#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFFE48000UL) +#endif + +#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__) +#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFFE4C000UL) +#endif +/** @} */ + +#endif /* _SPC5_LINFLEX_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c new file mode 100644 index 000000000..d8ae4b2d5 --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c @@ -0,0 +1,173 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/SIUL_v1/pal_lld.c + * @brief SPC5xx SIUL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if defined(SPC5_SIUL_SYSTEM_PINS) +static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS}; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SPC5xx I/O ports configuration. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + unsigned i; + +#if defined(SPC5_SIUL_PCTL) + /* SIUL clock gating if present.*/ + halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL, + SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); +#endif + + /* Initialize PCR registers for undefined pads.*/ + for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) { +#if defined(SPC5_SIUL_SYSTEM_PINS) + /* Handling the case where some SIU pins are not meant to be reprogrammed, + for example JTAG pins.*/ + unsigned j; + for (j = 0; j < sizeof system_pins; j++) { + if (i == system_pins[j]) + goto skip; + } + SIU.PCR[i].R = config->default_mode; +skip: + ; +#else + SIU.PCR[i].R = config->default_mode; +#endif + } + + /* Initialize PADSEL registers.*/ + for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++) + SIU.PSMI[i].R = config->padsels[i]; + + /* Initialize PCR registers for defined pads.*/ + i = 0; + while (config->inits[i].pcr_index != -1) { + SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value; + SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value; + i++; + } +} + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset) { + + (void)port; + (void)mask; + (void)offset; + return 0; +} + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits) { + + (void)port; + (void)mask; + (void)offset; + (void)bits; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH); + ioportmask_t m1 = 0x8000; + while (m1) { + if (mask & m1) + SIU.PCR[pcr_index].R = mode; + m1 >>= 1; + ++pcr_index; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h new file mode 100644 index 000000000..5304ac36d --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h @@ -0,0 +1,427 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/SIUL_v1/pal_lld.h + * @brief SPC5xx SIUL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name SIUL-specific PAL modes + * @{ + */ +#define PAL_SPC5_SMC (1U << 14) +#define PAL_SPC5_APC (1U << 13) +#define PAL_SPC5_PA_MASK (3U << 10) +#define PAL_SPC5_PA(n) ((n) << 10) +#define PAL_SPC5_OBE (1U << 9) +#define PAL_SPC5_IBE (1U << 8) +#define PAL_SPC5_ODE (1U << 5) +#define PAL_SPC5_SRC (1U << 2) +#define PAL_SPC5_WPE (1U << 1) +#define PAL_SPC5_WPS (1U << 0) +/** @} */ + +/** + * @name Pads mode constants + * @{ + */ +/** + * @brief After reset state. + */ +#define PAL_MODE_RESET 0 + +/** + * @brief Safe state for unconnected pads. + */ +#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS) + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_SPC5_IBE) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \ + PAL_SPC5_WPS) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_SPC5_APC + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_ODE) + +/** + * @brief Alternate "n" output pad. + * @note Both the IBE and OBE bits are specified in this mask, the OBE + * bit is not required for some PCRs but in that case it is + * ignored. + */ +#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_PA(n)) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint16_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint16_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/** + * @brief SIUL register initializer type. + */ +typedef struct { + int32_t pcr_index; + uint8_t gpdo_value; + iomode_t pcr_value; +} spc_siu_init_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + iomode_t default_mode; + const spc_siu_init_t *inits; + const uint8_t *padsels; +} PALConfig; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief I/O port A identifier. + */ +#define PORT_A 0 + +/** + * @brief I/O port B identifier. + */ +#define PORT_B 1 + +/** + * @brief I/O port C identifier. + */ +#define PORT_C 2 + +/** + * @brief I/O port D identifier. + */ +#define PORT_D 3 + +/** + * @brief I/O port E identifier. + */ +#define PORT_E 4 + +/** + * @brief I/O port F identifier. + */ +#define PORT_F 5 + +/** + * @brief I/O port G identifier. + */ +#define PORT_G 6 + +/** + * @brief I/O port H identifier. + */ +#define PORT_H 7 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Port bit helper macro. + * @note Overrides the one in @p pal.h. + * + * @param[in] n bit position within the port + * + * @return The bit mask. + */ +#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n))) + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port]) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port]) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + (((volatile uint16_t *)SIU.PGPDO)[port] = (bits)) + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + _pal_lld_readgroup(port, mask, offset) + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + _pal_lld_writegroup(port, mask, offset, bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) \ + (SIU.GPDI[((port) * 16) + (pad)].R) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (SIU.GPDO[((port) * 16) + (pad)].R = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 0) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset); + void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c new file mode 100644 index 000000000..1d77a177a --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c @@ -0,0 +1,145 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/SIU_v1/pal_lld.c + * @brief SPC5xx SIU low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if defined(SPC5_SIU_SYSTEM_PINS) +static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS}; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SPC5xx I/O ports configuration. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + unsigned i; + + /* Initialize PCR registers for defined pads.*/ + i = 0; + while (config->inits[i].pcr_index != -1) { + SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value; + SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value; + i++; + } +} + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset) { + + (void)port; + (void)mask; + (void)offset; + return 0; +} + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits) { + + (void)port; + (void)mask; + (void)offset; + (void)bits; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH); + ioportmask_t m1 = 0x8000; + while (m1) { + if (mask & m1) + SIU.PCR[pcr_index].R = mode; + m1 >>= 1; + ++pcr_index; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h new file mode 100644 index 000000000..b9c72bf0c --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h @@ -0,0 +1,423 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/SIU_v1/pal_lld.h + * @brief SPC5xx SIU low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name SIU-specific PAL modes + * @{ + */ +#define PAL_SPC5_PA_MASK (15U << 10) +#define PAL_SPC5_PA(n) ((n) << 10) +#define PAL_SPC5_OBE (1U << 9) +#define PAL_SPC5_IBE (1U << 8) +#define PAL_SPC5_DSC_10PF (0U << 6) +#define PAL_SPC5_DSC_20PF (1U << 6) +#define PAL_SPC5_DSC_30PF (2U << 6) +#define PAL_SPC5_DSC_50PF (3U << 6) +#define PAL_SPC5_ODE (1U << 5) +#define PAL_SPC5_HYS (1U << 4) +#define PAL_SPC5_WPE (1U << 1) +#define PAL_SPC5_WPS (1U << 0) +/** @} */ + +/** + * @name Pads mode constants + * @{ + */ +/** + * @brief After reset state. + */ +#define PAL_MODE_RESET 0 + +/** + * @brief Safe state for unconnected pads. + */ +#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS) + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_SPC5_IBE) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \ + PAL_SPC5_WPS) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_ODE) + +/** + * @brief Alternate "n" output pad. + * @note Both the IBE and OBE bits are specified in this mask, the OBE + * bit is not required for some PCRs but in that case it is + * ignored. + */ +#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_PA(n)) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint16_t ioportmask_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint16_t iomode_t; + +/** + * @brief SIU/SIUL register initializer type. + */ +typedef struct { + int32_t pcr_index; + uint8_t gpdo_value; + iomode_t pcr_value; +} spc_siu_init_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + const spc_siu_init_t *inits; +} PALConfig; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @name Port identifiers + * @{ + */ +#define PORT0 0 +#define PORT1 1 +#define PORT2 2 +#define PORT3 3 +#define PORT4 4 +#define PORT5 5 +#define PORT6 6 +#define PORT7 7 +#define PORT8 8 +#define PORT9 9 +#define PORT10 10 +#define PORT11 11 +#define PORT12 12 +#define PORT13 13 +#define PORT14 14 +#define PORT15 15 +#define PORT16 16 +#define PORT17 17 +#define PORT18 18 +#define PORT19 19 +#define PORT20 20 +#define PORT21 21 +#define PORT22 22 +#define PORT23 23 +#define PORT24 24 +#define PORT25 25 +#define PORT26 26 +#define PORT27 27 +#define PORT28 28 +#define PORT29 29 +#define PORT30 30 +#define PORT31 31 +/** @} */ + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Port bit helper macro. + * @note Overrides the one in @p pal.h. + * + * @param[in] n bit position within the port + * + * @return The bit mask. + */ +#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n))) + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__) +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port]) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port]) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + (((volatile uint16_t *)SIU.PGPDO)[port] = (bits)) + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + _pal_lld_readgroup(port, mask, offset) + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + _pal_lld_writegroup(port, mask, offset, bits) + +#endif /* SPC5_SIU_SUPPORTS_PORTS */ + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) \ + (SIU.GPDI[((port) * 16) + (pad)].R) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (SIU.GPDO[((port) * 16) + (pad)].R = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 0) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset); + void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c new file mode 100644 index 000000000..52337ff6b --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c @@ -0,0 +1,907 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/icu_lld.c + * @brief SPC5xx low level icu driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the unified channel eMIOS_CH0 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH0 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD2 allocates the unified channel eMIOS_CH1 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH1 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD3 allocates the unified channel eMIOS_CH2 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH2 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the unified channel eMIOS_CH3 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH3 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the unified channel eMIOS_CH4 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH4 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD6 driver identifier. + * @note The driver ICUD6 allocates the unified channel eMIOS_CH5 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH5 || defined(__DOXYGEN__) +ICUDriver ICUD6; +#endif + +/** + * @brief ICUD7 driver identifier. + * @note The driver ICUD7 allocates the unified channel eMIOS_CH6 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH6 || defined(__DOXYGEN__) +ICUDriver ICUD7; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the unified channel eMIOS_CH8 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH8 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the unified channel eMIOS_CH7 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH7 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/** + * @brief ICUD10 driver identifier. + * @note The driver ICUD10 allocates the unified channel eMIOS_CH16 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH16 || defined(__DOXYGEN__) +ICUDriver ICUD10; +#endif + +/** + * @brief ICUD11 driver identifier. + * @note The driver ICUD11 allocates the unified channel eMIOS_CH17 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH17 || defined(__DOXYGEN__) +ICUDriver ICUD11; +#endif + +/** + * @brief ICUD12 driver identifier. + * @note The driver ICUD12 allocates the unified channel eMIOS_CH18 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS_CH18 || defined(__DOXYGEN__) +ICUDriver ICUD12; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Width and Period registers. + */ +uint32_t width; +uint32_t period; + +/** + * @brief A2 temp registers. + */ +uint32_t A2_1, A2_2, A2_3; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ICU IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + + uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R; + + if (sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL) { + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC; + _icu_isr_invoke_overflow_cb(icup); + } + if (sr && EMIOSS_FLAG) { + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC; + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } + } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } + } + } + if (sr && EMIOSS_OVR) { + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC; + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS_CH0 +#if !defined(SPC5_EMIOS_FLAG_F0_HANDLER) +#error "SPC5_EMIOS_FLAG_F0_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 0 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ + +#if SPC5_ICU_USE_EMIOS_CH1 +#if !defined(SPC5_EMIOS_FLAG_F1_HANDLER) +#error "SPC5_EMIOS_FLAG_F1_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ + +#if SPC5_ICU_USE_EMIOS_CH2 +#if !defined(SPC5_EMIOS_FLAG_F2_HANDLER) +#error "SPC5_EMIOS_FLAG_F2_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ + +#if SPC5_ICU_USE_EMIOS_CH3 +#if !defined(SPC5_EMIOS_FLAG_F3_HANDLER) +#error "SPC5_EMIOS_FLAG_F3_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ + +#if SPC5_ICU_USE_EMIOS_CH4 +#if !defined(SPC5_EMIOS_FLAG_F4_HANDLER) +#error "SPC5_EMIOS_FLAG_F4_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ + +#if SPC5_ICU_USE_EMIOS_CH5 +#if !defined(SPC5_EMIOS_FLAG_F5_HANDLER) +#error "SPC5_EMIOS_FLAG_F5_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ + +#if SPC5_ICU_USE_EMIOS_CH6 +#if !defined(SPC5_EMIOS_FLAG_F6_HANDLER) +#error "SPC5_EMIOS_FLAG_F6_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 6 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ + +#if SPC5_ICU_USE_EMIOS_CH7 +#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER) +#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 7 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F7_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ + +#if SPC5_ICU_USE_EMIOS_CH7 +#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER) +#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 8 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F8_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ + +#if SPC5_ICU_USE_EMIOS_CH16 +#if !defined(SPC5_EMIOS_FLAG_F16_HANDLER) +#error "SPC5_EMIOS_FLAG_F16_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 16 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F16_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD10); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ + +#if SPC5_ICU_USE_EMIOS_CH17 +#if !defined(SPC5_EMIOS_FLAG_F17_HANDLER) +#error "SPC5_EMIOS_FLAG_F17_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 17 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F17_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ + +#if SPC5_ICU_USE_EMIOS_CH18 +#if !defined(SPC5_EMIOS_FLAG_F18_HANDLER) +#error "SPC5_EMIOS_FLAG_F18_HANDLER not defined" +#endif +/** + * @brief eMIOS Channel 18 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F18_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + + /* Initialize A2 temp registers.*/ + A2_1 = 0U; + A2_2 = 0U; + A2_3 = 0U; + + /* eMIOSx channels initially all not in use.*/ + reset_emios_active_channels(); + +#if SPC5_ICU_USE_EMIOS_CH0 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.emiosp = &EMIOS; + ICUD1.ch_number = 0U; + ICUD1.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ + +#if SPC5_ICU_USE_EMIOS_CH1 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.emiosp = &EMIOS; + ICUD2.ch_number = 1U; + ICUD2.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ + +#if SPC5_ICU_USE_EMIOS_CH2 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.emiosp = &EMIOS; + ICUD3.ch_number = 2U; + ICUD3.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ + +#if SPC5_ICU_USE_EMIOS_CH3 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.emiosp = &EMIOS; + ICUD4.ch_number = 3U; + ICUD4.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ + +#if SPC5_ICU_USE_EMIOS_CH4 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.emiosp = &EMIOS; + ICUD5.ch_number = 4U; + ICUD5.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ + +#if SPC5_ICU_USE_EMIOS_CH5 + /* Driver initialization.*/ + icuObjectInit(&ICUD6); + ICUD6.emiosp = &EMIOS; + ICUD6.ch_number = 5U; + ICUD6.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ + +#if SPC5_ICU_USE_EMIOS_CH6 + /* Driver initialization.*/ + icuObjectInit(&ICUD7); + ICUD7.emiosp = &EMIOS; + ICUD7.ch_number = 6U; + ICUD7.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ + +#if SPC5_ICU_USE_EMIOS_CH8 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.emiosp = &EMIOS; + ICUD8.ch_number = 8U; + ICUD8.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ + +#if SPC5_ICU_USE_EMIOS_CH7 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.emiosp = &EMIOS; + ICUD9.ch_number = 7U; + ICUD9.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ + +#if SPC5_ICU_USE_EMIOS_CH16 + /* Driver initialization.*/ + icuObjectInit(&ICUD10); + ICUD10.emiosp = &EMIOS; + ICUD10.ch_number = 16U; + ICUD10.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ + +#if SPC5_ICU_USE_EMIOS_CH17 + /* Driver initialization.*/ + icuObjectInit(&ICUD11); + ICUD11.emiosp = &EMIOS; + ICUD11.ch_number = 17U; + ICUD11.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ + +#if SPC5_ICU_USE_EMIOS_CH18 + /* Driver initialization.*/ + icuObjectInit(&ICUD12); + ICUD12.emiosp = &EMIOS; + ICUD12.ch_number = 18U; + ICUD12.clock = SPC5_EMIOS_CLK; +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + +#if SPC5_ICU_USE_EMIOS + +#if SPC5_EMIOS_NUM_CHANNELS == 16 + INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY; +#endif + +#if SPC5_EMIOS_NUM_CHANNELS == 24 + INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F7_NUMBER].R = SPC5_EMIOS_FLAG_F7_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F16_NUMBER].R = SPC5_EMIOS_FLAG_F16_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F17_NUMBER].R = SPC5_EMIOS_FLAG_F17_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F18_NUMBER].R = SPC5_EMIOS_FLAG_F18_PRIORITY; +#endif + +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "icu_lld_start(), #1", "too many channels"); + + if (icup->state == ICU_STOP) { + /* Enables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS_CH0 + if (&ICUD1 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ +#if SPC5_ICU_USE_EMIOS_CH1 + if (&ICUD2 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ +#if SPC5_ICU_USE_EMIOS_CH2 + if (&ICUD3 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ +#if SPC5_ICU_USE_EMIOS_CH3 + if (&ICUD4 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ +#if SPC5_ICU_USE_EMIOS_CH4 + if (&ICUD5 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ +#if SPC5_ICU_USE_EMIOS_CH5 + if (&ICUD6 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ +#if SPC5_ICU_USE_EMIOS_CH6 + if (&ICUD7 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ +#if SPC5_ICU_USE_EMIOS_CH8 + if (&ICUD8 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ +#if SPC5_ICU_USE_EMIOS_CH7 + if (&ICUD9 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ +#if SPC5_ICU_USE_EMIOS_CH16 + if (&ICUD10 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ +#if SPC5_ICU_USE_EMIOS_CH17 + if (&ICUD11 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ +#if SPC5_ICU_USE_EMIOS_CH18 + if (&ICUD12 == icup) + increase_emios_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + + /* Set eMIOS Clock.*/ +#if SPC5_ICU_USE_EMIOS + active_emios_clock(icup, NULL); +#endif + + } + /* Configures the peripheral.*/ + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set clock prescaler and control register.*/ + uint32_t psc = (icup->clock / icup->config->frequency); + chDbgAssert((psc <= 4) && + ((psc * icup->config->frequency) == icup->clock) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "icu_lld_start(), #1", "invalid frequency"); + + icup->emiosp->CH[icup->ch_number].CCR.B.UCPREN = 0; + icup->emiosp->CH[icup->ch_number].CCR.R |= + EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | + EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC; + icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1; + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN; + + /* Set source polarity.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) { + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL; + } else { + icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL; + } + + /* Direct pointers to the period and width registers in order to make + reading data faster from within callbacks.*/ + icup->pccrp = . + icup->wccrp = &width; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "icu_lld_stop(), #1", "too many channels"); + + if (icup->state == ICU_READY) { + + /* Disables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS_CH0 + if (&ICUD1 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH0 */ +#if SPC5_ICU_USE_EMIOS_CH1 + if (&ICUD2 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH1 */ +#if SPC5_ICU_USE_EMIOS_CH2 + if (&ICUD3 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH2 */ +#if SPC5_ICU_USE_EMIOS_CH3 + if (&ICUD4 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH3 */ +#if SPC5_ICU_USE_EMIOS_CH4 + if (&ICUD5 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH4 */ +#if SPC5_ICU_USE_EMIOS_CH5 + if (&ICUD6 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH5 */ +#if SPC5_ICU_USE_EMIOS_CH6 + if (&ICUD7 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH6 */ +#if SPC5_ICU_USE_EMIOS_CH8 + if (&ICUD8 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH8 */ +#if SPC5_ICU_USE_EMIOS_CH7 + if (&ICUD9 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH7 */ +#if SPC5_ICU_USE_EMIOS_CH16 + if (&ICUD10 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH16 */ +#if SPC5_ICU_USE_EMIOS_CH17 + if (&ICUD11 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH17 */ +#if SPC5_ICU_USE_EMIOS_CH18 + if (&ICUD12 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS_CH18 */ + + /* eMIOS clock deactivation.*/ +#if SPC5_ICU_USE_EMIOS + deactive_emios_clock(); +#endif + + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Active interrupts.*/ + if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \ + icup->config->overflow_cb != NULL) { + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U; + } + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h new file mode 100644 index 000000000..1a1d24c3f --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h @@ -0,0 +1,443 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/icu_lld.h + * @brief SPC5xx low level icu driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH0) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH0 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH1) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH1 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH2) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH2 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH3) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH3 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH4) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH4 FALSE +#endif + +/** + * @brief ICUD6 driver enable switch. + * @details If set to @p TRUE the support for ICUD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH5) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH5 FALSE +#endif + +/** + * @brief ICUD7 driver enable switch. + * @details If set to @p TRUE the support for ICUD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH6) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH6 FALSE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH8) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH8 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH7) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH7 FALSE +#endif + +/** + * @brief ICUD10 driver enable switch. + * @details If set to @p TRUE the support for ICUD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH16) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH16 FALSE +#endif + +/** + * @brief ICUD11 driver enable switch. + * @details If set to @p TRUE the support for ICUD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH17) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH17 FALSE +#endif + +/** + * @brief ICUD12 driver enable switch. + * @details If set to @p TRUE the support for ICUD12 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS_CH18) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS_CH18 FALSE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F0_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F0_PRIORITY 7 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F1_PRIORITY 7 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F2_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F2_PRIORITY 7 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F3_PRIORITY 7 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F4_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F4_PRIORITY 7 +#endif + +/** + * @brief ICUD6 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F5_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F5_PRIORITY 7 +#endif + +/** + * @brief ICUD7 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F6_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F6_PRIORITY 7 +#endif + +/** + * @brief ICUD8 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F8_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F8_PRIORITY 7 +#endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F7_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F7_PRIORITY 7 +#endif + +/** + * @brief ICUD10 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F16_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F16_PRIORITY 7 +#endif + +/** + * @brief ICUD11 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F17_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F17_PRIORITY 7 +#endif + +/** + * @brief ICUD12 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F18_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F18_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS +#error "EMIOS not present in the selected device" +#endif + +#define SPC5_ICU_USE_EMIOS (SPC5_ICU_USE_EMIOS_CH0 || \ + SPC5_ICU_USE_EMIOS_CH1 || \ + SPC5_ICU_USE_EMIOS_CH2 || \ + SPC5_ICU_USE_EMIOS_CH3 || \ + SPC5_ICU_USE_EMIOS_CH4 || \ + SPC5_ICU_USE_EMIOS_CH5 || \ + SPC5_ICU_USE_EMIOS_CH6 || \ + SPC5_ICU_USE_EMIOS_CH7 || \ + SPC5_ICU_USE_EMIOS_CH8 || \ + SPC5_ICU_USE_EMIOS_CH16 || \ + SPC5_ICU_USE_EMIOS_CH17 || \ + SPC5_ICU_USE_EMIOS_CH18) + +#if !SPC5_ICU_USE_EMIOS +#error "ICU driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint32_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief eMIOSx channel number. + */ + uint32_t ch_number; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; + /** + * @brief CH Counter clock. + */ + uint32_t clock; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; + /** + * @brief CCR register used for width capture. + */ + volatile vuint32_t *wccrp; + /** + * @brief CCR register used for period capture. + */ + volatile vuint32_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS_CH0 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if SPC5_ICU_USE_EMIOS_CH1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if SPC5_ICU_USE_EMIOS_CH2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if SPC5_ICU_USE_EMIOS_CH3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if SPC5_ICU_USE_EMIOS_CH4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if SPC5_ICU_USE_EMIOS_CH5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD6; +#endif + +#if SPC5_ICU_USE_EMIOS_CH6 && !defined(__DOXYGEN__) +extern ICUDriver ICUD7; +#endif + +#if SPC5_ICU_USE_EMIOS_CH8 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#if SPC5_ICU_USE_EMIOS_CH7 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#if SPC5_ICU_USE_EMIOS_CH16 && !defined(__DOXYGEN__) +extern ICUDriver ICUD10; +#endif + +#if SPC5_ICU_USE_EMIOS_CH17 && !defined(__DOXYGEN__) +extern ICUDriver ICUD11; +#endif + +#if SPC5_ICU_USE_EMIOS_CH18 && !defined(__DOXYGEN__) +extern ICUDriver ICUD12; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c new file mode 100644 index 000000000..b5538f60c --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c @@ -0,0 +1,951 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/pwm_lld.c + * @brief SPC5xx low level pwm driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the unified channel EMIOS_CH9 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH9 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the unified channel EMIOS_CH10 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH10 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the unified channel EMIOS_CH11 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH11 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the unified channel EMIOS_CH12 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH12 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the unified channel EMIOS_CH13 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH13 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD6 driver identifier. + * @note The driver PWMD6 allocates the unified channel EMIOS_CH14 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH14 || defined(__DOXYGEN__) +PWMDriver PWMD6; +#endif + +/** + * @brief PWMD7 driver identifier. + * @note The driver PWMD7 allocates the unified channel EMIOS_CH15 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH15 || defined(__DOXYGEN__) +PWMDriver PWMD7; +#endif + +/** + * @brief PWMD8 driver identifier. + * @note The driver PWMD8 allocates the unified channel EMIOS_CH23 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH23 || defined(__DOXYGEN__) +PWMDriver PWMD8; +#endif + +/** + * @brief PWMD9 driver identifier. + * @note The driver PWMD9 allocates the unified channel EMIOS_CH19 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH19 || defined(__DOXYGEN__) +PWMDriver PWMD9; +#endif + +/** + * @brief PWMD10 driver identifier. + * @note The driver PWMD10 allocates the unified channel EMIOS_CH20 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH20 || defined(__DOXYGEN__) +PWMDriver PWMD10; +#endif + +/** + * @brief PWMD11 driver identifier. + * @note The driver PWMD11 allocates the unified channel EMIOS_CH21 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH21 || defined(__DOXYGEN__) +PWMDriver PWMD11; +#endif + +/** + * @brief PWMD12 driver identifier. + * @note The driver PWMD12 allocates the unified channel EMIOS_CH22 + * when enabled. + */ +#if SPC5_PWM_USE_EMIOS_CH22 || defined(__DOXYGEN__) +PWMDriver PWMD12; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief PWM IRQ handler. + * + * @param[in] pwmp pointer to the @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + + uint32_t sr = pwmp->emiosp->CH[pwmp->ch_number].CSR.R; + + if (sr && EMIOSS_OVFL) { + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVFLC; + } + if (sr && EMIOSS_OVR) { + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVRC; + } + if (sr && EMIOSS_FLAG) { + pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_FLAGC; + + if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) { + if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \ + pwmp->config->callback != NULL) { + pwmp->config->callback(pwmp); + } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \ + pwmp->config->channels[0].callback != NULL) { + pwmp->config->channels[0].callback(pwmp); + } + } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) { + if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \ + pwmp->config->callback != NULL) { + pwmp->config->callback(pwmp); + } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \ + pwmp->config->channels[0].callback != NULL) { + pwmp->config->channels[0].callback(pwmp); + } + } + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS_CH9 +#if !defined(SPC5_EMIOS_FLAG_F9_HANDLER) +#error "SPC5_EMIOS_FLAG_F9_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 +#if !defined(SPC5_EMIOS_FLAG_F10_HANDLER) +#error "SPC5_EMIOS_FLAG_F10_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 10 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F10_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 +#if !defined(SPC5_EMIOS_FLAG_F11_HANDLER) +#error "SPC5_EMIOS_FLAG_F11_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 11 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 +#if !defined(SPC5_EMIOS_FLAG_F12_HANDLER) +#error "SPC5_EMIOS_FLAG_F12_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 12 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F12_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 +#if !defined(SPC5_EMIOS_FLAG_F13_HANDLER) +#error "SPC5_EMIOS_FLAG_F13_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 13 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F13_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 +#if !defined(SPC5_EMIOS_FLAG_F14_HANDLER) +#error "SPC5_EMIOS_FLAG_F14_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 14 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F14_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 +#if !defined(SPC5_EMIOS_FLAG_F15_HANDLER) +#error "SPC5_EMIOS_FLAG_F15_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 15 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH19 +#if !defined(SPC5_EMIOS_FLAG_F19_HANDLER) +#error "SPC5_EMIOS_FLAG_F19_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 19 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F19_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 +#if !defined(SPC5_EMIOS_FLAG_F20_HANDLER) +#error "SPC5_EMIOS_FLAG_F20_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 20 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F20_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD10); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 +#if !defined(SPC5_EMIOS_FLAG_F21_HANDLER) +#error "SPC5_EMIOS_FLAG_F21_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 21 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F21_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 +#if !defined(SPC5_EMIOS_FLAG_F22_HANDLER) +#error "SPC5_EMIOS_FLAG_F22_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 22 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F22_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + +#if SPC5_PWM_USE_EMIOS_CH23 +#if !defined(SPC5_EMIOS_FLAG_F23_HANDLER) +#error "SPC5_EMIOS_FLAG_F23_HANDLER not defined" +#endif +/** + * @brief EMIOS Channel 23 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F23_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + /* eMIOSx channels initially all not in use.*/ + reset_emios_active_channels(); + +#if SPC5_PWM_USE_EMIOS_CH9 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.emiosp = &EMIOS; + PWMD1.ch_number = 9U; +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.emiosp = &EMIOS; + PWMD2.ch_number = 10U; +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.emiosp = &EMIOS; + PWMD3.ch_number = 11U; +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.emiosp = &EMIOS; + PWMD4.ch_number = 12U; +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.emiosp = &EMIOS; + PWMD5.ch_number = 13U; +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + /* Driver initialization.*/ + pwmObjectInit(&PWMD6); + PWMD6.emiosp = &EMIOS; + PWMD6.ch_number = 14U; +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + /* Driver initialization.*/ + pwmObjectInit(&PWMD7); + PWMD7.emiosp = &EMIOS; + PWMD7.ch_number = 15U; +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + /* Driver initialization.*/ + pwmObjectInit(&PWMD8); + PWMD8.emiosp = &EMIOS; + PWMD8.ch_number = 23U; +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + /* Driver initialization.*/ + pwmObjectInit(&PWMD9); + PWMD9.emiosp = &EMIOS; + PWMD9.ch_number = 19U; +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + /* Driver initialization.*/ + pwmObjectInit(&PWMD10); + PWMD10.emiosp = &EMIOS; + PWMD10.ch_number = 20U; +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + /* Driver initialization.*/ + pwmObjectInit(&PWMD11); + PWMD11.emiosp = &EMIOS; + PWMD11.ch_number = 21U; +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + /* Driver initialization.*/ + pwmObjectInit(&PWMD12); + PWMD12.emiosp = &EMIOS; + PWMD12.ch_number = 22U; +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + +#if SPC5_PWM_USE_EMIOS + +#if SPC5_EMIOS_NUM_CHANNELS == 16 + INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY; +#endif + +#if SPC5_EMIOS_NUM_CHANNELS == 24 + INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F19_NUMBER].R = SPC5_EMIOS_FLAG_F19_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F20_NUMBER].R = SPC5_EMIOS_FLAG_F20_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F21_NUMBER].R = SPC5_EMIOS_FLAG_F21_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F22_NUMBER].R = SPC5_EMIOS_FLAG_F22_PRIORITY; + INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY; +#endif + +#endif + +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + uint32_t psc = 0; + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "pwm_lld_start(), #1", "too many channels"); + + if (pwmp->state == PWM_STOP) { +#if SPC5_PWM_USE_EMIOS_CH9 + if (&PWMD1 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + if (&PWMD2 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + if (&PWMD3 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + if (&PWMD4 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + if (&PWMD5 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + if (&PWMD6 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + if (&PWMD7 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + if (&PWMD8 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + if (&PWMD9 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + if (&PWMD10 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + if (&PWMD11 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + if (&PWMD12 == pwmp) { + increase_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + + /* Set eMIOS Clock.*/ +#if SPC5_PWM_USE_EMIOS + active_emios_clock(NULL, pwmp); +#endif + + } + /* Configures the peripheral.*/ + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set clock prescaler and control register.*/ + psc = (SPC5_EMIOS_CLK / pwmp->config->frequency); + chDbgAssert((psc <= 0xFFFF) && + (((psc) * pwmp->config->frequency) == SPC5_EMIOS_CLK) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "pwm_lld_start(), #1", "invalid frequency"); + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 0; + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 1U; + pwmp->emiosp->CH[pwmp->ch_number].CCNTR.R = 1U; + pwmp->emiosp->CH[pwmp->ch_number].CADR.R = 0U; + pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = pwmp->config->period; + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= + EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | EMIOS_CCR_MODE_OPWFMB | 2U; + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_UCPREN; + + /* Set output polarity.*/ + if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_EDPOL; + } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.R &= ~EMIOSC_EDPOL; + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number); + + } else if (pwmp->config->mode == PWM_ALIGN_CENTER) { + /* Not implemented.*/ + } + +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS, + "pwm_lld_stop(), #1", "too many channels"); + + if (pwmp->state == PWM_READY) { + + /* Disables the peripheral.*/ +#if SPC5_PWM_USE_EMIOS_CH9 + if (&PWMD1 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH9 */ + +#if SPC5_PWM_USE_EMIOS_CH10 + if (&PWMD2 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH10 */ + +#if SPC5_PWM_USE_EMIOS_CH11 + if (&PWMD3 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH11 */ + +#if SPC5_PWM_USE_EMIOS_CH12 + if (&PWMD4 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH12 */ + +#if SPC5_PWM_USE_EMIOS_CH13 + if (&PWMD5 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH13 */ + +#if SPC5_PWM_USE_EMIOS_CH14 + if (&PWMD6 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH14 */ + +#if SPC5_PWM_USE_EMIOS_CH15 + if (&PWMD7 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH15 */ + +#if SPC5_PWM_USE_EMIOS_CH23 + if (&PWMD8 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH23 */ + +#if SPC5_PWM_USE_EMIOS_CH19 + if (&PWMD9 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH19 */ + +#if SPC5_PWM_USE_EMIOS_CH20 + if (&PWMD10 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH20 */ + +#if SPC5_PWM_USE_EMIOS_CH21 + if (&PWMD11 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH21 */ + +#if SPC5_PWM_USE_EMIOS_CH22 + if (&PWMD12 == pwmp) { + /* Reset UC Control Register.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0; + + decrease_emios_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS_CH22 */ + + /* eMIOS clock deactivation.*/ +#if SPC5_PWM_USE_EMIOS + deactive_emios_clock(); +#endif + + } +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + + pwmp->period = period; + pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = period; + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + (void)channel; + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set pwm width.*/ + pwmp->emiosp->CH[pwmp->ch_number].CADR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL || \ + pwmp->config->channels[0].callback != NULL) { + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 1U; + } + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number); + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + (void)channel; + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 0; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number); + +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h new file mode 100644 index 000000000..fa7417844 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h @@ -0,0 +1,457 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/pwm_lld.h + * @brief SPC5xx low level pwm driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 1 + +/** + * @brief Edge-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_EDGE 0x00 + +/** + * @brief Center-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_CENTER 0x01 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH9) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH9 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH10) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH10 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH11) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH11 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH12) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH12 FALSE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH13) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH13 FALSE +#endif + +/** + * @brief PWMD6 driver enable switch. + * @details If set to @p TRUE the support for PWMD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH14) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH14 FALSE +#endif + +/** + * @brief PWMD7 driver enable switch. + * @details If set to @p TRUE the support for PWMD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH15) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH15 FALSE +#endif + +/** + * @brief PWMD8 driver enable switch. + * @details If set to @p TRUE the support for PWMD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH23) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH23 FALSE +#endif + +/** + * @brief PWMD9 driver enable switch. + * @details If set to @p TRUE the support for PWMD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH19) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH19 FALSE +#endif + +/** + * @brief PWMD10 driver enable switch. + * @details If set to @p TRUE the support for PWMD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH20) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH20 FALSE +#endif + +/** + * @brief PWMD11 driver enable switch. + * @details If set to @p TRUE the support for PWMD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH21) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH21 FALSE +#endif + +/** + * @brief PWMD12 driver enable switch. + * @details If set to @p TRUE the support for PWMD12 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS_CH22) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS_CH22 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F9_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F9_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F10_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F10_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F11_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F11_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F12_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F12_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F13_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F13_PRIORITY 7 +#endif + +/** + * @brief PWMD6 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F14_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F14_PRIORITY 7 +#endif + +/** + * @brief PWMD7 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F15_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F15_PRIORITY 7 +#endif + +/** + * @brief PWMD8 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F23_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F23_PRIORITY 7 +#endif + +/** + * @brief PWMD9 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F19_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F19_PRIORITY 7 +#endif + +/** + * @brief PWMD10 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F20_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F20_PRIORITY 7 +#endif + +/** + * @brief PWMD11 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F21_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F21_PRIORITY 7 +#endif + +/** + * @brief PWMD12 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS_FLAG_F22_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS_FLAG_F22_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS +#error "EMIOS not present in the selected device" +#endif + +#define SPC5_PWM_USE_EMIOS (SPC5_PWM_USE_EMIOS_CH9 || \ + SPC5_PWM_USE_EMIOS_CH10 || \ + SPC5_PWM_USE_EMIOS_CH11 || \ + SPC5_PWM_USE_EMIOS_CH12 || \ + SPC5_PWM_USE_EMIOS_CH13 || \ + SPC5_PWM_USE_EMIOS_CH14 || \ + SPC5_PWM_USE_EMIOS_CH15 || \ + SPC5_PWM_USE_EMIOS_CH19 || \ + SPC5_PWM_USE_EMIOS_CH20 || \ + SPC5_PWM_USE_EMIOS_CH21 || \ + SPC5_PWM_USE_EMIOS_CH22 || \ + SPC5_PWM_USE_EMIOS_CH23) + +#if !SPC5_PWM_USE_EMIOS +#error "PWM driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief PWM functional mode. + */ + pwmmode_t mode; +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief eMIOSx channel number. + */ + uint8_t ch_number; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS_CH9 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if SPC5_PWM_USE_EMIOS_CH10 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if SPC5_PWM_USE_EMIOS_CH11 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if SPC5_PWM_USE_EMIOS_CH12 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if SPC5_PWM_USE_EMIOS_CH13 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if SPC5_PWM_USE_EMIOS_CH14 && !defined(__DOXYGEN__) +extern PWMDriver PWMD6; +#endif + +#if SPC5_PWM_USE_EMIOS_CH15 && !defined(__DOXYGEN__) +extern PWMDriver PWMD7; +#endif + +#if SPC5_PWM_USE_EMIOS_CH23 && !defined(__DOXYGEN__) +extern PWMDriver PWMD8; +#endif + +#if SPC5_PWM_USE_EMIOS_CH19 && !defined(__DOXYGEN__) +extern PWMDriver PWMD9; +#endif + +#if SPC5_PWM_USE_EMIOS_CH20 && !defined(__DOXYGEN__) +extern PWMDriver PWMD10; +#endif + +#if SPC5_PWM_USE_EMIOS_CH21 && !defined(__DOXYGEN__) +extern PWMDriver PWMD11; +#endif + +#if SPC5_PWM_USE_EMIOS_CH22 && !defined(__DOXYGEN__) +extern PWMDriver PWMD12; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c new file mode 100644 index 000000000..0533b50e3 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c @@ -0,0 +1,117 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/spc5_emios.c + * @brief eMIOS200 helper driver code. + * + * @addtogroup SPC5xx_eMIOS200 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Number of active eMIOSx Channels. + */ +static uint32_t emios_active_channels; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +void reset_emios_active_channels() { + emios_active_channels = 0; +} + +uint32_t get_emios_active_channels() { + return emios_active_channels; +} + +void increase_emios_active_channels() { + emios_active_channels++; +} + +void decrease_emios_active_channels() { + emios_active_channels--; +} + +void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If this is the first Channel activated then the eMIOS0 is enabled.*/ + if (emios_active_channels == 1) { + SPC5_EMIOS_ENABLE_CLOCK(); + + /* Disable all unified channels.*/ + if (icup != NULL) { + icup->emiosp->MCR.B.GPREN = 0; + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER); + icup->emiosp->MCR.R |= EMIOSMCR_GPREN; + + icup->emiosp->MCR.B.GTBE = 1U; + + icup->emiosp->UCDIS.R = 0xFFFFFFFF; + + } else if (pwmp != NULL) { + pwmp->emiosp->MCR.B.GPREN = 0; + pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER); + pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN; + + pwmp->emiosp->MCR.B.GTBE = 1U; + + pwmp->emiosp->UCDIS.R = 0xFFFFFFFF; + + } + + } +} + +void deactive_emios_clock() { + /* If it is the last active channels then the eMIOS0 is disabled.*/ + if (emios_active_channels == 0) { + SPC5_EMIOS_DISABLE_CLOCK(); + + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +#endif /* HAL_USE_ICU || HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h new file mode 100644 index 000000000..97bff1ce9 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h @@ -0,0 +1,115 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC5xx/eMIOS200_v1/spc5_emios.h + * @brief eMIOS200 helper driver header. + * + * @addtogroup SPC5xx_eMIOS200 + * @{ + */ + +#ifndef _SPC5_EMIOS_H_ +#define _SPC5_EMIOS_H_ + +#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EMIOSMCR_MDIS (1 << 30) +#define EMIOSMCR_FRZ (1 << 29) +#define EMIOSMCR_GTBE (1 << 28) +#define EMIOSMCR_GPREN (1 << 26) +#define EMIOSMCR_GPRE(n) ((n) << 8) + +#define EMIOSC_FREN (1 << 31) +#define EMIOSC_UCPRE(n) ((n) << 26) +#define EMIOSC_UCPREN (1 << 25) +#define EMIOSC_DMA (1 << 24) +#define EMIOSC_IF(n) ((n) << 19) +#define EMIOSC_FCK (1 << 18) +#define EMIOSC_FEN (1 << 17) +#define EMIOSC_FORCMA (1 << 13) +#define EMIOSC_FORCMB (1 << 12) +#define EMIOSC_BSL(n) ((n) << 9) +#define EMIOSC_EDSEL (1 << 8) +#define EMIOSC_EDPOL (1 << 7) +#define EMIOSC_MODE(n) ((n) << 0) + +#define EMIOS_BSL_COUNTER_BUS_A 0 +#define EMIOS_BSL_COUNTER_BUS_2 1 +#define EMIOS_BSL_INTERNAL_COUNTER 3 + +#define EMIOS_CCR_MODE_GPIO_IN 0 +#define EMIOS_CCR_MODE_GPIO_OUT 1 +#define EMIOS_CCR_MODE_SAIC 2 +#define EMIOS_CCR_MODE_SAOC 3 +#define EMIOS_CCR_MODE_IPWM 4 +#define EMIOS_CCR_MODE_IPM 5 +#define EMIOS_CCR_MODE_DAOC_B_MATCH 6 +#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7 +#define EMIOS_CCR_MODE_MC_CMS 16 +#define EMIOS_CCR_MODE_MC_CME 17 +#define EMIOS_CCR_MODE_MC_UP_DOWN 18 +#define EMIOS_CCR_MODE_OPWMT 38 +#define EMIOS_CCR_MODE_MCB_UP 80 +#define EMIOS_CCR_MODE_MCB_UP_DOWN 84 +#define EMIOS_CCR_MODE_OPWFMB 88 +#define EMIOS_CCR_MODE_OPWMCB_TE 92 +#define EMIOS_CCR_MODE_OPWMCB_LE 93 +#define EMIOS_CCR_MODE_OPWMB 96 + +#define EMIOSS_OVR (1 << 31) +#define EMIOSS_OVRC (1 << 31) +#define EMIOSS_OVFL (1 << 15) +#define EMIOSS_OVFLC (1 << 15) +#define EMIOSS_FLAG (1 << 0) +#define EMIOSS_FLAGC (1 << 0) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +void reset_emios_active_channels(void); +uint32_t get_emios_active_channels(void);; +void increase_emios_active_channels(void); +void decrease_emios_active_channels(void); +void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp); +void deactive_emios_clock(void); + +#endif /* HAL_USE_ICU || HAL_USE_PWM */ + +#endif /* _SPC5_EMIOS_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c new file mode 100644 index 000000000..a8167c69c --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c @@ -0,0 +1,783 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/icu_lld.c + * @brief SPC5xx low level ICU driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the unified channel eMIOS0_CH0 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH0 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD2 allocates the unified channel eMIOS0_CH1 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH1 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD3 allocates the unified channel eMIOS0_CH2 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH2 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the unified channel eMIOS0_CH3 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH3 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the unified channel eMIOS0_CH4 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH4 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD6 driver identifier. + * @note The driver ICUD6 allocates the unified channel eMIOS0_CH5 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH5 || defined(__DOXYGEN__) +ICUDriver ICUD6; +#endif + +/** + * @brief ICUD7 driver identifier. + * @note The driver ICUD7 allocates the unified channel eMIOS0_CH6 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH6 || defined(__DOXYGEN__) +ICUDriver ICUD7; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the unified channel eMIOS0_CH7 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH7 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the unified channel eMIOS0_CH24 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS0_CH24 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/** + * @brief ICUD10 driver identifier. + * @note The driver ICUD10 allocates the unified channel eMIOS1_CH24 + * when enabled. + */ +#if SPC5_ICU_USE_EMIOS1_CH24 || defined(__DOXYGEN__) +ICUDriver ICUD10; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Width and Period registers. + */ +int16_t width; +int16_t period; + +/** + * @brief A2 temp registers. + */ +uint16_t A2_1, A2_2, A2_3; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ICU IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + uint32_t gfr = icup->emiosp->GFR.R; + + if (gfr && (1 << icup->ch_number)) { + uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R; + + if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC; + _icu_isr_invoke_overflow_cb(icup); + } + if (sr && EMIOSS_FLAG){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC; + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } + } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) { + if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \ + icup->config->width_cb != NULL) { + A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R; + width = A2_2 - A2_1; + _icu_isr_invoke_width_cb(icup); + } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \ + icup->config->period_cb != NULL) { + A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R; + period = A2_3 - A2_1; + _icu_isr_invoke_period_cb(icup); + A2_1 = A2_3; + } + } + } + if(sr && EMIOSS_OVR){ + icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC; + } + + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 +#if !defined(SPC5_EMIOS0_GFR_F0F1_HANDLER) +#error "SPC5_EMIOS0_GFR_F0F1_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 0 and 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F0F1_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS0_CH0 + icu_lld_serve_interrupt(&ICUD1); +#endif + +#if SPC5_ICU_USE_EMIOS0_CH1 + icu_lld_serve_interrupt(&ICUD2); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 */ + +#if SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 +#if !defined(SPC5_EMIOS0_GFR_F2F3_HANDLER) +#error "SPC5_EMIOS0_GFR_F2F3_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 2 and 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F2F3_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS0_CH2 + icu_lld_serve_interrupt(&ICUD3); +#endif + +#if SPC5_ICU_USE_EMIOS0_CH3 + icu_lld_serve_interrupt(&ICUD4); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 */ + +#if SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 +#if !defined(SPC5_EMIOS0_GFR_F4F5_HANDLER) +#error "SPC5_EMIOS0_GFR_F4F5_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 4 and 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F4F5_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS0_CH4 + icu_lld_serve_interrupt(&ICUD5); +#endif + +#if SPC5_ICU_USE_EMIOS0_CH5 + icu_lld_serve_interrupt(&ICUD6); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 */ + +#if SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 + +#if !defined(SPC5_EMIOS0_GFR_F6F7_HANDLER) +#error "SPC5_EMIOS0_GFR_F6F7_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 6 and 7 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F6F7_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS0_CH6 + icu_lld_serve_interrupt(&ICUD7); +#endif + +#if SPC5_ICU_USE_EMIOS0_CH7 + icu_lld_serve_interrupt(&ICUD8); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 */ + +#if SPC5_ICU_USE_EMIOS0_CH24 +#if !defined(SPC5_EMIOS0_GFR_F24F25_HANDLER) +#error "SPC5_EMIOS0_GFR_F24F25_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 24 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F24F25_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS0_CH24 + icu_lld_serve_interrupt(&ICUD9); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS0_CH24 */ + +#if SPC5_ICU_USE_EMIOS1_CH24 +#if !defined(SPC5_EMIOS1_GFR_F24F25_HANDLER) +#error "SPC5_EMIOS1_GFR_F24F25_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 24 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F24F25_HANDLER) { + + CH_IRQ_PROLOGUE(); + +#if SPC5_ICU_USE_EMIOS1_CH24 + icu_lld_serve_interrupt(&ICUD10); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_EMIOS1_CH24 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + + /* Initialize A2 temp registers.*/ + A2_1 = 0U; + A2_2 = 0U; + A2_3 = 0U; + + /* eMIOSx channels initially all not in use.*/ + reset_emios0_active_channels(); + reset_emios1_active_channels(); + +#if SPC5_ICU_USE_EMIOS0_CH0 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.emiosp = &EMIOS_0; + ICUD1.ch_number = 0U; + ICUD1.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH0 */ + +#if SPC5_ICU_USE_EMIOS0_CH1 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.emiosp = &EMIOS_0; + ICUD2.ch_number = 1U; + ICUD2.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH1 */ + +#if SPC5_ICU_USE_EMIOS0_CH2 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.emiosp = &EMIOS_0; + ICUD3.ch_number = 2U; + ICUD3.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH2 */ + +#if SPC5_ICU_USE_EMIOS0_CH3 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.emiosp = &EMIOS_0; + ICUD4.ch_number = 3U; + ICUD4.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH3 */ + +#if SPC5_ICU_USE_EMIOS0_CH4 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.emiosp = &EMIOS_0; + ICUD5.ch_number = 4U; + ICUD5.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH4 */ + +#if SPC5_ICU_USE_EMIOS0_CH5 + /* Driver initialization.*/ + icuObjectInit(&ICUD6); + ICUD6.emiosp = &EMIOS_0; + ICUD6.ch_number = 5U; + ICUD6.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH5 */ + +#if SPC5_ICU_USE_EMIOS0_CH6 + /* Driver initialization.*/ + icuObjectInit(&ICUD7); + ICUD7.emiosp = &EMIOS_0; + ICUD7.ch_number = 6U; + ICUD7.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH6 */ + +#if SPC5_ICU_USE_EMIOS0_CH7 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.emiosp = &EMIOS_0; + ICUD8.ch_number = 7U; + ICUD8.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH7 */ + +#if SPC5_ICU_USE_EMIOS0_CH24 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.emiosp = &EMIOS_0; + ICUD9.ch_number = 24U; + ICUD9.clock = SPC5_EMIOS0_CLK; +#endif /* SPC5_ICU_USE_EMIOS0_CH24 */ + +#if SPC5_ICU_USE_EMIOS1_CH24 + /* Driver initialization.*/ + icuObjectInit(&ICUD10); + ICUD10.emiosp = &EMIOS_1; + ICUD10.ch_number = 24U; + ICUD10.clock = SPC5_EMIOS1_CLK; +#endif /* SPC5_ICU_USE_EMIOS1_CH24 */ + +#if SPC5_ICU_USE_EMIOS0 + + INTC.PSR[SPC5_EMIOS0_GFR_F0F1_NUMBER].R = SPC5_EMIOS0_GFR_F0F1_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F2F3_NUMBER].R = SPC5_EMIOS0_GFR_F2F3_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F4F5_NUMBER].R = SPC5_EMIOS0_GFR_F4F5_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F6F7_NUMBER].R = SPC5_EMIOS0_GFR_F6F7_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F24F25_NUMBER].R = SPC5_EMIOS0_GFR_F24F25_PRIORITY; + +#endif + +#if SPC5_ICU_USE_EMIOS1 + + INTC.PSR[SPC5_EMIOS1_GFR_F24F25_NUMBER].R = SPC5_EMIOS1_GFR_F24F25_PRIORITY; + +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + //uint32_t emios0_active_channels = get_emios0_active_channels(); + //uint32_t emios1_active_channels = get_emios1_active_channels(); + + chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1", + "too many channels"); + + chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2", + "too many channels"); + + if (icup->state == ICU_STOP) { + /* Enables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS0_CH0 + if (&ICUD1 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH0 */ +#if SPC5_ICU_USE_EMIOS0_CH1 + if (&ICUD2 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH1 */ +#if SPC5_ICU_USE_EMIOS0_CH2 + if (&ICUD3 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH2 */ +#if SPC5_ICU_USE_EMIOS0_CH3 + if (&ICUD4 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH3 */ +#if SPC5_ICU_USE_EMIOS0_CH4 + if (&ICUD5 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH4 */ +#if SPC5_ICU_USE_EMIOS0_CH5 + if (&ICUD6 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH5 */ +#if SPC5_ICU_USE_EMIOS0_CH6 + if (&ICUD7 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH6 */ +#if SPC5_ICU_USE_EMIOS0_CH7 + if (&ICUD8 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH7 */ +#if SPC5_ICU_USE_EMIOS0_CH24 + if (&ICUD9 == icup) + increase_emios0_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS0_CH24 */ +#if SPC5_ICU_USE_EMIOS1_CH24 + if (&ICUD10 == icup) + increase_emios1_active_channels(); +#endif /* SPC5_ICU_USE_EMIOS1_CH24 */ + + /* Set eMIOS0 Clock.*/ +#if SPC5_ICU_USE_EMIOS0 + active_emios0_clock(icup, NULL); +#endif + + /* Set eMIOS1 Clock.*/ +#if SPC5_ICU_USE_EMIOS1 + active_emios1_clock(icup, NULL); +#endif + + } + /* Configures the peripheral.*/ + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Set clock prescaler and control register.*/ + uint32_t psc = (icup->clock / icup->config->frequency); + chDbgAssert((psc <= 0xFFFF) && + (((psc) * icup->config->frequency) == icup->clock) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "icu_lld_start(), #1", "invalid frequency"); + + //icup->emiosp->MCR.B.GPREN = 0; + icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0; + icup->emiosp->CH[icup->ch_number].CCR.R |= + EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | + EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC; + icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1; + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN; + /* + if (icup->emiosp == &EMIOS_0) { + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER); + } else if (icup->emiosp == &EMIOS_1) { + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER); + } + icup->emiosp->MCR.R |= EMIOSMCR_GPREN; + + icup->emiosp->MCR.B.GTBE = 1U; + */ + + /* Set source polarity.*/ + if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){ + icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL; + } else { + icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL; + } + + /* Direct pointers to the period and width registers in order to make + reading data faster from within callbacks.*/ + icup->pccrp = . + icup->wccrp = &width; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + //uint32_t emios0_active_channels = get_emios0_active_channels(); + //uint32_t emios1_active_channels = get_emios1_active_channels(); + + chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1", + "too many channels"); + chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2", + "too many channels"); + + if (icup->state == ICU_READY) { + + /* Disables the peripheral.*/ +#if SPC5_ICU_USE_EMIOS0_CH0 + if (&ICUD1 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH0 */ +#if SPC5_ICU_USE_EMIOS0_CH1 + if (&ICUD2 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH1 */ +#if SPC5_ICU_USE_EMIOS0_CH2 + if (&ICUD3 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH2 */ +#if SPC5_ICU_USE_EMIOS0_CH3 + if (&ICUD4 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH3 */ +#if SPC5_ICU_USE_EMIOS0_CH4 + if (&ICUD5 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH4 */ +#if SPC5_ICU_USE_EMIOS0_CH5 + if (&ICUD6 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH5 */ +#if SPC5_ICU_USE_EMIOS0_CH6 + if (&ICUD7 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH6 */ +#if SPC5_ICU_USE_EMIOS0_CH7 + if (&ICUD8 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH7 */ +#if SPC5_ICU_USE_EMIOS0_CH24 + if (&ICUD9 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios0_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS0_CH24 */ +#if SPC5_ICU_USE_EMIOS1_CH24 + if (&ICUD10 == icup) { + /* Reset UC Control Register.*/ + icup->emiosp->CH[icup->ch_number].CCR.R = 0; + + decrease_emios1_active_channels(); + } +#endif /* SPC5_ICU_USE_EMIOS1_CH24 */ + + /* eMIOS0 clock deactivation.*/ +#if SPC5_ICU_USE_EMIOS0 + deactive_emios0_clock(icup, NULL); +#endif + + /* eMIOS1 clock deactivation.*/ +#if SPC5_ICU_USE_EMIOS1 + deactive_emios1_clock(icup, NULL); +#endif + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + /* Channel enables.*/ + /* + if (!(icup->emiosp->UCDIS.R && (1 << icup->ch_number))) { + + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + } + */ + + /* Channel enables.*/ + icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number); + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Active interrupts.*/ + if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \ + icup->config->overflow_cb != NULL) { + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U; + } + + + + /* Enable Global Time Base.*/ + /* + if (icup->emiosp->MCR.B.GTBE == 0) { + icup->emiosp->MCR.B.GTBE = 1U; + } + */ + +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0; + + /* Channel disables.*/ + icup->emiosp->UCDIS.R |= (1 << icup->ch_number); + +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h new file mode 100644 index 000000000..31921333c --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h @@ -0,0 +1,382 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/icu_lld.h + * @brief SPC5xx low level ICU driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__) +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH0) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH0 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH1) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH1 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH2) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH2 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH3) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH3 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH4) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH4 FALSE +#endif + +/** + * @brief ICUD6 driver enable switch. + * @details If set to @p TRUE the support for ICUD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH5) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH5 FALSE +#endif + +/** + * @brief ICUD7 driver enable switch. + * @details If set to @p TRUE the support for ICUD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH6) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH6 FALSE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH7) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH7 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS0_CH24) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS0_CH24 FALSE +#endif + +/** + * @brief ICUD1 and ICUD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7 +#endif + +/** + * @brief ICUD3 and ICUD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7 +#endif + +/** + * @brief ICUD5 and ICUD6 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7 +#endif + +/** + * @brief ICUD7 and ICUD8 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7 +#endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7 +#endif +#endif + +#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__) +/** + * @brief ICUD10 driver enable switch. + * @details If set to @p TRUE the support for ICUD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_EMIOS1_CH24) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_EMIOS1_CH24 FALSE +#endif + +/** + * @brief ICUD10 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7 +#endif +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS0 +#error "EMIOS0 not present in the selected device" +#endif + +#if !SPC5_HAS_EMIOS1 +#error "EMIOS1 not present in the selected device" +#endif + +#define SPC5_ICU_USE_EMIOS0 (SPC5_ICU_USE_EMIOS0_CH0 || \ + SPC5_ICU_USE_EMIOS0_CH1 || \ + SPC5_ICU_USE_EMIOS0_CH2 || \ + SPC5_ICU_USE_EMIOS0_CH3 || \ + SPC5_ICU_USE_EMIOS0_CH4 || \ + SPC5_ICU_USE_EMIOS0_CH5 || \ + SPC5_ICU_USE_EMIOS0_CH6 || \ + SPC5_ICU_USE_EMIOS0_CH7 || \ + SPC5_ICU_USE_EMIOS0_CH24) + +#define SPC5_ICU_USE_EMIOS1 SPC5_ICU_USE_EMIOS1_CH24 + +#if !SPC5_ICU_USE_EMIOS0 && !SPC5_ICU_USE_EMIOS1 +#error "ICU driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief eMIOSx channel number. + */ + uint32_t ch_number; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; + /** + * @brief CH Counter clock. + */ + uint32_t clock; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; + /** + * @brief CCR register used for width capture. + */ + volatile vint16_t *wccrp; + /** + * @brief CCR register used for period capture. + */ + volatile vint16_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_EMIOS0_CH0 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD6; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH6 && !defined(__DOXYGEN__) +extern ICUDriver ICUD7; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH7 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#if SPC5_ICU_USE_EMIOS0_CH24 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#if SPC5_ICU_USE_EMIOS1_CH24 && !defined(__DOXYGEN__) +extern ICUDriver ICUD10; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c new file mode 100644 index 000000000..f353b180a --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c @@ -0,0 +1,1759 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/pwm_lld.c + * @brief SPC5xx low level PWM driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the unified channels eMIOS0_CH8 - + * eMIOS0_CH15 when enabled. + */ +#if SPC5_PWM_USE_EMIOS0_GROUP0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the unified channels eMIOS0_CH16 - + * eMIOS0_CH23 when enabled. + */ +#if SPC5_PWM_USE_EMIOS0_GROUP1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the unified channels eMIOS1_CH0 - + * eMIOS1_CH7 when enabled. + */ +#if SPC5_PWM_USE_EMIOS1_GROUP0 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the unified channels eMIOS1_CH8 - + * eMIOS1_CH15 when enabled. + */ +#if SPC5_PWM_USE_EMIOS1_GROUP1 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the unified channels eMIOS1_CH16 - + * eMIOS1_CH23 when enabled. + */ +#if SPC5_PWM_USE_EMIOS1_GROUP2 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief PWM IRQ handler. + * + * @param[in] pwmp pointer to the @p PWMDriver object + */ +static void pwm_lld_serve_interrupt1(PWMDriver *pwmp, uint32_t index) { + + uint32_t sr = pwmp->emiosp->CH[index].CSR.R; + if (sr & EMIOSS_OVFL) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC; + } + if (sr & EMIOSS_OVR) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC; + } + if (sr & EMIOSS_FLAG) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC; + if (pwmp->config->callback != NULL) { + pwmp->config->callback(pwmp); + } + } + +} + +static void pwm_lld_serve_interrupt2(PWMDriver *pwmp, uint32_t index) { + + uint32_t sr = pwmp->emiosp->CH[index].CSR.R; + if (sr & EMIOSS_OVFL) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC; + } + if (sr & EMIOSS_OVR) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC; + } + if (sr & EMIOSS_FLAG) { + pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC; + if (pwmp->config->channels[index%8U - 1].callback != NULL) { + pwmp->config->channels[index%8U - 1].callback(pwmp); + } + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS0_GROUP0 +#if !defined(SPC5_EMIOS0_GFR_F8F9_HANDLER) +#error "SPC5_EMIOS0_GFR_F8F9_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 8 and 9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F8F9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD1.emiosp->GFR.R; + + if (gfr & (1U << 8U)) { + pwm_lld_serve_interrupt1(&PWMD1, 8U); + } + if (gfr & (1U << 9U)) { + pwm_lld_serve_interrupt2(&PWMD1, 9U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F10F11_HANDLER) +#error "SPC5_EMIOS0_GFR_F10F11_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 10 and 11 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F10F11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD1.emiosp->GFR.R; + + if (gfr & (1U << 10U)) { + pwm_lld_serve_interrupt2(&PWMD1, 10U); + } + if (gfr & (1U << 11U)) { + pwm_lld_serve_interrupt2(&PWMD1, 11U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F12F13_HANDLER) +#error "SPC5_EMIOS0_GFR_F12F13_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 12 and 13 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F12F13_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD1.emiosp->GFR.R; + + if (gfr & (1U << 12U)) { + pwm_lld_serve_interrupt2(&PWMD1, 12U); + } + if (gfr & (1U << 13U)) { + pwm_lld_serve_interrupt2(&PWMD1, 13U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F14F15_HANDLER) +#error "SPC5_EMIOS0_GFR_F14F15_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 14 and 15 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F14F15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD1.emiosp->GFR.R; + + if (gfr && (1U << 14U)) { + pwm_lld_serve_interrupt2(&PWMD1, 14U); + } + if (gfr && (1U << 15U)) { + pwm_lld_serve_interrupt2(&PWMD1, 15U); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS0_GROUP1 +#if !defined(SPC5_EMIOS0_GFR_F16F17_HANDLER) +#error "SPC5_EMIOS0_GFR_F16F17_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 16 and 17 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F16F17_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD2.emiosp->GFR.R; + + if (gfr && (1U << 16U)) { + pwm_lld_serve_interrupt1(&PWMD2, 16U); + } + if (gfr && (1U << 17U)) { + pwm_lld_serve_interrupt2(&PWMD2, 17U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F18F19_HANDLER) +#error "SPC5_EMIOS0_GFR_F18F19_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 18 and 19 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F18F19_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD2.emiosp->GFR.R; + + if (gfr && (1U << 18U)) { + pwm_lld_serve_interrupt2(&PWMD2, 18U); + } + if (gfr && (1U << 19U)) { + pwm_lld_serve_interrupt2(&PWMD2, 19U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F20F21_HANDLER) +#error "SPC5_EMIOS0_GFR_F20F21_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 20 and 21 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F20F21_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD2.emiosp->GFR.R; + + if (gfr && (1U << 20U)) { + pwm_lld_serve_interrupt2(&PWMD2, 20U); + } + if (gfr && (1U << 21U)) { + pwm_lld_serve_interrupt2(&PWMD2, 21U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS0_GFR_F22F23_HANDLER) +#error "SPC5_EMIOS0_GFR_F22F23_HANDLER not defined" +#endif +/** + * @brief eMIOS0 Channels 22 and 23 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F22F23_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD2.emiosp->GFR.R; + + if (gfr && (1U << 22U)) { + pwm_lld_serve_interrupt2(&PWMD2, 22U); + } + if (gfr && (1U << 23U)) { + pwm_lld_serve_interrupt2(&PWMD2, 23U); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP0 +#if !defined(SPC5_EMIOS1_GFR_F0F1_HANDLER) +#error "SPC5_EMIOS1_GFR_F0F1_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 0 and 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F0F1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD3.emiosp->GFR.R; + + if (gfr && (1U << 0)) { + pwm_lld_serve_interrupt1(&PWMD3, 0); + } + if (gfr && (1U << 1U)) { + pwm_lld_serve_interrupt2(&PWMD3, 1U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F2F3_HANDLER) +#error "SPC5_EMIOS1_GFR_F2F3_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 2 and 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F2F3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD3.emiosp->GFR.R; + + if (gfr && (1U << 2U)) { + pwm_lld_serve_interrupt2(&PWMD3, 2U); + } + if (gfr && (1U << 3U)) { + pwm_lld_serve_interrupt2(&PWMD3, 3U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F4F5_HANDLER) +#error "SPC5_EMIOS1_GFR_F4F5_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 4 and 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F4F5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD3.emiosp->GFR.R; + + if (gfr && (1U << 4U)) { + pwm_lld_serve_interrupt2(&PWMD3, 4U); + } + if (gfr && (1U << 5U)) { + pwm_lld_serve_interrupt2(&PWMD3, 5U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F6F7_HANDLER) +#error "SPC5_EMIOS1_GFR_F6F7_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 6 and 7 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F6F7_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD3.emiosp->GFR.R; + + if (gfr && (1U << 6U)) { + pwm_lld_serve_interrupt2(&PWMD3, 6U); + } + if (gfr && (1U << 7U)) { + pwm_lld_serve_interrupt2(&PWMD3, 7U); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP1 +#if !defined(SPC5_EMIOS1_GFR_F8F9_HANDLER) +#error "SPC5_EMIOS1_GFR_F8F9_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 8 and 9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F8F9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD4.emiosp->GFR.R; + + if (gfr && (1U << 8U)) { + pwm_lld_serve_interrupt1(&PWMD4, 8U); + } + if (gfr && (1U << 9U)) { + pwm_lld_serve_interrupt2(&PWMD4, 9U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F10F11_HANDLER) +#error "SPC5_EMIOS1_GFR_F10F11_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 10 and 11 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F10F11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD4.emiosp->GFR.R; + + if (gfr && (1U << 10U)) { + pwm_lld_serve_interrupt2(&PWMD4, 10U); + } + if (gfr && (1U << 11U)) { + pwm_lld_serve_interrupt2(&PWMD4, 11U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F12F13_HANDLER) +#error "SPC5_EMIOS1_GFR_F12F13_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 12 and 13 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F12F13_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD4.emiosp->GFR.R; + + if (gfr && (1U << 12U)) { + pwm_lld_serve_interrupt2(&PWMD4, 12U); + } + if (gfr && (1U << 13U)) { + pwm_lld_serve_interrupt2(&PWMD4, 13U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F14F15_HANDLER) +#error "SPC5_EMIOS1_GFR_F14F15_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 14 and 15 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F14F15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD4.emiosp->GFR.R; + + if (gfr && (1U << 14U)) { + pwm_lld_serve_interrupt2(&PWMD4, 14U); + } + if (gfr && (1U << 15U)) { + pwm_lld_serve_interrupt2(&PWMD4, 15U); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP2 +#if !defined(SPC5_EMIOS1_GFR_F16F17_HANDLER) +#error "SPC5_EMIOS1_GFR_F16F17_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 16 and 17 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F16F17_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD5.emiosp->GFR.R; + + if (gfr && (1U << 16U)) { + pwm_lld_serve_interrupt1(&PWMD5, 16U); + } + if (gfr && (1U << 17U)) { + pwm_lld_serve_interrupt2(&PWMD5, 17U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F18F19_HANDLER) +#error "SPC5_EMIOS1_GFR_F18F19_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 18 and 19 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F18F19_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD5.emiosp->GFR.R; + + if (gfr && (1U << 18U)) { + pwm_lld_serve_interrupt2(&PWMD5, 18U); + } + if (gfr && (1U << 19U)) { + pwm_lld_serve_interrupt2(&PWMD5, 19U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F20F21_HANDLER) +#error "SPC5_EMIOS1_GFR_F20F21_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 20 and 21 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F20F21_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD5.emiosp->GFR.R; + + if (gfr && (1U << 20U)) { + pwm_lld_serve_interrupt2(&PWMD5, 20U); + } + if (gfr && (1U << 21U)) { + pwm_lld_serve_interrupt2(&PWMD5, 21U); + } + + CH_IRQ_EPILOGUE(); +} + +#if !defined(SPC5_EMIOS1_GFR_F22F23_HANDLER) +#error "SPC5_EMIOS1_GFR_F22F23_HANDLER not defined" +#endif +/** + * @brief eMIOS1 Channels 22 and 23 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) { + + CH_IRQ_PROLOGUE(); + + uint32_t gfr = PWMD5.emiosp->GFR.R; + + if (gfr && (1U << 22U)) { + pwm_lld_serve_interrupt2(&PWMD5, 22U); + } + if (gfr && (1U << 23U)) { + pwm_lld_serve_interrupt2(&PWMD5, 23U); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + /* eMIOSx channels initially all not in use.*/ + reset_emios0_active_channels(); + reset_emios1_active_channels(); + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.emiosp = &EMIOS_0; +#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.emiosp = &EMIOS_0; +#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.emiosp = &EMIOS_1; +#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.emiosp = &EMIOS_1; +#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.emiosp = &EMIOS_1; +#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */ + +#if SPC5_PWM_USE_EMIOS0 + + INTC.PSR[SPC5_EMIOS0_GFR_F8F9_NUMBER].R = SPC5_EMIOS0_GFR_F8F9_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F10F11_NUMBER].R = SPC5_EMIOS0_GFR_F10F11_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F12F13_NUMBER].R = SPC5_EMIOS0_GFR_F12F13_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F14F15_NUMBER].R = SPC5_EMIOS0_GFR_F14F15_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F16F17_NUMBER].R = SPC5_EMIOS0_GFR_F16F17_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F18F19_NUMBER].R = SPC5_EMIOS0_GFR_F18F19_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F20F21_NUMBER].R = SPC5_EMIOS0_GFR_F20F21_PRIORITY; + INTC.PSR[SPC5_EMIOS0_GFR_F22F23_NUMBER].R = SPC5_EMIOS0_GFR_F22F23_PRIORITY; + +#endif + +#if SPC5_PWM_USE_EMIOS1 + + INTC.PSR[SPC5_EMIOS1_GFR_F0F1_NUMBER].R = SPC5_EMIOS1_GFR_F0F1_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F2F3_NUMBER].R = SPC5_EMIOS1_GFR_F2F3_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F4F5_NUMBER].R = SPC5_EMIOS1_GFR_F4F5_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F6F7_NUMBER].R = SPC5_EMIOS1_GFR_F6F7_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F8F9_NUMBER].R = SPC5_EMIOS1_GFR_F8F9_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F10F11_NUMBER].R = SPC5_EMIOS1_GFR_F10F11_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F12F13_NUMBER].R = SPC5_EMIOS1_GFR_F12F13_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F14F15_NUMBER].R = SPC5_EMIOS1_GFR_F14F15_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F16F17_NUMBER].R = SPC5_EMIOS1_GFR_F16F17_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F18F19_NUMBER].R = SPC5_EMIOS1_GFR_F18F19_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F20F21_NUMBER].R = SPC5_EMIOS1_GFR_F20F21_PRIORITY; + INTC.PSR[SPC5_EMIOS1_GFR_F22F23_NUMBER].R = SPC5_EMIOS1_GFR_F22F23_PRIORITY; + +#endif + +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + uint32_t psc = 0, i = 0; + + chDbgAssert(get_emios0_active_channels() < 28, + "pwm_lld_start(), #1", "too many channels"); + chDbgAssert(get_emios1_active_channels() < 28, + "pwm_lld_start(), #2", "too many channels"); + + if (pwmp->state == PWM_STOP) { +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + increase_emios0_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + increase_emios0_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + increase_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + increase_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + increase_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */ + + /* Set eMIOS0 Clock.*/ +#if SPC5_PWM_USE_EMIOS0 + active_emios0_clock(NULL, pwmp); +#endif + + /* Set eMIOS1 Clock.*/ +#if SPC5_PWM_USE_EMIOS1 + active_emios1_clock(NULL, pwmp); +#endif + + } + /* Configures the peripheral.*/ + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 8U); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + } +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 16U); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~1U; + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[0].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 8U); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 16U); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + } +#endif + + /* Set clock prescaler and control register.*/ + if (pwmp->emiosp == &EMIOS_0) { + psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency); + chDbgAssert((psc <= 0xFFFF) && + (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "pwm_lld_start(), #1", "invalid frequency"); + } else if (pwmp->emiosp == &EMIOS_1) { + psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency); + chDbgAssert((psc <= 0xFFFF) && + (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) && + ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), + "pwm_lld_start(), #2", "invalid frequency"); + } + + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + + pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[8U].CCNTR.R = 1U; + pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period; + pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER); + pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP; + pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN; + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode) { + case PWM_OUTPUT_DISABLED: + break; + case PWM_OUTPUT_ACTIVE_HIGH: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 9U].CADR.R = 0; + pwmp->emiosp->CH[i + 9U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 9U)); + + break; + case PWM_OUTPUT_ACTIVE_LOW: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 9U].CADR.R = 1U; + pwmp->emiosp->CH[i + 9U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 9U)); + + break; + } + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << 8U); + + } + } +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + + pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[16U].CCNTR.R = 1U; + pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period; + pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER); + pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP; + pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN; + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode) { + case PWM_OUTPUT_DISABLED: + break; + case PWM_OUTPUT_ACTIVE_HIGH: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 17U].CADR.R = 0; + pwmp->emiosp->CH[i + 17U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 17U)); + + break; + case PWM_OUTPUT_ACTIVE_LOW: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 17U].CADR.R = 1U; + pwmp->emiosp->CH[i + 17U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 17U)); + + break; + } + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << 16U); + + } + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + + pwmp->emiosp->CH[0].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[0].CCNTR.R = 1U; + pwmp->emiosp->CH[0].CADR.R = pwmp->config->period; + pwmp->emiosp->CH[0].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER); + pwmp->emiosp->CH[0].CCR.R |= EMIOS_CCR_MODE_MCB_UP; + pwmp->emiosp->CH[0].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[0].CCR.R |= EMIOSC_UCPREN; + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode) { + case PWM_OUTPUT_DISABLED: + break; + case PWM_OUTPUT_ACTIVE_HIGH: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 1U].CADR.R = 0; + pwmp->emiosp->CH[i + 1U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 1U)); + + break; + case PWM_OUTPUT_ACTIVE_LOW: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 1U].CADR.R = 1U; + pwmp->emiosp->CH[i + 1U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 1U].CCR.R &= ~EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 1U)); + + break; + } + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= 1U; + + } + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + + pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[8U].CCNTR.R = 1U; + pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period; + pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER); + pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP; + pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN; + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode) { + case PWM_OUTPUT_DISABLED: + break; + case PWM_OUTPUT_ACTIVE_HIGH: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 9U].CADR.R = 0; + pwmp->emiosp->CH[i + 9U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 9U)); + + break; + case PWM_OUTPUT_ACTIVE_LOW: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 9U].CADR.R = 1U; + pwmp->emiosp->CH[i + 9U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 9U)); + + break; + } + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << 8U); + + } + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + + pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[16U].CCNTR.R = 1U; + pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period; + pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER); + pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP; + pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN; + + if (pwmp->config->mode == PWM_ALIGN_EDGE) { + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode) { + case PWM_OUTPUT_DISABLED: + break; + case PWM_OUTPUT_ACTIVE_HIGH: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 17U].CADR.R = 0; + pwmp->emiosp->CH[i + 17U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 17U)); + + break; + case PWM_OUTPUT_ACTIVE_LOW: + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0; + pwmp->emiosp->CH[i + 17U].CADR.R = 1U; + pwmp->emiosp->CH[i + 17U].CBDR.R = 0; + + /* Set output polarity.*/ + pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL; + + /* Set unified channel mode.*/ + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2); + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB; + + pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U; + pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN; + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << (i + 17U)); + + break; + } + } + + /* Channel disables.*/ + pwmp->emiosp->UCDIS.R |= (1U << 16U); + + } + } +#endif + +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + uint32_t i = 0; + + chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1", + "too many channels"); + chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2", + "too many channels"); + + if (pwmp->state == PWM_READY) { + + /* Disables the peripheral.*/ +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + /* Reset UC Control Register of group channels.*/ + for (i = 0; i < 8; i++) { + pwmp->emiosp->CH[i + 8U].CCR.R = 0; + } + decrease_emios0_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + /* Reset UC Control Register of group channels.*/ + for (i = 0; i < 8; i++) { + pwmp->emiosp->CH[i + 16U].CCR.R = 0; + } + decrease_emios0_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + /* Reset UC Control Register of group channels.*/ + for (i = 0; i < 8; i++) { + pwmp->emiosp->CH[i].CCR.R = 0; + } + decrease_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + /* Reset UC Control Register of group channels.*/ + for (i = 0; i < 8; i++) { + pwmp->emiosp->CH[i + 8U].CCR.R = 0; + } + decrease_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */ + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + /* Reset UC Control Register of group channels.*/ + for (i = 0; i < 8; i++) { + pwmp->emiosp->CH[i + 16U].CCR.R = 0; + } + decrease_emios1_active_channels(); + } +#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */ + + /* eMIOS0 clock deactivation.*/ +#if SPC5_PWM_USE_EMIOS0 + deactive_emios0_clock(NULL, pwmp); +#endif + + /* eMIOS1 clock deactivation.*/ +#if SPC5_PWM_USE_EMIOS1 + deactive_emios1_clock(NULL, pwmp); +#endif + } +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + pwmp->period = period; + pwmp->emiosp->CH[8U].CADR.R = period; + } +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + pwmp->period = period; + pwmp->emiosp->CH[16U].CADR.R = period; + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + pwmp->period = period; + pwmp->emiosp->CH[0].CADR.R = period; + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + pwmp->period = period; + pwmp->emiosp->CH[8U].CADR.R = period; + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + pwmp->period = period; + pwmp->emiosp->CH[16U].CADR.R = period; + } +#endif + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + /* Set PWM width.*/ + pwmp->emiosp->CH[channel + 9U].CBDR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U; + } + + /* Enables timer base channel if disable.*/ + if (pwmp->emiosp->UCDIS.R & (1U << 8U)) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 8U); + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL ) { + pwmp->emiosp->CH[8U].CCR.B.FEN = 1U; + } + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + /* Set PWM width.*/ + pwmp->emiosp->CH[channel + 17U].CBDR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U; + } + + /* Enables timer base channel if disable.*/ + if (pwmp->emiosp->UCDIS.R & (1U << 16U)) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 16U); + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL ) { + pwmp->emiosp->CH[16U].CCR.B.FEN = 1U; + } + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (1U + channel)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + /* Set PWM width.*/ + pwmp->emiosp->CH[channel + 1U].CBDR.R = width; + + + /* Active interrupts.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 1U; + } + + /* Enables timer base channel if disable.*/ + if (pwmp->emiosp->UCDIS.R & 1U) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~1U; + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL ) { + pwmp->emiosp->CH[0].CCR.B.FEN = 1U; + } + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + /* Set PWM width.*/ + pwmp->emiosp->CH[channel + 9U].CBDR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U; + } + + /* Enables timer base channel if disable.*/ + if (pwmp->emiosp->UCDIS.R & (1U << 8U)) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 8U); + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL ) { + pwmp->emiosp->CH[8U].CCR.B.FEN = 1U; + } + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel)); + + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC | + EMIOSS_FLAGC; + + /* Set PWM width.*/ + pwmp->emiosp->CH[channel + 17U].CBDR.R = width; + + /* Active interrupts.*/ + if (pwmp->config->channels[channel].callback != NULL) { + pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U; + } + + /* Enables timer base channel if disable.*/ + if (pwmp->emiosp->UCDIS.R & (1U << 16U)) { + /* Channel enables.*/ + pwmp->emiosp->UCDIS.R &= ~(1U << 16U); + + /* Active interrupts.*/ + if (pwmp->config->callback != NULL ) { + pwmp->emiosp->CH[16U].CCR.B.FEN = 1U; + } + } + + } +#endif + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + +#if SPC5_PWM_USE_EMIOS0_GROUP0 + if (&PWMD1 == pwmp) { + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U)); + + /* Disable timer base channel if all PWM channels are disabled.*/ + if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) { + /* Deactive interrupts.*/ + pwmp->emiosp->CH[8U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << 8U); + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 + if (&PWMD2 == pwmp) { + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << (channel + 17)); + + /* Disable timer base channel if all PWM channels are disabled.*/ + if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) { + /* Deactive interrupts.*/ + pwmp->emiosp->CH[16U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << 16U); + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 + if (&PWMD3 == pwmp) { + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << (channel + 1U)); + + /* Disable timer base channel if all PWM channels are disabled.*/ + if ((pwmp->emiosp->UCDIS.R & 0xFE) == 0xFE) { + /* Deactive interrupts.*/ + pwmp->emiosp->CH[0].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= 1U; + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 + if (&PWMD4 == pwmp) { + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U)); + + /* Disable timer base channel if all PWM channels are disabled.*/ + if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) { + /* Deactive interrupts.*/ + pwmp->emiosp->CH[8U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << 8U); + } + + } +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 + if (&PWMD5 == pwmp) { + /* Clear pending IRQs (if any).*/ + pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | + EMIOSS_OVFLC | EMIOSS_FLAGC; + + /* Disable interrupts.*/ + pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << (channel + 17U)); + + /* Disable timer base channel if all PWM channels are disabled.*/ + if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) { + /* Deactive interrupts.*/ + pwmp->emiosp->CH[16U].CCR.B.FEN = 0; + + /* Disable channel.*/ + pwmp->emiosp->UCDIS.R |= (1U << 16U); + } + + } +#endif + +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h new file mode 100644 index 000000000..e2dc403a8 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h @@ -0,0 +1,420 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/pwm_lld.h + * @brief SPC5xx low level PWM driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 7 + +/** + * @brief Edge-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_EDGE 0x00 + +/** + * @brief Center-Aligned PWM functional mode. + * @note This is an SPC5-specific setting. + */ +#define PWM_ALIGN_CENTER 0x01 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__) +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS0__GROUP0 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7 +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7 +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7 +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7 +#endif +#endif + +#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__) +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__) +#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7 +#endif +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SPC5_HAS_EMIOS0 +#error "EMIOS0 not present in the selected device" +#endif + +#if !SPC5_HAS_EMIOS1 +#error "EMIOS1 not present in the selected device" +#endif + +#define SPC5_PWM_USE_EMIOS0 (SPC5_PWM_USE_EMIOS0_GROUP0 || \ + SPC5_PWM_USE_EMIOS0_GROUP1) + +#define SPC5_PWM_USE_EMIOS1 (SPC5_PWM_USE_EMIOS1_GROUP0 || \ + SPC5_PWM_USE_EMIOS1_GROUP1 || \ + SPC5_PWM_USE_EMIOS1_GROUP2) + +#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1 +#error "PWM driver activated but no Channels assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief PWM functional mode. + */ + pwmmode_t mode; +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the eMIOSx registers block. + */ + volatile struct EMIOS_tag *emiosp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c new file mode 100644 index 000000000..20ce38773 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c @@ -0,0 +1,195 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/spc5_emios.c + * @brief SPC5xx low level ICU and PWM drivers common code. + * + * @addtogroup ICU - PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) + +#include "spc5_emios.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Number of active eMIOSx Channels. + */ +static uint32_t emios0_active_channels; +static uint32_t emios1_active_channels; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +void reset_emios0_active_channels() { + emios0_active_channels = 0; +} + +void reset_emios1_active_channels() { + emios1_active_channels = 0; +} + +uint32_t get_emios0_active_channels() { + return emios0_active_channels; +} + +uint32_t get_emios1_active_channels() { + return emios1_active_channels; +} + +void increase_emios0_active_channels() { + emios0_active_channels++; +} + +void decrease_emios0_active_channels() { + emios0_active_channels--; +} + +void increase_emios1_active_channels() { + emios1_active_channels++; +} + +void decrease_emios1_active_channels() { + emios1_active_channels--; +} + +void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If this is the first Channel activated then the eMIOS0 is enabled.*/ + if (emios0_active_channels == 1) { + halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL, + SPC5_EMIOS0_START_PCTL); + + /* Disable all unified channels.*/ + if (icup != NULL) { + icup->emiosp->MCR.B.GPREN = 0; + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER); + icup->emiosp->MCR.R |= EMIOSMCR_GPREN; + + icup->emiosp->MCR.B.GTBE = 1U; + + icup->emiosp->UCDIS.R = 0xFFFFFFFF; + + } else if (pwmp != NULL) { + pwmp->emiosp->MCR.B.GPREN = 0; + pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER); + pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN; + + pwmp->emiosp->MCR.B.GTBE = 1U; + + pwmp->emiosp->UCDIS.R = 0xFFFFFFFF; + + } + + } +} + +void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If this is the first Channel activated then the eMIOS1 is enabled.*/ + if (emios1_active_channels == 1) { + halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL, + SPC5_EMIOS1_START_PCTL); + + /* Disable all unified channels.*/ + if (icup != NULL) { + icup->emiosp->MCR.B.GPREN = 0; + icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER); + icup->emiosp->MCR.R |= EMIOSMCR_GPREN; + + icup->emiosp->MCR.B.GTBE = 1U; + + icup->emiosp->UCDIS.R = 0xFFFFFFFF; + + } else if (pwmp != NULL) { + pwmp->emiosp->MCR.B.GPREN = 0; + pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER); + pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN; + + pwmp->emiosp->MCR.B.GTBE = 1U; + + pwmp->emiosp->UCDIS.R = 0xFFFFFFFF; + + } + + } +} + +void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If it is the last active channels then the eMIOS0 is disabled.*/ + if (emios0_active_channels == 0) { + if (icup != NULL) { + if (icup->emiosp->UCDIS.R == 0) { + //icup->emiosp->MCR.B.MDIS = 0; + halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL, + SPC5_EMIOS0_STOP_PCTL); + } + } else if (pwmp != NULL) { + if (pwmp->emiosp->UCDIS.R == 0) { + //pwmp->emiosp->MCR.B.MDIS = 0; + halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL, + SPC5_EMIOS0_STOP_PCTL); + } + } + } +} + +void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) { + /* If it is the last active channels then the eMIOS1 is disabled.*/ + if (emios1_active_channels == 0) { + if (icup != NULL) { + if (icup->emiosp->UCDIS.R == 0) { + //icup->emiosp->MCR.B.MDIS = 0; + halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL, + SPC5_EMIOS1_STOP_PCTL); + } + } else if (pwmp != NULL) { + if (pwmp->emiosp->UCDIS.R == 0) { + //pwmp->emiosp->MCR.B.MDIS = 0; + halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL, + SPC5_EMIOS1_STOP_PCTL); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +#endif /* HAL_USE_ICU || HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h new file mode 100644 index 000000000..946db2400 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h @@ -0,0 +1,169 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eMIOS_v1/spc5_emios.h + * @brief SPC5xx low level ICU - PWM driver common header. + * + * @addtogroup ICU - PWM + * @{ + */ + +#ifndef _SPC5_EMIOS_H_ +#define _SPC5_EMIOS_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EMIOSMCR_MDIS (1U << 30U) +#define EMIOSMCR_FRZ (1U << 29U) +#define EMIOSMCR_GTBE (1U << 28U) +#define EMIOSMCR_GPREN (1U << 26U) +#define EMIOSMCR_GPRE(n) ((n) << 8U) + +#define EMIOSC_FREN (1U << 31U) +#define EMIOSC_UCPRE(n) ((n) << 26U) +#define EMIOSC_UCPREN (1U << 25U) +#define EMIOSC_DMA (1U << 24U) +#define EMIOSC_IF(n) ((n) << 19U) +#define EMIOSC_FCK (1U << 18U) +#define EMIOSC_FEN (1U << 17U) +#define EMIOSC_FORCMA (1U << 13U) +#define EMIOSC_FORCMB (1U << 12U) +#define EMIOSC_BSL(n) ((n) << 9U) +#define EMIOSC_EDSEL (1U << 8U) +#define EMIOSC_EDPOL (1U << 7U) +#define EMIOSC_MODE(n) ((n) << 0) + +#define EMIOS_BSL_COUNTER_BUS_A 0 +#define EMIOS_BSL_COUNTER_BUS_2 1U +#define EMIOS_BSL_INTERNAL_COUNTER 3U + +#define EMIOS_CCR_MODE_GPIO_IN 0 +#define EMIOS_CCR_MODE_GPIO_OUT 1U +#define EMIOS_CCR_MODE_SAIC 2U +#define EMIOS_CCR_MODE_SAOC 3U +#define EMIOS_CCR_MODE_IPWM 4U +#define EMIOS_CCR_MODE_IPM 5U +#define EMIOS_CCR_MODE_DAOC_B_MATCH 6U +#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7U +#define EMIOS_CCR_MODE_MC_CMS 16U +#define EMIOS_CCR_MODE_MC_CME 17U +#define EMIOS_CCR_MODE_MC_UP_DOWN 18U +#define EMIOS_CCR_MODE_OPWMT 38U +#define EMIOS_CCR_MODE_MCB_UP 80U +#define EMIOS_CCR_MODE_MCB_UP_DOWN 84U +#define EMIOS_CCR_MODE_OPWFMB 88U +#define EMIOS_CCR_MODE_OPWMCB_TE 92U +#define EMIOS_CCR_MODE_OPWMCB_LE 93U +#define EMIOS_CCR_MODE_OPWMB 96U + +#define EMIOSS_OVR (1U << 31U) +#define EMIOSS_OVRC (1U << 31U) +#define EMIOSS_OVFL (1U << 15U) +#define EMIOSS_OVFLC (1U << 15U) +#define EMIOSS_FLAG (1U << 0) +#define EMIOSS_FLAGC (1U << 0) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if SPC5_HAS_EMIOS0 +/** + * @brief eMIOS0 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EMIOS0_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief eMIOS0 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EMIOS0_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif +#endif + +#if SPC5_HAS_EMIOS1 +/** + * @brief eMIOS1 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EMIOS1_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief eMIOS1 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EMIOS1_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +void reset_emios0_active_channels(void); +void reset_emios1_active_channels(void); +uint32_t get_emios0_active_channels(void); +uint32_t get_emios1_active_channels(void); +void increase_emios0_active_channels(void); +void decrease_emios0_active_channels(void); +void increase_emios1_active_channels(void); +void decrease_emios1_active_channels(void); +void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp); +void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp); +void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp); +void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp); + +#endif /* HAL_USE_ICU */ + +#endif /* _SPC5_EMIOS_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c new file mode 100644 index 000000000..4cdfab8f7 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c @@ -0,0 +1,1389 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eTimer_v1/icu_lld.c + * @brief SPC5xx low level ICU driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the complex timer SMOD0 when enabled. + */ +#if SPC5_ICU_USE_SMOD0 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD2 allocates the complex timer SMOD1 when enabled. + */ +#if SPC5_ICU_USE_SMOD1 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD3 allocates the complex timer SMOD2 when enabled. + */ +#if SPC5_ICU_USE_SMOD2 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the complex timer SMOD3 when enabled. + */ +#if SPC5_ICU_USE_SMOD3 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the complex timer SMOD4 when enabled. + */ +#if SPC5_ICU_USE_SMOD4 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD6 driver identifier. + * @note The driver ICUD6 allocates the complex timer SMOD5 when enabled. + */ +#if SPC5_ICU_USE_SMOD5 || defined(__DOXYGEN__) +ICUDriver ICUD6; +#endif + +/** + * @brief ICUD7 driver identifier. + * @note The driver ICUD7 allocates the complex timer SMOD6 when enabled. + */ +#if SPC5_ICU_USE_SMOD6 || defined(__DOXYGEN__) +ICUDriver ICUD7; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the complex timer SMOD7 when enabled. + */ +#if SPC5_ICU_USE_SMOD7 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the complex timer SMOD8 when enabled. + */ +#if SPC5_ICU_USE_SMOD8 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/** + * @brief ICUD10 driver identifier. + * @note The driver ICUD10 allocates the complex timer SMOD9 when enabled. + */ +#if SPC5_ICU_USE_SMOD9 || defined(__DOXYGEN__) +ICUDriver ICUD10; +#endif + +/** + * @brief ICUD11 driver identifier. + * @note The driver ICUD11 allocates the complex timer SMOD10 when enabled. + */ +#if SPC5_ICU_USE_SMOD10 || defined(__DOXYGEN__) +ICUDriver ICUD11; +#endif + +/** + * @brief ICUD12 driver identifier. + * @note The driver ICUD12 allocates the complex timer SMOD11 when enabled. + */ +#if SPC5_ICU_USE_SMOD11 || defined(__DOXYGEN__) +ICUDriver ICUD12; +#endif + +/** + * @brief ICUD13 driver identifier. + * @note The driver ICUD13 allocates the complex timer SMOD12 when enabled. + */ +#if SPC5_ICU_USE_SMOD12 || defined(__DOXYGEN__) +ICUDriver ICUD13; +#endif + +/** + * @brief ICUD14 driver identifier. + * @note The driver ICUD14 allocates the complex timer SMOD13 when enabled. + */ +#if SPC5_ICU_USE_SMOD13 || defined(__DOXYGEN__) +ICUDriver ICUD14; +#endif + +/** + * @brief ICUD15 driver identifier. + * @note The driver ICUD15 allocates the complex timer SMOD14 when enabled. + */ +#if SPC5_ICU_USE_SMOD14 || defined(__DOXYGEN__) +ICUDriver ICUD15; +#endif + +/** + * @brief ICUD16 driver identifier. + * @note The driver ICUD16 allocates the complex timer SMOD15 when enabled. + */ +#if SPC5_ICU_USE_SMOD15 || defined(__DOXYGEN__) +ICUDriver ICUD16; +#endif + +/** + * @brief ICUD17 driver identifier. + * @note The driver ICUD17 allocates the complex timer SMOD16 when enabled. + */ +#if SPC5_ICU_USE_SMOD16 || defined(__DOXYGEN__) +ICUDriver ICUD17; +#endif + +/** + * @brief ICUD18 driver identifier. + * @note The driver ICUD18 allocates the complex timer SMOD17 when enabled. + */ +#if SPC5_ICU_USE_SMOD17 || defined(__DOXYGEN__) +ICUDriver ICUD18; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Number of active eTimer Submodules. + */ +static uint32_t icu_active_submodules0; +static uint32_t icu_active_submodules1; +static uint32_t icu_active_submodules2; + +/** + * @brief Width and Period registers. + */ +uint16_t width; +uint16_t period; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + uint16_t sr = icup->etimerp->CHANNEL[icup->smod_number].STS.R & + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R; + + if (ICU_SKIP_FIRST_CAPTURE) { + if ((sr & 0x0008) != 0) { /* TOF */ + icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U; + _icu_isr_invoke_overflow_cb(icup); + } + if ((sr & 0x0040) != 0) { /* ICF1 */ + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE == + SPC5_ETIMER_CNTMODE_RFE_SIHA) { + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U; + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = + SPC5_ETIMER_CNTMODE_RE; + } + else { + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U; + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) { + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + } else { + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + } + _icu_isr_invoke_period_cb(icup); + } + } + else if ((sr & 0x0080) != 0) { /* ICF2 */ + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE == + SPC5_ETIMER_CNTMODE_RFE_SIHA) { + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U; + icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0; + } + else { + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U; + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) { + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + } else { + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + } + _icu_isr_invoke_width_cb(icup); + } + } + } else { /* ICU_SKIP_FIRST_CAPTURE = TRUE*/ + if ((sr & 0x0008) != 0) { /* TOF */ + icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U; + _icu_isr_invoke_overflow_cb(icup); + } + if ((sr & 0x0040) != 0) { /* ICF1 */ + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U; + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) { + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + } else { + period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; + } + _icu_isr_invoke_period_cb(icup); + } + else if ((sr & 0x0080) != 0) { /* ICF2 */ + icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U; + if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) { + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + } else { + width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; + } + _icu_isr_invoke_width_cb(icup); + } + } /* ICU_SKIP_FIRST_CAPTURE = FALSE */ +} + +/** + * @brief eTimer SubModules initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p ICUDriver object + * @param[in] config the architecture-dependent ICU driver configuration + */ +static void spc5_icu_smod_init(ICUDriver *icup) { + uint32_t psc = (icup->clock / icup->config->frequency); + + chDbgAssert((psc <= 0xFFFF) && + ((psc * icup->config->frequency) == icup->clock) && + ((psc == 1) || (psc == 2) || (psc == 4) || + (psc == 8) || (psc == 16) || (psc == 32) || + (psc == 64) || (psc == 128)), + "spc5_icu_smod_init(), #1", "invalid frequency"); + + /* Set primary source and clock prescaler.*/ + switch (psc) { + case 1: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1; + break; + case 2: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2; + break; + case 4: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4; + break; + case 8: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8; + break; + case 16: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16; + break; + case 32: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32; + break; + case 64: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64; + break; + case 128: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC = + SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128; + break; + } + + /* Set control registers.*/ + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.ONCE = 0U; + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.LENGTH = 0U; + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.DIR = 0U; + icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U; + + /* Set secondary source.*/ + switch (icup->smod_number) { + case 0: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_0_INPUT_PIN; + break; + case 1: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_1_INPUT_PIN; + break; + case 2: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_2_INPUT_PIN; + break; + case 3: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_3_INPUT_PIN; + break; + case 4: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_4_INPUT_PIN; + break; + case 5: + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = + SPC5_ETIMER_COUNTER_5_INPUT_PIN; + break; + } + + /* Set secondary source polarity.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) { + icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 0U; + } + else { + icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 1U; + } + + /* Direct pointers to the capture registers in order to make reading + data faster from within callbacks.*/ + icup->pccrp = . + icup->wccrp = &width; + + /* Enable channel.*/ + icup->etimerp->ENBL.B.ENBL |= 1U << (icup->smod_number); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_SMOD0 +#if !defined(SPC5_ETIMER0_TC0IR_HANDLER) +#error "SPC5_ETIMER0_TC0IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 0 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC0IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD0 */ + +#if SPC5_ICU_USE_SMOD1 +#if !defined(SPC5_ETIMER0_TC1IR_HANDLER) +#error "SPC5_ETIMER0_TC1IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC1IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD1 */ + +#if SPC5_ICU_USE_SMOD2 +#if !defined(SPC5_ETIMER0_TC2IR_HANDLER) +#error "SPC5_ETIMER0_TC2IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC2IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD2 */ + +#if SPC5_ICU_USE_SMOD3 +#if !defined(SPC5_ETIMER0_TC3IR_HANDLER) +#error "SPC5_ETIMER0_TC3IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC3IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD3 */ + +#if SPC5_ICU_USE_SMOD4 +#if !defined(SPC5_ETIMER0_TC4IR_HANDLER) +#error "SPC5_ETIMER0_TC4IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC4IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD4 */ + +#if SPC5_ICU_USE_SMOD5 +#if !defined(SPC5_ETIMER0_TC5IR_HANDLER) +#error "SPC5_ETIMER0_TC5IR_HANDLER not defined" +#endif +/** + * @brief eTimer0 Channel 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER0_TC5IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD5 */ + +#if SPC5_ICU_USE_SMOD6 +#if !defined(SPC5_ETIMER1_TC0IR_HANDLER) +#error "SPC5_ETIMER1_TC0IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 0 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC0IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD6 */ + +#if SPC5_ICU_USE_SMOD7 +#if !defined(SPC5_ETIMER1_TC1IR_HANDLER) +#error "SPC5_ETIMER1_TC1IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC1IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD7 */ + +#if SPC5_ICU_USE_SMOD8 +#if !defined(SPC5_ETIMER1_TC2IR_HANDLER) +#error "SPC5_ETIMER1_TC2IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC2IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD8 */ + +#if SPC5_ICU_USE_SMOD9 +#if !defined(SPC5_ETIMER1_TC3IR_HANDLER) +#error "SPC5_ETIMER1_TC3IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC3IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD10); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD9 */ + +#if SPC5_ICU_USE_SMOD10 +#if !defined(SPC5_ETIMER1_TC4IR_HANDLER) +#error "SPC5_ETIMER1_TC4IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC4IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD10 */ + +#if SPC5_ICU_USE_SMOD11 +#if !defined(SPC5_ETIMER1_TC5IR_HANDLER) +#error "SPC5_ETIMER1_TC5IR_HANDLER not defined" +#endif +/** + * @brief eTimer1 Channel 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER1_TC5IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD11 */ + +#if SPC5_ICU_USE_SMOD12 +#if !defined(SPC5_ETIMER2_TC0IR_HANDLER) +#error "SPC5_ETIMER2_TC0IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 0 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC0IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD13); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD12 */ + +#if SPC5_ICU_USE_SMOD13 +#if !defined(SPC5_ETIMER2_TC1IR_HANDLER) +#error "SPC5_ETIMER2_TC1IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC1IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD14); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD13 */ + +#if SPC5_ICU_USE_SMOD14 +#if !defined(SPC5_ETIMER2_TC2IR_HANDLER) +#error "SPC5_ETIMER2_TC2IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC2IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD15); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD14 */ + +#if SPC5_ICU_USE_SMOD15 +#if !defined(SPC5_ETIMER2_TC3IR_HANDLER) +#error "SPC5_ETIMER2_TC3IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC3IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD16); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD15 */ + +#if SPC5_ICU_USE_SMOD16 +#if !defined(SPC5_ETIMER2_TC4IR_HANDLER) +#error "SPC5_ETIMER2_TC4IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC4IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD17); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD16 */ + +#if SPC5_ICU_USE_SMOD17 +#if !defined(SPC5_ETIMER2_TC5IR_HANDLER) +#error "SPC5_ETIMER2_TC5IR_HANDLER not defined" +#endif +/** + * @brief eTimer2 Channel 5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_ETIMER2_TC5IR_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD18); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_ICU_USE_SMOD17 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + + /* Submodules initially all not in use.*/ + icu_active_submodules0 = 0; + icu_active_submodules1 = 0; + icu_active_submodules2 = 0; + + /* Reset width and period registers.*/ + width = 0; + period = 0; + +#if SPC5_ICU_USE_SMOD0 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.etimerp = &SPC5_ETIMER_0; + ICUD1.smod_number = 0U; + ICUD1.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD1 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.etimerp = &SPC5_ETIMER_0; + ICUD2.smod_number = 1U; + ICUD2.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD2 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.etimerp = &SPC5_ETIMER_0; + ICUD3.smod_number = 2U; + ICUD3.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD3 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.etimerp = &SPC5_ETIMER_0; + ICUD4.smod_number = 3U; + ICUD4.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD4 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.etimerp = &SPC5_ETIMER_0; + ICUD5.smod_number = 4U; + ICUD5.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD5 + /* Driver initialization.*/ + icuObjectInit(&ICUD6); + ICUD6.etimerp = &SPC5_ETIMER_0; + ICUD6.smod_number = 5U; + ICUD6.clock = SPC5_ETIMER0_CLK; +#endif + +#if SPC5_ICU_USE_SMOD6 + /* Driver initialization.*/ + icuObjectInit(&ICUD7); + ICUD7.etimerp = &SPC5_ETIMER_1; + ICUD7.smod_number = 0U; + ICUD7.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD7 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.etimerp = &SPC5_ETIMER_1; + ICUD8.smod_number = 1U; + ICUD8.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD8 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.etimerp = &SPC5_ETIMER_1; + ICUD9.smod_number = 2U; + ICUD9.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD9 + /* Driver initialization.*/ + icuObjectInit(&ICUD10); + ICUD10.etimerp = &SPC5_ETIMER_1; + ICUD10.smod_number = 3U; + ICUD10.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD10 + /* Driver initialization.*/ + icuObjectInit(&ICUD11); + ICUD11.etimerp = &SPC5_ETIMER_1; + ICUD11.smod_number = 4U; + ICUD11.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD11 + /* Driver initialization.*/ + icuObjectInit(&ICUD12); + ICUD12.etimerp = &SPC5_ETIMER_1; + ICUD12.smod_number = 5U; + ICUD12.clock = SPC5_ETIMER1_CLK; +#endif + +#if SPC5_ICU_USE_SMOD12 + /* Driver initialization.*/ + icuObjectInit(&ICUD13); + ICUD13.etimerp = &SPC5_ETIMER_2; + ICUD13.smod_number = 0U; + ICUD13.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_SMOD13 + /* Driver initialization.*/ + icuObjectInit(&ICUD14); + ICUD14.etimerp = &SPC5_ETIMER_2; + ICUD14.smod_number = 1U; + ICUD14.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_SMOD14 + /* Driver initialization.*/ + icuObjectInit(&ICUD15); + ICUD15.etimerp = &SPC5_ETIMER_2; + ICUD15.smod_number = 2U; + ICUD15.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_SMOD15 + /* Driver initialization.*/ + icuObjectInit(&ICUD16); + ICUD16.etimerp = &SPC5_ETIMER_2; + ICUD16.smod_number = 3U; + ICUD16.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_SMOD16 + /* Driver initialization.*/ + icuObjectInit(&ICUD17); + ICUD17.etimerp = &SPC5_ETIMER_2; + ICUD17.smod_number = 4U; + ICUD17.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_SMOD17 + /* Driver initialization.*/ + icuObjectInit(&ICUD18); + ICUD18.etimerp = &SPC5_ETIMER_2; + ICUD18.smod_number = 5U; + ICUD18.clock = SPC5_ETIMER2_CLK; +#endif + +#if SPC5_ICU_USE_ETIMER0 + + INTC.PSR[SPC5_ETIMER0_TC0IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_TC1IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_TC2IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_TC3IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_TC4IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_TC5IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_WTIF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + INTC.PSR[SPC5_ETIMER0_RCF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY; + +#endif + +#if SPC5_ICU_USE_ETIMER1 + + INTC.PSR[SPC5_ETIMER1_TC0IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_TC1IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_TC2IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_TC3IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_TC4IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_TC5IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + INTC.PSR[SPC5_ETIMER1_RCF_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY; + +#endif + +#if SPC5_ICU_USE_ETIMER2 + + INTC.PSR[SPC5_ETIMER2_TC0IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_TC1IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_TC2IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_TC3IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_TC4IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_TC5IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + INTC.PSR[SPC5_ETIMER2_RCF_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY; + +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + chDbgAssert(icu_active_submodules0 < 6, "icu_lld_start(), #1", + "too many submodules"); + chDbgAssert(icu_active_submodules1 < 6, "icu_lld_start(), #2", + "too many submodules"); + chDbgAssert(icu_active_submodules2 < 6, "icu_lld_start(), #3", + "too many submodules"); + + if (icup->state == ICU_STOP) { +#if SPC5_ICU_USE_SMOD0 + if (&ICUD1 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD1 + if (&ICUD2 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD2 + if (&ICUD3 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD3 + if (&ICUD4 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD4 + if (&ICUD5 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD5 + if (&ICUD6 == icup) + icu_active_submodules0++; +#endif +#if SPC5_ICU_USE_SMOD6 + if (&ICUD7 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD7 + if (&ICUD8 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD8 + if (&ICUD9 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD9 + if (&ICUD10 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD10 + if (&ICUD11 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD11 + if (&ICUD12 == icup) + icu_active_submodules1++; +#endif +#if SPC5_ICU_USE_SMOD12 + if (&ICUD13 == icup) + icu_active_submodules2++; +#endif +#if SPC5_ICU_USE_SMOD13 + if (&ICUD14 == icup) + icu_active_submodules2++; +#endif +#if SPC5_ICU_USE_SMOD14 + if (&ICUD15 == icup) + icu_active_submodules2++; +#endif +#if SPC5_ICU_USE_SMOD15 + if (&ICUD16 == icup) + icu_active_submodules2++; +#endif +#if SPC5_ICU_USE_SMOD16 + if (&ICUD17 == icup) + icu_active_submodules2++; +#endif +#if SPC5_ICU_USE_SMOD17 + if (&ICUD18 == icup) + icu_active_submodules2++; +#endif + + /* Set eTimer0 Clock.*/ +#if SPC5_ICU_USE_ETIMER0 + + /* If this is the first Submodule activated then the eTimer0 is enabled.*/ + if (icu_active_submodules0 == 1) { + halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL, + SPC5_ICU_ETIMER0_START_PCTL); + } +#endif + + /* Set eTimer1 Clock.*/ +#if SPC5_ICU_USE_ETIMER1 + /* If this is the first Submodule activated then the eTimer1 is enabled.*/ + if (icu_active_submodules1 == 1) { + halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL, + SPC5_ICU_ETIMER1_START_PCTL); + } +#endif + + /* Set eTimer2 Clock.*/ +#if SPC5_ICU_USE_ETIMER2 + /* If this is the first Submodule activated then the eTimer2 is enabled.*/ + if (icu_active_submodules2 == 1) { + halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL, + SPC5_ICU_ETIMER2_START_PCTL); + } +#endif + + /* Timer disabled.*/ + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = + SPC5_ETIMER_CNTMODE_NO_OPERATION; + + /* Clear pending IRQs (if any).*/ + icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF; + + /* All IRQs and DMA requests disabled.*/ + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0U; + + /* Compare Load 1 and Compare Load 2 disabled.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0U; + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0U; + + /* Capture 1 and Capture 2 disabled.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = + SPC5_ETIMER_CPT1MODE_DISABLED; + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = + SPC5_ETIMER_CPT2MODE_DISABLED; + + /* Counter reset to zero.*/ + icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0U; + } + + /* Configuration.*/ + spc5_icu_smod_init(icup); +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + chDbgAssert(icu_active_submodules0 < 6, "icu_lld_stop(), #1", + "too many submodules"); + chDbgAssert(icu_active_submodules1 < 6, "icu_lld_stop(), #2", + "too many submodules"); + chDbgAssert(icu_active_submodules2 < 6, "icu_lld_stop(), #3", + "too many submodules"); + + if (icup->state == ICU_READY) { + +#if SPC5_ICU_USE_SMOD0 + if (&ICUD1 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFE; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD1 + if (&ICUD2 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFD; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD2 + if (&ICUD3 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFB; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD3 + if (&ICUD4 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xF7; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD4 + if (&ICUD5 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xEF; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD5 + if (&ICUD6 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xDF; + icu_active_submodules0--; + } +#endif +#if SPC5_ICU_USE_SMOD6 + if (&ICUD7 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFE; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD7 + if (&ICUD8 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFD; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD8 + if (&ICUD9 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFB; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD9 + if (&ICUD10 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xF7; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD10 + if (&ICUD11 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xEF; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD11 + if (&ICUD12 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xDF; + icu_active_submodules1--; + } +#endif +#if SPC5_ICU_USE_SMOD12 + if (&ICUD13 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFE; + icu_active_submodules2--; + } +#endif +#if SPC5_ICU_USE_SMOD13 + if (&ICUD14 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFD; + icu_active_submodules2--; + } +#endif +#if SPC5_ICU_USE_SMOD14 + if (&ICUD15 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xFB; + icu_active_submodules2--; + } +#endif +#if SPC5_ICU_USE_SMOD15 + if (&ICUD16 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xF7; + icu_active_submodules2--; + } +#endif +#if SPC5_ICU_USE_SMOD16 + if (&ICUD17 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xEF; + icu_active_submodules2--; + } +#endif +#if SPC5_ICU_USE_SMOD17 + if (&ICUD18 == icup) { + /* Disable channel.*/ + icup->etimerp->ENBL.B.ENBL &= 0xDF; + icu_active_submodules2--; + } +#endif + /* eTimer0 clock deactivation.*/ +#if SPC5_ICU_USE_ETIMER0 + /* If it is the last active submodules then the eTimer0 is disabled.*/ + if (icu_active_submodules0 == 0) { + if (icup->etimerp->ENBL.B.ENBL == 0) { + halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL, + SPC5_ICU_ETIMER0_STOP_PCTL); + } + } +#endif + + /* eTimer1 clock deactivation.*/ +#if SPC5_ICU_USE_ETIMER1 + /* If it is the last active submodules then the eTimer1 is disabled.*/ + if (icu_active_submodules1 == 0) { + if (icup->etimerp->ENBL.B.ENBL == 0) { + halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL, + SPC5_ICU_ETIMER1_STOP_PCTL); + } + } +#endif + + /* eTimer2 clock deactivation.*/ +#if SPC5_ICU_USE_ETIMER2 + /* If it is the last active submodules then the eTimer2 is disabled.*/ + if (icu_active_submodules2 == 0) { + if (icup->etimerp->ENBL.B.ENBL == 0) { + halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL, + SPC5_ICU_ETIMER2_STOP_PCTL); + } + } +#endif + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + /* Clear pending IRQs (if any).*/ + icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF; + + /* Set Capture 1 and Capture 2 Mode.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = + SPC5_ETIMER_CPT1MODE_RISING_EDGE; + icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.ROC = + SPC5_ETIMER_ROC_REL_ON_CAP1; + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = + SPC5_ETIMER_CPT2MODE_FALLING_EDGE; + + /* Active interrupts.*/ + if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) { + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 1U; + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 1U; + } + if (icup->config->overflow_cb != NULL) { + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 1U; + } + + /* Set Capture FIFO Water Mark.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CFWM = 0U; + + /* Enable Counter.*/ + if (ICU_SKIP_FIRST_CAPTURE) { + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = + SPC5_ETIMER_CNTMODE_RFE_SIHA; + } + else { + icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = + SPC5_ETIMER_CNTMODE_RE; + } + + /* Enable Capture process.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 1U; +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + /* Disable Capture process.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 0U; + + /* Clear pending IRQs (if any).*/ + icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF; + + /* Set Capture 1 and Capture 2 Mode to Disabled.*/ + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = + SPC5_ETIMER_CPT1MODE_DISABLED; + icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = + SPC5_ETIMER_CPT2MODE_DISABLED; + + /* Disable interrupts.*/ + if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) { + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 0U; + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 0U; + } + if (icup->config->overflow_cb != NULL) + icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 0U; +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h new file mode 100644 index 000000000..f95f5356f --- /dev/null +++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h @@ -0,0 +1,612 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eTimer_v1/icu_lld.h + * @brief SPC5xx low level ICU driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +#include "spc5_etimer.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Mode options + * @{ + */ + +/** + * @brief Skip first capture cycle. + * @details If set to @p TRUE the first capture cycle is skipped. + * @note The default is @p FALSE. + */ +#if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__) +#define ICU_SKIP_FIRST_CAPTURE FALSE +#endif + +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1 0x18 +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2 0x19 +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4 0x1A +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8 0x1B +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16 0x1C +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32 0x1D +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64 0x1E +#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128 0x1F + +#define SPC5_ETIMER_COUNTER_0_INPUT_PIN 0U +#define SPC5_ETIMER_COUNTER_1_INPUT_PIN 1U +#define SPC5_ETIMER_COUNTER_2_INPUT_PIN 2U +#define SPC5_ETIMER_COUNTER_3_INPUT_PIN 3U +#define SPC5_ETIMER_COUNTER_4_INPUT_PIN 4U +#define SPC5_ETIMER_COUNTER_5_INPUT_PIN 5U + +#define SPC5_ETIMER_CNTMODE_NO_OPERATION 0U +#define SPC5_ETIMER_CNTMODE_RE 1U +#define SPC5_ETIMER_CNTMODE_RFE 2U +#define SPC5_ETIMER_CNTMODE_RFE_SIHA 3U +#define SPC5_ETIMER_CNTMODE_QUADRATURE 4U +#define SPC5_ETIMER_CNTMODE_RE_SSSD 5U +#define SPC5_ETIMER_CNTMODE_ESS_TRIGGER 6U +#define SPC5_ETIMER_CNTMODE_CASCADE 7U + +#define SPC5_ETIMER_CPT1MODE_DISABLED 0U +#define SPC5_ETIMER_CPT1MODE_FALLING_EDGE 1U +#define SPC5_ETIMER_CPT1MODE_RISING_EDGE 2U +#define SPC5_ETIMER_CPT1MODE_ANY_EDGE 3U + +#define SPC5_ETIMER_CPT2MODE_DISABLED 0U +#define SPC5_ETIMER_CPT2MODE_FALLING_EDGE 1U +#define SPC5_ETIMER_CPT2MODE_RISING_EDGE 2U +#define SPC5_ETIMER_CPT2MODE_ANY_EDGE 3U + +#define SPC5_ETIMER_ROC_DO_NOT_RELOAD 0U +#define SPC5_ETIMER_ROC_REL_ON_CAP1 1U +#define SPC5_ETIMER_ROC_REL_ON_CAP2 2U +#define SPC5_ETIMER_ROC_REL_ON_CAP1_CAP2 3U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD0) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD0 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD1) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD1 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD2) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD2 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD3) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD3 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD4) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD4 FALSE +#endif + +/** + * @brief ICUD6 driver enable switch. + * @details If set to @p TRUE the support for ICUD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD5) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD5 FALSE +#endif + +/** + * @brief eTimer0 interrupt priority level setting. + */ +#if !defined(SPC5_ICU_ETIMER0_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#endif + +/** + * @brief eTIMER0 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER0_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief eTIMER0 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER0_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief ICUD6 driver enable switch. + * @details If set to @p TRUE the support for ICUD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD6) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD6 FALSE +#endif + +/** + * @brief ICUD7 driver enable switch. + * @details If set to @p TRUE the support for ICUD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD7) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD7 FALSE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD8) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD8 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD9) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD9 FALSE +#endif + +/** + * @brief ICUD10 driver enable switch. + * @details If set to @p TRUE the support for ICUD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD10) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD10 FALSE +#endif + +/** + * @brief ICUD11 driver enable switch. + * @details If set to @p TRUE the support for ICUD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD11) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD11 FALSE +#endif + +/** + * @brief eTimer1 interrupt priority level setting. + */ +#if !defined(SPC5_ICU_ETIMER1_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#endif + +/** + * @brief eTIMER1 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER1_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief eTIMER1 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER1_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif + +/** + * @brief ICUD13 driver enable switch. + * @details If set to @p TRUE the support for ICUD13 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD12) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD12 FALSE +#endif + +/** + * @brief ICUD14 driver enable switch. + * @details If set to @p TRUE the support for ICUD14 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD13) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD13 FALSE +#endif + +/** + * @brief ICUD15 driver enable switch. + * @details If set to @p TRUE the support for ICUD15 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD14) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD14 FALSE +#endif + +/** + * @brief ICUD16 driver enable switch. + * @details If set to @p TRUE the support for ICUD16 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD15) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD15 FALSE +#endif + +/** + * @brief ICUD17 driver enable switch. + * @details If set to @p TRUE the support for ICUD17 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD16) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD16 FALSE +#endif + +/** + * @brief ICUD18 driver enable switch. + * @details If set to @p TRUE the support for ICUD18 is included. + * @note The default is @p FALSE. + */ +#if !defined(SPC5_ICU_USE_SMOD17) || defined(__DOXYGEN__) +#define SPC5_ICU_USE_SMOD17 FALSE +#endif + +/** + * @brief eTimer2 interrupt priority level setting. + */ +#if !defined(SPC5_ICU_ETIMER2_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#endif + +/** + * @brief eTIMER2 peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER2_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#endif + +/** + * @brief eTIMER2 peripheral configuration when stopped. + * @note The default configuration is 0 (never run) in run mode and + * 0 (never run) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_ICU_ETIMER2_STOP_PCTL) || defined(__DOXYGEN__) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#define SPC5_ICU_USE_ETIMER0 (SPC5_ICU_USE_SMOD0 || \ + SPC5_ICU_USE_SMOD1 || \ + SPC5_ICU_USE_SMOD2 || \ + SPC5_ICU_USE_SMOD3 || \ + SPC5_ICU_USE_SMOD4 || \ + SPC5_ICU_USE_SMOD5) + +#define SPC5_ICU_USE_ETIMER1 (SPC5_ICU_USE_SMOD6 || \ + SPC5_ICU_USE_SMOD7 || \ + SPC5_ICU_USE_SMOD8 || \ + SPC5_ICU_USE_SMOD9 || \ + SPC5_ICU_USE_SMOD10 || \ + SPC5_ICU_USE_SMOD11) + +#define SPC5_ICU_USE_ETIMER2 (SPC5_ICU_USE_SMOD12 || \ + SPC5_ICU_USE_SMOD13 || \ + SPC5_ICU_USE_SMOD14 || \ + SPC5_ICU_USE_SMOD15 || \ + SPC5_ICU_USE_SMOD16 || \ + SPC5_ICU_USE_SMOD17) + +#if !SPC5_HAS_ETIMER0 && SPC5_ICU_USE_ETIMER0 +#error "ETIMER0 not present in the selected device" +#endif + +#if !SPC5_HAS_ETIMER1 && SPC5_ICU_USE_ETIMER1 +#error "ETIMER1 not present in the selected device" +#endif + +#if !SPC5_HAS_ETIMER2 && SPC5_ICU_USE_ETIMER2 +#error "ETIMER2 not present in the selected device" +#endif + +#if !SPC5_ICU_USE_ETIMER0 && !SPC5_ICU_USE_ETIMER1 && !SPC5_ICU_USE_ETIMER2 +#error "ICU driver activated but no SMOD peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU channel. + */ +typedef enum { + ICU_CHANNEL_1 = 0, /**< Use SMODxCH1. */ + ICU_CHANNEL_2 = 1, /**< Use SMODxCH2. */ + ICU_CHANNEL_3 = 2, /**< Use SMODxCH3. */ + ICU_CHANNEL_4 = 3, /**< Use SMODxCH4. */ + ICU_CHANNEL_5 = 4, /**< Use SMODxCH5. */ + ICU_CHANNEL_6 = 5, /**< Use SMODxCH6. */ +} icuchannel_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Clock value for this unit. + */ + uint32_t clock; + /** + * @brief eTimer submodule number. + */ + uint32_t smod_number; + /** + * @brief Pointer to the eTimerx registers block. + */ + volatile struct spc5_etimer *etimerp; + /** + * @brief CCR register used for width capture. + */ + volatile vuint16_t *wccrp; + /** + * @brief CCR register used for period capture. + */ + volatile vuint16_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_ICU_USE_SMOD0 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if SPC5_ICU_USE_SMOD1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if SPC5_ICU_USE_SMOD2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if SPC5_ICU_USE_SMOD3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if SPC5_ICU_USE_SMOD4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if SPC5_ICU_USE_SMOD5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD6; +#endif + +#if SPC5_ICU_USE_SMOD6 && !defined(__DOXYGEN__) +extern ICUDriver ICUD7; +#endif + +#if SPC5_ICU_USE_SMOD7 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#if SPC5_ICU_USE_SMOD8 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#if SPC5_ICU_USE_SMOD9 && !defined(__DOXYGEN__) +extern ICUDriver ICUD10; +#endif + +#if SPC5_ICU_USE_SMOD10 && !defined(__DOXYGEN__) +extern ICUDriver ICUD11; +#endif + +#if SPC5_ICU_USE_SMOD11 && !defined(__DOXYGEN__) +extern ICUDriver ICUD12; +#endif + +#if SPC5_ICU_USE_SMOD12 && !defined(__DOXYGEN__) +extern ICUDriver ICUD13; +#endif + +#if SPC5_ICU_USE_SMOD13 && !defined(__DOXYGEN__) +extern ICUDriver ICUD14; +#endif + +#if SPC5_ICU_USE_SMOD14 && !defined(__DOXYGEN__) +extern ICUDriver ICUD15; +#endif + +#if SPC5_ICU_USE_SMOD15 && !defined(__DOXYGEN__) +extern ICUDriver ICUD16; +#endif + +#if SPC5_ICU_USE_SMOD16 && !defined(__DOXYGEN__) +extern ICUDriver ICUD17; +#endif + +#if SPC5_ICU_USE_SMOD17 && !defined(__DOXYGEN__) +extern ICUDriver ICUD18; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h b/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h new file mode 100644 index 000000000..390af2ec8 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h @@ -0,0 +1,316 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file eTimer_v1/etimer.h + * @brief SPC5xx eTimer header file. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ETIMER_H_ +#define _ETIMER_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief SPC5 FlexPWM registers block. + * @note Redefined from the SPC5 headers because the non uniform + * declaration of the SubModules registers among the various + * sub-families. + */ +struct spc5_etimer_submodule { + + union { + vuint16_t R; + struct { + vuint16_t COMP1 :16; + } B; + } COMP1; /* Compare Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t COMP2 :16; + } B; + } COMP2; /* Compare Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t CAPT1 :16; + } B; + } CAPT1; /* Capture Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CAPT2 :16; + } B; + } CAPT2; /* Capture Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t LOAD :16; + } B; + } LOAD; /* Load Register */ + + union { + vuint16_t R; + struct { + vuint16_t HOLD :16; + } B; + } HOLD; /* Hold Register */ + + union { + vuint16_t R; + struct { + vuint16_t CNTR :16; + } B; + } CNTR; /* Counter Register */ + + union { + vuint16_t R; + struct { + vuint16_t CNTMODE :3; + vuint16_t PRISRC :5; + vuint16_t ONCE :1; + vuint16_t LENGTH :1; + vuint16_t DIR :1; + vuint16_t SECSRC :5; + } B; + } CTRL; /* Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t OEN :1; + vuint16_t RDNT :1; + vuint16_t INPUT :1; + vuint16_t VAL :1; + vuint16_t FORCE :1; + vuint16_t COFRC :1; + vuint16_t COINIT :2; + vuint16_t SIPS :1; + vuint16_t PIPS :1; + vuint16_t OPS :1; + vuint16_t MSTR :1; + vuint16_t OUTMODE :4; + } B; + } CTRL2; /* Control Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t STPEN :1; + vuint16_t ROC :2; + vuint16_t FMODE :1; + vuint16_t FDIS :4; + vuint16_t C2FCNT :3; + vuint16_t C1FCNT :3; + vuint16_t DBGEN :2; + } B; + } CTRL3; /* Control Register 3 */ + + union { + vuint16_t R; + struct { + vuint16_t :6; + vuint16_t WDF :1; + vuint16_t RCF :1; + vuint16_t ICF2 :1; + vuint16_t ICF1 :1; + vuint16_t IEHF :1; + vuint16_t IELF :1; + vuint16_t TOF :1; + vuint16_t TCF2 :1; + vuint16_t TCF1 :1; + vuint16_t TCF :1; + } B; + } STS; /* Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t ICF2DE :1; + vuint16_t ICF1DE :1; + vuint16_t CMPLD2DE :1; + vuint16_t CMPLD1DE :1; + vuint16_t :2; + vuint16_t WDFIE :1; + vuint16_t RCFIE :1; + vuint16_t ICF2IE :1; + vuint16_t ICF1IE :1; + vuint16_t IEHFIE :1; + vuint16_t IELFIE :1; + vuint16_t TOFIE :1; + vuint16_t TCF2IE :1; + vuint16_t TCF1IE :1; + vuint16_t TCFIE :1; + } B; + } INTDMA; /* Interrupt and DMA Register */ + + union { + vuint16_t R; + struct { + vuint16_t CMPLD1 :16; + } B; + } CMPLD1; /* Compare Load Register 1 */ + + union { + vuint16_t R; + struct { + vuint16_t CMPLD2 :16; + } B; + } CMPLD2; /* Compare Load Register 2 */ + + union { + vuint16_t R; + struct { + vuint16_t CLC2 :3; + vuint16_t CLC1 :3; + vuint16_t CMPMODE :2; + vuint16_t CPT2MODE :2; + vuint16_t CPT1MODE :2; + vuint16_t CFWM :2; + vuint16_t ONESHOT :1; + vuint16_t ARM :1; + } B; + } CCCTRL; /* Compare and Capture Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t FILTCNT :3; + vuint16_t FILTPER :8; + } B; + } FILT; /* Input Filter Register */ + +}; +/* end of ETIMER_CHANNEL_tag */ + +struct spc5_etimer { + + struct spc5_etimer_submodule CHANNEL[8]; + + union { + vuint16_t R; + struct { + vuint16_t WDTOL :16; + } B; + } WDTOL; /* Watchdog Time-out Low Register */ + + union { + vuint16_t R; + struct { + vuint16_t WDTOH :16; + } B; + } WDTOH; /* Watchdog Time-out High Register */ + + union { + vuint16_t R; + struct { + vuint16_t :3; + vuint16_t FTEST :1; + vuint16_t FIE :4; + vuint16_t :4; + vuint16_t FLVL :4; + } B; + } FCTRL; /* Fault Control Register */ + + union { + vuint16_t R; + struct { + vuint16_t :4; + vuint16_t FFPIN :4; + vuint16_t :4; + vuint16_t FFLAG :4; + } B; + } FSTS; /* Fault Status Register */ + + union { + vuint16_t R; + struct { + vuint16_t :5; + vuint16_t FFILTCNT :3; + vuint16_t FFILTPER :8; + } B; + } FFILT; /* Fault Filter Register */ + + int16_t ETIMER_reserved1; + + union { + vuint16_t R; + struct { + vuint16_t :8; + vuint16_t ENBL :8; + } B; + } ENBL; /* Channel Enable Register */ + + int16_t ETIMER_reserved2; + + union { + vuint16_t R; + struct { + vuint16_t :11; + vuint16_t DREQ :5; + } B; + } DREQ[4]; /* DMA Request 0->3 Select Register */ + +}; +/* end of ETIMER_tag */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name FlexPWM units references + * @{ + */ +#if SPC5_HAS_ETIMER0 +#define SPC5_ETIMER_0 (*(volatile struct spc5_etimer *)0xFFE18000UL) +#endif + +#if SPC5_HAS_ETIMER1 +#define SPC5_ETIMER_1 (*(volatile struct spc5_etimer *)0xFFE1C000UL) +#endif + +#if SPC5_HAS_ETIMER2 +#define SPC5_ETIMER_2 (*(volatile struct spc5_etimer *)0xFFE20000UL) +#endif +/** @} */ + +#endif /* _FLEXPWM_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/os/hal/platforms/STM32/GPIOv1/pal_lld.c new file mode 100644 index 000000000..31eec7883 --- /dev/null +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.c @@ -0,0 +1,184 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/GPIOv1/pal_lld.c + * @brief STM32F1xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if STM32_HAS_GPIOG +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ + RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) +#elif STM32_HAS_GPIOE +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) +#else +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_AFIOEN) +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 I/O ports configuration. + * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks. + */ + rccEnableAPB2(APB2_EN_MASK, FALSE); + + /* + * Initial GPIO setup. + */ + GPIOA->ODR = config->PAData.odr; + GPIOA->CRH = config->PAData.crh; + GPIOA->CRL = config->PAData.crl; + GPIOB->ODR = config->PBData.odr; + GPIOB->CRH = config->PBData.crh; + GPIOB->CRL = config->PBData.crl; + GPIOC->ODR = config->PCData.odr; + GPIOC->CRH = config->PCData.crh; + GPIOC->CRL = config->PCData.crl; + GPIOD->ODR = config->PDData.odr; + GPIOD->CRH = config->PDData.crh; + GPIOD->CRL = config->PDData.crl; +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + GPIOE->ODR = config->PEData.odr; + GPIOE->CRH = config->PEData.crh; + GPIOE->CRL = config->PEData.crl; +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + GPIOF->ODR = config->PFData.odr; + GPIOF->CRH = config->PFData.crh; + GPIOF->CRL = config->PFData.crl; +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + GPIOG->ODR = config->PGData.odr; + GPIOG->CRH = config->PGData.crh; + GPIOG->CRL = config->PGData.crl; +#endif +#endif +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + static const uint8_t cfgtab[] = { + 4, /* PAL_MODE_RESET, implemented as input.*/ + 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ + 4, /* PAL_MODE_INPUT */ + 8, /* PAL_MODE_INPUT_PULLUP */ + 8, /* PAL_MODE_INPUT_PULLDOWN */ + 0, /* PAL_MODE_INPUT_ANALOG */ + 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ + 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/ + 0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/ + }; + uint32_t mh, ml, crh, crl, cfg; + unsigned i; + + if (mode == PAL_MODE_INPUT_PULLUP) + port->BSRR = mask; + else if (mode == PAL_MODE_INPUT_PULLDOWN) + port->BRR = mask; + cfg = cfgtab[mode]; + mh = ml = crh = crl = 0; + for (i = 0; i < 8; i++) { + ml <<= 4; + mh <<= 4; + crl <<= 4; + crh <<= 4; + if ((mask & 0x0080) == 0) + ml |= 0xf; + else + crl |= cfg; + if ((mask & 0x8000) == 0) + mh |= 0xf; + else + crh |= cfg; + mask <<= 1; + } + port->CRH = (port->CRH & mh) | crh; + port->CRL = (port->CRL & ml) | crl; +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/os/hal/platforms/STM32/GPIOv1/pal_lld.h new file mode 100644 index 000000000..56255ed1a --- /dev/null +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.h @@ -0,0 +1,334 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/GPIOv1/pal_lld.h + * @brief STM32F1xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/** + * @name STM32-specific I/O mode flags + * @{ + */ +/** + * @brief STM32 specific alternate push-pull output mode. + */ +#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 + +/** + * @brief STM32 specific alternate open-drain output mode. + */ +#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for ODR register.*/ + uint32_t odr; + /** Initial value for CRL register.*/ + uint32_t crl; + /** Initial value for CRH register.*/ + uint32_t crh; +} stm32_gpio_setup_t; + +/** + * @brief STM32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port A setup data.*/ + stm32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + stm32_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + stm32_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + stm32_gpio_setup_t PDData; +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + /** @brief Port E setup data.*/ + stm32_gpio_setup_t PEData; +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + /** @brief Port F setup data.*/ + stm32_gpio_setup_t PFData; +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief Port G setup data.*/ + stm32_gpio_setup_t PGData; +#endif +#endif +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the STM32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/** + * @brief GPIO port E identifier. + */ +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +#define IOPORT5 GPIOE +#endif + +/** + * @brief GPIO port F identifier. + */ +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +#define IOPORT6 GPIOF +#endif + +/** + * @brief GPIO port G identifier. + */ +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSRR = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BRR = (bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c new file mode 100644 index 000000000..a082842bc --- /dev/null +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -0,0 +1,238 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/GPIOv2/pal_lld.c + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if defined(STM32L1XX_MD) +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) +#define AHB_LPEN_MASK AHB_EN_MASK +#elif defined(STM32F0XX) +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOFEN) +#elif defined(STM32F2XX) +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) +#define AHB1_LPEN_MASK AHB1_EN_MASK +#elif defined(STM32F30X) || defined(STM32F37X) +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN) +#elif defined(STM32F4XX) +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) +#define AHB1_LPEN_MASK AHB1_EN_MASK +#else +#error "missing or unsupported platform for GPIOv2 PAL driver" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 I/O ports configuration. + * @details Ports A-D(E, F, G, H) clocks enabled. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks. + */ +#if defined(STM32L1XX_MD) + rccEnableAHB(AHB_EN_MASK, TRUE); + RCC->AHBLPENR |= AHB_LPEN_MASK; +#elif defined(STM32F0XX) + rccEnableAHB(AHB_EN_MASK, TRUE); +#elif defined(STM32F30X) || defined(STM32F37X) + rccEnableAHB(AHB_EN_MASK, TRUE); +#elif defined(STM32F2XX) || defined(STM32F4XX) + RCC->AHB1ENR |= AHB1_EN_MASK; + RCC->AHB1LPENR |= AHB1_LPEN_MASK; +#endif + + /* + * Initial GPIO setup. + */ + initgpio(GPIOA, &config->PAData); + initgpio(GPIOB, &config->PBData); + initgpio(GPIOC, &config->PCData); + initgpio(GPIOD, &config->PDData); +#if STM32_HAS_GPIOE + initgpio(GPIOE, &config->PEData); +#endif +#if STM32_HAS_GPIOF + initgpio(GPIOF, &config->PFData); +#endif +#if STM32_HAS_GPIOG + initgpio(GPIOG, &config->PGData); +#endif +#if STM32_HAS_GPIOH + initgpio(GPIOH, &config->PHData); +#endif +#if STM32_HAS_GPIOI + initgpio(GPIOI, &config->PIData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +#if 1 +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0; + uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2; + uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3; + uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5; + uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7; + uint32_t bit = 0; + while (TRUE) { + if ((mask & 1) != 0) { + uint32_t altrmask, m1, m2, m4; + + altrmask = altr << ((bit & 7) * 4); + m4 = 15 << ((bit & 7) * 4); + if (bit < 8) + port->AFRL = (port->AFRL & ~m4) | altrmask; + else + port->AFRH = (port->AFRH & ~m4) | altrmask; + m1 = 1 << bit; + port->OTYPER = (port->OTYPER & ~m1) | otyper; + m2 = 3 << (bit * 2); + port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; + port->PUPDR = (port->PUPDR & ~m2) | pupdr; + port->MODER = (port->MODER & ~m2) | moder; + } + mask >>= 1; + if (!mask) + return; + otyper <<= 1; + ospeedr <<= 2; + pupdr <<= 2; + moder <<= 2; + bit++; + } +} +#else +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm; + uint32_t m1 = (uint32_t)mask; + uint32_t m2 = 0; + uint32_t m4l = 0; + uint32_t m4h = 0; + uint32_t bit = 0; + do { + if ((mask & 1) != 0) { + m2 |= 3 << bit; + if (bit < 16) + m4l |= 15 << ((bit & 14) * 2); + else + m4h |= 15 << ((bit & 14) * 2); + } + bit += 2; + mask >>= 1; + } while (mask); + + afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111; + port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l); + port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h); + + ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555; + port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2); + + otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff; + port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1); + + pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555; + port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2); + + moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555; + port->MODER = (port->MODER & ~m2) | (moderm & m2); +} +#endif + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h new file mode 100644 index 000000000..82b04c7f4 --- /dev/null +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -0,0 +1,453 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/GPIOv2/pal_lld.h + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name STM32-specific I/O mode flags + * @{ + */ +#define PAL_STM32_MODE_MASK (3 << 0) +#define PAL_STM32_MODE_INPUT (0 << 0) +#define PAL_STM32_MODE_OUTPUT (1 << 0) +#define PAL_STM32_MODE_ALTERNATE (2 << 0) +#define PAL_STM32_MODE_ANALOG (3 << 0) + +#define PAL_STM32_OTYPE_MASK (1 << 2) +#define PAL_STM32_OTYPE_PUSHPULL (0 << 2) +#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2) + +#define PAL_STM32_OSPEED_MASK (3 << 3) +#define PAL_STM32_OSPEED_LOWEST (0 << 3) +#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X) +#define PAL_STM32_OSPEED_MID (1 << 3) +#else +#define PAL_STM32_OSPEED_MID1 (1 << 3) +#define PAL_STM32_OSPEED_MID2 (2 << 3) +#endif +#define PAL_STM32_OSPEED_HIGHEST (3 << 3) + +#define PAL_STM32_PUDR_MASK (3 << 5) +#define PAL_STM32_PUDR_FLOATING (0 << 5) +#define PAL_STM32_PUDR_PULLUP (1 << 5) +#define PAL_STM32_PUDR_PULLDOWN (2 << 5) + +#define PAL_STM32_ALTERNATE_MASK (15 << 7) +#define PAL_STM32_ALTERNATE(n) ((n) << 7) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ + PAL_STM32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_STM32_MODE_INPUT + +/** + * @brief This mode is implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLUP) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLDOWN) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \ + PAL_STM32_OTYPE_PUSHPULL) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ + PAL_STM32_OTYPE_OPENDRAIN) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief STM32 GPIO registers block. + */ +typedef struct { + + volatile uint32_t MODER; + volatile uint32_t OTYPER; + volatile uint32_t OSPEEDR; + volatile uint32_t PUPDR; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile union { + uint32_t W; + struct { + uint16_t set; + uint16_t clear; + } H; + } BSRR; + volatile uint32_t LCKR; + volatile uint32_t AFRL; + volatile uint32_t AFRH; +} GPIO_TypeDef; + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for MODER register.*/ + uint32_t moder; + /** Initial value for OTYPER register.*/ + uint32_t otyper; + /** Initial value for OSPEEDR register.*/ + uint32_t ospeedr; + /** Initial value for PUPDR register.*/ + uint32_t pupdr; + /** Initial value for ODR register.*/ + uint32_t odr; + /** Initial value for AFRL register.*/ + uint32_t afrl; + /** Initial value for AFRH register.*/ + uint32_t afrh; +} stm32_gpio_setup_t; + +/** + * @brief STM32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port A setup data.*/ + stm32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + stm32_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + stm32_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + stm32_gpio_setup_t PDData; +#if STM32_HAS_GPIOE + /** @brief Port E setup data.*/ + stm32_gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF + /** @brief Port F setup data.*/ + stm32_gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG + /** @brief Port G setup data.*/ + stm32_gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH + /** @brief Port H setup data.*/ + stm32_gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI + /** @brief Port I setup data.*/ + stm32_gpio_setup_t PIData; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the STM32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/** + * @brief GPIO port E identifier. + */ +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +#define IOPORT5 GPIOE +#endif + +/** + * @brief GPIO port F identifier. + */ +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +#define IOPORT6 GPIOF +#endif + +/** + * @brief GPIO port G identifier. + */ +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/** + * @brief GPIO port H identifier. + */ +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) +#define IOPORT8 GPIOH +#endif + +/** + * @brief GPIO port I identifier. + */ +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c new file mode 100644 index 000000000..ba5d0a140 --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c @@ -0,0 +1,902 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/I2Cv1/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define I2C1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_CHN) + +#define I2C1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_CHN) + +#define I2C2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_CHN) + +#define I2C2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_CHN) + +#define I2C3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_CHN) + +#define I2C3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_EV5_MASTER_MODE_SELECT \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) + +#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ + I2C_SR1_ADDR | I2C_SR1_TXE)) + +#define I2C_EV6_MASTER_REC_MODE_SELECTED \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR)) + +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ + I2C_SR1_BTF | I2C_SR1_TXE)) + +#define I2C_EV_MASK 0x00FFFFFF + +#define I2C_ERROR_MASK \ + ((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR | \ + I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/** @brief I2C3 driver identifier.*/ +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Aborts an I2C transaction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_abort_operation(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + /* Stops the I2C peripheral.*/ + dp->CR1 = I2C_CR1_SWRST; + dp->CR1 = 0; + dp->CR2 = 0; + dp->SR1 = 0; + + /* Stops the associated DMA streams.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); +} + +/** + * @brief Handling of stalled I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_safety_timeout(void *p) { + I2CDriver *i2cp = (I2CDriver *)p; + + chSysLockFromIsr(); + if (i2cp->thread) { + Thread *tp = i2cp->thread; + i2c_lld_abort_operation(i2cp); + i2cp->thread = NULL; + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + } + chSysUnlockFromIsr(); +} + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_clock(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint16_t regCCR, clock_div; + int32_t clock_speed = i2cp->config->clock_speed; + i2cdutycycle_t duty = i2cp->config->duty_cycle; + + chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), + "i2c_lld_set_clock"); + + /* CR2 Configuration.*/ + dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; + dp->CR2 |= (uint16_t)I2C_CLK_FREQ; + + /* CCR Configuration.*/ + regCCR = 0; + clock_div = I2C_CCR_CCR; + + if (clock_speed <= 100000) { + /* Configure clock_div in standard mode.*/ + chDbgAssert(duty == STD_DUTY_CYCLE, + "i2c_lld_set_clock(), #1", + "Invalid standard mode duty cycle"); + + /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, + "i2c_lld_set_clock(), #2", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); + + chDbgAssert(clock_div >= 0x04, + "i2c_lld_set_clock(), #3", + "Clock divider less then 0x04 not allowed"); + regCCR |= (clock_div & I2C_CCR_CCR); + + /* Sets the Maximum Rise Time for standard mode.*/ + dp->TRISE = I2C_CLK_FREQ + 1; + } + else if (clock_speed <= 400000) { + /* Configure clock_div in fast mode.*/ + chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9), + "i2c_lld_set_clock(), #4", + "Invalid fast mode duty cycle"); + + if (duty == FAST_DUTY_CYCLE_2) { + /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, + "i2c_lld_set_clock(), #5", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); + } + else if (duty == FAST_DUTY_CYCLE_16_9) { + /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, + "i2c_lld_set_clock(), #6", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); + regCCR |= I2C_CCR_DUTY; + } + + chDbgAssert(clock_div >= 0x01, + "i2c_lld_set_clock(), #7", + "Clock divider less then 0x04 not allowed"); + regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); + + /* Sets the Maximum Rise Time for fast mode.*/ + dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; + } + + chDbgAssert((clock_div <= I2C_CCR_CCR), + "i2c_lld_set_clock(), #8", "the selected clock is too low"); + + dp->CCR = regCCR; +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_opmode(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + i2copmode_t opmode = i2cp->config->op_mode; + uint16_t regCR1; + + regCR1 = dp->CR1; + switch (opmode) { + case OPMODE_I2C: + regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_DEVICE: + regCR1 |= I2C_CR1_SMBUS; + regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_HOST: + regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + } + dp->CR1 = regCR1; +} + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint32_t regSR2 = dp->SR2; + uint32_t event = dp->SR1; + + /* Interrupts are disabled just before dmaStreamEnable() because there + is no need of interrupts until next transaction begin. All the work is + done by the DMA.*/ + switch (I2C_EV_MASK & (event | (regSR2 << 16))) { + case I2C_EV5_MASTER_MODE_SELECT: + dp->DR = i2cp->addr; + break; + case I2C_EV6_MASTER_REC_MODE_SELECTED: + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dmaStreamEnable(i2cp->dmarx); + dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */ + if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) + dp->CR1 &= ~I2C_CR1_ACK; + break; + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dmaStreamEnable(i2cp->dmatx); + break; + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + /* Catches BTF event after the end of transmission.*/ + if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { + /* Starts "read after write" operation, LSB = 1 -> receive.*/ + i2cp->addr |= 0x01; + dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; + return; + } + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_STOP; + wakeup_isr(i2cp, RDY_OK); + break; + default: + break; + } + /* Clear ADDR flag. */ + if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)) + (void)dp->SR2; +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmarx); + + dp->CR2 &= ~I2C_CR2_LAST; + dp->CR1 &= ~I2C_CR1_ACK; + dp->CR1 |= I2C_CR1_STOP; + wakeup_isr(i2cp, RDY_OK); +} + +/** + * @brief DMA TX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmatx); + /* Enables interrupts to catch BTF event meaning transmission part complete. + Interrupt handler will decide to generate STOP or to begin receiving part + of R/W transaction itself.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] sr content of the SR1 register to be decoded + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { + + /* Clears interrupt flags just to be safe.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + + i2cp->errors = I2CD_NO_ERROR; + + if (sr & I2C_SR1_BERR) /* Bus error. */ + i2cp->errors |= I2CD_BUS_ERROR; + + if (sr & I2C_SR1_ARLO) /* Arbitration lost. */ + i2cp->errors |= I2CD_ARBITRATION_LOST; + + if (sr & I2C_SR1_AF) { /* Acknowledge fail. */ + i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN; + i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ + i2cp->errors |= I2CD_ACK_FAILURE; + } + + if (sr & I2C_SR1_OVR) /* Overrun. */ + i2cp->errors |= I2CD_OVERRUN; + + if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */ + i2cp->errors |= I2CD_TIMEOUT; + + if (sr & I2C_SR1_PECERR) /* PEC error. */ + i2cp->errors |= I2CD_PEC_ERROR; + + if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */ + i2cp->errors |= I2CD_SMB_ALERT; + + /* If some error has been identified then sends wakes the waiting thread.*/ + if (i2cp->errors != I2CD_NO_ERROR) + wakeup_isr(i2cp, RDY_RESET); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C1_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { + uint16_t sr = I2CD1.i2c->SR1; + + CH_IRQ_PROLOGUE(); + + I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK); + i2c_lld_serve_error_interrupt(&I2CD1, sr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { + uint16_t sr = I2CD2.i2c->SR1; + + CH_IRQ_PROLOGUE(); + + I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK); + i2c_lld_serve_error_interrupt(&I2CD2, sr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +/** + * @brief I2C3 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C3 error interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C3_ER_IRQHandler) { + uint16_t sr = I2CD3.i2c->SR1; + + CH_IRQ_PROLOGUE(); + + I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK); + i2c_lld_serve_error_interrupt(&I2CD3, sr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = I2C1; + I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); + I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + i2cObjectInit(&I2CD2); + I2CD2.thread = NULL; + I2CD2.i2c = I2C2; + I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); + I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 + i2cObjectInit(&I2CD3); + I2CD3.thread = NULL; + I2CD3.i2c = I2C3; + I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); + I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C3 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | + STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DIR_M2P; + i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | + STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DIR_P2M; + + /* If in stopped state then enables the I2C and DMA clocks.*/ + if (i2cp->state == I2C_STOP) { + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + bool_t b; + + rccResetI2C1(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); + rccEnableI2C1(FALSE); + nvicEnableVector(I2C1_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + nvicEnableVector(I2C1_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + + i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + bool_t b; + + rccResetI2C2(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); + rccEnableI2C2(FALSE); + nvicEnableVector(I2C2_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + nvicEnableVector(I2C2_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + + i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + bool_t b; + + rccResetI2C3(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated"); + rccEnableI2C3(FALSE); + nvicEnableVector(I2C3_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + nvicEnableVector(I2C3_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + + i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); + i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C3 */ + } + + /* I2C registers pointed by the DMA.*/ + dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); + dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); + + /* Reset i2c peripheral.*/ + dp->CR1 = I2C_CR1_SWRST; + dp->CR1 = 0; + dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; + + /* Setup I2C parameters.*/ + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + + /* Ready to go.*/ + dp->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2c_lld_abort_operation(i2cp); + dmaStreamRelease(i2cp->dmatx); + dmaStreamRelease(i2cp->dmarx); + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + nvicDisableVector(I2C1_EV_IRQn); + nvicDisableVector(I2C1_ER_IRQn); + rccDisableI2C1(FALSE); + } +#endif + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + nvicDisableVector(I2C2_EV_IRQn); + nvicDisableVector(I2C2_ER_IRQn); + rccDisableI2C2(FALSE); + } +#endif + +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + nvicDisableVector(I2C3_EV_IRQn); + nvicDisableVector(I2C3_ER_IRQn); + rccDisableI2C3(FALSE); + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on STM32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + +#if defined(STM32F1XX_I2C) + chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); +#endif + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields, LSB = 1 -> receive.*/ + i2cp->addr = (addr << 1) | 0x01; + i2cp->errors = 0; + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + +#if defined(STM32F1XX_I2C) + chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), + "i2c_lld_master_transmit_timeout"); +#endif + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields, LSB = 0 -> write.*/ + i2cp->addr = addr << 1; + i2cp->errors = 0; + + /* TX DMA setup.*/ + dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_START; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h new file mode 100644 index 000000000..dcadb3278 --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h @@ -0,0 +1,463 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/I2Cv1/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Peripheral clock frequency. + */ +#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 FALSE +#endif + +/** + * @brief I2C3 driver enable switch. + * @details If set to @p TRUE the support for I2C3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C3 FALSE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C3 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_IRQ_PRIORITY 10 +#endif + +/** +* @brief I2C1 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#endif + +/** +* @brief I2C2 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#endif + +/** +* @brief I2C3 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_DMA_PRIORITY 1 +#endif + +/** + * @brief I2C DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for I2C1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for I2C1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for I2C2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +/** + * @brief DMA stream used for I2C3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#endif /* !STM32_ADVANCED_DMA*/ + +/* Flag for the whole STM32F1XX family. */ +#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(STM32F10X_CL) +#define STM32F1XX_I2C +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief error checks */ +#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 +#error "I2C1 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 +#error "I2C2 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 +#error "I2C3 not present in the selected device" +#endif + +#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \ + !STM32_I2C_USE_I2C3 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 RX" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 TX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 RX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 TX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C3 RX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* Check clock range. */ +#if defined(STM32F4XX) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32L1XX_MD) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F2XX) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(STM32F10X_CL) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36) +#error "I2C peripheral clock frequency out of range." +#endif +#else +#error "unspecified, unsupported or invalid STM32 platform" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + OPMODE_I2C = 1, + OPMODE_SMBUS_DEVICE = 2, + OPMODE_SMBUS_HOST = 3, +} i2copmode_t; + +/** + * @brief Supported duty cycle modes for the I2C bus. + */ +typedef enum { + STD_DUTY_CYCLE = 1, + FAST_DUTY_CYCLE_2 = 2, + FAST_DUTY_CYCLE_16_9 = 3, +} i2cdutycycle_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_speed; /**< @brief Specifies the clock frequency. + @note Must be set to a value lower + than 400kHz. */ + i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode + duty cycle. */ +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#if STM32_I2C_USE_I2C3 +extern I2CDriver I2CD3; +#endif +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c new file mode 100644 index 000000000..1050dc08f --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c @@ -0,0 +1,789 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/I2Cv2/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define DMAMODE_COMMON \ + (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE) + +#define I2C1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_CHN) + +#define I2C1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_CHN) + +#define I2C2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_CHN) + +#define I2C2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_MASTER_TC \ + ((uint32_t)(I2C_ISR_BUSY | I2C_ISR_TC)) + +#define I2C_ERROR_MASK \ + ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \ + I2C_ISR_TIMEOUT | I2C_ISR_ALERT)) + +#define I2C_INT_MASK \ + ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \ + I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Aborts an I2C transaction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_abort_operation(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + if (dp->CR1 & I2C_CR1_PE) { + /* Stops the I2C peripheral.*/ + dp->CR1 &= ~I2C_CR1_PE; + while (dp->CR1 & I2C_CR1_PE) + dp->CR1 &= ~I2C_CR1_PE; + dp->CR1 |= I2C_CR1_PE; + } + + /* Stops the associated DMA streams.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); +} + +/** + * @brief Handling of stalled I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_safety_timeout(void *p) { + I2CDriver *i2cp = (I2CDriver *)p; + + chSysLockFromIsr(); + if (i2cp->thread) { + Thread *tp = i2cp->thread; + i2c_lld_abort_operation(i2cp); + i2cp->thread = NULL; + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + } + chSysUnlockFromIsr(); +} + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] isr content of the ISR register to be decoded + * + * @notapi + */ +static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) { + I2C_TypeDef *dp = i2cp->i2c; + + if ((isr & I2C_ISR_TC) && (i2cp->state == I2C_ACTIVE_TX)) { + size_t rxbytes; + + /* Make sure no more 'Transfer complete' interrupts.*/ + dp->CR1 &= ~I2C_CR1_TCIE; + + rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx); + if (rxbytes > 0) { + i2cp->state = I2C_ACTIVE_RX; + + /* Enable RX DMA */ + dmaStreamEnable(i2cp->dmarx); + + dp->CR2 &= ~I2C_CR2_NBYTES; + dp->CR2 |= rxbytes << 16; + + /* Starts the read operation.*/ + dp->CR2 |= I2C_CR2_RD_WRN; + dp->CR2 |= I2C_CR2_START; + } + else { + /* Nothing to receive - send STOP immediately.*/ + dp->CR2 |= I2C_CR2_STOP; + } + } + if (isr & I2C_ISR_NACKF) { + /* Starts a STOP sequence immediately on error.*/ + dp->CR2 |= I2C_CR2_STOP; + + i2cp->errors |= I2CD_ACK_FAILURE; + } + if (isr & I2C_ISR_STOPF) { + /* Stops the associated DMA streams.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + + if (i2cp->errors) { + wakeup_isr(i2cp, RDY_RESET); + } + else { + wakeup_isr(i2cp, RDY_OK); + } + } +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmarx); + dp->CR2 |= I2C_CR2_STOP; + wakeup_isr(i2cp, RDY_OK); +} + +/** + * @brief DMA TX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmatx); +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] isr content of the ISR register to be decoded + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) { + + /* Clears interrupt flags just to be safe.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + + if (isr & I2C_ISR_BERR) + i2cp->errors |= I2CD_BUS_ERROR; + + if (isr & I2C_ISR_ARLO) + i2cp->errors |= I2CD_ARBITRATION_LOST; + + if (isr & I2C_ISR_OVR) + i2cp->errors |= I2CD_OVERRUN; + + if (isr & I2C_ISR_TIMEOUT) + i2cp->errors |= I2CD_TIMEOUT; + + /* If some error has been identified then sends wakes the waiting thread.*/ + if (i2cp->errors != I2CD_NO_ERROR) + wakeup_isr(i2cp, RDY_RESET); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) { + uint32_t isr = I2CD1.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD1.i2c->ICR = isr; + + if (isr & I2C_ERROR_MASK) + i2c_lld_serve_error_interrupt(&I2CD1, isr); + else if (isr & I2C_INT_MASK) + i2c_lld_serve_interrupt(&I2CD1, isr); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER) +CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) { + uint32_t isr = I2CD1.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD1.i2c->ICR = isr & I2C_INT_MASK; + + i2c_lld_serve_interrupt(&I2CD1, isr); + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) { + uint32_t isr = I2CD1.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD1.i2c->ICR = isr & I2C_ERROR_MASK; + + i2c_lld_serve_error_interrupt(&I2CD1, isr); + + CH_IRQ_EPILOGUE(); +} + +#else +#error "I2C1 interrupt handlers not defined" +#endif +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) { + uint32_t isr = I2CD2.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD2.i2c->ICR = isr; + + if (isr & I2C_ERROR_MASK) + i2c_lld_serve_error_interrupt(&I2CD2, isr); + else if (isr & I2C_INT_MASK) + i2c_lld_serve_interrupt(&I2CD2, isr); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER) +CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) { + uint32_t isr = I2CD2.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD2.i2c->ICR = isr & I2C_INT_MASK; + + i2c_lld_serve_interrupt(&I2CD2, isr); + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) { + uint32_t isr = I2CD2.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + /* Clearing IRQ bits.*/ + I2CD2.i2c->ICR = isr & I2C_ERROR_MASK; + + i2c_lld_serve_error_interrupt(&I2CD2, isr); + + CH_IRQ_EPILOGUE(); +} + +#else +#error "I2C2 interrupt handlers not defined" +#endif +#endif /* STM32_I2C_USE_I2C2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = I2C1; + I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); + I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + i2cObjectInit(&I2CD2); + I2CD2.thread = NULL; + I2CD2.i2c = I2C2; + I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); + I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C2 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P; + i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M; + + /* Make sure I2C peripheral is disabled */ + dp->CR1 &= ~I2C_CR1_PE; + + /* If in stopped state then enables the I2C and DMA clocks.*/ + if (i2cp->state == I2C_STOP) { + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + bool_t b; + + rccResetI2C1(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); + rccEnableI2C1(FALSE); + +#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) + nvicEnableVector(STM32_I2C1_EVENT_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + nvicEnableVector(STM32_I2C1_ERROR_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#else +#error "I2C1 interrupt numbers not defined" +#endif + + i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + bool_t b; + + rccResetI2C2(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); + rccEnableI2C2(FALSE); + +#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); +#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) + nvicEnableVector(STM32_I2C2_EVENT_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + nvicEnableVector(STM32_I2C2_ERROR_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); +#else +#error "I2C2 interrupt numbers not defined" +#endif + + i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C2 */ + } + + /* I2C registers pointed by the DMA.*/ + dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR); + dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR); + + /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ + dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE | + I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN; + + /* Set slave address field (master mode) */ + dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD); + + /* Setup I2C parameters.*/ + dp->TIMINGR = i2cp->config->timingr; + + /* Ready to go.*/ + dp->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2c_lld_abort_operation(i2cp); + dmaStreamRelease(i2cp->dmatx); + dmaStreamRelease(i2cp->dmarx); + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { +#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER); +#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) + nvicDisableVector(STM32_I2C1_EVENT_NUMBER); + nvicDisableVector(STM32_I2C1_ERROR_NUMBER); +#else +#error "I2C1 interrupt numbers not defined" +#endif + + rccDisableI2C1(FALSE); + } +#endif + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { +#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER); +#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) + nvicDisableVector(STM32_I2C2_EVENT_NUMBER); + nvicDisableVector(STM32_I2C2_ERROR_NUMBER); +#else +#error "I2C2 interrupt numbers not defined" +#endif + + rccDisableI2C2(FALSE); + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on STM32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + uint32_t addr_cr2 = addr & I2C_CR2_SADD; + + chDbgCheck((rxbytes > 0), "i2c_lld_master_receive_timeout"); + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2CD_NO_ERROR; + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while (dp->ISR & I2C_ISR_BUSY) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Adjust slave address (master mode) for 7-bit address mode */ + if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0) + addr_cr2 = (addr_cr2 & 0x7f) << 1; + + /* Set slave address field (master mode) */ + dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); + dp->CR2 |= (rxbytes << 16) | addr_cr2; + + /* Initializes driver fields */ + i2cp->errors = 0; + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Enable RX DMA */ + dmaStreamEnable(i2cp->dmarx); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CR2 |= I2C_CR2_RD_WRN; + dp->CR2 |= I2C_CR2_START; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + uint32_t addr_cr2 = addr & I2C_CR2_SADD; + + chDbgCheck(((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))), + "i2c_lld_master_transmit_timeout"); + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2CD_NO_ERROR; + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while (dp->ISR & I2C_ISR_BUSY) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Adjust slave address (master mode) for 7-bit address mode */ + if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0) + addr_cr2 = (addr_cr2 & 0x7f) << 1; + + /* Set slave address field (master mode) */ + dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); + dp->CR2 |= (txbytes << 16) | addr_cr2; + + /* Initializes driver fields */ + i2cp->errors = 0; + + /* TX DMA setup.*/ + dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Enable TX DMA */ + dmaStreamEnable(i2cp->dmatx); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Transmission complete interrupt enabled.*/ + dp->CR1 |= I2C_CR1_TCIE; + + /* Starts the operation as the very last thing.*/ + dp->CR2 &= ~I2C_CR2_RD_WRN; + dp->CR2 |= I2C_CR2_START; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h new file mode 100644 index 000000000..810c7be84 --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/I2Cv2/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name TIMINGR register definitions + * @{ + */ +#define STM32_TIMINGR_PRESC_MASK (15U << 28) +#define STM32_TIMINGR_PRESC(n) ((n) << 28) +#define STM32_TIMINGR_SCLDEL_MASK (15U << 20) +#define STM32_TIMINGR_SCLDEL(n) ((n) << 20) +#define STM32_TIMINGR_SDADEL_MASK (15U << 16) +#define STM32_TIMINGR_SDADEL(n) ((n) << 16) +#define STM32_TIMINGR_SCLH_MASK (255U << 8) +#define STM32_TIMINGR_SCLH(n) ((n) << 8) +#define STM32_TIMINGR_SCLL_MASK (255U << 0) +#define STM32_TIMINGR_SCLL(n) ((n) << 0) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 FALSE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#endif + +/** + * @brief I2C2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#endif + +/** + * @brief I2C DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Streams for the DMA peripheral.*/ +#if defined(STM32F0XX) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#elif defined(STM32F30X) || defined(STM32F37X) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#else +#error "device unsupported by I2Cv2 driver" +#endif + +/** @brief error checks */ +#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 +#error "I2C1 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 +#error "I2C2 not present in the selected device" +#endif + +#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 RX" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 TX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 RX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* Check clock range. */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief TIMINGR register initialization. + * @note Refer to the STM32 reference manual, the values are affected + * by the system clock settings in mcuconf.h. + */ + uint32_t timingr; + /** + * @brief CR1 register initialization. + * @note Leave to zero unless you know what you are doing. + */ + uint32_t cr1; + /** + * @brief CR2 register initialization. + * @note Only the ADD10 bit can eventually be specified here. + */ + uint32_t cr2; +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/os/hal/platforms/STM32/OTGv1/stm32_otg.h new file mode 100644 index 000000000..a78ba57e4 --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/stm32_otg.h @@ -0,0 +1,916 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file stm32_otg.h + * @brief STM32 OTG registers layout header. + * + * @addtogroup USB + * @{ + */ + +#ifndef _STM32_OTG_H_ +#define _STM32_OTG_H_ + +/** + * @brief Number of the implemented endpoints in OTG_FS. + * @details This value does not include the endpoint 0 that is always present. + */ +#define STM32_OTG1_ENDOPOINTS_NUMBER 3 + +/** + * @brief Number of the implemented endpoints in OTG_HS. + * @details This value does not include the endpoint 0 that is always present. + */ +#define STM32_OTG2_ENDOPOINTS_NUMBER 5 + +/** + * @brief OTG_FS FIFO memory size in words. + */ +#define STM32_OTG1_FIFO_MEM_SIZE 384 + +/** + * @brief OTG_HS FIFO memory size in words. + */ +#define STM32_OTG2_FIFO_MEM_SIZE 1024 + +/** + * @brief Host channel registers group. + */ +typedef struct { + volatile uint32_t HCCHAR; /**< @brief Host channel characteristics + register. */ + volatile uint32_t resvd8; + volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ + volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask + register. */ + volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size + register. */ + volatile uint32_t resvd14; + volatile uint32_t resvd18; + volatile uint32_t resvd1c; +} stm32_otg_host_chn_t; + +/** + * @brief Device input endpoint registers group. + */ +typedef struct { + volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint + control register. */ + volatile uint32_t resvd4; + volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt + register. */ + volatile uint32_t resvdC; + volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size + register. */ + volatile uint32_t resvd14; + volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO + status register. */ + volatile uint32_t resvd1C; +} stm32_otg_in_ep_t; + +/** + * @brief Device output endpoint registers group. + */ +typedef struct { + volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint + control register. */ + volatile uint32_t resvd4; + volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt + register. */ + volatile uint32_t resvdC; + volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer + size register. */ + volatile uint32_t resvd14; + volatile uint32_t resvd18; + volatile uint32_t resvd1C; +} stm32_otg_out_ep_t; + +/** + * @brief USB registers memory map. + */ +typedef struct { + volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ + volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ + volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ + volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ + volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ + volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ + volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ + volatile uint32_t GRXSTSR; /**< @brief Receive status debug read + register. */ + volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop + register. */ + volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ + volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size + register. */ + volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue + status register. */ + volatile uint32_t resvd30; + volatile uint32_t resvd34; + volatile uint32_t GCCFG; /**< @brief General core configuration. */ + volatile uint32_t CID; /**< @brief Core ID register. */ + volatile uint32_t resvd58[48]; + volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size + register. */ + volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO + size registers. */ + volatile uint32_t resvd140[176]; + volatile uint32_t HCFG; /**< @brief Host configuration register. */ + volatile uint32_t HFIR; /**< @brief Host frame interval register. */ + volatile uint32_t HFNUM; /**< @brief Host frame number/frame time + Remaining register. */ + volatile uint32_t resvd40C; + volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue + status register. */ + volatile uint32_t HAINT; /**< @brief Host all channels interrupt + register. */ + volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask + register. */ + volatile uint32_t resvd41C[9]; + volatile uint32_t HPRT; /**< @brief Host port control and status + register. */ + volatile uint32_t resvd444[47]; + stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ + volatile uint32_t resvd700[64]; + volatile uint32_t DCFG; /**< @brief Device configuration register. */ + volatile uint32_t DCTL; /**< @brief Device control register. */ + volatile uint32_t DSTS; /**< @brief Device status register. */ + volatile uint32_t resvd80C; + volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common + interrupt mask register. */ + volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common + interrupt mask register. */ + volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt + register. */ + volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt + mask register. */ + volatile uint32_t resvd820; + volatile uint32_t resvd824; + volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time + register. */ + volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time + register. */ + volatile uint32_t resvd830; + volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty + interrupt mask register. */ + volatile uint32_t resvd838; + volatile uint32_t resvd83C; + volatile uint32_t resvd840[16]; + volatile uint32_t resvd880[16]; + volatile uint32_t resvd8C0[16]; + stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ + stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ + volatile uint32_t resvdD00[64]; + volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control + register. */ + volatile uint32_t resvdE04[127]; + volatile uint32_t FIFO[16][1024]; +} stm32_otg_t; + +/** + * @name GOTGCTL register bit definitions + * @{ + */ +#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ +#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ +#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ +#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ +#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ +#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ +#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ +#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ +#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ +#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ +/** @} */ + +/** + * @name GOTGINT register bit definitions + * @{ + */ +#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ +#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ +#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ +#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success + status change. */ +#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success + status change. */ +#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ +/** @} */ + +/** + * @name GAHBCFG register bit definitions + * @{ + */ +#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty + level. */ +#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty + level. */ +#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ +#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS + only). */ +#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS + only). */ +#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ +/** @} */ + +/** + * @name GUSBCFG register bit definitions + * @{ + */ +#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ +#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ +#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ +#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field + mask. */ +#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field + value. */ +#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ +#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ +#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or + USB 1.1 Full-Speed serial + transceiver Select. */ +#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration + field mask. */ +#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration + field value. */ +/** @} */ + +/** + * @name GRSTCTL register bit definitions + * @{ + */ +#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ +#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ +#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ +#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ +#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ +#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ +#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ +#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ +/** @} */ + +/** + * @name GINTSTS register bit definitions + * @{ + */ +#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup + detected interrupt. */ +#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session + detected interrupt. */ +#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected + interrupt. */ +#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ +#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ +#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ +#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ +#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic + transfer. */ +#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT + transfer. */ +#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN + transfer. */ +#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ +#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ +#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame + interrupt. */ +#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet + dropped interrupt. */ +#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ +#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ +#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ +#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ +#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ +#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK + effective. */ +#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ +#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ +#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ +#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ +#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ +#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ +/** @} */ + +/** + * @name GINTMSK register bit definitions + * @{ + */ +#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup + detected interrupt mask. */ +#define GINTMSK_SRQM (1U<<30) /**< Session request/New session + detected interrupt mask. */ +#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected + interrupt mask. */ +#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change + mask. */ +#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ +#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt + mask. */ +#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ +#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic + transfer mask. */ +#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT + transfer mask. */ +#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN + transfer mask. */ +#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt + mask. */ +#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt + mask. */ +#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame + interrupt mask. */ +#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet + dropped interrupt mask. */ +#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ +#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ +#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ +#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ +#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective + mask. */ +#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK + effective mask. */ +#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty + mask. */ +#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty + mask. */ +#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ +#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ +#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt + mask. */ +/** @} */ + +/** + * @name GRXSTSR register bit definitions + * @{ + */ +#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ +#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) +#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) +#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) +#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) +#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) +#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ +#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ +#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ +#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +/** @} */ + +/** + * @name GRXSTSP register bit definitions + * @{ + */ +#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ +#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) +#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) +#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) +#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) +#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) +#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ +#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ +#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ +#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ +#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ +#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +/** @} */ + +/** + * @name GRXFSIZ register bit definitions + * @{ + */ +#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ +#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ +/** @} */ + +/** + * @name DIEPTXFx register bit definitions + * @{ + */ +#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth + mask. */ +#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth + value. */ +#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit + RAM start address mask. */ +#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit + RAM start address value. */ +/** @} */ + +/** + * @name GCCFG register bit definitions + * @{ + */ +#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ +#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ +#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" + device. */ +#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" + device. */ +#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ +/** @} */ + +/** + * @name HPTXFSIZ register bit definitions + * @{ + */ +#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO + depth mask. */ +#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO + depth value. */ +#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO + Start address mask. */ +#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO + start address value. */ +/** @} */ + +/** + * @name HCFG register bit definitions + * @{ + */ +#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ +#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select + mask. */ +#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at + 48 MHz. */ +#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at + 6 MHz. */ +/** @} */ + +/** + * @name HFIR register bit definitions + * @{ + */ +#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ +#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ +/** @} */ + +/** + * @name HFNUM register bit definitions + * @{ + */ +#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ +#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ +#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ +#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ +/** @} */ + +/** + * @name HPTXSTS register bit definitions + * @{ + */ +#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic + transmit request queue + mask. */ +#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic + transmit request queue + value. */ +#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request + queue Space Available + mask. */ +#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request + queue Space Available + value. */ +#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data + FIFO Space Available + mask. */ +#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data + FIFO Space Available + value. */ +/** @} */ + +/** + * @name HAINT register bit definitions + * @{ + */ +#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ +#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ +/** @} */ + +/** + * @name HAINTMSK register bit definitions + * @{ + */ +#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask + mask. */ +#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask + value. */ +/** @} */ + +/** + * @name HPRT register bit definitions + * @{ + */ +#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ +#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ +#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ +#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ +#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ +#define HPRT_PPWR (1U<<12) /**< Port power. */ +#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ +#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ +#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ +#define HPRT_PRST (1U<<8) /**< Port reset. */ +#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ +#define HPRT_PRES (1U<<6) /**< Port Resume. */ +#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ +#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ +#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ +#define HPRT_PENA (1U<<2) /**< Port enable. */ +#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ +#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ +/** @} */ + +/** + * @name HCCHAR register bit definitions + * @{ + */ +#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ +#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ +#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ +#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ +#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ +#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ +#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ +#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ +#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ +#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ +#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ +#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ +#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ +#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ +#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ +#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ +#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ +#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */ +#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */ +/** @} */ + +/** + * @name HCINT register bit definitions + * @{ + */ +#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ +#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ +#define HCINT_BBERR (1U<<8) /**< Babble error. */ +#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ +#define HCINT_ACK (1U<<5) /**< ACK response + received/transmitted + interrupt. */ +#define HCINT_NAK (1U<<4) /**< NAK response received + interrupt. */ +#define HCINT_STALL (1U<<3) /**< STALL response received + interrupt. */ +#define HCINT_CHH (1U<<1) /**< Channel halted. */ +#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ +/** @} */ + +/** + * @name HCINTMSK register bit definitions + * @{ + */ +#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ +#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ +#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ +#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ +#define HCINTMSK_NYET (1U<<6) /**< NYET response received + interrupt mask. */ +#define HCINTMSK_ACKM (1U<<5) /**< ACK Response + received/transmitted + interrupt mask. */ +#define HCINTMSK_NAKM (1U<<4) /**< NAK response received + interrupt mask. */ +#define HCINTMSK_STALLM (1U<<3) /**< STALL response received + interrupt mask. */ +#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ +#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ +/** @} */ + +/** + * @name HCTSIZ register bit definitions + * @{ + */ +#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ +#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ +#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ +#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ +#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ +#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ +#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ +#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ +#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +/** @} */ + +/** + * @name DCFG register bit definitions + * @{ + */ +#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval + mask. */ +#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval + value. */ +#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ +#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ +#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status + OUT handshake. */ +#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ +#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ +#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS + mode. */ +#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 + transceiver clock is 48 + MHz). */ +/** @} */ + +/** + * @name DCTL register bit definitions + * @{ + */ +#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ +#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ +#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ +#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic + IN NAK. */ +#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic + IN NAK. */ +#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ +#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ +#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ +#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN + NAK status. */ +#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ +#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ +/** @} */ + +/** + * @name DSTS register bit definitions + * @{ + */ +#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received + SOF mask. */ +#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received + SOF value. */ +#define DSTS_EERR (1U<<3) /**< Erratic error. */ +#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ +#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is + running at 48 MHz). */ +#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ +/** @} */ + +/** + * @name DIEPMSK register bit definitions + * @{ + */ +#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ +#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective + mask. */ +#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when + TxFIFO empty mask. */ +#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ +#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled + interrupt mask. */ +#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed + interrupt mask. */ +/** @} */ + +/** + * @name DOEPMSK register bit definitions + * @{ + */ +#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when + endpoint disabled mask. */ +#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ +#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled + interrupt mask. */ +#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed + interrupt mask. */ +/** @} */ + +/** + * @name DAINT register bit definitions + * @{ + */ +#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt + bits mask. */ +#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt + bits value. */ +#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt + bits mask. */ +#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt + bits value. */ +/** @} */ + +/** + * @name DAINTMSK register bit definitions + * @{ + */ +#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask + bits mask. */ +#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask + bits value. */ +#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask + bits mask. */ +#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask + bits value. */ +/** @} */ + +/** + * @name DVBUSDIS register bit definitions + * @{ + */ +#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge + time mask. */ +#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge + time value. */ +/** @} */ + +/** + * @name DVBUSPULSE register bit definitions + * @{ + */ +#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time + mask. */ +#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time + value. */ +/** @} */ + +/** + * @name DIEPEMPMSK register bit definitions + * @{ + */ +#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty + interrupt mask bit. */ +/** @} */ + +/** + * @name DIEPCTL register bit definitions + * @{ + */ +#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ +#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ +#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ +#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ +#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ +#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ +#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ +#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ +#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ +#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ +#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ +#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ +#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ +#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ +#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ +#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ +#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ +#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ +#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ +#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ +#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ +#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ +#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ +/** @} */ + +/** + * @name DIEPINT register bit definitions + * @{ + */ +#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ +#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ +#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when + TxFIFO is empty. */ +#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ +#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled + interrupt. */ +#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ +/** @} */ + +/** + * @name DIEPTSIZ register bit definitions + * @{ + */ +#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ +#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ +#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ +#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ +#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ +#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +/** @} */ + +/** + * @name DTXFSTS register bit definitions. + * @{ + */ +#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space + available. */ +/** @} */ + +/** + * @name DOEPCTL register bit definitions. + * @{ + */ +#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ +#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ +#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ +#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ +#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ +#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ +#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ +#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ +#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ +#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ +#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ +#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ +#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ +#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ +#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ +#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ +#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ +#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ +#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ +#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ +#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ +/** @} */ + +/** + * @name DOEPINT register bit definitions + * @{ + */ +#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets + received. */ +#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when + endpoint disabled. */ +#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ +#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled + interrupt. */ +#define DOEPINT_XFRC (1U<<0) /**< Transfer completed + interrupt. */ +/** @} */ + +/** + * @name DOEPTSIZ register bit definitions + * @{ + */ +#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ +#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ +#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ +#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ +#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ +#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ +#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ +#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +/** @} */ + +/** + * @name PCGCCTL register bit definitions + * @{ + */ +#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ +#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ +#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ +/** @} */ + +/** + * @brief OTG_FS registers block memory address. + */ +#define OTG_FS_ADDR 0x50000000 + +/** + * @brief OTG_HS registers block memory address. + */ +#define OTG_HS_ADDR 0x40040000 + +/** + * @brief Accesses to the OTG_FS registers block. + */ +#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR) + +/** + * @brief Accesses to the OTG_HS registers block. + */ +#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR) + +#endif /* _STM32_OTG_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.c b/os/hal/platforms/STM32/OTGv1/usb_lld.c new file mode 100644 index 000000000..f6287a49c --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/usb_lld.c @@ -0,0 +1,1300 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/OTGv1/usb_lld.c + * @brief STM32 USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define TRDT_VALUE 5 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief OTG_FS driver identifier.*/ +#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/** @brief OTG_HS driver identifier.*/ +#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) +USBDriver USBD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out, + 1, + ep0setup_buffer +}; + +#if STM32_USB_USE_OTG1 +static const stm32_otg_params_t fsparams = { + STM32_USB_OTG1_RX_FIFO_SIZE / 4, + STM32_OTG1_FIFO_MEM_SIZE, + STM32_OTG1_ENDOPOINTS_NUMBER +}; +#endif + +#if STM32_USB_USE_OTG2 +static const stm32_otg_params_t hsparams = { + STM32_USB_OTG2_RX_FIFO_SIZE / 4, + STM32_OTG2_FIFO_MEM_SIZE, + STM32_OTG2_ENDOPOINTS_NUMBER +}; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the pump thread. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void usb_lld_wakeup_pump(USBDriver *usbp) { + + if (usbp->thd_wait != NULL) { + chThdResumeI(usbp->thd_wait); + usbp->thd_wait = NULL; + } +} + +static void otg_core_reset(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + + /* Core reset and delay of at least 3 PHY cycles.*/ + otgp->GRSTCTL = GRSTCTL_CSRST; + while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) + ; + halPolledDelay(12); + /* Wait AHB idle condition.*/ + while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) + ; +} + +static void otg_disable_ep(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + unsigned i; + + for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { + /* Disable only if enabled because this sentence in the manual: + "The application must set this bit only if Endpoint Enable is + already set for this endpoint".*/ + if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) { + otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS; + /* Wait for endpoint disable.*/ + while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD)) + ; + } + else + otgp->ie[i].DIEPCTL = 0; + otgp->ie[i].DIEPTSIZ = 0; + otgp->ie[i].DIEPINT = 0xFFFFFFFF; + /* Disable only if enabled because this sentence in the manual: + "The application must set this bit only if Endpoint Enable is + already set for this endpoint". + Note that the attempt to disable the OUT EP0 is ignored by the + hardware but the code is simpler this way.*/ + if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) { + otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS; + /* Wait for endpoint disable.*/ + while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS)) + ; + } + else + otgp->oe[i].DOEPCTL = 0; + otgp->oe[i].DOEPTSIZ = 0; + otgp->oe[i].DOEPINT = 0xFFFFFFFF; + } + otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); +} + +static void otg_rxfifo_flush(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + + otgp->GRSTCTL = GRSTCTL_RXFFLSH; + while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) + ; + /* Wait for 3 PHY Clocks.*/ + halPolledDelay(12); +} + +static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) { + stm32_otg_t *otgp = usbp->otg; + + otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; + while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) + ; + /* Wait for 3 PHY Clocks.*/ + halPolledDelay(12); +} + +/** + * @brief Resets the FIFO RAM memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_ram_reset(USBDriver *usbp) { + + usbp->pmnext = usbp->otgparams->rx_fifo_size; +} + +/** + * @brief Allocates a block from the FIFO RAM memory. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] size size of the packet buffer to allocate in words + * + * @notapi + */ +static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) { + uint32_t next; + + next = usbp->pmnext; + usbp->pmnext += size; + chDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size, + "otg_fifo_alloc(), #1", "OTG FIFO memory overflow"); + return next; +} + +/** + * @brief Pushes a series of words into a FIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] buf pointer to the words buffer, not necessarily word + * aligned + * @param[in] n number of words to push + * + * @return A pointer after the last word pushed. + * + * @notapi + */ +static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) { + + while (n > 0) { + /* Note, this line relies on the Cortex-M3/M4 ability to perform + unaligned word accesses and on the LSB-first memory organization.*/ + *fifop = *((uint32_t *)buf); + buf += 4; + n--; + } + return buf; +} + +/** + * @brief Writes to a TX FIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] buf buffer where to copy the endpoint data + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +static void otg_fifo_write_from_buffer(volatile uint32_t *fifop, + const uint8_t *buf, + size_t n) { + + otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4); +} + +/** + * @brief Writes to a TX FIFO fetching data from a queue. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] oqp pointer to an @p OutputQueue object + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +static void otg_fifo_write_from_queue(volatile uint32_t *fifop, + OutputQueue *oqp, + size_t n) { + size_t ntogo; + + ntogo = n; + while (ntogo > 0) { + uint32_t w, i; + size_t nw = ntogo / 4; + + if (nw > 0) { + size_t streak; + uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4; + + ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4; + oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak); + if (oqp->q_rdptr >= oqp->q_top) { + oqp->q_rdptr = oqp->q_buffer; + continue; + } + } + + /* If this condition is not satisfied then there is a word lying across + queue circular buffer boundary or there are some remaining bytes.*/ + if (ntogo <= 0) + break; + + /* One byte at time.*/ + w = 0; + i = 0; + while ((ntogo > 0) && (i < 4)) { + w |= (uint32_t)*oqp->q_rdptr++ << (i * 8); + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + ntogo--; + i++; + } + *fifop = w; + } + + /* Updating queue.*/ + chSysLock(); + oqp->q_counter += n; + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Pops a series of words from a FIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] buf pointer to the words buffer, not necessarily word + * aligned + * @param[in] n number of words to push + * + * @return A pointer after the last word pushed. + * + * @notapi + */ +static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) { + + while (n > 0) { + uint32_t w = *fifop; + /* Note, this line relies on the Cortex-M3/M4 ability to perform + unaligned word accesses and on the LSB-first memory organization.*/ + *((uint32_t *)buf) = w; + buf += 4; + n--; + } + return buf; +} + +/** + * @brief Reads a packet from the RXFIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[out] buf buffer where to copy the endpoint data + * @param[in] n number of bytes to pull from the FIFO + * @param[in] max number of bytes to copy into the buffer + * + * @notapi + */ +static void otg_fifo_read_to_buffer(volatile uint32_t *fifop, + uint8_t *buf, + size_t n, + size_t max) { + + n = (n + 3) / 4; + max = (max + 3) / 4; + while (n) { + uint32_t w = *fifop; + if (max) { + /* Note, this line relies on the Cortex-M3/M4 ability to perform + unaligned word accesses and on the LSB-first memory organization.*/ + *((uint32_t *)buf) = w; + buf += 4; + max--; + } + n--; + } +} + +/** + * @brief Reads a packet from the RXFIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] iqp pointer to an @p InputQueue object + * @param[in] n number of bytes to pull from the FIFO + * + * @notapi + */ +static void otg_fifo_read_to_queue(volatile uint32_t *fifop, + InputQueue *iqp, + size_t n) { + size_t ntogo; + + ntogo = n; + while (ntogo > 0) { + uint32_t w, i; + size_t nw = ntogo / 4; + + if (nw > 0) { + size_t streak; + uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4; + + ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4; + iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak); + if (iqp->q_wrptr >= iqp->q_top) { + iqp->q_wrptr = iqp->q_buffer; + continue; + } + } + + /* If this condition is not satisfied then there is a word lying across + queue circular buffer boundary or there are some remaining bytes.*/ + if (ntogo <= 0) + break; + + /* One byte at time.*/ + w = *fifop; + i = 0; + while ((ntogo > 0) && (i < 4)) { + *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8)); + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + ntogo--; + i++; + } + } + + /* Updating queue.*/ + chSysLock(); + iqp->q_counter += n; + while (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Incoming packets handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_rxfifo_handler(USBDriver *usbp) { + uint32_t sts, cnt, ep; + + sts = usbp->otg->GRXSTSP; + switch (sts & GRXSTSP_PKTSTS_MASK) { + case GRXSTSP_SETUP_COMP: + break; + case GRXSTSP_SETUP_DATA: + cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; + ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; + otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf, + cnt, 8); + break; + case GRXSTSP_OUT_DATA: + cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; + ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; + if (usbp->epc[ep]->out_state->rxqueued) { + /* Queue associated.*/ + otg_fifo_read_to_queue(usbp->otg->FIFO[0], + usbp->epc[ep]->out_state->mode.queue.rxqueue, + cnt); + } + else { + otg_fifo_read_to_buffer(usbp->otg->FIFO[0], + usbp->epc[ep]->out_state->mode.linear.rxbuf, + cnt, + usbp->epc[ep]->out_state->rxsize - + usbp->epc[ep]->out_state->rxcnt); + usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt; + } + usbp->epc[ep]->out_state->rxcnt += cnt; + break; + case GRXSTSP_OUT_GLOBAL_NAK: + case GRXSTSP_OUT_COMP: + default: + ; + } +} + +/** + * @brief Outgoing packets handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { + + /* The TXFIFO is filled until there is space and data to be transmitted.*/ + while (TRUE) { + uint32_t n; + + /* Transaction end condition.*/ + if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) + return TRUE; + + /* Number of bytes remaining in current transaction.*/ + n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt; + if (n > usbp->epc[ep]->in_maxsize) + n = usbp->epc[ep]->in_maxsize; + + /* Checks if in the TXFIFO there is enough space to accommodate the + next packet.*/ + if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n) + return FALSE; + +#if STM32_USB_OTGFIFO_FILL_BASEPRI + __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI)); +#endif + /* Handles the two cases: linear buffer or queue.*/ + if (usbp->epc[ep]->in_state->txqueued) { + /* Queue associated.*/ + otg_fifo_write_from_queue(usbp->otg->FIFO[ep], + usbp->epc[ep]->in_state->mode.queue.txqueue, + n); + } + else { + /* Linear buffer associated.*/ + otg_fifo_write_from_buffer(usbp->otg->FIFO[ep], + usbp->epc[ep]->in_state->mode.linear.txbuf, + n); + usbp->epc[ep]->in_state->mode.linear.txbuf += n; + } + usbp->epc[ep]->in_state->txcnt += n; + } +#if STM32_USB_OTGFIFO_FILL_BASEPRI + __set_BASEPRI(0); +#endif +} + +/** + * @brief Generic endpoint IN handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { + stm32_otg_t *otgp = usbp->otg; + uint32_t epint = otgp->ie[ep].DIEPINT; + + otgp->ie[ep].DIEPINT = 0xFFFFFFFF; + + if (epint & DIEPINT_TOC) { + /* Timeouts not handled yet, not sure how to handle.*/ + } + if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) { + /* Transmit transfer complete.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + if ((epint & DIEPINT_TXFE) && + (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) { + /* The thread is made ready, it will be scheduled on ISR exit.*/ + chSysLockFromIsr(); + usbp->txpending |= (1 << ep); + otgp->DIEPEMPMSK &= ~(1 << ep); + usb_lld_wakeup_pump(usbp); + chSysUnlockFromIsr(); + } +} + +/** + * @brief Generic endpoint OUT handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { + stm32_otg_t *otgp = usbp->otg; + uint32_t epint = otgp->oe[ep].DOEPINT; + + /* Resets all EP IRQ sources.*/ + otgp->oe[ep].DOEPINT = 0xFFFFFFFF; + + if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) { + /* Setup packets handling, setup packets are handled using a + specific callback.*/ + _usb_isr_invoke_setup_cb(usbp, ep); + + } + if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) { + /* Receive transfer complete.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } +} + +/** + * @brief OTG shared ISR. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void usb_lld_serve_interrupt(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + uint32_t sts, src; + + sts = otgp->GINTSTS & otgp->GINTMSK; + otgp->GINTSTS = sts; + + /* Reset interrupt handling.*/ + if (sts & GINTSTS_USBRST) { + _usb_reset(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); + } + + /* Enumeration done.*/ + if (sts & GINTSTS_ENUMDNE) { + (void)otgp->DSTS; + } + + /* SOF interrupt handling.*/ + if (sts & GINTSTS_SOF) { + _usb_isr_invoke_sof_cb(usbp); + } + + /* RX FIFO not empty handling.*/ + if (sts & GINTSTS_RXFLVL) { + /* The interrupt is masked while the thread has control or it would + be triggered again.*/ + chSysLockFromIsr(); + otgp->GINTMSK &= ~GINTMSK_RXFLVLM; + usb_lld_wakeup_pump(usbp); + chSysUnlockFromIsr(); + } + + /* IN/OUT endpoints event handling.*/ + src = otgp->DAINT; + if (sts & GINTSTS_IEPINT) { + if (src & (1 << 0)) + otg_epin_handler(usbp, 0); + if (src & (1 << 1)) + otg_epin_handler(usbp, 1); + if (src & (1 << 2)) + otg_epin_handler(usbp, 2); + if (src & (1 << 3)) + otg_epin_handler(usbp, 3); +#if STM32_USB_USE_OTG2 + if (src & (1 << 4)) + otg_epin_handler(usbp, 4); + if (src & (1 << 5)) + otg_epin_handler(usbp, 5); +#endif + } + if (sts & GINTSTS_OEPINT) { + if (src & (1 << 16)) + otg_epout_handler(usbp, 0); + if (src & (1 << 17)) + otg_epout_handler(usbp, 1); + if (src & (1 << 18)) + otg_epout_handler(usbp, 2); + if (src & (1 << 19)) + otg_epout_handler(usbp, 3); +#if STM32_USB_USE_OTG2 + if (src & (1 << 20)) + otg_epout_handler(usbp, 4); + if (src & (1 << 21)) + otg_epout_handler(usbp, 5); +#endif + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers and threads. */ +/*===========================================================================*/ + +static msg_t usb_lld_pump(void *p) { + USBDriver *usbp = (USBDriver *)p; + stm32_otg_t *otgp = usbp->otg; + + chRegSetThreadName("usb_lld_pump"); + chSysLock(); + while (TRUE) { + usbep_t ep; + uint32_t epmask; + + /* Nothing to do, going to sleep.*/ + if ((usbp->state == USB_STOP) || + ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) { + otgp->GINTMSK |= GINTMSK_RXFLVLM; + usbp->thd_wait = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + } + chSysUnlock(); + + /* Checks if there are TXFIFOs to be filled.*/ + for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { + + /* Empties the RX FIFO.*/ + while (otgp->GINTSTS & GINTSTS_RXFLVL) { + otg_rxfifo_handler(usbp); + } + + epmask = (1 << ep); + if (usbp->txpending & epmask) { + bool_t done; + + chSysLock(); + /* USB interrupts are globally *suspended* because the peripheral + does not allow any interference during the TX FIFO filling + operation. + Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) + "The application has to finish writing one complete packet before + switching to a different channel/endpoint FIFO. Violating this + rule results in an error.".*/ + otgp->GAHBCFG &= ~GAHBCFG_GINTMSK; + usbp->txpending &= ~epmask; + chSysUnlock(); + + done = otg_txfifo_handler(usbp, ep); + + chSysLock(); + otgp->GAHBCFG |= GAHBCFG_GINTMSK; + if (!done) + otgp->DIEPEMPMSK |= epmask; + chSysUnlock(); + } + } + chSysLock(); + } + chSysUnlock(); + return 0; +} + +#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) +#if !defined(STM32_OTG1_HANDLER) +#error "STM32_OTG1_HANDLER not defined" +#endif +/** + * @brief OTG1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_OTG1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + usb_lld_serve_interrupt(&USBD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) +#if !defined(STM32_OTG2_HANDLER) +#error "STM32_OTG2_HANDLER not defined" +#endif +/** + * @brief OTG2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_OTG2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + usb_lld_serve_interrupt(&USBD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + + /* Driver initialization.*/ +#if STM32_USB_USE_OTG1 + usbObjectInit(&USBD1); + USBD1.thd_ptr = NULL; + USBD1.thd_wait = NULL; + USBD1.otg = OTG_FS; + USBD1.otgparams = &fsparams; + + /* Filling the thread working area here because the function + @p chThdCreateI() does not do it.*/ +#if CH_DBG_FILL_THREADS + { + void *wsp = USBD1.wa_pump; + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + sizeof(USBD1.wa_pump) - sizeof(Thread), + CH_STACK_FILL_VALUE); + } +#endif +#endif + +#if STM32_USB_USE_OTG2 + usbObjectInit(&USBD2); + USBD2.thd_ptr = NULL; + USBD2.thd_wait = NULL; + USBD2.otg = OTG_HS; + USBD2.otgparams = &hsparams; + + /* Filling the thread working area here because the function + @p chThdCreateI() does not do it.*/ +#if CH_DBG_FILL_THREADS + { + void *wsp = USBD2.wa_pump; + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + sizeof(USBD2.wa_pump) - sizeof(Thread), + CH_STACK_FILL_VALUE); + } +#endif +#endif +} + +/** + * @brief Configures and activates the USB peripheral. + * @note Starting the OTG cell can be a slow operation carried out with + * interrupts disabled, perform it before starting time-critical + * operations. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + + if (usbp->state == USB_STOP) { + /* Clock activation.*/ +#if STM32_USB_USE_OTG1 + if (&USBD1 == usbp) { + /* OTG FS clock enable and reset.*/ + rccEnableOTG_FS(FALSE); + rccResetOTG_FS(); + + /* Enables IRQ vector.*/ + nvicEnableVector(STM32_OTG1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY)); + } +#endif +#if STM32_USB_USE_OTG2 + if (&USBD2 == usbp) { + /* OTG HS clock enable and reset.*/ + rccEnableOTG_HS(FALSE); + rccResetOTG_HS(); + + /* Enables IRQ vector.*/ + nvicEnableVector(STM32_OTG2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY)); + } +#endif + + /* Creates the data pump threads in a suspended state. Note, it is + created only once, the first time @p usbStart() is invoked.*/ + usbp->txpending = 0; + if (usbp->thd_ptr == NULL) + usbp->thd_ptr = usbp->thd_wait = chThdCreateI(usbp->wa_pump, + sizeof usbp->wa_pump, + STM32_USB_OTG_THREAD_PRIO, + usb_lld_pump, + usbp); + + /* - Forced device mode. + - USB turn-around time = TRDT_VALUE. + - Full Speed 1.1 PHY.*/ + otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL; + + /* 48MHz 1.1 PHY.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; + + /* PHY enabled.*/ + otgp->PCGCCTL = 0; + + /* Internal FS PHY activation.*/ + otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN; + + /* Soft core reset.*/ + otg_core_reset(usbp); + + /* Interrupts on TXFIFOs half empty.*/ + otgp->GAHBCFG = 0; + + /* Endpoints re-initialization.*/ + otg_disable_ep(usbp); + + /* Clear all pending Device Interrupts, only the USB Reset interrupt + is required initially.*/ + otgp->DIEPMSK = 0; + otgp->DOEPMSK = 0; + otgp->DAINTMSK = 0; + if (usbp->config->sof_cb == NULL) + otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM | + GINTMSK_ESUSPM |*/; + else + otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM | + GINTMSK_ESUSPM */ | GINTMSK_SOFM; + otgp->GINTSTS = 0xFFFFFFFF; /* Clears all pending IRQs, if any. */ + + /* Global interrupts enable.*/ + otgp->GAHBCFG |= GAHBCFG_GINTMSK; + } +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + + /* If in ready state then disables the USB clock.*/ + if (usbp->state != USB_STOP) { + + /* Disabling all endpoints in case the driver has been stopped while + active.*/ + otg_disable_ep(usbp); + + usbp->txpending = 0; + + otgp->DAINTMSK = 0; + otgp->GAHBCFG = 0; + otgp->GCCFG = 0; + +#if STM32_USB_USE_USB1 + if (&USBD1 == usbp) { + nvicDisableVector(STM32_OTG1_NUMBER); + rccDisableOTG1(FALSE); + } +#endif + +#if STM32_USB_USE_USB2 + if (&USBD2 == usbp) { + nvicDisableVector(STM32_OTG2_NUMBER); + rccDisableOTG2(FALSE); + } +#endif + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + unsigned i; + stm32_otg_t *otgp = usbp->otg; + + /* Flush the Tx FIFO.*/ + otg_txfifo_flush(usbp, 0); + + /* All endpoints in NAK mode, interrupts cleared.*/ + for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { + otgp->ie[i].DIEPCTL = DIEPCTL_SNAK; + otgp->oe[i].DOEPCTL = DOEPCTL_SNAK; + otgp->ie[i].DIEPINT = 0xFF; + otgp->oe[i].DOEPINT = 0xFF; + } + + /* Endpoint interrupts all disabled and cleared.*/ + otgp->DAINT = 0xFFFFFFFF; + otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); + + /* Resets the FIFO memory allocator.*/ + otg_ram_reset(usbp); + + /* Receive FIFO size initialization, the address is always zero.*/ + otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size; + otg_rxfifo_flush(usbp); + + /* Resets the device address to zero.*/ + otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); + + /* Enables also EP-related interrupt sources.*/ + otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; + otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; + otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; + + /* EP0 initialization, it is a special case.*/ + usbp->epc[0] = &ep0config; + otgp->oe[0].DOEPTSIZ = 0; + otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL | + DOEPCTL_MPSIZ(ep0config.out_maxsize); + otgp->ie[0].DIEPTSIZ = 0; + otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL | + DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize); + otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) | + DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, + ep0config.in_maxsize / 4)); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + stm32_otg_t *otgp = usbp->otg; + + otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address); +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + uint32_t ctl, fsize; + stm32_otg_t *otgp = usbp->otg; + + /* IN and OUT common parameters.*/ + switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_CTRL: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL; + break; + case USB_EP_MODE_TYPE_ISOC: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO; + break; + case USB_EP_MODE_TYPE_BULK: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR; + break; + default: + return; + } + + /* OUT endpoint activation or deactivation.*/ + otgp->oe[ep].DOEPTSIZ = 0; + if (usbp->epc[ep]->out_cb != NULL) { + otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize); + otgp->DAINTMSK |= DAINTMSK_OEPM(ep); + } + else { + otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP; + otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep); + } + + /* IN endpoint activation or deactivation.*/ + otgp->ie[ep].DIEPTSIZ = 0; + if (usbp->epc[ep]->in_cb != NULL) { + /* FIFO allocation for the IN endpoint.*/ + fsize = usbp->epc[ep]->in_maxsize / 4; + if (usbp->epc[ep]->in_multiplier > 1) + fsize *= usbp->epc[ep]->in_multiplier; + otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) | + DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize)); + otg_txfifo_flush(usbp, ep); + + otgp->ie[ep].DIEPCTL = ctl | + DIEPCTL_TXFNUM(ep) | + DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize); + otgp->DAINTMSK |= DAINTMSK_IEPM(ep); + } + else { + otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/ + otg_txfifo_flush(usbp, ep); + otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP; + otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep); + } +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + + /* Resets the FIFO memory allocator.*/ + otg_ram_reset(usbp); + + /* Disabling all endpoints.*/ + otg_disable_ep(usbp); +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + uint32_t ctl; + + (void)usbp; + + ctl = usbp->otg->oe[ep].DOEPCTL; + if (!(ctl & DOEPCTL_USBAEP)) + return EP_STATUS_DISABLED; + if (ctl & DOEPCTL_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + uint32_t ctl; + + (void)usbp; + + ctl = usbp->otg->ie[ep].DIEPCTL; + if (!(ctl & DIEPCTL_USBAEP)) + return EP_STATUS_DISABLED; + if (ctl & DIEPCTL_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + + memcpy(buf, usbp->epc[ep]->setup_buf, 8); +} + +/** + * @brief Prepares for a receive operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { + uint32_t pcnt; + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize; + usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | + DOEPTSIZ_XFRSIZ(usbp->epc[ep]->out_maxsize); + +} + +/** + * @brief Prepares for a transmit operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + if (isp->txsize == 0) { + /* Special case, sending zero size packet.*/ + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0); + } + else { + /* Normal case.*/ + uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) / + usbp->epc[ep]->in_maxsize; + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) | + DIEPTSIZ_XFRSIZ(usbp->epc[ep]->in_state->txsize); + } + +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK; +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; + usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep); +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL; +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL; +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL; +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL; +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.h b/os/hal/platforms/STM32/OTGv1/usb_lld.h new file mode 100644 index 000000000..570309750 --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/usb_lld.h @@ -0,0 +1,534 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/OTGv1/usb_lld.h + * @brief STM32 USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "stm32_otg.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__) +#define USB_MAX_ENDPOINTS 3 +#else +#define USB_MAX_ENDPOINTS 5 +#endif + +/** + * @brief The address can be changed immediately upon packet reception. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief OTG1 driver enable switch. + * @details If set to @p TRUE the support for OTG_FS is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__) +#define STM32_USB_USE_OTG1 FALSE +#endif + +/** + * @brief OTG2 driver enable switch. + * @details If set to @p TRUE the support for OTG_HS is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__) +#define STM32_USB_USE_OTG2 FALSE +#endif + +/** + * @brief OTG1 interrupt priority level setting. + */ +#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#endif + +/** + * @brief OTG2 interrupt priority level setting. + */ +#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#endif + +/** + * @brief OTG1 RX shared FIFO size. + * @note Must be a multiple of 4. + */ +#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__) +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#endif + +/** + * @brief OTG2 RX shared FIFO size. + * @note Must be a multiple of 4. + */ +#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__) +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#endif + +/** + * @brief Dedicated data pump threads priority. + */ +#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__) +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#endif + +/** + * @brief Dedicated data pump threads stack size. + */ +#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#endif + +/** + * @brief Exception priority level during TXFIFOs operations. + * @note Because an undocumented silicon behavior the operation of + * copying a packet into a TXFIFO must not be interrupted by + * any other operation on the OTG peripheral. + * This parameter represents the priority mask during copy + * operations. The default value only allows to call USB + * functions from callbacks invoked from USB ISR handlers. + * If you need to invoke USB functions from other handlers + * then raise this priority mast to the same level of the + * handler you need to use. + * @note The value zero means disabled, when disabled calling USB + * functions is only safe from thread level or from USB + * callbacks. + */ +#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__) +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1 +#error "OTG1 not present in the selected device" +#endif + +#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2 +#error "OTG2 not present in the selected device" +#endif + +#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2 +#error "USB driver activated but no USB peripheral assigned" +#endif + +#if STM32_USB_USE_OTG1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to OTG1" +#endif + +#if STM32_USB_USE_OTG2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to OTG2" +#endif + +#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0 +#error "OTG1 RX FIFO size must be a multiple of 4" +#endif + +#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0 +#error "OTG2 RX FIFO size must be a multiple of 4" +#endif + +#if defined(STM32F4XX) || defined(STM32F2XX) +#define STM32_USBCLK STM32_PLL48CLK +#elif defined(STM32F10X_CL) +#define STM32_USBCLK STM32_OTGFSCLK +#else +#error "unsupported STM32 platform for OTG functionality" +#endif + +#if STM32_USBCLK != 48000000 +#error "the USB OTG driver requires a 48MHz clock" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Peripheral-specific parameters block. + */ +typedef struct { + uint32_t rx_fifo_size; + uint32_t otg_ram_size; + uint32_t num_endpoints; +} stm32_otg_params_t; + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t txqueued; + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + union { + struct { + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; + } linear; + struct { + /** + * @brief Pointer to the output queue. + */ + OutputQueue *txqueue; + } queue; + } mode; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t rxqueued; + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + union { + struct { + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; + } linear; + struct { + /** + * @brief Pointer to the input queue. + */ + InputQueue *rxqueue; + } queue; + } mode; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Determines the space allocated for the TXFIFO as multiples of + * the packet size (@p in_maxsize). Note that zero is interpreted + * as one for simplicity and robustness. + */ + uint16_t in_multiplier; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the OTG peripheral associated to this driver. + */ + stm32_otg_t *otg; + /** + * @brief Peripheral-specific parameters. + */ + const stm32_otg_params_t *otgparams; + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; + /** + * @brief Mask of TXFIFOs to be filled by the pump thread. + */ + uint32_t txpending; + /** + * @brief Pointer to the thread. + */ + Thread *thd_ptr; + /** + * @brief Pointer to the thread when it is sleeping or @p NULL. + */ + Thread *thd_wait; + /** + * @brief Working area for the dedicated data pump thread; + */ + WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE); +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__) +extern USBDriver USBD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c new file mode 100644 index 000000000..108d94fb6 --- /dev/null +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -0,0 +1,329 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv1/rtc_lld.c + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for synchronization of RTC registers with APB1 bus. + * @details This function must be invoked before trying to read RTC registers + * in the backup domain: DIV, CNT, ALR. CR registers can always + * be read. + * + * @notapi + */ +#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);} + +/** + * @brief Wait for for previous write operation complete. + * @details This function must be invoked before writing to any RTC registers + * + * @notapi + */ +#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);} + +/** + * @brief Acquires write access to RTC registers. + * @details Before writing to the backup domain RTC registers the previous + * write operation must be completed. Use this function before + * writing to PRL, CNT, ALR registers. + * + * @notapi + */ +#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;} + +/** + * @brief Releases write access to RTC registers. + * + * @notapi + */ +#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(RTC_IRQHandler) { + uint16_t flags; + + CH_IRQ_PROLOGUE(); + + /* This wait works only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases it does nothing.*/ + rtc_lld_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTC->CRH & RTC->CRL; + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Load value of RTCCLK to prescaler registers. + * @note The pre-scaler must not be set on every reset as RTC clock + * counts are lost when it is set. + * @note This function designed to be called from + * hal_lld_backup_domain_init(). Because there is only place + * where possible to detect BKP domain reset event reliably. + * + * @notapi + */ +void rtc_lld_set_prescaler(void){ + rtc_lld_acquire(); + RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF); + rtc_lld_release(); +} + +/** + * @brief Initialize RTC. + * + * @notapi + */ +void rtc_lld_init(void){ + + /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock + stop. Otherwise its value will not be actual. */ + RTC->CRL &= ~RTC_CRL_RSF; + + /* Required because access to PRL.*/ + rtc_lld_apb1_sync(); + + /* All interrupts initially disabled.*/ + rtc_lld_wait_write(); + RTC->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { + + (void)rtcp; + + rtc_lld_acquire(); + RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16); + RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); + rtc_lld_release(); +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { + (void)rtcp; + + uint32_t time_frac; + + /* Required because access to CNT and DIV.*/ + rtc_lld_apb1_sync(); + + /* Loops until two consecutive read returning the same value.*/ + do { + timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL; + time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL; + } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL)); + + timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) / + STM32_RTCCLK); +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + + (void)rtcp; + (void)alarm; + + rtc_lld_acquire(); + if (alarmspec != NULL) { + RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); + RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); + } + else { + RTC->ALRH = 0; + RTC->ALRL = 0; + } + rtc_lld_release(); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + + (void)rtcp; + (void)alarm; + + /* Required because access to ALR.*/ + rtc_lld_apb1_sync(); + + alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + + rtc_lld_wait_write(); + RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; + } + else { + rtc_lld_wait_write(); + RTC->CRH = 0; + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } +} + +#include "chrtclib.h" + +/** + * @brief Get current time in format suitable for usage in FatFS. + * + * @param[in] rtcp pointer to RTC driver structure + * @return FAT time value. + * + * @api + */ +uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) { + uint32_t fattime; + struct tm timp; + + rtcGetTimeTm(rtcp, &timp); + + fattime = (timp.tm_sec) >> 1; + fattime |= (timp.tm_min) << 5; + fattime |= (timp.tm_hour) << 11; + fattime |= (timp.tm_mday) << 16; + fattime |= (timp.tm_mon + 1) << 21; + fattime |= (timp.tm_year - 80) << 25; + + return fattime; +} +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h new file mode 100644 index 000000000..62b74cc46 --- /dev/null +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -0,0 +1,187 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv1/rtc_lld.h + * @brief STM32F1xx RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !STM32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if STM32_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of a structure representing an RTC callbacks config. + */ +typedef struct RTCCallbackConfig RTCCallbackConfig; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC callbacks config. + */ +struct RTCCallbackConfig{ + /** + * @brief Generic RTC callback pointer. + */ + rtccb_t callback; +}; + +/** + * @brief Structure representing an RTC time stamp. + */ +struct RTCTime { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; + /** + * @brief Fractional part. + */ + uint32_t tv_msec; +}; + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ + /** + * @brief Callback pointer. + */ + rtccb_t callback; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_set_prescaler(void); + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/os/hal/platforms/STM32/RTCv2/rtc_lld.c new file mode 100644 index 000000000..17ae46ccf --- /dev/null +++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.c @@ -0,0 +1,322 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv2/rtc_lld.c + * @brief STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +/** + * @brief Wait for synchronization of RTC registers with APB1 bus. + * @details This function must be invoked before trying to read RTC registers. + * + * @notapi + */ +#define rtc_lld_apb1_sync() {while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0);} + +/** + * @brief Beginning of configuration procedure. + * + * @notapi + */ +#define rtc_lld_enter_init() { \ + RTCD1.id_rtc->ISR |= RTC_ISR_INIT; \ + while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0) \ + ; \ +} + +/** + * @brief Finalizing of configuration procedure. + * + * @notapi + */ +#define rtc_lld_exit_init() {RTCD1.id_rtc->ISR &= ~RTC_ISR_INIT;} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers. + * + * @api + */ +void rtc_lld_init(void){ + RTCD1.id_rtc = RTC; + + /* Asynchronous part of preloader. Set it to maximum value. */ + uint32_t prediv_a = 0x7F; + + /* Disable write protection. */ + RTCD1.id_rtc->WPR = 0xCA; + RTCD1.id_rtc->WPR = 0x53; + + /* If calendar not init yet. */ + if (!(RTC->ISR & RTC_ISR_INITS)){ + rtc_lld_enter_init(); + + /* Prescaler register must be written in two SEPARATE writes. */ + prediv_a = (prediv_a << 16) | + (((STM32_RTCCLK / (prediv_a + 1)) - 1) & 0x7FFF); + RTCD1.id_rtc->PRER = prediv_a; + RTCD1.id_rtc->PRER = prediv_a; + rtc_lld_exit_init(); + } +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to set it on STM32 platform. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { + (void)rtcp; + + rtc_lld_enter_init(); + if (timespec->h12) + RTCD1.id_rtc->CR |= RTC_CR_FMT; + else + RTCD1.id_rtc->CR &= ~RTC_CR_FMT; + RTCD1.id_rtc->TR = timespec->tv_time; + RTCD1.id_rtc->DR = timespec->tv_date; + rtc_lld_exit_init(); +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { + (void)rtcp; + + rtc_lld_apb1_sync(); + +#if STM32_RTC_HAS_SUBSECONDS + timespec->tv_msec = + (1000 * ((RTCD1.id_rtc->PRER & 0x7FFF) - RTCD1.id_rtc->SSR)) / + ((RTCD1.id_rtc->PRER & 0x7FFF) + 1); +#endif /* STM32_RTC_HAS_SUBSECONDS */ + timespec->tv_time = RTCD1.id_rtc->TR; + timespec->tv_date = RTCD1.id_rtc->DR; +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset for both comparators is 0. + * @note Function does not performs any checks of alarm time validity. + * + * @param[in] rtcp Pointer to RTC driver structure. + * @param[in] alarm Alarm identifier. Can be 1 or 2. + * @param[in] alarmspec Pointer to a @p RTCAlarm structure. + * + * @api + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + if (alarm == 1){ + if (alarmspec != NULL){ + rtcp->id_rtc->CR &= ~RTC_CR_ALRAE; + while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRAWF)) + ; + rtcp->id_rtc->ALRMAR = alarmspec->tv_datetime; + rtcp->id_rtc->CR |= RTC_CR_ALRAE; + rtcp->id_rtc->CR |= RTC_CR_ALRAIE; + } + else { + rtcp->id_rtc->CR &= ~RTC_CR_ALRAIE; + rtcp->id_rtc->CR &= ~RTC_CR_ALRAE; + } + } + else{ + if (alarmspec != NULL){ + rtcp->id_rtc->CR &= ~RTC_CR_ALRBE; + while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRBWF)) + ; + rtcp->id_rtc->ALRMBR = alarmspec->tv_datetime; + rtcp->id_rtc->CR |= RTC_CR_ALRBE; + rtcp->id_rtc->CR |= RTC_CR_ALRBIE; + } + else { + rtcp->id_rtc->CR &= ~RTC_CR_ALRBIE; + rtcp->id_rtc->CR &= ~RTC_CR_ALRBE; + } + } +} + +/** + * @brief Get alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @api + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + if (alarm == 1) + alarmspec->tv_datetime = rtcp->id_rtc->ALRMAR; + else + alarmspec->tv_datetime = rtcp->id_rtc->ALRMBR; +} + +/** + * @brief Sets time of periodic wakeup. + * + * @note Default value after BKP domain reset is 0x0000FFFF + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] wakeupspec pointer to a @p RTCWakeup structure + * + * @api + */ +void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){ + chDbgCheck((wakeupspec->wakeup != 0x30000), + "rtc_lld_set_periodic_wakeup, forbidden combination"); + + if (wakeupspec != NULL){ + rtcp->id_rtc->CR &= ~RTC_CR_WUTE; + while(!(rtcp->id_rtc->ISR & RTC_ISR_WUTWF)) + ; + rtcp->id_rtc->WUTR = wakeupspec->wakeup & 0xFFFF; + rtcp->id_rtc->CR = (wakeupspec->wakeup >> 16) & 0x7; + rtcp->id_rtc->CR |= RTC_CR_WUTIE; + rtcp->id_rtc->CR |= RTC_CR_WUTE; + } + else { + rtcp->id_rtc->CR &= ~RTC_CR_WUTIE; + rtcp->id_rtc->CR &= ~RTC_CR_WUTE; + } +} + +/** + * @brief Gets time of periodic wakeup. + * + * @note Default value after BKP domain reset is 0x0000FFFF + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] wakeupspec pointer to a @p RTCWakeup structure + * + * @api + */ +void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){ + wakeupspec->wakeup = 0; + wakeupspec->wakeup |= rtcp->id_rtc->WUTR; + wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16; +} + +/** + * @brief Get current time in format suitable for usage in FatFS. + * + * @param[in] rtcp pointer to RTC driver structure + * @return FAT time value. + * + * @api + */ +uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) { + uint32_t fattime; + RTCTime timespec; + uint32_t tv_time; + uint32_t tv_date; + uint32_t v; + + chSysLock(); + rtcGetTimeI(rtcp, ×pec); + chSysUnlock(); + + tv_time = timespec.tv_time; + tv_date = timespec.tv_date; + + v = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET; + v += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10; + fattime = v >> 1; + + v = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET; + v += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10; + fattime |= v << 5; + + v = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET; + v += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10; + v += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET); + fattime |= v << 11; + + v = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET; + v += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10; + fattime |= v << 16; + + v = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET; + v += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10; + fattime |= v << 21; + + v = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET; + v += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10; + v += 2000 - 1900 - 80; + fattime |= v << 25; + + return fattime; +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/os/hal/platforms/STM32/RTCv2/rtc_lld.h new file mode 100644 index 000000000..8e0ce8dd0 --- /dev/null +++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv2/rtc_lld.h + * @brief STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Two alarm comparators available on STM32F4x. + */ +#define RTC_ALARMS 2 + +/** + * @brief Data offsets in RTC date and time registers. + */ +#define RTC_TR_PM_OFFSET 22 +#define RTC_TR_HT_OFFSET 20 +#define RTC_TR_HU_OFFSET 16 +#define RTC_TR_MNT_OFFSET 12 +#define RTC_TR_MNU_OFFSET 8 +#define RTC_TR_ST_OFFSET 4 +#define RTC_TR_SU_OFFSET 0 + +#define RTC_DR_YT_OFFSET 20 +#define RTC_DR_YU_OFFSET 16 +#define RTC_DR_WDU_OFFSET 13 +#define RTC_DR_MT_OFFSET 12 +#define RTC_DR_MU_OFFSET 8 +#define RTC_DR_DT_OFFSET 4 +#define RTC_DR_DU_OFFSET 0 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !STM32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) && \ + !(STM32_RTCSEL == STM32_RTCSEL_LSI) && \ + !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV) +#error "invalid source selected for RTC clock" +#endif + +#if !defined(RTC_USE_INTERRUPTS) || defined(__DOXYGEN__) +#define RTC_USE_INTERRUPTS FALSE +#endif + +#if STM32_PCLK1 < (STM32_RTCCLK * 7) +#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of a structure representing an RTC wakeup period. + */ +typedef struct RTCWakeup RTCWakeup; + +/** + * @brief Type of a structure representing an RTC callbacks config. + */ +typedef struct RTCCallbackConfig RTCCallbackConfig; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Structure representing an RTC time stamp. + */ +struct RTCTime { + /** + * @brief RTC date register in STM32 BCD format. + */ + uint32_t tv_date; + /** + * @brief RTC time register in STM32 BCD format. + */ + uint32_t tv_time; + /** + * @brief Set this to TRUE to use 12 hour notation. + */ + bool_t h12; + /** + * @brief Fractional part of time. + */ +#if STM32_RTC_HAS_SUBSECONDS + uint32_t tv_msec; +#endif +}; + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Date and time of alarm in STM32 BCD. + */ + uint32_t tv_datetime; +}; + +/** + * @brief Structure representing an RTC periodic wakeup period. + */ +struct RTCWakeup { + /** + * @brief RTC WUTR register. + * @details Bits [15:0] contain value of WUTR register + * Bits [18:16] contain value of WUCKSEL bits in CR register + * + * @note ((WUTR == 0) || (WUCKSEL == 3)) is forbidden combination. + */ + uint32_t wakeup; +}; + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ + /** + * @brief Pointer to the RTC registers block. + */ + RTC_TypeDef *id_rtc; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); + void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec); + void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec); + uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/SPIv1/spi_lld.c b/os/hal/platforms/STM32/SPIv1/spi_lld.c new file mode 100644 index 000000000..dad91c6a8 --- /dev/null +++ b/os/hal/platforms/STM32/SPIv1/spi_lld.c @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/SPIv1/spi_lld.c + * @brief STM32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SPI1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ + STM32_SPI1_RX_DMA_CHN) + +#define SPI1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ + STM32_SPI1_TX_DMA_CHN) + +#define SPI2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ + STM32_SPI2_RX_DMA_CHN) + +#define SPI2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ + STM32_SPI2_TX_DMA_CHN) + +#define SPI3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ + STM32_SPI3_RX_DMA_CHN) + +#define SPI3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ + STM32_SPI3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** @brief SPI3 driver identifier.*/ +#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + + /* Stop everything.*/ + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + (void)spip; + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)spip; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + + dummytx = 0xFFFF; + +#if STM32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); + SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); + SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); + SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); + SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); + SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); + SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + rccEnableSPI1(FALSE); + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); + rccEnableSPI2(FALSE); + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); + rccEnableSPI3(FALSE); + } +#endif + + /* DMA setup.*/ + dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); + dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); + } + + /* Configuration-specific DMA setup.*/ + if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { + /* Frame width is 8 bits or smaller.*/ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + } + else { + /* Frame width is larger than 8 bits.*/ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } + /* SPI setup and enable.*/ + spip->spi->CR1 = 0; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | + SPI_CR1_SSI; + spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; + spip->spi->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* SPI disable.*/ + spip->spi->CR1 = 0; + spip->spi->CR2 = 0; + dmaStreamRelease(spip->dmarx); + dmaStreamRelease(spip->dmatx); + +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) + rccDisableSPI1(FALSE); +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) + rccDisableSPI2(FALSE); +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) + rccDisableSPI3(FALSE); +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->DR = frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return spip->spi->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM32/SPIv1/spi_lld.h b/os/hal/platforms/STM32/SPIv1/spi_lld.h new file mode 100644 index 000000000..fe37c8f66 --- /dev/null +++ b/os/hal/platforms/STM32/SPIv1/spi_lld.h @@ -0,0 +1,411 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/SPIv1/spi_lld.h + * @brief STM32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 FALSE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 FALSE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI3 FALSE +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI DMA error hook. + */ +#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for SPI1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#endif + +/** + * @brief DMA stream used for SPI1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#endif + +/** + * @brief DMA stream used for SPI2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for SPI2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for SPI3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for SPI3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI1" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI2" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI3" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI1" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI2" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI3" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 RX" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 TX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 RX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 TX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 RX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint16_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver{ + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Receive DMA stream. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA stream. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.c b/os/hal/platforms/STM32/SPIv2/spi_lld.c new file mode 100644 index 000000000..752c2af66 --- /dev/null +++ b/os/hal/platforms/STM32/SPIv2/spi_lld.c @@ -0,0 +1,502 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/SPIv2/spi_lld.c + * @brief STM32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SPI1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ + STM32_SPI1_RX_DMA_CHN) + +#define SPI1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ + STM32_SPI1_TX_DMA_CHN) + +#define SPI2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ + STM32_SPI2_RX_DMA_CHN) + +#define SPI2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ + STM32_SPI2_TX_DMA_CHN) + +#define SPI3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ + STM32_SPI3_RX_DMA_CHN) + +#define SPI3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ + STM32_SPI3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** @brief SPI3 driver identifier.*/ +#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + + /* Stop everything.*/ + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + (void)spip; + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)spip; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + + dummytx = 0xFFFF; + +#if STM32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); + SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); + SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); + SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); + SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); + SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); + SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + uint32_t ds; + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + rccEnableSPI1(FALSE); + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); + rccEnableSPI2(FALSE); + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); + rccEnableSPI3(FALSE); + } +#endif + + /* DMA setup.*/ + dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); + dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); + } + + /* Configuration-specific DMA setup.*/ + ds = spip->config->cr2 & SPI_CR2_DS; + if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) { + /* Frame width is 8 bits or smaller.*/ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + } + else { + /* Frame width is larger than 8 bits.*/ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } + /* SPI setup and enable.*/ + spip->spi->CR1 = 0; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | + SPI_CR1_SSI; + spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE | + SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; + spip->spi->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* SPI disable.*/ + spip->spi->CR1 = 0; + spip->spi->CR2 = 0; + dmaStreamRelease(spip->dmarx); + dmaStreamRelease(spip->dmatx); + +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) + rccDisableSPI1(FALSE); +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) + rccDisableSPI2(FALSE); +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) + rccDisableSPI3(FALSE); +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + /* + * Data register must be accessed with the appropriate data size. + * Byte size access (uint8_t *) for transactions that are <= 8-bit. + * Halfword size access (uint16_t) for transactions that are <= 8-bit. + */ + if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 | + SPI_CR2_DS_1 | + SPI_CR2_DS_0)) { + volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR; + *spidr = (uint8_t)frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return (uint16_t)*spidr; + } + else { + spip->spi->DR = frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return spip->spi->DR; + } +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.h b/os/hal/platforms/STM32/SPIv2/spi_lld.h new file mode 100644 index 000000000..f4cc67da5 --- /dev/null +++ b/os/hal/platforms/STM32/SPIv2/spi_lld.h @@ -0,0 +1,424 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/SPIv2/spi_lld.h + * @brief STM32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 FALSE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 FALSE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI3 FALSE +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI DMA error hook. + */ +#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for SPI1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#endif + +/** + * @brief DMA stream used for SPI1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#endif + +/** + * @brief DMA stream used for SPI2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for SPI2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for SPI3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for SPI3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +#if defined(STM32F0XX) +/* Fixed values for STM32F0xx devices.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif /* defined(STM32F0XX) */ + +#if defined(STM32F30X) || defined(STM32F37X) +/* Fixed values for STM32F3xx devices.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif /* defined(STM32F30X) */ + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI1" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI2" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI3" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI1" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI2" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI3" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 RX" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 TX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 RX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 TX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 RX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI CR1 register initialization data. + */ + uint16_t cr1; + /** + * @brief SPI CR2 register initialization data. + */ + uint16_t cr2; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver{ + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Receive DMA stream. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA stream. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.c b/os/hal/platforms/STM32/USARTv1/serial_lld.c new file mode 100644 index 000000000..a8333bf77 --- /dev/null +++ b/os/hal/platforms/STM32/USARTv1/serial_lld.c @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv1/serial_lld.c + * @brief STM32 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** @brief USART2 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** @brief USART3 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** @brief UART4 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/** @brief UART5 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +SerialDriver SD5; +#endif + +/** @brief USART6 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +SerialDriver SD6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = +{ + SERIAL_DEFAULT_BITRATE, + 0, + USART_CR2_STOP1_BITS | USART_CR2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + USART_TypeDef *u = sdp->usart; + + /* Baud rate setting.*/ +#if STM32_HAS_USART6 + if ((sdp->usart == USART1) || (sdp->usart == USART6)) +#else + if (sdp->usart == USART1) +#endif + u->BRR = STM32_PCLK2 / config->speed; + else + u->BRR = STM32_PCLK1 / config->speed; + + /* Note that some bits are enforced.*/ + u->CR2 = config->cr2 | USART_CR2_LBDIE; + u->CR3 = config->cr3 | USART_CR3_EIE; + u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | + USART_CR1_RXNEIE | USART_CR1_TE | + USART_CR1_RE; + u->SR = 0; + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(USART_TypeDef *u) { + + u->CR1 = 0; + u->CR2 = 0; + u->CR3 = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr USART SR register value + */ +static void set_error(SerialDriver *sdp, uint16_t sr) { + flagsmask_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= SD_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= SD_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= SD_NOISE_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +static void serve_interrupt(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + uint16_t cr1 = u->CR1; + uint16_t sr = u->SR; /* SR reset step 1.*/ + uint16_t dr = u->DR; /* SR reset step 2.*/ + + /* Error condition detection.*/ + if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) + set_error(sdp, sr); + /* Special case, LIN break detection.*/ + if (sr & USART_SR_LBD) { + chSysLockFromIsr(); + chnAddFlagsI(sdp, SD_BREAK_DETECTED); + chSysUnlockFromIsr(); + u->SR &= ~USART_SR_LBD; + } + /* Data available.*/ + if (sr & USART_SR_RXNE) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, (uint8_t)dr); + chSysUnlockFromIsr(); + } + /* Transmission buffer empty.*/ + if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) { + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; + } + else + u->DR = b; + chSysUnlockFromIsr(); + } + /* Physical transmission end.*/ + if (sr & USART_SR_TC) { + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_TRANSMISSION_END); + chSysUnlockFromIsr(); + u->CR1 = cr1 & ~USART_CR1_TCIE; + u->SR &= ~USART_SR_TC; + } +} + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + USART1->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + USART2->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + USART3->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify4(GenericQueue *qp) { + + (void)qp; + UART4->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +static void notify5(GenericQueue *qp) { + + (void)qp; + UART5->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +static void notify6(GenericQueue *qp) { + + (void)qp; + USART6->CR1 |= USART_CR1_TXEIE; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +#if !defined(STM32_USART1_HANDLER) +#error "STM32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +#if !defined(STM32_USART2_HANDLER) +#error "STM32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +#if !defined(STM32_USART3_HANDLER) +#error "STM32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +#if !defined(STM32_UART4_HANDLER) +#error "STM32_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_UART4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +#if !defined(STM32_UART5_HANDLER) +#error "STM32_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_UART5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD5); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +#if !defined(STM32_USART6_HANDLER) +#error "STM32_USART6_HANDLER not defined" +#endif +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM32_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = USART1; +#endif + +#if STM32_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = USART2; +#endif + +#if STM32_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = USART3; +#endif + +#if STM32_SERIAL_USE_UART4 + sdObjectInit(&SD4, NULL, notify4); + SD4.usart = UART4; +#endif + +#if STM32_SERIAL_USE_UART5 + sdObjectInit(&SD5, NULL, notify5); + SD5.usart = UART5; +#endif + +#if STM32_SERIAL_USE_USART6 + sdObjectInit(&SD6, NULL, notify6); + SD6.usart = USART6; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccEnableUSART1(FALSE); + nvicEnableVector(STM32_USART1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccEnableUSART2(FALSE); + nvicEnableVector(STM32_USART2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccEnableUSART3(FALSE); + nvicEnableVector(STM32_USART3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccEnableUART4(FALSE); + nvicEnableVector(STM32_UART4_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccEnableUART5(FALSE); + nvicEnableVector(STM32_UART5_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccEnableUSART6(FALSE); + nvicEnableVector(STM32_USART6_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); + } +#endif + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccDisableUSART1(FALSE); + nvicDisableVector(STM32_USART1_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccDisableUSART2(FALSE); + nvicDisableVector(STM32_USART2_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccDisableUSART3(FALSE); + nvicDisableVector(STM32_USART3_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccDisableUART4(FALSE); + nvicDisableVector(STM32_UART4_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccDisableUART5(FALSE); + nvicDisableVector(STM32_UART5_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccDisableUSART6(FALSE); + nvicDisableVector(STM32_USART6_NUMBER); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.h b/os/hal/platforms/STM32/USARTv1/serial_lld.h new file mode 100644 index 000000000..7242537d7 --- /dev/null +++ b/os/hal/platforms/STM32/USARTv1/serial_lld.h @@ -0,0 +1,303 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv1/serial_lld.h + * @brief STM32 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART1 FALSE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART2 FALSE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief USART6 driver enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART6 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART1_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART2_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART3_PRIORITY 12 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART4_PRIORITY 12 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART5_PRIORITY 12 +#endif + +/** + * @brief USART6 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART6_PRIORITY 12 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + +#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ + !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ + !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 +#error "SERIAL driver activated but no USART/UART peripheral assigned" +#endif + +#if STM32_SERIAL_USE_USART1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if STM32_SERIAL_USE_USART2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if STM32_SERIAL_USE_USART3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if STM32_SERIAL_USE_UART4 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if STM32_SERIAL_USE_UART5 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if STM32_SERIAL_USE_USART6 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY) +#error "Invalid IRQ priority assigned to USART6" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields.*/ + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t cr3; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + USART_TypeDef *usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * Extra USARTs definitions here (missing from the ST header file). + */ +#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ +#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ +#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ +#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif +#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif +#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv1/uart_lld.c b/os/hal/platforms/STM32/USARTv1/uart_lld.c new file mode 100644 index 000000000..c1e624918 --- /dev/null +++ b/os/hal/platforms/STM32/USARTv1/uart_lld.c @@ -0,0 +1,663 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv1/uart_lld.c + * @brief STM32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define USART1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_CHN) + +#define USART1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_CHN) + +#define USART2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_CHN) + +#define USART2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_CHN) + +#define USART3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_CHN) + +#define USART3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_CHN) + +#define USART6_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \ + STM32_USART6_RX_DMA_CHN) + +#define USART6_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \ + STM32_USART6_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + + +/** @brief USART6 UART driver identifier.*/ +#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) +UARTDriver UARTD6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr USART SR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint16_t sr) { + uartflags_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= UART_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= UART_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= UART_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= UART_NOISE_ERROR; + if (sr & USART_SR_LBD) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void set_rx_idle_loop(UARTDriver *uartp) { + uint32_t mode; + + /* RX DMA channel preparation, if the char callback is defined then the + TCIE interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; + else + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; + dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, 1); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamDisable(uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CR1 = 0; + uartp->usart->CR2 = 0; + uartp->usart->CR3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint16_t cr1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ +#if STM32_HAS_USART6 + if ((uartp->usart == USART1) || (uartp->usart == USART6)) +#else + if (uartp->usart == USART1) +#endif + u->BRR = STM32_PCLK2 / uartp->config->speed; + else + u->BRR = STM32_PCLK1 / uartp->config->speed; + + /* Resetting eventual pending status flags.*/ + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + u->SR = 0; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; + u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | + USART_CR3_EIE; + if (uartp->config->txend2_cb == NULL) + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; + else + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | + USART_CR1_TCIE; + u->CR1 = uartp->config->cr1 | cr1; + + /* Starting the receiver idle loop.*/ + set_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) + uartp->config->rxchar_cb(uartp, uartp->rxbuf); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaStreamDisable(uartp->dmarx); + uartp->rxstate = UART_RX_COMPLETE; + if (uartp->config->rxend_cb != NULL) + uartp->config->rxend_cb(uartp); + + /* If the callback didn't explicitly change state then the receiver + automatically returns to the idle state.*/ + if (uartp->rxstate == UART_RX_COMPLETE) { + uartp->rxstate = UART_RX_IDLE; + set_rx_idle_loop(uartp); + } + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(uartp->dmatx); + + /* A callback is generated, if enabled, after a completed transfer.*/ + uartp->txstate = UART_TX_COMPLETE; + if (uartp->config->txend1_cb != NULL) + uartp->config->txend1_cb(uartp); + + /* If the callback didn't explicitly change state then the transmitter + automatically returns to the idle state.*/ + if (uartp->txstate == UART_TX_COMPLETE) + uartp->txstate = UART_TX_IDLE; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_usart_irq(UARTDriver *uartp) { + uint16_t sr; + USART_TypeDef *u = uartp->usart; + + sr = u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | + USART_SR_FE | USART_SR_PE)) { + u->SR = ~USART_SR_LBD; + if (uartp->config->rxerr_cb != NULL) + uartp->config->rxerr_cb(uartp, translate_errors(sr)); + } + if (sr & USART_SR_TC) { + u->SR = ~USART_SR_TC; + + /* End of transmission, a callback is generated.*/ + if (uartp->config->txend2_cb != NULL) + uartp->config->txend2_cb(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +#if !defined(STM32_USART1_HANDLER) +#error "STM32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART1 */ + +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +#if !defined(STM32_USART2_HANDLER) +#error "STM32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART2 */ + +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +#if !defined(STM32_USART3_HANDLER) +#error "STM32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART3 */ + +#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) +#if !defined(STM32_USART6_HANDLER) +#error "STM32_USART6_HANDLER not defined" +#endif +/** + * @brief USART6 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART6 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if STM32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); + UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); + UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); + UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART6 + uartObjectInit(&UARTD6); + UARTD6.usart = USART6; + UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM); + UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM); +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); + rccEnableUSART1(FALSE); + nvicEnableVector(STM32_USART1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableUSART2(FALSE); + nvicEnableVector(STM32_USART2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); + rccEnableUSART3(FALSE); + nvicEnableVector(STM32_USART3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART6 + if (&UARTD6 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART6_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART6_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); + rccEnableUSART6(FALSE); + nvicEnableVector(STM32_USART6_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) + uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); + dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + dmaStreamRelease(uartp->dmarx); + dmaStreamRelease(uartp->dmatx); + +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + nvicDisableVector(STM32_USART1_NUMBER); + rccDisableUSART1(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + nvicDisableVector(STM32_USART2_NUMBER); + rccDisableUSART2(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + nvicDisableVector(STM32_USART3_NUMBER); + rccDisableUSART3(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART6 + if (&UARTD6 == uartp) { + nvicDisableVector(STM32_USART6_NUMBER); + rccDisableUSART6(FALSE); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmatx, txbuf); + dmaStreamSetTransactionSize(uartp->dmatx, n); + dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaStreamDisable(uartp->dmatx); + return dmaStreamGetTransactionSize(uartp->dmatx); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaStreamDisable(uartp->dmarx); + + /* RX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmarx, rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, n); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaStreamDisable(uartp->dmarx); + n = dmaStreamGetTransactionSize(uartp->dmarx); + set_rx_idle_loop(uartp); + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv1/uart_lld.h b/os/hal/platforms/STM32/USARTv1/uart_lld.h new file mode 100644 index 000000000..ffaed007e --- /dev/null +++ b/os/hal/platforms/STM32/USARTv1/uart_lld.h @@ -0,0 +1,521 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv1/uart_lld.h + * @brief STM32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART1 FALSE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART2 FALSE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART3 FALSE +#endif + +/** + * @brief UART driver on USART6 enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART6 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART6 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_DMA_PRIORITY 0 +#endif + +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief USART6 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART6_DMA_PRIORITY 0 +#endif + +/** + * @brief USART1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for USART1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#endif + +/** + * @brief DMA stream used for USART1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#endif + +/** + * @brief DMA stream used for USART2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +/** + * @brief DMA stream used for USART2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for USART3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#endif + +/** + * @brief DMA stream used for USART3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for USART6 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART6_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif + +/** + * @brief DMA stream used for USART6 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART6_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if STM32_UART_USE_USART6 && !STM32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + +#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ + !STM32_UART_USE_USART3 && !STM32_UART_USE_USART6 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if STM32_UART_USE_USART1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if STM32_UART_USE_USART2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if STM32_UART_USE_USART3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if STM32_UART_USE_USART6 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART6" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART1" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART2" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART3" +#endif + +#if STM32_UART_USE_USART6 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART6" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_MSK) +#error "invalid DMA stream associated to USART1 RX" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_MSK) +#error "invalid DMA stream associated to USART1 TX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_MSK) +#error "invalid DMA stream associated to USART2 RX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_MSK) +#error "invalid DMA stream associated to USART2 TX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_MSK) +#error "invalid DMA stream associated to USART3 RX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_MSK) +#error "invalid DMA stream associated to USART3 TX" +#endif + +#if STM32_UART_USE_USART6 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \ + STM32_USART6_RX_DMA_MSK) +#error "invalid DMA stream associated to USART6 RX" +#endif + +#if STM32_UART_USE_USART6 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \ + STM32_USART6_TX_DMA_MSK) +#error "invalid DMA stream associated to USART6 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t cr3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__) +extern UARTDriver UARTD6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.c b/os/hal/platforms/STM32/USARTv2/serial_lld.c new file mode 100644 index 000000000..5209c499b --- /dev/null +++ b/os/hal/platforms/STM32/USARTv2/serial_lld.c @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv2/serial_lld.c + * @brief STM32 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** @brief USART2 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** @brief USART3 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** @brief UART4 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/** @brief UART5 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +SerialDriver SD5; +#endif + +/** @brief USART6 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +SerialDriver SD6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = +{ + SERIAL_DEFAULT_BITRATE, + 0, + USART_CR2_STOP1_BITS | USART_CR2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + USART_TypeDef *u = sdp->usart; + + /* Baud rate setting.*/ + u->BRR = (uint16_t)(sdp->clock / config->speed); + + /* Note that some bits are enforced.*/ + u->CR2 = config->cr2 | USART_CR2_LBDIE; + u->CR3 = config->cr3 | USART_CR3_EIE; + u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | + USART_CR1_RXNEIE | USART_CR1_TE | + USART_CR1_RE; + u->ICR = 0xFFFFFFFF; +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(USART_TypeDef *u) { + + u->CR1 = 0; + u->CR2 = 0; + u->CR3 = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] isr USART ISR register value + */ +static void set_error(SerialDriver *sdp, uint32_t isr) { + flagsmask_t sts = 0; + + if (isr & USART_ISR_ORE) + sts |= SD_OVERRUN_ERROR; + if (isr & USART_ISR_PE) + sts |= SD_PARITY_ERROR; + if (isr & USART_ISR_FE) + sts |= SD_FRAMING_ERROR; + if (isr & USART_ISR_NE) + sts |= SD_NOISE_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +static void serve_interrupt(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + uint32_t cr1 = u->CR1; + uint32_t isr; + + /* Reading and clearing status.*/ + isr = u->ISR; + u->ICR = isr; + + /* Error condition detection.*/ + if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE)) + set_error(sdp, isr); + /* Special case, LIN break detection.*/ + if (isr & USART_ISR_LBD) { + chSysLockFromIsr(); + chnAddFlagsI(sdp, SD_BREAK_DETECTED); + chSysUnlockFromIsr(); + } + /* Data available.*/ + if (isr & USART_ISR_RXNE) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, (uint8_t)u->RDR); + chSysUnlockFromIsr(); + } + /* Transmission buffer empty.*/ + if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) { + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; + } + else + u->TDR = b; + chSysUnlockFromIsr(); + } + /* Physical transmission end.*/ + if (isr & USART_ISR_TC) { + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_TRANSMISSION_END); + chSysUnlockFromIsr(); + u->CR1 = cr1 & ~USART_CR1_TCIE; + } +} + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + USART1->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + USART2->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + USART3->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify4(GenericQueue *qp) { + + (void)qp; + UART4->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +static void notify5(GenericQueue *qp) { + + (void)qp; + UART5->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +static void notify6(GenericQueue *qp) { + + (void)qp; + USART6->CR1 |= USART_CR1_TXEIE; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +#if !defined(STM32_USART1_HANDLER) +#error "STM32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +#if !defined(STM32_USART2_HANDLER) +#error "STM32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +#if !defined(STM32_USART3_HANDLER) +#error "STM32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +#if !defined(STM32_UART4_HANDLER) +#error "STM32_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_UART4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +#if !defined(STM32_UART5_HANDLER) +#error "STM32_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_UART5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD5); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +#if !defined(STM32_USART6_HANDLER) +#error "STM32_USART6_HANDLER not defined" +#endif +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM32_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = USART1; + SD1.clock = STM32_USART1CLK; +#endif + +#if STM32_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = USART2; + SD2.clock = STM32_USART2CLK; +#endif + +#if STM32_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = USART3; + SD3.clock = STM32_USART3CLK; +#endif + +#if STM32_SERIAL_USE_UART4 + sdObjectInit(&SD4, NULL, notify4); + SD4.usart = UART4; + SD4.clock = STM32_UART4CLK; +#endif + +#if STM32_SERIAL_USE_UART5 + sdObjectInit(&SD5, NULL, notify5); + SD5.usart = UART5; + SD5.clock = STM32_UART5CLK; +#endif + +#if STM32_SERIAL_USE_USART6 + sdObjectInit(&SD6, NULL, notify6); + SD6.usart = USART6; + SD6.clock = STM32_USART6CLK; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccEnableUSART1(FALSE); + nvicEnableVector(STM32_USART1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccEnableUSART2(FALSE); + nvicEnableVector(STM32_USART2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccEnableUSART3(FALSE); + nvicEnableVector(STM32_USART3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccEnableUART4(FALSE); + nvicEnableVector(STM32_UART4_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccEnableUART5(FALSE); + nvicEnableVector(STM32_UART5_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccEnableUSART6(FALSE); + nvicEnableVector(STM32_USART6_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); + } +#endif + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccDisableUSART1(FALSE); + nvicDisableVector(STM32_USART1_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccDisableUSART2(FALSE); + nvicDisableVector(STM32_USART2_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccDisableUSART3(FALSE); + nvicDisableVector(STM32_USART3_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccDisableUART4(FALSE); + nvicDisableVector(STM32_UART4_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccDisableUART5(FALSE); + nvicDisableVector(STM32_UART5_NUMBER); + return; + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccDisableUSART6(FALSE); + nvicDisableVector(STM32_USART6_NUMBER); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.h b/os/hal/platforms/STM32/USARTv2/serial_lld.h new file mode 100644 index 000000000..743cb0b50 --- /dev/null +++ b/os/hal/platforms/STM32/USARTv2/serial_lld.h @@ -0,0 +1,305 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv2/serial_lld.h + * @brief STM32 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART1 FALSE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART2 FALSE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief USART6 driver enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART6 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART1_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART2_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART3_PRIORITY 12 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART4_PRIORITY 12 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART5_PRIORITY 12 +#endif + +/** + * @brief USART6 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART6_PRIORITY 12 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + +#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ + !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ + !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 +#error "SERIAL driver activated but no USART/UART peripheral assigned" +#endif + +#if STM32_SERIAL_USE_USART1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if STM32_SERIAL_USE_USART2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if STM32_SERIAL_USE_USART3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if STM32_SERIAL_USE_UART4 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if STM32_SERIAL_USE_UART5 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if STM32_SERIAL_USE_USART6 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY) +#error "Invalid IRQ priority assigned to USART6" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields.*/ + /** + * @brief Initialization value for the CR1 register. + */ + uint32_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint32_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint32_t cr3; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + USART_TypeDef *usart; \ + /* Clock frequency for the associated USART/UART.*/ \ + uint32_t clock; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * Extra USARTs definitions here (missing from the ST header file). + */ +#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ +#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ +#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ +#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif +#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif +#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv2/uart_lld.c b/os/hal/platforms/STM32/USARTv2/uart_lld.c new file mode 100644 index 000000000..740c2fd98 --- /dev/null +++ b/os/hal/platforms/STM32/USARTv2/uart_lld.c @@ -0,0 +1,594 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv2/uart_lld.c + * @brief STM32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define USART1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_CHN) + +#define USART1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_CHN) + +#define USART2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_CHN) + +#define USART2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_CHN) + +#define USART3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_CHN) + +#define USART3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr USART SR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t isr) { + uartflags_t sts = 0; + + if (isr & USART_ISR_ORE) + sts |= UART_OVERRUN_ERROR; + if (isr & USART_ISR_PE) + sts |= UART_PARITY_ERROR; + if (isr & USART_ISR_FE) + sts |= UART_FRAMING_ERROR; + if (isr & USART_ISR_NE) + sts |= UART_NOISE_ERROR; + if (isr & USART_ISR_LBD) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void set_rx_idle_loop(UARTDriver *uartp) { + uint32_t mode; + + /* RX DMA channel preparation, if the char callback is defined then the + TCIE interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; + else + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; + dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, 1); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamDisable(uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CR1 = 0; + uartp->usart->CR2 = 0; + uartp->usart->CR3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint32_t cr1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ +#if defined(STM32F0XX) + if (uartp->usart == USART1) + u->BRR = STM32_USART1CLK / uartp->config->speed; + else + u->BRR = STM32_PCLK / uartp->config->speed; +#else /* !defined(STM32F0XX) */ + if (uartp->usart == USART1) + u->BRR = STM32_PCLK2 / uartp->config->speed; + else + u->BRR = STM32_PCLK1 / uartp->config->speed; +#endif /* !defined(STM32F0XX) */ + + /* Resetting eventual pending status flags.*/ + u->ICR = 0xFFFFFFFF; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; + u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | + USART_CR3_EIE; + if (uartp->config->txend2_cb == NULL) + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; + else + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | + USART_CR1_TCIE; + u->CR1 = uartp->config->cr1 | cr1; + + /* Starting the receiver idle loop.*/ + set_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) + uartp->config->rxchar_cb(uartp, uartp->rxbuf); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaStreamDisable(uartp->dmarx); + uartp->rxstate = UART_RX_COMPLETE; + if (uartp->config->rxend_cb != NULL) + uartp->config->rxend_cb(uartp); + + /* If the callback didn't explicitly change state then the receiver + automatically returns to the idle state.*/ + if (uartp->rxstate == UART_RX_COMPLETE) { + uartp->rxstate = UART_RX_IDLE; + set_rx_idle_loop(uartp); + } + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(uartp->dmatx); + + /* A callback is generated, if enabled, after a completed transfer.*/ + uartp->txstate = UART_TX_COMPLETE; + if (uartp->config->txend1_cb != NULL) + uartp->config->txend1_cb(uartp); + + /* If the callback didn't explicitly change state then the transmitter + automatically returns to the idle state.*/ + if (uartp->txstate == UART_TX_COMPLETE) + uartp->txstate = UART_TX_IDLE; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_usart_irq(UARTDriver *uartp) { + uint32_t isr; + USART_TypeDef *u = uartp->usart; + + /* Reading and clearing status.*/ + isr = u->ISR; + u->ICR = isr; + + if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE | + USART_ISR_FE | USART_ISR_PE)) { + if (uartp->config->rxerr_cb != NULL) + uartp->config->rxerr_cb(uartp, translate_errors(isr)); + } + if (isr & USART_ISR_TC) { + /* End of transmission, a callback is generated.*/ + if (uartp->config->txend2_cb != NULL) + uartp->config->txend2_cb(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +#if !defined(STM32_USART1_HANDLER) +#error "STM32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART1 */ + +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +#if !defined(STM32_USART2_HANDLER) +#error "STM32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART2 */ + +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +#if !defined(STM32_USART3_HANDLER) +#error "STM32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USART3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if STM32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); + UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); + UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); + UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); + rccEnableUSART1(FALSE); + nvicEnableVector(STM32_USART1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableUSART2(FALSE); + nvicEnableVector(STM32_USART2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); + rccEnableUSART3(FALSE); + nvicEnableVector(STM32_USART3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) + uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); + dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + dmaStreamRelease(uartp->dmarx); + dmaStreamRelease(uartp->dmatx); + +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + nvicDisableVector(STM32_USART1_NUMBER); + rccDisableUSART1(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + nvicDisableVector(STM32_USART2_NUMBER); + rccDisableUSART2(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + nvicDisableVector(STM32_USART3_NUMBER); + rccDisableUSART3(FALSE); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmatx, txbuf); + dmaStreamSetTransactionSize(uartp->dmatx, n); + dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaStreamDisable(uartp->dmatx); + return dmaStreamGetTransactionSize(uartp->dmatx); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaStreamDisable(uartp->dmarx); + + /* RX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmarx, rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, n); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaStreamDisable(uartp->dmarx); + n = dmaStreamGetTransactionSize(uartp->dmarx); + set_rx_idle_loop(uartp); + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USARTv2/uart_lld.h b/os/hal/platforms/STM32/USARTv2/uart_lld.h new file mode 100644 index 000000000..6d44af0ba --- /dev/null +++ b/os/hal/platforms/STM32/USARTv2/uart_lld.h @@ -0,0 +1,458 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USARTv2/uart_lld.h + * @brief STM32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART1 FALSE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART2 FALSE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART3 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_DMA_PRIORITY 0 +#endif + +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief USART1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for USART1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#endif + +/** + * @brief DMA stream used for USART1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#endif + +/** + * @brief DMA stream used for USART2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +/** + * @brief DMA stream used for USART2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for USART3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#endif + +/** + * @brief DMA stream used for USART3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +#else /* !STM32_ADVANCED_DMA*/ + +#if defined(STM32F0XX) +/* Fixed values for STM32F0xx devices.*/ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif /* defined(STM32F0XX) */ + +#if defined(STM32F30X)|| defined(STM32F37X) +/* Fixed values for STM32F3xx devices.*/ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif /* defined(STM32F30X) */ + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ + !STM32_UART_USE_USART3 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if STM32_UART_USE_USART1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if STM32_UART_USE_USART2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if STM32_UART_USE_USART3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART1" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART2" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART3" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_MSK) +#error "invalid DMA stream associated to USART1 RX" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_MSK) +#error "invalid DMA stream associated to USART1 TX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_MSK) +#error "invalid DMA stream associated to USART2 RX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_MSK) +#error "invalid DMA stream associated to USART2 TX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_MSK) +#error "invalid DMA stream associated to USART3 RX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_MSK) +#error "invalid DMA stream associated to USART3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint32_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint32_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint32_t cr3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/platforms/STM32/USBv1/stm32_usb.h new file mode 100644 index 000000000..83f349e42 --- /dev/null +++ b/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -0,0 +1,243 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file stm32_usb.h + * @brief STM32 USB registers layout header. + * @note This file requires definitions from the ST STM32 header files + * stm32f10x.h or stm32l1xx.h. + * + * @addtogroup USB + * @{ + */ + +#ifndef _STM32_USB_H_ +#define _STM32_USB_H_ + +/** + * @brief Number of the available endpoints. + * @details This value does not include the endpoint 0 which is always present. + */ +#define USB_ENDOPOINTS_NUMBER 7 + +/** + * @brief USB registers block. + */ +typedef struct { + /** + * @brief Endpoint registers. + */ + volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1]; + /* + * @brief Reserved space. + */ + volatile uint32_t _r20[8]; + /* + * @brief Control Register. + */ + volatile uint32_t CNTR; + /* + * @brief Interrupt Status Register. + */ + volatile uint32_t ISTR; + /* + * @brief Frame Number Register. + */ + volatile uint32_t FNR; + /* + * @brief Device Address Register. + */ + volatile uint32_t DADDR; + /* + * @brief Buffer Table Address. + */ + volatile uint32_t BTABLE; +} stm32_usb_t; + +/** + * @brief USB descriptor registers block. + */ +typedef struct { + /** + * @brief TX buffer offset register. + */ + volatile uint32_t TXADDR0; + /** + * @brief TX counter register 0. + */ + volatile uint16_t TXCOUNT0; + /** + * @brief TX counter register 1. + */ + volatile uint16_t TXCOUNT1; + /** + * @brief RX buffer offset register. + */ + volatile uint32_t RXADDR0; + /** + * @brief RX counter register 0. + */ + volatile uint16_t RXCOUNT0; + /** + * @brief RX counter register 1. + */ + volatile uint16_t RXCOUNT1; +} stm32_usb_descriptor_t; + +/** + * @name Register aliases + * @{ + */ +#define RXADDR1 TXADDR0 +#define TXADDR1 RXADDR0 +/** @} */ + +/** + * @brief USB registers block numeric address. + */ +#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) + +/** + * @brief USB RAM numeric address. + */ +#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) + +/** + * @brief Pointer to the USB registers block. + */ +#define STM32_USB ((stm32_usb_t *)STM32_USB_BASE) + +/** + * @brief Pointer to the USB RAM. + */ +#define STM32_USBRAM ((uint32_t *)STM32_USBRAM_BASE) + +/** + * @brief Size of the dedicated packet memory. + */ +#define USB_PMA_SIZE 512 + +/** + * @brief Mask of all the toggling bits in the EPR register. + */ +#define EPR_TOGGLE_MASK (EPR_STAT_TX_MASK | EPR_DTOG_TX | \ + EPR_STAT_RX_MASK | EPR_DTOG_RX | \ + EPR_SETUP) + +#define EPR_EA_MASK 0x000F +#define EPR_STAT_TX_MASK 0x0030 +#define EPR_STAT_TX_DIS 0x0000 +#define EPR_STAT_TX_STALL 0x0010 +#define EPR_STAT_TX_NAK 0x0020 +#define EPR_STAT_TX_VALID 0x0030 +#define EPR_DTOG_TX 0x0040 +#define EPR_SWBUF_RX EPR_DTOG_TX +#define EPR_CTR_TX 0x0080 +#define EPR_EP_KIND 0x0100 +#define EPR_EP_DBL_BUF EPR_EP_KIND +#define EPR_EP_STATUS_OUT EPR_EP_KIND +#define EPR_EP_TYPE_MASK 0x0600 +#define EPR_EP_TYPE_BULK 0x0000 +#define EPR_EP_TYPE_CONTROL 0x0200 +#define EPR_EP_TYPE_ISO 0x0400 +#define EPR_EP_TYPE_INTERRUPT 0x0600 +#define EPR_SETUP 0x0800 +#define EPR_STAT_RX_MASK 0x3000 +#define EPR_STAT_RX_DIS 0x0000 +#define EPR_STAT_RX_STALL 0x1000 +#define EPR_STAT_RX_NAK 0x2000 +#define EPR_STAT_RX_VALID 0x3000 +#define EPR_DTOG_RX 0x4000 +#define EPR_SWBUF_TX EPR_DTOG_RX +#define EPR_CTR_RX 0x8000 + +#define CNTR_FRES 0x0001 +#define CNTR_PDWN 0x0002 +#define CNTR_LP_MODE 0x0004 +#define CNTR_FSUSP 0x0008 +#define CNTR_RESUME 0x0010 +#define CNTR_ESOFM 0x0100 +#define CNTR_SOFM 0x0200 +#define CNTR_RESETM 0x0400 +#define CNTR_SUSPM 0x0800 +#define CNTR_WKUPM 0x1000 +#define CNTR_ERRM 0x2000 +#define CNTR_PMAOVRM 0x4000 +#define CNTR_CTRM 0x8000 + +#define ISTR_EP_ID_MASK 0x000F +#define ISTR_DIR 0x0010 +#define ISTR_ESOF 0x0100 +#define ISTR_SOF 0x0200 +#define ISTR_RESET 0x0400 +#define ISTR_SUSP 0x0800 +#define ISTR_WKUP 0x1000 +#define ISTR_ERR 0x2000 +#define ISTR_PMAOVR 0x4000 +#define ISTR_CTR 0x8000 + +#define FNR_FN_MASK 0x07FF +#define FNR_LSOF 0x1800 +#define FNR_LCK 0x2000 +#define FNR_RXDM 0x4000 +#define FNR_RXDP 0x8000 + +#define DADDR_ADD_MASK 0x007F +#define DADDR_EF 0x0080 + +#define RXCOUNT_COUNT_MASK 0x03FF +#define TXCOUNT_COUNT_MASK 0x03FF + +#define EPR_SET(ep, epr) \ + STM32_USB->EPR[ep] = (epr) & ~EPR_TOGGLE_MASK + +#define EPR_TOGGLE(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) + +#define EPR_SET_STAT_RX(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \ + ~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \ + (epr) + +#define EPR_SET_STAT_TX(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \ + ~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \ + (epr) + +#define EPR_CLEAR_CTR_RX(ep) \ + STM32_USB->EPR[ep] &= ~EPR_CTR_RX & ~EPR_TOGGLE_MASK + +#define EPR_CLEAR_CTR_TX(ep) \ + STM32_USB->EPR[ep] &= ~EPR_CTR_TX & ~EPR_TOGGLE_MASK + +/** + * @brief Returns an endpoint descriptor pointer. + */ +#define USB_GET_DESCRIPTOR(ep) \ + ((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \ + (uint32_t)STM32_USB->BTABLE * 2 + \ + (uint32_t)(ep) * \ + sizeof(stm32_usb_descriptor_t))) + +/** + * @brief Converts from a PMA address to a physical address. + */ +#define USB_ADDR2PTR(addr) \ + ((uint32_t *)((addr) * 2 + STM32_USBRAM_BASE)) + +#endif /* _STM32_USB_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c new file mode 100644 index 000000000..22af59866 --- /dev/null +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -0,0 +1,830 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USBv1/usb_lld.c + * @brief STM32 USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BTABLE_ADDR 0x0000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USB1 driver identifier.*/ +#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out, + 1, + ep0setup_buffer +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Resets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void usb_pm_reset(USBDriver *usbp) { + + /* The first 64 bytes are reserved for the descriptors table. The effective + available RAM for endpoint buffers is just 448 bytes.*/ + usbp->pmnext = 64; +} + +/** + * @brief Resets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] size size of the packet buffer to allocate + */ +static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) { + uint32_t next; + + next = usbp->pmnext; + usbp->pmnext += size; + chDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "usb_pm_alloc(), #1", "PMA overflow"); + return next; +} + +/** + * @brief Reads from a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_read_to_buffer(stm32_usb_descriptor_t *udp, + uint8_t *buf, size_t n) { + uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0); + + n = (n + 1) / 2; + while (n > 0) { + /* Note, this line relies on the Cortex-M3/M4 ability to perform + unaligned word accesses.*/ + *(uint16_t *)buf = (uint16_t)*pmap++; + buf += 2; + n--; + } +} + +/** + * @brief Reads from a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[in] iqp pointer to an @p InputQueue object + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_read_to_queue(stm32_usb_descriptor_t *udp, + InputQueue *iqp, size_t n) { + size_t nhw; + uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0); + + nhw = n / 2; + while (nhw > 0) { + uint32_t w; + + w = *pmap++; + *iqp->q_wrptr++ = (uint8_t)w; + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + *iqp->q_wrptr++ = (uint8_t)(w >> 8); + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + nhw--; + } + /* Last byte for odd numbers.*/ + if ((n & 1) != 0) { + *iqp->q_wrptr++ = (uint8_t)*pmap; + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + } + + /* Updating queue.*/ + chSysLockFromIsr(); + iqp->q_counter += n; + while (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; + chSysUnlockFromIsr(); +} + +/** + * @brief Writes to a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_write_from_buffer(stm32_usb_descriptor_t *udp, + const uint8_t *buf, + size_t n) { + uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0); + + udp->TXCOUNT0 = (uint16_t)n; + n = (n + 1) / 2; + while (n > 0) { + /* Note, this line relies on the Cortex-M3/M4 ability to perform + unaligned word accesses.*/ + *pmap++ = *(uint16_t *)buf; + buf += 2; + n--; + } +} + +/** + * @brief Writes to a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp, + OutputQueue *oqp, size_t n) { + size_t nhw; + uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0); + + udp->TXCOUNT0 = (uint16_t)n; + nhw = n / 2; + while (nhw > 0) { + uint32_t w; + + w = (uint32_t)*oqp->q_rdptr++; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + w |= (uint32_t)*oqp->q_rdptr++ << 8; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + *pmap++ = w; + nhw--; + } + + /* Last byte for odd numbers.*/ + if ((n & 1) != 0) { + *pmap = (uint32_t)*oqp->q_rdptr++; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + } + + /* Updating queue. Note, the lock is done in this unusual way because this + function can be called from both ISR and thread context so the kind + of lock function to be invoked cannot be decided beforehand.*/ + port_lock(); + dbg_enter_lock(); + + oqp->q_counter += n; + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + + dbg_leave_lock(); + port_unlock(); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) +#if !defined(STM32_USB1_HP_HANDLER) +#error "STM32_USB1_HP_HANDLER not defined" +#endif +/** + * @brief USB high priority interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(STM32_USB1_LP_HANDLER) +#error "STM32_USB1_LP_HANDLER not defined" +#endif +/** + * @brief USB low priority interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) { + uint32_t istr; + USBDriver *usbp = &USBD1; + + CH_IRQ_PROLOGUE(); + + istr = STM32_USB->ISTR; + + /* USB bus reset condition handling.*/ + if (istr & ISTR_RESET) { + _usb_reset(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); + STM32_USB->ISTR = ~ISTR_RESET; + } + + /* USB bus SUSPEND condition handling.*/ + if (istr & ISTR_SUSP) { + STM32_USB->CNTR |= CNTR_FSUSP; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND); +#if STM32_USB_LOW_POWER_ON_SUSPEND + STM32_USB->CNTR |= CNTR_LP_MODE; +#endif + STM32_USB->ISTR = ~ISTR_SUSP; + } + + /* USB bus WAKEUP condition handling.*/ + if (istr & ISTR_WKUP) { + uint32_t fnr = STM32_USB->FNR; + if (!(fnr & FNR_RXDP)) { + STM32_USB->CNTR &= ~CNTR_FSUSP; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP); + } +#if STM32_USB_LOW_POWER_ON_SUSPEND + else { + /* Just noise, going back in SUSPEND mode, reference manual 22.4.5, + table 169.*/ + STM32_USB->CNTR |= CNTR_LP_MODE; + } +#endif + STM32_USB->ISTR = ~ISTR_WKUP; + } + + /* SOF handling.*/ + if (istr & ISTR_SOF) { + _usb_isr_invoke_sof_cb(usbp); + STM32_USB->ISTR = ~ISTR_SOF; + } + + /* Endpoint events handling.*/ + while (istr & ISTR_CTR) { + size_t n; + uint32_t ep; + uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK]; + const USBEndpointConfig *epcp = usbp->epc[ep]; + + if (epr & EPR_CTR_TX) { + size_t transmitted; + /* IN endpoint, transmission.*/ + EPR_CLEAR_CTR_TX(ep); + + transmitted = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0; + epcp->in_state->txcnt += transmitted; + n = epcp->in_state->txsize - epcp->in_state->txcnt; + if (n > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (n > epcp->in_maxsize) + n = epcp->in_maxsize; + + if (epcp->in_state->txqueued) + usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep), + epcp->in_state->mode.queue.txqueue, + n); + else { + epcp->in_state->mode.linear.txbuf += transmitted; + usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep), + epcp->in_state->mode.linear.txbuf, + n); + } + chSysLockFromIsr(); + usb_lld_start_in(usbp, ep); + chSysUnlockFromIsr(); + } + else { + /* Transfer completed, invokes the callback.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + } + if (epr & EPR_CTR_RX) { + EPR_CLEAR_CTR_RX(ep); + /* OUT endpoint, receive.*/ + if (epr & EPR_SETUP) { + /* Setup packets handling, setup packets are handled using a + specific callback.*/ + _usb_isr_invoke_setup_cb(usbp, ep); + } + else { + stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep); + n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; + + /* Reads the packet into the defined buffer.*/ + if (epcp->out_state->rxqueued) + usb_packet_read_to_queue(udp, + epcp->out_state->mode.queue.rxqueue, + n); + else { + usb_packet_read_to_buffer(udp, + epcp->out_state->mode.linear.rxbuf, + n); + epcp->out_state->mode.linear.rxbuf += n; + } + /* Transaction data updated.*/ + epcp->out_state->rxcnt += n; + epcp->out_state->rxsize -= n; + epcp->out_state->rxpkts -= 1; + + /* The transaction is completed if the specified number of packets + has been received or the current packet is a short packet.*/ + if ((n < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) { + /* Transfer complete, invokes the callback.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } + else { + /* Transfer not complete, there are more packets to receive.*/ + EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); + } + } + } + istr = STM32_USB->ISTR; + } + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + + /* Driver initialization.*/ + usbObjectInit(&USBD1); +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Clock activation.*/ +#if STM32_USB_USE_USB1 + if (&USBD1 == usbp) { + /* USB clock enabled.*/ + rccEnableUSB(FALSE); + /* Powers up the transceiver while holding the USB in reset state.*/ + STM32_USB->CNTR = CNTR_FRES; + /* Enabling the USB IRQ vectors, this also gives enough time to allow + the transceiver power up (1uS).*/ + nvicEnableVector(STM32_USB1_HP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY)); + nvicEnableVector(STM32_USB1_LP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY)); + /* Releases the USB reset.*/ + STM32_USB->CNTR = 0; + } +#endif + /* Reset procedure enforced on driver start.*/ + _usb_reset(usbp); + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + + /* If in ready state then disables the USB clock.*/ + if (usbp->state == USB_STOP) { +#if STM32_USB_USE_USB1 + if (&USBD1 == usbp) { + nvicDisableVector(STM32_USB1_HP_NUMBER); + nvicDisableVector(STM32_USB1_LP_NUMBER); + STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; + rccDisableUSB(FALSE); + } +#endif + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + uint32_t cntr; + + /* Post reset initialization.*/ + STM32_USB->BTABLE = 0; + STM32_USB->ISTR = 0; + STM32_USB->DADDR = DADDR_EF; + cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | + CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; + /* The SOF interrupt is only enabled if a callback is defined for + this service because it is an high rate source.*/ + if (usbp->config->sof_cb != NULL) + cntr |= CNTR_SOFM; + STM32_USB->CNTR = cntr; + + /* Resets the packet memory allocator.*/ + usb_pm_reset(usbp); + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + + STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + uint16_t nblocks, epr; + stm32_usb_descriptor_t *dp; + const USBEndpointConfig *epcp = usbp->epc[ep]; + + /* Setting the endpoint type.*/ + switch (epcp->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_ISOC: + epr = EPR_EP_TYPE_ISO; + break; + case USB_EP_MODE_TYPE_BULK: + epr = EPR_EP_TYPE_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + epr = EPR_EP_TYPE_INTERRUPT; + break; + default: + epr = EPR_EP_TYPE_CONTROL; + } + + /* IN endpoint initially in NAK mode.*/ + if (epcp->in_cb != NULL) + epr |= EPR_STAT_TX_NAK; + + /* OUT endpoint initially in NAK mode.*/ + if (epcp->out_cb != NULL) + epr |= EPR_STAT_RX_NAK; + + /* EPxR register setup.*/ + EPR_SET(ep, epr | ep); + EPR_TOGGLE(ep, epr); + + /* Endpoint size and address initialization.*/ + if (epcp->out_maxsize > 62) + nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) | + 0x8000; + else + nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10; + dp = USB_GET_DESCRIPTOR(ep); + dp->TXCOUNT0 = 0; + dp->RXCOUNT0 = nblocks; + dp->TXADDR0 = usb_pm_alloc(usbp, epcp->in_maxsize); + dp->RXADDR0 = usb_pm_alloc(usbp, epcp->out_maxsize); +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + unsigned i; + + /* Resets the packet memory allocator.*/ + usb_pm_reset(usbp); + + /* Disabling all endpoints.*/ + for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) { + EPR_TOGGLE(i, 0); + EPR_SET(i, 0); + } +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) { + case EPR_STAT_RX_DIS: + return EP_STATUS_DISABLED; + case EPR_STAT_RX_STALL: + return EP_STATUS_STALLED; + default: + return EP_STATUS_ACTIVE; + } +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) { + case EPR_STAT_TX_DIS: + return EP_STATUS_DISABLED; + case EPR_STAT_TX_STALL: + return EP_STATUS_STALLED; + default: + return EP_STATUS_ACTIVE; + } +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + uint32_t *pmap; + stm32_usb_descriptor_t *udp; + uint32_t n; + + (void)usbp; + udp = USB_GET_DESCRIPTOR(ep); + pmap = USB_ADDR2PTR(udp->RXADDR0); + for (n = 0; n < 4; n++) { + *(uint16_t *)buf = (uint16_t)*pmap++; + buf += 2; + } +} + +/** + * @brief Prepares for a receive operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + if (osp->rxsize == 0) /* Special case for zero sized packets.*/ + osp->rxpkts = 1; + else + osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize); +} + +/** + * @brief Prepares for a transmit operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { + size_t n; + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + n = isp->txsize; + if (n > (size_t)usbp->epc[ep]->in_maxsize) + n = (size_t)usbp->epc[ep]->in_maxsize; + + if (isp->txqueued) + usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep), + isp->mode.queue.txqueue, n); + else + usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep), + isp->mode.linear.txbuf, n); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL); +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL); +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID) + EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK); +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID) + EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK); +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.h b/os/hal/platforms/STM32/USBv1/usb_lld.h new file mode 100644 index 000000000..a0092a334 --- /dev/null +++ b/os/hal/platforms/STM32/USBv1/usb_lld.h @@ -0,0 +1,437 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/USBv1/usb_lld.h + * @brief STM32 USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "stm32_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS USB_ENDOPOINTS_NUMBER + +/** + * @brief This device requires the address change after the status packet. + */ +#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver enable switch. + * @details If set to @p TRUE the support for USB1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__) +#define STM32_USB_USE_USB1 FALSE +#endif + +/** + * @brief Enables the USB device low power mode on suspend. + */ +#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__) +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#endif + +/** + * @brief USB1 interrupt priority level setting. + */ +#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#endif + +/** + * @brief USB1 interrupt priority level setting. + */ +#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 && !STM32_HAS_USB +#error "USB not present in the selected device" +#endif + +#if !STM32_USB_USE_USB1 +#error "USB driver activated but no USB peripheral assigned" +#endif + +#if STM32_USB_USE_USB1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USB HP" +#endif + +#if STM32_USB_USE_USB1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USB LP" +#endif + +#if STM32_USBCLK != 48000000 +#error "the USB driver requires a 48MHz clock" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t txqueued; + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + union { + struct { + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; + } linear; + struct { + /** + * @brief Pointer to the output queue. + */ + OutputQueue *txqueue; + } queue; + /* End of the mandatory fields.*/ + } mode; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t rxqueued; + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + union { + struct { + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; + } linear; + struct { + /** + * @brief Pointer to the input queue. + */ + InputQueue *rxqueue; + } queue; + } mode; + /* End of the mandatory fields.*/ + /** + * @brief Number of packets to receive. + */ + uint16_t rxpkts; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Reserved field, not currently used. + * @note Initialize this field to 1 in order to be forward compatible. + */ + uint16_t ep_buffers; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Returns the exact size of a received packet. + * @pre The OUT endpoint must have been configured in packet mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_packet_size(usbp, ep) \ + ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c new file mode 100644 index 000000000..30e9dd7cf --- /dev/null +++ b/os/hal/platforms/STM32/can_lld.c @@ -0,0 +1,719 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/can_lld.c + * @brief STM32 CAN subsystem low level driver source. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief CAN1 driver identifier.*/ +#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/** @brief CAN2 driver identifier.*/ +#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) +CANDriver CAND2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Programs the filters. + * + * @param[in] can2sb number of the first filter assigned to CAN2 + * @param[in] num number of entries in the filters array, if zero then + * a default filter is programmed + * @param[in] cfp pointer to the filters array, can be @p NULL if + * (num == 0) + * + * @notapi + */ +static void can_lld_set_filters(uint32_t can2sb, + uint32_t num, + const CANFilter *cfp) { + + /* Temporarily enabling CAN1 clock.*/ + rccEnableCAN1(FALSE); + + /* Filters initialization.*/ + CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT; + if (num > 0) { + uint32_t i, fmask; + + /* All filters cleared.*/ + CAN1->FA1R = 0; + CAN1->FM1R = 0; + CAN1->FS1R = 0; + CAN1->FFA1R = 0; + for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { + CAN1->sFilterRegister[i].FR1 = 0; + CAN1->sFilterRegister[i].FR2 = 0; + } + + /* Scanning the filters array.*/ + for (i = 0; i < num; i++) { + fmask = 1 << cfp->filter; + if (cfp->mode) + CAN1->FM1R |= fmask; + if (cfp->scale) + CAN1->FS1R |= fmask; + if (cfp->assignment) + CAN1->FFA1R |= fmask; + CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1; + CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2; + CAN1->FA1R |= fmask; + cfp++; + } + } + else { + /* Setting up a single default filter that enables everything for both + CANs.*/ + CAN1->sFilterRegister[0].FR1 = 0; + CAN1->sFilterRegister[0].FR2 = 0; + CAN1->sFilterRegister[can2sb].FR1 = 0; + CAN1->sFilterRegister[can2sb].FR2 = 0; + CAN1->FM1R = 0; + CAN1->FFA1R = 0; + CAN1->FS1R = 1 | (1 << can2sb); + CAN1->FA1R = 1 | (1 << can2sb); + } + CAN1->FMR &= ~CAN_FMR_FINIT; + + /* Clock disabled, it will be enabled again in can_lld_start().*/ + rccDisableCAN1(FALSE); +} + +/** + * @brief Common TX ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_tx_handler(CANDriver *canp) { + + /* No more events until a message is transmitted.*/ + canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2; + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->txsem) < 0) + chSemSignalI(&canp->txsem); + chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1)); + chSysUnlockFromIsr(); +} + +/** + * @brief Common RX0 ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_rx0_handler(CANDriver *canp) { + uint32_t rf0r; + + rf0r = canp->can->RF0R; + if ((rf0r & CAN_RF0R_FMP0) > 0) { + /* No more receive events until the queue 0 has been emptied.*/ + canp->can->IER &= ~CAN_IER_FMPIE0; + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->rxsem) < 0) + chSemSignalI(&canp->rxsem); + chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1)); + chSysUnlockFromIsr(); + } + if ((rf0r & CAN_RF0R_FOVR0) > 0) { + /* Overflow events handling.*/ + canp->can->RF0R = CAN_RF0R_FOVR0; + chSysLockFromIsr(); + chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); + chSysUnlockFromIsr(); + } +} + +/** + * @brief Common RX1 ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_rx1_handler(CANDriver *canp) { + uint32_t rf1r; + + rf1r = canp->can->RF1R; + if ((rf1r & CAN_RF1R_FMP1) > 0) { + /* No more receive events until the queue 0 has been emptied.*/ + canp->can->IER &= ~CAN_IER_FMPIE1; + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->rxsem) < 0) + chSemSignalI(&canp->rxsem); + chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2)); + chSysUnlockFromIsr(); + } + if ((rf1r & CAN_RF1R_FOVR1) > 0) { + /* Overflow events handling.*/ + canp->can->RF1R = CAN_RF1R_FOVR1; + chSysLockFromIsr(); + chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); + chSysUnlockFromIsr(); + } +} + +/** + * @brief Common SCE ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_sce_handler(CANDriver *canp) { + uint32_t msr; + + msr = canp->can->MSR; + canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI; + /* Wakeup event.*/ +#if CAN_USE_SLEEP_MODE + if (msr & CAN_MSR_WKUI) { + canp->state = CAN_READY; + canp->can->MCR &= ~CAN_MCR_SLEEP; + chSysLockFromIsr(); + chEvtBroadcastI(&canp->wakeup_event); + chSysUnlockFromIsr(); + } +#endif /* CAN_USE_SLEEP_MODE */ + /* Error event.*/ + if (msr & CAN_MSR_ERRI) { + flagsmask_t flags; + uint32_t esr = canp->can->ESR; + + canp->can->ESR &= ~CAN_ESR_LEC; + flags = (flagsmask_t)(esr & 7); + if ((esr & CAN_ESR_LEC) > 0) + flags |= CAN_FRAMING_ERROR; + + chSysLockFromIsr(); + /* The content of the ESR register is copied unchanged in the upper + half word of the listener flags mask.*/ + chEvtBroadcastFlagsI(&canp->error_event, flags | (flagsmask_t)(esr << 16)); + chSysUnlockFromIsr(); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) +/** + * @brief CAN1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN1 RX0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx0_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 RX1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx1_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 SCE interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_sce_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_CAN_USE_CAN1 */ + +#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) +/** + * @brief CAN2 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN2 RX0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx0_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 RX1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx1_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 SCE interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_sce_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_CAN_USE_CAN2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if STM32_CAN_USE_CAN1 + /* Driver initialization.*/ + canObjectInit(&CAND1); + CAND1.can = CAN1; +#endif +#if STM32_CAN_USE_CAN2 + /* Driver initialization.*/ + canObjectInit(&CAND2); + CAND2.can = CAN2; +#endif + + /* Filters initialization.*/ +#if STM32_HAS_CAN2 + can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL); +#else + can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL); +#endif + +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + /* Clock activation.*/ +#if STM32_CAN_USE_CAN1 + if (&CAND1 == canp) { + nvicEnableVector(STM32_CAN1_TX_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN1_RX0_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN1_RX1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN1_SCE_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + rccEnableCAN1(FALSE); + } +#endif +#if STM32_CAN_USE_CAN2 + if (&CAND2 == canp) { + + chDbgAssert(CAND1.state != CAN_STOP, + "can_lld_start(), #1", "CAN1 must be started"); + + nvicEnableVector(STM32_CAN2_TX_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN2_RX0_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN2_RX1_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); + nvicEnableVector(STM32_CAN2_SCE_NUMBER, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); + rccEnableCAN2(FALSE); + } +#endif + + /* Entering initialization mode. */ + canp->state = CAN_STARTING; + canp->can->MCR = CAN_MCR_INRQ; + while ((canp->can->MSR & CAN_MSR_INAK) == 0) + chThdSleepS(1); + /* BTR initialization.*/ + canp->can->BTR = canp->config->btr; + /* MCR initialization.*/ + canp->can->MCR = canp->config->mcr; + + /* Interrupt sources initialization.*/ + canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | + CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | + CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | + CAN_IER_FOVIE0 | CAN_IER_FOVIE1; +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { +#if STM32_CAN_USE_CAN1 + if (&CAND1 == canp) { + +#if STM32_CAN_USE_CAN2 + chDbgAssert(CAND2.state == CAN_STOP, + "can_lld_stop(), #1", "CAN2 must be stopped"); +#endif + + CAN1->MCR = 0x00010002; /* Register reset value. */ + CAN1->IER = 0x00000000; /* All sources disabled. */ + nvicDisableVector(STM32_CAN1_TX_NUMBER); + nvicDisableVector(STM32_CAN1_RX0_NUMBER); + nvicDisableVector(STM32_CAN1_RX1_NUMBER); + nvicDisableVector(STM32_CAN1_SCE_NUMBER); + rccDisableCAN1(FALSE); + } +#endif +#if STM32_CAN_USE_CAN2 + if (&CAND2 == canp) { + CAN2->MCR = 0x00010002; /* Register reset value. */ + CAN2->IER = 0x00000000; /* All sources disabled. */ + nvicDisableVector(STM32_CAN2_TX_NUMBER); + nvicDisableVector(STM32_CAN2_RX0_NUMBER); + nvicDisableVector(STM32_CAN2_RX1_NUMBER); + nvicDisableVector(STM32_CAN2_SCE_NUMBER); + rccDisableCAN2(FALSE); + } +#endif + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + + switch (mailbox) { + case CAN_ANY_MAILBOX: + return (canp->can->TSR & CAN_TSR_TME) != 0; + case 1: + return (canp->can->TSR & CAN_TSR_TME0) != 0; + case 2: + return (canp->can->TSR & CAN_TSR_TME1) != 0; + case 3: + return (canp->can->TSR & CAN_TSR_TME2) != 0; + default: + return FALSE; + } +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp) { + uint32_t tir; + CAN_TxMailBox_TypeDef *tmbp; + + /* Pointer to a free transmission mailbox.*/ + switch (mailbox) { + case CAN_ANY_MAILBOX: + tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24]; + break; + case 1: + tmbp = &canp->can->sTxMailBox[0]; + break; + case 2: + tmbp = &canp->can->sTxMailBox[1]; + break; + case 3: + tmbp = &canp->can->sTxMailBox[2]; + break; + default: + return; + } + + /* Preparing the message.*/ + if (ctfp->IDE) + tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) | + CAN_TI0R_IDE; + else + tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1); + tmbp->TDTR = ctfp->DLC; + tmbp->TDLR = ctfp->data32[0]; + tmbp->TDHR = ctfp->data32[1]; + tmbp->TIR = tir | CAN_TI0R_TXRQ; +} + +/** + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + + switch (mailbox) { + case CAN_ANY_MAILBOX: + return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 || + (canp->can->RF1R & CAN_RF1R_FMP1) != 0); + case 1: + return (canp->can->RF0R & CAN_RF0R_FMP0) != 0; + case 2: + return (canp->can->RF1R & CAN_RF1R_FMP1) != 0; + default: + return FALSE; + } +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp) { + uint32_t rir, rdtr; + + if (mailbox == CAN_ANY_MAILBOX) { + if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0) + mailbox = 1; + else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0) + mailbox = 2; + else { + /* Should not happen, do nothing.*/ + return; + } + } + switch (mailbox) { + case 1: + /* Fetches the message.*/ + rir = canp->can->sFIFOMailBox[0].RIR; + rdtr = canp->can->sFIFOMailBox[0].RDTR; + crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR; + crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR; + + /* Releases the mailbox.*/ + canp->can->RF0R = CAN_RF0R_RFOM0; + + /* If the queue is empty re-enables the interrupt in order to generate + events again.*/ + if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0) + canp->can->IER |= CAN_IER_FMPIE0; + break; + case 2: + /* Fetches the message.*/ + rir = canp->can->sFIFOMailBox[1].RIR; + rdtr = canp->can->sFIFOMailBox[1].RDTR; + crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR; + crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR; + + /* Releases the mailbox.*/ + canp->can->RF1R = CAN_RF1R_RFOM1; + + /* If the queue is empty re-enables the interrupt in order to generate + events again.*/ + if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0) + canp->can->IER |= CAN_IER_FMPIE1; + break; + default: + /* Should not happen, do nothing.*/ + return; + } + + /* Decodes the various fields in the RX frame.*/ + crfp->RTR = (rir & CAN_RI0R_RTR) >> 1; + crfp->IDE = (rir & CAN_RI0R_IDE) >> 2; + if (crfp->IDE) + crfp->EID = rir >> 3; + else + crfp->SID = rir >> 21; + crfp->DLC = rdtr & CAN_RDT0R_DLC; + crfp->FMI = (uint8_t)(rdtr >> 8); + crfp->TIME = (uint16_t)(rdtr >> 16); +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + + canp->can->MCR |= CAN_MCR_SLEEP; +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + + canp->can->MCR &= ~CAN_MCR_SLEEP; +} +#endif /* CAN_USE_SLEEP_MODE */ + +/** + * @brief Programs the filters. + * @note This is an STM32-specific API. + * + * @param[in] can2sb number of the first filter assigned to CAN2 + * @param[in] num number of entries in the filters array, if zero then + * a default filter is programmed + * @param[in] cfp pointer to the filters array, can be @p NULL if + * (num == 0) + * + * @api + */ +void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) { + + chDbgCheck((can2sb > 1) && (can2sb < STM32_CAN_MAX_FILTERS) && + (num < STM32_CAN_MAX_FILTERS), + "canSTM32SetFilters"); + +#if STM32_CAN_USE_CAN1 + chDbgAssert(CAND1.state == CAN_STOP, + "canSTM32SetFilters(), #1", "invalid state"); +#endif +#if STM32_CAN_USE_CAN2 + chDbgAssert(CAND2.state == CAN_STOP, + "canSTM32SetFilters(), #2", "invalid state"); +#endif + + can_lld_set_filters(can2sb, num, cfp); +} + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h new file mode 100644 index 000000000..c339c01e7 --- /dev/null +++ b/os/hal/platforms/STM32/can_lld.h @@ -0,0 +1,366 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/can_lld.h + * @brief STM32 CAN subsystem low level driver header. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * The following macros from the ST header file are replaced with better + * equivalents. + */ +#undef CAN_BTR_BRP +#undef CAN_BTR_TS1 +#undef CAN_BTR_TS2 +#undef CAN_BTR_SJW + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with automatic an wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP TRUE + +/** + * @brief This implementation supports three transmit mailboxes. + */ +#define CAN_TX_MAILBOXES 3 + +/** + * @brief This implementation supports two receive mailboxes. + */ +#define CAN_RX_MAILBOXES 2 + +/** + * @name CAN registers helper macros + * @{ + */ +#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/ +#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/ +#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/ +#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/ + +#define CAN_IDE_STD 0 /**< @brief Standard id. */ +#define CAN_IDE_EXT 1 /**< @brief Extended id. */ + +#define CAN_RTR_DATA 0 /**< @brief Data frame. */ +#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for CAN1 is included. + */ +#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__) +#define STM32_CAN_USE_CAN1 FALSE +#endif + +/** + * @brief CAN2 driver enable switch. + * @details If set to @p TRUE the support for CAN2 is included. + */ +#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__) +#define STM32_CAN_USE_CAN2 FALSE +#endif + +/** + * @brief CAN1 interrupt priority level setting. + */ +#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN2 interrupt priority level setting. + */ +#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1 +#error "CAN1 not present in the selected device" +#endif + +#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2 +#error "CAN2 not present in the selected device" +#endif + +#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2 +#error "CAN driver activated but no CAN peripheral assigned" +#endif + +#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2 +#error "CAN2 requires CAN1, it cannot operate independently" +#endif + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a transmission mailbox index. + */ +typedef uint32_t canmbx_t; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t FMI; /**< @brief Filter id. */ + uint16_t TIME; /**< @brief Time stamp. */ + }; + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Refer to the STM32 reference manual for info about filters. + */ +typedef struct { + /** + * @brief Number of the filter to be programmed. + */ + uint32_t filter; + /** + * @brief Filter mode. + * @note This bit represent the CAN_FM1R register bit associated to this + * filter (0=mask mode, 1=list mode). + */ + uint32_t mode:1; + /** + * @brief Filter scale. + * @note This bit represent the CAN_FS1R register bit associated to this + * filter (0=16 bits mode, 1=32 bits mode). + */ + uint32_t scale:1; + /** + * @brief Filter mode. + * @note This bit represent the CAN_FFA1R register bit associated to this + * filter, must be set to zero in this version of the driver. + */ + uint32_t assignment:1; + /** + * @brief Filter register 1 (identifier). + */ + uint32_t register1; + /** + * @brief Filter register 2 (mask/identifier depending on mode=0/1). + */ + uint32_t register2; +} CANFilter; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CAN MCR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t mcr; + /** + * @brief CAN BTR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t btr; +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p chReceive() when listening to this event. + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + * @note The flags associated to the listeners will indicate which + * receive mailboxes become non-empty. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the listeners will indicate which + * transmit mailboxes become empty. + * + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + * @note The flags associated to the listeners will indicate the + * error(s) that have occurred. + */ + EventSource error_event; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CAN registers. + */ + CAN_TypeDef *can; +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__) +extern CANDriver CAND2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_is_tx_empty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *crfp); + bool_t can_lld_is_rx_nonempty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c new file mode 100644 index 000000000..970e0ce8e --- /dev/null +++ b/os/hal/platforms/STM32/ext_lld.c @@ -0,0 +1,221 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/ext_lld.c + * @brief STM32 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + unsigned i; + + if (extp->state == EXT_STOP) + ext_lld_exti_irq_enable(); + + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) + ext_lld_channel_enable(extp, i); + else + ext_lld_channel_disable(extp, i); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) + ext_lld_exti_irq_disable(); + + EXTI->EMR = 0; + EXTI->IMR = 0; + EXTI->PR = 0xFFFFFFFF; +#if STM32_EXTI_NUM_CHANNELS > 32 + EXTI->PR2 = 0xFFFFFFFF; +#endif +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + +#if STM32_EXTI_NUM_CHANNELS > 32 + if (channel < 32) { +#endif + /* Programming edge registers.*/ + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + EXTI->RTSR |= (1 << channel); + else + EXTI->RTSR &= ~(1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + EXTI->FTSR |= (1 << channel); + else + EXTI->FTSR &= ~(1 << channel); + + /* Programming interrupt and event registers.*/ + if (extp->config->channels[channel].cb != NULL) { + EXTI->IMR |= (1 << channel); + EXTI->EMR &= ~(1 << channel); + } + else { + EXTI->EMR |= (1 << channel); + EXTI->IMR &= ~(1 << channel); + } +#if STM32_EXTI_NUM_CHANNELS > 32 + } + else { + /* Programming edge registers.*/ + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + EXTI->RTSR2 |= (1 << (32 - channel)); + else + EXTI->RTSR2 &= ~(1 << (32 - channel)); + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + EXTI->FTSR2 |= (1 << (32 - channel)); + else + EXTI->FTSR2 &= ~(1 << (32 - channel)); + + /* Programming interrupt and event registers.*/ + if (extp->config->channels[channel].cb != NULL) { + EXTI->IMR2 |= (1 << (32 - channel)); + EXTI->EMR2 &= ~(1 << (32 - channel)); + } + else { + EXTI->EMR2 |= (1 << (32 - channel)); + EXTI->IMR2 &= ~(1 << (32 - channel)); + } + } +#endif + + /* Setting the associated GPIO for external channels.*/ + if (channel < 16) { + uint32_t n = channel >> 2; + uint32_t mask = ~(0xF << ((channel & 3) * 4)); + uint32_t port = ((extp->config->channels[channel].mode & + EXT_MODE_GPIO_MASK) >> + EXT_MODE_GPIO_OFF) << ((channel & 3) * 4); + +#if defined(STM32L1XX_MD) || defined(STM32F0XX) || defined(STM32F2XX) || \ + defined(STM32F30X) || defined(STM32F37X) || defined(STM32F4XX) + SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port; +#else /* STM32F1XX */ + AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port; +#endif /* STM32F1XX */ + } +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + +#if STM32_EXTI_NUM_CHANNELS > 32 + if (channel < 32) { +#endif + EXTI->IMR &= ~(1 << channel); + EXTI->EMR &= ~(1 << channel); + EXTI->RTSR &= ~(1 << channel); + EXTI->FTSR &= ~(1 << channel); + EXTI->PR = (1 << channel); +#if STM32_EXTI_NUM_CHANNELS > 32 + } + else { + EXTI->IMR2 &= ~(1 << (32 - channel)); + EXTI->EMR2 &= ~(1 << (32 - channel)); + EXTI->RTSR2 &= ~(1 << (32 - channel)); + EXTI->FTSR2 &= ~(1 << (32 - channel)); + EXTI->PR2 = (1 << (32 - channel)); + } +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h new file mode 100644 index 000000000..7a59fa728 --- /dev/null +++ b/os/hal/platforms/STM32/ext_lld.h @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/ext_lld.h + * @brief STM32 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS STM32_EXTI_NUM_CHANNELS + +/** + * @name STM32-specific EXT channel modes + * @{ + */ +#define EXT_MODE_GPIO_MASK 0xF0 /**< @brief Port field mask. */ +#define EXT_MODE_GPIO_OFF 4 /**< @brief Port field offset. */ +#define EXT_MODE_GPIOA 0x00 /**< @brief GPIOA identifier. */ +#define EXT_MODE_GPIOB 0x10 /**< @brief GPIOB identifier. */ +#define EXT_MODE_GPIOC 0x20 /**< @brief GPIOC identifier. */ +#define EXT_MODE_GPIOD 0x30 /**< @brief GPIOD identifier. */ +#define EXT_MODE_GPIOE 0x40 /**< @brief GPIOE identifier. */ +#define EXT_MODE_GPIOF 0x50 /**< @brief GPIOF identifier. */ +#define EXT_MODE_GPIOG 0x60 /**< @brief GPIOG identifier. */ +#define EXT_MODE_GPIOH 0x70 /**< @brief GPIOH identifier. */ +#define EXT_MODE_GPIOI 0x80 /**< @brief GPIOI identifier. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c new file mode 100644 index 000000000..35268fbe5 --- /dev/null +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -0,0 +1,762 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/gpt_lld.c + * @brief STM32 GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + * @note The driver GPTD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + * @note The driver GPTD2 allocates the timer TIM2 when enabled. + */ +#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPTD3 driver identifier. + * @note The driver GPTD3 allocates the timer TIM3 when enabled. + */ +#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPTD4 driver identifier. + * @note The driver GPTD4 allocates the timer TIM4 when enabled. + */ +#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/** + * @brief GPTD5 driver identifier. + * @note The driver GPTD5 allocates the timer TIM5 when enabled. + */ +#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__) +GPTDriver GPTD5; +#endif + +/** + * @brief GPTD6 driver identifier. + * @note The driver GPTD6 allocates the timer TIM6 when enabled. + */ +#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__) +GPTDriver GPTD6; +#endif + +/** + * @brief GPTD7 driver identifier. + * @note The driver GPTD7 allocates the timer TIM7 when enabled. + */ +#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__) +GPTDriver GPTD7; +#endif + +/** + * @brief GPTD8 driver identifier. + * @note The driver GPTD8 allocates the timer TIM8 when enabled. + */ +#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__) +GPTDriver GPTD8; +#endif + +/** + * @brief GPTD9 driver identifier. + * @note The driver GPTD9 allocates the timer TIM9 when enabled. + */ +#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__) +GPTDriver GPTD9; +#endif + +/** + * @brief GPTD11 driver identifier. + * @note The driver GPTD11 allocates the timer TIM11 when enabled. + */ +#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__) +GPTDriver GPTD11; +#endif + +/** + * @brief GPTD12 driver identifier. + * @note The driver GPTD12 allocates the timer TIM12 when enabled. + */ +#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__) +GPTDriver GPTD12; +#endif + +/** + * @brief GPTD14 driver identifier. + * @note The driver GPTD14 allocates the timer TIM14 when enabled. + */ +#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__) +GPTDriver GPTD14; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tim->SR = 0; + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 +#if !defined(STM32_TIM1_UP_HANDLER) +#error "STM32_TIM1_UP_HANDLER not defined" +#endif +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM1 */ + +#if STM32_GPT_USE_TIM2 +#if !defined(STM32_TIM2_HANDLER) +#error "STM32_TIM2_HANDLER not defined" +#endif +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM2 */ + +#if STM32_GPT_USE_TIM3 +#if !defined(STM32_TIM3_HANDLER) +#error "STM32_TIM3_HANDLER not defined" +#endif +/** + * @brief TIM3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM3 */ + +#if STM32_GPT_USE_TIM4 +#if !defined(STM32_TIM4_HANDLER) +#error "STM32_TIM4_HANDLER not defined" +#endif +/** + * @brief TIM4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM4 */ + +#if STM32_GPT_USE_TIM5 +#if !defined(STM32_TIM5_HANDLER) +#error "STM32_TIM5_HANDLER not defined" +#endif +/** + * @brief TIM5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM5 */ + +#if STM32_GPT_USE_TIM6 +#if !defined(STM32_TIM6_HANDLER) +#error "STM32_TIM6_HANDLER not defined" +#endif +/** + * @brief TIM6 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM6_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD6); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM6 */ + +#if STM32_GPT_USE_TIM7 +#if !defined(STM32_TIM7_HANDLER) +#error "STM32_TIM7_HANDLER not defined" +#endif +/** + * @brief TIM7 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM7_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD7); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM7 */ + +#if STM32_GPT_USE_TIM8 +#if !defined(STM32_TIM8_UP_HANDLER) +#error "STM32_TIM8_UP_HANDLER not defined" +#endif +/** + * @brief TIM8 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM8 */ + +#if STM32_GPT_USE_TIM9 +#if !defined(STM32_TIM9_HANDLER) +#error "STM32_TIM9_HANDLER not defined" +#endif +/** + * @brief TIM9 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM9 */ + +#if STM32_GPT_USE_TIM11 +#if !defined(STM32_TIM11_HANDLER) +#error "STM32_TIM11_HANDLER not defined" +#endif +/** + * @brief TIM11 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD11); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM11 */ + +#if STM32_GPT_USE_TIM12 +#if !defined(STM32_TIM12_HANDLER) +#error "STM32_TIM12_HANDLER not defined" +#endif +/** + * @brief TIM12 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM12_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD12); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM12 */ + +#if STM32_GPT_USE_TIM14 +#if !defined(STM32_TIM14_HANDLER) +#error "STM32_TIM14_HANDLER not defined" +#endif +/** + * @brief TIM14 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM14_HANDLER) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD14); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM14 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if STM32_GPT_USE_TIM1 + /* Driver initialization.*/ + GPTD1.tim = STM32_TIM1; + gptObjectInit(&GPTD1); +#endif + +#if STM32_GPT_USE_TIM2 + /* Driver initialization.*/ + GPTD2.tim = STM32_TIM2; + gptObjectInit(&GPTD2); +#endif + +#if STM32_GPT_USE_TIM3 + /* Driver initialization.*/ + GPTD3.tim = STM32_TIM3; + gptObjectInit(&GPTD3); +#endif + +#if STM32_GPT_USE_TIM4 + /* Driver initialization.*/ + GPTD4.tim = STM32_TIM4; + gptObjectInit(&GPTD4); +#endif + +#if STM32_GPT_USE_TIM5 + /* Driver initialization.*/ + GPTD5.tim = STM32_TIM5; + gptObjectInit(&GPTD5); +#endif + +#if STM32_GPT_USE_TIM6 + /* Driver initialization.*/ + GPTD6.tim = STM32_TIM6; + gptObjectInit(&GPTD6); +#endif + +#if STM32_GPT_USE_TIM7 + /* Driver initialization.*/ + GPTD7.tim = STM32_TIM7; + gptObjectInit(&GPTD7); +#endif + +#if STM32_GPT_USE_TIM8 + /* Driver initialization.*/ + GPTD8.tim = STM32_TIM8; + gptObjectInit(&GPTD8); +#endif + +#if STM32_GPT_USE_TIM9 + /* Driver initialization.*/ + GPTD9.tim = STM32_TIM9; + gptObjectInit(&GPTD9); +#endif + +#if STM32_GPT_USE_TIM11 + /* Driver initialization.*/ + GPTD11.tim = STM32_TIM11; + gptObjectInit(&GPTD11); +#endif + +#if STM32_GPT_USE_TIM12 + /* Driver initialization.*/ + GPTD12.tim = STM32_TIM12; + gptObjectInit(&GPTD12); +#endif + +#if STM32_GPT_USE_TIM14 + /* Driver initialization.*/ + GPTD14.tim = STM32_TIM14; + gptObjectInit(&GPTD14); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint16_t psc; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if STM32_GPT_USE_TIM1 + if (&GPTD1 == gptp) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(STM32_TIM1_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif +#if STM32_GPT_USE_TIM2 + if (&GPTD2 == gptp) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(STM32_TIM2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_GPT_USE_TIM3 + if (&GPTD3 == gptp) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(STM32_TIM3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_GPT_USE_TIM4 + if (&GPTD4 == gptp) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(STM32_TIM4_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM5 + if (&GPTD5 == gptp) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(STM32_TIM5_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM6 + if (&GPTD6 == gptp) { + rccEnableTIM6(FALSE); + rccResetTIM6(); + nvicEnableVector(STM32_TIM6_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM6_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM7 + if (&GPTD7 == gptp) { + rccEnableTIM7(FALSE); + rccResetTIM7(); + nvicEnableVector(STM32_TIM7_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM7_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM8 + if (&GPTD8 == gptp) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(STM32_TIM8_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif + +#if STM32_GPT_USE_TIM9 + if (&GPTD9 == gptp) { + rccEnableTIM9(FALSE); + rccResetTIM9(); + nvicEnableVector(STM32_TIM9_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM9_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif + +#if STM32_GPT_USE_TIM11 + if (&GPTD11 == gptp) { + rccEnableTIM11(FALSE); + rccResetTIM11(); + nvicEnableVector(STM32_TIM11_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM11_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif + +#if STM32_GPT_USE_TIM12 + if (&GPTD12 == gptp) { + rccEnableTIM12(FALSE); + rccResetTIM12(); + nvicEnableVector(STM32_TIM12_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM12_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM14 + if (&GPTD14 == gptp) { + rccEnableTIM14(FALSE); + rccResetTIM14(); + nvicEnableVector(STM32_TIM14_NUMBER, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM14_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + } + + /* Prescaler value calculation.*/ + psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tim->CR1 = 0; /* Initially stopped. */ + gptp->tim->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */ + gptp->tim->PSC = psc; /* Prescaler value. */ + gptp->tim->DIER = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tim->CR1 = 0; /* Timer disabled. */ + gptp->tim->DIER = 0; /* All IRQs disabled. */ + gptp->tim->SR = 0; /* Clear eventual pending IRQs. */ + +#if STM32_GPT_USE_TIM1 + if (&GPTD1 == gptp) { + nvicDisableVector(STM32_TIM1_UP_NUMBER); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_GPT_USE_TIM2 + if (&GPTD2 == gptp) { + nvicDisableVector(STM32_TIM2_NUMBER); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_GPT_USE_TIM3 + if (&GPTD3 == gptp) { + nvicDisableVector(STM32_TIM3_NUMBER); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_GPT_USE_TIM4 + if (&GPTD4 == gptp) { + nvicDisableVector(STM32_TIM4_NUMBER); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_GPT_USE_TIM5 + if (&GPTD5 == gptp) { + nvicDisableVector(STM32_TIM5_NUMBER); + rccDisableTIM5(FALSE); + } +#endif +#if STM32_GPT_USE_TIM6 + if (&GPTD6 == gptp) { + nvicDisableVector(STM32_TIM6_NUMBER); + rccDisableTIM6(FALSE); + } +#endif +#if STM32_GPT_USE_TIM7 + if (&GPTD7 == gptp) { + nvicDisableVector(STM32_TIM7_NUMBER); + rccDisableTIM7(FALSE); + } +#endif +#if STM32_GPT_USE_TIM8 + if (&GPTD8 == gptp) { + nvicDisableVector(STM32_TIM8_UP_NUMBER); + rccDisableTIM8(FALSE); + } +#endif +#if STM32_GPT_USE_TIM9 + if (&GPTD9 == gptp) { + nvicDisableVector(STM32_TIM9_NUMBER); + rccDisableTIM9(FALSE); + } +#endif +#if STM32_GPT_USE_TIM11 + if (&GPTD11 == gptp) { + nvicDisableVector(STM32_TIM11_NUMBER); + rccDisableTIM11(FALSE); + } +#endif +#if STM32_GPT_USE_TIM12 + if (&GPTD12 == gptp) { + nvicDisableVector(STM32_TIM12_NUMBER); + rccDisableTIM12(FALSE); + } +#endif +#if STM32_GPT_USE_TIM14 + if (&GPTD14 == gptp) { + nvicDisableVector(STM32_TIM14_NUMBER); + rccDisableTIM14(FALSE); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tim->ARR = interval - 1; /* Time constant. */ + gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ + gptp->tim->CNT = 0; /* Reset counter. */ + /* NOTE: After generating the UG event it takes several clock cycles before + SR bit 0 goes to 1. This is because the clearing of CNT has been inserted + before the clearing of SR, to give it some time.*/ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ + gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tim->CR1 = 0; /* Initially stopped. */ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->DIER = 0; /* Interrupts disabled. */ +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tim->ARR = interval - 1; /* Time constant. */ + gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->CR1 = TIM_CR1_OPM | TIM_CR1_URS | TIM_CR1_CEN; + while (!(gptp->tim->SR & TIM_SR_UIF)) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h new file mode 100644 index 000000000..ecb1dcb35 --- /dev/null +++ b/os/hal/platforms/STM32/gpt_lld.h @@ -0,0 +1,504 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/gpt_lld.h + * @brief STM32 GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM1 FALSE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM2 FALSE +#endif + +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM3 FALSE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM4 FALSE +#endif + +/** + * @brief GPTD5 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM5 FALSE +#endif + +/** + * @brief GPTD6 driver enable switch. + * @details If set to @p TRUE the support for GPTD6 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM6 FALSE +#endif + +/** + * @brief GPTD7 driver enable switch. + * @details If set to @p TRUE the support for GPTD7 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM7 FALSE +#endif + +/** + * @brief GPTD8 driver enable switch. + * @details If set to @p TRUE the support for GPTD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM8 FALSE +#endif + +/** + * @brief GPTD9 driver enable switch. + * @details If set to @p TRUE the support for GPTD9 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM9 FALSE +#endif + +/** + * @brief GPTD11 driver enable switch. + * @details If set to @p TRUE the support for GPTD11 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM11 FALSE +#endif + +/** + * @brief GPTD12 driver enable switch. + * @details If set to @p TRUE the support for GPTD12 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM12 FALSE +#endif + +/** + * @brief GPTD14 driver enable switch. + * @details If set to @p TRUE the support for GPTD14 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM14 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD2 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD3 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD4 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD6 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD7 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD8 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD9 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD11 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD12 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD14 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6 +#error "TIM6 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7 +#error "TIM7 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9 +#error "TIM9 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11 +#error "TIM11 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12 +#error "TIM12 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14 +#error "TIM14 not present in the selected device" +#endif + +#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \ + !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \ + !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 && \ + !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 && \ + !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \ + !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14 +#error "GPT driver activated but no TIM peripheral assigned" +#endif + +#if STM32_GPT_USE_TIM1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM1" +#endif + +#if STM32_GPT_USE_TIM2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM2" +#endif + +#if STM32_GPT_USE_TIM3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM3" +#endif + +#if STM32_GPT_USE_TIM4 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM4" +#endif + +#if STM32_GPT_USE_TIM5 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM5" +#endif + +#if STM32_GPT_USE_TIM6 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM6" +#endif + +#if STM32_GPT_USE_TIM7 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM7" +#endif + +#if STM32_GPT_USE_TIM8 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM8" +#endif + +#if STM32_GPT_USE_TIM9 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM9" +#endif + +#if STM32_GPT_USE_TIM11 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM11" +#endif + +#if STM32_GPT_USE_TIM12 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM12" +#endif + +#if STM32_GPT_USE_TIM14 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM14" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->tim->ARR = (uint16_t)((interval) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD5; +#endif + +#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__) +extern GPTDriver GPTD6; +#endif + +#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__) +extern GPTDriver GPTD7; +#endif + +#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__) +extern GPTDriver GPTD8; +#endif + +#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__) +extern GPTDriver GPTD9; +#endif + +#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__) +extern GPTDriver GPTD11; +#endif + +#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__) +extern GPTDriver GPTD12; +#endif + +#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__) +extern GPTDriver GPTD14; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/i2s_lld.c b/os/hal/platforms/STM32/i2s_lld.c new file mode 100644 index 000000000..b7eaf4b0c --- /dev/null +++ b/os/hal/platforms/STM32/i2s_lld.c @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/i2s_lld.c + * @brief I2S Driver subsystem low level driver source template. + * + * @addtogroup I2S + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2S || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2S driver initialization. + * + * @notapi + */ +void i2s_lld_init(void) { + +#if STM32_I2S_USE_I2S2 + spiObjectInit(&I2SD2); + I2SD2.spi = SPI2; +#endif + +#if STM32_I2S_USE_I2S3 + spiObjectInit(&I2SD3); + I2SD3.spi = SPI3; +#endif +} + +/** + * @brief Configures and activates the I2S peripheral. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @notapi + */ +void i2s_lld_start(I2SDriver *i2sp) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (i2sp->state == I2S_STOP) { +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dma, + STM32_I2S_I2S2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + rccEnableSPI2(FALSE); + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dma, + STM32_I2S_I2S3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + rccEnableSPI3(FALSE); + } +#endif + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the I2S peripheral. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @notapi + */ +void i2s_lld_stop(I2SDriver *i2sp) { + + if (i2sp->state == I2S_READY) { + /* Clock deactivation.*/ + + } +} + +/** + * @brief Starts a I2S data exchange. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @notapi + */ +void i2s_lld_start_exchange(I2SDriver *i2sp) { + +} + +/** + * @brief Starts a I2S data exchange in continuous mode. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @notapi + */ +void i2s_lld_start_exchange_continuous(I2SDriver *i2sp) { + +} + +/** + * @brief Stops the ongoing data exchange. + * @details The ongoing data exchange, if any, is stopped, if the driver + * was not active the function does nothing. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @notapi + */ +void i2s_lld_stop_exchange(I2SDriver *i2sp) { + +} + +#endif /* HAL_USE_I2S */ + +/** @} */ diff --git a/os/hal/platforms/STM32/i2s_lld.h b/os/hal/platforms/STM32/i2s_lld.h new file mode 100644 index 000000000..3f9c640b3 --- /dev/null +++ b/os/hal/platforms/STM32/i2s_lld.h @@ -0,0 +1,317 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/i2s_lld.h + * @brief I2S Driver subsystem low level driver header template. + * + * @addtogroup I2S + * @{ + */ + +#ifndef _I2S_LLD_H_ +#define _I2S_LLD_H_ + +#if HAL_USE_I2S || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2S2 driver enable switch. + * @details If set to @p TRUE the support for I2S2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2S_USE_I2S2) || defined(__DOXYGEN__) +#define STM32_I2S_USE_I2S2 FALSE +#endif + +/** + * @brief I2S3 driver enable switch. + * @details If set to @p TRUE the support for I2S3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2S_USE_I2S3) || defined(__DOXYGEN__) +#define STM32_I2S_USE_I2S3 FALSE +#endif + +/** + * @brief I2S2 interrupt priority level setting. + */ +#if !defined(STM32_I2S_I2S2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_I2S2_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2S3 interrupt priority level setting. + */ +#if !defined(STM32_I2S_I2S3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_I2S3_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2S2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_I2S2_DMA_PRIORITY 1 +#endif + +/** + * @brief I2S3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_I2S2_DMA_PRIORITY 1 +#endif + +/** + * @brief I2S DMA error hook. + */ +#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for I2S2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2S_I2S2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#endif + +/** + * @brief DMA stream used for I2S2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2S_I2S2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for I2S3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2S_I2S3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for I2S3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2S_I2S3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#endif /* !STM32_ADVANCED_DMA */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_I2S_USE_I2S2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_I2S_USE_I2S3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_I2S_USE_I2S2 && !STM32_I2S_USE_I2S3 +#error "I2S driver activated but no I2S peripheral assigned" +#endif + +#if STM32_I2S_USE_I2S2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) +#error "invalid DMA stream associated to I2S2 RX" +#endif + +#if STM32_I2S_USE_I2S2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) +#error "invalid DMA stream associated to I2S2 TX" +#endif + +#if STM32_I2S_USE_I2S3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) +#error "invalid DMA stream associated to I2S3 RX" +#endif + +#if STM32_I2S_USE_I2S3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) +#error "invalid DMA stream associated to I2S3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief I2S mode type. + */ +typedef uint32_t i2smode_t; + +/** + * @brief Type of a structure representing an I2S driver. + */ +typedef struct I2SDriver I2SDriver; + +/** + * @brief I2S notification callback type. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * @param[in] buffer pointer to the buffer + * @param[in] n number of sample positions starting from @p buffer + */ +typedef void (*i2scallback_t)(I2SDriver *i2sp, void *buffer, size_t n); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief I2S mode selection. + */ + i2smode_t mode; + /** + * @brief Transmission buffer pointer. + */ + const void *tx_buffer; + /** + * @brief Transmission buffer size in number of samples. + */ + size_t tx_size; + /** + * @brief Callback function associated to the transmission or @p NULL. + */ + i2scallback_t tx_cb; + /** + * @brief Receive buffer pointer. + */ + void *rx_buffer; + /** + * @brief Receive buffer size in number of samples. + */ + size_t rx_size; + /** + * @brief Callback function associated to the reception or @p NULL. + */ + i2scallback_t rx_cb;; + /* End of the mandatory fields.*/ + /** + * @brief Configuration of the I2SCFGR register. + * @details See the STM32 reference manual, this register is used for + * the I2S configuration, the following bits must not be + * specified because handled directly by the driver: + * - I2SMOD + * - I2SE + * - I2SCFG + * . + */ + int16_t i2scfgr; + /** + * @brief Configuration of the I2SPR register. + * @details See the STM32 reference manual, this register is used for + * the I2S clock setup. + */ + int16_t i2spr; +} I2SConfig; + +/** + * @brief Structure representing an I2S driver. + */ +struct I2SDriver { + /** + * @brief Driver state. + */ + i2sstate_t state; + /** + * @brief Current configuration data. + */ + const I2SConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief DMA stream. + */ + const stm32_dma_stream_t *dma; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_I2S_USE_I2S2 && !defined(__DOXYGEN__) +extern I2SDriver I2SD2; +#endif + +#if STM32_I2S_USE_I2S3 && !defined(__DOXYGEN__) +extern I2SDriver I2SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void i2s_lld_init(void); + void i2s_lld_start(I2SDriver *i2sp); + void i2s_lld_stop(I2SDriver *i2sp); + void i2s_lld_start_exchange(I2SDriver *i2sp); + void i2s_lld_start_exchange_continuous(I2SDriver *i2sp); + void i2s_lld_stop_exchange(I2SDriver *i2sp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2S */ + +#endif /* _I2S_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c new file mode 100644 index 000000000..2e3c4334b --- /dev/null +++ b/os/hal/platforms/STM32/icu_lld.c @@ -0,0 +1,639 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Fabio Utzig and + Xo Wang. + */ + +/** + * @file STM32/icu_lld.c + * @brief STM32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD1 allocates the timer TIM2 when enabled. + */ +#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD1 allocates the timer TIM3 when enabled. + */ +#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the timer TIM4 when enabled. + */ +#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the timer TIM5 when enabled. + */ +#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the timer TIM8 when enabled. + */ +#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the timer TIM9 when enabled. + */ +#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + uint16_t sr; + + sr = icup->tim->SR; + sr &= icup->tim->DIER; + icup->tim->SR = ~sr; + if (icup->config->channel == ICU_CHANNEL_1) { + if ((sr & TIM_SR_CC1IF) != 0) + _icu_isr_invoke_period_cb(icup); + if ((sr & TIM_SR_CC2IF) != 0) + _icu_isr_invoke_width_cb(icup); + } else { + if ((sr & TIM_SR_CC1IF) != 0) + _icu_isr_invoke_width_cb(icup); + if ((sr & TIM_SR_CC2IF) != 0) + _icu_isr_invoke_period_cb(icup); + } + if ((sr & TIM_SR_UIF) != 0) + _icu_isr_invoke_overflow_cb(icup); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 +#if !defined(STM32_TIM1_UP_HANDLER) +#error "STM32_TIM1_UP_HANDLER not defined" +#endif +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(STM32_TIM1_CC_HANDLER) +#error "STM32_TIM1_CC_HANDLER not defined" +#endif +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM1 */ + +#if STM32_ICU_USE_TIM2 +#if !defined(STM32_TIM2_HANDLER) +#error "STM32_TIM2_HANDLER not defined" +#endif +/** + * @brief TIM2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM2 */ + +#if STM32_ICU_USE_TIM3 +#if !defined(STM32_TIM3_HANDLER) +#error "STM32_TIM3_HANDLER not defined" +#endif +/** + * @brief TIM3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM3 */ + +#if STM32_ICU_USE_TIM4 +#if !defined(STM32_TIM4_HANDLER) +#error "STM32_TIM4_HANDLER not defined" +#endif +/** + * @brief TIM4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM4 */ + +#if STM32_ICU_USE_TIM5 +#if !defined(STM32_TIM5_HANDLER) +#error "STM32_TIM5_HANDLER not defined" +#endif +/** + * @brief TIM5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM5 */ + +#if STM32_ICU_USE_TIM8 +#if !defined(STM32_TIM8_UP_HANDLER) +#error "STM32_TIM8_UP_HANDLER not defined" +#endif +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(STM32_TIM8_CC_HANDLER) +#error "STM32_TIM8_CC_HANDLER not defined" +#endif +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM8 */ + +#if STM32_ICU_USE_TIM9 +#if !defined(STM32_TIM9_HANDLER) +#error "STM32_TIM9_HANDLER not defined" +#endif +/** + * @brief TIM9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM9 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + +#if STM32_ICU_USE_TIM1 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.tim = STM32_TIM1; +#endif + +#if STM32_ICU_USE_TIM2 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.tim = STM32_TIM2; +#endif + +#if STM32_ICU_USE_TIM3 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.tim = STM32_TIM3; +#endif + +#if STM32_ICU_USE_TIM4 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.tim = STM32_TIM4; +#endif + +#if STM32_ICU_USE_TIM5 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.tim = STM32_TIM5; +#endif + +#if STM32_ICU_USE_TIM8 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.tim = STM32_TIM8; +#endif + +#if STM32_ICU_USE_TIM9 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.tim = STM32_TIM9; +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + uint32_t psc; + + chDbgAssert((icup->config->channel == ICU_CHANNEL_1) || + (icup->config->channel == ICU_CHANNEL_2), + "icu_lld_start(), #1", "invalid input"); + + if (icup->state == ICU_STOP) { + /* Clock activation and timer reset.*/ +#if STM32_ICU_USE_TIM1 + if (&ICUD1 == icup) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(STM32_TIM1_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); + nvicEnableVector(STM32_TIM1_CC_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK2; + } +#endif +#if STM32_ICU_USE_TIM2 + if (&ICUD2 == icup) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(STM32_TIM2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM3 + if (&ICUD3 == icup) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(STM32_TIM3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM4 + if (&ICUD4 == icup) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(STM32_TIM4_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM5 + if (&ICUD5 == icup) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(STM32_TIM5_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM8 + if (&ICUD8 == icup) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(STM32_TIM8_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); + nvicEnableVector(STM32_TIM8_CC_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK2; + } +#endif +#if STM32_ICU_USE_TIM9 + if (&ICUD9 == icup) { + rccEnableTIM9(FALSE); + rccResetTIM9(); + nvicEnableVector(STM32_TIM9_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + icup->tim->CR1 = 0; /* Timer disabled. */ + icup->tim->DIER = 0; /* All IRQs disabled. */ + icup->tim->SR = 0; /* Clear eventual pending IRQs. */ + icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + icup->tim->CNT = 0; /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (icup->clock / icup->config->frequency) - 1; + chDbgAssert((psc <= 0xFFFF) && + ((psc + 1) * icup->config->frequency) == icup->clock, + "icu_lld_start(), #1", "invalid frequency"); + icup->tim->PSC = (uint16_t)psc; + icup->tim->ARR = 0xFFFF; + + if (icup->config->channel == ICU_CHANNEL_1) { + /* Selected input 1. + CCMR1_CC1S = 01 = CH1 Input on TI1. + CCMR1_CC2S = 10 = CH2 Input on TI1.*/ + icup->tim->CCMR1 = TIM_CCMR1_CC1S_0 | + TIM_CCMR1_CC2S_1; + /* SMCR_TS = 101, input is TI1FP1. + SMCR_SMS = 100, reset on rising edge.*/ + icup->tim->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | + TIM_SMCR_SMS_2; + /* The CCER settings depend on the selected trigger mode. + ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. + ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) + icup->tim->CCER = TIM_CCER_CC1E | + TIM_CCER_CC2E | TIM_CCER_CC2P; + else + icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | + TIM_CCER_CC2E; + /* Direct pointers to the capture registers in order to make reading + data faster from within callbacks.*/ + icup->wccrp = &icup->tim->CCR[1]; + icup->pccrp = &icup->tim->CCR[0]; + } else { + /* Selected input 2. + CCMR1_CC1S = 10 = CH1 Input on TI2. + CCMR1_CC2S = 01 = CH2 Input on TI2.*/ + icup->tim->CCMR1 = TIM_CCMR1_CC1S_1 | + TIM_CCMR1_CC2S_0; + /* SMCR_TS = 110, input is TI2FP2. + SMCR_SMS = 100, reset on rising edge.*/ + icup->tim->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | + TIM_SMCR_SMS_2; + /* The CCER settings depend on the selected trigger mode. + ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. + ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) + icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | + TIM_CCER_CC2E; + else + icup->tim->CCER = TIM_CCER_CC1E | + TIM_CCER_CC2E | TIM_CCER_CC2P; + /* Direct pointers to the capture registers in order to make reading + data faster from within callbacks.*/ + icup->wccrp = &icup->tim->CCR[0]; + icup->pccrp = &icup->tim->CCR[1]; + } +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Clock deactivation.*/ + icup->tim->CR1 = 0; /* Timer disabled. */ + icup->tim->DIER = 0; /* All IRQs disabled. */ + icup->tim->SR = 0; /* Clear eventual pending IRQs. */ + +#if STM32_ICU_USE_TIM1 + if (&ICUD1 == icup) { + nvicDisableVector(STM32_TIM1_UP_NUMBER); + nvicDisableVector(STM32_TIM1_CC_NUMBER); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_ICU_USE_TIM2 + if (&ICUD2 == icup) { + nvicDisableVector(STM32_TIM2_NUMBER); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_ICU_USE_TIM3 + if (&ICUD3 == icup) { + nvicDisableVector(STM32_TIM3_NUMBER); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_ICU_USE_TIM4 + if (&ICUD4 == icup) { + nvicDisableVector(STM32_TIM4_NUMBER); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_ICU_USE_TIM5 + if (&ICUD5 == icup) { + nvicDisableVector(STM32_TIM5_NUMBER); + rccDisableTIM5(FALSE); + } +#endif +#if STM32_ICU_USE_TIM8 + if (&ICUD8 == icup) { + nvicDisableVector(STM32_TIM8_UP_NUMBER); + nvicDisableVector(STM32_TIM8_CC_NUMBER); + rccDisableTIM8(FALSE); + } +#endif +#if STM32_ICU_USE_TIM9 + if (&ICUD9 == icup) { + nvicDisableVector(STM32_TIM9_NUMBER); + rccDisableTIM9(FALSE); + } +#endif + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + icup->tim->SR = 0; /* Clear pending IRQs (if any). */ + if (icup->config->channel == ICU_CHANNEL_1) { + if (icup->config->period_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC1IE; + if (icup->config->width_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC2IE; + } else { + if (icup->config->width_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC1IE; + if (icup->config->period_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC2IE; + } + if (icup->config->overflow_cb != NULL) + icup->tim->DIER |= TIM_DIER_UIE; + icup->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + icup->tim->CR1 = 0; /* Initially stopped. */ + icup->tim->SR = 0; /* Clear pending IRQs (if any). */ + icup->tim->DIER = 0; /* Interrupts disabled. */ +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h new file mode 100644 index 000000000..ee5f313f3 --- /dev/null +++ b/os/hal/platforms/STM32/icu_lld.h @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/icu_lld.h + * @brief STM32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM1 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM2 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM3 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM4 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM5 FALSE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM8 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM9 FALSE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD8 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9 +#error "TIM9 not present in the selected device" +#endif + +#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \ + !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \ + !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \ + !STM32_ICU_USE_TIM9 +#error "ICU driver activated but no TIM peripheral assigned" +#endif + +#if STM32_ICU_USE_TIM1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM1" +#endif + +#if STM32_ICU_USE_TIM2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM2" +#endif + +#if STM32_ICU_USE_TIM3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM3" +#endif + +#if STM32_ICU_USE_TIM4 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM4" +#endif + +#if STM32_ICU_USE_TIM5 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM5" +#endif + +#if STM32_ICU_USE_TIM8 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM8" +#endif + +#if STM32_ICU_USE_TIM9 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM9" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU channel type. + */ +typedef enum { + ICU_CHANNEL_1 = 0, /**< Use TIMxCH1. */ + ICU_CHANNEL_2 = 1, /**< Use TIMxCH2. */ +} icuchannel_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ + /** + * @brief Timer input channel to be used. + * @note Only inputs TIMx 1 and 2 are supported. + */ + icuchannel_t channel; +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; + /** + * @brief CCR register used for width capture. + */ + volatile uint32_t *wccrp; + /** + * @brief CCR register used for period capture. + */ + volatile uint32_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c new file mode 100644 index 000000000..c1244aa39 --- /dev/null +++ b/os/hal/platforms/STM32/mac_lld.c @@ -0,0 +1,739 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/mac_lld.c + * @brief STM32 low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) + +/* MII divider optimal value.*/ +#if (STM32_HCLK >= 150000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102 +#elif (STM32_HCLK >= 100000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62 +#elif (STM32_HCLK >= 60000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42 +#elif (STM32_HCLK >= 35000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26 +#elif (STM32_HCLK >= 20000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16 +#else +#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, + 0x37, 0x01, 0x10}; + +static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS]; +static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS]; + +static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; +static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Writes a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + */ +static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { + + ETH->MACMIIDR = value; + ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | + ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) + ; +} + +/** + * @brief Reads a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The PHY register content. + */ +static uint32_t mii_read(MACDriver *macp, uint32_t reg) { + + ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) + ; + return ETH->MACMIIDR; +} + +#if !defined(BOARD_PHY_ADDRESS) +/** + * @brief PHY address detection. + * + * @param[in] macp pointer to the @p MACDriver object + */ +static void mii_find_phy(MACDriver *macp) { + uint32_t i; + +#if STM32_MAC_PHY_TIMEOUT > 0 + halrtcnt_t start = halGetCounterValue(); + halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT); + while (halIsCounterWithin(start, timeout)) { +#endif + for (i = 0; i < 31; i++) { + macp->phyaddr = i << 11; + ETH->MACMIIDR = (i << 6) | MACMIIDR_CR; + if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && + ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { + return; + } + } +#if STM32_MAC_PHY_TIMEOUT > 0 + } +#endif + /* Wrong or defective board.*/ + chSysHalt(); +} +#endif + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void mac_lld_set_address(const uint8_t *p) { + + /* MAC address configuration, only a single address comparator is used, + hash table not used.*/ + ETH->MACA0HR = ((uint32_t)p[5] << 8) | + ((uint32_t)p[4] << 0); + ETH->MACA0LR = ((uint32_t)p[3] << 24) | + ((uint32_t)p[2] << 16) | + ((uint32_t)p[1] << 8) | + ((uint32_t)p[0] << 0); + ETH->MACA1HR = 0x0000FFFF; + ETH->MACA1LR = 0xFFFFFFFF; + ETH->MACA2HR = 0x0000FFFF; + ETH->MACA2LR = 0xFFFFFFFF; + ETH->MACA3HR = 0x0000FFFF; + ETH->MACA3LR = 0xFFFFFFFF; + ETH->MACHTHR = 0; + ETH->MACHTLR = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +CH_IRQ_HANDLER(ETH_IRQHandler) { + uint32_t dmasr; + + CH_IRQ_PROLOGUE(); + + dmasr = ETH->DMASR; + ETH->DMASR = dmasr; /* Clear status bits.*/ + + if (dmasr & ETH_DMASR_RS) { + /* Data Received.*/ + chSysLockFromIsr(); + chSemResetI(ÐD1.rdsem, 0); +#if MAC_USE_EVENTS + chEvtBroadcastI(ÐD1.rdevent); +#endif + chSysUnlockFromIsr(); + } + + if (dmasr & ETH_DMASR_TS) { + /* Data Transmitted.*/ + chSysLockFromIsr(); + chSemResetI(ÐD1.tdsem, 0); + chSysUnlockFromIsr(); + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + unsigned i; + + macObjectInit(ÐD1); + ETHD1.link_up = FALSE; + + /* Descriptor tables are initialized in chained mode, note that the first + word is not initialized here but in mac_lld_start().*/ + for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE; + rd[i].rdes2 = (uint32_t)rb[i]; + rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS]; + } + for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes1 = 0; + td[i].tdes2 = (uint32_t)tb[i]; + td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS]; + } + + /* Selection of the RMII or MII mode based on info exported by board.h.*/ +#if defined(STM32F10X_CL) +#if defined(BOARD_PHY_RMII) + AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL; +#else + AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL; +#endif +#elif defined(STM32F2XX) || defined(STM32F4XX) +#if defined(BOARD_PHY_RMII) + SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; +#else + SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; +#endif +#else +#error "unsupported STM32 platform for MAC driver" +#endif + + /* Reset of the MAC core.*/ + rccResetETH(); + + /* MAC clocks temporary activation.*/ + rccEnableETH(FALSE); + + /* PHY address setup.*/ +#if defined(BOARD_PHY_ADDRESS) + ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; +#else + mii_find_phy(ÐD1); +#endif + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + mii_write(ÐD1, MII_BMCR, BMCR_RESET); +#if defined(BOARD_PHY_RESET_DELAY) + halPolledDelay(BOARD_PHY_RESET_DELAY); +#endif + while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) + ; +#endif + +#if STM32_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be started.*/ + mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC clocks stopped again.*/ + rccDisableETH(FALSE); +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + + /* Resets the state of all descriptors.*/ + for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) + rd[i].rdes0 = STM32_RDES0_OWN; + macp->rxptr = (stm32_eth_rx_descriptor_t *)rd; + for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) + td[i].tdes0 = STM32_TDES0_TCH; + macp->txptr = (stm32_eth_tx_descriptor_t *)td; + + /* MAC clocks activation and commanded reset procedure.*/ + rccEnableETH(FALSE); + ETH->DMABMR |= ETH_DMABMR_SR; + while(ETH->DMABMR & ETH_DMABMR_SR) + ; + + /* ISR vector enabled.*/ + nvicEnableVector(ETH_IRQn, + CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY)); + +#if STM32_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power up mode.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); +#endif + + /* MAC configuration.*/ + ETH->MACFFR = 0; + ETH->MACFCR = 0; + ETH->MACVLANTR = 0; + + /* MAC address setup.*/ + if (macp->config->mac_address == NULL) + mac_lld_set_address(default_mac_address); + else + mac_lld_set_address(macp->config->mac_address); + + /* Transmitter and receiver enabled. + Note that the complete setup of the MAC is performed when the link + status is detected.*/ +#if STM32_MAC_IP_CHECKSUM_OFFLOAD + ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; +#else + ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; +#endif + + /* DMA configuration: + Descriptor chains pointers.*/ + ETH->DMARDLAR = (uint32_t)rd; + ETH->DMATDLAR = (uint32_t)td; + + /* Enabling required interrupt sources.*/ + ETH->DMASR = ETH->DMASR; + ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; + + /* DMA general settings.*/ + ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat; + + /* Transmit FIFO flush.*/ + ETH->DMAOMR = ETH_DMAOMR_FTF; + while (ETH->DMAOMR & ETH_DMAOMR_FTF) + ; + + /* DMA final configuration and start.*/ + ETH->DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF | + ETH_DMAOMR_ST | ETH_DMAOMR_SR; +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + if (macp->state != MAC_STOP) { +#if STM32_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be restarted.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC and DMA stopped.*/ + ETH->MACCR = 0; + ETH->DMAOMR = 0; + ETH->DMAIER = 0; + ETH->DMASR = ETH->DMASR; + + /* MAC clocks stopped.*/ + rccDisableETH(FALSE); + + /* ISR vector disabled.*/ + nvicDisableVector(ETH_IRQn); + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + stm32_eth_tx_descriptor_t *tdes; + + if (!macp->link_up) + return RDY_TIMEOUT; + + chSysLock(); + + /* Get Current TX descriptor.*/ + tdes = macp->txptr; + + /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by + another thread.*/ + if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) { + chSysUnlock(); + return RDY_TIMEOUT; + } + + /* Marks the current descriptor as locked using a reserved bit.*/ + tdes->tdes0 |= STM32_TDES0_LOCKED; + + /* Next TX descriptor to use.*/ + macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3; + + chSysUnlock(); + + /* Set the buffer size and configuration.*/ + tdp->offset = 0; + tdp->size = STM32_MAC_BUFFERS_SIZE; + tdp->physdesc = tdes; + + return RDY_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), + "mac_lld_release_transmit_descriptor(), #1", + "attempt to release descriptor already owned by DMA"); + + chSysLock(); + + /* Unlocks the descriptor and returns it to the DMA engine.*/ + tdp->physdesc->tdes1 = tdp->offset; + tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) | + STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | + STM32_TDES0_TCH | STM32_TDES0_OWN; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/ + } + + chSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + stm32_eth_rx_descriptor_t *rdes; + + chSysLock(); + + /* Get Current RX descriptor.*/ + rdes = macp->rxptr; + + /* Iterates through received frames until a valid one is found, invalid + frames are discarded.*/ + while (!(rdes->rdes0 & STM32_RDES0_OWN)) { + if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) +#if STM32_MAC_IP_CHECKSUM_OFFLOAD + && (rdes->rdes0 & STM32_RDES0_FT) + && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE)) +#endif + && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) { + /* Found a valid one.*/ + rdp->offset = 0; + rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4; + rdp->physdesc = rdes; + macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3; + + chSysUnlock(); + return RDY_OK; + } + /* Invalid frame found, purging.*/ + rdes->rdes0 = STM32_RDES0_OWN; + rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3; + } + + /* Next descriptor to check.*/ + macp->rxptr = rdes; + + chSysUnlock(); + return RDY_TIMEOUT; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + + chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), + "mac_lld_release_receive_descriptor(), #1", + "attempt to release descriptor already owned by DMA"); + + chSysLock(); + + /* Give buffer back to the Ethernet DMA.*/ + rdp->physdesc->rdes0 = STM32_RDES0_OWN; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/ + } + + chSysUnlock(); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + uint32_t maccr, bmsr, bmcr; + + maccr = ETH->MACCR; + + /* PHY CR and SR registers read.*/ + (void)mii_read(macp, MII_BMSR); + bmsr = mii_read(macp, MII_BMSR); + bmcr = mii_read(macp, MII_BMCR); + + /* Check on auto-negotiation mode.*/ + if (bmcr & BMCR_ANENABLE) { + uint32_t lpa; + + /* Auto-negotiation must be finished without faults and link established.*/ + if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != + (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) + return macp->link_up = FALSE; + + /* Auto-negotiation enabled, checks the LPA register.*/ + lpa = mii_read(macp, MII_LPA); + + /* Check on link speed.*/ + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + maccr |= ETH_MACCR_FES; + else + maccr &= ~ETH_MACCR_FES; + + /* Check on link mode.*/ + if (lpa & (LPA_10FULL | LPA_100FULL)) + maccr |= ETH_MACCR_DM; + else + maccr &= ~ETH_MACCR_DM; + } + else { + /* Link must be established.*/ + if (!(bmsr & BMSR_LSTATUS)) + return macp->link_up = FALSE; + + /* Check on link speed.*/ + if (bmcr & BMCR_SPEED100) + maccr |= ETH_MACCR_FES; + else + maccr &= ~ETH_MACCR_FES; + + /* Check on link mode.*/ + if (bmcr & BMCR_FULLDPLX) + maccr |= ETH_MACCR_DM; + else + maccr &= ~ETH_MACCR_DM; + } + + /* Changes the mode in the MAC.*/ + ETH->MACCR = maccr; + + /* Returns the link status.*/ + return macp->link_up = TRUE; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), + "mac_lld_write_transmit_descriptor(), #1", + "attempt to write descriptor already owned by DMA"); + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); + tdp->offset += size; + } + return size; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), + "mac_lld_read_receive_descriptor(), #1", + "attempt to read descriptor already owned by DMA"); + + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + + if (size > 0) { + memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); + rdp->offset += size; + } + return size; +} + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * Note that a returned size lower than the amount + * requested means that more buffers must be requested + * in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep) { + + if (tdp->offset == 0) { + *sizep = tdp->size; + tdp->offset = size; + return (uint8_t *)tdp->physdesc->tdes2; + } + *sizep = 0; + return NULL; +} + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep) { + + if (rdp->size > 0) { + *sizep = rdp->size; + rdp->offset = rdp->size; + rdp->size = 0; + return (uint8_t *)rdp->physdesc->rdes2; + } + *sizep = 0; + return NULL; +} +#endif /* MAC_USE_ZERO_COPY */ + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h new file mode 100644 index 000000000..bde7e0345 --- /dev/null +++ b/os/hal/platforms/STM32/mac_lld.h @@ -0,0 +1,362 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/mac_lld.h + * @brief STM32 low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY TRUE + +/** + * @name RDES0 constants + * @{ + */ +#define STM32_RDES0_OWN 0x80000000 +#define STM32_RDES0_AFM 0x40000000 +#define STM32_RDES0_FL_MASK 0x3FFF0000 +#define STM32_RDES0_ES 0x00008000 +#define STM32_RDES0_DESERR 0x00004000 +#define STM32_RDES0_SAF 0x00002000 +#define STM32_RDES0_LE 0x00001000 +#define STM32_RDES0_OE 0x00000800 +#define STM32_RDES0_VLAN 0x00000400 +#define STM32_RDES0_FS 0x00000200 +#define STM32_RDES0_LS 0x00000100 +#define STM32_RDES0_IPHCE 0x00000080 +#define STM32_RDES0_LCO 0x00000040 +#define STM32_RDES0_FT 0x00000020 +#define STM32_RDES0_RWT 0x00000010 +#define STM32_RDES0_RE 0x00000008 +#define STM32_RDES0_DE 0x00000004 +#define STM32_RDES0_CE 0x00000002 +#define STM32_RDES0_PCE 0x00000001 +/** @} */ + +/** + * @name RDES1 constants + * @{ + */ +#define STM32_RDES1_DIC 0x80000000 +#define STM32_RDES1_RBS2_MASK 0x1FFF0000 +#define STM32_RDES1_RER 0x00008000 +#define STM32_RDES1_RCH 0x00004000 +#define STM32_RDES1_RBS1_MASK 0x00001FFF +/** @} */ + +/** + * @name TDES0 constants + * @{ + */ +#define STM32_TDES0_OWN 0x80000000 +#define STM32_TDES0_IC 0x40000000 +#define STM32_TDES0_LS 0x20000000 +#define STM32_TDES0_FS 0x10000000 +#define STM32_TDES0_DC 0x08000000 +#define STM32_TDES0_DP 0x04000000 +#define STM32_TDES0_TTSE 0x02000000 +#define STM32_TDES0_LOCKED 0x01000000 /* NOTE: Pseudo flag. */ +#define STM32_TDES0_CIC_MASK 0x00C00000 +#define STM32_TDES0_CIC(n) ((n) << 22) +#define STM32_TDES0_TER 0x00200000 +#define STM32_TDES0_TCH 0x00100000 +#define STM32_TDES0_TTSS 0x00020000 +#define STM32_TDES0_IHE 0x00010000 +#define STM32_TDES0_ES 0x00008000 +#define STM32_TDES0_JT 0x00004000 +#define STM32_TDES0_FF 0x00002000 +#define STM32_TDES0_IPE 0x00001000 +#define STM32_TDES0_LCA 0x00000800 +#define STM32_TDES0_NC 0x00000400 +#define STM32_TDES0_LCO 0x00000200 +#define STM32_TDES0_EC 0x00000100 +#define STM32_TDES0_VF 0x00000080 +#define STM32_TDES0_CC_MASK 0x00000078 +#define STM32_TDES0_ED 0x00000004 +#define STM32_TDES0_UF 0x00000002 +#define STM32_TDES0_DB 0x00000001 +/** @} */ + +/** + * @name TDES1 constants + * @{ + */ +#define STM32_TDES1_TBS2_MASK 0x1FFF0000 +#define STM32_TDES1_TBS1_MASK 0x00001FFF +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Number of available transmit buffers. + */ +#if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define STM32_MAC_RECEIVE_BUFFERS 4 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define STM32_MAC_BUFFERS_SIZE 1522 +#endif + +/** + * @brief PHY detection timeout. + * @details Timeout, in milliseconds, for PHY address detection, if a PHY + * is not detected within the timeout then the driver halts during + * initialization. This setting applies only if the PHY address is + * not explicitly set in the board header file using + * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a + * single search path is performed. + */ +#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) +#define STM32_MAC_PHY_TIMEOUT 100 +#endif + +/** + * @brief Change the PHY power state inside the driver. + */ +#if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#endif + +/** + * @brief ETHD1 interrupt priority level setting. + */ +#if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#endif + +/** + * @brief IP checksum offload. + * @details The following modes are available: + * - 0 Function disabled. + * - 1 Only IP header checksum calculation and insertion are enabled. + * - 2 IP header checksum and payload checksum calculation and + * insertion are enabled, but pseudo-header checksum is not + * calculated in hardware. + * - 3 IP Header checksum and payload checksum calculation and + * insertion are enabled, and pseudo-header checksum is + * calculated in hardware. + * . + */ +#if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM32_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS +#error "STM32_MAC_PHY_TIMEOUT requires the realtime counter service" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an STM32 Ethernet receive descriptor. + */ +typedef struct { + volatile uint32_t rdes0; + volatile uint32_t rdes1; + volatile uint32_t rdes2; + volatile uint32_t rdes3; +} stm32_eth_rx_descriptor_t; + +/** + * @brief Type of an STM32 Ethernet transmit descriptor. + */ +typedef struct { + volatile uint32_t tdes0; + volatile uint32_t tdes1; + volatile uint32_t tdes2; + volatile uint32_t tdes3; +} stm32_eth_tx_descriptor_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool_t link_up; + /** + * @brief PHY address (pre shifted). + */ + uint32_t phyaddr; + /** + * @brief Receive next frame pointer. + */ + stm32_eth_rx_descriptor_t *rxptr; + /** + * @brief Transmit next frame pointer. + */ + stm32_eth_tx_descriptor_t *txptr; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + stm32_eth_tx_descriptor_t *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + stm32_eth_rx_descriptor_t *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c new file mode 100644 index 000000000..1e9e0adfb --- /dev/null +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -0,0 +1,710 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/pwm_lld.c + * @brief STM32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TIM2 when enabled. + */ +#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TIM3 when enabled. + */ +#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TIM4 when enabled. + */ +#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the timer TIM5 when enabled. + */ +#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD8 driver identifier. + * @note The driver PWMD8 allocates the timer TIM8 when enabled. + */ +#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__) +PWMDriver PWMD8; +#endif + +/** + * @brief PWMD9 driver identifier. + * @note The driver PWMD9 allocates the timer TIM9 when enabled. + */ +#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) +PWMDriver PWMD9; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \ + STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM8 || STM32_PWM_USE_TIM9 || \ + defined(__DOXYGEN__) +/** + * @brief Common TIM2...TIM5 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint16_t sr; + + sr = pwmp->tim->SR; + sr &= pwmp->tim->DIER; + pwmp->tim->SR = ~sr; + if ((sr & TIM_SR_CC1IF) != 0) + pwmp->config->channels[0].callback(pwmp); + if ((sr & TIM_SR_CC2IF) != 0) + pwmp->config->channels[1].callback(pwmp); + if ((sr & TIM_SR_CC3IF) != 0) + pwmp->config->channels[2].callback(pwmp); + if ((sr & TIM_SR_CC4IF) != 0) + pwmp->config->channels[3].callback(pwmp); + if ((sr & TIM_SR_UIF) != 0) + pwmp->config->callback(pwmp); +} +#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 +#if !defined(STM32_TIM1_UP_HANDLER) +#error "STM32_TIM1_UP_HANDLER not defined" +#endif +/** + * @brief TIM1 update interrupt handler. + * @note It is assumed that this interrupt is only activated if the callback + * pointer is not equal to @p NULL in order to not perform an extra + * check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + STM32_TIM1->SR = ~TIM_SR_UIF; + PWMD1.config->callback(&PWMD1); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(STM32_TIM1_CC_HANDLER) +#error "STM32_TIM1_CC_HANDLER not defined" +#endif +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { + uint16_t sr; + + CH_IRQ_PROLOGUE(); + + sr = STM32_TIM1->SR & STM32_TIM1->DIER; + STM32_TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | + TIM_SR_CC3IF | TIM_SR_CC4IF); + if ((sr & TIM_SR_CC1IF) != 0) + PWMD1.config->channels[0].callback(&PWMD1); + if ((sr & TIM_SR_CC2IF) != 0) + PWMD1.config->channels[1].callback(&PWMD1); + if ((sr & TIM_SR_CC3IF) != 0) + PWMD1.config->channels[2].callback(&PWMD1); + if ((sr & TIM_SR_CC4IF) != 0) + PWMD1.config->channels[3].callback(&PWMD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM1 */ + +#if STM32_PWM_USE_TIM2 +#if !defined(STM32_TIM2_HANDLER) +#error "STM32_TIM2_HANDLER not defined" +#endif +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM2 */ + +#if STM32_PWM_USE_TIM3 +#if !defined(STM32_TIM3_HANDLER) +#error "STM32_TIM3_HANDLER not defined" +#endif +/** + * @brief TIM3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM3 */ + +#if STM32_PWM_USE_TIM4 +#if !defined(STM32_TIM4_HANDLER) +#error "STM32_TIM4_HANDLER not defined" +#endif +/** + * @brief TIM4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM4 */ + +#if STM32_PWM_USE_TIM5 +#if !defined(STM32_TIM5_HANDLER) +#error "STM32_TIM5_HANDLER not defined" +#endif +/** + * @brief TIM5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM5 */ + +#if STM32_PWM_USE_TIM8 +#if !defined(STM32_TIM8_UP_HANDLER) +#error "STM32_TIM8_UP_HANDLER not defined" +#endif +/** + * @brief TIM8 update interrupt handler. + * @note It is assumed that this interrupt is only activated if the callback + * pointer is not equal to @p NULL in order to not perform an extra + * check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { + + CH_IRQ_PROLOGUE(); + + STM32_TIM8->SR = ~TIM_SR_UIF; + PWMD8.config->callback(&PWMD8); + + CH_IRQ_EPILOGUE(); +} + +#if !defined(STM32_TIM8_CC_HANDLER) +#error "STM32_TIM8_CC_HANDLER not defined" +#endif +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { + uint16_t sr; + + CH_IRQ_PROLOGUE(); + + sr = STM32_TIM8->SR & STM32_TIM8->DIER; + STM32_TIM8->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | + TIM_SR_CC3IF | TIM_SR_CC4IF); + if ((sr & TIM_SR_CC1IF) != 0) + PWMD8.config->channels[0].callback(&PWMD8); + if ((sr & TIM_SR_CC2IF) != 0) + PWMD8.config->channels[1].callback(&PWMD8); + if ((sr & TIM_SR_CC3IF) != 0) + PWMD8.config->channels[2].callback(&PWMD8); + if ((sr & TIM_SR_CC4IF) != 0) + PWMD8.config->channels[3].callback(&PWMD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM8 */ + +#if STM32_PWM_USE_TIM9 +#if !defined(STM32_TIM9_HANDLER) +#error "STM32_TIM9_HANDLER not defined" +#endif +/** + * @brief TIM9 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM9 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if STM32_PWM_USE_TIM1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.tim = STM32_TIM1; +#endif + +#if STM32_PWM_USE_TIM2 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.tim = STM32_TIM2; +#endif + +#if STM32_PWM_USE_TIM3 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.tim = STM32_TIM3; +#endif + +#if STM32_PWM_USE_TIM4 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.tim = STM32_TIM4; +#endif + +#if STM32_PWM_USE_TIM5 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.tim = STM32_TIM5; +#endif + +#if STM32_PWM_USE_TIM8 + /* Driver initialization.*/ + pwmObjectInit(&PWMD8); + PWMD8.tim = STM32_TIM8; +#endif + +#if STM32_PWM_USE_TIM9 + /* Driver initialization.*/ + pwmObjectInit(&PWMD9); + PWMD9.tim = STM32_TIM9; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t psc; + uint16_t ccer; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if STM32_PWM_USE_TIM1 + if (&PWMD1 == pwmp) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(STM32_TIM1_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); + nvicEnableVector(STM32_TIM1_CC_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK2; + } +#endif +#if STM32_PWM_USE_TIM2 + if (&PWMD2 == pwmp) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(STM32_TIM2_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM3 + if (&PWMD3 == pwmp) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(STM32_TIM3_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM4 + if (&PWMD4 == pwmp) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(STM32_TIM4_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_PWM_USE_TIM5 + if (&PWMD5 == pwmp) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(STM32_TIM5_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(STM32_TIM8_UP_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); + nvicEnableVector(STM32_TIM8_CC_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK2; + } +#endif +#if STM32_PWM_USE_TIM9 + if (&PWMD9 == pwmp) { + rccEnableTIM9(FALSE); + rccResetTIM9(); + nvicEnableVector(STM32_TIM9_NUMBER, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM9_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif + + /* All channels configured in PWM1 mode with preload enabled and will + stay that way until the driver is stopped.*/ + pwmp->tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | + TIM_CCMR1_OC1PE | + TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | + TIM_CCMR1_OC2PE; + pwmp->tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 | + TIM_CCMR2_OC3PE | + TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | + TIM_CCMR2_OC4PE; + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->tim->CR1 = 0; /* Timer disabled. */ + pwmp->tim->DIER = 0; /* All IRQs disabled. */ + pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ + pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ + pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ + pwmp->tim->CNT = 0; /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (pwmp->clock / pwmp->config->frequency) - 1; + chDbgAssert((psc <= 0xFFFF) && + ((psc + 1) * pwmp->config->frequency) == pwmp->clock, + "pwm_lld_start(), #1", "invalid frequency"); + pwmp->tim->PSC = (uint16_t)psc; + pwmp->tim->ARR = (uint16_t)(pwmp->period - 1); + pwmp->tim->CR2 = pwmp->config->cr2; + + /* Output enables and polarities setup.*/ + ccer = 0; + switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC1P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC1E; + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC2P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC2E; + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC3P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC3E; + default: + ; + } + switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC4P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC4E; + default: + ; + } +#if STM32_PWM_USE_ADVANCED +#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 + if (&PWMD1 == pwmp) { +#endif +#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { +#endif +#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 + if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) { +#endif + switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC1NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC1NE; + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC2NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC2NE; + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC3NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC3NE; + default: + ; + } + } +#endif /* STM32_PWM_USE_ADVANCED*/ + + pwmp->tim->CCER = ccer; + pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */ + pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE; + pwmp->tim->SR = 0; /* Clear pending IRQs. */ +#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 +#if STM32_PWM_USE_ADVANCED + pwmp->tim->BDTR = pwmp->config->bdtr | TIM_BDTR_MOE; +#else + pwmp->tim->BDTR = TIM_BDTR_MOE; +#endif +#endif + /* Timer configured and started.*/ + pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->tim->CR1 = 0; /* Timer disabled. */ + pwmp->tim->DIER = 0; /* All IRQs disabled. */ + pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ +#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 + pwmp->tim->BDTR = 0; +#endif + +#if STM32_PWM_USE_TIM1 + if (&PWMD1 == pwmp) { + nvicDisableVector(STM32_TIM1_UP_NUMBER); + nvicDisableVector(STM32_TIM1_CC_NUMBER); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_PWM_USE_TIM2 + if (&PWMD2 == pwmp) { + nvicDisableVector(STM32_TIM2_NUMBER); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_PWM_USE_TIM3 + if (&PWMD3 == pwmp) { + nvicDisableVector(STM32_TIM3_NUMBER); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_PWM_USE_TIM4 + if (&PWMD4 == pwmp) { + nvicDisableVector(STM32_TIM4_NUMBER); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_PWM_USE_TIM5 + if (&PWMD5 == pwmp) { + nvicDisableVector(STM32_TIM5_NUMBER); + rccDisableTIM5(FALSE); + } +#endif +#if STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { + nvicDisableVector(STM32_TIM8_UP_NUMBER); + nvicDisableVector(STM32_TIM8_CC_NUMBER); + rccDisableTIM8(FALSE); + } +#endif +#if STM32_PWM_USE_TIM9 + if (&PWMD9 == pwmp) { + nvicDisableVector(STM32_TIM9_NUMBER); + rccDisableTIM9(FALSE); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + pwmp->tim->CCR[channel] = width; /* New duty cycle. */ + /* If there is a callback defined for the channel then the associated + interrupt must be enabled.*/ + if (pwmp->config->channels[channel].callback != NULL) { + uint32_t dier = pwmp->tim->DIER; + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((dier & (2 << channel)) == 0) { + pwmp->tim->DIER = dier | (2 << channel); + pwmp->tim->SR = ~(2 << channel); + } + } +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + pwmp->tim->CCR[channel] = 0; + pwmp->tim->DIER &= ~(2 << channel); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h new file mode 100644 index 000000000..57fc17c29 --- /dev/null +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -0,0 +1,472 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/pwm_lld.h + * @brief STM32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 4 + +/** + * @brief Complementary output modes mask. + * @note This is an STM32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an STM32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an STM32-specific setting. + * @note This setting is only available if the configuration option + * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced + * timers TIM1 and TIM8. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an STM32-specific setting. + * @note This setting is only available if the configuration option + * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced + * timers TIM1 and TIM8. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief If advanced timer features switch. + * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are + * enabled. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__) +#define STM32_PWM_USE_ADVANCED FALSE +#endif + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM1 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM2 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM3 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM4 FALSE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM5 FALSE +#endif + +/** + * @brief PWMD8 driver enable switch. + * @details If set to @p TRUE the support for PWMD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM8 FALSE +#endif + +/** + * @brief PWMD9 driver enable switch. + * @details If set to @p TRUE the support for PWMD9 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM9) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM9 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD8 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#endif +/** @} */ + +/** + * @brief PWMD9 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM9 && !STM32_HAS_TIM9 +#error "TIM9 not present in the selected device" +#endif + +#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \ + !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \ + !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 && \ + !STM32_PWM_USE_TIM8 +#error "PWM driver activated but no TIM peripheral assigned" +#endif + +#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 +#error "advanced mode selected but no advanced timer assigned" +#endif + +#if STM32_PWM_USE_TIM1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM1" +#endif + +#if STM32_PWM_USE_TIM2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM2" +#endif + +#if STM32_PWM_USE_TIM3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM3" +#endif + +#if STM32_PWM_USE_TIM4 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM4" +#endif + +#if STM32_PWM_USE_TIM5 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM5" +#endif + +#if STM32_PWM_USE_TIM8 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM8" +#endif + +#if STM32_PWM_USE_TIM9 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM9" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief TIM CR2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint16_t cr2; +#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__) + /** + * @brief TIM BDTR (break & dead-time) register initialization data. + * @note The value of this field should normally be equal to zero. + */ \ + uint16_t bdtr; +#endif +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) + +/** + * @brief Returns a PWM channel status. + * @pre The PWM unit must have been activated using @p pwmStart(). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +#define pwm_lld_is_channel_enabled(pwmp, channel) \ + (((pwmp)->tim->CCR[channel] != 0) || \ + (((pwmp)->tim->DIER & (2 << channel)) != 0)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__) +extern PWMDriver PWMD8; +#endif + +#if STM32_PWM_USE_TIM9 && !defined(__DOXYGEN__) +extern PWMDriver PWMD9; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c new file mode 100644 index 000000000..69873d5f0 --- /dev/null +++ b/os/hal/platforms/STM32/sdc_lld.c @@ -0,0 +1,788 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/sdc_lld.c + * @brief STM32 SDC subsystem low level driver source. + * + * @addtogroup SDC + * @{ + */ + +/* + TODO: Try preerase blocks before writing (ACMD23). + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM, \ + STM32_SDC_SDIO_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SDCD1 driver identifier.*/ +SDCDriver SDCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if STM32_SDC_SDIO_UNALIGNED_SUPPORT +/** + * @brief Buffer for temporary storage during unaligned transfers. + */ +static union { + uint32_t alignment; + uint8_t buf[MMCSD_BLOCK_SIZE]; +} u; +#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Prepares card to handle read transaction. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[in] n number of blocks to read + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk, + uint32_t n, uint32_t *resp) { + + /* Driver handles data in 512 bytes blocks (just like HC cards). But if we + have not HC card than we must convert address from blocks to bytes.*/ + if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) + startblk *= MMCSD_BLOCK_SIZE; + + if (n > 1) { + /* Send read multiple blocks command to card.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) + return CH_FAILED; + } + else{ + /* Send read single block command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) + return CH_FAILED; + } + + return CH_SUCCESS; +} + +/** + * @brief Prepares card to handle write transaction. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[in] n number of blocks to write + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk, + uint32_t n, uint32_t *resp) { + + /* Driver handles data in 512 bytes blocks (just like HC cards). But if we + have not HC card than we must convert address from blocks to bytes.*/ + if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) + startblk *= MMCSD_BLOCK_SIZE; + + if (n > 1) { + /* Write multiple blocks command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) + return CH_FAILED; + } + else{ + /* Write single block command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) + return CH_FAILED; + } + + return CH_SUCCESS; +} + +/** + * @brief Wait end of data transaction and performs finalizations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] n number of blocks in transaction + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + */ +static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, + uint32_t *resp) { + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_start_data_transaction(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_start_data_transaction(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + return CH_FAILED; + } + +#if (defined(STM32F4XX) || defined(STM32F2XX)) + /* Wait until DMA channel enabled to be sure that all data transferred.*/ + while (sdcp->dma->stream->CR & STM32_DMA_CR_EN) + ; + + /* DMA event flags must be manually cleared.*/ + dmaStreamClearInterrupt(sdcp->dma); + + SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; + SDIO->DCTRL = 0; + chSysUnlock(); + + /* Wait until interrupt flags to be cleared.*/ + /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF) + dmaStreamClearInterrupt(sdcp->dma);*/ +#else + /* Waits for transfer completion at DMA level, the the stream is + disabled and cleared.*/ + dmaWaitCompletion(sdcp->dma); + + SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; + SDIO->DCTRL = 0; + chSysUnlock(); +#endif + + /* Finalize transaction.*/ + if (n > 1) + return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); + + return CH_SUCCESS; +} + +/** + * @brief Gets SDC errors. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] sta value of the STA register + * + * @notapi + */ +static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) { + uint32_t errors = SDC_NO_ERROR; + + if (sta & SDIO_STA_CCRCFAIL) + errors |= SDC_CMD_CRC_ERROR; + if (sta & SDIO_STA_DCRCFAIL) + errors |= SDC_DATA_CRC_ERROR; + if (sta & SDIO_STA_CTIMEOUT) + errors |= SDC_COMMAND_TIMEOUT; + if (sta & SDIO_STA_DTIMEOUT) + errors |= SDC_DATA_TIMEOUT; + if (sta & SDIO_STA_TXUNDERR) + errors |= SDC_TX_UNDERRUN; + if (sta & SDIO_STA_RXOVERR) + errors |= SDC_RX_OVERRUN; + if (sta & SDIO_STA_STBITERR) + errors |= SDC_STARTBIT_ERROR; + + sdcp->errors |= errors; +} + +/** + * @brief Performs clean transaction stopping in case of errors. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] n number of blocks in transaction + * @param[in] resp pointer to the response buffer + * + * @notapi + */ +static void sdc_lld_error_cleanup(SDCDriver *sdcp, + uint32_t n, + uint32_t *resp) { + uint32_t sta = SDIO->STA; + + dmaStreamClearInterrupt(sdcp->dma); + dmaStreamDisable(sdcp->dma); + SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + sdc_lld_collect_errors(sdcp, sta); + if (n > 1) + sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_SDIO_HANDLER) +#error "STM32_SDIO_HANDLER not defined" +#endif +/** + * @brief SDIO IRQ handler. + * @details It just wakes transaction thread. All error handling performs in + * that thread. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_SDIO_HANDLER) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr() + + /* Disables the source but the status flags are not reset because the + read/write functions needs to check them.*/ + SDIO->MASK = 0; + + if (SDCD1.thread != NULL) { + chSchReadyI(SDCD1.thread); + SDCD1.thread = NULL; + } + + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); + SDCD1.thread = NULL; + SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM); +#if CH_DBG_ENABLE_ASSERTS + SDCD1.sdio = SDIO; +#endif +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | + STM32_DMA_CR_MINC; + +#if (defined(STM32F4XX) || defined(STM32F2XX)) + sdcp->dmamode |= STM32_DMA_CR_PFCTRL | + STM32_DMA_CR_PBURST_INCR4 | + STM32_DMA_CR_MBURST_INCR4; +#endif + + if (sdcp->state == BLK_STOP) { + /* Note, the DMA must be enabled before the IRQs.*/ + bool_t b; + b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL); + chDbgAssert(!b, "sdc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO); +#if (defined(STM32F4XX) || defined(STM32F2XX)) + dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); +#endif + nvicEnableVector(STM32_SDIO_NUMBER, + CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); + rccEnableSDIO(FALSE); + } + + /* Configuration, card clock is initially stopped.*/ + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = 0; +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if (sdcp->state != BLK_STOP) { + + /* SDIO deactivation.*/ + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = 0; + + /* Clock deactivation.*/ + nvicDisableVector(STM32_SDIO_NUMBER); + dmaStreamRelease(sdcp->dma); + rccDisableSDIO(FALSE); + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + (void)sdcp; + + /* Initial clock setting: 400kHz, 1bit mode.*/ + SDIO->CLKCR = STM32_SDIO_DIV_LS; + SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; + SDIO->CLKCR |= SDIO_CLKCR_CLKEN; +} + +/** + * @brief Sets the SDIO clock to data mode (25MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp) { + + (void)sdcp; + + SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + (void)sdcp; + + SDIO->CLKCR = 0; + SDIO->POWER = 0; +} + +/** + * @brief Switches the bus to 4 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; + + (void)sdcp; + + switch (mode) { + case SDC_MODE_1BIT: + SDIO->CLKCR = clk; + break; + case SDC_MODE_4BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; + break; + case SDC_MODE_8BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; + break; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + (void)sdcp; + + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; + while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDSENTC; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = sta; + if ((sta & (SDIO_STA_CTIMEOUT)) != 0) { + sdc_lld_collect_errors(sdcp, sta); + return CH_FAILED; + } + *resp = SDIO->RESP1; + return CH_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = sta; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) { + sdc_lld_collect_errors(sdcp, sta); + return CH_FAILED; + } + *resp = SDIO->RESP1; + return CH_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | + SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = sta; + if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) { + sdc_lld_collect_errors(sdcp, sta); + return CH_FAILED; + } + /* Save bytes in reverse order because MSB in response comes first.*/ + *resp++ = SDIO->RESP4; + *resp++ = SDIO->RESP3; + *resp++ = SDIO->RESP2; + *resp = SDIO->RESP1; + return CH_SUCCESS; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size"); + + SDIO->DTIMER = STM32_SDC_READ_TIMEOUT; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return CH_FAILED; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(sdcp->dma, buf); + dmaStreamSetTransactionSize(sdcp->dma, + (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); + dmaStreamEnable(sdcp->dma); + + /* Setting up data transfer.*/ + SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | + SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_STBITERRIE | + SDIO_MASK_RXOVERRIE | + SDIO_MASK_DATAENDIE; + SDIO->DLEN = n * MMCSD_BLOCK_SIZE; + + /* Talk to card what we want from it.*/ + if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE) + goto error; + + /* Transaction starts just after DTEN bit setting.*/ + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | + SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE) + goto error; + + return CH_SUCCESS; + +error: + sdc_lld_error_cleanup(sdcp, n, resp); + return CH_FAILED; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size"); + + SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return CH_FAILED; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(sdcp->dma, buf); + dmaStreamSetTransactionSize(sdcp->dma, + (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P); + dmaStreamEnable(sdcp->dma); + + /* Setting up data transfer.*/ + SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | + SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_STBITERRIE | + SDIO_MASK_TXUNDERRIE | + SDIO_MASK_DATAENDIE; + SDIO->DLEN = n * MMCSD_BLOCK_SIZE; + + /* Talk to card what we want from it.*/ + if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE) + goto error; + + /* Transaction starts just after DTEN bit setting.*/ + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | + SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE) + goto error; + + return CH_SUCCESS; + +error: + sdc_lld_error_cleanup(sdcp, n, resp); + return CH_FAILED; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + +#if STM32_SDC_SDIO_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1)) + return CH_FAILED; + memcpy(buf, u.buf, MMCSD_BLOCK_SIZE); + buf += MMCSD_BLOCK_SIZE; + startblk++; + } + return CH_SUCCESS; + } +#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ + return sdc_lld_read_aligned(sdcp, startblk, buf, n); +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + +#if STM32_SDC_SDIO_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + memcpy(u.buf, buf, MMCSD_BLOCK_SIZE); + buf += MMCSD_BLOCK_SIZE; + if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1)) + return CH_FAILED; + startblk++; + } + return CH_SUCCESS; + } +#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ + return sdc_lld_write_aligned(sdcp, startblk, buf, n); +} + +/** + * @brief Waits for card idle condition. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t sdc_lld_sync(SDCDriver *sdcp) { + + /* TODO: Implement.*/ + (void)sdcp; + return CH_SUCCESS; +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h new file mode 100644 index 000000000..8b01ba915 --- /dev/null +++ b/os/hal/platforms/STM32/sdc_lld.h @@ -0,0 +1,310 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/sdc_lld.h + * @brief STM32 SDC subsystem low level driver header. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_LLD_H_ +#define _SDC_LLD_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Value to clear all interrupts flag at once. + */ +#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | \ + SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC | \ + SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | \ + SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | \ + SDIO_ICR_DATAENDC | SDIO_ICR_STBITERRC | \ + SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | \ + SDIO_ICR_CEATAENDC) + +/** + * @brief Mask of error flags in STA register. + */ +#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | \ + SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT | \ + SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SDIO DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#endif + +/** + * @brief SDIO interrupt priority level setting. + */ +#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_WRITE_TIMEOUT_MS 250 +#endif + +/** + * @brief Read timeout in milliseconds. + */ +#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_READ_TIMEOUT_MS 5 +#endif + +/** + * @brief Support for unaligned transfers. + * @note Unaligned transfers are much slower. + */ +#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for SDC operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SDC_SDIO_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#endif + +#else /* !STM32_ADVANCED_DMA*/ +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_HAS_SDIO +#error "SDIO not present in the selected device" +#endif + +#if !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDIO" +#endif + +#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDIO_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDIO" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* + * SDIO clock divider. + */ +#if (defined(STM32F4XX) || defined(STM32F2XX)) +#define STM32_SDIO_DIV_HS 0 +#define STM32_SDIO_DIV_LS 120 + +#elif STM32_HCLK > 48000000 +#define STM32_SDIO_DIV_HS 1 +#define STM32_SDIO_DIV_LS 178 +#else + +#define STM32_SDIO_DIV_HS 0 +#define STM32_SDIO_DIV_LS 118 +#endif + +/** + * @brief SDIO data timeouts in SDIO clock cycles. + */ +#if (defined(STM32F4XX) || defined(STM32F2XX)) +#if !STM32_CLOCK48_REQUIRED +#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled" +#endif + +#define STM32_SDC_WRITE_TIMEOUT \ + (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS) +#define STM32_SDC_READ_TIMEOUT \ + (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS) + +#else +#define STM32_SDC_WRITE_TIMEOUT \ + (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS) +#define STM32_SDC_READ_TIMEOUT \ + (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of SDIO bus mode. + */ +typedef enum { + SDC_MODE_1BIT = 0, + SDC_MODE_4BIT, + SDC_MODE_8BIT +} sdcbusmode_t; + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief SDC Driver condition flags type. + */ +typedef uint32_t sdcflags_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} SDCConfig; + +/** + * @brief @p SDCDriver specific methods. + */ +#define _sdc_driver_methods \ + _mmcsd_block_device_methods + +/** + * @extends MMCSDBlockDeviceVMT + * + * @brief @p SDCDriver virtual methods table. + */ +struct SDCDriverVMT { + _sdc_driver_methods +}; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Virtual Methods Table. + */ + const struct SDCDriverVMT *vmt; + _mmcsd_block_device_data + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Errors flags. + */ + sdcflags_t errors; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion IRQ. + */ + Thread *thread; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Pointer to the SDIO registers block. + * @note Used only for dubugging purpose. + */ +#if CH_DBG_ENABLE_ASSERTS + SDIO_TypeDef *sdio; +#endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n); + bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n); + bool_t sdc_lld_sync(SDCDriver *sdcp); + bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h new file mode 100644 index 000000000..b56f769b5 --- /dev/null +++ b/os/hal/platforms/STM32/stm32.h @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/stm32.h + * @brief STM32 common header. + * @pre One of the following macros must be defined before including + * this header, the macro selects the inclusion of the appropriate + * vendor header: + * - STM32F0XX for Entry Level devices. + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XL for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. + * - STM32F2XX for High-performance STM32 F-2 devices. + * - STM32F30X for Analog & DSP devices. + * - STM32F37X for Analog & DSP devices. + * - STM32F4XX for High-performance STM32 F-4 devices. + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_H_ +#define _STM32_H_ + +#if defined(STM32F0XX) +#include "stm32f0xx.h" + +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ + defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) || \ + defined(__DOXYGEN__) +#include "stm32f10x.h" + +#elif defined(STM32F2XX) +#include "stm32f2xx.h" + +#elif defined(STM32F30X) +#include "stm32f30x.h" + +#elif defined(STM32F37X) +#include "stm32f37x.h" + +#elif defined(STM32F4XX) +#include "stm32f4xx.h" + +#elif defined(STM32L1XX_MD) +#include "stm32l1xx.h" + +#else +#error "STM32 device not specified" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 TIM registers block. + * @note Redefined from the ST headers because the non uniform + * declaration of the CCR registers among the various + * sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} stm32_tim_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name TIM units references + * @{ + */ +#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) +#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) +#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) +#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) +#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) +#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) +#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) +#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) +#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) +#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) +#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) +#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) +#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) +#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c new file mode 100644 index 000000000..5fa419679 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/adc_lld.c @@ -0,0 +1,298 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/adc_lld.c + * @brief STM32F0xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Stops an ongoing conversion, if any. + * + * @param[in] adc pointer to the ADC registers block + */ +static void adc_lld_stop_adc(ADC_TypeDef *adc) { + + if (adc->CR & ADC_CR_ADSTART) { + adc->CR |= ADC_CR_ADSTP; + while (adc->CR & ADC_CR_ADSTP) + ; + } +} + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector70) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = ADC1->ISR; + ADC1->ISR = isr; + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (ADCD1.grpp != NULL) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((isr & ADC_ISR_OVR) && + (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + if (isr & ADC_ISR_AWD) { + /* Analog watchdog error.*/ + _adc_isr_error_code(&ADCD1, ADC_ERR_AWD); + } + } + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC1_COMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); + + /* Calibration procedure.*/ + rccEnableADC1(FALSE); + chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state"); + ADC1->CR |= ADC_CR_ADCAL; + while (ADC1->CR & ADC_CR_ADCAL) + ; + rccDisableADC1(FALSE); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); +#if STM32_ADCSW == STM32_ADCSW_HSI14 + /* Clock from HSI14, no need for jitter removal.*/ + ADC1->CFGR2 = 0x00001000; +#else +#if STM32_ADCPRE == STM32_ADCPRE_DIV2 + ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2; +#else + ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4; +#endif +#endif + } +#endif /* STM32_ADC_USE_ADC1 */ + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR = ADC_CR_ADEN; + while (!(adcp->adc->ISR & ADC_ISR_ADRDY)) + ; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock and analog part.*/ + if (adcp->state == ADC_READY) { + + dmaStreamRelease(adcp->dmastp); + + /* Disabling ADC.*/ + if (adcp->adc->CR & ADC_CR_ADEN) { + adc_lld_stop_adc(adcp->adc); + adcp->adc->CR |= ADC_CR_ADDIS; + while (adcp->adc->CR & ADC_CR_ADDIS) + ; + } + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup, if it is defined a callback for the analog watch dog then it + is enabled.*/ + adcp->adc->ISR = adcp->adc->ISR; + adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE; + adcp->adc->TR = grpp->tr; + adcp->adc->SMPR = grpp->smpr; + adcp->adc->CHSELR = grpp->chselr; + + /* ADC configuration and start.*/ + adcp->adc->CFGR1 = grpp->cfgr1 | ADC_CFGR1_CONT | ADC_CFGR1_DMACFG | + ADC_CFGR1_DMAEN; + adcp->adc->CR |= ADC_CR_ADSTART; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adc_lld_stop_adc(adcp->adc); +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h new file mode 100644 index 000000000..411e31581 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/adc_lld.h @@ -0,0 +1,333 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/adc_lld.h + * @brief STM32F0xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */ +#define ADC_SMPR_SMP_7P5 1 /**< @brief 21 cycles conversion time. */ +#define ADC_SMPR_SMP_13P5 2 /**< @brief 28 cycles conversion time. */ +#define ADC_SMPR_SMP_28P5 3 /**< @brief 41 cycles conversion time. */ +#define ADC_SMPR_SMP_41P5 4 /**< @brief 54 cycles conversion time. */ +#define ADC_SMPR_SMP_55P5 5 /**< @brief 68 cycles conversion time. */ +#define ADC_SMPR_SMP_71P5 6 /**< @brief 84 cycles conversion time. */ +#define ADC_SMPR_SMP_239P5 7 /**< @brief 252 cycles conversion time. */ +/** @} */ + +/** + * @name Resolution + * @{ + */ +#define ADC_CFGR1_RES_12BIT (0 << 3) +#define ADC_CFGR1_RES_10BIT (1 << 3) +#define ADC_CFGR1_RES_8BIT (2 << 3) +#define ADC_CFGR1_RES_6BIT (3 << 3) +/** @} */ + +/** + * @name Threashold register initializer + * @{ + */ +#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low)) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 2 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CFGR1 register initialization data. + */ + uint32_t cfgr1; + /** + * @brief ADC TR register initialization data. + */ + uint32_t tr; + /** + * @brief ADC SMPR register initialization data. + */ + uint32_t smpr; + /** + * @brief ADC CHSELR register initialization data. + * @details The number of bits at logic level one in this register must + * be equal to the number in the @p num_channels field. + */ + uint32_t chselr; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the value of the ADC CCR register. + * @details Use this function in order to enable or disable the internal + * analog sources. See the documentation in the STM32F0xx Reference + * Manual. + */ +#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c new file mode 100644 index 000000000..afccfdd8c --- /dev/null +++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/ext_lld_isr.c + * @brief STM32F0xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0]...EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector54) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 0) | (1 << 1)); + EXTI->PR = pr; + if (pr & (1 << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + if (pr & (1 << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2]...EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector58) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 2) | (1 << 3)); + EXTI->PR = pr; + if (pr & (1 << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + if (pr & (1 << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | + (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | + (1 << 14) | (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(Vector44) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(Vector48) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_15_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_1_IRQn); + nvicDisableVector(EXTI2_3_IRQn); + nvicDisableVector(EXTI4_15_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/platforms/STM32F0xx/ext_lld_isr.h new file mode 100644 index 000000000..9885fbc65 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.h @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/ext_lld_isr.h + * @brief STM32F0xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0..1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2..3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI4..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c new file mode 100644 index 000000000..debc51ea3 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/hal_lld.c + * @brief STM32F0xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(~RCC_APB2RSTR_DBGMCURST); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON; +#endif + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_HSE14_ENABLED + /* HSI14 activation.*/ + RCC->CR2 |= RCC_CR2_HSI14ON; + while (!(RCC->CR2 & RCC_CR2_HSI14RDY)) + ; /* Waits until HSI14 is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Clock settings.*/ + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + RCC->CFGR2 = STM32_PREDIV; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | + STM32_USART1SW; + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +#endif /* !STM32_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h new file mode 100644 index 000000000..dcff57a5c --- /dev/null +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -0,0 +1,780 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/hal_lld.h + * @brief STM32F0xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - STM32F0XX for Entry Level devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" +#include "stm32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F05x Entry Level" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 48000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 25000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 48000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB clock frequency. + */ +#define STM32_PCLK_MAX 48000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 8000000 /**< High speed internal clock. */ +#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/ +#define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PCLK divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PCLK divided by 4. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as + RTC clock. */ +/** @} */ + +/** + * @name RCC_CFGR3 register bits definitions + * @{ + */ +#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */ +#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */ +#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */ +#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */ +#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */ +#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */ +#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */ +#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */ +#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */ +#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */ +#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */ +#define STM32_ADCSW_MASK (1 << 8) /**< ADC clock source mask. */ +#define STM32_ADCSW_HSI14 (0 << 8) /**< ADC clock is HSI14. */ +#define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSI14 clock source. + */ +#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI14_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 48MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 48MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV_VALUE 1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 48MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 6 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 48MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE) || defined(__DOXYGEN__) +#define STM32_PPRE STM32_PPRE_DIV1 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief ADC clock source. + */ +#if !defined(STM32_ADCSW) || defined(__DOXYGEN__) +#define STM32_ADCSW STM32_ADCSW_HSI14 +#endif + +/** + * @brief CEC clock source. + */ +#if !defined(STM32_CECSW) || defined(__DOXYGEN__) +#define STM32_CECSW STM32_CECSW_HSI +#endif + +/** + * @brief I2C1 clock source. + */ +#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__) +#define STM32_I2C1SW STM32_I2C1SW_HSI +#endif + +/** + * @brief USART1 clock source. + */ +#if !defined(STM32_USART1SW) || defined(__DOXYGEN__) +#define STM32_USART1SW STM32_USART1SW_PCLK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F0xx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if STM32_CECSW == STM32_CECSW_HSI +#error "HSI not enabled, required by STM32_CECSW" +#endif + +#if STM32_I2C1SW == STM32_I2C1SW_HSI +#error "HSI not enabled, required by STM32_I2C1SW" +#endif + +#if STM32_USART1SW == STM32_USART1SW_HSI +#error "HSI not enabled, required by STM32_USART1SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSI14 related checks. + */ +#if STM32_HSI14_ENABLED +#else /* !STM32_HSI14_ENABLED */ + +#if STM32_MCOSEL == STM32_MCOSEL_HSI14 +#error "HSI14 not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_ADCSW == STM32_ADCSW_HSI14 +#error "HSI14 not enabled, required by STM32_ADCSW" +#endif + +#endif /* !STM32_HSI14_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + +#if STM32_CECSW == STM32_CECSW_LSE +#error "LSE not enabled, required by STM32_CECSW" +#endif + +#if STM32_USART1SW == STM32_USART1SW_LSE +#error "LSE not enabled, required by STM32_USART1SW" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) +#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB frequency. + */ +#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK (STM32_HCLK / 1) +#elif STM32_PPRE == STM32_PPRE_DIV2 +#define STM32_PCLK (STM32_HCLK / 2) +#elif STM32_PPRE == STM32_PPRE_DIV4 +#define STM32_PCLK (STM32_HCLK / 4) +#elif STM32_PPRE == STM32_PPRE_DIV8 +#define STM32_PCLK (STM32_HCLK / 8) +#elif STM32_PPRE == STM32_PPRE_DIV16 +#define STM32_PCLK (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE value specified" +#endif + +/* APB frequency check.*/ +#if STM32_PCLK > STM32_PCLK_MAX +#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 32) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if STM32_ADCSW == STM32_ADCSW_HSI14 +#define STM32_ADCCLK STM32_HSI14CLK +#elif STM32_ADCSW == STM32_ADCSW_PCLK +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK / 4) +#else +#error "invalid STM32_ADCPRE value specified" +#endif +#else +#error "invalid source selected for ADC clock" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief CEC frequency. + */ +#if STM32_CECSW == STM32_CECSW_HSI +#define STM32_CECCLK STM32_HSICLK +#elif STM32_CECSW == STM32_CECSW_LSE +#define STM32_CECCLK STM32_LSECLK +#else +#error "invalid source selected for CEC clock" +#endif + +/** + * @brief I2C1 frequency. + */ +#if STM32_I2CSW == STM32_I2C1SW_HSI +#define STM32_I2C1CLK STM32_HSICLK +#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK +#define STM32_I2C1CLK STM32_SYSCLK +#else +#error "invalid source selected for I2C1 clock" +#endif + +/** + * @brief USART1 frequency. + */ +#if STM32_USART1SW == STM32_USART1SW_PCLK +#define STM32_USART1CLK STM32_PCLK +#elif STM32_USART1SW == STM32_USART1SW_SYSCLK +#define STM32_USART1CLK STM32_SYSCLK +#elif STM32_USART1SW == STM32_USART1SW_LSECLK +#define STM32_USART1CLK STM32_LSECLK +#elif STM32_USART1SW == STM32_USART1SW_HSICLK +#define STM32_USART1CLK STM32_HSICLK +#else +#error "invalid source selected for USART1 clock" +#endif + +/** + * @brief USART2 frequency. + */ +#define STM32_USART2CLK STM32_PCLK + +/** + * @brief Timers clock. + */ +#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK * 1) +#define STM32_TIMCLK2 (STM32_PCLK * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK * 2) +#define STM32_TIMCLK2 (STM32_PCLK * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#else +#define STM32_FLASHBITS 0x00000011 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/platform.dox b/os/hal/platforms/STM32F0xx/platform.dox new file mode 100644 index 000000000..c8caa2b89 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/platform.dox @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers + * @details This section describes all the supported drivers on the STM32F0xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F0xx_HAL STM32F0xx Initialization Support + * @details The STM32F0xx HAL support is responsible for system initialization. + * + * @section stm32f0xx_hal_1 Supported HW resources + * - PLL1. + * - RCC. + * - Flash. + * . + * @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_ADC STM32F0xx ADC Support + * @details The STM32F0xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f0xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA errors detection. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_EXT STM32F0xx EXT Support + * @details The STM32F0xx EXT driver uses the EXTI peripheral. + * + * @section stm32f0xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_GPT STM32F0xx GPT Support + * @details The STM32F0xx GPT driver uses the TIMx peripherals. + * + * @section stm32f0xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * . + * @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_ICU STM32F0xx ICU Support + * @details The STM32F0xx ICU driver uses the TIMx peripherals. + * + * @section stm32f0xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * . + * @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_PAL STM32F0xx PAL Support + * @details The STM32F0xx PAL driver uses the GPIO peripherals. + * + * @section stm32f0xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOF. + * . + * @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f0xx_pal_3 Supported PAL setup modes + * The STM32F0xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f0xx_pal_4 Suboptimal behavior + * The STM32F0xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_PWM STM32F0xx PWM Support + * @details The STM32F0xx PWM driver uses the TIMx peripherals. + * + * @section stm32f0xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * . + * @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support + * @details The STM32F0xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f0xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * . + * @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_SPI STM32F0xx SPI Support + * @details The SPI driver supports the STM32F0xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f0xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - DMA1. + * . + * @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_UART STM32F0xx UART Support + * @details The UART driver supports the STM32F0xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f0xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - DMA1. + * . + * @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F0xx_DRIVERS + */ + +/** + * @defgroup STM32F0xx_DMA STM32F0xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f0xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F0xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F0xx_ISR STM32F0xx ISR Support + * @details This ISR helper driver is used by the other drivers in order to + * map ISR names to physical vector names. + * + * @ingroup STM32F0xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F0xx_RCC STM32F0xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f0xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F0xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk new file mode 100644 index 000000000..c04d85c76 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/platform.mk @@ -0,0 +1,22 @@ +# List of all the STM32F0xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c new file mode 100644 index 000000000..2305d952d --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_dma.c @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32F0xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn} +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector64) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 streams 2 and 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector68) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 2.*/ + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + } + + /* Check on channel 3.*/ + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + } + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 streams 4 and 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector6C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + } + + /* Check on channel 5.*/ + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h new file mode 100644 index 000000000..277ebf4d4 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_dma.h @@ -0,0 +1,394 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f0xx.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32F0xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 5 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR_EN +#define STM32_DMA_CR_TEIE DMA_CCR_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR_CIRC +#define STM32_DMA_CR_PINC DMA_CCR_PINC +#define STM32_DMA_CR_MINC DMA_CCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h new file mode 100644 index 000000000..52421a4d5 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_isr.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32F0xx_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ + +/* + * I2C units. + */ +#define STM32_I2C1_GLOBAL_HANDLER Vector9C +#define STM32_I2C1_GLOBAL_NUMBER 23 + +#define STM32_I2C2_GLOBAL_HANDLER VectorA0 +#define STM32_I2C2_GLOBAL_NUMBER 24 + +/* + * TIM units. + */ +#define STM32_TIM1_UP_HANDLER Vector74 +#define STM32_TIM1_CC_HANDLER Vector78 +#define STM32_TIM2_HANDLER Vector7C +#define STM32_TIM3_HANDLER Vector80 + +#define STM32_TIM1_UP_NUMBER 13 +#define STM32_TIM1_CC_NUMBER 14 +#define STM32_TIM2_NUMBER 15 +#define STM32_TIM3_NUMBER 16 + +/* + * USART units. + */ +#define STM32_USART1_HANDLER VectorAC +#define STM32_USART2_HANDLER VectorB0 + +#define STM32_USART1_NUMBER 27 +#define STM32_USART2_NUMBER 28 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h new file mode 100644 index 000000000..88e47f2c0 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -0,0 +1,596 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f0xx.h. + * + * @addtogroup STM32F0xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name DMA peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA1() +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Disables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Resets the CRC peripheral. + * + * @api + */ +#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST) + +/** + * @brief Enables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Disables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Resets the WWDG peripheral. + * + * @api + */ +#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/stm32_registry.h b/os/hal/platforms/STM32F0xx/stm32_registry.h new file mode 100644 index 000000000..ccef92730 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_registry.h @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_registry.h + * @brief STM32F0xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_REGISTRY_H_ +#define _STM32_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F0xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_ADC2_DMA_MSK 0x00000000 +#define STM32_ADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC3 FALSE +#define STM32_ADC3_DMA_MSK 0x00000000 +#define STM32_ADC3_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC4 FALSE +#define STM32_ADC4_DMA_MSK 0x00000000 +#define STM32_ADC4_DMA_CHN 0x00000000 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 28 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +#endif /* _STM32_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h new file mode 100644 index 000000000..b041e5e12 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h @@ -0,0 +1,3221 @@ +/** + ****************************************************************************** + * @file stm32f0xx.h + * @author MCD Application Team + * @version V1.0.1 + * @date 20-April-2012 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0XX_H +#define __STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32F0 device used in your + application + */ + +#if !defined (STM32F0XX) + #define STM32F0XX /*!< STM32F0XX: STM32F0xx devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + STM32F0xx devices are: + - STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes. + - STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes. + */ + +#if !defined (STM32F0XX) + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif /* STM32F0XX */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F0xx Standard Peripheral Library version number V1.0.1 + */ +#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F0XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TS_IRQn = 8, /*!< TS Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_IRQn = 30 /*!< CEC Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" +/* CHIBIOS FIX */ +/*#include "system_stm32f0xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ +} COMP_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ +} CRC_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + uint32_t RESERVED[6]; /*!< Reserved, 0x14 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + uint32_t RESERVED1; /*!< Reserved, 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!CR1 = 0; + ADC1->CR2 = ADC_CR2_ADON; + + /* Reset calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + + /* Return the ADC in low power mode.*/ + ADC1->CR2 = 0; + rccDisableADC1(FALSE); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif + + /* ADC setup, the calibration procedure has already been performed + during initialization.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR1 = 0; + ADC1->CR2 = 0; + dmaStreamRelease(adcp->dmastp); + rccDisableADC1(FALSE); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, n, cr2; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; + } + else + n = (uint32_t)grpp->num_channels; + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, n); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0) + cr2 |= ADC_CR2_CONT; + adcp->adc->CR2 = grpp->cr2 | cr2; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC start by writing ADC_CR2_ADON a second time.*/ + adcp->adc->CR2 = cr2; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR2 = 0; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h new file mode 100644 index 000000000..a4966d99d --- /dev/null +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -0,0 +1,393 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/adc_lld.h + * @brief STM32F1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...17. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/ext_lld_isr.c b/os/hal/platforms/STM32F1xx/ext_lld_isr.c new file mode 100644 index 000000000..ee4236c9b --- /dev/null +++ b/os/hal/platforms/STM32F1xx/ext_lld_isr.c @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/ext_lld_isr.c + * @brief STM32F1xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI0_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(PVD_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) + +#else /* Other STM32F1xx devices.*/ +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); +#if defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicEnableVector(USB_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); +#if defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicDisableVector(USB_FS_WKUP_IRQn); +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/ext_lld_isr.h b/os/hal/platforms/STM32F1xx/ext_lld_isr.h new file mode 100644 index 000000000..1114acf49 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/ext_lld_isr.h @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/ext_lld_isr.h + * @brief STM32F1xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c new file mode 100644 index 000000000..eb87a1a84 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -0,0 +1,302 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/hal_lld.c + * @brief STM32F1xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + +#if HAL_USE_RTC + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif /* STM32_LSE_ENABLED */ + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* Prescaler value loaded in registers.*/ + rtc_lld_set_prescaler(); + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +#endif /* HAL_USE_RTC */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR and BD clocks enabled.*/ + rccEnablePWRInterface(FALSE); + rccEnableBKPInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ + defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) +/* + * Clocks initialization for all sub-families except CL. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEBYP; +#endif + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_USB + RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#else + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif + +#if !STM32_HSI_ENABLED + RCC->CR &= ~RCC_CR_HSION; +#endif +#endif /* !STM32_NO_INIT */ +} + +#elif defined(STM32F10X_CL) +/* + * Clocks initialization for the CL sub-family. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CFGR = 0; + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Wait until HSI is the source.*/ + +#if STM32_HSE_ENABLED +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEBYP; +#endif + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Settings of various dividers and multipliers in CFGR2.*/ + RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | + STM32_PREDIV1 | STM32_PREDIV1SRC; + + /* PLL2 setup, if activated.*/ +#if STM32_ACTIVATE_PLL2 + RCC->CR |= RCC_CR_PLL2ON; + while (!(RCC->CR & RCC_CR_PLL2RDY)) + ; /* Waits until PLL2 is stable. */ +#endif + + /* PLL3 setup, if activated.*/ +#if STM32_ACTIVATE_PLL3 + RCC->CR |= RCC_CR_PLL3ON; + while (!(RCC->CR & RCC_CR_PLL3RDY)) + ; /* Waits until PLL3 is stable. */ +#endif + + /* PLL1 setup, if activated.*/ +#if STM32_ACTIVATE_PLL1 + RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL1 is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_OTG1 + RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#else + RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif + +#if !STM32_HSI_ENABLED + RCC->CR &= ~RCC_CR_HSION; +#endif +#endif /* !STM32_NO_INIT */ +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h new file mode 100644 index 000000000..969f96474 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -0,0 +1,255 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/hal_lld.h + * @brief STM32F1xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XL for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 8000000 /**< High speed internal clock. */ +#define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F1xx capabilities + * @{ + */ +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(__DOXYGEN__) +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32" +/** @} */ + +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) +#include "hal_lld_f100.h" + +#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) +#include "hal_lld_f103.h" + +#elif defined(STM32F10X_CL) || defined(__DOXYGEN__) +#include "hal_lld_f105_f107.h" + +#else +#error "unspecified, unsupported or invalid STM32 platform" +#endif + +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#if defined(STM32F10X_XL) +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + +#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h new file mode 100644 index 000000000..ce5b591f4 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -0,0 +1,951 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F100_HAL STM32F100 HAL Support + * @details HAL support for STM32 Value Line LD, MD and HD sub-families. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f100.h + * @brief STM32F100 Value Line HAL subsystem low level driver header. + * + * @addtogroup STM32F100_HAL + * @{ + */ + +#ifndef _HAL_LLD_F100_H_ +#define _HAL_LLD_F100_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F100 Value Line" + +#elif defined(STM32F10X_LD_VL) +#define PLATFORM_NAME "STM32F100 Value Line Low Density" + +#elif defined(STM32F10X_MD_VL) +#define PLATFORM_NAME "STM32F100 Value Line Medium Density" +#else +#error "unsupported STM32 Value Line member" +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 24000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 24000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 24000000 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 24000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 24000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 24000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 12000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ +#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 LD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 18 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 FALSE +#define STM32_I2C2_RX_DMA_MSK 0 +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK 0 +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD_VL) */ + +#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD_VL) */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#endif +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#endif +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#endif +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define USART3_IRQHandler VectorDC /**< USART3. */ +#endif +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define CEC_IRQHandler VectorE8 /**< CEC. */ +#define TIM12_IRQHandler VectorEC /**< TIM12. */ +#define TIM13_IRQHandler VectorF0 /**< TIM13. */ +#define TIM14_IRQHandler VectorF4 /**< TIM14. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 24MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 3 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 24MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV2 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F100_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSELSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ + (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) +#error "invalid STM32_PLLXTPRE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) +#else +#define STM32_PLLCLKIN (STM32_HSECLK / 2) +#endif +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F100_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h new file mode 100644 index 000000000..813970305 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -0,0 +1,1304 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F103_HAL STM32F103 HAL Support + * @details HAL support for STM32 Performance Line LD, MD and HD sub-families. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f103.h + * @brief STM32F103 Performance Line HAL subsystem low level driver header. + * + * @addtogroup STM32F103_HAL + * @{ + */ + +#ifndef _HAL_LLD_F103_H_ +#define _HAL_LLD_F103_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F10x Performance Line" + +#elif defined(STM32F10X_LD) +#define PLATFORM_NAME "STM32F10x Performance Line Low Density" + +#elif defined(STM32F10X_MD) +#define PLATFORM_NAME "STM32F10x Performance Line Medium Density" + +#elif defined(STM32F10X_HD) +#define PLATFORM_NAME "STM32F10x Performance Line High Density" + +#elif defined(STM32F10X_XL) +#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density" + +#else +#error "unsupported STM32 Performance Line member" +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 25000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 25000000 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 72000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ +#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ + +#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ +#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD) || defined(__DOXYGEN__) +/** + * @name STM32F103 LD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 FALSE +#define STM32_I2C2_RX_DMA_MSK 0 +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK 0 +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD) */ + +#if defined(STM32F10X_MD) || defined(__DOXYGEN__) +/** + * @name STM32F103 MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD) */ + +#if defined(STM32F10X_HD) || defined(__DOXYGEN__) +/** + * @name STM32F103 HD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_HD) */ + +#if defined(STM32F10X_XL) || defined(__DOXYGEN__) +/** + * @name STM32F103 XL capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_XL) */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define ADC3_IRQHandler VectorFC /**< ADC3. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief USB prescaler initialization. + */ +#if !defined(STM32_USBPRE) || defined(__DOXYGEN__) +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F103_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if STM32_USB_CLOCK_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ + (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) +#error "invalid STM32_PLLXTPRE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) +#else +#define STM32_PLLCLKIN (STM32_HSECLK / 2) +#endif +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief USB frequency. + */ +#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__) +#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3) +#elif (STM32_USBPRE == STM32_USBPRE_DIV1) +#define STM32_USBCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_USBPRE value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F103_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h new file mode 100644 index 000000000..4daa5df52 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -0,0 +1,1047 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support + * @details HAL support for STM32 Connectivity Line sub-family. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f105_f107.h + * @brief STM32F10x Connectivity Line HAL subsystem low level driver header. + * + * @addtogroup STM32F10X_CL_HAL + * @{ + */ + +#ifndef _HAL_LLD_F105_F107_H_ +#define _HAL_LLD_F105_F107_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F10x Connectivity Line" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 50000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLL1IN_MAX 12000000 + +/** + * @brief Maximum PLL1 input clock frequency. + */ +#define STM32_PLL1IN_MIN 3000000 + +/** + * @brief Maximum PLL1 input clock frequency. + */ +#define STM32_PLL23IN_MAX 5000000 + +/** + * @brief Maximum PLL2 and PLL3 input clock frequency. + */ +#define STM32_PLL23IN_MIN 3000000 + +/** + * @brief Maximum PLL1 VCO clock frequency. + */ +#define STM32_PLL1VCO_MAX 144000000 + +/** + * @brief Maximum PLL1 VCO clock frequency. + */ +#define STM32_PLL1VCO_MIN 36000000 + +/** + * @brief Maximum PLL2 and PLL3 VCO clock frequency. + */ +#define STM32_PLL23VCO_MAX 148000000 + +/** + * @brief Maximum PLL2 and PLL3 VCO clock frequency. + */ +#define STM32_PLL23VCO_MIN 80000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 18000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is + PREDIV1. */ + +#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */ +#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +#define STM32_MCOSEL_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */ +#define STM32_MCOSEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */ +#define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ +#define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ +#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ +#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F105/F107 CL capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 20 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI + line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ +#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#endif + +/** + * @brief PREDIV1 clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__) +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_HSE +#endif + +/** + * @brief PREDIV1 division factor. + * @note The allowed range is 1...16. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV1_VALUE 5 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 4...9. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief PREDIV2 division factor. + * @note The allowed range is 1...16. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV2_VALUE 5 +#endif + +/** + * @brief PLL2 multiplier value. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL2MUL_VALUE 8 +#endif + +/** + * @brief PLL3 multiplier value. + * @note The default value is calculated for a 50MHz clock from + * a 25MHz crystal. + */ +#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3MUL_VALUE 10 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_OTG_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_OTG_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief OTG prescaler initialization. + */ +#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__) +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#endif + +/** + * @brief Dedicated I2S clock setting. + */ +#if !defined(STM32_I2S_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_I2S_CLOCK_REQUIRED FALSE +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F107_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F107_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_XT1) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL1 activation conditions.*/ +#if STM32_OTG_CLOCK_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL1 activation flag. + */ +#define STM32_ACTIVATE_PLL1 TRUE +#else +#define STM32_ACTIVATE_PLL1 FALSE +#endif + +/* PLL2 activation conditions.*/ +#if STM32_OTG_CLOCK_REQUIRED || \ + (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL2 activation flag. + */ +#define STM32_ACTIVATE_PLL2 TRUE +#else +#define STM32_ACTIVATE_PLL2 FALSE +#endif + +/* PLL3 activation conditions.*/ +#if STM32_I2S_CLOCK_REQUIRED || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3) || \ + defined(__DOXYGEN__) +/** + * @brief PLL3 activation flag. + */ +#define STM32_ACTIVATE_PLL3 TRUE +#else +#define STM32_ACTIVATE_PLL3 FALSE +#endif + +/** + * @brief PREDIV1 field. + */ +#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) || \ + defined(__DOXYGEN__) +#define STM32_PREDIV1 ((STM32_PREDIV1_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV1_VALUE value specified" +#endif + +/** + * @brief PREDIV2 field. + */ +#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) || \ + defined(__DOXYGEN__) +#define STM32_PREDIV2 ((STM32_PREDIV2_VALUE - 1) << 4) +#else +#error "invalid STM32_PREDIV2_VALUE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL2MUL field. + */ +#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) || \ + defined(__DOXYGEN__) +#define STM32_PLL2MUL ((STM32_PLL2MUL_VALUE - 2) << 8) +#elif (STM32_PLL2MUL_VALUE == 16) +#define STM32_PLL2MUL (14 << 8) +#elif (STM32_PLL2MUL_VALUE == 20) +#define STM32_PLL2MUL (15 << 8) +#else +#error "invalid STM32_PLL2MUL_VALUE value specified" +#endif + +/** + * @brief PLL3MUL field. + */ +#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3MUL ((STM32_PLL3MUL_VALUE - 2) << 12) +#elif (STM32_PLL3MUL_VALUE == 16) +#define STM32_PLL3MUL (14 << 12) +#elif (STM32_PLL3MUL_VALUE == 20) +#define STM32_PLL3MUL (15 << 12) +#else +#error "invalid STM32_PLL3MUL_VALUE value specified" +#endif + +/** + * @brief PLL2 input frequency. + */ +#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) + +/* PLL2 input frequency range check.*/ +#if (STM32_PLL2CLKIN < STM32_PLL23IN_MIN) || \ + (STM32_PLL2CLKIN > STM32_PLL23IN_MAX) +#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" +#endif + +/** + * @brief PLL2 output clock frequency. + */ +#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE) + +/** + * @brief PLL2 VCO clock frequency. + */ +#define STM32_PLL2VCO (STM32_PLL2CLKOUT * 2) + +/* PLL2 output frequency range check.*/ +#if (STM32_PLL2VCO < STM32_PLL23VCO_MIN) || \ + (STM32_PLL2VCO > STM32_PLL23VCO_MAX) +#error "STM32_PLL2VCO outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" +#endif + +/** + * @brief PLL3 input frequency. + */ +#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) + +/* PLL3 input frequency range check.*/ +#if (STM32_PLL3CLKIN < STM32_PLL23IN_MIN) || \ + (STM32_PLL3CLKIN > STM32_PLL23IN_MAX) +#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" +#endif + +/** + * @brief PLL3 output clock frequency. + */ +#define STM32_PLL3CLKOUT (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE) + +/** + * @brief PLL3 VCO clock frequency. + */ +#define STM32_PLL3VCO (STM32_PLL3CLKOUT * 2) + +/* PLL3 output frequency range check.*/ +#if (STM32_PLL3VCO < STM32_PLL23VCO_MIN) || \ + (STM32_PLL3VCO > STM32_PLL23VCO_MAX) +#error "STM32_PLL3CLKOUT outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" +#endif + +/** + * @brief PREDIV1 input frequency. + */ +#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) || defined(__DOXYGEN__) +#define STM32_PREDIV1CLK STM32_HSECLK +#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1CLK STM32_PLL2CLKOUT +#else +#error "invalid STM32_PREDIV1SRC value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLL1IN_MIN) || (STM32_PLLCLKIN > STM32_PLL1IN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/** + * @brief PLL VCO clock frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKOUT * 2) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < STM32_PLL1VCO_MIN) || (STM32_PLLVCO > STM32_PLL1VCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief OTG frequency. + */ +#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) +#define STM32_OTGFSCLK (STM32_PLLVCO / 3) +#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) +#define STM32_OTGFSCLK (STM32_PLLVCO / 2) +#else +#error "invalid STM32_OTGFSPRE value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F105_F107_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox new file mode 100644 index 000000000..ecbe2d4e0 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -0,0 +1,398 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers + * @details This section describes all the supported drivers on the STM32F1xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support + * @details The STM32F1xx HAL support is responsible for system initialization. + * + * @section stm32f1xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2 (where present). + * - RCC. + * - Flash. + * . + * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features + * - PLLs startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_ADC STM32F1xx ADC Support + * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA errors detection. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_CAN STM32F1xx CAN Support + * @details The STM32F1xx CAN driver uses the CAN peripherals. + * + * @section stm32f1xx_can_1 Supported HW resources + * - bxCAN1. + * . + * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Support for bxCAN sleep mode. + * - Programmable bxCAN interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_EXT STM32F1xx EXT Support + * @details The STM32F1xx EXT driver uses the EXTI peripheral. + * + * @section stm32f1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_GPT STM32F1xx GPT Support + * @details The STM32F1xx GPT driver uses the TIMx peripherals. + * + * @section stm32f1xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_I2C STM32F1xx I2C Support + * @details The STM32F1xx I2C driver uses the I2Cx peripherals. + * + * @section stm32f1xx_i2c_1 Supported HW resources + * - I2C1. + * - I2C2. + * . + * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features + * - Each I2C port can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable I2Cx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_ICU STM32F1xx ICU Support + * @details The STM32F1xx ICU driver uses the TIMx peripherals. + * + * @section stm32f1xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_MAC STM32F1xx MAC Support + * @details The STM32 MAC driver supports the ETH peripheral. + * + * @section at91sam7_mac_1 Supported HW resources + * - ETH. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PAL STM32F1xx PAL Support + * @details The STM32F1xx PAL driver uses the GPIO peripherals. + * + * @section stm32f1xx_pal_1 Supported HW resources + * - AFIO. + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE (where present). + * - GPIOF (where present). + * - GPIOG (where present). + * . + * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f1xx_pal_3 Supported PAL setup modes + * The STM32F1xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard). + * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f1xx_pal_4 Suboptimal behavior + * The STM32F1xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * - Writing on pads/groups/ports programmed as input with pull-up/down + * resistor can change the resistor setting because the output latch is + * used for resistor selection. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PWM STM32F1xx PWM Support + * @details The STM32F1xx PWM driver uses the TIMx peripherals. + * + * @section stm32f1xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_RTC STM32F1xx RTC Support + * @details The STM32F1xx RTC driver uses the RTC peripheral. + * + * @section stm32f1xx_rtc_1 Supported HW resources + * - RTC. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SDC STM32F1xx SDC Support + * @details The STM32F1xx SDC driver uses the SDIO peripheral. + * + * @section stm32f1xx_sdc_1 Supported HW resources + * - SDIO. + * - DMA2. + * . + * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support + * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f1xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - UART5 (where present). + * . + * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SPI STM32F1xx SPI Support + * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_UART STM32F1xx UART Support + * @details The UART driver supports the STM32F1xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_USB STM32F1xx USB Support + * @details The USB driver supports the STM32F1xx USB peripheral. + * + * @section stm32f1xx_usb_1 Supported HW resources + * The USB driver can support any of the following hardware resources: + * - USB. + * . + * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority levels. + * - Each endpoint programmable in Control, Bulk and Interrupt modes. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_DMA STM32F1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F1xx_ISR STM32F1xx ISR Support + * @details This ISR helper driver is used by the other drivers in order to + * map ISR names to physical vector names. + * + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F1xx_RCC STM32F1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk new file mode 100644 index 000000000..a1959cf34 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -0,0 +1,30 @@ +# List of all the STM32F1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 + diff --git a/os/hal/platforms/STM32F1xx/platform_f105_f107.mk b/os/hal/platforms/STM32F1xx/platform_f105_f107.mk new file mode 100644 index 000000000..5778a63eb --- /dev/null +++ b/os/hal/platforms/STM32F1xx/platform_f105_f107.mk @@ -0,0 +1,29 @@ +# List of all the STM32F1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c new file mode 100644 index 000000000..5f94f3392 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_dma.c @@ -0,0 +1,492 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32F1xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) + {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, + {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, + {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, +#else /* !STM32F10X_CL */ + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} +#else /* !STM32F10X_CL */ +/** + * @brief DMA2 streams 4 and 5 shared interrupt handler. + * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a + * bit less efficient because an extra check. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + } + + /* Check on channel 5.*/ + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + DMA2->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h new file mode 100644 index 000000000..70737fe7c --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -0,0 +1,406 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f10x.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32F1xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA_STREAMS 12 +#else +#define STM32_DMA_STREAMS 7 +#endif + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32_isr.h b/os/hal/platforms/STM32F1xx/stm32_isr.h new file mode 100644 index 000000000..97a79e337 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_isr.h @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32F1xx_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * CAN units. + */ +#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler +#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler +#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler +#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler +#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler +#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler +#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler +#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler + +#ifdef STM32F10X_CL +#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn +#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn +#else +#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn +#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn +#endif +#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn +#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn +#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn +#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn +#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn +#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn + +/* + * OTG units. + */ +#define STM32_OTG1_HANDLER OTG_FS_IRQHandler + +#define STM32_OTG1_NUMBER OTG_FS_IRQn + +/* + * SDIO unit. + */ +#define STM32_SDIO_HANDLER SDIO_IRQHandler + +#define STM32_SDIO_NUMBER SDIO_IRQn + +/* + * TIM units. + */ +#if defined(STM32F10X_XL) +#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler +#else +#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler +#endif +#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler +#define STM32_TIM2_HANDLER TIM2_IRQHandler +#define STM32_TIM3_HANDLER TIM3_IRQHandler +#define STM32_TIM4_HANDLER TIM4_IRQHandler +#define STM32_TIM5_HANDLER TIM5_IRQHandler +#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler +#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler + +#if defined(STM32F10X_XL) +#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM16_IRQn +#else +#define STM32_TIM1_UP_NUMBER TIM1_UP_IRQn +#endif +#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn +#define STM32_TIM2_NUMBER TIM2_IRQn +#define STM32_TIM3_NUMBER TIM3_IRQn +#define STM32_TIM4_NUMBER TIM4_IRQn +#define STM32_TIM5_NUMBER TIM5_IRQn +#ifdef STM32F10X_XL +#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn +#else +#define STM32_TIM8_UP_NUMBER TIM8_UP_IRQn +#endif +#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn + +/* + * USART units. + */ +#define STM32_USART1_HANDLER USART1_IRQHandler +#define STM32_USART2_HANDLER USART2_IRQHandler +#define STM32_USART3_HANDLER USART3_IRQHandler +#define STM32_UART4_HANDLER UART4_IRQHandler +#define STM32_UART5_HANDLER UART5_IRQHandler + +#define STM32_USART1_NUMBER USART1_IRQn +#define STM32_USART2_NUMBER USART2_IRQn +#define STM32_USART3_NUMBER USART3_IRQn +#define STM32_UART4_NUMBER UART4_IRQn +#define STM32_UART5_NUMBER UART5_IRQn + +/* + * USB units. + */ +#define STM32_USB1_HP_HANDLER Vector8C +#define STM32_USB1_LP_HANDLER Vector90 + +#define STM32_USB1_HP_NUMBER USB_HP_CAN1_TX_IRQn +#define STM32_USB1_LP_NUMBER USB_LP_CAN1_RX0_IRQn +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h new file mode 100644 index 000000000..61d68831a --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -0,0 +1,961 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f10x.h. + * + * @addtogroup STM32F1xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name Backup domain interface specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp) + +/** + * @brief Disables BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp) + +/** + * @brief Resets the Backup Domain interface. + * + * @api + */ +#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) + +/** + * @brief Resets the entire Backup Domain. + * + * @api + */ +#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) +/** @} */ + +/** + * @name DMA peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA1() + +/** + * @brief Enables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA2() +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name OTG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_FS(lp) rccDisableAHB(RCC_AHBENR_OTGFSEN, lp) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST) +/** @} */ + +/** + * @name SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h new file mode 100644 index 000000000..6697b9648 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -0,0 +1,8357 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral�s drivers in application code(i.e. + * code will be based on direct access to peripheral�s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* CHIBIOS FIX */ +#include "board.h" + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/*#include "system_stm32f10x.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_XL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) +#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) +#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/os/hal/platforms/STM32F30x/adc_lld.c b/os/hal/platforms/STM32F30x/adc_lld.c new file mode 100644 index 000000000..7936be680 --- /dev/null +++ b/os/hal/platforms/STM32F30x/adc_lld.c @@ -0,0 +1,555 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/adc_lld.c + * @brief STM32F30x ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if STM32_ADC_DUAL_MODE +#if STM32_ADC_COMPACT_SAMPLES +/* Compact type dual mode.*/ +#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD) +#define ADC_DMA_MDMA ADC_CCR_MDMA_HWORD + +#else /* !STM32_ADC_COMPACT_SAMPLES */ +/* Large type dual mode.*/ +#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD) +#define ADC_DMA_MDMA ADC_CCR_MDMA_WORD +#endif /* !STM32_ADC_COMPACT_SAMPLES */ + +#else /* !STM32_ADC_DUAL_MODE */ +#if STM32_ADC_COMPACT_SAMPLES +/* Compact type single mode.*/ +#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE) +#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED + +#else /* !STM32_ADC_COMPACT_SAMPLES */ +/* Large type single mode.*/ +#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD) +#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED +#endif /* !STM32_ADC_COMPACT_SAMPLES */ +#endif /* !STM32_ADC_DUAL_MODE */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC voltage regulator. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_vreg_on(ADCDriver *adcp) { + + adcp->adcm->CR = 0; /* RM 12.4.3.*/ + adcp->adcm->CR = ADC_CR_ADVREGEN_0; +#if STM32_ADC_DUAL_MODE + adcp->adcs->CR = ADC_CR_ADVREGEN_0; +#endif + halPolledDelay(US2RTT(10)); +} + +/** + * @brief Disables the ADC voltage regulator. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_vreg_off(ADCDriver *adcp) { + + adcp->adcm->CR = 0; /* RM 12.4.3.*/ + adcp->adcm->CR = ADC_CR_ADVREGEN_1; +#if STM32_ADC_DUAL_MODE + adcp->adcs->CR = ADC_CR_ADVREGEN_1; +#endif +} + +/** + * @brief Enables the ADC analog circuit. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_analog_on(ADCDriver *adcp) { + + adcp->adcm->CR |= ADC_CR_ADEN; + while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0) + ; +#if STM32_ADC_DUAL_MODE + adcp->adcs->CR |= ADC_CR_ADEN; + while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0) + ; +#endif +} + +/** + * @brief Disables the ADC analog circuit. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_analog_off(ADCDriver *adcp) { + + adcp->adcm->CR |= ADC_CR_ADDIS; + while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0) + ; +#if STM32_ADC_DUAL_MODE + adcp->adcs->CR |= ADC_CR_ADDIS; + while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0) + ; +#endif +} + +/** + * @brief Calibrates and ADC unit. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_calibrate(ADCDriver *adcp) { + + chDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1", + "invalid register state"); + adcp->adcm->CR |= ADC_CR_ADCAL; + while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0) + ; +#if STM32_ADC_DUAL_MODE + chDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2", + "invalid register state"); + adcp->adcs->CR |= ADC_CR_ADCAL; + while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0) + ; +#endif +} + +/** + * @brief Stops an ongoing conversion, if any. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_stop_adc(ADCDriver *adcp) { + + if (adcp->adcm->CR & ADC_CR_ADSTART) { + adcp->adcm->CR |= ADC_CR_ADSTP; + while (adcp->adcm->CR & ADC_CR_ADSTP) + ; + } +} + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] isr content of the ISR register + */ +static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((isr & ADC_ISR_OVR) && + (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); + } + if (isr & ADC_ISR_AWD1) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD1); + } + if (isr & ADC_ISR_AWD2) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD2); + } + if (isr & ADC_ISR_AWD3) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD3); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC1/ADC2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + +#if STM32_ADC_DUAL_MODE + isr = ADC1->ISR; + isr |= ADC2->ISR; + ADC1->ISR = isr; + ADC2->ISR = isr; +#else /* !STM32_ADC_DUAL_MODE */ + isr = ADC1->ISR; + ADC1->ISR = isr; +#endif /* !STM32_ADC_DUAL_MODE */ + + adc_lld_serve_interrupt(&ADCD1, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) +/** + * @brief ADC3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorFC) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = ADC3->ISR; + ADC3->ISR = isr; + + adc_lld_serve_interrupt(&ADCD3, isr); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_ADC_DUAL_MODE +/** + * @brief ADC4 interrupt handler (as ADC3 slave). + * + * @isr + */ +CH_IRQ_HANDLER(Vector134) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = ADC4->ISR; + ADC4->ISR = isr; + + adc_lld_serve_interrupt(&ADCD3, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_DUAL_MODE */ +#endif /* STM32_ADC_USE_ADC3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adcc = ADC1_2; + ADCD1.adcm = ADC1; +#if STM32_ADC_DUAL_MODE + ADCD1.adcs = ADC2; +#endif + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = ADC_DMA_SIZE | + STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(ADC1_2_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY)); +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC3 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD3.adcc = ADC3_4; + ADCD3.adcm = ADC3; +#if STM32_ADC_DUAL_MODE + ADCD3.adcs = ADC4; +#endif + ADCD3.dmastp = STM32_DMA2_STREAM5; + ADCD3.dmamode = ADC_DMA_SIZE | + STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(ADC3_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY)); +#if STM32_ADC_DUAL_MODE + nvicEnableVector(ADC4_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY)); +#endif +#endif /* STM32_ADC_USE_ADC3 */ +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC12_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + rccEnableADC12(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC34_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + rccEnableADC34(FALSE); + } +#endif /* STM32_ADC_USE_ADC2 */ + + /* Setting DMA peripheral-side pointer.*/ +#if STM32_ADC_DUAL_MODE + dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR); +#else + dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR); +#endif + + /* Clock source setting.*/ + adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; + + /* Master ADC calibration.*/ + adc_lld_vreg_on(adcp); + adc_lld_calibrate(adcp); + + /* Master ADC enabled here in order to reduce conversions latencies.*/ + adc_lld_analog_on(adcp); + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock and analog part.*/ + if (adcp->state == ADC_READY) { + + /* Releasing the associated DMA channel.*/ + dmaStreamRelease(adcp->dmastp); + + /* Stopping the ongoing conversion, if any.*/ + adc_lld_stop_adc(adcp); + + /* Disabling ADC analog circuit and regulator.*/ + adc_lld_analog_off(adcp); + adc_lld_vreg_off(adcp); + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC12(FALSE); +#endif + +#if STM32_ADC_USE_ADC3 + if (&ADCD1 == adcp) + rccDisableADC34(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t dmamode, ccr, cfgr; + const ADCConversionGroup *grpp = adcp->grpp; + + chDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0), + "adc_lld_start_conversion(), #1", + "odd number of channels in dual mode"); + + /* Calculating control registers values.*/ + dmamode = adcp->dmamode; + ccr = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK | + ADC_CCR_MDMA_MASK)); + cfgr = grpp->cfgr | ADC_CFGR_CONT | ADC_CFGR_DMAEN; + if (grpp->circular) { + dmamode |= STM32_DMA_CR_CIRC; +#if STM32_ADC_DUAL_MODE + ccr |= ADC_CCR_DMACFG_CIRCULAR; +#else + cfgr |= ADC_CFGR_DMACFG_CIRCULAR; +#endif + } + + /* DMA setup.*/ + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + dmamode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); +#if STM32_ADC_DUAL_MODE + dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) * + (uint32_t)adcp->depth); +#else + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); +#endif + dmaStreamSetMode(adcp->dmastp, dmamode); + dmaStreamEnable(adcp->dmastp); + + /* Configuring the CCR register with the static settings ORed with + the user-specified settings in the conversion group configuration + structure.*/ + adcp->adcc->CCR = ccr; + + /* ADC setup, if it is defined a callback for the analog watch dog then it + is enabled.*/ + adcp->adcm->ISR = adcp->adcm->ISR; + adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1; + adcp->adcm->TR1 = grpp->tr1; +#if STM32_ADC_DUAL_MODE + adcp->adcm->SMPR1 = grpp->smpr[0]; + adcp->adcm->SMPR2 = grpp->smpr[1]; + adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2); + adcp->adcm->SQR2 = grpp->sqr[1]; + adcp->adcm->SQR3 = grpp->sqr[2]; + adcp->adcm->SQR4 = grpp->sqr[3]; + adcp->adcs->SMPR1 = grpp->ssmpr[0]; + adcp->adcs->SMPR2 = grpp->ssmpr[1]; + adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2); + adcp->adcs->SQR2 = grpp->ssqr[1]; + adcp->adcs->SQR3 = grpp->ssqr[2]; + adcp->adcs->SQR4 = grpp->ssqr[3]; + +#else /* !STM32_ADC_DUAL_MODE */ + adcp->adcm->SMPR1 = grpp->smpr[0]; + adcp->adcm->SMPR2 = grpp->smpr[1]; + adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels); + adcp->adcm->SQR2 = grpp->sqr[1]; + adcp->adcm->SQR3 = grpp->sqr[2]; + adcp->adcm->SQR4 = grpp->sqr[3]; +#endif /* !STM32_ADC_DUAL_MODE */ + + /* ADC configuration.*/ + adcp->adcm->CFGR = cfgr; + + /* Starting conversion.*/ + adcp->adcm->CR |= ADC_CR_ADSTART; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adc_lld_stop_adc(adcp); +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/adc_lld.h b/os/hal/platforms/STM32F30x/adc_lld.h new file mode 100644 index 000000000..85dd429f1 --- /dev/null +++ b/os/hal/platforms/STM32F30x/adc_lld.h @@ -0,0 +1,612 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/adc_lld.h + * @brief STM32F30x ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_IN16 16 /**< @brief External analog input 16. */ +#define ADC_CHANNEL_IN17 17 /**< @brief External analog input 17. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */ +#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */ +#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */ +#define ADC_SMPR_SMP_7P5 3 /**< @brief 20 cycles conversion time. */ +#define ADC_SMPR_SMP_19P5 4 /**< @brief 32 cycles conversion time. */ +#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */ +#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */ +#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */ +/** @} */ + +/** + * @name Resolution + * @{ + */ +#define ADC_CFGR1_RES_12BIT (0 << 3) +#define ADC_CFGR1_RES_10BIT (1 << 3) +#define ADC_CFGR1_RES_8BIT (2 << 3) +#define ADC_CFGR1_RES_6BIT (3 << 3) +/** @} */ + +/** + * @name CFGR register configuration helpers + * @{ + */ +#define ADC_CFGR_DMACFG_MASK (1 << 1) +#define ADC_CFGR_DMACFG_ONESHOT (0 << 1) +#define ADC_CFGR_DMACFG_CIRCULAR (1 << 1) + +#define ADC_CFGR_RES_MASK (3 << 3) +#define ADC_CFGR_RES_12BITS (0 << 3) +#define ADC_CFGR_RES_10BITS (1 << 3) +#define ADC_CFGR_RES_8BITS (2 << 3) +#define ADC_CFGR_RES_6BITS (3 << 3) + +#define ADC_CFGR_ALIGN_MASK (1 << 5) +#define ADC_CFGR_ALIGN_RIGHT (0 << 5) +#define ADC_CFGR_ALIGN_LEFT (1 << 5) + +#define ADC_CFGR_EXTSEL_MASK (15 << 6) +#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 6) + +#define ADC_CFGR_EXTEN_MASK (3 << 10) +#define ADC_CFGR_EXTEN_DISABLED (0 << 10) +#define ADC_CFGR_EXTEN_RISING (1 << 10) +#define ADC_CFGR_EXTEN_FALLING (2 << 10) +#define ADC_CFGR_EXTEN_BOTH (3 << 10) + +#define ADC_CFGR_DISCEN_MASK (1 << 16) +#define ADC_CFGR_DISCEN_DISABLED (0 << 16) +#define ADC_CFGR_DISCEN_ENABLED (1 << 16) + +#define ADC_CFGR_DISCNUM_MASK (7 << 17) +#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17) + +#define ADC_CFGR_AWD1_DISABLED 0 +#define ADC_CFGR_AWD1_ALL (1 << 23) +#define ADC_CFGR_AWD1_SINGLE(n) (((n) << 26) | (1 << 23) | (1 << 22)) +/** @} */ + +/** + * @name CCR register configuration helpers + * @{ + */ +#define ADC_CCR_DUAL_MASK (31 << 0) +#define ADC_CCR_DUAL(n) ((n) << 0) +#define ADC_CCR_DELAY_MASK (15 << 8) +#define ADC_CCR_DELAY(n) ((n) << 8) +#define ADC_CCR_DMACFG_MASK (1 << 13) +#define ADC_CCR_DMACFG_ONESHOT (0 << 13) +#define ADC_CCR_DMACFG_CIRCULAR (1 << 13) +#define ADC_CCR_MDMA_MASK (3 << 14) +#define ADC_CCR_MDMA_DISABLED (0 << 14) +#define ADC_CCR_MDMA_WORD (2 << 14) +#define ADC_CCR_MDMA_HWORD (3 << 14) +#define ADC_CCR_CKMODE_MASK (3 << 16) +#define ADC_CCR_CKMODE_ADCCK (0 << 16) +#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16) +#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16) +#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16) +#define ADC_CCR_VREFEN (1 << 22) +#define ADC_CCR_TSEN (1 << 23) +#define ADC_CCR_VBATEN (1 << 24) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC3 driver enable switch. + * @details If set to @p TRUE the support for ADC3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC3 FALSE +#endif + +/** + * @brief ADC1/ADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC3/ADC4 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1/ADC2 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3/ADC4 interrupt priority level setting. + */ +#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1/ADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3/ADC4 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1/ADC2 clock source and mode. + */ +#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__) +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#endif + +/** + * @brief ADC3/ADC4 clock source and mode. + */ +#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__) +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#endif + +/** + * @brief Enables the ADC master/slave mode. + */ +#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__) +#define STM32_ADC_DUAL_MODE FALSE +#endif + +/** + * @brief Makes the ADC samples type an 8bits one. + */ +#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__) +#define STM32_ADC_COMPACT_SAMPLES FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 +#error "ADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC3" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC3 DMA" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC3" +#endif + +#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK +#define STM32_ADC12_CLOCK STM32_ADC12CLK +#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC12_CLOCK (STM32_HCLK / 1) +#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 +#define STM32_ADC12_CLOCK (STM32_HCLK / 2) +#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 +#define STM32_ADC12_CLOCK (STM32_HCLK / 4) +#else +#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" +#endif + +#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK +#define STM32_ADC34_CLOCK STM32_ADC34CLK +#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC34_CLOCK (STM32_HCLK / 1) +#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 +#define STM32_ADC34_CLOCK (STM32_HCLK / 2) +#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 +#define STM32_ADC34_CLOCK (STM32_HCLK / 4) +#else +#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" +#endif + +#if STM32_ADC12_CLOCK > 72000000 +#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)" +#endif + +#if STM32_ADC34_CLOCK > 72000000 +#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__) +typedef uint16_t adcsample_t; +#else +typedef uint8_t adcsample_t; +#endif + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */ + ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */ + ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CFGR register initialization data. + * @note The bits DMAEN, DMACFG, OVRMOD, CONT are enforced internally + * to the driver, keep them to zero. + */ + uint32_t cfgr; + /** + * @brief ADC TR1 register initialization data. + */ + uint32_t tr1; + /** + * @brief ADC CCR register initialization data. + * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the + * driver, keep them to zero. + */ + uint32_t ccr; + /** + * @brief ADC SMPRx registers initialization data. + */ + uint32_t smpr[2]; + /** + * @brief ADC SQRx register initialization data. + */ + uint32_t sqr[4]; +#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__) + /** + * @brief Slave ADC SMPRx registers initialization data. + */ + uint32_t ssmpr[2]; + /** + * @brief Slave ADC SQRx register initialization data. + */ + uint32_t ssqr[4]; +#endif /* STM32_ADC_DUAL_MODE */ +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the common ADCx_y registers block. + */ + ADC_Common_TypeDef *adcc; + /** + * @brief Pointer to the master ADCx registers block. + */ + ADC_TypeDef *adcm; +#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__) + /** + * @brief Pointer to the slave ADCx registers block. + */ + ADC_TypeDef *adcs; +#endif /* STM32_ADC_DUAL_MODE */ + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Threashold register initializer + * @{ + */ +#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low)) +/** @} */ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 0) + +#define ADC_SQR1_SQ1_N(n) ((n) << 6) /**< @brief 1st channel in seq. */ +#define ADC_SQR1_SQ2_N(n) ((n) << 12) /**< @brief 2nd channel in seq. */ +#define ADC_SQR1_SQ3_N(n) ((n) << 18) /**< @brief 3rd channel in seq. */ +#define ADC_SQR1_SQ4_N(n) ((n) << 24) /**< @brief 4th channel in seq. */ + +#define ADC_SQR2_SQ5_N(n) ((n) << 0) /**< @brief 5th channel in seq. */ +#define ADC_SQR2_SQ6_N(n) ((n) << 6) /**< @brief 6th channel in seq. */ +#define ADC_SQR2_SQ7_N(n) ((n) << 12) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 18) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 24) /**< @brief 9th channel in seq. */ + +#define ADC_SQR3_SQ10_N(n) ((n) << 0) /**< @brief 10th channel in seq.*/ +#define ADC_SQR3_SQ11_N(n) ((n) << 6) /**< @brief 11th channel in seq.*/ +#define ADC_SQR3_SQ12_N(n) ((n) << 12) /**< @brief 12th channel in seq.*/ +#define ADC_SQR3_SQ13_N(n) ((n) << 18) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 24) /**< @brief 14th channel in seq.*/ + +#define ADC_SQR4_SQ15_N(n) ((n) << 0) /**< @brief 15th channel in seq.*/ +#define ADC_SQR4_SQ16_N(n) ((n) << 6) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR1_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR1_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR1_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR1_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR1_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR1_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_AN16(n) ((n) << 18) /**< @brief AN16 sampling time. */ +#define ADC_SMPR2_SMP_AN17(n) ((n) << 21) /**< @brief AN17 sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/ext_lld_isr.c b/os/hal/platforms/STM32F30x/ext_lld_isr.c new file mode 100644 index 000000000..c9802713e --- /dev/null +++ b/os/hal/platforms/STM32F30x/ext_lld_isr.c @@ -0,0 +1,418 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/ext_lld_isr.c + * @brief STM32F30x EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_DISABLE_EXTI0_HANDLER) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector58) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI1_HANDLER) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector5C) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI2_HANDLER) +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector60) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI3_HANDLER) +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector64) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_HANDLER) +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector68) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(Vector44) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI17_HANDLER) +/** + * @brief EXTI[17] interrupt handler (RTC Alarm). + * + * @isr + */ +CH_IRQ_HANDLER(VectorE4) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI18_HANDLER) +/** + * @brief EXTI[18] interrupt handler (USB Wakeup). + * + * @isr + */ +CH_IRQ_HANDLER(VectorE8) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI19_HANDLER) +/** + * @brief EXTI[19] interrupt handler (Tamper TimeStamp). + * + * @isr + */ +CH_IRQ_HANDLER(Vector48) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI20_HANDLER) +/** + * @brief EXTI[20] interrupt handler (RTC Wakeup). + * + * @isr + */ +CH_IRQ_HANDLER(Vector4C) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) +/** + * @brief EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3). + * + * @isr + */ +CH_IRQ_HANDLER(Vector140) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29)); + EXTI->PR = pr; + if (pr & (1 << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1 << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + if (pr & (1 << 29)) + EXTD1.config->channels[29].cb(&EXTD1, 29); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI30_32_HANDLER) +/** + * @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6). + * + * @isr + */ +CH_IRQ_HANDLER(Vector144) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 30) | (1 << 31)); + EXTI->PR = pr; + if (pr & (1 << 30)) + EXTD1.config->channels[30].cb(&EXTD1, 30); + if (pr & (1 << 31)) + EXTD1.config->channels[31].cb(&EXTD1, 31); + + pr = EXTI->PR2 & (1 << 0); + EXTI->PR2 = pr; + if (pr & (1 << 0)) + EXTD1.config->channels[32].cb(&EXTD1, 32); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI33_HANDLER) +/** + * @brief EXTI[33] interrupt handler (COMP7). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR2 = (1 << 1); + EXTD1.config->channels[33].cb(&EXTD1, 33); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_TS_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); + nvicEnableVector(USBWakeUp_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(COMP1_2_3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY)); + nvicEnableVector(COMP4_5_6_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI30_32_IRQ_PRIORITY)); + nvicEnableVector(COMP7_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI33_IRQ_PRIORITY)); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_TS_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(USBWakeUp_IRQn); + nvicDisableVector(TAMPER_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP1_2_3_IRQn); + nvicDisableVector(COMP4_5_6_IRQn); + nvicDisableVector(COMP7_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/ext_lld_isr.h b/os/hal/platforms/STM32F30x/ext_lld_isr.h new file mode 100644 index 000000000..42f1e30fe --- /dev/null +++ b/os/hal/platforms/STM32F30x/ext_lld_isr.h @@ -0,0 +1,177 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/ext_lld_isr.h + * @brief STM32F30x EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI5..9 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI10..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21,22,29 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI30..32 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI33 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/hal_lld.c b/os/hal/platforms/STM32F30x/hal_lld.c new file mode 100644 index 000000000..5c1d1efb1 --- /dev/null +++ b/os/hal/platforms/STM32F30x/hal_lld.c @@ -0,0 +1,209 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/hal_lld.c + * @brief STM32F30x HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + + /* USB IRQ relocated to not conflict with CAN.*/ + SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP; +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON; +#endif + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Clock settings.*/ + RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | + STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 | + STM32_HPRE; + RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV; + RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW | + STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW | + STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW; + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif +#endif /* !STM32_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/hal_lld.h b/os/hal/platforms/STM32F30x/hal_lld.h new file mode 100644 index 000000000..625700ab5 --- /dev/null +++ b/os/hal/platforms/STM32F30x/hal_lld.h @@ -0,0 +1,1137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/hal_lld.h + * @brief STM32F30x HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - STM32F30X for Analog & DSP devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" +#include "stm32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F30x Analog & DSP" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 24000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 72000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 72000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 8000000 /**< High speed internal clock. */ +#define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI/2. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is + HSE/PREDIV. */ + +#define STM32_USBPRE_DIV1P5 (0 << 22) /**< USB clock is PLLCLK/1.5. */ +#define STM32_USBPRE_DIV1 (1 << 22) /**< USB clock is PLLCLK/1. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_LSI (2 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (3 << 24) /**< LSE clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as + RTC clock. */ +/** @} */ + +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ +#define STM32_PREDIV_MASK (15 << 0) /**< PREDIV divisor mask. */ +#define STM32_ADC12PRES_MASK (31 << 4) /**< ADC12 clock source mask. */ +#define STM32_ADC12PRES_NOCLOCK (0 << 4) /**< ADC12 clock is disabled. */ +#define STM32_ADC12PRES_DIV1 (16 << 4) /**< ADC12 clock is PLL/1. */ +#define STM32_ADC12PRES_DIV2 (17 << 4) /**< ADC12 clock is PLL/2. */ +#define STM32_ADC12PRES_DIV4 (18 << 4) /**< ADC12 clock is PLL/4. */ +#define STM32_ADC12PRES_DIV6 (19 << 4) /**< ADC12 clock is PLL/6. */ +#define STM32_ADC12PRES_DIV8 (20 << 4) /**< ADC12 clock is PLL/8. */ +#define STM32_ADC12PRES_DIV10 (21 << 4) /**< ADC12 clock is PLL/10. */ +#define STM32_ADC12PRES_DIV12 (22 << 4) /**< ADC12 clock is PLL/12. */ +#define STM32_ADC12PRES_DIV16 (23 << 4) /**< ADC12 clock is PLL/16. */ +#define STM32_ADC12PRES_DIV32 (24 << 4) /**< ADC12 clock is PLL/32. */ +#define STM32_ADC12PRES_DIV64 (25 << 4) /**< ADC12 clock is PLL/64. */ +#define STM32_ADC12PRES_DIV128 (26 << 4) /**< ADC12 clock is PLL/128. */ +#define STM32_ADC12PRES_DIV256 (27 << 4) /**< ADC12 clock is PLL/256. */ +#define STM32_ADC34PRES_MASK (31 << 4) /**< ADC34 clock source mask. */ +#define STM32_ADC34PRES_NOCLOCK (0 << 4) /**< ADC34 clock is disabled. */ +#define STM32_ADC34PRES_DIV1 (16 << 4) /**< ADC34 clock is PLL/1. */ +#define STM32_ADC34PRES_DIV2 (17 << 4) /**< ADC34 clock is PLL/2. */ +#define STM32_ADC34PRES_DIV4 (18 << 4) /**< ADC34 clock is PLL/4. */ +#define STM32_ADC34PRES_DIV6 (19 << 4) /**< ADC34 clock is PLL/6. */ +#define STM32_ADC34PRES_DIV8 (20 << 4) /**< ADC34 clock is PLL/8. */ +#define STM32_ADC34PRES_DIV10 (21 << 4) /**< ADC34 clock is PLL/10. */ +#define STM32_ADC34PRES_DIV12 (22 << 4) /**< ADC34 clock is PLL/12. */ +#define STM32_ADC34PRES_DIV16 (23 << 4) /**< ADC34 clock is PLL/16. */ +#define STM32_ADC34PRES_DIV32 (24 << 4) /**< ADC34 clock is PLL/32. */ +#define STM32_ADC34PRES_DIV64 (25 << 4) /**< ADC34 clock is PLL/64. */ +#define STM32_ADC34PRES_DIV128 (26 << 4) /**< ADC34 clock is PLL/128. */ +#define STM32_ADC34PRES_DIV256 (27 << 4) /**< ADC34 clock is PLL/256. */ +/** @} */ + +/** + * @name RCC_CFGR3 register bits definitions + * @{ + */ +#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */ +#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */ +#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */ +#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */ +#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */ +#define STM32_I2C1SW_MASK (1 << 4) /**< I2C1 clock source mask. */ +#define STM32_I2C1SW_HSI (0 << 4) /**< I2C1 clock is HSI. */ +#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C1 clock is SYSCLK. */ +#define STM32_I2C2SW_MASK (1 << 5) /**< I2C2 clock source mask. */ +#define STM32_I2C2SW_HSI (0 << 5) /**< I2C2 clock is HSI. */ +#define STM32_I2C2SW_SYSCLK (1 << 5) /**< I2C2 clock is SYSCLK. */ +#define STM32_TIM1SW_MASK (1 << 8) /**< TIM1 clock source mask. */ +#define STM32_TIM1SW_PCLK2 (0 << 8) /**< TIM1 clock is PCLK2. */ +#define STM32_TIM1SW_PLLX2 (1 << 10) /**< TIM1 clock is PLL*2. */ +#define STM32_TIM8SW_MASK (1 << 10) /**< TIM8 clock source mask. */ +#define STM32_TIM8SW_PCLK2 (0 << 10) /**< TIM8 clock is PCLK2. */ +#define STM32_TIM8SW_PLLX2 (1 << 10) /**< TIM8 clock is PLL*2. */ +#define STM32_USART2SW_MASK (3 << 16) /**< USART2 clock source mask. */ +#define STM32_USART2SW_PCLK (0 << 16) /**< USART2 clock is PCLK. */ +#define STM32_USART2SW_SYSCLK (1 << 16) /**< USART2 clock is SYSCLK. */ +#define STM32_USART2SW_LSE (2 << 16) /**< USART2 clock is LSE. */ +#define STM32_USART2SW_HSI (3 << 16) /**< USART2 clock is HSI. */ +#define STM32_USART3SW_MASK (3 << 18) /**< USART3 clock source mask. */ +#define STM32_USART3SW_PCLK (0 << 18) /**< USART3 clock is PCLK. */ +#define STM32_USART3SW_SYSCLK (1 << 18) /**< USART3 clock is SYSCLK. */ +#define STM32_USART3SW_LSE (2 << 18) /**< USART3 clock is LSE. */ +#define STM32_USART3SW_HSI (3 << 18) /**< USART3 clock is HSI. */ +#define STM32_UART4SW_MASK (3 << 20) /**< USART4 clock source mask. */ +#define STM32_UART4SW_PCLK (0 << 20) /**< USART4 clock is PCLK. */ +#define STM32_UART4SW_SYSCLK (1 << 20) /**< USART4 clock is SYSCLK. */ +#define STM32_UART4SW_LSE (2 << 20) /**< USART4 clock is LSE. */ +#define STM32_UART4SW_HSI (3 << 20) /**< USART4 clock is HSI. */ +#define STM32_UART5SW_MASK (3 << 22) /**< USART5 clock source mask. */ +#define STM32_UART5SW_PCLK (0 << 22) /**< USART5 clock is PCLK. */ +#define STM32_UART5SW_SYSCLK (1 << 22) /**< USART5 clock is SYSCLK. */ +#define STM32_UART5SW_LSE (2 << 22) /**< USART5 clock is LSE. */ +#define STM32_UART5SW_HSI (3 << 22) /**< USART5 clock is HSI. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV_VALUE 1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief ADC12 prescaler value. + */ +#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__) +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#endif + +/** + * @brief ADC34 prescaler value. + */ +#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__) +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#endif + +/** + * @brief USART1 clock source. + */ +#if !defined(STM32_USART1SW) || defined(__DOXYGEN__) +#define STM32_USART1SW STM32_USART1SW_PCLK +#endif + +/** + * @brief USART2 clock source. + */ +#if !defined(STM32_USART2SW) || defined(__DOXYGEN__) +#define STM32_USART2SW STM32_USART2SW_PCLK +#endif + +/** + * @brief USART3 clock source. + */ +#if !defined(STM32_USART3SW) || defined(__DOXYGEN__) +#define STM32_USART3SW STM32_USART3SW_PCLK +#endif + +/** + * @brief UART4 clock source. + */ +#if !defined(STM32_UART4SW) || defined(__DOXYGEN__) +#define STM32_UART4SW STM32_UART4SW_PCLK +#endif + +/** + * @brief UART5 clock source. + */ +#if !defined(STM32_UART5SW) || defined(__DOXYGEN__) +#define STM32_UART5SW STM32_UART5SW_PCLK +#endif + +/** + * @brief I2C1 clock source. + */ +#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__) +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#endif + +/** + * @brief I2C2 clock source. + */ +#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__) +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#endif + +/** + * @brief TIM1 clock source. + */ +#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__) +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#endif + +/** + * @brief TIM8 clock source. + */ +#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__) +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief USB prescaler initialization. + */ +#if !defined(STM32_USBPRE) || defined(__DOXYGEN__) +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F30x_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F30x_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if STM32_USART1SW == STM32_USART1SW_HSI +#error "HSI not enabled, required by STM32_USART1SW" +#endif + +#if STM32_USART2SW == STM32_USART2SW_HSI +#error "HSI not enabled, required by STM32_USART2SW" +#endif + +#if STM32_USART3SW == STM32_USART3SW_HSI +#error "HSI not enabled, required by STM32_USART3SW" +#endif + +#if STM32_UART4SW == STM32_UART4SW_HSI +#error "HSI not enabled, required by STM32_UART4SW" +#endif + +#if STM32_UART5SW == STM32_UART5SW_HSI +#error "HSI not enabled, required by STM32_UART5SW" +#endif + +#if STM32_I2C1SW == STM32_I2C1SW_HSI +#error "HSI not enabled, required by STM32_I2C1SW" +#endif + +#if STM32_I2C2SW == STM32_I2C2SW_HSI +#error "HSI not enabled, required by STM32_I2C2SW" +#endif + +#if STM32_TIM1SW == STM32_TIM1SW_HSI +#error "HSI not enabled, required by STM32_TIM1SW" +#endif + +#if STM32_TIM8SW == STM32_TIM8SW_HSI +#error "HSI not enabled, required by STM32_TIM8SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0) +#error "STM32_LSECLK not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + +#if STM32_USART1SW == STM32_USART1SW_LSE +#error "LSE not enabled, required by STM32_USART1SW" +#endif + +#if STM32_USART2SW == STM32_USART2SW_LSE +#error "LSE not enabled, required by STM32_USART2SW" +#endif + +#if STM32_USART3SW == STM32_USART3SW_LSE +#error "LSE not enabled, required by STM32_USART3SW" +#endif + +#if STM32_UART4SW == STM32_UART4SW_LSE +#error "LSE not enabled, required by STM32_UART4SW" +#endif + +#if STM32_UART5SW == STM32_UART5SW_LSE +#error "LSE not enabled, required by STM32_UART5SW" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + (STM32_TIM1SW == STM32_TIM1SW_PLLX2) || \ + (STM32_TIM8SW == STM32_TIM8SW_PLLX2) || \ + (STM32_ADC12PRES != STM32_ADC12PRES_NOCLOCK) || \ + (STM32_ADC34PRES != STM32_ADC34PRES_NOCLOCK) || \ + STM32_USB_CLOCK_REQUIRED || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) +#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 32) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC12 frequency. + */ +#if (STM32_ADC12PRES == STM32_ADC12PRES_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_ADC12CLK 0 +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV1 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 1) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV2 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 2) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV4 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 4) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV6 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 6) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV8 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 8) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV10 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 10) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV12 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 12) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV16 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 16) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV32 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 32) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV64 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 64) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV128 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 128) +#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV256 +#define STM32_ADC12CLK (STM32_PLLCLKOUT / 256) +#else +#error "invalid STM32_ADC12PRES value specified" +#endif + +/** + * @brief ADC34 frequency. + */ +#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_ADC34CLK 0 +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 1) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV2 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 2) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV4 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 4) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV6 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 6) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV8 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 8) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV10 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 10) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV12 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 12) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV16 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 16) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV32 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 32) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV64 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 64) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV128 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 128) +#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV256 +#define STM32_ADC34CLK (STM32_PLLCLKOUT / 256) +#else +#error "invalid STM32_ADC34PRES value specified" +#endif + +/* ADC12 frequency check.*/ +#if STM32_ADC12CLK > STM32_ADCCLK_MAX +#error "STM32_ADC12CLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/* ADC34 frequency check.*/ +#if STM32_ADC34CLK > STM32_ADCCLK_MAX +#error "STM32_ADC34CLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief I2C1 frequency. + */ +#if STM32_I2C1SW == STM32_I2C1SW_HSI +#define STM32_I2C1CLK STM32_HSICLK +#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK +#define STM32_I2C1CLK STM32_SYSCLK +#else +#error "invalid source selected for I2C1 clock" +#endif + +/** + * @brief I2C2 frequency. + */ +#if STM32_I2C2SW == STM32_I2C2SW_HSI +#define STM32_I2C2CLK STM32_HSICLK +#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK +#define STM32_I2C2CLK STM32_SYSCLK +#else +#error "invalid source selected for I2C2 clock" +#endif + +/** + * @brief USART1 frequency. + */ +#if STM32_USART1SW == STM32_USART1SW_PCLK +#define STM32_USART1CLK STM32_PCLK2 +#elif STM32_USART1SW == STM32_USART1SW_SYSCLK +#define STM32_USART1CLK STM32_SYSCLK +#elif STM32_USART1SW == STM32_USART1SW_LSECLK +#define STM32_USART1CLK STM32_LSECLK +#elif STM32_USART1SW == STM32_USART1SW_HSICLK +#define STM32_USART1CLK STM32_HSICLK +#else +#error "invalid source selected for USART1 clock" +#endif + +/** + * @brief USART2 frequency. + */ +#if STM32_USART2SW == STM32_USART2SW_PCLK +#define STM32_USART2CLK STM32_PCLK1 +#elif STM32_USART2SW == STM32_USART2SW_SYSCLK +#define STM32_USART2CLK STM32_SYSCLK +#elif STM32_USART2SW == STM32_USART2SW_LSECLK +#define STM32_USART2CLK STM32_LSECLK +#elif STM32_USART2SW == STM32_USART2SW_HSICLK +#define STM32_USART2CLK STM32_HSICLK +#else +#error "invalid source selected for USART2 clock" +#endif + +/** + * @brief USART3 frequency. + */ +#if STM32_USART3SW == STM32_USART3SW_PCLK +#define STM32_USART3CLK STM32_PCLK1 +#elif STM32_USART3SW == STM32_USART3SW_SYSCLK +#define STM32_USART3CLK STM32_SYSCLK +#elif STM32_USART3SW == STM32_USART3SW_LSECLK +#define STM32_USART3CLK STM32_LSECLK +#elif STM32_USART3SW == STM32_USART3SW_HSICLK +#define STM32_USART3CLK STM32_HSICLK +#else +#error "invalid source selected for USART3 clock" +#endif + +/** + * @brief UART4 frequency. + */ +#if STM32_UART4SW == STM32_UART4SW_PCLK +#define STM32_UART4CLK STM32_PCLK1 +#elif STM32_UART4SW == STM32_UART4SW_SYSCLK +#define STM32_UART4CLK STM32_SYSCLK +#elif STM32_UART4SW == STM32_UART4SW_LSECLK +#define STM32_UART4CLK STM32_LSECLK +#elif STM32_UART4SW == STM32_UART4SW_HSICLK +#define STM32_UART4CLK STM32_HSICLK +#else +#error "invalid source selected for UART4 clock" +#endif + +/** + * @brief UART5 frequency. + */ +#if STM32_UART5SW == STM32_UART5SW_PCLK +#define STM32_UART5CLK STM32_PCLK1 +#elif STM32_UART5SW == STM32_UART5SW_SYSCLK +#define STM32_UART5CLK STM32_SYSCLK +#elif STM32_UART5SW == STM32_UART5SW_LSECLK +#define STM32_UART5CLK STM32_LSECLK +#elif STM32_UART5SW == STM32_UART5SW_HSICLK +#define STM32_UART5CLK STM32_HSICLK +#else +#error "invalid source selected for UART5 clock" +#endif + +/** + * @brief TIM1 frequency. + */ +#if STM32_TIM1SW == STM32_TIM1SW_PCLK2 +#define STM32_TIM1CLK STM32_PCLK2 +#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2 +#define STM32_TIM1CLK (STM32_PLLCLKOUT * 2) +#else +#error "invalid source selected for TIM1 clock" +#endif + +/** + * @brief TIM8 frequency. + */ +#if STM32_TIM8SW == STM32_TIM8SW_PCLK2 +#define STM32_TIM8CLK STM32_PCLK2 +#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2 +#define STM32_TIM8CLK (STM32_PLLCLKOUT * 2) +#else +#error "invalid source selected for TIM8 clock" +#endif + +/** + * @brief Timers 2, 3, 4, 6, 7 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 15, 16, 17 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief USB frequency. + */ +#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__) +#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3) +#elif (STM32_USBPRE == STM32_USBPRE_DIV1) +#define STM32_USBCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_USBPRE value specified" +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/platform.mk b/os/hal/platforms/STM32F30x/platform.mk new file mode 100644 index 000000000..ce219fa15 --- /dev/null +++ b/os/hal/platforms/STM32F30x/platform.mk @@ -0,0 +1,27 @@ +# List of all the STM32F30x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F30x/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F30x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F30x/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F30x/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F30x \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 diff --git a/os/hal/platforms/STM32F30x/stm32_dma.c b/os/hal/platforms/STM32F30x/stm32_dma.c new file mode 100644 index 000000000..71777583d --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32_dma.c @@ -0,0 +1,450 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32F30x_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, + {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, + {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, + {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector6C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector70) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector74) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector7C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector120) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector124) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector128) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector12C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector130) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + DMA2->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32_dma.h b/os/hal/platforms/STM32F30x/stm32_dma.h new file mode 100644 index 000000000..2415f00f2 --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32_dma.h @@ -0,0 +1,406 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f30x.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32F30x_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA_STREAMS 12 +#else +#define STM32_DMA_STREAMS 7 +#endif + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR_EN +#define STM32_DMA_CR_TEIE DMA_CCR_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR_CIRC +#define STM32_DMA_CR_PINC DMA_CCR_PINC +#define STM32_DMA_CR_MINC DMA_CCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32_isr.h b/os/hal/platforms/STM32F30x/stm32_isr.h new file mode 100644 index 000000000..94b04b63e --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32_isr.h @@ -0,0 +1,132 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32F30x_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * CAN units. + */ +#define STM32_CAN1_TX_HANDLER Vector8C +#define STM32_CAN1_RX0_HANDLER Vector90 +#define STM32_CAN1_RX1_HANDLER Vector94 +#define STM32_CAN1_SCE_HANDLER Vector98 + +#define STM32_CAN1_TX_NUMBER 19 +#define STM32_CAN1_RX0_NUMBER 20 +#define STM32_CAN1_RX1_NUMBER 21 +#define STM32_CAN1_SCE_NUMBER 22 + +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_NUMBER 32 + +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_NUMBER 34 + +/* + * TIM units. + */ +#define STM32_TIM1_UP_HANDLER VectorA4 +#define STM32_TIM1_CC_HANDLER VectorAC +#define STM32_TIM2_HANDLER VectorB0 +#define STM32_TIM3_HANDLER VectorB4 +#define STM32_TIM4_HANDLER VectorB8 +#define STM32_TIM6_HANDLER Vector118 +#define STM32_TIM7_HANDLER Vector11C +#define STM32_TIM8_UP_HANDLER VectorF0 +#define STM32_TIM8_CC_HANDLER VectorF8 + +#define STM32_TIM1_UP_NUMBER 25 +#define STM32_TIM1_CC_NUMBER 27 +#define STM32_TIM2_NUMBER 28 +#define STM32_TIM3_NUMBER 29 +#define STM32_TIM4_NUMBER 30 +#define STM32_TIM6_NUMBER 54 +#define STM32_TIM7_NUMBER 55 +#define STM32_TIM8_UP_NUMBER 44 +#define STM32_TIM8_CC_NUMBER 46 + +/* + * USART units. + */ +#define STM32_USART1_HANDLER VectorD4 +#define STM32_USART2_HANDLER VectorD8 +#define STM32_USART3_HANDLER VectorDC +#define STM32_UART4_HANDLER Vector110 +#define STM32_UART5_HANDLER Vector114 + +#define STM32_USART1_NUMBER 37 +#define STM32_USART2_NUMBER 38 +#define STM32_USART3_NUMBER 39 +#define STM32_UART4_NUMBER 52 +#define STM32_UART5_NUMBER 53 + +/* + * USB units. + */ +#define STM32_USB1_HP_HANDLER Vector168 +#define STM32_USB1_LP_HANDLER Vector16C + +#define STM32_USB1_HP_NUMBER 74 +#define STM32_USB1_LP_NUMBER 75 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32_rcc.h b/os/hal/platforms/STM32F30x/stm32_rcc.h new file mode 100644 index 000000000..9cc2edf52 --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32_rcc.h @@ -0,0 +1,835 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f30x.h. + * + * @addtogroup STM32F30x_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1/ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp) + +/** + * @brief Disables the ADC1/ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp) + +/** + * @brief Resets the ADC1/ADC2 peripheral. + * + * @api + */ +#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST) + +/** + * @brief Enables the ADC3/ADC4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp) + +/** + * @brief Disables the ADC3/ADC4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp) + +/** + * @brief Resets the ADC3/ADC4 peripheral. + * + * @api + */ +#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST) +/** @} */ + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) + +/** + * @brief Enables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32_registry.h b/os/hal/platforms/STM32F30x/stm32_registry.h new file mode 100644 index 000000000..f32637aa4 --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32_registry.h @@ -0,0 +1,209 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F30x/stm32_registry.h + * @brief STM32F30x capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_REGISTRY_H_ +#define _STM32_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F30x capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_ADC3_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC4 TRUE +#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC4_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC1 FALSE +#define STM32_SDADC1_DMA_MSK 0 +#define STM32_SDADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC2 FALSE +#define STM32_SDADC2_DMA_MSK 0 +#define STM32_SDADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC3 FALSE +#define STM32_SDADC3_DMA_MSK 0 +#define STM32_SDADC3_DMA_CHN 0x00000000 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 34 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +#endif /* _STM32_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32f30x.h b/os/hal/platforms/STM32F30x/stm32f30x.h new file mode 100644 index 000000000..99c6178ee --- /dev/null +++ b/os/hal/platforms/STM32F30x/stm32f30x.h @@ -0,0 +1,6213 @@ +/** + ****************************************************************************** + * @file stm32f30x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F30x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x + * @{ + */ + +#ifndef __STM32F30x_H +#define __STM32F30x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F30X) + #define STM32F30X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F30X) + #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + + +/** + * @brief STM32F30x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F30X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ + + +/** + * @brief STM32F30X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the lines 17, 19 & 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ + COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* CHIBIOS FIX */ +/*#include "system_stm32f30x.h"*/ /* STM32F30x System Header */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ + __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ + +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ + __IO uint16_t RDP; /*!adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; + adcp->adc->CR2 = cr2; + adcp->adc->CR1 = 0; + adcp->adc->CR2 = cr2 | ADC_CR2_ADON; + + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + /* SDADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[0]; + adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[1]; + adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[2]; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC +else { + chDbgAssert(FALSE, "adc_lld_start(), #5", "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] sr content of the ISR register + * + * @notapi + */ +static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + if (sr & ADC_SR_AWD) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD1); + } + } +} +#endif /* STM32_ADC_USE_ADC */ + +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] isr content of the ISR register + * + * @notapi + */ +static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((isr & SDADC_ISR_JOVRF) && + (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); + } + } +} +#endif /* STM32_ADC_USE_SDADC */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + adc_lld_serve_interrupt(&ADCD1, sr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) +/** + * @brief SDADC1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector134) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC1->ISR; + SDADC1->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD1, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC1 */ + +#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) +/** + * @brief SDADC2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector138) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC2->ISR; + SDADC2->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD2, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC2 */ + +#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) +/** + * @brief SDADC3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector13C) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = SDADC3->ISR; + SDADC3->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD3, isr); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; +#if STM32_ADC_USE_SDADC + ADCD1.sdadc = NULL; +#endif + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +#endif + +#if STM32_ADC_USE_SDADC1 + /* Driver initialization.*/ + adcObjectInit(&SDADCD1); +#if STM32_ADC_USE_ADC + SDADCD1.adc = NULL; +#endif + SDADCD1.sdadc = SDADC1; + SDADCD1.dmastp = STM32_DMA2_STREAM3; + SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC1_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY)); +#endif + +#if STM32_ADC_USE_SDADC2 + /* Driver initialization.*/ + adcObjectInit(&SDADCD2); +#if STM32_ADC_USE_ADC + SDADCD2.adc = NULL; +#endif + SDADCD2.sdadc = SDADC2; + SDADCD2.dmastp = STM32_DMA2_STREAM4; + SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC2_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY)); +#endif + +#if STM32_ADC_USE_SDADC3 + /* Driver initialization.*/ + adcObjectInit(&SDADCD3); +#if STM32_ADC_USE_ADC + SDADCD3.adc = NULL; +#endif + SDADCD3.sdadc = SDADC3; + SDADCD3.dmastp = STM32_DMA2_STREAM5; + SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC3_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY)); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + if (adcp->config == NULL) + adcp->config = &adc_lld_default_config; + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_SDADC1 + if (&SDADCD1 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); + rccEnableSDADC1(FALSE); + PWR->CR |= PWR_CR_SDADC1EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC1 */ + +#if STM32_ADC_USE_SDADC2 + if (&SDADCD2 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); + rccEnableSDADC1(FALSE); + PWR->CR |= PWR_CR_SDADC2EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC2 */ + +#if STM32_ADC_USE_SDADC3 + if (&SDADCD3 == adcp) { + bool_t b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); + rccEnableSDADC1(FALSE); + PWR->CR |= PWR_CR_SDADC3EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC3 */ + } + + adc_lld_reconfig(adcp); +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + rccDisableADC1(FALSE); + } +#endif + +#if STM32_ADC_USE_SDADC1 + if (&SDADCD1 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC1(FALSE); + PWR->CR &= ~PWR_CR_SDADC1EN; + } +#endif + +#if STM32_ADC_USE_SDADC2 + if (&SDADCD2 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC2(FALSE); + PWR->CR &= ~PWR_CR_SDADC2EN; + } +#endif + +#if STM32_ADC_USE_SDADC3 + if (&SDADCD3 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC3(FALSE); + PWR->CR &= ~PWR_CR_SDADC3EN; + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup* grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, + (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; + cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + if ((cr2 & ADC_CR2_SWSTART) != 0) + cr2 |= ADC_CR2_CONT; + adcp->adc->CR2 = cr2; + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->LTR = grpp->u.adc.ltr; + adcp->adc->HTR = grpp->u.adc.htr; + adcp->adc->SMPR1 = grpp->u.adc.smpr[0]; + adcp->adc->SMPR2 = grpp->u.adc.smpr[1]; + adcp->adc->SQR1 = grpp->u.adc.sqr[0] | + ADC_SQR1_NUM_CH(grpp->num_channels); + adcp->adc->SQR2 = grpp->u.adc.sqr[1]; + adcp->adc->SQR3 = grpp->u.adc.sqr[2]; + + /* ADC conversion start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN; + adcp->adc->CR2 = adcp->adc->CR2; /* Triggers the conversion start.*/ + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) | + SDADC_CR2_ADON; + if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0) + cr2 |= SDADC_CR2_JCONT; + + /* Entering initialization mode.*/ + adcp->sdadc->CR1 |= SDADC_CR1_INIT; + while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) + ; + + /* SDADC setup.*/ + adcp->sdadc->JCHGR = grpp->u.sdadc.jchgr; + adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0]; + adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1]; + + /* Leaving initialization mode.*/ + adcp->sdadc->CR1 &= ~SDADC_CR1_INIT; + + /* SDADC conversion start, the start is performed using the method + specified in the CR2 configuration, usually SDADC_CR2_JSWSTART.*/ + adcp->sdadc->CR2 = cr2; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else { + chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + /* Disabling the associated DMA stream.*/ + dmaStreamDisable(adcp->dmastp); + + /* Stopping and restarting the whole ADC, apparently the only way to stop + a conversion.*/ + adc_lld_reconfig(adcp); +} + +/** + * @brief Calibrates an ADC unit. + * @note The calibration must be performed after calling @p adcStart(). + * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT + * has been + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcSTM32Calibrate(ADCDriver *adcp) { + + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), + "adcSTM32Calibrate(), #1", "not ready"); + +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + /* Resetting calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + /* Selecting a full calibration in three steps.*/ + adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) | + SDADC_CR2_CALIBCNT_1; + + /* Calibration.*/ + adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB; + while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) + ; + + /* Clearing the EOCALF flag.*/ + adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else { + chDbgAssert(FALSE, "adcSTM32Calibrate(), #2", "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableTSVREFE(void) { + + ADC1->CR2 |= ADC_CR2_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableTSVREFE(void) { + + ADC1->CR2 &= ~ADC_CR2_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableVBATE(void) { + + SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableVBATE(void) { + + SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT; +} +#endif /* STM32_ADC_USE_ADC */ + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/adc_lld.h b/os/hal/platforms/STM32F37x/adc_lld.h new file mode 100644 index 000000000..2258952b1 --- /dev/null +++ b/os/hal/platforms/STM32F37x/adc_lld.h @@ -0,0 +1,711 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/adc_lld.h + * @brief STM32F37x ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/** + * @name SDADC JCHGR bit definitions + * @{ + */ +#define SDADC_JCHG_MASK (511U << 0) +#define SDADC_JCHG(n) (1U << (n)) +/** @} */ + +/** + * @name SDADC channels definitions + * @{ + */ +#define SDADC_CHANNEL_0 SDADC_JCHG(0) +#define SDADC_CHANNEL_1 SDADC_JCHG(1) +#define SDADC_CHANNEL_2 SDADC_JCHG(2) +#define SDADC_CHANNEL_3 SDADC_JCHG(3) +#define SDADC_CHANNEL_4 SDADC_JCHG(4) +#define SDADC_CHANNEL_5 SDADC_JCHG(5) +#define SDADC_CHANNEL_6 SDADC_JCHG(6) +#define SDADC_CHANNEL_7 SDADC_JCHG(7) +#define SDADC_CHANNEL_8 SDADC_JCHG(8) +#define SDADC_CHANNEL_9 SDADC_JCHG(9) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief SDADC1 driver enable switch. + * @details If set to @p TRUE the support for SDADC1 is included. + */ +#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC1 FALSE +#endif + +/** + * @brief SDADC2 driver enable switch. + * @details If set to @p TRUE the support for SDADC2 is included. + */ +#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC2 FALSE +#endif + +/** + * @brief SDADC3 driver enable switch. + * @details If set to @p TRUE the support for SDADC3 is included. + */ +#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC3 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC2 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC3 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief At least an ADC unit is in use. + */ +#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1 + +/** + * @brief At least an SDADC unit is in use. + */ +#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \ + STM32_ADC_USE_SDADC2 || \ + STM32_ADC_USE_SDADC3) + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1 +#error "SDADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2 +#error "SDADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3 +#error "SDADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC +#error "ADC driver activated but no ADC/SDADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC1" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC1 DMA" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC1" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC2" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC2 DMA" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC2" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC3" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC3 DMA" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC3" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + + /** + * @brief Union of ADC and SDADC config parms. The decision of which struct + * union to use is determined by the ADCDriver. If the ADCDriver adc parm + * is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm + * is not NULL, then use the sdadc struct. + */ + union { +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) + struct { + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC LTR register initialization data. + */ + uint32_t ltr; + /** + * @brief ADC HTR register initialization data. + */ + uint32_t htr; + /** + * @brief ADC SMPRx registers initialization data. + */ + uint32_t smpr[2]; + /** + * @brief ADC SQRx register initialization data. + */ + uint32_t sqr[3]; + } adc; +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) + struct { + /** + * @brief SDADC CR2 register initialization data. + * @note Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL + * and @p SDADC_CR2_JEXTEN can be specified in this field. + */ + uint32_t cr2; + /** + * @brief SDADC JCHGR register initialization data. + */ + uint32_t jchgr; + /** + * @brief SDADC CONFCHxR registers initialization data. + */ + uint32_t confchr[2]; + } sdadc; +#endif /* STM32_ADC_USE_SDADC */ + } u; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { +#if STM32_ADC_USE_SDADC + /** + * @brief SDADC CR1 register initialization data. + */ + uint32_t cr1; + /** + * @brief SDADC CONFxR registers initialization data. + */ + uint32_t confxr[3]; +#else /* !STM32_ADC_USE_SDADC */ + uint32_t dummy; +#endif /* !STM32_ADC_USE_SDADC */ +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; + +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; +#endif +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) + /** + * @brief Pointer to the SDADCx registers block. + */ + SDADC_TypeDef *sdadc; +#endif + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros for ADC + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/** + * @name Sequences building helper macros for SDADC + * @{ + */ +#define SDADC_JCHGR_CH(n) (1U << (n)) +/** @} */ + +/** + * @name Channel configuration number helper macros for SDADC + * @{ + */ +#define SDADC_CONFCHR1_CH0(n) ((n) << 0) +#define SDADC_CONFCHR1_CH1(n) ((n) << 4) +#define SDADC_CONFCHR1_CH2(n) ((n) << 8) +#define SDADC_CONFCHR1_CH3(n) ((n) << 12) +#define SDADC_CONFCHR1_CH4(n) ((n) << 16) +#define SDADC_CONFCHR1_CH5(n) ((n) << 20) +#define SDADC_CONFCHR1_CH6(n) ((n) << 24) +#define SDADC_CONFCHR1_CH7(n) ((n) << 28) +#define SDADC_CONFCHR2_CH8(n) ((n) << 0) +/** @} */ + +/** + * @name Configuration registers helper macros for SDADC + * @{ + */ +#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0) +#define SDADC_CONFR_OFFSET(n) ((n) << 0) +#define SDADC_CONFR_GAIN_MASK (7U << 20) +#define SDADC_CONFR_GAIN_1X (0U << 20) +#define SDADC_CONFR_GAIN_2X (1U << 20) +#define SDADC_CONFR_GAIN_4X (2U << 20) +#define SDADC_CONFR_GAIN_8X (3U << 20) +#define SDADC_CONFR_GAIN_16X (4U << 20) +#define SDADC_CONFR_GAIN_32X (5U << 20) +#define SDADC_CONFR_GAIN_0P5X (7U << 20) +#define SDADC_CONFR_SE_MASK (3U << 26) +#define SDADC_CONFR_SE_DIFF (0U << 26) +#define SDADC_CONFR_SE_OFFSET (1U << 26) +#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26) +#define SDADC_CONFR_COMMON_MASK (3U << 30) +#define SDADC_CONFR_COMMON_VSSSD (0U << 30) +#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30) +#define SDADC_CONFR_COMMON_VDDSD (2U << 30) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD1; +#endif + +#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD2; +#endif + +#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32Calibrate(ADCDriver *adcdp); +#if STM32_ADC_USE_ADC + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#endif /* STM32_ADC_USE_ADC */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/ext_lld_isr.c b/os/hal/platforms/STM32F37x/ext_lld_isr.c new file mode 100644 index 000000000..f43f3aecb --- /dev/null +++ b/os/hal/platforms/STM32F37x/ext_lld_isr.c @@ -0,0 +1,366 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/ext_lld_isr.c + * @brief STM32F37x EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_DISABLE_EXTI0_HANDLER) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector58) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI1_HANDLER) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector5C) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI2_HANDLER) +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector60) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI3_HANDLER) +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector64) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_HANDLER) +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector68) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(Vector44) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI17_HANDLER) +/** + * @brief EXTI[17] interrupt handler (RTC Alarm). + * + * @isr + */ +CH_IRQ_HANDLER(VectorE4) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI18_HANDLER) +/** + * @brief EXTI[18] interrupt handler (USB Wakeup). + * + * @isr + */ +CH_IRQ_HANDLER(VectorE8) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI19_HANDLER) +/** + * @brief EXTI[19] interrupt handler (Tamper TimeStamp). + * + * @isr + */ +CH_IRQ_HANDLER(Vector48) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI20_HANDLER) +/** + * @brief EXTI[20] interrupt handler (RTC Wakeup). + * + * @isr + */ +CH_IRQ_HANDLER(Vector4C) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI21_22_HANDLER) +/** + * @brief EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2). + * + * @isr + */ +CH_IRQ_HANDLER(Vector140) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 21) | (1 << 22)); + EXTI->PR = pr; + if (pr & (1 << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1 << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_TS_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); + nvicEnableVector(USBWakeUp_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(COMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY)); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_TS_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(USBWakeUp_IRQn); + nvicDisableVector(TAMPER_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/ext_lld_isr.h b/os/hal/platforms/STM32F37x/ext_lld_isr.h new file mode 100644 index 000000000..088012dc0 --- /dev/null +++ b/os/hal/platforms/STM32F37x/ext_lld_isr.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/ext_lld_isr.h + * @brief STM32F37x EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI5..9 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI10..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21..22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/hal_lld.c b/os/hal/platforms/STM32F37x/hal_lld.c new file mode 100644 index 000000000..a47ab59fc --- /dev/null +++ b/os/hal/platforms/STM32F37x/hal_lld.c @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/hal_lld.c + * @brief STM32F37x HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON; +#endif + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Clock settings.*/ + RCC->CFGR = STM32_SDPRE | STM32_MCOSEL | STM32_USBPRE | + STM32_PLLMUL | STM32_PLLSRC | STM32_ADCPRE | + STM32_PPRE1 | STM32_PPRE2 | STM32_HPRE; + RCC->CFGR2 = STM32_PREDIV; + RCC->CFGR3 = STM32_USART3SW | STM32_USART2SW | STM32_I2C2SW | + STM32_I2C1SW | STM32_USART1SW; + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif +#endif /* !STM32_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/hal_lld.h b/os/hal/platforms/STM32F37x/hal_lld.h new file mode 100644 index 000000000..96659baf3 --- /dev/null +++ b/os/hal/platforms/STM32F37x/hal_lld.h @@ -0,0 +1,1025 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/hal_lld.h + * @brief STM32F37x HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - STM32F37X for Analog & DSP devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" +#include "stm32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F37x Analog & DSP" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 24000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 72000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 + +/** + * @brief Minimum ADC clock frequency. + */ +#define STM32_ADCCLK_MIN 6000000 + +/** + * @brief Maximum SDADC clock frequency in fast mode. + */ +#define STM32_SDADCCLK_FAST_MAX 6000000 + +/** + * @brief Maximum SDADC clock frequency in slow mode. + */ +#define STM32_SDADCCLK_SLOW_MAX 1500000 + +/** + * @brief Minimum SDADC clock frequency. + */ +#define STM32_SDADCCLK_MIN 500000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 8000000 /**< High speed internal clock. */ +#define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7U << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0U << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1U << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2U << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3U << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4U << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5U << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6U << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7U << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0U << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1U << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2U << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0U << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8u << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9U << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10U << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11U << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12U << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13U << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14U << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15U << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0U << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4U << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5U << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6U << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7U << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0U << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4U << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5U << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6U << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7U << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0U << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1U << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2U << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3U << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0U << 16) /**< PLL clock source is HSI/2. */ +#define STM32_PLLSRC_HSE (1U << 16) /**< PLL clock source is + HSE/PREDIV. */ + +#define STM32_USBPRE_DIV1P5 (0U << 22) /**< USB clock is PLLCLK/1.5. */ +#define STM32_USBPRE_DIV1 (1U << 22) /**< USB clock is PLLCLK/1. */ + +#define STM32_MCOSEL_NOCLOCK (0U << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_LSI (2U << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (3U << 24) /**< LSE clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4U << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5U << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6U << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7U << 24) /**< PLL/2 clock on MCO pin. */ + +#define STM32_SDPRE_DIV2 (16U << 27) /**< SYSCLK divided by 2. */ +#define STM32_SDPRE_DIV4 (17U << 27) /**< SYSCLK divided by 4. */ +#define STM32_SDPRE_DIV6 (18U << 27) /**< SYSCLK divided by 6. */ +#define STM32_SDPRE_DIV8 (19U << 27) /**< SYSCLK divided by 8. */ +#define STM32_SDPRE_DIV10 (20U << 27) /**< SYSCLK divided by 10. */ +#define STM32_SDPRE_DIV12 (21U << 27) /**< SYSCLK divided by 12. */ +#define STM32_SDPRE_DIV14 (22U << 27) /**< SYSCLK divided by 14. */ +#define STM32_SDPRE_DIV16 (23U << 27) /**< SYSCLK divided by 16. */ +#define STM32_SDPRE_DIV20 (24U << 27) /**< SYSCLK divided by 20. */ +#define STM32_SDPRE_DIV24 (25U << 27) /**< SYSCLK divided by 24. */ +#define STM32_SDPRE_DIV28 (26U << 27) /**< SYSCLK divided by 28. */ +#define STM32_SDPRE_DIV32 (27U << 27) /**< SYSCLK divided by 32. */ +#define STM32_SDPRE_DIV36 (28U << 27) /**< SYSCLK divided by 36. */ +#define STM32_SDPRE_DIV40 (29U << 27) /**< SYSCLK divided by 40. */ +#define STM32_SDPRE_DIV44 (30U << 27) /**< SYSCLK divided by 44. */ +#define STM32_SDPRE_DIV48 (31U << 27) /**< SYSCLK divided by 48. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3U << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0U << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1U << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2U << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3U << 8) /**< HSE divided by 32 used as + RTC clock. */ +/** @} */ + +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ +#define STM32_PREDIV_MASK (15U << 0) /**< PREDIV divisor mask. */ +/** @} */ + +/** + * @name RCC_CFGR3 register bits definitions + * @{ + */ +#define STM32_USART1SW_MASK (3U << 0) /**< USART1 clock source mask. */ +#define STM32_USART1SW_PCLK (0U << 0) /**< USART1 clock is PCLK. */ +#define STM32_USART1SW_SYSCLK (1U << 0) /**< USART1 clock is SYSCLK. */ +#define STM32_USART1SW_LSE (2U << 0) /**< USART1 clock is LSE. */ +#define STM32_USART1SW_HSI (3U << 0) /**< USART1 clock is HSI. */ +#define STM32_I2C1SW_MASK (1U << 4) /**< I2C1 clock source mask. */ +#define STM32_I2C1SW_HSI (0U << 4) /**< I2C1 clock is HSI. */ +#define STM32_I2C1SW_SYSCLK (1U << 4) /**< I2C1 clock is SYSCLK. */ +#define STM32_I2C2SW_MASK (1U << 5) /**< I2C2 clock source mask. */ +#define STM32_I2C2SW_HSI (0U << 5) /**< I2C2 clock is HSI. */ +#define STM32_I2C2SW_SYSCLK (1U << 5) /**< I2C2 clock is SYSCLK. */ +#define STM32_USART2SW_MASK (3U << 16) /**< USART2 clock source mask. */ +#define STM32_USART2SW_PCLK (0U << 16) /**< USART2 clock is PCLK. */ +#define STM32_USART2SW_SYSCLK (1U << 16) /**< USART2 clock is SYSCLK. */ +#define STM32_USART2SW_LSE (2U << 16) /**< USART2 clock is LSE. */ +#define STM32_USART2SW_HSI (3U << 16) /**< USART2 clock is HSI. */ +#define STM32_USART3SW_MASK (3U << 18) /**< USART3 clock source mask. */ +#define STM32_USART3SW_PCLK (0U << 18) /**< USART3 clock is PCLK. */ +#define STM32_USART3SW_SYSCLK (1U << 18) /**< USART3 clock is SYSCLK. */ +#define STM32_USART3SW_LSE (2U << 18) /**< USART3 clock is LSE. */ +#define STM32_USART3SW_HSI (3U << 18) /**< USART3 clock is HSI. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV_VALUE 1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief SDADC prescaler value. + */ +#if !defined(STM32_SDPRE) || defined(__DOXYGEN__) +#define STM32_SDPRE STM32_SDPRE_DIV12 +#endif + +/** + * @brief USART1 clock source. + */ +#if !defined(STM32_USART1SW) || defined(__DOXYGEN__) +#define STM32_USART1SW STM32_USART1SW_PCLK +#endif + +/** + * @brief USART2 clock source. + */ +#if !defined(STM32_USART2SW) || defined(__DOXYGEN__) +#define STM32_USART2SW STM32_USART2SW_PCLK +#endif + +/** + * @brief USART3 clock source. + */ +#if !defined(STM32_USART3SW) || defined(__DOXYGEN__) +#define STM32_USART3SW STM32_USART3SW_PCLK +#endif + +/** + * @brief I2C1 clock source. + */ +#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__) +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#endif + +/** + * @brief I2C2 clock source. + */ +#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__) +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief USB prescaler initialization. + */ +#if !defined(STM32_USBPRE) || defined(__DOXYGEN__) +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32F37x_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if STM32_USART1SW == STM32_USART1SW_HSI +#error "HSI not enabled, required by STM32_USART1SW" +#endif + +#if STM32_USART2SW == STM32_USART2SW_HSI +#error "HSI not enabled, required by STM32_USART2SW" +#endif + +#if STM32_USART3SW == STM32_USART3SW_HSI +#error "HSI not enabled, required by STM32_USART3SW" +#endif + +#if STM32_I2C1SW == STM32_I2C1SW_HSI +#error "HSI not enabled, required by STM32_I2C1SW" +#endif + +#if STM32_I2C2SW == STM32_I2C2SW_HSI +#error "HSI not enabled, required by STM32_I2C2SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0) +#error "STM32_LSECLK not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + +#if STM32_USART1SW == STM32_USART1SW_LSE +#error "LSE not enabled, required by STM32_USART1SW" +#endif + +#if STM32_USART2SW == STM32_USART2SW_LSE +#error "LSE not enabled, required by STM32_USART2SW" +#endif + +#if STM32_USART3SW == STM32_USART3SW_LSE +#error "LSE not enabled, required by STM32_USART3SW" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + STM32_USB_CLOCK_REQUIRED || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) +#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 32) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC maximum frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/* ADC minimum frequency check.*/ +#if STM32_ADCCLK < STM32_ADCCLK_MIN +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MIN)" +#endif + +/** + * @brief SDADC frequency. + */ +#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 2) +#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 4) +#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 6) +#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 8) +#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 10) +#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 12) +#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 14) +#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 16) +#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 20) +#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 24) +#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 28) +#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 32) +#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 36) +#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 40) +#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 44) +#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__) +#define STM32_SDADCCLK (STM32_SYSCLK / 48) +#else +#error "invalid STM32_SDPRE value specified" +#endif + +/* SDADC maximum frequency check.*/ +#if STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX +#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)" +#endif + +/* SDADC minimum frequency check.*/ +#if STM32_SDADCCLK < STM32_SDADCCLK_MIN +#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)" +#endif + +/** + * @brief I2C1 frequency. + */ +#if STM32_I2C1SW == STM32_I2C1SW_HSI +#define STM32_I2C1CLK STM32_HSICLK +#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK +#define STM32_I2C1CLK STM32_SYSCLK +#else +#error "invalid source selected for I2C1 clock" +#endif + +/** + * @brief I2C2 frequency. + */ +#if STM32_I2C2SW == STM32_I2C2SW_HSI +#define STM32_I2C2CLK STM32_HSICLK +#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK +#define STM32_I2C2CLK STM32_SYSCLK +#else +#error "invalid source selected for I2C2 clock" +#endif + +/** + * @brief USART1 frequency. + */ +#if STM32_USART1SW == STM32_USART1SW_PCLK +#define STM32_USART1CLK STM32_PCLK2 +#elif STM32_USART1SW == STM32_USART1SW_SYSCLK +#define STM32_USART1CLK STM32_SYSCLK +#elif STM32_USART1SW == STM32_USART1SW_LSECLK +#define STM32_USART1CLK STM32_LSECLK +#elif STM32_USART1SW == STM32_USART1SW_HSICLK +#define STM32_USART1CLK STM32_HSICLK +#else +#error "invalid source selected for USART1 clock" +#endif + +/** + * @brief USART2 frequency. + */ +#if STM32_USART2SW == STM32_USART2SW_PCLK +#define STM32_USART2CLK STM32_PCLK1 +#elif STM32_USART2SW == STM32_USART2SW_SYSCLK +#define STM32_USART2CLK STM32_SYSCLK +#elif STM32_USART2SW == STM32_USART2SW_LSECLK +#define STM32_USART2CLK STM32_LSECLK +#elif STM32_USART2SW == STM32_USART2SW_HSICLK +#define STM32_USART2CLK STM32_HSICLK +#else +#error "invalid source selected for USART2 clock" +#endif + +/** + * @brief USART3 frequency. + */ +#if STM32_USART3SW == STM32_USART3SW_PCLK +#define STM32_USART3CLK STM32_PCLK1 +#elif STM32_USART3SW == STM32_USART3SW_SYSCLK +#define STM32_USART3CLK STM32_SYSCLK +#elif STM32_USART3SW == STM32_USART3SW_LSECLK +#define STM32_USART3CLK STM32_LSECLK +#elif STM32_USART3SW == STM32_USART3SW_HSICLK +#define STM32_USART3CLK STM32_HSICLK +#else +#error "invalid source selected for USART3 clock" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 15, 16, 17, 19 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief USB frequency. + */ +#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__) +#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3) +#elif (STM32_USBPRE == STM32_USBPRE_DIV1) +#define STM32_USBCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_USBPRE value specified" +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/platform.mk b/os/hal/platforms/STM32F37x/platform.mk new file mode 100644 index 000000000..47cc548aa --- /dev/null +++ b/os/hal/platforms/STM32F37x/platform.mk @@ -0,0 +1,27 @@ +# List of all the STM32F37x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F37x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F37x/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F37x/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F37x \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 diff --git a/os/hal/platforms/STM32F37x/stm32_dma.c b/os/hal/platforms/STM32F37x/stm32_dma.c new file mode 100644 index 000000000..b9ce0ddfc --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32_dma.c @@ -0,0 +1,450 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32F37x_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, + {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, + {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, + {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector6C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector70) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector74) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector7C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector120) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector124) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector128) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector12C) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector130) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + DMA2->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/stm32_dma.h b/os/hal/platforms/STM32F37x/stm32_dma.h new file mode 100644 index 000000000..79d295598 --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32_dma.h @@ -0,0 +1,406 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f30x.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32F37x_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA_STREAMS 12 +#else +#define STM32_DMA_STREAMS 7 +#endif + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR_EN +#define STM32_DMA_CR_TEIE DMA_CCR_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR_CIRC +#define STM32_DMA_CR_PINC DMA_CCR_PINC +#define STM32_DMA_CR_MINC DMA_CCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/stm32_isr.h b/os/hal/platforms/STM32F37x/stm32_isr.h new file mode 100644 index 000000000..30d98163e --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32_isr.h @@ -0,0 +1,126 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32F37x_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * CAN units. + */ +#define STM32_CAN1_TX_HANDLER Vector8C +#define STM32_CAN1_RX0_HANDLER Vector90 +#define STM32_CAN1_RX1_HANDLER Vector94 +#define STM32_CAN1_SCE_HANDLER Vector98 + +#define STM32_CAN1_TX_NUMBER 19 +#define STM32_CAN1_RX0_NUMBER 20 +#define STM32_CAN1_RX1_NUMBER 21 +#define STM32_CAN1_SCE_NUMBER 22 + +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_NUMBER 32 + +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_NUMBER 34 + +/* + * TIM units. + */ +#define STM32_TIM2_HANDLER VectorB0 +#define STM32_TIM3_HANDLER VectorB4 +#define STM32_TIM4_HANDLER VectorB8 +#define STM32_TIM5_HANDLER Vector108 +#define STM32_TIM6_HANDLER Vector118 +#define STM32_TIM7_HANDLER Vector11C +#define STM32_TIM12_HANDLER VectorEC +#define STM32_TIM14_HANDLER VectorF4 + +#define STM32_TIM2_NUMBER 28 +#define STM32_TIM3_NUMBER 29 +#define STM32_TIM4_NUMBER 30 +#define STM32_TIM5_NUMBER 50 +#define STM32_TIM6_NUMBER 54 +#define STM32_TIM7_NUMBER 55 +#define STM32_TIM12_NUMBER 43 +#define STM32_TIM14_NUMBER 45 + +/* + * USART units. + */ +#define STM32_USART1_HANDLER VectorD4 +#define STM32_USART2_HANDLER VectorD8 +#define STM32_USART3_HANDLER VectorDC + +#define STM32_USART1_NUMBER 37 +#define STM32_USART2_NUMBER 38 +#define STM32_USART3_NUMBER 39 + +/* + * USB units. + */ +#define STM32_USB1_HP_HANDLER Vector168 +#define STM32_USB1_LP_HANDLER Vector16C + +#define STM32_USB1_HP_NUMBER 74 +#define STM32_USB1_LP_NUMBER 75 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/stm32_rcc.h b/os/hal/platforms/STM32F37x/stm32_rcc.h new file mode 100644 index 000000000..607d9d7bc --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32_rcc.h @@ -0,0 +1,860 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f30x.h. + * + * @addtogroup STM32F37x_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC1 peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SDADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SDADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp) + +/** + * @brief Disables the SDADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDADC1(lp) rccDisableAPB2(RCC_APB2ENR_SDADC1EN, lp) + +/** + * @brief Resets the SDADC1 peripheral. + * + * @api + */ +#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST) + +/** + * @brief Enables the SDADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp) + +/** + * @brief Disables the SDADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDADC2(lp) rccDisableAPB2(RCC_APB2ENR_SDADC2EN, lp) + +/** + * @brief Resets the SDADC2 peripheral. + * + * @api + */ +#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST) + +/** + * @brief Enables the SDADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp) + +/** + * @brief Disables the SDADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDADC3(lp) rccDisableAPB2(RCC_APB2ENR_SDADC3EN, lp) + +/** + * @brief Resets the SDADC3 peripheral. + * + * @api + */ +#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) +/** @} */ + +/** + * @brief Enables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) +/** @} */ + +/** + * @brief Enables the TIM12 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Disables the TIM12 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Resets the TIM12 peripheral. + * + * @api + */ +#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) +/** @} */ + +/** + * @brief Enables the TIM14 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/stm32_registry.h b/os/hal/platforms/STM32F37x/stm32_registry.h new file mode 100644 index 000000000..8f0842263 --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32_registry.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/stm32_registry.h + * @brief STM32F37x capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_REGISTRY_H_ +#define _STM32_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F37x capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_ADC2_DMA_MSK 0 +#define STM32_ADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC3 FALSE +#define STM32_ADC3_DMA_MSK 0 +#define STM32_ADC3_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC4 FALSE +#define STM32_ADC4_DMA_MSK 0 +#define STM32_ADC4_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC1 TRUE +#define STM32_SDADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SDADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC2 TRUE +#define STM32_SDADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SDADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_SDADC3 TRUE +#define STM32_SDADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SDADC3_DMA_CHN 0x00000000 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 29 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 FALSE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 TRUE +#define STM32_HAS_TIM19 TRUE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +#endif /* _STM32_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F37x/stm32f37x.h b/os/hal/platforms/STM32F37x/stm32f37x.h new file mode 100644 index 000000000..d9b8d66ec --- /dev/null +++ b/os/hal/platforms/STM32F37x/stm32f37x.h @@ -0,0 +1,5442 @@ +/** + ****************************************************************************** + * @file stm32f37x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F37x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE + * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f37x + * @{ + */ + +#ifndef __STM32F37x_H +#define __STM32F37x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F37X) + #define STM32F37X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F37X) + #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F37x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F37X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F37X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F37X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F37X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F37X_STDPERIPH_VERSION ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F37X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F37X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F37X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F37X provide an FPU */ + + +/** + * @brief STM32F37X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM15_IRQn = 24, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 25, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 26, /*!< TIM17 global Interrupt */ + TIM18_DAC2_IRQn = 27, /*!< TIM18 global Interrupt and DAC2 underrun Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + SDADC1_IRQn = 61, /*!< ADC Sigma Delta 1 global Interrupt */ + SDADC2_IRQn = 62, /*!< ADC Sigma Delta 2 global Interrupt */ + SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ + USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */ + TIM19_IRQn = 78, /*!< TIM19 global Interrupt */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* CHIBIOS FIX */ +/*#include "system_stm32f37x.h"*/ /* STM32F37x System Header */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ + defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + +#if STM32_ADC_USE_ADC1 + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + sr = ADC2->SR; + ADC2->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD2.grpp != NULL) + _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + sr = ADC3->SR; + ADC3->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD3.grpp != NULL) + _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC3 */ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC2 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD2.adc = ADC2; + ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); + ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC3 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD3.adc = ADC3; + ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); + ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); + rccEnableADC2(FALSE); + } +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); + rccEnableADC3(FALSE); + } +#endif /* STM32_ADC_USE_ADC3 */ + + /* This is a common register but apparently it requires that at least one + of the ADCs is clocked in order to allow writing, see bug 3575297.*/ + ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) | + (STM32_ADC_ADCPRE << 16); + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) + rccDisableADC2(FALSE); +#endif + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) + rccDisableADC3(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + if ((grpp->cr2 & ADC_CR2_SWSTART) != 0) + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; + else + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * @note This function is meant to be called after @p adcStart(). + */ +void adcSTM32EnableVBATE(void) { + + ADC->CCR |= ADC_CCR_VBATE; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * @note This function is meant to be called after @p adcStart(). + */ +void adcSTM32DisableVBATE(void) { + + ADC->CCR &= ~ADC_CCR_VBATE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h new file mode 100644 index 000000000..7cda791ac --- /dev/null +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -0,0 +1,567 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/adc_lld.h + * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Minimum ADC clock frequency. + */ +#define STM32_ADCCLK_MIN 600000 + +/** + * @brief Maximum ADC clock frequency. + */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#define STM32_ADCCLK_MAX 36000000 +#else +#define STM32_ADCCLK_MAX 30000000 +#endif +/** @} */ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. + @note Available onADC1 only. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ +#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ +#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ +#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ +#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ +#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ +#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ +#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the datasheet for more + * info.
    + * See section 5.3.20 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#endif + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC2 driver enable switch. + * @details If set to @p TRUE the support for ADC2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC2 FALSE +#endif + +/** + * @brief ADC3 driver enable switch. + * @details If set to @p TRUE the support for ADC3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC3 FALSE +#endif + +/** + * @brief DMA stream used for ADC1 operations. + */ +#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#endif + +/** + * @brief DMA stream used for ADC2 operations. + */ +#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif + +/** + * @brief DMA stream used for ADC3 operations. + */ +#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + * @note This setting is shared among ADC1, ADC2 and ADC3 because + * all ADCs share the same vector. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 +#error "ADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 +#error "ADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) +#error "invalid DMA stream associated to ADC1" +#endif + +#if STM32_ADC_USE_ADC2 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) +#error "invalid DMA stream associated to ADC2" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) +#error "invalid DMA stream associated to ADC3" +#endif + +/* ADC clock related settings and checks.*/ +#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADC_ADCPRE value specified" +#endif + +#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) +#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...18. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/os/hal/platforms/STM32F4xx/ext_lld_isr.c new file mode 100644 index 000000000..5576ff834 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/ext_lld_isr.c @@ -0,0 +1,353 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/ext_lld_isr.c + * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI0_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(PVD_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 21); + EXTD1.config->channels[21].cb(&EXTD1, 21); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[22] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 22); + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); + nvicEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(OTG_HS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(TAMP_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); + nvicDisableVector(OTG_HS_WKUP_IRQn); + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.h b/os/hal/platforms/STM32F4xx/ext_lld_isr.h new file mode 100644 index 000000000..33e8e0be1 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/ext_lld_isr.h @@ -0,0 +1,170 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/ext_lld_isr.h + * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c new file mode 100644 index 000000000..f72812da9 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -0,0 +1,238 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/hal_lld.c + * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +/* TODO: LSEBYP like in F3.*/ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals. AHB3 is not reseted because it could have + been initialized in the board initialization file (board.c).*/ + rccResetAHB1(~0); + rccResetAHB2(~0); + rccResetAHB3(~0); + rccResetAPB1(~RCC_APB1RSTR_PWRRST); + rccResetAPB2(~0); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32F2xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* PWR initialization.*/ +#if defined(STM32F4XX) || defined(__DOXYGEN__) + PWR->CR = STM32_VOS; + while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) + ; /* Waits until power regulator is stable. */ +#else + PWR->CR = 0; +#endif + + /* Initial clocks setup and wait for HSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON; +#endif + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->BDCR |= RCC_BDCR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | + STM32_PLLM; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + +#if STM32_ACTIVATE_PLLI2S + /* PLLI2S activation.*/ + RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; + RCC->CR |= RCC_CR_PLLI2SON; + while (!(RCC->CR & RCC_CR_PLLI2SRDY)) + ; /* Waits until PLLI2S is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Flash setup.*/ +#if defined(STM32_USE_REVISION_A_FIX) + /* Some old revisions of F4x MCUs randomly crashes with compiler + optimizations enabled AND flash caches enabled. */ + if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241)) + FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS; + else + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | + FLASH_ACR_DCEN | STM32_FLASHBITS; +#else + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | + FLASH_ACR_DCEN | STM32_FLASHBITS; +#endif + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h new file mode 100644 index 000000000..0a7291420 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -0,0 +1,1549 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/hal_lld.h + * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * - STM32_VDD (as hundredths of Volt). + * . + * One of the following macros must also be defined: + * - STM32F2XX for High-performance STM32 F-2 devices. + * - STM32F4XX for High-performance STM32 F-4 devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F4xx High Performance" +#else /* !defined(STM32F4XX) */ +#define PLATFORM_NAME "STM32F2xx High Performance" +#endif /* !defined(STM32F4XX) */ +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 26000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 2000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 950000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MAX 432000000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MIN 192000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 168000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 24000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 42000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 84000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 37500000 + +#else /* !defined(STM32F4XX) */ +#define STM32_SYSCLK_MAX 120000000 +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_MIN 1000000 +#define STM32_LSECLK_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2000000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLOUT_MAX 120000000 +#define STM32_PLLOUT_MIN 24000000 +#define STM32_PCLK1_MAX 30000000 +#define STM32_PCLK2_MAX 60000000 +#define STM32_SPII2S_MAX 37500000 +#endif /* !defined(STM32F4XX) */ +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 32000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */ +#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ +#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */ +#endif +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MASK (3 << 0) /**< SW mask. */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ + +#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ +#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ +#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ + +#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ +#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ +#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ + +#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ +#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ +#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ +#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ +#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ +#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ + +#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ +#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ +#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ +#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ +#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ +#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ + +#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ + +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable + prescaler used as RTC clock*/ + +/** + * @name RCC_PLLI2SCFGR register bits definitions + * @{ + */ +#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F4xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +#define STM32_HAS_ADC4 FALSE +#define STM32_ADC4_DMA_MSK 0x00000000 +#define STM32_ADC4_DMA_CHN 0x00000000 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 23 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) | \ + (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#define STM32_RTC_HAS_SUBSECONDS TRUE +#else +#define STM32_RTC_HAS_SUBSECONDS FALSE +#endif +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 TRUE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp + through EXTI Line. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ +#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ +#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ +#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ +#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ +#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ +#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ +#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B) + through EXTI line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ +#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ +#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ +#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ +#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ +#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ +#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ +#define USART6_IRQHandler Vector15C /**< USART6. */ +#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ +#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ +#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ +#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ +#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through + EXTI line. */ +#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ +#define DCMI_IRQHandler Vector178 /**< DCMI. */ +#define CRYP_IRQHandler Vector17C /**< CRYP. */ +#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */ +#endif +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief USB/SDIO clock setting. + */ +#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define STM32_CLOCK48_REQUIRED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +#if defined(STM32F4XX) || defined(__DOXYGEN__) +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_HIGH +#endif + +/** + * @brief Clock source for the PLLs. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 8 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 336 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ multiplier value. + * @note The allowed values are 2..15. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 7 +#endif + +#else /* !defined(STM32F4XX) */ +/** + * @brief Clock source for the PLLs. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 8 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 240 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ multiplier value. + * @note The allowed values are 2..15. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 5 +#endif +#endif /* !defined(STM32F4XX) */ + +/** + * @brief AHB prescaler value. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief RTC HSE prescaler value. + */ +#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#define STM32_RTCPRE_VALUE 8 +#endif + +/** + * @brief MC01 clock source value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#endif + +/** + * @brief MC01 prescaler value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#endif + +/** + * @brief MC02 clock source value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#endif + +/** + * @brief MC02 prescaler value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#endif + +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 192..432. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 192 +#endif + +/** + * @brief PLLI2SR multiplier value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(STM32F4XX) || defined(__DOXYGEN__) +/* + * Configuration-related checks. + */ +#if !defined(STM32F4xx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined" +#endif + +/** + * @brief Maximum SYSCLK. + * @note It is a function of the core voltage setting. + */ +#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__) +#define STM32_SYSCLK_MAX 168000000 +#else +#define STM32_SYSCLK_MAX 144000000 +#endif + +#else /* !defined(STM32F4XX) */ +/* + * Configuration-related checks. + */ +#if !defined(STM32F2xx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined" +#endif +#endif /* !defined(STM32F4XX) */ + +/** + * @brief Maximum frequency thresholds and wait states for flash access. + * @note The values are valid for 2.7V to 3.6V supply range. + */ +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 150000000 +#define STM32_5WS_THRESHOLD 168000000 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 144000000 +#define STM32_6WS_THRESHOLD 168000000 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +#define STM32_3WS_THRESHOLD 72000000 +#define STM32_4WS_THRESHOLD 90000000 +#define STM32_5WS_THRESHOLD 108000000 +#define STM32_6WS_THRESHOLD 120000000 +#define STM32_7WS_THRESHOLD 138000000 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 16000000 +#define STM32_1WS_THRESHOLD 32000000 +#define STM32_2WS_THRESHOLD 48000000 +#define STM32_3WS_THRESHOLD 64000000 +#define STM32_4WS_THRESHOLD 80000000 +#define STM32_5WS_THRESHOLD 96000000 +#define STM32_6WS_THRESHOLD 112000000 +#define STM32_7WS_THRESHOLD 128000000 +#else +#error "invalid VDD voltage specified" +#endif + +#else /* !defined(STM32F4XX) */ +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +#define STM32_3WS_THRESHOLD 72000000 +#define STM32_4WS_THRESHOLD 90000000 +#define STM32_5WS_THRESHOLD 108000000 +#define STM32_6WS_THRESHOLD 120000000 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 16000000 +#define STM32_1WS_THRESHOLD 32000000 +#define STM32_2WS_THRESHOLD 48000000 +#define STM32_3WS_THRESHOLD 64000000 +#define STM32_4WS_THRESHOLD 80000000 +#define STM32_5WS_THRESHOLD 96000000 +#define STM32_6WS_THRESHOLD 112000000 +#define STM32_7WS_THRESHOLD 120000000 +#else +#error "invalid VDD voltage specified" +#endif +#endif /* !defined(STM32F4XX) */ + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSI) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_I2SSRC" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_I2SSRC" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM (STM32_PLLM_VALUE << 0) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* + * PLLs input frequency range check. + */ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLL enable check. + */ +#if STM32_CLOCK48_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 6) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLP field. + */ +#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLP (0 << 16) +#elif STM32_PLLP_VALUE == 4 +#define STM32_PLLP (1 << 16) +#elif STM32_PLLP_VALUE == 6 +#define STM32_PLLP (2 << 16) +#elif STM32_PLLP_VALUE == 8 +#define STM32_PLLP (3 << 16) +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/* + * PLL output frequency range check. + */ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* + * AHB frequency check. + */ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/* + * PLLI2S enable check. + */ +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLLI2S TRUE +#else +#define STM32_ACTIVATE_PLLI2S FALSE +#endif + +/** + * @brief STM32_PLLI2SN field. + */ +#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) +#else +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SR field. + */ +#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) +#else +#error "invalid STM32_PLLI2SR_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S output clock frequency. + */ +#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) + +/** + * @brief MCO1 divider clock. + */ +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) +#define STM32_MCO1DIVCLK STM32_HSICLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE +#define STM32_MCO1DIVCLK STM32_LSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE +#define STM32_MCO1DIVCLK STM32_HSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL +#define STM32_MCO1DIVCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_MCO1SEL value specified" +#endif + +/** + * @brief MCO1 output pin clock. + */ +#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO1CLK STM32_MCO1DIVCLK +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) +#else +#error "invalid STM32_MCO1PRE value specified" +#endif + +/** + * @brief MCO2 divider clock. + */ +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) +#define STM32_MCO2DIVCLK STM32_HSECLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL +#define STM32_MCO2DIVCLK STM32_PLLCLKOUT +#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK +#define STM32_MCO2DIVCLK STM32_SYSCLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S +#define STM32_MCO2DIVCLK STM32_PLLI2S +#else +#error "invalid STM32_MCO2SEL value specified" +#endif + +/** + * @brief MCO2 output pin clock. + */ +#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO2CLK STM32_MCO2DIVCLK +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) +#else +#error "invalid STM32_MCO2PRE value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief 48MHz frequency. + */ +#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#else +#define STM32_PLL48CLK 0 +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000000 +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS 0x00000001 +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS 0x00000002 +#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#define STM32_FLASHBITS 0x00000003 +#elif STM32_HCLK <= STM32_4WS_THRESHOLD +#define STM32_FLASHBITS 0x00000004 +#elif STM32_HCLK <= STM32_5WS_THRESHOLD +#define STM32_FLASHBITS 0x00000005 +#elif STM32_HCLK <= STM32_6WS_THRESHOLD +#define STM32_FLASHBITS 0x00000006 +#else +#define STM32_FLASHBITS 0x00000007 +#endif + +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/platform.dox b/os/hal/platforms/STM32F4xx/platform.dox new file mode 100644 index 000000000..38e98bd59 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/platform.dox @@ -0,0 +1,364 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32F4xx_DRIVERS STM32F4xx/STM32F2xx Drivers + * @details This section describes all the supported drivers on the STM32F4xx + * and STM32F2xx platform and the implementation details of the single + * drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support + * @details The STM32F4xx HAL support is responsible for system initialization. + * + * @section stm32f4xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2. + * - RCC. + * - Flash. + * . + * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ADC STM32F4xx ADC Support + * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_adc_1 Supported HW resources + * - ADC1. + * - ADC2. + * - ADC3. + * - DMA2. + * . + * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_CAN STM32F4xx CAN Support + * @details The STM32F4xx CAN driver uses the CAN peripherals. + * + * @section stm32f4xx_can_1 Supported HW resources + * - bxCAN1. + * . + * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Support for bxCAN sleep mode. + * - Programmable bxCAN interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_EXT STM32F4xx EXT Support + * @details The STM32F4xx EXT driver uses the EXTI peripheral. + * + * @section stm32f4xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_GPT STM32F4xx GPT Support + * @details The STM32F4xx GPT driver uses the TIMx peripherals. + * + * @section stm32f4xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ICU STM32F4xx ICU Support + * @details The STM32F4xx ICU driver uses the TIMx peripherals. + * + * @section stm32f4xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_MAC STM32F4xx MAC Support + * @details The STM32F4xx MAC driver supports the ETH peripheral. + * + * @section stm32f4xx_mac_1 Supported HW resources + * - ETH. + * - PHY (external). + * . + * @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features + * - Dedicated DMA operations. + * - Support for checksum off-loading. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PAL STM32F4xx PAL Support + * @details The STM32F4xx PAL driver uses the GPIO peripherals. + * + * @section stm32f4xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH. + * - GPIOI. + * . + * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f4xx_pal_3 Supported PAL setup modes + * The STM32F4xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f4xx_pal_4 Suboptimal behavior + * The STM32F4xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PWM STM32F4xx PWM Support + * @details The STM32F4xx PWM driver uses the TIMx peripherals. + * + * @section stm32f4xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SDC STM32F4xx SDC Support + * @details The STM32F4xx SDC driver uses the SDIO peripheral. + * + * @section stm32f4xx_sdc_1 Supported HW resources + * - SDIO. + * - DMA2. + * . + * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support + * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f4xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - UART4. + * - UART5. + * - USART6. + * . + * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SPI STM32F4xx SPI Support + * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_UART STM32F4xx UART Support + * @details The UART driver supports the STM32F4xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_DMA STM32F4xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f4xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ISR STM32F4xx ISR Support + * @details This ISR helper driver is used by the other drivers in order to + * map ISR names to physical vector names. + * + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F4xx_RCC STM32F4xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f4xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk new file mode 100644 index 000000000..813630b87 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -0,0 +1,29 @@ +# List of all the STM32F2xx/STM32F4xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c new file mode 100644 index 000000000..cd5f5b2e1 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -0,0 +1,528 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/stm32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup STM32F4xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x000000FF + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x0000FF00 + +/** + * @brief Post-reset value of the stream CR register. + */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000 + +/** + * @brief Post-reset value of the stream FCR register. + */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn}, + {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn}, + {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn}, + {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn}, + {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn}, + {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn}, + {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn}, + {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn}, + {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn}, + {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn}, + {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn}, + {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn}, + {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn}, + {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn}, + {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn}, + {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[12].dma_func) + dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[13].dma_func) + dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[14].dma_func) + dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[15].dma_func) + dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].stream->CR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->LIFCR = 0xFFFFFFFF; + DMA1->HIFCR = 0xFFFFFFFF; + DMA2->LIFCR = 0xFFFFFFFF; + DMA2->HIFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h new file mode 100644 index 000000000..62b0fbd43 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -0,0 +1,461 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/stm32_dma.h + * @brief Enhanced-DMA helper driver header. + * @note This file requires definitions from the ST STM32F4xx header file + * stm32f4xx.h. + * + * @addtogroup STM32F4xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 16 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x3D + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] id the unique numeric stream identifier + * @param[in] c a stream/channel association word, one channel per + * nibble + * @return Returns the channel associated to the stream. + */ +#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7) + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) +#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) +#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_SxCR_EN +#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE +#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE +#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE +#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 +#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 +#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC +#define STM32_DMA_CR_PINC DMA_SxCR_PINC +#define STM32_DMA_CR_MINC DMA_SxCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 16) +/** @} */ + +/** + * @name CR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE +#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL +#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS +#define STM32_DMA_CR_DBM DMA_SxCR_DBM +#define STM32_DMA_CR_CT DMA_SxCR_CT +#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST +#define STM32_DMA_CR_PBURST_SINGLE 0 +#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 +#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 +#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) +#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST +#define STM32_DMA_CR_MBURST_SINGLE 0 +#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 +#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 +#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) +#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL +#define STM32_DMA_CR_CHSEL(n) ((n) << 25) +/** @} */ + +/** + * @name FCR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE +#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS +#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS +#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH +#define STM32_DMA_FCR_FTH_1Q 0 +#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 +#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 +#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 +#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 +#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 +#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 +#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the xISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the PAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->PAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M0AR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->M0AR = (uint32_t)(addr); \ +} + +/** + * @brief Associates an alternate memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M1AR register + * + * @special + */ +#define dmaStreamSetMemory1(dmastp, addr) { \ + (dmastp)->stream->M1AR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->stream->NDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CR = (uint32_t)(mode); \ +} + +/** + * @brief Programs the stream FIFO settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the FCR register + * + * @special + */ +#define dmaStreamSetFIFO(dmastp, mode) { \ + (dmastp)->stream->FCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream, waits for the disable + * operation to complete and then clears any pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \ + STM32_DMA_CR_EN); \ + while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \ + ; \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->stream->NDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32_isr.h b/os/hal/platforms/STM32F4xx/stm32_isr.h new file mode 100644 index 000000000..fc655165a --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_isr.h @@ -0,0 +1,150 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32F4xx_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * CAN units. + */ +#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler +#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler +#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler +#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler +#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler +#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler +#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler +#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler + +#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn +#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn +#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn +#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn +#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn +#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn +#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn +#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn + +/* + * OTG units. + */ +#define STM32_OTG1_HANDLER Vector14C +#define STM32_OTG2_HANDLER Vector174 +#define STM32_OTG2_EP1OUT_HANDLER Vector168 +#define STM32_OTG2_EP1IN_HANDLER Vector16C + +#define STM32_OTG1_NUMBER OTG_FS_IRQn +#define STM32_OTG2_NUMBER OTG_HS_IRQn +#define STM32_OTG2_EP1OUT_NUMBER OTG_HS_EP1_OUT_IRQn +#define STM32_OTG2_EP1IN_NUMBER OTG_HS_EP1_IN_IRQn + +/* + * SDIO unit. + */ +#define STM32_SDIO_HANDLER SDIO_IRQHandler + +#define STM32_SDIO_NUMBER SDIO_IRQn + +/* + * TIM units. + */ +#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler +#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler +#define STM32_TIM2_HANDLER TIM2_IRQHandler +#define STM32_TIM3_HANDLER TIM3_IRQHandler +#define STM32_TIM4_HANDLER TIM4_IRQHandler +#define STM32_TIM5_HANDLER TIM5_IRQHandler +#define STM32_TIM6_HANDLER TIM6_IRQHandler +#define STM32_TIM7_HANDLER TIM7_IRQHandler +#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler +#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler +#define STM32_TIM9_HANDLER TIM1_BRK_IRQHandler +#define STM32_TIM11_HANDLER TIM1_TRG_COM_IRQHandler +#define STM32_TIM12_HANDLER TIM8_BRK_IRQHandler +#define STM32_TIM14_HANDLER TIM8_TRG_COM_IRQHandler + +#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn +#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn +#define STM32_TIM2_NUMBER TIM2_IRQn +#define STM32_TIM3_NUMBER TIM3_IRQn +#define STM32_TIM4_NUMBER TIM4_IRQn +#define STM32_TIM5_NUMBER TIM5_IRQn +#define STM32_TIM6_NUMBER TIM6_IRQn +#define STM32_TIM7_NUMBER TIM7_IRQn +#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn +#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn +#define STM32_TIM9_NUMBER TIM1_BRK_TIM9_IRQn +#define STM32_TIM11_NUMBER TIM1_TRG_COM_TIM11_IRQn +#define STM32_TIM12_NUMBER TIM8_BRK_TIM12_IRQn +#define STM32_TIM14_NUMBER TIM8_TRG_COM_TIM14_IRQn + +/* + * USART units. + */ +#define STM32_USART1_HANDLER USART1_IRQHandler +#define STM32_USART2_HANDLER USART2_IRQHandler +#define STM32_USART3_HANDLER USART3_IRQHandler +#define STM32_UART4_HANDLER UART4_IRQHandler +#define STM32_UART5_HANDLER UART5_IRQHandler +#define STM32_USART6_HANDLER USART6_IRQHandler + +#define STM32_USART1_NUMBER USART1_IRQn +#define STM32_USART2_NUMBER USART2_IRQn +#define STM32_USART3_NUMBER USART3_IRQn +#define STM32_UART4_NUMBER UART4_IRQn +#define STM32_UART5_NUMBER UART5_IRQn +#define STM32_USART6_NUMBER USART6_IRQn +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h new file mode 100644 index 000000000..d87bc2ab2 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -0,0 +1,1254 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f4xx.h. + * + * @addtogroup STM32F4xx_RCC + * @{ + */ +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB1(mask, lp) { \ + RCC->AHB1ENR &= ~(mask); \ + if (lp) \ + RCC->AHB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB2(mask, lp) { \ + RCC->AHB2ENR &= ~(mask); \ + if (lp) \ + RCC->AHB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB3(mask, lp) { \ + RCC->AHB3ENR &= ~(mask); \ + if (lp) \ + RCC->AHB3LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) + +/** + * @brief Enables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Disables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Resets the ADC2 peripheral. + * + * @api + */ +#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) + +/** + * @brief Enables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Disables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Resets the ADC3 peripheral. + * + * @api + */ +#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) + +/** + * @brief Enables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Disables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Resets the CAN2 peripheral. + * + * @api + */ +#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) +/** @} */ + +/** + * @name OTG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) + +/** + * @brief Enables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp) + +/** + * @brief Disables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp) + +/** + * @brief Resets the OTG_HS peripheral. + * + * @api + */ +#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST) +/** @} */ + +/** + * @name SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) + +/** + * @brief Enables the TIM7 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) + +/** + * @brief Enables the TIM89peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM9 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) + +/** + * @brief Enables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Disables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Resets the TIM11 peripheral. + * + * @api + */ +#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) + +/** + * @brief Enables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Disables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Resets the TIM12 peripheral. + * + * @api + */ +#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Disables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) + +/** + * @brief Resets the USART6 peripheral. + * + * @api + */ +#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32f2xx.h b/os/hal/platforms/STM32F4xx/stm32f2xx.h new file mode 100644 index 000000000..f4506b2fe --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32f2xx.h @@ -0,0 +1,6881 @@ +/** + ****************************************************************************** + * @file stm32f2xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F2xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral�s drivers in application code(i.e. + * code will be based on direct access to peripheral�s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx + * @{ + */ + +#ifndef __STM32F2xx_H +#define __STM32F2xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F2XX) + #define STM32F2XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F2XX) + #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F2XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/* #include "system_stm32f2xx.h" */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; /* added for STM32F2xx */ + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; /* added for STM32F2xx */ + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ +} GPIO_TypeDef; +#endif + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved, 0x38 */ + uint32_t RESERVED4; /*!< Reserved, 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved, 0x44 */ + uint32_t RESERVED6; /*!< Reserved, 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!
    © COPYRIGHT 2011 STMicroelectronics
    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F4XX) + #define STM32F4XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F4XX) + #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F4XX Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F4XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* CHIBIOS FIX */ +/*#include "system_stm32f4xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; +#endif + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock and analog part.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SMPR3 = grpp->smpr3; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->SQR4 = grpp->sqr4; + adcp->adc->SQR5 = grpp->sqr5; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + if ((grpp->cr2 & ADC_CR2_SWSTART) != 0) + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; + else + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h new file mode 100644 index 000000000..2ac857c16 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -0,0 +1,484 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/adc_lld.h + * @brief STM32L1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV1 0 +#define ADC_CCR_ADCPRE_DIV2 1 +#define ADC_CCR_ADCPRE_DIV4 2 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ +#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ +#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ +#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ +#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ +#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ +#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ +#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ +#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ +#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ +#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ +#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ +#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ +#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
    + * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 20...25. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...19. + */ + uint32_t smpr2; + /** + * @brief ADC SMPR3 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr3; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 25...27 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 19...24. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 13...18. + */ + uint32_t sqr3; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr4; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr5; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ +#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ + +#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ +#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ +#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ +#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ +#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ +#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ + +#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ +#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ +#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ + +#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ +#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ +#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ +#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ +#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ +#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/ext_lld_isr.c b/os/hal/platforms/STM32L1xx/ext_lld_isr.c new file mode 100644 index 000000000..ea9259a69 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/ext_lld_isr.c @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/ext_lld_isr.c + * @brief STM32L1xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI0_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(PVD_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21]...EXTI[22] interrupt handler (COMP). + * + * @isr + */ +CH_IRQ_HANDLER(COMP_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 21) | (1 << 22)); + EXTI->PR = pr; + if (pr & (1 << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1 << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); + nvicEnableVector(USB_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(COMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY)); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(USB_FS_WKUP_IRQn); + nvicDisableVector(TAMPER_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/ext_lld_isr.h b/os/hal/platforms/STM32L1xx/ext_lld_isr.h new file mode 100644 index 000000000..9ee4db42e --- /dev/null +++ b/os/hal/platforms/STM32L1xx/ext_lld_isr.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/ext_lld_isr.h + * @brief STM32L1xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21..22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c new file mode 100644 index 000000000..529099e6a --- /dev/null +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -0,0 +1,236 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/hal_lld.c + * @brief STM32L1xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +/* TODO: LSEBYP like in F3.*/ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->CSR |= RCC_CSR_RTCRST; + RCC->CSR &= ~RCC_CSR_RTCRST; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->CSR |= RCC_CSR_LSEON; + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->CSR & RCC_CSR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->CSR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->CSR |= RCC_CSR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAHB(~RCC_AHBRSTR_FLITFRST); + rccResetAPB1(~RCC_APB1RSTR_PWRRST); + rccResetAPB2(~0); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32L1xx voltage, clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32L1XX_MD) || defined(__DOXYGEN__) +/** + * @brief Clocks and internal voltage initialization. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* Core voltage setup.*/ + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + PWR->CR = STM32_VOS; + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + + /* Initial clocks setup and wait for MSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails. + Trim fields are not altered from reset values.*/ + RCC->CFGR = 0; + RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE; + RCC->CSR = RCC_CSR_RMVF; + RCC->CR = RCC_CR_MSION; + while ((RCC->CR & RCC_CR_MSIRDY) == 0) + ; /* Waits until MSI is stable. */ + +#if STM32_HSI_ENABLED + /* HSI activation.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ +#endif + +#if STM32_HSE_ENABLED +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEBYP; +#endif + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->CSR & RCC_CSR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->CSR |= RCC_CSR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CR |= STM32_RTCPRE; + RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + RCC->CSR |= STM32_RTCSEL; + + /* Flash setup and final clock selection.*/ +#if defined(STM32_FLASHBITS1) + FLASH->ACR = STM32_FLASHBITS1; +#endif +#if defined(STM32_FLASHBITS2) + FLASH->ACR = STM32_FLASHBITS2; +#endif + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_MSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h new file mode 100644 index 000000000..d4e6daa8b --- /dev/null +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -0,0 +1,1069 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/hal_lld.h + * @brief STM32L1xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density" +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 38000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ +#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ +#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ +#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ + +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_CR register bits definitions + * @{ + */ +#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ +#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */ +#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ +#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */ +#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */ + +#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */ +/** @} */ + +/** + * @name RCC_ICSCR register bits definitions + * @{ + */ +#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */ +#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */ +#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */ +#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */ +#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */ +#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */ +#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */ +#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */ +/** @} */ + +/** + * @name RCC_CSR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32L1xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 23 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 FALSE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_STAMP_IRQHandler Vector48 /**< Tamper and Time Stamp + through EXTI. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC Wakeup Timer through + EXTI. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_IRQHandler Vector88 /**< ADC1. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */ +#define DAC_IRQHandler Vector94 /**< DAC. */ +#define COMP_IRQHandler Vector98 /**< Comparator through EXTI. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM9_IRQHandler VectorA0 /**< TIM9. */ +#define TIM10_IRQHandler VectorA4 /**< TIM10. */ +#define TIM11_IRQHandler VectorA8 /**< TIM11. */ +#define LCD_IRQHandler VectorAC /**< LCD. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM6_IRQHandler VectorEC /**< TIM6. */ +#define TIM7_IRQHandler VectorF0 /**< TIM7. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_1P8 +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief ADC clock setting. + */ +#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_ADC_CLOCK_ENABLED TRUE +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_ENABLED TRUE +#endif + +/** + * @brief MSI frequency setting. + */ +#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__) +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSI +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 6 +#endif + +/** + * @brief PLL divider value. + * @note The allowed values are 2, 3, 4. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLDIV_VALUE 3 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief MCO clock source. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief MCO divider setting. + */ +#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__) +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#endif + +/** + * @brief RTC/LCD clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief HSE divider toward RTC setting. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32L1xx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined" +#endif + +/* Voltage related limits.*/ +#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__) +/** + * @brief Maximum HSE clock frequency at current voltage setting. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Maximum SYSCLK clock frequency at current voltage setting. + */ +#define STM32_SYSCLK_MAX 32000000 + +/** + * @brief Maximum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MAX 96000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MIN 6000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 32000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 32000000 + +/** + * @brief Maximum frequency not requiring a wait state for flash accesses. + */ +#define STM32_0WS_THRESHOLD 16000000 + +/** + * @brief HSI availability at current voltage settings. + */ +#define STM32_HSI_AVAILABLE TRUE + +#elif STM32_VOS == STM32_VOS_1P5 +#define STM32_HSECLK_MAX 16000000 +#define STM32_SYSCLK_MAX 16000000 +#define STM32_PLLVCO_MAX 48000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 16000000 +#define STM32_PCLK2_MAX 16000000 +#define STM32_0WS_THRESHOLD 8000000 +#define STM32_HSI_AVAILABLE TRUE +#elif STM32_VOS == STM32_VOS_1P2 +#define STM32_HSECLK_MAX 4000000 +#define STM32_SYSCLK_MAX 4000000 +#define STM32_PLLVCO_MAX 24000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 4000000 +#define STM32_PCLK2_MAX 4000000 +#define STM32_0WS_THRESHOLD 2000000 +#define STM32_HSI_AVAILABLE FALSE +#else +#error "invalid STM32_VOS value specified" +#endif + +/* HSI related checks.*/ +#if STM32_HSI_ENABLED +#if !STM32_HSI_AVAILABLE + #error "impossible to activate HSI under the current voltage settings" +#endif +#else /* !STM32_HSI_ENABLED */ +#if STM32_ADC_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_HSI) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "required HSI clock is not enabled" +#endif +#endif /* !STM32_HSI_ENABLED */ + +/* HSE related checks.*/ +#if STM32_HSE_ENABLED +#if STM32_HSECLK == 0 +#error "impossible to activate HSE" +#endif +#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" +#endif +#else /* !STM32_HSE_ENABLED */ +#if (STM32_SW == STM32_SW_HSE) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV) +#error "required HSE clock is not enabled" +#endif +#endif /* !STM32_HSE_ENABLED */ + +/* LSI related checks.*/ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ +#if STM_RTCCLK == STM32_LSICLK +#error "required LSI clock is not enabled" +#endif +#endif /* !STM32_LSI_ENABLED */ + +/* LSE related checks.*/ +#if STM32_LSE_ENABLED +#if (STM32_LSECLK == 0) +#error "impossible to activate LSE" +#endif +#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) +#error "STM32_LSECLK outside acceptable range (1...1000kHz)" +#endif +#else /* !STM32_LSE_ENABLED */ +#if STM_RTCCLK == STM32_LSECLK +#error "required LSE clock is not enabled" +#endif +#endif /* !STM32_LSE_ENABLED */ + +/* PLL related checks.*/ +#if STM32_USB_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief PLLMUL field. + */ +#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__) +#define STM32_PLLMUL (0 << 18) +#elif STM32_PLLMUL_VALUE == 4 +#define STM32_PLLMUL (1 << 18) +#elif STM32_PLLMUL_VALUE == 6 +#define STM32_PLLMUL (2 << 18) +#elif STM32_PLLMUL_VALUE == 8 +#define STM32_PLLMUL (3 << 18) +#elif STM32_PLLMUL_VALUE == 12 +#define STM32_PLLMUL (4 << 18) +#elif STM32_PLLMUL_VALUE == 16 +#define STM32_PLLMUL (5 << 18) +#elif STM32_PLLMUL_VALUE == 24 +#define STM32_PLLMUL (6 << 18) +#elif STM32_PLLMUL_VALUE == 32 +#define STM32_PLLMUL (7 << 18) +#elif STM32_PLLMUL_VALUE == 48 +#define STM32_PLLMUL (8 << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLLDIV field. + */ +#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLDIV (1 << 22) +#elif STM32_PLLDIV_VALUE == 3 +#define STM32_PLLDIV (2 << 22) +#elif STM32_PLLDIV_VALUE == 4 +#define STM32_PLLDIV (3 << 22) +#else +#error "invalid STM32_PLLDIV_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN STM32_HSECLK +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN STM32_HSICLK +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000) +#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000) +#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)" +#endif + +/** + * @brief MSI frequency. + * @note Values are taken from the STM8Lxx datasheet. + */ +#if STM32_MSIRANGE == STM32_MSIRANGE_64K +#define STM32_MSICLK 65500 +#elif STM32_MSIRANGE == STM32_MSIRANGE_128K +#define STM32_MSICLK 131000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_256K +#define STM32_MSICLK 262000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_512K +#define STM32_MSICLK 524000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_1M +#define STM32_MSICLK 1050000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_2M +#define STM32_MSICLK 2100000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_4M +#define STM32_MSICLK 4200000 +#else +#error "invalid STM32_MSIRANGE value specified" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK 2100000 +#elif (STM32_SW == STM32_SW_MSI) +#define STM32_SYSCLK STM32_MSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief MCO divider clock. + */ +#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_MCODIVCLK 0 +#elif STM32_MCOSEL == STM32_MCOSEL_HSI +#define STM_MCODIVCLK STM32_HSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_MSI +#define STM_MCODIVCLK STM32_MSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_HSE +#define STM_MCODIVCLK STM32_HSECLK +#elif STM32_MCOSEL == STM32_MCOSEL_PLL +#define STM_MCODIVCLK STM32_PLLCLKOUT +#elif STM32_MCOSEL == STM32_MCOSEL_LSI +#define STM_MCODIVCLK STM32_LSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_LSE +#define STM_MCODIVCLK STM32_LSECLK +#else +#error "invalid STM32_MCOSEL value specified" +#endif + +/** + * @brief MCO output pin clock. + */ +#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__) +#define STM_MCOCLK STM_MCODIVCLK +#elif STM32_MCOPRE == STM32_MCOPRE_DIV2 +#define STM_MCOCLK (STM_MCODIVCLK / 2) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV4 +#define STM_MCOCLK (STM_MCODIVCLK / 4) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV8 +#define STM_MCOCLK (STM_MCODIVCLK / 8) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV16 +#define STM_MCOCLK (STM_MCODIVCLK / 16) +#else +#error "invalid STM32_MCOPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 2) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 4) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 8) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC/LCD clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief ADC frequency. + */ +#define STM32_ADCCLK STM32_HSICLK + +/** + * @brief USB frequency. + */ +#define STM32_USBCLK (STM32_PLLVCO / 2) + +/** + * @brief Timers 2, 3, 4, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS1 0x00000000 +#else +#define STM32_FLASHBITS1 0x00000004 +#define STM32_FLASHBITS2 0x00000007 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 ISR, DMA and RCC helpers.*/ +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox new file mode 100644 index 000000000..879b164c9 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -0,0 +1,315 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers + * @details This section describes all the supported drivers on the STM32L1xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support + * @details The STM32L1xx HAL support is responsible for system initialization. + * + * @section stm32l1xx_hal_1 Supported HW resources + * - PLL1. + * - RCC. + * - Flash. + * . + * @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_ADC STM32L1xx ADC Support + * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_EXT STM32L1xx EXT Support + * @details The STM32L1xx EXT driver uses the EXTI peripheral. + * + * @section stm32l1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_GPT STM32L1xx GPT Support + * @details The STM32L1xx GPT driver uses the TIMx peripherals. + * + * @section stm32l1xx_gpt_1 Supported HW resources + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_ICU STM32L1xx ICU Support + * @details The STM32L1xx ICU driver uses the TIMx peripherals. + * + * @section stm32l1xx_icu_1 Supported HW resources + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PAL STM32L1xx PAL Support + * @details The STM32L1xx PAL driver uses the GPIO peripherals. + * + * @section stm32l1xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOH. + * . + * @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32l1xx_pal_3 Supported PAL setup modes + * The STM32L1xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32l1xx_pal_4 Suboptimal behavior + * The STM32L1xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PWM STM32L1xx PWM Support + * @details The STM32L1xx PWM driver uses the TIMx peripherals. + * + * @section stm32l1xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support + * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32l1xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - UART5 (where present). + * . + * @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_SPI STM32L1xx SPI Support + * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_UART STM32L1xx UART Support + * @details The UART driver supports the STM32L1xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - DMA1. + * . + * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_USB STM32L1xx USB Support + * @details The USB driver supports the STM32L1xx USB peripheral. + * + * @section stm32l1xx_usb_1 Supported HW resources + * The USB driver can support any of the following hardware resources: + * - USB. + * . + * @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority levels. + * - Each endpoint programmable in Control, Bulk and Interrupt modes. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PLATFORM_DRIVERS STM32L1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_DMA STM32L1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32l1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * . + * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32L1xx_ISR STM32L1xx ISR Support + * @details This ISR helper driver is used by the other drivers in order to + * map ISR names to physical vector names. + * + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32L1xx_RCC STM32L1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk new file mode 100644 index 000000000..dfb4b7c35 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -0,0 +1,24 @@ +# List of all the STM32L1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c new file mode 100644 index 000000000..31b475589 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_dma.c @@ -0,0 +1,344 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32L1xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn} +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h new file mode 100644 index 000000000..2e3225ce9 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -0,0 +1,396 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32l1xx.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32L1xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 7 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval FALSE invalid DMA priority. + * @retval TRUE correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32_isr.h b/os/hal/platforms/STM32L1xx/stm32_isr.h new file mode 100644 index 000000000..d90d28c0b --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_isr.h @@ -0,0 +1,92 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/stm32_isr.h + * @brief ISR remapper driver header. + * + * @addtogroup STM32L1xx_ISR + * @{ + */ + +#ifndef _STM32_ISR_H_ +#define _STM32_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * TIM units. + */ +#define STM32_TIM2_HANDLER TIM2_IRQHandler +#define STM32_TIM3_HANDLER TIM3_IRQHandler +#define STM32_TIM4_HANDLER TIM4_IRQHandler +#define STM32_TIM9_HANDLER TIM9_IRQHandler + +#define STM32_TIM2_NUMBER TIM2_IRQn +#define STM32_TIM3_NUMBER TIM3_IRQn +#define STM32_TIM4_NUMBER TIM4_IRQn +#define STM32_TIM9_NUMBER TIM9_IRQn + +/* + * USART units. + */ +#define STM32_USART1_HANDLER USART1_IRQHandler +#define STM32_USART2_HANDLER USART2_IRQHandler +#define STM32_USART3_HANDLER USART3_IRQHandler + +#define STM32_USART1_NUMBER USART1_IRQn +#define STM32_USART2_NUMBER USART2_IRQn +#define STM32_USART3_NUMBER USART3_IRQn + +/* + * USB units. + */ +#define STM32_USB1_HP_HANDLER Vector8C +#define STM32_USB1_LP_HANDLER Vector90 + +#define STM32_USB1_HP_NUMBER USB_HP_IRQn +#define STM32_USB1_LP_NUMBER USB_LP_IRQn +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_ISR_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h new file mode 100644 index 000000000..5340b9e15 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -0,0 +1,607 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32l1xx.h. + * + * @addtogroup STM32L1xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ + if (lp) \ + RCC->AHBLPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ + if (lp) \ + RCC->AHBLPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM89peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h new file mode 100644 index 000000000..62a0a658e --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -0,0 +1,6354 @@ +/** + ****************************************************************************** + * @file stm32l1xx.h + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx High-, Medium-density + * and Medium-density Plus devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) + /* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ + /* #define STM32L1XX_MDP */ /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */ + #define STM32L1XX_HD /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and + STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes. + - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx + microcontrollers where the Flash memory density is 384 Kbytes. + */ + +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif + +/** + * @brief STM32L1xx Standard Peripheral Library version number V1.1.1 + */ +#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32L1XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ +#ifdef STM32L1XX_MD + TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ +#endif + +#ifdef STM32L1XX_MDP + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif + +#ifdef STM32L1XX_HD + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + SDIO_IRQn = 45, /*!< SDIO global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/*#include "system_stm32l1xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source + module. Using the 'Options for File' dialog you can simply change the + 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + 'Options for Target' dialog. +*/ + #define __RAM_FUNC FLASH_Status + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ + #define __RAM_FUNC __ramfunc FLASH_Status + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".data")))". +*/ + #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) + +#elif defined ( __TASKING__ ) +/* TASKING Compiler + ---------------- + RAM functions are defined using a specific toolchain pragma. This pragma is + defined in the stm32l1xx_flash_ramfunc.c +*/ + #define __RAM_FUNC FLASH_Status + +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ +} AES_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ + __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ + __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ + __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ + __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ + __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ + __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ + __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ + uint32_t RESERVED[23]; /*!< Reserved, 0x24 */ + __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */ + __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ + __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ + __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ + __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ + __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ + __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ + __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ + __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ +} OB_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief General Purpose IO + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + uint16_t RESERVED1; /*!< Reserved, 0x12 */ + __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + uint16_t RESERVED2; /*!< Reserved, 0x16 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ + __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint16_t RESERVED3; /*!< Reserved, 0x2A */ +} GPIO_TypeDef; +#endif + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ + __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED10; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + uint32_t RESERVED12; /*!< Reserved, 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + uint32_t RESERVED17; /*!< Reserved, 0x44 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED18; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED19; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED20; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) +#define RI_BASE (APB1PERIPH_BASE + 0x7C04) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC_BASE (APB2PERIPH_BASE + 0x2700) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define RCC_BASE (AHBPERIPH_BASE + 0x3800) + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) + +#define DMA2_BASE (AHBPERIPH_BASE + 0x6400) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) + +#define AES_BASE ((uint32_t)0x50060000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define RI ((RI_TypeDef *) RI_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) + +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +#define AES ((AES_TypeDef *) AES_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ +#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ +#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ +#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + +/****************** Bit definition for ADC_SMPR0 register *******************/ +#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ +#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ +#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */ +#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */ +#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */ +#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */ + +#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */ +#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */ +#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */ +#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */ +#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */ +#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_IVR0 register *******************/ +#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register *******************/ +#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register *******************/ +#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register *******************/ +#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ + +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ + +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ + +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for OPAMP_CSR register ******************/ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */ +#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */ +#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */ +#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */ +#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */ +#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */ + +/******************* Bit definition for OPAMP_OTR register ******************/ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ + +/******************* Bit definition for OPAMP_LPOTR register ****************/ +#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */ +#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */ +#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!ICKCR |= CLK_ICKCR_HSION; + while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0) + ; + + /* LSI startup and stabilization if required.*/ +#if STM8L_LSI_ENABLED + CLK->ICKCR |= CLK_ICKCR_LSION; + while ((CLK->ICKCR & CLK_ICKCR_LSIRDY) == 0) + ; +#endif + + /* HSE startup and stabilization if required.*/ +#if STM8L_HSE_ENABLED +#if HSEBYPASS + CLK->ECKCR |= CLK_ECKCR_HSEON | CLK_ECKCR_HSEBYP; +#else + CLK->ECKCR |= CLK_ECKCR_HSEON; +#endif + while ((CLK->ECKCR & CLK_ECKCR_HSERDY) == 0) + ; +#endif + + /* LSE startup and stabilization if required.*/ +#if STM8L_LSE_ENABLED +#if LSEBYPASS + CLK->ECKCR |= CLK_ECKCR_LSEON | CLK_ECKCR_LSEBYP; +#else + CLK->ECKCR |= CLK_ECKCR_LSEON; +#endif + while ((CLK->ECKCR & CLK_ECKCR_LSERDY) == 0) + ; +#endif + + /* Setting up clock dividers.*/ + CLK->CKDIVR = STM8L_SYSCLK_DIVIDER << 0; + + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8L_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + + /* Clocks initially all disabled, note the boot ROM clock is disabled + because the boot loader is no more required and it draws precious uAs.*/ + CLK->PCKENR1 = 0; + CLK->PCKENR2 = 0; + CLK->PCKENR3 = 0; + + /* Other clock related initializations.*/ + CLK->CSSR = 0; + CLK->CCOR = 0; + + /* HSI disabled if it is no more required.*/ +#if !STM8L_HSI_ENABLED + CLK->ICKCR &= ~CLK_ICKCR_HSION; +#endif +#endif /* !STM8L_NO_CLOCK_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h new file mode 100644 index 000000000..0f8ca6776 --- /dev/null +++ b/os/hal/platforms/STM8L/hal_lld.h @@ -0,0 +1,282 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/hal_lld.h + * @brief STM8L HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * - HSEBYPASS (@p TRUE if external oscillator rather than a crystal). + * - LSECLK (@p 0 if disabled or frequency in Hertz). + * - LSEBYPASS (@p TRUE if external oscillator rather than a crystal). + * . + * One of the following macros must also be defined: + * - STM8L15X_MD for Medium Density devices. + * - STM8L15X_MDP for Medium Density Plus devices. + * - STM8L15X_HD for High Density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#undef FALSE +#undef TRUE +#include "stm8l15x.h" +#define FALSE 0 +#define TRUE (!FALSE) + +#if defined (STM8L15X_MD) +#include "hal_lld_stm8l_md.h" +#elif defined (STM8L15X_MDP) +#include "hal_lld_stm8l_mdp.h" +#elif defined (STM8L15X_HD) +#include "hal_lld_stm8l_hd.h" +#else +#error "unspecified, unsupported or invalid STM8L platform" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM8L" + +#define LSICLK 38000 /**< Low speed internal clock. */ +#define HSICLK 16000000 /**< High speed internal clock. */ + +#define CLK_SYSSEL_HSI 1 /**< HSI system clock selector. */ +#define CLK_SYSSEL_LSI 2 /**< LSI system clock selector. */ +#define CLK_SYSSEL_HSE 4 /**< HSE system clock selector. */ +#define CLK_SYSSEL_LSE 8 /**< LSE system clock selector. */ + +#define CLK_SYSCLK_DIV1 0 /**< Source clock divided by 1. */ +#define CLK_SYSCLK_DIV2 1 /**< Source clock divided by 2. */ +#define CLK_SYSCLK_DIV4 2 /**< Source clock divided by 4. */ +#define CLK_SYSCLK_DIV8 3 /**< Source clock divided by 8. */ +#define CLK_SYSCLK_DIV16 4 /**< Source clock divided by 16. */ +#define CLK_SYSCLK_DIV32 5 /**< Source clock divided by 32. */ +#define CLK_SYSCLK_DIV64 6 /**< Source clock divided by 64. */ +#define CLK_SYSCLK_DIV128 7 /**< Source clock divided by 128. */ + +#define CLK_RTCSEL_HSI 1 /**< HSI RTC clock selector. */ +#define CLK_RTCSEL_LSI 2 /**< LSI RTC clock selector. */ +#define CLK_RTCSEL_HSE 4 /**< HSE RTC clock selector. */ +#define CLK_RTCSEL_LSE 8 /**< LSE RTC clock selector. */ + +#define CLK_RTCCLK_DIV1 0 /**< Source clock divided by 1. */ +#define CLK_RTCCLK_DIV2 1 /**< Source clock divided by 2. */ +#define CLK_RTCCLK_DIV4 2 /**< Source clock divided by 4. */ +#define CLK_RTCCLK_DIV8 3 /**< Source clock divided by 8. */ +#define CLK_RTCCLK_DIV16 4 /**< Source clock divided by 16. */ +#define CLK_RTCCLK_DIV32 5 /**< Source clock divided by 32. */ +#define CLK_RTCCLK_DIV64 6 /**< Source clock divided by 64. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8L_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8L_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8L_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8L_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8L_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8L_HSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8L_LSE_ENABLED FALSE +#endif + +/** + * @brief System clock source selection. + */ +#if !defined(STM8L_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI +#endif + +/** + * @brief System clock divider. + */ +#if !defined(STM8L_SYSCLK_DIVIDER) || defined(__DOXYGEN__) +#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 +#endif + +/** + * @brief RTC clock source selection. + */ +#if !defined(STM8L_RTCCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_HSI +#endif + +/** + * @brief RTC clock divider. + */ +#if !defined(STM8L_RTCCLK_DIVIDER) || defined(__DOXYGEN__) +#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV1) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV2) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV4) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV8) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV16) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV32) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV64) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV128) +#error "specified invalid SYSCLK divider" +#endif + +#if (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV1) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV2) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV4) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV8) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV16) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV32) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV64) +#error "specified invalid RTCCLK divider" +#endif + +#if STM8L_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if STM8L_LSE_ENABLED && (LSECLK == 0) +#error "impossible to activate LSE" +#endif + +#if !STM8L_HSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI)) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8L_LSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI)) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8L_HSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE)) +#error "requested HSE clock is not enabled" +#endif + +#if !STM8L_LSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE)) +#error "requested LSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define SYSCLK (HSICLK / 8) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI +#define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI +#define SYSCLK (LSICLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE +#define SYSCLK (HSECLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE +#define SYSCLK (LSECLK / (1 << STM8L_SYSCLK_DIVIDER)) +#else +#error "specified invalid SYSCLK source" +#endif + +/** + * @brief RTC clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define RTCCLK 0 +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI +#define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI +#define RTCCLK (LSICLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE +#define RTCCLK (HSECLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE +#define RTCCLK (LSECLK / (1 << STM8L_RTCCLK_DIVIDER)) +#else +#error "specified invalid RTCCLK source" +#endif + +/** + * @brief CPU clock. + * @details On the STM8L the CPU clock is always equal to the system clock. + */ +#define CPUCLK SYSCLK + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h b/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h new file mode 100644 index 000000000..68a3211d8 --- /dev/null +++ b/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM8L_HD_HAL STM8L High Density sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_hd.h + * @brief STM8L High Density sub-family capabilities descriptor. + * + * @addtogroup STM8L_HD_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_HD_H_ +#define _HAL_LLD_STM8L_HD_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG TRUE +#define STM8L_HAS_GPIOH TRUE +#define STM8L_HAS_GPIOI TRUE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 TRUE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 TRUE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 TRUE +#define STM8L_HAS_USART3 TRUE + +#endif /* _HAL_LLD_STM8L_HD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_md.h b/os/hal/platforms/STM8L/hal_lld_stm8l_md.h new file mode 100644 index 000000000..072a77dca --- /dev/null +++ b/os/hal/platforms/STM8L/hal_lld_stm8l_md.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM8L_MD_HAL STM8L Medium Density sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_md.h + * @brief STM8L Medium Density sub-family capabilities descriptor. + * + * @addtogroup STM8L_MD_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_MD_H_ +#define _HAL_LLD_STM8L_MD_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG FALSE +#define STM8L_HAS_GPIOH FALSE +#define STM8L_HAS_GPIOI FALSE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 FALSE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 FALSE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 FALSE +#define STM8L_HAS_USART3 FALSE + +#endif /* _HAL_LLD_STM8L_MD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h b/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h new file mode 100644 index 000000000..83e0672c9 --- /dev/null +++ b/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM8L_MDP_HAL STM8L Medium Density Plus sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_mdp.h + * @brief STM8L Medium Density Plus sub-family capabilities descriptor. + * + * @addtogroup STM8L_MDP_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_MDP_H_ +#define _HAL_LLD_STM8L_MDP_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG TRUE +#define STM8L_HAS_GPIOH TRUE +#define STM8L_HAS_GPIOI TRUE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 TRUE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 TRUE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 TRUE +#define STM8L_HAS_USART3 TRUE + +#endif /* _HAL_LLD_STM8L_MDP_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/pal_lld.c b/os/hal/platforms/STM8L/pal_lld.c new file mode 100644 index 000000000..1b83d8a8d --- /dev/null +++ b/os/hal/platforms/STM8L/pal_lld.c @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/pal_lld.c + * @brief STM8L GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->DDR &= ~mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_OUTPUT_PUSHPULL_SLOW: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 |= mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/pal_lld.h b/os/hal/platforms/STM8L/pal_lld.h new file mode 100644 index 000000000..b7dffed26 --- /dev/null +++ b/os/hal/platforms/STM8L/pal_lld.h @@ -0,0 +1,244 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/pal_lld.h + * @brief STM8L GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/** + * @brief STM8L specific alternate push-pull slow output mode. + */ +#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 + +/** + * @brief STM8L specific alternate open-drain slow output mode. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) + GPIO_TypeDef P[9]; +#elif STM8L_HAS_GPIOH || defined(__DOXYGEN__) + GPIO_TypeDef P[8]; +#elif STM8L_HAS_GPIOG || defined(__DOXYGEN__) + GPIO_TypeDef P[7]; +#else + GPIO_TypeDef P[6]; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports as a whole. + */ +#define IOPORTS ((PALConfig *)0x5000) + +#if STM8L_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA +#endif + +#if STM8L_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB +#endif + +#if STM8L_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC +#endif + +#if STM8L_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD +#endif + +#if STM8L_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE +#endif + +#if STM8L_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF +#endif + +#if STM8L_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 GPIOG +#endif + +#if STM8L_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 GPIOH +#endif + +#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) +/** + * @brief GPIO port I identifier. + */ +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) (*IOPORTS = *(config)) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/platform.dox b/os/hal/platforms/STM8L/platform.dox new file mode 100644 index 000000000..9c28a931b --- /dev/null +++ b/os/hal/platforms/STM8L/platform.dox @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM8L_DRIVERS STM8L Drivers + * @details This section describes all the supported drivers on the STM8L + * and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM8L_HAL STM8L Initialization Support + * @details The STM8L HAL support is responsible for system initialization. + * + * @section stm8l_hal_1 Supported HW resources + * - CLK. + * . + * @section stm8l_hal_2 STM8L HAL driver implementation features + * - Board related initializations. + * - Clock tree initialization. + * - Clock source selection. + * . + * @ingroup STM8L_DRIVERS + */ + +/** + * @defgroup STM8L_PAL STM8L PAL Support + * @details The STM8L PAL driver uses the GPIO peripherals. + * + * @section stm8l_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH (where present). + * - GPIOI (where present). + * . + * @section stm8l_pal_2 STM8L PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special STM8L instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm8l_pal_3 Supported PAL setup modes + * The STM8L PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm8l_pal_4 Suboptimal behavior + * The STM8L GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM8L_DRIVERS + */ + +/** + * @defgroup STM8L_SERIAL STM8L Serial Support + * @details The STM8L Serial driver uses the USART1 peripheral in a + * buffered, interrupt driven, implementation. + * + * @section stm8l_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2 (where present). + * - USART3 (where present). + * . + * @section stm8l_serial_2 STM8L Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * . + * @ingroup STM8L_DRIVERS + */ diff --git a/os/hal/platforms/STM8L/serial_lld.c b/os/hal/platforms/STM8L/serial_lld.c new file mode 100644 index 000000000..2ef60bce8 --- /dev/null +++ b/os/hal/platforms/STM8L/serial_lld.c @@ -0,0 +1,209 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/serial_lld.c + * @brief STM8L low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USART1 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief USART2 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief USART3 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static ROMCONST SerialConfig default_config = { + BRR(SERIAL_DEFAULT_BITRATE), + SD_MODE_PARITY_NONE | SD_MODE_STOP_1 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + USART1->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + USART2->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + USART3->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART3 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/* See in serial_lld.h.*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr USART SR register value + * + * @notapi + */ +void sd_lld_set_error(SerialDriver *sdp, uint8_t sr) { + flagsmask_t sts = 0; + + if (sr & USART_SR_OR) + sts |= SD_OVERRUN_ERROR; + if (sr & USART_SR_NF) + sts |= SD_NOISE_ERROR; + if (sr & USART_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & USART_SR_PE) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM8L_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + CLK->PCKENR1 |= CLK_PCKENR1_USART1; /* PCKEN12, clock source. */ + USART1->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD1.usart = USART1; +#endif + +#if STM8L_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + CLK->PCKENR3 |= CLK_PCKENR3_USART2; /* PCKEN13, clock source. */ + USART2->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD2.usart = USART2; +#endif + +#if STM8L_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + CLK->PCKENR3 |= CLK_PCKENR3_USART3; /* PCKEN13, clock source. */ + USART3->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD3.usart = USART3; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + USART_TypeDef *u = sdp->usart; + + if (config == NULL) + config = &default_config; + + u->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + u->BRR1 = (uint8_t)(config->sc_brr >> 4); + u->CR1 = (uint8_t)(config->sc_mode & SD_MODE_PARITY); + u->CR2 = USART_CR2_RIEN | USART_CR2_TEN | USART_CR2_REN; + u->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + u->CR4 = 0; + u->CR5 = 0; + u->PSCR = 1; + (void)u->SR; + (void)u->DR; +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + + u->CR1 = USART_CR1_USARTD; + u->CR2 = 0; + u->CR3 = 0; + u->CR4 = 0; + u->CR5 = 0; + u->PSCR = 0; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/serial_lld.h b/os/hal/platforms/STM8L/serial_lld.h new file mode 100644 index 000000000..1164cc8fc --- /dev/null +++ b/os/hal/platforms/STM8L/serial_lld.h @@ -0,0 +1,270 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/serial_lld.h + * @brief STM8L low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ + +#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ +#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ +#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ +#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART1 TRUE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART2 TRUE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART3 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 && !STM8L_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM8L_SERIAL_USE_USART2 && !STM8L_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM8L_SERIAL_USE_USART3 && !STM8L_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate register. + */ + uint16_t sc_brr; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + USART_TypeDef *usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define BRR(b) (SYSCLK / (b)) + +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 RX interrupt handler segment. + */ +#define _USART1_RECEIVE_ISR() { \ + uint8_t sr = USART1->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD1, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD1, USART1->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART1 TX interrupt handler segment. + */ +#define _USART1_TRANSMIT_ISR() { \ + if (USART1->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD1); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART1->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART1->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 RX interrupt handler segment. + */ +#define _USART2_RECEIVE_ISR() { \ + uint8_t sr = USART2->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD2, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD2, USART2->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART2 TX interrupt handler segment. + */ +#define _USART2_TRANSMIT_ISR() { \ + if (USART2->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD2); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART2->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART2->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART2 */ + +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 RX interrupt handler segment. + */ +#define _USART3_RECEIVE_ISR() { \ + uint8_t sr = USART3->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD3, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD3, USART3->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART3 TX interrupt handler segment. + */ +#define _USART3_TRANSMIT_ISR() { \ + if (USART3->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD3); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART3->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART3->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART3 */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM8L_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM8L_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + void sd_lld_set_error(SerialDriver *sdp, uint8_t sr); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/shared_isr.c b/os/hal/platforms/STM8L/shared_isr.c new file mode 100644 index 000000000..ed94a112b --- /dev/null +++ b/os/hal/platforms/STM8L/shared_isr.c @@ -0,0 +1,188 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8L/shared_isr.c + * @brief STM8L shared interrupt code source. + * @details The STM8L shares some interrupt handlers among several sources. + * This module includes all the interrupt handlers that are + * used by more than one peripheral. + * @note Only the interrupt handlers that are used by the HAL are defined + * in this module. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* This inclusion allows user ISR to be added to the HAL.*/ +#if defined(_USER_ISR_) +#include "user_isr.h" +#endif + +#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 19 service routine. + * @details This handler is shared between the following sources: + * - TIM2 update/overflow/trigger/break. + * - USART2 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(19) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM2_UPDATE_ISR) + _TIM2_UPDATE_ISR(); +#endif +#if defined(_USART2_TRANSMIT_ISR) + _USART2_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) */ + +#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * @details This handler is shared between the following sources: + * - TIM2 compare/capture + * - USART2 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(20) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM2_COMPARE_ISR) + _TIM2_COMPARE_ISR(); +#endif +#if defined(_USART2_RECEIVE_ISR) + _USART2_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) */ + +#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 21 service routine. + * @details This handler is shared between the following sources: + * - TIM3 update/overflow/trigger/break. + * - USART3 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(21) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM3_UPDATE_ISR) + _TIM3_UPDATE_ISR(); +#endif +#if defined(_USART3_TRANSMIT_ISR) + _USART3_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) */ + +#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 22 service routine. + * @details This handler is shared between the following sources: + * - TIM3 compare/capture + * - USART3 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(22) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM3_COMPARE_ISR) + _TIM3_COMPARE_ISR(); +#endif +#if defined(_USART3_RECEIVE_ISR) + _USART3_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) */ + +#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 27 service routine. + * @details This handler is shared between the following sources: + * - TIM5 update/overflow/trigger/break. + * - USART1 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(27) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM5_UPDATE_ISR) + _TIM5_UPDATE_ISR(); +#endif +#if defined(_USART1_TRANSMIT_ISR) + _USART1_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) */ + +#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 28 service routine. + * @details This handler is shared between the following sources: + * - TIM5 compare/capture + * - USART1 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(28) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM5_COMPARE_ISR) + _TIM5_COMPARE_ISR(); +#endif +#if defined(_USART1_RECEIVE_ISR) + _USART1_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) */ + +/** @} */ diff --git a/os/hal/platforms/STM8L/stm8l15x.h b/os/hal/platforms/STM8L/stm8l15x.h new file mode 100644 index 000000000..6971a9da5 --- /dev/null +++ b/os/hal/platforms/STM8L/stm8l15x.h @@ -0,0 +1,3000 @@ +/** + ****************************************************************************** + * @file stm8l15x.h + * @author MCD Application Team + * @version V1.5.0 + * @date 13-May-2011 + * @brief This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM8L15x devices. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8L15x_H + #define __STM8L15x_H + +/** @addtogroup STM8L15x_StdPeriph_Driver + * @{ + */ +/* Uncomment the line below according to the target STM8L15x device used in your + application + */ +/* #define STM8L15X_LD */ /*!< STM8L15X_LD: STM8L15x Low density devices */ +/* #define STM8L15X_MD */ /*!< STM8L15X_MD: STM8L15x Medium density devices */ +/* #define STM8L15X_MDP */ /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */ +/* #define STM8L15X_HD */ /*!< STM8L15X_HD: STM8L15x/16x High density devices */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3, + STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the + Flash memory density ranges between 4 and 8 Kbytes. + - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4, + STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4, + STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory + density ranges between 16 and 32 Kbytes. + - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where + the Flash memory density is fixed and equal to 32 Kbytes and a wider range of + peripheral than the medium density devices. + - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8 + microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with + the same peripheral set than Medium Density Plus devices. + + */ + +#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD) + #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)" +#endif + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #define _COSMIC_ +#elif defined(__RCST7__) + #define _RAISONANCE_ +#elif defined(__ICCSTM8__) + #define _IAR_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ +/* CHIBIOS FIX */ +/* #define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_Value + #define HSE_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */ +#endif /* HSE_Value */ + +/** + * @brief Definition of External Low Speed oscillator (LSE) frequency + */ +#define LSE_VALUE ((uint32_t)32768) /*!< Typical Value of the LSE in Hz */ + +/** + * @brief Definition of Device on-chip RC oscillator frequencies + */ +#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ +#define LSI_VALUE ((uint32_t)38000) /*!< Typical Value of the LSI in Hz */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define EEPROM @eeprom + #define CONST const +#elif defined (_RAISONANCE_) /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define EEPROM eeprom + #define CONST code + #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) + /*!< Used with memory Models for code less than 64K */ + #define MEMCPY memcpy + #else /* STM8L15X_HD */ + /*!< Used with memory Models for code higher than 64K */ + #define MEMCPY fmemcpy + #endif /* STM8L15X_MD or STM8L15X_MDP */ +#else /*_IAR_*/ + #define FAR __far + #define NEAR __near + #define TINY __tiny + #define EEPROM __eeprom + #define CONST const +#endif /* __CSMC__ */ + +/** + * @brief Legacy definition + */ +#define __CONST CONST + +#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) +/*!< Used with memory Models for code smaller than 64K */ + #define PointerAttr NEAR +#else /* STM8L15X_HD */ +/*!< Used with memory Models for code higher than 64K */ + #define PointerAttr FAR +#endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD*/ + +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#if !defined (RAM_EXECUTION) +/* #define RAM_EXECUTION (1) */ +#endif /* RAM_EXECUTION */ + +#ifdef RAM_EXECUTION + #ifdef _COSMIC_ + #define IN_RAM(a) a + #elif defined (_RAISONANCE_) /* __RCST7__ */ + #define IN_RAM(a) a inram + #else /*_IAR_*/ + #define IN_RAM(a) __ramfunc a + #endif /* _COSMIC_ */ +#else + #define IN_RAM(a) a +#endif /* RAM_EXECUTION */ + +/*!< [31:16] STM8L15X Standard Peripheral Library main version */ +#define __STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01) /*!< [31:24] main version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x05) /*!< [23:16] sub1 version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ +#define __STM8L15X_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ +#define __STM8L15X_STDPERIPH_VERSION ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM8L15X_STDPERIPH_VERSION_RC)) + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types and constants ----------------------------------------------*/ + +/** @addtogroup Exported_types + * @{ + */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/* CHIBIOS FIX */ +#if 0 +/*!< Signed integer types */ +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +#endif + +/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */ + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX (255) +#define S8_MAX (127) +#define S8_MIN (-128) +#define U16_MAX (65535u) +#define S16_MAX (32767) +#define S16_MIN (-32768) +#define U32_MAX (4294967295uL) +#define S32_MAX (2147483647) +#define S32_MIN (-2147483648uL) + +/** + * @} + */ + +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ +typedef struct GPIO_struct +{ + __IO uint8_t ODR; /*!< Output Data Register */ + __IO uint8_t IDR; /*!< Input Data Register */ + __IO uint8_t DDR; /*!< Data Direction Register */ + __IO uint8_t CR1; /*!< Configuration Register 1 */ + __IO uint8_t CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ +#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) +/** + * @} + */ +/*----------------------------------------------------------------------------*/ + +/** + * @brief Real-Time Clock (RTC) peripheral registers. + */ +typedef struct RTC_struct +{ + __IO uint8_t TR1; /*!< Time Register 1*/ + __IO uint8_t TR2; /*!< Time Register 2*/ + __IO uint8_t TR3; /*!< Time Register 3*/ + + uint8_t RESERVED0; + + __IO uint8_t DR1; /*!< Date Register 1*/ + __IO uint8_t DR2; /*!< Date Register 2*/ + __IO uint8_t DR3; /*!< Date Register 3*/ + + uint8_t RESERVED1; + + __IO uint8_t CR1; /*!< Control Register 1*/ + __IO uint8_t CR2; /*!< Control Register 2*/ + __IO uint8_t CR3; /*!< Control Register 3*/ + + uint8_t RESERVED2; + + __IO uint8_t ISR1; /*!< Initialisation and Status Register 1 */ + __IO uint8_t ISR2; /*!< Initialisation and Status Register 2 */ + + uint8_t RESERVED3; + uint8_t RESERVED4; + + __IO uint8_t SPRERH; /*!< Synchronous Prediv high Register */ + __IO uint8_t SPRERL; /*!< Synchronous Prediv Low Register */ + __IO uint8_t APRER; /*!< Asynchronous Prediv Register */ + + uint8_t RESERVED5; + + __IO uint8_t WUTRH; /*!< Wake-Up Timer High Register */ + __IO uint8_t WUTRL; /*!< Wake-Up Timer Low Register */ + + uint8_t RESERVED6; + + __IO uint8_t SSRH; /*!< Sub Second High Register */ + __IO uint8_t SSRL; /*!< Sub Second Low Register */ + + __IO uint8_t WPR; /*!< Write Protection Register */ + + __IO uint8_t SHIFTRH; /*!< Shift control High Register */ + __IO uint8_t SHIFTRL; /*!< Shift control Low Register */ + + __IO uint8_t ALRMAR1; /*!< ALARM A Register 1 */ + __IO uint8_t ALRMAR2; /*!< ALARM A Register 2 */ + __IO uint8_t ALRMAR3; /*!< ALARM A Register 3 */ + __IO uint8_t ALRMAR4; /*!< ALARM A Register 4 */ + + uint8_t RESERVED7[4]; + + __IO uint8_t ALRMASSRH; /*!< ALARM A Subsecond Register High */ + __IO uint8_t ALRMASSRL; /*!< ALARM A Subsecond Register Low */ + __IO uint8_t ALRMASSMSKR; /*!< ALARM A Subsecond Mask Register */ + + uint8_t RESERVED8[3]; + + __IO uint8_t CALRH; /*!< Calibration register high */ + __IO uint8_t CALRL; /*!< Calibration register low */ + + __IO uint8_t TCR1; /*!< Tamper control register 1 */ + __IO uint8_t TCR2; /*!< Tamper control register 2 */ +} +RTC_TypeDef; + +/** @addtogroup RTC_Registers_Reset_Value + * @{ + */ +#define RTC_TR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_DR1_RESET_VALUE ((uint8_t)0x01) +#define RTC_DR2_RESET_VALUE ((uint8_t)0x21) +#define RTC_DR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ISR1_RESET_VALUE ((uint8_t)0x07) +#define RTC_ISR2_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SPRERH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF) +#define RTC_APRER_RESET_VALUE ((uint8_t)0x7F) + +#define RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF) +#define RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF) + +#define RTC_WPR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CALRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_CALRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_TCR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TCR2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup RTC_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for RTC_TR1 register*/ +#define RTC_TR1_ST ((uint8_t)0x70) +#define RTC_TR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR2 register*/ +#define RTC_TR2_MNT ((uint8_t)0x70) +#define RTC_TR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR3 register*/ +#define RTC_TR3_PM ((uint8_t)0x40) +#define RTC_TR3_HT ((uint8_t)0x30) +#define RTC_TR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR1 register*/ +#define RTC_DR1_DT ((uint8_t)0x30) +#define RTC_DR1_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR2 register*/ +#define RTC_DR2_WDU ((uint8_t)0xE0) +#define RTC_DR2_MT ((uint8_t)0x10) +#define RTC_DR2_MU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR3 register*/ +#define RTC_DR3_YT ((uint8_t)0xF0) +#define RTC_DR3_YU ((uint8_t)0x0F) + +/* Bits definition for RTC_CR1 register*/ +#define RTC_CR1_FMT ((uint8_t)0x40) +#define RTC_CR1_RATIO ((uint8_t)0x20) +#define RTC_CR1_WUCKSEL ((uint8_t)0x07) +#define RTC_CR1_BYPSHAD ((uint8_t)0x10) + + +/* Bits definition for RTC_CR2 register*/ +#define RTC_CR2_WUTIE ((uint8_t)0x40) +#define RTC_CR2_ALRAIE ((uint8_t)0x10) +#define RTC_CR2_WUTE ((uint8_t)0x04) +#define RTC_CR2_ALRAE ((uint8_t)0x01) +#define RTC_CR2_ALRIE ((uint8_t)0x20) + + + +/* Bits definition for RTC_CR3 register*/ +#define RTC_CR3_COE ((uint8_t)0x80) +#define RTC_CR3_OSEL ((uint8_t)0x60) +#define RTC_CR3_POL ((uint8_t)0x10) +#define RTC_CR3_COSEL ((uint8_t)0x08) +#define RTC_CR3_BCK ((uint8_t)0x04) +#define RTC_CR3_SUB1H ((uint8_t)0x02) +#define RTC_CR3_ADD1H ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR1 register*/ +#define RTC_ISR1_INIT ((uint8_t)0x80) +#define RTC_ISR1_INITF ((uint8_t)0x40) +#define RTC_ISR1_RSF ((uint8_t)0x20) +#define RTC_ISR1_INITS ((uint8_t)0x10) +#define RTC_ISR1_SHPF ((uint8_t)0x08) +#define RTC_ISR1_WUTWF ((uint8_t)0x04) +#define RTC_ISR1_RECALPF ((uint8_t)0x02) +#define RTC_ISR1_ALRAWF ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR2 register*/ +#define RTC_ISR2_WUTF ((uint8_t)0x04) +#define RTC_ISR2_ALRAF ((uint8_t)0x01) +#define RTC_ISR2_TAMP3F ((uint8_t)0x80) +#define RTC_ISR2_TAMP2F ((uint8_t)0x40) +#define RTC_ISR2_TAMP1F ((uint8_t)0x20) + +/* Bits definition for RTC_SHIFTRH register*/ +#define RTC_SHIFTRH_ADD1S ((uint8_t)0x80) +#define RTC_SHIFTRH_SUBFS ((uint8_t)0x7F) + +/* Bits definition for RTC_SHIFTRL register*/ +#define RTC_SHIFTRL_SUBFS ((uint8_t)0xFF) + + +/* Bits definition for RTC_ALRMAR1 register*/ +#define RTC_ALRMAR1_MSK1 ((uint8_t)0x80) +#define RTC_ALRMAR1_ST ((uint8_t)0x70) +#define RTC_ALRMAR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR2 register*/ +#define RTC_ALRMAR2_MSK2 ((uint8_t)0x80) +#define RTC_ALRMAR2_MNT ((uint8_t)0x70) +#define RTC_ALRMAR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR3 register*/ +#define RTC_ALRMAR3_MSK3 ((uint8_t)0x80) +#define RTC_ALRMAR3_PM ((uint8_t)0x40) +#define RTC_ALRMAR3_HT ((uint8_t)0x30) +#define RTC_ALRMAR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR4 register*/ +#define RTC_ALRMAR4_MSK4 ((uint8_t)0x80) +#define RTC_ALRMAR4_WDSEL ((uint8_t)0x40) +#define RTC_ALRMAR4_DT ((uint8_t)0x30) +#define RTC_ALRMAR4_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMASSRH register*/ +#define RTC_ALRMASSRH_ALSS ((uint8_t)0x7F) + +/* Bits definition for RTC_ALRMASSRL register*/ +#define RTC_ALRMASSRL_ALSS ((uint8_t)0xFF) + +/* Bits definition for RTC_ALRMASSMSKR register*/ +#define RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F) + + +/* Bits definition for RTC_CALRH register*/ +#define RTC_CALRH_CALP ((uint8_t)0x80) +#define RTC_CALRH_CALW8 ((uint8_t)0x40) +#define RTC_CALRH_CALW16 ((uint8_t)0x20) +#define RTC_CALRH_CALWx ((uint8_t)0x60) +#define RTC_CALRH_CALM ((uint8_t)0x01) + +/* Bits definition for RTC_CALRL register*/ +#define RTC_CALRL_CALM ((uint8_t)0xFF) + +/* Bits definition for RTC_TCR1 register*/ +#define RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40) +#define RTC_TCR1_TAMP3E ((uint8_t)0x20) +#define RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10) +#define RTC_TCR1_TAMP2E ((uint8_t)0x08) +#define RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04) +#define RTC_TCR1_TAMP1E ((uint8_t)0x02) +#define RTC_TCR1_TAMPIE ((uint8_t)0x01) + +/* Bits definition for RTC_TCR2 register*/ +#define RTC_TCR2_TAMPPUDIS ((uint8_t)0x80) +#define RTC_TCR2_TAMPPRCH ((uint8_t)0x60) +#define RTC_TCR2_TAMPFLT ((uint8_t)0x18) +#define RTC_TCR2_TAMPFREQ ((uint8_t)0x07) + + +/*RTC special defines */ +#define RTC_WPR_EnableKey ((uint8_t)0xFF) +#define RTC_WPR_DisableKey1 ((uint8_t)0xCA) +#define RTC_WPR_DisableKey2 ((uint8_t)0x53) + +/** + * @} + */ + +/** + * @brief CSS on LSE registers. + */ +typedef struct CSSLSE_struct +{ + __IO uint8_t CSR; /*!< Control and Status Register*/ +} +CSSLSE_TypeDef; + +/** @addtogroup CSSLSE_Registers_Reset_Value + * @{ + */ +#define CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CSSLSE_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for CSSLSE_CSR register*/ +#define CSSLSE_CSR_SWITCHF ((uint8_t)0x10) +#define CSSLSE_CSR_CSSF ((uint8_t)0x08) +#define CSSLSE_CSR_CSSIE ((uint8_t)0x04) +#define CSSLSE_CSR_SWITCHEN ((uint8_t)0x02) +#define CSSLSE_CSR_CSSEN ((uint8_t)0x01) + +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + __IO uint8_t CSR1; /*!< BEEP Control status register1 */ + uint8_t RSERVED1; + uint8_t RESERVED2; + __IO uint8_t CSR2; /*!< BEEP Control status register2 */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ +#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR1_MSR ((uint8_t)0x01) /*!< Measurement enable mask */ + +#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR2_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Configuration Registers (CFG) + */ + +typedef struct CFG_struct +{ + __IO uint8_t GCR; /*!< Global Configuration register */ +} +CFG_TypeDef; + +/** @addtogroup CFG_Registers_Reset_Value + * @{ + */ + +#define CFG_GCR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CFG_Registers_Bits_Definition + * @{ + */ + +#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ +#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief SYSCFG + */ + +typedef struct SYSCFG_struct +{ + __IO uint8_t RMPCR3; /*!< Remap control register 3 */ + __IO uint8_t RMPCR1; /*!< Remap control register 1 */ + __IO uint8_t RMPCR2; /*!< Remap control register 2 */ +} +SYSCFG_TypeDef; + +/** @addtogroup SYSCFG_Registers_Reset_Value + * @{ + */ +#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C) +#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00) +#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup SYSCFG_Registers_Bits_Definition + * @{ + */ + +/* For DMA Channel Mapping*/ +#define SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */ +#define SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */ + + +/* For GPIO Reapping*/ +#define SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */ +#define SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40) /*!< USART1_CK remapping */ +#define SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80) /*!< SPI1 remapping */ + +#define SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01) /*!< ADC1 External Trigger remap */ +#define SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02) /*!< TIM2 Trigger remap */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */ +#define SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20) /*!< SPI2 remapping */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */ +#define SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */ + +#define SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01) /*!< SPI1 remapping */ +#define SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */ +#define SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04) /*!< USART3_CK remapping */ +#define SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */ +#define SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */ +#define SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20) /*!< CCO remapping */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Clock Controller (CLK) + */ +typedef struct CLK_struct +{ + __IO uint8_t CKDIVR; /*!< Clock Master Divider Register */ + __IO uint8_t CRTCR; /*!< RTC Clock selection Register */ + __IO uint8_t ICKCR; /*!< Internal Clocks Control Register */ + __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ + __IO uint8_t ECKCR; /*!< External Clocks Control Register */ + __IO uint8_t SCSR; /*!< System clock status Register */ + __IO uint8_t SWR; /*!< System clock Switch Register */ + __IO uint8_t SWCR; /*!< Switch Control Register */ + __IO uint8_t CSSR; /*!< Clock Security Sytem Register */ + __IO uint8_t CBEEPR; /*!< Clock BEEP Register */ + __IO uint8_t HSICALR; /*!< HSI Calibration Register */ + __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */ + __IO uint8_t HSIUNLCKR; /*!< HSI Unlock Register */ + __IO uint8_t REGCSR; /*!< Main regulator control status register */ + __IO uint8_t PCKENR3; /*!< Peripheral Clock Gating Register 3 */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ +#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03) +#define CLK_CRTCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ICKCR_RESET_VALUE ((uint8_t)0x11) +#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00) +#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80) +#define CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00) +#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ECKCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_SCSR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSICALR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00) +#define CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9) +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_CKDIVR_CKM ((uint8_t)0x07) /*!< System clock prescaler mask */ + +#define CLK_CRTCR_RTCDIV ((uint8_t)0xE0) /*!< RTC clock prescaler mask*/ +#define CLK_CRTCR_RTCSEL ((uint8_t)0x1E) /*!< RTC clock output selection mask */ +#define CLK_CRTCR_RTCSWBSY ((uint8_t)0x01) /*!< RTC clock switch busy */ + +#define CLK_ICKCR_BEEPAHALT ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */ +#define CLK_ICKCR_FHWU ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKCR_SAHALT ((uint8_t)0x10) /*!< Slow Active-halt mode */ +#define CLK_ICKCR_LSIRDY ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */ +#define CLK_ICKCR_LSION ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKCR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKCR_HSION ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_PCKENR1_TIM2 ((uint8_t)0x01) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM3 ((uint8_t)0x02) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM4 ((uint8_t)0x04) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_I2C1 ((uint8_t)0x08) /*!< I2C1 clock enable */ +#define CLK_PCKENR1_SPI1 ((uint8_t)0x10) /*!< SPI1 clock enable */ +#define CLK_PCKENR1_USART1 ((uint8_t)0x20) /*!< USART1 clock enable */ +#define CLK_PCKENR1_BEEP ((uint8_t)0x40) /*!< BEEP clock enable */ +#define CLK_PCKENR1_DAC ((uint8_t)0x80) /*!< DAC clock enable */ + +#define CLK_PCKENR2_ADC1 ((uint8_t)0x01) /*!< ADC1 clock enable */ +#define CLK_PCKENR2_TIM1 ((uint8_t)0x02) /*!< TIM1 clock enable */ +#define CLK_PCKENR2_RTC ((uint8_t)0x04) /*!< RTC clock enable */ +#define CLK_PCKENR2_LCD ((uint8_t)0x08) /*!< LCD clock enable */ +#define CLK_PCKENR2_DMA1 ((uint8_t)0x10) /*!< DMA1 clock enable */ +#define CLK_PCKENR2_COMP ((uint8_t)0x20) /*!< Comparator clock enable */ +#define CLK_PCKENR2_BOOTROM ((uint8_t)0x80) /*!< Boot ROM clock enable */ + +#define CLK_PCKENR3_AES ((uint8_t)0x01) /*!< AES clock enable */ +#define CLK_PCKENR3_TIM5 ((uint8_t)0x02) /*!< Timer 5 clock enable */ +#define CLK_PCKENR3_SPI2 ((uint8_t)0x04) /*!< SPI2 clock enable */ +#define CLK_PCKENR3_UASRT2 ((uint8_t)0x08) /*!< USART2 clock enable */ +#define CLK_PCKENR3_USART3 ((uint8_t)0x10) /*!< USART3 clock enable */ + +#define CLK_CCOR_CCODIV ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */ +#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOSWBSY ((uint8_t)0x01) /*!< Configurable clock output switch busy flag */ + +#define CLK_ECKCR_LSEBYP ((uint8_t)0x20) /*!< Low speed external clock bypass */ +#define CLK_ECKCR_HSEBYP ((uint8_t)0x10) /*!< High speed external clock bypass */ +#define CLK_ECKCR_LSERDY ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */ +#define CLK_ECKCR_LSEON ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */ +#define CLK_ECKCR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKCR_HSEON ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_SCSR_CKM ((uint8_t)0x0F) /*!< System clock status bits */ + +#define CLK_SWR_SWI ((uint8_t)0x0F) /*!< System clock selection bits */ + +#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy */ + +#define CLK_CSSR_CSSDGON ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */ +#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ + +#define CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */ +#define CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01) /*!< BEEP clock busy in switch */ + +#define CLK_HSICALR_HSICAL ((uint8_t)0xFF) /*!< Copy of otpion byte trimming HSI oscillator */ + +#define CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */ + +#define CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock */ + +#define CLK_REGCSR_EEREADY ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */ +#define CLK_REGCSR_EEBUSY ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */ +#define CLK_REGCSR_LSEPD ((uint8_t)0x20) /*!< LSE power-down */ +#define CLK_REGCSR_HSEPD ((uint8_t)0x10) /*!< HSE power-down */ +#define CLK_REGCSR_LSIPD ((uint8_t)0x08) /*!< LSI power-down */ +#define CLK_REGCSR_HSIPD ((uint8_t)0x04) /*!< HSI power-down */ +#define CLK_REGCSR_REGOFF ((uint8_t)0x02) /*!< Main regulator OFF */ +#define CLK_REGCSR_REGREADY ((uint8_t)0x01) /*!< Main regulator ready */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Comparator interface (COMP) + */ + +typedef struct COMP_struct +{ + __IO uint8_t CSR1; /*!< Control status register 1 */ + __IO uint8_t CSR2; /*!< Control status register 2 */ + __IO uint8_t CSR3; /*!< Control status register 3 */ + __IO uint8_t CSR4; /*!< Control status register 4 */ + __IO uint8_t CSR5; /*!< Control status register 5 */ +} +COMP_TypeDef; + + +/** @addtogroup COMP_Registers_Reset_Value + * @{ + */ +#define COMP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR2_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR3_RESET_VALUE ((uint8_t)0xC0) +#define COMP_CSR4_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR5_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup COMP_Registers_Bits_Definition + * @{ + */ + +/* CSR1 */ +#define COMP_CSR1_IE1 ((uint8_t)0x20) /*!< Comparator 1 Interrupt Enable Mask. */ +#define COMP_CSR1_EF1 ((uint8_t)0x10) /*!< Comparator 1 Event Flag Mask. */ +#define COMP_CSR1_CMP1OUT ((uint8_t)0x08) /*!< Comparator 1 Ouptput Mask. */ +#define COMP_CSR1_STE ((uint8_t)0x04) /*!< Schmitt trigger enable Mask. */ +#define COMP_CSR1_CMP1 ((uint8_t)0x03) /*!< Comparator 1 Configuration Mask. */ + +/* CSR2 */ +#define COMP_CSR2_IE2 ((uint8_t)0x20) /*!< Comparator 2 Interrupt Enable Mask. */ +#define COMP_CSR2_EF2 ((uint8_t)0x10) /*!< Comparator 2 Event Flag Mask. */ +#define COMP_CSR2_CMP2OUT ((uint8_t)0x08) /*!< Comparator 2 Ouptput Mask. */ +#define COMP_CSR2_SPEED ((uint8_t)0x04) /*!< Comparator 2 speed modeMask. */ +#define COMP_CSR2_CMP2 ((uint8_t)0x03) /*!< Comparator 2 Configuration Mask. */ + +/* CSR3 */ +#define COMP_CSR3_OUTSEL ((uint8_t)0xC0) /*!< Comparator 2 output selection Mask. */ +#define COMP_CSR3_INSEL ((uint8_t)0x38) /*!< Inversion input selection Mask. */ +#define COMP_CSR3_VREFEN ((uint8_t)0x04) /*!< Internal reference voltage Enable Mask. */ +#define COMP_CSR3_WNDWE ((uint8_t)0x02) /*!< Window Mode Enable Mask. */ +#define COMP_CSR3_VREFOUTEN ((uint8_t)0x01) /*!< VREF Output Enable Mask. */ + +/* CSR4 */ +#define COMP_CSR4_NINVTRIG ((uint8_t)0x38) /*!< COMP2 non-inverting input Mask. */ +#define COMP_CSR4_INVTRIG ((uint8_t)0x07) /*!< COMP2 inverting input Mask. */ + +/* CSR5 */ +#define COMP_CSR5_DACTRIG ((uint8_t)0x38) /*!< DAC outputs Mask. */ +#define COMP_CSR5_VREFTRIG ((uint8_t)0x07) /*!< VREF outputs Mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief External Interrupt Controller (EXTI) + */ +typedef struct EXTI_struct +{ + __IO uint8_t CR1; /*!< The four LSB EXTI pin sensitivity */ + __IO uint8_t CR2; /*!< The four MSB EXTI pin sensitivity */ + __IO uint8_t CR3; /*!< EXTI port B & port D sensitivity */ + __IO uint8_t SR1; /*!< Pins Status flag register 1 */ + __IO uint8_t SR2; /*!< Ports Status flage register 2 */ + __IO uint8_t CONF1; /*!< Port interrupt selector */ + uint8_t RESERVED[4]; /*!< reserved area */ + __IO uint8_t CR4; /*!< EXTI port G & port H sensitivity */ + __IO uint8_t CONF2; /*!< Port interrupt selector */ +} +EXTI_TypeDef; + +/** @addtogroup EXTI_Registers_Reset_Value + * @{ + */ + +#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR3_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR4_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup EXTI_Registers_Bits_Definition + * @{ + */ +/* CR1 */ +#define EXTI_CR1_P3IS ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P2IS ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P1IS ((uint8_t)0x0C) /*!< EXTI Pin 1 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P0IS ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */ + +/* CR2 */ +#define EXTI_CR2_P7IS ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P6IS ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P5IS ((uint8_t)0x0C) /*!< EXTI Pin 5 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P4IS ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */ + +/* CR3 */ +#define EXTI_CR3_PBIS ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PDIS ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PEIS ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PFIS ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */ + +/* CONF1 */ +#define EXTI_CONF1_PBLIS ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */ +#define EXTI_CONF1_PBHIS ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */ +#define EXTI_CONF1_PDLIS ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */ +#define EXTI_CONF1_PDHIS ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */ +#define EXTI_CONF1_PELIS ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */ +#define EXTI_CONF1_PEHIS ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */ +#define EXTI_CONF1_PFLIS ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */ +#define EXTI_CONF1_PFES ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */ + +/* CR4 */ +#define EXTI_CR4_PGIS ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */ +#define EXTI_CR4_PHIS ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */ + +/* CONF2 */ +#define EXTI_CONF2_PFHIS ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */ +#define EXTI_CONF2_PGLIS ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */ +#define EXTI_CONF2_PGHIS ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */ +#define EXTI_CONF2_PHLIS ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */ +#define EXTI_CONF2_PHHIS ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */ +#define EXTI_CONF2_PGBS ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */ +#define EXTI_CONF2_PHDS ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief FLASH and Data EEPROM + */ +typedef struct FLASH_struct +{ + __IO uint8_t CR1; /*!< Flash control register 1 */ + __IO uint8_t CR2; /*!< Flash control register 2 */ + __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ + __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ + __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ +} +FLASH_TypeDef; + +/** @addtogroup FLASH_Registers_Reset_Value + * @{ + */ +#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) +#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) +#define FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE) +#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x56) +#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) + + +/** + * @} + */ + +/** @addtogroup FLASH_Registers_Bits_Definition + * @{ + */ +#define FLASH_CR1_EEPM ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */ +#define FLASH_CR1_WAITM ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */ +#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */ +#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time Mask */ + +#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Enable write access to option bytes*/ +#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word write once Mask */ +#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block Mask */ +#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode Mask */ +#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block Mask */ + +#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag Mask */ +#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */ +#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag Mask */ +#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */ +#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page Mask */ + +#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ + +#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ + + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Inter-Integrated Circuit (I2C) + */ +typedef struct I2C_struct +{ + __IO uint8_t CR1; /*!< I2C control register 1 */ + __IO uint8_t CR2; /*!< I2C control register 2 */ + __IO uint8_t FREQR; /*!< I2C frequency register */ + __IO uint8_t OARL; /*!< I2C own address register 1 LSB */ + __IO uint8_t OARH; /*!< I2C own address register 1 MSB */ + __IO uint8_t OAR2; /*!< I2C own address register 2 */ + __IO uint8_t DR; /*!< I2C data register */ + __IO uint8_t SR1; /*!< I2C status register 1 */ + __IO uint8_t SR2; /*!< I2C status register 2 */ + __IO uint8_t SR3; /*!< I2C status register 3 */ + __IO uint8_t ITR; /*!< I2C interrupt & DMA register */ + __IO uint8_t CCRL; /*!< I2C clock control register low */ + __IO uint8_t CCRH; /*!< I2C clock control register high */ + __IO uint8_t TRISER; /*!< I2C maximum rise time register */ + __IO uint8_t PECR; /*!< I2CPacket Error Checking register */ +} +I2C_TypeDef; + +/** @addtogroup I2C_Registers_Reset_Value + * @{ + */ +#define I2C_CR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_CR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARL_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARH_RESET_VALUE ((uint8_t)0x00) +#define I2C_OAR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_DR_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR3_RESET_VALUE ((uint8_t)0x00) +#define I2C_ITR_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) +#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) +#define I2C_PECR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup I2C_Registers_Bits_Definition + * @{ + */ + +#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ +#define I2C_CR1_ENPEC ((uint8_t)0x20) /*!< PEC Enable */ +#define I2C_CR1_ARP ((uint8_t)0x10) /*!< ARP Enable */ +#define I2C_CR1_SMBTYPE ((uint8_t)0x08) /*!< SMBus type */ +#define I2C_CR1_SMBUS ((uint8_t)0x02) /*!< SMBus mode */ +#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ + +#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ +#define I2C_CR2_ALERT ((uint8_t)0x20) /*!< SMBus Alert*/ +#define I2C_CR2_PEC ((uint8_t)0x10) /*!< Packet Error Checking */ +#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ +#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ +#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ +#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ + +#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ + +#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ + +#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ +#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address mode configuration */ +#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ + +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ + +#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ + +#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ + +#define I2C_SR2_SMBALERT ((uint8_t)0x80) /*!< SMBus Alert */ +#define I2C_SR2_TIMEOUT ((uint8_t)0x40) /*!< Time out or TLow error */ +#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ +#define I2C_SR2_PECERR ((uint8_t)0x10) /*!< PEC error in reception */ +#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ +#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ +#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ +#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ + +#define I2C_SR3_DUALF ((uint8_t)0x80) /*!< Dual flag (Slave mode) */ +#define I2C_SR3_SMBHOST ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR3_SMBDEFAULT ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */ +#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ +#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ +#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ +#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ + +#define I2C_ITR_LAST ((uint8_t)0x10) /*!< DMA Last transfer */ +#define I2C_ITR_DMAEN ((uint8_t)0x08) /*!< DMA request Enable */ +#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ +#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ +#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ + +#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ + +#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ +#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ +#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ + +#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +#define I2C_PECR_PEC ((uint8_t)0xFF) /*!< Packet error checking */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief IR digital interface (IRTIM) + */ +typedef struct IRTIM_struct +{ + __IO uint8_t CR; /*!< control register */ +} +IRTIM_TypeDef; +/** @addtogroup IRTIM_Registers_Reset_Value + * @{ + */ +#define IRTIM_CR_RESET_VALUE ((uint8_t)0x00) + + +/** +* @} +*/ + +/** @addtogroup IRTIM_Registers_Bits_Definition + * @{ + */ +/* CR*/ +#define IRTIM_CR_EN ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */ +#define IRTIM_CR_HSEN ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Interrupt Controller (ITC) + */ +typedef struct ITC_struct +{ + __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ + __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ + __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ + __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ + __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ + __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ + __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ + __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ +} +ITC_TypeDef; + +/** @addtogroup ITC_Registers_Reset_Value + * @{ + */ +#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Internal Low Speed Watchdog (IWDG) + */ +typedef struct IWDG_struct +{ + __IO uint8_t KR; /*!< Low Speed Watchdog Key Register */ + __IO uint8_t PR; /*!< Low Speed Watchdog Prescaler Register */ + __IO uint8_t RLR; /*!< Low Speed Watchdog Reload Register */ +} +IWDG_TypeDef; + +/** @addtogroup IWDG_Registers_Reset_Value + * @{ + */ +#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) /*! + #define enableInterrupts() _rim_() /*! + #define enableInterrupts() __enable_interrupt() /* enable interrupts */ + #define disableInterrupts() __disable_interrupt() /* disable interrupts */ + #define rim() __enable_interrupt() /* enable interrupts */ + #define sim() __disable_interrupt() /* disable interrupts */ + #define nop() __no_operation() /* No Operation */ + #define trap() __trap() /* Trap (soft IT) */ + #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ + #define wfe() __wait_for_event(); /* Wait for event */ + #define halt() __halt() /* Halt */ +#endif /* _RAISONANCE_ */ + +/*============================== Interrupt vector Handling ========================*/ + +#ifdef _COSMIC_ + #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) + #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) +#endif /* _COSMIC_ */ + +#ifdef _RAISONANCE_ + #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b + #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap +#endif /* _RAISONANCE_ */ + +#ifdef _IAR_ + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define INTERRUPT_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define INTERRUPT_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) +#endif /* _IAR_ */ + +/*============================== Interrupt Handler declaration ========================*/ +#ifdef _COSMIC_ + #define INTERRUPT @far @interrupt +#elif defined(_IAR_) + #define INTERRUPT __interrupt +#endif /* _COSMIC_ */ + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reseted if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((uint8_t)1<<(Place))) : \ + ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) + +#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE(STATE) \ + (((STATE) == SET) || \ + ((STATE) == RESET)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + + +#endif /* __STM8L15x_H */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/os/hal/platforms/STM8S/hal_lld.c b/os/hal/platforms/STM8S/hal_lld.c new file mode 100644 index 000000000..ddc7c79b6 --- /dev/null +++ b/os/hal/platforms/STM8S/hal_lld.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/hal_lld.c + * @brief STM8S HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * @details Clock sources initialization, HSI is assumed to be already + * started after reset. + * @note If the @p STM8S_CLOCK_INIT option is set to @p FALSE then the + * initialization is not performed and is left to the application. + * + * @notapi + */ +void hal_lld_init(void) { + +#if !STM8S_NO_CLOCK_INIT + /* Makes sure that HSI is stable before proceeding.*/ + CLK->ICKR |= CLK_ICKR_HSIEN; + while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0) + ; + + /* LSI startup and stabilization if required.*/ +#if STM8S_LSI_ENABLED + CLK->ICKR |= CLK_ICKR_LSIEN; + while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0) + ; +#endif + + /* HSE startup and stabilization if required.*/ +#if STM8S_HSE_ENABLED + CLK->ECKR |= CLK_ECKR_HSEEN; + while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0) + ; +#endif + + /* Setting up clock dividers.*/ + CLK->CKDIVR = (STM8S_HSI_DIVIDER << 3) | (STM8S_CPU_DIVIDER << 0); + + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8S_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8S_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + + /* Clocks initially all disabled.*/ + CLK->PCKENR1 = 0; + CLK->PCKENR2 = 0; + + /* Other clock related initializations.*/ + CLK->CSSR = 0; + CLK->CCOR = 0; + + /* HSI disabled if it is no more required.*/ +#if !STM8S_HSI_ENABLED + CLK->ICKR &= ~CLK_ICKR_HSIEN; +#endif +#endif /* !STM8S_NO_CLOCK_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM8S/hal_lld.h b/os/hal/platforms/STM8S/hal_lld.h new file mode 100644 index 000000000..0bf87ac01 --- /dev/null +++ b/os/hal/platforms/STM8S/hal_lld.h @@ -0,0 +1,222 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/hal_lld.h + * @brief STM8S HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * . + * One of the following macros must also be defined: + * - STM8S103. + * - STM8S105. + * - STM8S207. + * - STM8S208. + * - STM8S903. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#undef FALSE +#undef TRUE + +#if defined(STM8S208) || defined(STM8S207) || defined(STM8S105) || \ + defined(STM8S103) || defined(STM8S903) +#include "stm8s.h" +#else +#error "unsupported or invalid STM8 platform" +#endif + +#define FALSE 0 +#define TRUE (!FALSE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM8S" + +#define LSICLK 128000 /**< Low speed internal clock. */ +#define HSICLK 16000000 /**< High speed internal clock. */ + +#define CLK_SYSSEL_HSI 0xE1 /**< HSI clock selector. */ +#define CLK_SYSSEL_LSI 0xD2 /**< LSI clock selector. */ +#define CLK_SYSSEL_HSE 0xB4 /**< HSE clock selector. */ + +#define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */ +#define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */ +#define CLK_HSI_DIV4 2 /**< HSI clock divided by 4. */ +#define CLK_HSI_DIV8 3 /**< HSI clock divided by 8. */ + +#define CLK_CPU_DIV1 0 /**< CPU clock divided by 1. */ +#define CLK_CPU_DIV2 1 /**< CPU clock divided by 2. */ +#define CLK_CPU_DIV4 2 /**< CPU clock divided by 4. */ +#define CLK_CPU_DIV8 3 /**< CPU clock divided by 8. */ +#define CLK_CPU_DIV16 4 /**< CPU clock divided by 16. */ +#define CLK_CPU_DIV32 5 /**< CPU clock divided by 32. */ +#define CLK_CPU_DIV64 6 /**< CPU clock divided by 64. */ +#define CLK_CPU_DIV128 7 /**< CPU clock divided by 128. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8S_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8S_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8S_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8S_HSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8S_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8S_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8S_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8S_HSE_ENABLED TRUE +#endif + +/** + * @brief Clock source setting. + */ +#if !defined(STM8S_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#endif + +/** + * @brief HSI clock divider. + */ +#if !defined(STM8S_HSI_DIVIDER) || defined(__DOXYGEN__) +#define STM8S_HSI_DIVIDER CLK_HSI_DIV8 +#endif + +/** + * @brief CPU clock divider. + */ +#if !defined(STM8S_CPU_DIVIDER) || defined(__DOXYGEN__) +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM8S_HSI_DIVIDER != CLK_HSI_DIV1) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV2) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV4) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV8) +#error "specified invalid HSI divider" +#endif + +#if (STM8S_CPU_DIVIDER != CLK_CPU_DIV1) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV2) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV4) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV8) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV16) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV32) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV64) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV128) +#error "specified invalid CPU divider" +#endif + +#if STM8S_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if !STM8S_HSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8S_LSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8S_HSE_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE) +#error "requested HSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8SL_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define SYSCLK (HSICLK / 8) +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI +#define SYSCLK (HSICLK / (1 << STM8S_HSI_DIVIDER)) +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI +#define SYSCLK LSICLK +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE +#define SYSCLK HSECLK +#else +#error "specified invalid clock source" +#endif + +/** + * @brief CPU clock. + * @details On the STM8SS the CPU clock can be programmed to be a fraction of + * the system clock. + */ +#define CPUCLK (SYSCLK / (1 << STM8S_CPU_DIVIDER)) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/pal_lld.c b/os/hal/platforms/STM8S/pal_lld.c new file mode 100644 index 000000000..b377abc63 --- /dev/null +++ b/os/hal/platforms/STM8S/pal_lld.c @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/pal_lld.c + * @brief STM8S GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->DDR &= ~mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_OUTPUT_PUSHPULL_SLOW: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 |= mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/pal_lld.h b/os/hal/platforms/STM8S/pal_lld.h new file mode 100644 index 000000000..86246a05b --- /dev/null +++ b/os/hal/platforms/STM8S/pal_lld.h @@ -0,0 +1,229 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/pal_lld.h + * @brief STM8S GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/** + * @brief STM8S specific alternate push-pull slow output mode. + */ +#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 + +/** + * @brief STM8S specific alternate open-drain slow output mode. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(STM8S105) || defined(__DOXYGEN__) + GPIO_TypeDef P[7]; +#elif defined(STM8S207) || defined(STM8S208) + GPIO_TypeDef P[9]; +#else + GPIO_TypeDef P[6]; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports as a whole. + */ +#define IOPORTS ((PALConfig *)0x5000) + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) || \ + defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 GPIOG +#endif + +#if defined(STM8S207) || defined(STM8S208) || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 GPIOH + +/** + * @brief GPIO port I identifier. + */ +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) (*IOPORTS = *(config)) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/platform.dox b/os/hal/platforms/STM8S/platform.dox new file mode 100644 index 000000000..9d259cadc --- /dev/null +++ b/os/hal/platforms/STM8S/platform.dox @@ -0,0 +1,119 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup STM8S STM8S Drivers + * @details This section describes all the supported drivers on the STM8S + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM8S_HAL STM8S Initialization Support + * @details The STM8S HAL support is responsible for system initialization. + * + * @section stm8s_hal_1 Supported HW resources + * - CLK. + * . + * @section stm8s_hal_2 STM8S HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_PAL STM8S PAL Support + * @details The STM8S PAL driver uses the GPIO peripherals. + * + * @section stm8s_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG (where present). + * - GPIOH (where present). + * - GPIOI (where present). + * . + * @section stm8s_pal_2 STM8S PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special STM8S instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm8s_pal_3 Supported PAL setup modes + * The STM8S PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm8s_pal_4 Suboptimal behavior + * The STM8S GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_SERIAL STM8S Serial Support + * @details The STM8S Serial driver uses the UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm8s_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART1. + * - UART2 (where present). + * - UART3 (where present). + * . + * @section stm8s_serial_2 STM8S Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_SPI STM8S SPI Support + * @details The SPI driver supports the STM8S SPI peripheral in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section stm8s_spi_1 Supported HW resources + * - SPI. + * . + * @section stm8s_spi_2 STM8S SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * . + * @ingroup STM8S + */ diff --git a/os/hal/platforms/STM8S/serial_lld.c b/os/hal/platforms/STM8S/serial_lld.c new file mode 100644 index 000000000..fc49540a6 --- /dev/null +++ b/os/hal/platforms/STM8S/serial_lld.c @@ -0,0 +1,446 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/serial_lld.c + * @brief STM8S low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief UART1 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief UART2 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief UART3 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static ROMCONST SerialConfig default_config = { + BRR(SERIAL_DEFAULT_BITRATE), + SD_MODE_PARITY_NONE | SD_MODE_STOP_1 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(SerialDriver *sdp, uint8_t sr) { + flagsmask_t sts = 0; + + /* Note, SR register bit definitions are equal for all UARTs so using + the UART1 definitions is fine.*/ + if (sr & UART1_SR_OR) + sts |= SD_OVERRUN_ERROR; + if (sr & UART1_SR_NF) + sts |= SD_NOISE_ERROR; + if (sr & UART1_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & UART1_SR_PE) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + UART1->CR2 |= UART1_CR2_TIEN; +} + +/** + * @brief UART1 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart1_init(const SerialConfig *config) { + + UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART1->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART1->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART1->CR2 = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN; + UART1->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 1; + (void)UART1->SR; + (void)UART1->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart1_deinit(void) { + + UART1->CR1 = UART1_CR1_UARTD; + UART1->CR2 = 0; + UART1->CR3 = 0; + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 0; +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + UART2->CR2 |= UART2_CR2_TIEN; +} + +/** + * @brief UART2 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart2_init(const SerialConfig *config) { + + UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART2->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART2->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART2->CR2 = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN; + UART2->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 1; + (void)UART2->SR; + (void)UART2->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart2_deinit(void) { + + UART2->CR1 = UART2_CR1_UARTD; + UART2->CR2 = 0; + UART2->CR3 = 0; + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 0; +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + UART3->CR2 |= UART3_CR2_TIEN; +} + +/** + * @brief UART3 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart3_init(const SerialConfig *config) { + + UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART3->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART3->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART3->CR2 = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN; + UART3->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART3->CR4 = 0; + UART3->CR6 = 0; + (void)UART3->SR; + (void)UART3->DR; +} + +/** + * @brief UART3 de-initialization. + */ +static void uart3_deinit(void) { + + UART3->CR1 = UART3_CR1_UARTD; + UART3->CR2 = 0; + UART3->CR3 = 0; + UART3->CR4 = 0; + UART3->CR6 = 0; +} +#endif /* STM8S_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** + * @brief IRQ 17 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(17) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN; + else + UART1->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 18 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(18) { + uint8_t sr = UART1->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF | + UART1_SR_FE | UART1_SR_PE)) + set_error(&SD1, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, UART1->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN; + else + UART2->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART2->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF | + UART2_SR_FE | UART2_SR_PE)) + set_error(&SD2, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, UART2->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART2 */ + +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD3); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN; + else + UART3->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART3->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF | + UART3_SR_FE | UART3_SR_PE)) + set_error(&SD3, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD3, UART3->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM8S_SERIAL_USE_UART1 + sdObjectInit(&SD1, NULL, notify1); + CLK->PCKENR1 |= CLK_PCKENR1_UART1; /* PCKEN12, clock source. */ + UART1->CR1 = UART1_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8S_SERIAL_USE_UART2 + sdObjectInit(&SD2, NULL, notify2); + CLK->PCKENR1 |= CLK_PCKENR1_UART2; /* PCKEN13, clock source. */ + UART2->CR1 = UART2_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8S_SERIAL_USE_UART3 + sdObjectInit(&SD3, NULL, notify3); + CLK->PCKENR1 |= CLK_PCKENR1_UART3; /* PCKEN13, clock source. */ + UART3->CR1 = UART3_CR1_UARTD; /* UARTD (low power). */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if STM8S_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_init(config); + return; + } +#endif +#if STM8S_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_init(config); + return; + } +#endif +#if STM8S_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if STM8S_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_deinit(); + return; + } +#endif +#if STM8S_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_deinit(); + return; + } +#endif +#if STM8S_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_deinit(); + return; + } +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/serial_lld.h b/os/hal/platforms/STM8S/serial_lld.h new file mode 100644 index 000000000..9dfca2262 --- /dev/null +++ b/os/hal/platforms/STM8S/serial_lld.h @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/serial_lld.h + * @brief STM8S low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ + +#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ +#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ +#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ +#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART1 TRUE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART2 TRUE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART3 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART2 && STM8S_SERIAL_USE_UART3 +#error "STM8S UART2 and UART3 cannot be used together" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate register. + */ + uint16_t sc_brr; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define BRR(b) (SYSCLK / (b)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM8S_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM8S_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/spi_lld.c b/os/hal/platforms/STM8S/spi_lld.c new file mode 100644 index 000000000..9a9256c61 --- /dev/null +++ b/os/hal/platforms/STM8S/spi_lld.c @@ -0,0 +1,289 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/spi_lld.c + * @brief STM8S low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__) +/** + * @brief IRQ 10 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(10) { + + CH_IRQ_PROLOGUE(); + + if ((SPI->SR & SPI_SR_OVR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + STM8S_SPI_ERROR_HOOK(&SPID1); + } + /* Handling the DR register like it is a FIFO with depth>1 in order to + handle the case where a frame arrives immediately after reading the + DR register.*/ + while ((SPI->SR & SPI_SR_RXNE) != 0) { + if (SPID1.rxptr != NULL) + *SPID1.rxptr++ = SPI->DR; + else + (void)SPI->DR; + if (--SPID1.rxcnt == 0) { + chDbgAssert(SPID1.txcnt == 0, + "IRQ10, #1", "counter out of synch"); + /* Stops all the IRQ sources.*/ + SPI->ICR = 0; + /* Portable SPI ISR code defined in the high level driver, note, it + is a macro.*/ + _spi_isr_code(&SPID1); + /* Goto because it is mandatory to go through the epilogue, cannot + just return.*/ + goto exit_isr; + } + } + /* Loading the DR register.*/ + if ((SPI->SR & SPI_SR_TXE) != 0) { + if (SPID1.txptr != NULL) + SPI->DR = *SPID1.txptr++; + else + SPI->DR = 0xFF; + } + +exit_isr: + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if STM8S_SPI_USE_SPI + spiObjectInit(&SPID1); +#endif /* STM8S_SPI_USE_SPI */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* Clock activation.*/ + CLK->PCKENR1 |= CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ + + /* Configuration.*/ + SPI->CR1 = 0; + SPI->CR1 = spip->config->cr1 | SPI_CR1_MSTR; + SPI->CR2 = SPI_CR2_SSI | SPI_CR2_SSM; + SPI->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + (void)spip; + + /* Reset state.*/ + SPI->CR1 = 0; + SPI->CR2 = 0; + SPI->ICR = 0; + + /* Clock de-activation.*/ + CLK->PCKENR1 &= (uint8_t)~CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) { + + (void)spip; + + SPI->DR = (uint32_t)frame; + while ((SPI->SR & SPI_SR_RXNE) == 0) + ; + return (uint16_t)SPI->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/spi_lld.h b/os/hal/platforms/STM8S/spi_lld.h new file mode 100644 index 000000000..8b87b81fc --- /dev/null +++ b/os/hal/platforms/STM8S/spi_lld.h @@ -0,0 +1,187 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM8S/spi_lld.h + * @brief STM8S low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SPI_USE_SPI) || defined(__DOXYGEN__) +#define STM8S_SPI_USE_SPI TRUE +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(STM8S_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM8S_SPI_USE_SPI +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint8_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Number of bytes yet to be received. + */ + uint16_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + uint8_t *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint16_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const uint8_t *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/stm8s.h b/os/hal/platforms/STM8S/stm8s.h new file mode 100644 index 000000000..07a8362d3 --- /dev/null +++ b/os/hal/platforms/STM8S/stm8s.h @@ -0,0 +1,2725 @@ +/** + ****************************************************************************** + * @file stm8s.h + * @author MCD Application Team + * @version V2.1.0 + * @date 18-November-2011 + * @brief This file contains all HW registers definitions and memory mapping. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_H +#define __STM8S_H + +/** @addtogroup STM8S_StdPeriph_Driver + * @{ + */ + +/* Uncomment the line below according to the target STM8S or STM8A device used in your + application. */ + + /* #define STM8S208 */ /*!< STM8S High density devices with CAN */ + /* #define STM8S207 */ /*!< STM8S High density devices without CAN */ + /* #define STM8S007 */ /*!< STM8S Value Line High density devices */ + /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */ + /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */ + /* #define STM8S105 */ /*!< STM8S Medium density devices */ + /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */ + /* #define STM8AF626x */ /*!< STM8A Medium density devices */ + /* #define STM8S103 */ /*!< STM8S Low density devices */ + /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */ + /* #define STM8S903 */ /*!< STM8S Low density devices */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax, + STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory + density ranges between 32 to 128 Kbytes + - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68, + STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory + density ranges between 8 to 32 Kbytes + - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers + where the Flash memory density ranges between 32 to 128 Kbytes. + - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers + where the Flash memory density ranges between 16 to 32-Kbytes. + - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers + where the Flash density is 8 Kbytes. */ + +#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \ + !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \ + !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \ + !defined (STM8S003)&& !defined (STM8S005) + #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)" +#endif + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #define _COSMIC_ +#elif defined(__RCST7__) + #define _RAISONANCE_ +#elif defined(__ICCSTM8__) + #define _IAR_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ +/* CHIBIOS FIX */ +/* #define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_Value + #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ + defined (STM8AF62Ax) + #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/ + #else + #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/ + #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */ +#endif /* HSE_Value */ + +/** + * @brief Definition of Device on-chip RC oscillator frequencies + */ +#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ +#define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define EEPROM @eeprom + #define CONST const +#elif defined (_RAISONANCE_) /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define EEPROM eeprom + #define CONST code + #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ + defined (STM8AF62Ax) + /*!< Used with memory Models for code higher than 64K */ + #define MEMCPY fmemcpy + #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */ + /*!< Used with memory Models for code less than 64K */ + #define MEMCPY memcpy + #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */ +#else /*_IAR_*/ + #define FAR __far + #define NEAR __near + #define TINY __tiny + #define EEPROM __eeprom + #define CONST const +#endif /* __CSMC__ */ + +/* For FLASH routines, select whether pointer will be declared as near (2 bytes, + to handle code smaller than 64KB) or far (3 bytes, to handle code larger + than 64K) */ + +#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \ + defined (STM8S903) || defined (STM8AF626x) +/*!< Used with memory Models for code smaller than 64K */ + #define PointerAttr NEAR +#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */ +/*!< Used with memory Models for code higher than 64K */ + #define PointerAttr FAR +#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */ + +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#if !defined (RAM_EXECUTION) +/* #define RAM_EXECUTION (1) */ +#endif /* RAM_EXECUTION */ + +#ifdef RAM_EXECUTION + #ifdef _COSMIC_ + #define IN_RAM(a) a + #elif defined (_RAISONANCE_) /* __RCST7__ */ + #define IN_RAM(a) a inram + #else /*_IAR_*/ + #define IN_RAM(a) __ramfunc a + #endif /* _COSMIC_ */ +#else + #define IN_RAM(a) a +#endif /* RAM_EXECUTION */ + +/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/ +#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */ +#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01) /*!< [23:16] sub1 version */ +#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ +#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ +#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM8S_STDPERIPH_VERSION_RC)) + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types and constants ----------------------------------------------*/ + +/** @addtogroup Exported_types + * @{ + */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*!< Signed integer types */ +/* CHIBIOS FIX */ +#if 0 +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +#endif + +/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */ + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX (255) +#define S8_MAX (127) +#define S8_MIN (-128) +#define U16_MAX (65535u) +#define S16_MAX (32767) +#define S16_MIN (-32768) +#define U32_MAX (4294967295uL) +#define S32_MAX (2147483647) +#define S32_MIN (-2147483648uL) + +/** + * @} + */ + +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/** + * @brief General Purpose I/Os (GPIO) + */ +typedef struct GPIO_struct +{ + __IO uint8_t ODR; /*!< Output Data Register */ + __IO uint8_t IDR; /*!< Input Data Register */ + __IO uint8_t DDR; /*!< Data Direction Register */ + __IO uint8_t CR1; /*!< Configuration Register 1 */ + __IO uint8_t CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ + +#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ + defined(STM8S903) || defined(STM8AF626x) +/** + * @brief Analog to Digital Converter (ADC1) + */ + typedef struct ADC1_struct + { + __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ + __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ + __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ + uint8_t RESERVED[12]; /*!< Reserved byte */ + __IO uint8_t CSR; /*!< ADC1 control status register */ + __IO uint8_t CR1; /*!< ADC1 configuration register 1 */ + __IO uint8_t CR2; /*!< ADC1 configuration register 2 */ + __IO uint8_t CR3; /*!< ADC1 configuration register 3 */ + __IO uint8_t DRH; /*!< ADC1 Data high */ + __IO uint8_t DRL; /*!< ADC1 Data low */ + __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */ + __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */ + __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/ + __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/ + __IO uint8_t LTRH; /*!< ADC1 low threshold register high */ + __IO uint8_t LTRL; /*!< ADC1 low threshold register low */ + __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */ + __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */ + __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */ + __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */ + } + ADC1_TypeDef; + +/** @addtogroup ADC1_Registers_Reset_Value + * @{ + */ + #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00) + #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00) + #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00) + #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00) + #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00) + #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00) + #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03) + #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF) + #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00) + #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00) + #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00) + #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC1_Registers_Bits_Definition + * @{ + */ + #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ + #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */ + #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ + #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */ + #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ + + #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ + #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ + #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ + + #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ + #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ + #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ + #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */ + + #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */ + #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */ + +#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Analog to Digital Converter (ADC2) + */ +#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax) + typedef struct ADC2_struct + { + __IO uint8_t CSR; /*!< ADC2 control status register */ + __IO uint8_t CR1; /*!< ADC2 configuration register 1 */ + __IO uint8_t CR2; /*!< ADC2 configuration register 2 */ + uint8_t RESERVED; /*!< Reserved byte */ + __IO uint8_t DRH; /*!< ADC2 Data high */ + __IO uint8_t DRL; /*!< ADC2 Data low */ + __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */ + __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */ + } + ADC2_TypeDef; + +/** @addtogroup ADC2_Registers_Reset_Value + * @{ + */ + #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00) + #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00) + #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00) + #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00) + #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC2_Registers_Bits_Definition + * @{ + */ + #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ + #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ + #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ + + #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ + #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ + #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ + + #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ + #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ + #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ + +#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Auto Wake Up (AWU) peripheral registers. + */ +typedef struct AWU_struct +{ + __IO uint8_t CSR; /*!< AWU Control status register */ + __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */ + __IO uint8_t TBR; /*!< AWU Time base selection register */ +} +AWU_TypeDef; + +/** @addtogroup AWU_Registers_Reset_Value + * @{ + */ +#define AWU_CSR_RESET_VALUE ((uint8_t)0x00) +#define AWU_APR_RESET_VALUE ((uint8_t)0x3F) +#define AWU_TBR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup AWU_Registers_Bits_Definition + * @{ + */ + +#define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */ +#define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */ +#define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */ + +#define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */ + +#define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + __IO uint8_t CSR; /*!< BEEP Control status register */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ +#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F) +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ +#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Clock Controller (CLK) + */ +typedef struct CLK_struct +{ + __IO uint8_t ICKR; /*!< Internal Clocks Control Register */ + __IO uint8_t ECKR; /*!< External Clocks Control Register */ + uint8_t RESERVED; /*!< Reserved byte */ + __IO uint8_t CMSR; /*!< Clock Master Status Register */ + __IO uint8_t SWR; /*!< Clock Master Switch Register */ + __IO uint8_t SWCR; /*!< Switch Control Register */ + __IO uint8_t CKDIVR; /*!< Clock Divider Register */ + __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + __IO uint8_t CSSR; /*!< Clock Security System Register */ + __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ + __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + uint8_t RESERVED1; /*!< Reserved byte */ + __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */ + __IO uint8_t SWIMCCR; /*!< SWIM clock control register */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ + +#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01) +#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1) +#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1) +#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18) +#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF) +#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF) +#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) +#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ +#define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ +#define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */ +#define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */ + +#define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */ + +#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/ + +#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */ +#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */ + +#define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */ +#define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */ +#define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */ +#define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */ +#define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */ +#define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */ +#define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */ +#define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */ + +#define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */ +#define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */ +#define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */ + +#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */ +#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ + +#define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */ +#define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */ +#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */ + +#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */ + +#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with complementary PWM outputs (TIM1) + */ + +typedef struct TIM1_struct +{ + __IO uint8_t CR1; /*!< control register 1 */ + __IO uint8_t CR2; /*!< control register 2 */ + __IO uint8_t SMCR; /*!< Synchro mode control register */ + __IO uint8_t ETR; /*!< external trigger register */ + __IO uint8_t IER; /*!< interrupt enable register*/ + __IO uint8_t SR1; /*!< status register 1 */ + __IO uint8_t SR2; /*!< status register 2 */ + __IO uint8_t EGR; /*!< event generation register */ + __IO uint8_t CCMR1; /*!< CC mode register 1 */ + __IO uint8_t CCMR2; /*!< CC mode register 2 */ + __IO uint8_t CCMR3; /*!< CC mode register 3 */ + __IO uint8_t CCMR4; /*!< CC mode register 4 */ + __IO uint8_t CCER1; /*!< CC enable register 1 */ + __IO uint8_t CCER2; /*!< CC enable register 2 */ + __IO uint8_t CNTRH; /*!< counter high */ + __IO uint8_t CNTRL; /*!< counter low */ + __IO uint8_t PSCRH; /*!< prescaler high */ + __IO uint8_t PSCRL; /*!< prescaler low */ + __IO uint8_t ARRH; /*!< auto-reload register high */ + __IO uint8_t ARRL; /*!< auto-reload register low */ + __IO uint8_t RCR; /*!< Repetition Counter register */ + __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ + __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ + __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ + __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ + __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ + __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ + __IO uint8_t CCR4H; /*!< capture/compare register 3 high */ + __IO uint8_t CCR4L; /*!< capture/compare register 3 low */ + __IO uint8_t BKR; /*!< Break Register */ + __IO uint8_t DTR; /*!< dead-time register */ + __IO uint8_t OISR; /*!< Output idle register */ +} +TIM1_TypeDef; + +/** @addtogroup TIM1_Registers_Reset_Value + * @{ + */ + +#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00) +#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_IER_RESET_VALUE ((uint8_t)0x00) +#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00) +#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00) +#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00) +#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00) +#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00) +#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF) +#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF) +#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00) +#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00) +#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00) +#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup TIM1_Registers_Bits_Definition + * @{ + */ +/* CR1*/ +#define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */ +#define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */ +#define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ +#define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ +#define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ +#define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ +/* CR2*/ +#define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */ +#define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */ +#define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */ +#define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */ +/* SMCR*/ +#define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */ +#define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */ +#define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */ +/*ETR*/ +#define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */ +#define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */ +#define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */ +#define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */ +/*IER*/ +#define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */ +#define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ +#define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/ +#define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ +#define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */ +#define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ +#define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */ +#define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ +#define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ +#define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */ +#define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ +#define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */ +#define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */ +#define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ +#define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */ +#define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ + +#define CCMR_TIxDirect_Set ((uint8_t)0x01) +/*CCER1*/ +#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ +#define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ +#define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */ +#define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */ +#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ +#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ +#define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTRH*/ +#define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ +/*CNTRL*/ +#define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCH*/ +#define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*PSCL*/ +#define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */ +/*ARR*/ +#define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*RCR*/ +#define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */ +/*CCR1*/ +#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ +/*CCR4*/ +#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ +#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ +/*BKR*/ +#define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */ +#define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */ +#define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */ +#define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */ +#define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */ +#define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */ +#define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */ +/*DTR*/ +#define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */ +/*OISR*/ +#define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ +#define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ +#define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ +#define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ +#define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ +#define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ +#define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM2) + */ + +typedef struct TIM2_struct +{ + __IO uint8_t CR1; /*!< control register 1 */ +#if defined(STM8S103) || defined(STM8S003) + uint8_t RESERVED1; /*!< Reserved register */ + uint8_t RESERVED2; /*!< Reserved register */ +#endif + __IO uint8_t IER; /*!< interrupt enable register */ + __IO uint8_t SR1; /*!< status register 1 */ + __IO uint8_t SR2; /*!< status register 2 */ + __IO uint8_t EGR; /*!< event generation register */ + __IO uint8_t CCMR1; /*!< CC mode register 1 */ + __IO uint8_t CCMR2; /*!< CC mode register 2 */ + __IO uint8_t CCMR3; /*!< CC mode register 3 */ + __IO uint8_t CCER1; /*!< CC enable register 1 */ + __IO uint8_t CCER2; /*!< CC enable register 2 */ + __IO uint8_t CNTRH; /*!< counter high */ + __IO uint8_t CNTRL; /*!< counter low */ + __IO uint8_t PSCR; /*!< prescaler register */ + __IO uint8_t ARRH; /*!< auto-reload register high */ + __IO uint8_t ARRL; /*!< auto-reload register low */ + __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ + __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ + __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ + __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ + __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ + __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ +} +TIM2_TypeDef; + +/** @addtogroup TIM2_Registers_Reset_Value + * @{ + */ + +#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00) +#define TIM2_IER_RESET_VALUE ((uint8_t)0x00) +#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00) +#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00) +#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00) +#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00) +#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF) +#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF) +#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00) +#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup TIM2_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ +#define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ +#define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ +#define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ +#define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTR*/ +#define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM3) + */ +typedef struct TIM3_struct +{ + __IO uint8_t CR1; /*!< control register 1 */ + __IO uint8_t IER; /*!< interrupt enable register */ + __IO uint8_t SR1; /*!< status register 1 */ + __IO uint8_t SR2; /*!< status register 2 */ + __IO uint8_t EGR; /*!< event generation register */ + __IO uint8_t CCMR1; /*!< CC mode register 1 */ + __IO uint8_t CCMR2; /*!< CC mode register 2 */ + __IO uint8_t CCER1; /*!< CC enable register 1 */ + __IO uint8_t CNTRH; /*!< counter high */ + __IO uint8_t CNTRL; /*!< counter low */ + __IO uint8_t PSCR; /*!< prescaler register */ + __IO uint8_t ARRH; /*!< auto-reload register high */ + __IO uint8_t ARRL; /*!< auto-reload register low */ + __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ + __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ + __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ + __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ +} +TIM3_TypeDef; + +/** @addtogroup TIM3_Registers_Reset_Value + * @{ + */ + +#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00) +#define TIM3_IER_RESET_VALUE ((uint8_t)0x00) +#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00) +#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00) +#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00) +#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00) +#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF) +#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF) +#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00) +#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup TIM3_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ +#define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ +#define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ +#define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ +#define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CNTR*/ +#define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 8-bit system timer (TIM4) + */ + +typedef struct TIM4_struct +{ + __IO uint8_t CR1; /*!< control register 1 */ +#if defined(STM8S103) || defined(STM8S003) + uint8_t RESERVED1; /*!< Reserved register */ + uint8_t RESERVED2; /*!< Reserved register */ +#endif + __IO uint8_t IER; /*!< interrupt enable register */ + __IO uint8_t SR1; /*!< status register 1 */ + __IO uint8_t EGR; /*!< event generation register */ + __IO uint8_t CNTR; /*!< counter register */ + __IO uint8_t PSCR; /*!< prescaler register */ + __IO uint8_t ARR; /*!< auto-reload register */ +} +TIM4_TypeDef; + +/** @addtogroup TIM4_Registers_Reset_Value + * @{ + */ + +#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00) +#define TIM4_IER_RESET_VALUE ((uint8_t)0x00) +#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00) +#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00) +#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00) +#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00) +#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF) + +/** + * @} + */ + +/** @addtogroup TIM4_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ +#define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ +#define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ +#define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ +/*EGR*/ +#define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ +/*CNTR*/ +#define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */ +/*ARR*/ +#define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with synchro module (TIM5) + */ + +typedef struct TIM5_struct +{ + __IO uint8_t CR1; /*! + #define enableInterrupts() _rim_() /* enable interrupts */ + #define disableInterrupts() _sim_() /* disable interrupts */ + #define rim() _rim_() /* enable interrupts */ + #define sim() _sim_() /* disable interrupts */ + #define nop() _nop_() /* No Operation */ + #define trap() _trap_() /* Trap (soft IT) */ + #define wfi() _wfi_() /* Wait For Interrupt */ + #define halt() _halt_() /* Halt */ +#elif defined(_COSMIC_) + #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ + #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ + #define rim() {_asm("rim\n");} /* enable interrupts */ + #define sim() {_asm("sim\n");} /* disable interrupts */ + #define nop() {_asm("nop\n");} /* No Operation */ + #define trap() {_asm("trap\n");} /* Trap (soft IT) */ + #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ + #define halt() {_asm("halt\n");} /* Halt */ +#else /*_IAR_*/ + #include + #define enableInterrupts() __enable_interrupt() /* enable interrupts */ + #define disableInterrupts() __disable_interrupt() /* disable interrupts */ + #define rim() __enable_interrupt() /* enable interrupts */ + #define sim() __disable_interrupt() /* disable interrupts */ + #define nop() __no_operation() /* No Operation */ + #define trap() __trap() /* Trap (soft IT) */ + #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ + #define halt() __halt() /* Halt */ +#endif /*_RAISONANCE_*/ + +/*============================== Interrupt vector Handling ========================*/ + +#ifdef _COSMIC_ + #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) + #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) +#endif /* _COSMIC_ */ + +#ifdef _RAISONANCE_ + #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b + #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap +#endif /* _RAISONANCE_ */ + +#ifdef _IAR_ + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define INTERRUPT_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define INTERRUPT_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) +#endif /* _IAR_ */ + +/*============================== Interrupt Handler declaration ========================*/ +#ifdef _COSMIC_ + #define INTERRUPT @far @interrupt +#elif defined(_IAR_) + #define INTERRUPT __interrupt +#endif /* _COSMIC_ */ + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reset if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((uint8_t)1<<(Place))) : \ + ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) + +#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE_OK(SensitivityValue) \ + (((SensitivityValue) == ENABLE) || \ + ((SensitivityValue) == DISABLE)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/os/hal/platforms/STM8S/stm8s_type.h b/os/hal/platforms/STM8S/stm8s_type.h new file mode 100644 index 000000000..5c80f6687 --- /dev/null +++ b/os/hal/platforms/STM8S/stm8s_type.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm8s_type.h + * @brief This file contains all common data types. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2009 STMicroelectronics

    + * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_TYPE_H +#define __STM8S_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum +{ + FALSE = 0, + TRUE = !FALSE +} +bool; + +typedef enum { + RESET = 0, + SET = !RESET +} +FlagStatus, ITStatus, BitStatus; + +typedef enum { + DISABLE = 0, + ENABLE = !DISABLE +} +FunctionalState; + +#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) ) + +typedef enum { + ERROR = 0, + SUCCESS = !ERROR +} +ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_TYPE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/os/hal/platforms/Win32/console.c b/os/hal/platforms/Win32/console.c new file mode 100644 index 000000000..dbbfbf661 --- /dev/null +++ b/os/hal/platforms/Win32/console.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file console.c + * @brief Simulator console driver code. + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "console.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Console driver 1. + */ +BaseChannel CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static size_t write(void *ip, const uint8_t *bp, size_t n) { + size_t ret; + + (void)ip; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t read(void *ip, uint8_t *bp, size_t n) { + + (void)ip; + return fread(bp, 1, n, stdin); +} + +static msg_t put(void *ip, uint8_t b) { + + (void)ip; + + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t get(void *ip) { + + (void)ip; + + return fgetc(stdin); +} + +static msg_t putt(void *ip, uint8_t b, systime_t time) { + + (void)ip; + (void)time; + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t gett(void *ip, systime_t time) { + + (void)ip; + (void)time; + return fgetc(stdin); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + size_t ret; + + (void)ip; + (void)time; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + (void)ip; + (void)time; + return fread(bp, 1, n, stdin); +} + +static const struct BaseChannelVMT vmt = { + write, read, put, get, + putt, gett, writet, readt +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void conInit(void) { + + CD1.vmt = &vmt; +} + +/** @} */ diff --git a/os/hal/platforms/Win32/console.h b/os/hal/platforms/Win32/console.h new file mode 100644 index 000000000..491b6f36b --- /dev/null +++ b/os/hal/platforms/Win32/console.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file console.h + * @brief Simulator console driver header. + * @{ + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern BaseChannel CD1; + +#ifdef __cplusplus +extern "C" { +#endif + void conInit(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Win32/hal_lld.c b/os/hal/platforms/Win32/hal_lld.c new file mode 100644 index 000000000..c86e84de7 --- /dev/null +++ b/os/hal/platforms/Win32/hal_lld.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/hal_lld.c + * @brief Win32 HAL subsystem low level driver code. + * @addtogroup WIN32_HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static LARGE_INTEGER nextcnt; +static LARGE_INTEGER slice; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + */ +void hal_lld_init(void) { + WSADATA wsaData; + + /* Initialization.*/ + if (WSAStartup(2, &wsaData) != 0) { + printf("Unable to locate a winsock DLL\n"); + exit(1); + } + + printf("ChibiOS/RT simulator (Win32)\n"); + if (!QueryPerformanceFrequency(&slice)) { + printf("QueryPerformanceFrequency() error"); + exit(1); + } + slice.QuadPart /= CH_FREQUENCY; + QueryPerformanceCounter(&nextcnt); + nextcnt.QuadPart += slice.QuadPart; + + fflush(stdout); +} + +/** + * @brief Interrupt simulation. + */ +void ChkIntSources(void) { + LARGE_INTEGER n; + +#if HAL_USE_SERIAL + if (sd_lld_interrupt_pending()) { + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + return; + } +#endif + + /* Interrupt Timer simulation (10ms interval).*/ + QueryPerformanceCounter(&n); + if (n.QuadPart > nextcnt.QuadPart) { + nextcnt.QuadPart += slice.QuadPart; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); + + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + } +} + +/** @} */ diff --git a/os/hal/platforms/Win32/hal_lld.h b/os/hal/platforms/Win32/hal_lld.h new file mode 100644 index 000000000..2f07c682d --- /dev/null +++ b/os/hal/platforms/Win32/hal_lld.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/hal_lld.h + * @brief WIN32 simulator HAL subsystem low level driver header. + * + * @addtogroup WIN32_HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include +#include + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "Win32" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Win32/pal_lld.c b/os/hal/platforms/Win32/pal_lld.c new file mode 100644 index 000000000..94f5380b3 --- /dev/null +++ b/os/hal/platforms/Win32/pal_lld.c @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/pal_lld.c + * @brief Win32 low level simulated PAL driver code. + * + * @addtogroup WIN32_PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief VIO1 simulated port. + */ +sim_vio_port_t vio_port_1; + +/** + * @brief VIO2 simulated port. + */ +sim_vio_port_t vio_port_2; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high + * state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->latch |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/Win32/pal_lld.h b/os/hal/platforms/Win32/pal_lld.h new file mode 100644 index 000000000..59273a109 --- /dev/null +++ b/os/hal/platforms/Win32/pal_lld.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/pal_lld.h + * @brief Win32 low level simulated PAL driver header. + * + * @addtogroup WIN32_PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN +#undef PAL_MODE_INPUT_ANALOG + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief VIO port structure. + */ +typedef struct { + /** + * @brief VIO_LATCH register. + * @details This register represents the output latch of the VIO port. + */ + uint32_t latch; + /** + * @brief VIO_PIN register. + * @details This register represents the logical level at the VIO port + * pin level. + */ + uint32_t pin; + /** + * @brief VIO_DIR register. + * @details Direction of the VIO port bits, 0=input, 1=output. + */ + uint32_t dir; +} sim_vio_port_t; + +/** + * @brief Virtual I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** + * @brief Virtual port 1 setup data. + */ + sim_vio_port_t VP1Data; + /** + * @brief Virtual port 2 setup data. + */ + sim_vio_port_t VP2Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef sim_vio_port_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief VIO port 1 identifier. + */ +#define IOPORT1 (&vio_port_1) + +/** + * @brief VIO port 2 identifier. + */ +#define IOPORT2 (&vio_port_2) + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) \ + (vio_port_1 = (config)->VP1Data, \ + vio_port_2 = (config)->VP2Data) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->pin) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->latch) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +#if !defined(__DOXYGEN__) +extern sim_vio_port_t vio_port_1; +extern sim_vio_port_t vio_port_2; +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Win32/platform.mk b/os/hal/platforms/Win32/platform.mk new file mode 100644 index 000000000..0887c1ae3 --- /dev/null +++ b/os/hal/platforms/Win32/platform.mk @@ -0,0 +1,7 @@ +# List of all the Win32 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Win32/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Win32/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Win32/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Win32 diff --git a/os/hal/platforms/Win32/serial_lld.c b/os/hal/platforms/Win32/serial_lld.c new file mode 100644 index 000000000..bfa5b80f8 --- /dev/null +++ b/os/hal/platforms/Win32/serial_lld.c @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/serial_lld.c + * @brief Win32 low level simulated serial driver code. + * @addtogroup WIN32_SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief Serial driver 1 identifier.*/ +#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif +/** @brief Serial driver 2 identifier.*/ +#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { +}; + +static u_long nb = 1; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void init(SerialDriver *sdp, uint16_t port) { + struct sockaddr_in sad; + struct protoent *prtp; + + if ((prtp = getprotobyname("tcp")) == NULL) { + printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); + goto abort; + } + + sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); + if (sdp->com_listen == INVALID_SOCKET) { + printf("%s: Error creating simulator socket\n", sdp->com_name); + goto abort; + } + + if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); + goto abort; + } + + memset(&sad, 0, sizeof(sad)); + sad.sin_family = AF_INET; + sad.sin_addr.s_addr = INADDR_ANY; + sad.sin_port = htons(port); + if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { + printf("%s: Error binding socket\n", sdp->com_name); + goto abort; + } + + if (listen(sdp->com_listen, 1) != 0) { + printf("%s: Error listening socket\n", sdp->com_name); + goto abort; + } + printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); + return; + +abort: + if (sdp->com_listen != INVALID_SOCKET) + closesocket(sdp->com_listen); + WSACleanup(); + exit(1); +} + +static bool_t connint(SerialDriver *sdp) { + + if (sdp->com_data == INVALID_SOCKET) { + struct sockaddr addr; + int addrlen = sizeof(addr); + + if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) + return FALSE; + + if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); + goto abort; + } + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_CONNECTED); + chSysUnlockFromIsr(); + return TRUE; + } + return FALSE; +abort: + if (sdp->com_listen != INVALID_SOCKET) + closesocket(sdp->com_listen); + if (sdp->com_data != INVALID_SOCKET) + closesocket(sdp->com_data); + WSACleanup(); + exit(1); +} + +static bool_t inint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int i; + uint8_t data[32]; + + /* + * Input. + */ + int n = recv(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case SOCKET_ERROR: + if (WSAGetLastError() == WSAEWOULDBLOCK) + return FALSE; + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + for (i = 0; i < n; i++) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, data[i]); + chSysUnlockFromIsr(); + } + return TRUE; + } + return FALSE; +} + +static bool_t outint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int n; + uint8_t data[1]; + + /* + * Input. + */ + chSysLockFromIsr(); + n = sdRequestDataI(sdp); + chSysUnlockFromIsr(); + if (n < 0) + return FALSE; + data[0] = (uint8_t)n; + n = send(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case SOCKET_ERROR: + if (WSAGetLastError() == WSAEWOULDBLOCK) + return FALSE; + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + return TRUE; + } + return FALSE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * Low level serial driver initialization. + */ +void sd_lld_init(void) { + +#if USE_WIN32_SERIAL1 + sdObjectInit(&SD1, NULL, NULL); + SD1.com_listen = INVALID_SOCKET; + SD1.com_data = INVALID_SOCKET; + SD1.com_name = "SD1"; +#endif + +#if USE_WIN32_SERIAL1 + sdObjectInit(&SD2, NULL, NULL); + SD2.com_listen = INVALID_SOCKET; + SD2.com_data = INVALID_SOCKET; + SD2.com_name = "SD2"; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_WIN32_SERIAL1 + if (sdp == &SD1) + init(&SD1, SD1_PORT); +#endif + +#if USE_WIN32_SERIAL1 + if (sdp == &SD2) + init(&SD2, SD2_PORT); +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) { + + (void)sdp; +} + +bool_t sd_lld_interrupt_pending(void) { + bool_t b; + + CH_IRQ_PROLOGUE(); + + b = connint(&SD1) || connint(&SD2) || + inint(&SD1) || inint(&SD2) || + outint(&SD1) || outint(&SD2); + + CH_IRQ_EPILOGUE(); + + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/Win32/serial_lld.h b/os/hal/platforms/Win32/serial_lld.h new file mode 100644 index 000000000..9618ae5b9 --- /dev/null +++ b/os/hal/platforms/Win32/serial_lld.h @@ -0,0 +1,143 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Win32/serial_lld.h + * @brief Win32 low level simulated serial driver header. + * + * @addtogroup WIN32_SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 1024 +#endif + +/** + * @brief SD1 driver enable switch. + * @details If set to @p TRUE the support for SD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__) +#define USE_WIN32_SERIAL1 TRUE +#endif + +/** + * @brief SD2 driver enable switch. + * @details If set to @p TRUE the support for SD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__) +#define USE_WIN32_SERIAL2 TRUE +#endif + +/** + * @brief Listen port for SD1. + */ +#if !defined(SD1_PORT) || defined(__DOXYGEN__) +#define SD1_PORT 29001 +#endif + +/** + * @brief Listen port for SD2. + */ +#if !defined(SD2_PORT) || defined(__DOXYGEN__) +#define SD2_PORT 29002 +#endif + +/*===========================================================================*/ +/* Unsupported event flags and custom events. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Listen socket for simulated serial port.*/ \ + SOCKET com_listen; \ + /* Data socket for simulated serial port.*/ \ + SOCKET com_data; \ + /* Port readable name.*/ \ + const char *com_name; + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + bool_t sd_lld_interrupt_pending(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/platforms.dox b/os/hal/platforms/platforms.dox new file mode 100644 index 000000000..3ff14f700 --- /dev/null +++ b/os/hal/platforms/platforms.dox @@ -0,0 +1,24 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup platforms Platforms + * @brief Supported platforms. + * @details The implementation of the device drivers can be slightly different + * on the various platforms because architectural constrains. This section + * describes the implementation of the various device drivers on the various + * supported platforms. + */ diff --git a/os/hal/src/adc.c b/os/hal/src/adc.c new file mode 100644 index 000000000..d0e814ae2 --- /dev/null +++ b/os/hal/src/adc.c @@ -0,0 +1,343 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file adc.c + * @brief ADC Driver code. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief ADC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void adcInit(void) { + + adc_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p ADCDriver structure. + * + * @param[out] adcp pointer to the @p ADCDriver object + * + * @init + */ +void adcObjectInit(ADCDriver *adcp) { + + adcp->state = ADC_STOP; + adcp->config = NULL; + adcp->samples = NULL; + adcp->depth = 0; + adcp->grpp = NULL; +#if ADC_USE_WAIT + adcp->thread = NULL; +#endif /* ADC_USE_WAIT */ +#if ADC_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&adcp->mutex); +#else + chSemInit(&adcp->semaphore, 1); +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_INIT_HOOK) + ADC_DRIVER_EXT_INIT_HOOK(adcp); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] config pointer to the @p ADCConfig object. Depending on + * the implementation the value can be @p NULL. + * + * @api + */ +void adcStart(ADCDriver *adcp, const ADCConfig *config) { + + chDbgCheck(adcp != NULL, "adcStart"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), + "adcStart(), #1", "invalid state"); + adcp->config = config; + adc_lld_start(adcp); + adcp->state = ADC_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcStop(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcStop"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), + "adcStop(), #1", "invalid state"); + adc_lld_stop(adcp); + adcp->state = ADC_STOP; + chSysUnlock(); +} + +/** + * @brief Starts an ADC conversion. + * @details Starts an asynchronous conversion operation. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * + * @api + */ +void adcStartConversion(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + + chSysLock(); + adcStartConversionI(adcp, grpp, samples, depth); + chSysUnlock(); +} + +/** + * @brief Starts an ADC conversion. + * @details Starts an asynchronous conversion operation. + * @post The callbacks associated to the conversion group will be invoked + * on buffer fill and error events. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * + * @iclass + */ +void adcStartConversionI(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + + chDbgCheckClassI(); + chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) && + ((depth == 1) || ((depth & 1) == 0)), + "adcStartConversionI"); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), + "adcStartConversionI(), #1", "not ready"); + + adcp->samples = samples; + adcp->depth = depth; + adcp->grpp = grpp; + adcp->state = ADC_ACTIVE; + adc_lld_start_conversion(adcp); +} + +/** + * @brief Stops an ongoing conversion. + * @details This function stops the currently ongoing conversion and returns + * the driver in the @p ADC_READY state. If there was no conversion + * being processed then the function does nothing. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcStopConversion(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcStopConversion"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_ACTIVE), + "adcStopConversion(), #1", "invalid state"); + if (adcp->state != ADC_READY) { + adc_lld_stop_conversion(adcp); + adcp->grpp = NULL; + adcp->state = ADC_READY; + _adc_reset_s(adcp); + } + chSysUnlock(); +} + +/** + * @brief Stops an ongoing conversion. + * @details This function stops the currently ongoing conversion and returns + * the driver in the @p ADC_READY state. If there was no conversion + * being processed then the function does nothing. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @iclass + */ +void adcStopConversionI(ADCDriver *adcp) { + + chDbgCheckClassI(); + chDbgCheck(adcp != NULL, "adcStopConversionI"); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_ACTIVE) || + (adcp->state == ADC_COMPLETE), + "adcStopConversionI(), #1", "invalid state"); + + if (adcp->state != ADC_READY) { + adc_lld_stop_conversion(adcp); + adcp->grpp = NULL; + adcp->state = ADC_READY; + _adc_reset_i(adcp); + } +} + +#if ADC_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Performs an ADC conversion. + * @details Performs a synchronous conversion operation. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * @return The operation result. + * @retval RDY_OK Conversion finished. + * @retval RDY_RESET The conversion has been stopped using + * @p acdStopConversion() or @p acdStopConversionI(), + * the result buffer may contain incorrect data. + * @retval RDY_TIMEOUT The conversion has been stopped because an hardware + * error. + * + * @api + */ +msg_t adcConvert(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + msg_t msg; + + chSysLock(); + chDbgAssert(adcp->thread == NULL, "adcConvert(), #1", "already waiting"); + adcStartConversionI(adcp, grpp, samples, depth); + adcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + msg = chThdSelf()->p_u.rdymsg; + chSysUnlock(); + return msg; +} +#endif /* ADC_USE_WAIT */ + +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the ADC peripheral. + * @details This function tries to gain ownership to the ADC bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option + * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcAcquireBus(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&adcp->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&adcp->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the ADC peripheral. + * @pre In order to use this function the option + * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcReleaseBus(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcReleaseBus"); + +#if CH_USE_MUTEXES + (void)adcp; + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&adcp->semaphore); +#endif +} +#endif /* ADC_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/src/can.c b/os/hal/src/can.c new file mode 100644 index 000000000..a57f12356 --- /dev/null +++ b/os/hal/src/can.c @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file can.c + * @brief CAN Driver code. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief CAN Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void canInit(void) { + + can_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p CANDriver structure. + * + * @param[out] canp pointer to the @p CANDriver object + * + * @init + */ +void canObjectInit(CANDriver *canp) { + + canp->state = CAN_STOP; + canp->config = NULL; + chSemInit(&canp->txsem, 0); + chSemInit(&canp->rxsem, 0); + chEvtInit(&canp->rxfull_event); + chEvtInit(&canp->txempty_event); + chEvtInit(&canp->error_event); +#if CAN_USE_SLEEP_MODE + chEvtInit(&canp->sleep_event); + chEvtInit(&canp->wakeup_event); +#endif /* CAN_USE_SLEEP_MODE */ +} + +/** + * @brief Configures and activates the CAN peripheral. + * @note Activating the CAN bus can be a slow operation this this function + * is not atomic, it waits internally for the initialization to + * complete. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] config pointer to the @p CANConfig object. Depending on + * the implementation the value can be @p NULL. + * + * @api + */ +void canStart(CANDriver *canp, const CANConfig *config) { + + chDbgCheck(canp != NULL, "canStart"); + + chSysLock(); + chDbgAssert((canp->state == CAN_STOP) || + (canp->state == CAN_STARTING) || + (canp->state == CAN_READY), + "canStart(), #1", "invalid state"); + while (canp->state == CAN_STARTING) + chThdSleepS(1); + if (canp->state == CAN_STOP) { + canp->config = config; + can_lld_start(canp); + canp->state = CAN_READY; + } + chSysUnlock(); +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @api + */ +void canStop(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canStop"); + + chSysLock(); + chDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY), + "canStop(), #1", "invalid state"); + can_lld_stop(canp); + chSemResetI(&canp->rxsem, 0); + chSemResetI(&canp->txsem, 0); + chSchRescheduleS(); + canp->state = CAN_STOP; + chSysUnlock(); +} + +/** + * @brief Can frame transmission. + * @details The specified frame is queued for transmission, if the hardware + * queue is full then the invoking thread is queued. + * @note Trying to transmit while in sleep mode simply enqueues the thread. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation result. + * @retval RDY_OK the frame has been queued for transmission. + * @retval RDY_TIMEOUT The operation has timed out. + * @retval RDY_RESET The driver has been stopped while waiting. + * + * @api + */ +msg_t canTransmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp, + systime_t timeout) { + + chDbgCheck((canp != NULL) && (ctfp != NULL) && (mailbox <= CAN_TX_MAILBOXES), + "canTransmit"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canTransmit(), #1", "invalid state"); + while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) { + msg_t msg = chSemWaitTimeoutS(&canp->txsem, timeout); + if (msg != RDY_OK) { + chSysUnlock(); + return msg; + } + } + can_lld_transmit(canp, mailbox, ctfp); + chSysUnlock(); + return RDY_OK; +} + +/** + * @brief Can frame receive. + * @details The function waits until a frame is received. + * @note Trying to receive while in sleep mode simply enqueues the thread. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout (useful in an + * event driven scenario where a thread never blocks + * for I/O). + * - @a TIME_INFINITE no timeout. + * . + * @return The operation result. + * @retval RDY_OK a frame has been received and placed in the buffer. + * @retval RDY_TIMEOUT The operation has timed out. + * @retval RDY_RESET The driver has been stopped while waiting. + * + * @api + */ +msg_t canReceive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp, + systime_t timeout) { + + chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox < CAN_RX_MAILBOXES), + "canReceive"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canReceive(), #1", "invalid state"); + while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) { + msg_t msg = chSemWaitTimeoutS(&canp->rxsem, timeout); + if (msg != RDY_OK) { + chSysUnlock(); + return msg; + } + } + can_lld_receive(canp, mailbox, crfp); + chSysUnlock(); + return RDY_OK; +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * @details This function puts the CAN driver in sleep mode and broadcasts + * the @p sleep_event event source. + * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must + * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported + * by the low level driver. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @api + */ +void canSleep(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canSleep"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canSleep(), #1", "invalid state"); + if (canp->state == CAN_READY) { + can_lld_sleep(canp); + canp->state = CAN_SLEEP; + chEvtBroadcastI(&canp->sleep_event); + chSchRescheduleS(); + } + chSysUnlock(); +} + +/** + * @brief Enforces leaving the sleep mode. + * @note The sleep mode is supposed to be usually exited automatically by + * an hardware event. + * + * @param[in] canp pointer to the @p CANDriver object + */ +void canWakeup(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canWakeup"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canWakeup(), #1", "invalid state"); + if (canp->state == CAN_SLEEP) { + can_lld_wakeup(canp); + canp->state = CAN_READY; + chEvtBroadcastI(&canp->wakeup_event); + chSchRescheduleS(); + } + chSysUnlock(); +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/os/hal/src/ext.c b/os/hal/src/ext.c new file mode 100644 index 000000000..a0dc9f38e --- /dev/null +++ b/os/hal/src/ext.c @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ext.c + * @brief EXT Driver code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EXT Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void extInit(void) { + + ext_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p EXTDriver structure. + * + * @param[out] extp pointer to the @p EXTDriver object + * + * @init + */ +void extObjectInit(EXTDriver *extp) { + + extp->state = EXT_STOP; + extp->config = NULL; +} + +/** + * @brief Configures and activates the EXT peripheral. + * @post After activation all EXT channels are in the disabled state, + * use @p extChannelEnable() in order to activate them. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] config pointer to the @p EXTConfig object + * + * @api + */ +void extStart(EXTDriver *extp, const EXTConfig *config) { + + chDbgCheck((extp != NULL) && (config != NULL), "extStart"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStart(), #1", "invalid state"); + extp->config = config; + ext_lld_start(extp); + extp->state = EXT_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @api + */ +void extStop(EXTDriver *extp) { + + chDbgCheck(extp != NULL, "extStop"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStop(), #1", "invalid state"); + ext_lld_stop(extp); + extp->state = EXT_STOP; + chSysUnlock(); +} + +/** + * @brief Enables an EXT channel. + * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @api + */ +void extChannelEnable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS), + "extChannelEnable"); + + chSysLock(); + chDbgAssert((extp->state == EXT_ACTIVE) && + ((extp->config->channels[channel].mode & + EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), + "extChannelEnable(), #1", "invalid state"); + extChannelEnableI(extp, channel); + chSysUnlock(); +} + +/** + * @brief Disables an EXT channel. + * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @api + */ +void extChannelDisable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS), + "extChannelDisable"); + + chSysLock(); + chDbgAssert((extp->state == EXT_ACTIVE) && + ((extp->config->channels[channel].mode & + EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), + "extChannelDisable(), #1", "invalid state"); + extChannelDisableI(extp, channel); + chSysUnlock(); +} + +/** + * @brief Changes the operation mode of a channel. + * @note This function attempts to write over the current configuration + * structure that must have been not declared constant. This + * violates the @p const qualifier in @p extStart() but it is + * intentional. + * @note This function cannot be used if the configuration structure is + * declared @p const. + * @note The effect of this function on constant configuration structures + * is not defined. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be changed + * @param[in] extcp new configuration for the channel + * + * @iclass + */ +void extSetChannelModeI(EXTDriver *extp, + expchannel_t channel, + const EXTChannelConfig *extcp) { + EXTChannelConfig *oldcp; + + chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS) && + (extcp != NULL), "extSetChannelModeI"); + + chDbgAssert(extp->state == EXT_ACTIVE, + "extSetChannelModeI(), #1", "invalid state"); + + /* Note that here the access is enforced as non-const, known access + violation.*/ + oldcp = (EXTChannelConfig *)&extp->config->channels[channel]; + + /* Overwiting the old channels configuration then the channel is reconfigured + by the low level driver.*/ + *oldcp = *extcp; + ext_lld_channel_enable(extp, channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/src/gpt.c b/os/hal/src/gpt.c new file mode 100644 index 000000000..e37e1a5d8 --- /dev/null +++ b/os/hal/src/gpt.c @@ -0,0 +1,268 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file gpt.c + * @brief GPT Driver code. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief GPT Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void gptInit(void) { + + gpt_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p GPTDriver structure. + * + * @param[out] gptp pointer to the @p GPTDriver object + * + * @init + */ +void gptObjectInit(GPTDriver *gptp) { + + gptp->state = GPT_STOP; + gptp->config = NULL; +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] config pointer to the @p GPTConfig object + * + * @api + */ +void gptStart(GPTDriver *gptp, const GPTConfig *config) { + + chDbgCheck((gptp != NULL) && (config != NULL), "ptStart"); + + chSysLock(); + chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), + "gptStart(), #1", "invalid state"); + gptp->config = config; + gpt_lld_start(gptp); + gptp->state = GPT_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStop(GPTDriver *gptp) { + + chDbgCheck(gptp != NULL, "gptStop"); + + chSysLock(); + chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), + "gptStop(), #1", "invalid state"); + gpt_lld_stop(gptp); + gptp->state = GPT_STOP; + chSysUnlock(); +} + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * + * @api + */ +void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) { + + chDbgCheck(gptp != NULL, "gptChangeInterval"); + + chSysLock(); + chDbgAssert(gptp->state == GPT_CONTINUOUS, + "gptChangeInterval(), #1", "invalid state"); + gptChangeIntervalI(gptp, interval); + chSysUnlock(); +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @api + */ +void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) { + + chSysLock(); + gptStartContinuousI(gptp, interval); + chSysUnlock(); +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @iclass + */ +void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStartContinuousI"); + chDbgAssert(gptp->state == GPT_READY, + "gptStartContinuousI(), #1", "invalid state"); + + gptp->state = GPT_CONTINUOUS; + gpt_lld_start_timer(gptp, interval); +} + +/** + * @brief Starts the timer in one shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) { + + chSysLock(); + gptStartOneShotI(gptp, interval); + chSysUnlock(); +} + +/** + * @brief Starts the timer in one shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStartOneShotI"); + chDbgAssert(gptp->state == GPT_READY, + "gptStartOneShotI(), #1", "invalid state"); + + gptp->state = GPT_ONESHOT; + gpt_lld_start_timer(gptp, interval); +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStopTimer(GPTDriver *gptp) { + + chSysLock(); + gptStopTimerI(gptp); + chSysUnlock(); +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStopTimerI(GPTDriver *gptp) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStopTimerI"); + chDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) || + (gptp->state == GPT_ONESHOT), + "gptStopTimerI(), #1", "invalid state"); + + gptp->state = GPT_READY; + gpt_lld_stop_timer(gptp); +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * @note The configured callback is not invoked when using this function. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) { + + chDbgAssert(gptp->state == GPT_READY, + "gptPolledDelay(), #1", "invalid state"); + + gptp->state = GPT_ONESHOT; + gpt_lld_polled_delay(gptp, interval); + gptp->state = GPT_READY; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/src/hal.c b/os/hal/src/hal.c new file mode 100644 index 000000000..974a8854b --- /dev/null +++ b/os/hal/src/hal.c @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file hal.c + * @brief HAL subsystem code. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief HAL initialization. + * @details This function invokes the low level initialization code then + * initializes all the drivers enabled in the HAL. Finally the + * board-specific initialization is performed by invoking + * @p boardInit() (usually defined in @p board.c). + * + * @init + */ +void halInit(void) { + + hal_lld_init(); + +#if HAL_USE_TM || defined(__DOXYGEN__) + tmInit(); +#endif +#if HAL_USE_PAL || defined(__DOXYGEN__) + palInit(&pal_default_config); +#endif +#if HAL_USE_ADC || defined(__DOXYGEN__) + adcInit(); +#endif +#if HAL_USE_CAN || defined(__DOXYGEN__) + canInit(); +#endif +#if HAL_USE_EXT || defined(__DOXYGEN__) + extInit(); +#endif +#if HAL_USE_GPT || defined(__DOXYGEN__) + gptInit(); +#endif +#if HAL_USE_I2C || defined(__DOXYGEN__) + i2cInit(); +#endif +#if HAL_USE_ICU || defined(__DOXYGEN__) + icuInit(); +#endif +#if HAL_USE_MAC || defined(__DOXYGEN__) + macInit(); +#endif +#if HAL_USE_PWM || defined(__DOXYGEN__) + pwmInit(); +#endif +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + sdInit(); +#endif +#if HAL_USE_SDC || defined(__DOXYGEN__) + sdcInit(); +#endif +#if HAL_USE_SPI || defined(__DOXYGEN__) + spiInit(); +#endif +#if HAL_USE_UART || defined(__DOXYGEN__) + uartInit(); +#endif +#if HAL_USE_USB || defined(__DOXYGEN__) + usbInit(); +#endif +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + mmcInit(); +#endif +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + sduInit(); +#endif +#if HAL_USE_RTC || defined(__DOXYGEN__) + rtcInit(); +#endif + /* Board specific initialization.*/ + boardInit(); +} + +#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) +/** + * @brief Realtime window test. + * @details This function verifies if the current realtime counter value + * lies within the specified range or not. The test takes care + * of the realtime counter wrapping to zero on overflow. + * @note When start==end then the function returns always true because the + * whole time range is specified. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @par Example 1 + * Example of a guarded loop using the realtime counter. The loop implements + * a timeout after one second. + * @code + * halrtcnt_t start = halGetCounterValue(); + * halrtcnt_t timeout = start + S2RTT(1); + * while (my_condition) { + * if (!halIsCounterWithin(start, timeout) + * return TIMEOUT; + * // Do something. + * } + * // Continue. + * @endcode + * + * @par Example 2 + * Example of a loop that lasts exactly 50 microseconds. + * @code + * halrtcnt_t start = halGetCounterValue(); + * halrtcnt_t timeout = start + US2RTT(50); + * while (halIsCounterWithin(start, timeout)) { + * // Do something. + * } + * // Continue. + * @endcode + * + * @param[in] start the start of the time window (inclusive) + * @param[in] end the end of the time window (non inclusive) + * @retval TRUE current time within the specified time window. + * @retval FALSE current time not within the specified time window. + * + * @special + */ +bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end) { + halrtcnt_t now = halGetCounterValue(); + + return end > start ? (now >= start) && (now < end) : + (now >= start) || (now < end); +} + +/** + * @brief Polled delay. + * @note The real delays is always few cycles in excess of the specified + * value. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @param[in] ticks number of ticks + * + * @special + */ +void halPolledDelay(halrtcnt_t ticks) { + halrtcnt_t start = halGetCounterValue(); + halrtcnt_t timeout = start + (ticks); + while (halIsCounterWithin(start, timeout)) + ; +} +#endif /* HAL_IMPLEMENTS_COUNTERS */ + +/** @} */ diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c new file mode 100644 index 000000000..78519cc35 --- /dev/null +++ b/os/hal/src/i2c.c @@ -0,0 +1,303 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file i2c.c + * @brief I2C Driver code. + * + * @addtogroup I2C + * @{ + */ +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief I2C Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void i2cInit(void) { + i2c_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p I2CDriver structure. + * + * @param[out] i2cp pointer to the @p I2CDriver object + * + * @init + */ +void i2cObjectInit(I2CDriver *i2cp) { + + i2cp->state = I2C_STOP; + i2cp->config = NULL; + +#if I2C_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&i2cp->mutex); +#else + chSemInit(&i2cp->semaphore, 1); +#endif /* CH_USE_MUTEXES */ +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#if defined(I2C_DRIVER_EXT_INIT_HOOK) + I2C_DRIVER_EXT_INIT_HOOK(i2cp); +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] config pointer to the @p I2CConfig object + * + * @api + */ +void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { + + chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart"); + chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || + (i2cp->state == I2C_LOCKED), + "i2cStart(), #1", + "invalid state"); + + chSysLock(); + i2cp->config = config; + i2c_lld_start(i2cp); + i2cp->state = I2C_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cStop(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cStop"); + chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || + (i2cp->state == I2C_LOCKED), + "i2cStop(), #1", + "invalid state"); + + chSysLock(); + i2c_lld_stop(i2cp); + i2cp->state = I2C_STOP; + chSysUnlock(); +} + +/** + * @brief Returns the errors mask associated to the previous operation. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @return The errors mask. + * + * @api + */ +i2cflags_t i2cGetErrors(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cGetErrors"); + + return i2c_lld_get_errors(i2cp); +} + +/** + * @brief Sends data via the I2C bus. + * @details Function designed to realize "read-through-write" transfer + * paradigm. If you want transmit data without any further read, + * than set @b rxbytes field to 0. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address (7 bits) without R/W bit + * @param[in] txbuf pointer to transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to receive buffer + * @param[in] rxbytes number of bytes to be received, set it to 0 if + * you want transmit only + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. + * + * @api + */ +msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, + i2caddr_t addr, + const uint8_t *txbuf, + size_t txbytes, + uint8_t *rxbuf, + size_t rxbytes, + systime_t timeout) { + msg_t rdymsg; + + chDbgCheck((i2cp != NULL) && (addr != 0) && + (txbytes > 0) && (txbuf != NULL) && + ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) && + (timeout != TIME_IMMEDIATE), + "i2cMasterTransmitTimeout"); + + chDbgAssert(i2cp->state == I2C_READY, + "i2cMasterTransmitTimeout(), #1", "not ready"); + + chSysLock(); + i2cp->errors = I2CD_NO_ERROR; + i2cp->state = I2C_ACTIVE_TX; + rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes, + rxbuf, rxbytes, timeout); + if (rdymsg == RDY_TIMEOUT) + i2cp->state = I2C_LOCKED; + else + i2cp->state = I2C_READY; + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address (7 bits) without R/W bit + * @param[out] rxbuf pointer to receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. + * + * @api + */ +msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, + i2caddr_t addr, + uint8_t *rxbuf, + size_t rxbytes, + systime_t timeout){ + + msg_t rdymsg; + + chDbgCheck((i2cp != NULL) && (addr != 0) && + (rxbytes > 0) && (rxbuf != NULL) && + (timeout != TIME_IMMEDIATE), + "i2cMasterReceiveTimeout"); + + chDbgAssert(i2cp->state == I2C_READY, + "i2cMasterReceive(), #1", "not ready"); + + chSysLock(); + i2cp->errors = I2CD_NO_ERROR; + i2cp->state = I2C_ACTIVE_RX; + rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout); + if (rdymsg == RDY_TIMEOUT) + i2cp->state = I2C_LOCKED; + else + i2cp->state = I2C_READY; + chSysUnlock(); + return rdymsg; +} + +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the I2C bus. + * @details This function tries to gain ownership to the SPI bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cAcquireBus(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&i2cp->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&i2cp->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the I2C bus. + * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cReleaseBus(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cReleaseBus"); + +#if CH_USE_MUTEXES + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&i2cp->semaphore); +#endif +} +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/src/i2s.c b/os/hal/src/i2s.c new file mode 100644 index 000000000..e43d51ab2 --- /dev/null +++ b/os/hal/src/i2s.c @@ -0,0 +1,179 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file i2s.c + * @brief I2S Driver code. + * + * @addtogroup I2S + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2S || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief I2S Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void i2sInit(void) { + + i2s_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p I2SDriver structure. + * + * @param[out] i2sp pointer to the @p I2SDriver object + * + * @init + */ +void i2sObjectInit(I2SDriver *i2sp) { + + i2sp->state = I2S_STOP; + i2sp->config = NULL; +} + +/** + * @brief Configures and activates the I2S peripheral. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * @param[in] config pointer to the @p I2SConfig object + * + * @api + */ +void i2sStart(I2SDriver *i2sp, const I2SConfig *config) { + + chDbgCheck((i2sp != NULL) && (config != NULL), "i2sStart"); + + chSysLock(); + chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY), + "i2sStart(), #1", "invalid state"); + i2sp->config = config; + i2s_lld_start(i2sp); + i2sp->state = I2S_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the I2S peripheral. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @api + */ +void i2sStop(I2SDriver *i2sp) { + + chDbgCheck(i2sp != NULL, "i2sStop"); + + chSysLock(); + chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY), + "i2sStop(), #1", "invalid state"); + i2s_lld_stop(i2sp); + i2sp->state = I2S_STOP; + chSysUnlock(); +} + +/** + * @brief Starts a I2S data exchange. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @api + */ +void i2sStartExchange(I2SDriver *i2sp) { + + chDbgCheck(i2sp != NULL "i2sStartExchange"); + + chSysLock(); + chDbgAssert(i2sp->state == I2S_READY, + "i2sStartExchange(), #1", "not ready"); + i2sStartExchangeI(i2sp); + chSysUnlock(); +} + +/** + * @brief Starts a I2S data exchange in continuous mode. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @api + */ +void i2sStartExchangeContinuous(I2SDriver *i2sp) { + + chDbgCheck(i2sp != NULL "i2sStartExchangeContinuous"); + + chSysLock(); + chDbgAssert(i2sp->state == I2S_READY, + "i2sStartExchangeContinuous(), #1", "not ready"); + i2sStartExchangeContinuousI(i2sp); + chSysUnlock(); +} + +/** + * @brief Stops the ongoing data exchange. + * @details The ongoing data exchange, if any, is stopped, if the driver + * was not active the function does nothing. + * + * @param[in] i2sp pointer to the @p I2SDriver object + * + * @api + */ +void i2sStopExchange(I2SDriver *i2sp) { + + chDbgCheck((i2sp != NULL), "i2sStopExchange"); + + chSysLock(); + chDbgAssert((i2sp->state == I2S_READY) || + (i2sp->state == I2S_ACTIVE) || + (i2sp->state == I2S_COMPLETE), + "i2sStopExchange(), #1", "not ready"); + i2sStopExchangeI(i2sp); + chSysUnlock(); +} + +#endif /* HAL_USE_I2S */ + +/** @} */ diff --git a/os/hal/src/icu.c b/os/hal/src/icu.c new file mode 100644 index 000000000..65d5de907 --- /dev/null +++ b/os/hal/src/icu.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file icu.c + * @brief ICU Driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief ICU Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void icuInit(void) { + + icu_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p ICUDriver structure. + * + * @param[out] icup pointer to the @p ICUDriver object + * + * @init + */ +void icuObjectInit(ICUDriver *icup) { + + icup->state = ICU_STOP; + icup->config = NULL; +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * @param[in] config pointer to the @p ICUConfig object + * + * @api + */ +void icuStart(ICUDriver *icup, const ICUConfig *config) { + + chDbgCheck((icup != NULL) && (config != NULL), "icuStart"); + + chSysLock(); + chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), + "icuStart(), #1", "invalid state"); + icup->config = config; + icu_lld_start(icup); + icup->state = ICU_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuStop(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuStop"); + + chSysLock(); + chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), + "icuStop(), #1", "invalid state"); + icu_lld_stop(icup); + icup->state = ICU_STOP; + chSysUnlock(); +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuEnable(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuEnable"); + + chSysLock(); + chDbgAssert(icup->state == ICU_READY, "icuEnable(), #1", "invalid state"); + icu_lld_enable(icup); + icup->state = ICU_WAITING; + chSysUnlock(); +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuDisable(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuDisable"); + + chSysLock(); + chDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) || + (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE), + "icuDisable(), #1", "invalid state"); + icu_lld_disable(icup); + icup->state = ICU_READY; + chSysUnlock(); +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/src/mac.c b/os/hal/src/mac.c new file mode 100644 index 000000000..cb62db612 --- /dev/null +++ b/os/hal/src/mac.c @@ -0,0 +1,272 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file mac.c + * @brief MAC Driver code. + * + * @addtogroup MAC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if MAC_USE_ZERO_COPY && !MAC_SUPPORTS_ZERO_COPY +#error "MAC_USE_ZERO_COPY not supported by this implementation" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MAC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void macInit(void) { + + mac_lld_init(); +} + +/** + * @brief Initialize the standard part of a @p MACDriver structure. + * + * @param[out] macp pointer to the @p MACDriver object + * + * @init + */ +void macObjectInit(MACDriver *macp) { + + macp->state = MAC_STOP; + macp->config = NULL; + chSemInit(&macp->tdsem, 0); + chSemInit(&macp->rdsem, 0); +#if MAC_USE_EVENTS + chEvtInit(&macp->rdevent); +#endif +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] config pointer to the @p MACConfig object + * + * @api + */ +void macStart(MACDriver *macp, const MACConfig *config) { + + chDbgCheck((macp != NULL) && (config != NULL), "macStart"); + + chSysLock(); + chDbgAssert(macp->state == MAC_STOP, + "macStart(), #1", "invalid state"); + macp->config = config; + mac_lld_start(macp); + macp->state = MAC_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @api + */ +void macStop(MACDriver *macp) { + + chDbgCheck(macp != NULL, "macStop"); + + chSysLock(); + chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE), + "macStop(), #1", "invalid state"); + mac_lld_stop(macp); + macp->state = MAC_STOP; + chSysUnlock(); +} + +/** + * @brief Allocates a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. If a descriptor is not currently available then the + * invoking thread is queued until one is freed. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK the descriptor was obtained. + * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. + * + * @api + */ +msg_t macWaitTransmitDescriptor(MACDriver *macp, + MACTransmitDescriptor *tdp, + systime_t time) { + msg_t msg; + systime_t now; + + chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1", + "not active"); + + while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) && + (time > 0)) { + chSysLock(); + now = chTimeNow(); + if ((msg = chSemWaitTimeoutS(&macp->tdsem, time)) == RDY_TIMEOUT) { + chSysUnlock(); + break; + } + if (time != TIME_INFINITE) + time -= (chTimeNow() - now); + chSysUnlock(); + } + return msg; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @api + */ +void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { + + chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor"); + + mac_lld_release_transmit_descriptor(tdp); +} + +/** + * @brief Waits for a received frame. + * @details Stops until a frame is received and buffered. If a frame is + * not immediately available then the invoking thread is queued + * until one is received. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK the descriptor was obtained. + * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. + * + * @api + */ +msg_t macWaitReceiveDescriptor(MACDriver *macp, + MACReceiveDescriptor *rdp, + systime_t time) { + msg_t msg; + systime_t now; + + chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1", + "not active"); + + while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) && + (time > 0)) { + chSysLock(); + now = chTimeNow(); + if ((msg = chSemWaitTimeoutS(&macp->rdsem, time)) == RDY_TIMEOUT) { + chSysUnlock(); + break; + } + if (time != TIME_INFINITE) + time -= (chTimeNow() - now); + chSysUnlock(); + } + return msg; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @api + */ +void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { + + chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor"); + + mac_lld_release_receive_descriptor(rdp); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @api + */ +bool_t macPollLinkStatus(MACDriver *macp) { + + chDbgCheck((macp != NULL), "macPollLinkStatus"); + chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1", + "not active"); + + return mac_lld_poll_link_status(macp); +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/src/mmc_spi.c b/os/hal/src/mmc_spi.c new file mode 100644 index 000000000..3a5958ec8 --- /dev/null +++ b/os/hal/src/mmc_spi.c @@ -0,0 +1,878 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Parts of this file have been contributed by Matthias Blaicher. + */ + +/** + * @file mmc_spi.c + * @brief MMC over SPI driver code. + * + * @addtogroup MMC_SPI + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/* Forward declarations required by mmc_vmt.*/ +static bool_t mmc_read(void *instance, uint32_t startblk, + uint8_t *buffer, uint32_t n); +static bool_t mmc_write(void *instance, uint32_t startblk, + const uint8_t *buffer, uint32_t n); + +/** + * @brief Virtual methods table. + */ +static const struct MMCDriverVMT mmc_vmt = { + (bool_t (*)(void *))mmc_lld_is_card_inserted, + (bool_t (*)(void *))mmc_lld_is_write_protected, + (bool_t (*)(void *))mmcConnect, + (bool_t (*)(void *))mmcDisconnect, + mmc_read, + mmc_write, + (bool_t (*)(void *))mmcSync, + (bool_t (*)(void *, BlockDeviceInfo *))mmcGetInfo +}; + +/** + * @brief Lookup table for CRC-7 ( based on polynomial x^7 + x^3 + 1). + */ +static const uint8_t crc7_lookup_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, + 0x6c, 0x65, 0x7e, 0x77, 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, 0x32, 0x3b, 0x20, 0x29, + 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, + 0x47, 0x4e, 0x55, 0x5c, 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, 0x7d, 0x74, 0x6f, 0x66, + 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, + 0x3a, 0x33, 0x28, 0x21, 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5a, + 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, + 0x34, 0x3d, 0x26, 0x2f, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x6a, 0x63, 0x78, 0x71, + 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, + 0x49, 0x40, 0x5b, 0x52, 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, 0x17, 0x1e, 0x05, 0x0c, + 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, + 0x62, 0x6b, 0x70, 0x79 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static bool_t mmc_read(void *instance, uint32_t startblk, + uint8_t *buffer, uint32_t n) { + + if (mmcStartSequentialRead((MMCDriver *)instance, startblk)) + return CH_FAILED; + while (n > 0) { + if (mmcSequentialRead((MMCDriver *)instance, buffer)) + return CH_FAILED; + buffer += MMCSD_BLOCK_SIZE; + n--; + } + if (mmcStopSequentialRead((MMCDriver *)instance)) + return CH_FAILED; + return CH_SUCCESS; +} + +static bool_t mmc_write(void *instance, uint32_t startblk, + const uint8_t *buffer, uint32_t n) { + + if (mmcStartSequentialWrite((MMCDriver *)instance, startblk)) + return CH_FAILED; + while (n > 0) { + if (mmcSequentialWrite((MMCDriver *)instance, buffer)) + return CH_FAILED; + buffer += MMCSD_BLOCK_SIZE; + n--; + } + if (mmcStopSequentialWrite((MMCDriver *)instance)) + return CH_FAILED; + return CH_SUCCESS; +} + +/** + * @brief Calculate the MMC standard CRC-7 based on a lookup table. + * + * @param[in] crc start value for CRC + * @param[in] buffer pointer to data buffer + * @param[in] len length of data + * @return Calculated CRC + */ +static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) { + + while (len--) + crc = crc7_lookup_table[(crc << 1) ^ (*buffer++)]; + return crc; +} + +/** + * @brief Waits an idle condition. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @notapi + */ +static void wait(MMCDriver *mmcp) { + int i; + uint8_t buf[4]; + + for (i = 0; i < 16; i++) { + spiReceive(mmcp->config->spip, 1, buf); + if (buf[0] == 0xFF) + return; + } + /* Looks like it is a long wait.*/ + while (TRUE) { + spiReceive(mmcp->config->spip, 1, buf); + if (buf[0] == 0xFF) + break; +#ifdef MMC_NICE_WAITING + /* Trying to be nice with the other threads.*/ + chThdSleep(1); +#endif + } +} + +/** + * @brief Sends a command header. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * + * @notapi + */ +static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { + uint8_t buf[6]; + + /* Wait for the bus to become idle if a write operation was in progress.*/ + wait(mmcp); + + buf[0] = 0x40 | cmd; + buf[1] = arg >> 24; + buf[2] = arg >> 16; + buf[3] = arg >> 8; + buf[4] = arg; + /* Calculate CRC for command header, shift to right position, add stop bit.*/ + buf[5] = ((crc7(0, buf, 5) & 0x7F) << 1) | 0x01; + + spiSend(mmcp->config->spip, 6, buf); +} + +/** + * @brief Receives a single byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The response as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t recvr1(MMCDriver *mmcp) { + int i; + uint8_t r1[1]; + + for (i = 0; i < 9; i++) { + spiReceive(mmcp->config->spip, 1, r1); + if (r1[0] != 0xFF) + return r1[0]; + } + return 0xFF; +} + +/** + * @brief Receives a three byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to four bytes wide buffer + * @return First response byte as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t recvr3(MMCDriver *mmcp, uint8_t* buffer) { + uint8_t r1; + + r1 = recvr1(mmcp); + spiReceive(mmcp->config->spip, 4, buffer); + + return r1; +} + +/** + * @brief Sends a command an returns a single byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * @return The response as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t send_command_R1(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { + uint8_t r1; + + spiSelect(mmcp->config->spip); + send_hdr(mmcp, cmd, arg); + r1 = recvr1(mmcp); + spiUnselect(mmcp->config->spip); + return r1; +} + +/** + * @brief Sends a command which returns a five bytes response (R3). + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * @param[out] response pointer to four bytes wide uint8_t buffer + * @return The first byte of the response (R1) as an @p + * uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg, + uint8_t *response) { + uint8_t r1; + + spiSelect(mmcp->config->spip); + send_hdr(mmcp, cmd, arg); + r1 = recvr3(mmcp, response); + spiUnselect(mmcp->config->spip); + return r1; +} + +/** + * @brief Reads the CSD. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] csd pointer to the CSD buffer + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @notapi + */ +static bool_t read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) { + unsigned i; + uint8_t *bp, buf[16]; + + spiSelect(mmcp->config->spip); + send_hdr(mmcp, cmd, 0); + if (recvr1(mmcp) != 0x00) { + spiUnselect(mmcp->config->spip); + return CH_FAILED; + } + + /* Wait for data availability.*/ + for (i = 0; i < MMC_WAIT_DATA; i++) { + spiReceive(mmcp->config->spip, 1, buf); + if (buf[0] == 0xFE) { + uint32_t *wp; + + spiReceive(mmcp->config->spip, 16, buf); + bp = buf; + for (wp = &cxd[3]; wp >= cxd; wp--) { + *wp = ((uint32_t)bp[0] << 24) | ((uint32_t)bp[1] << 16) | + ((uint32_t)bp[2] << 8) | (uint32_t)bp[3]; + bp += 4; + } + + /* CRC ignored then end of transaction. */ + spiIgnore(mmcp->config->spip, 2); + spiUnselect(mmcp->config->spip); + + return CH_SUCCESS; + } + } + return CH_FAILED; +} + +/** + * @brief Waits that the card reaches an idle state. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @notapi + */ +static void sync(MMCDriver *mmcp) { + uint8_t buf[1]; + + spiSelect(mmcp->config->spip); + while (TRUE) { + spiReceive(mmcp->config->spip, 1, buf); + if (buf[0] == 0xFF) + break; +#ifdef MMC_NICE_WAITING + chThdSleep(1); /* Trying to be nice with the other threads.*/ +#endif + } + spiUnselect(mmcp->config->spip); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MMC over SPI driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void mmcInit(void) { + +} + +/** + * @brief Initializes an instance. + * + * @param[out] mmcp pointer to the @p MMCDriver object + * + * @init + */ +void mmcObjectInit(MMCDriver *mmcp) { + + mmcp->vmt = &mmc_vmt; + mmcp->state = BLK_STOP; + mmcp->config = NULL; + mmcp->block_addresses = FALSE; +} + +/** + * @brief Configures and activates the MMC peripheral. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] config pointer to the @p MMCConfig object. + * + * @api + */ +void mmcStart(MMCDriver *mmcp, const MMCConfig *config) { + + chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart"); + chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), + "mmcStart(), #1", "invalid state"); + + mmcp->config = config; + mmcp->state = BLK_ACTIVE; +} + +/** + * @brief Disables the MMC peripheral. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @api + */ +void mmcStop(MMCDriver *mmcp) { + + chDbgCheck(mmcp != NULL, "mmcStop"); + chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), + "mmcStop(), #1", "invalid state"); + + spiStop(mmcp->config->spip); + mmcp->state = BLK_STOP; +} + +/** + * @brief Performs the initialization procedure on the inserted card. + * @details This function should be invoked when a card is inserted and + * brings the driver in the @p MMC_READY state where it is possible + * to perform read and write operations. + * @note It is possible to invoke this function from the insertion event + * handler. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded and the driver is now + * in the @p MMC_READY state. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcConnect(MMCDriver *mmcp) { + unsigned i; + uint8_t r3[4]; + + chDbgCheck(mmcp != NULL, "mmcConnect"); + + chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), + "mmcConnect(), #1", "invalid state"); + + /* Connection procedure in progress.*/ + mmcp->state = BLK_CONNECTING; + + /* Slow clock mode and 128 clock pulses.*/ + spiStart(mmcp->config->spip, mmcp->config->lscfg); + spiIgnore(mmcp->config->spip, 16); + + /* SPI mode selection.*/ + i = 0; + while (TRUE) { + if (send_command_R1(mmcp, MMCSD_CMD_GO_IDLE_STATE, 0) == 0x01) + break; + if (++i >= MMC_CMD0_RETRY) + goto failed; + chThdSleepMilliseconds(10); + } + + /* Try to detect if this is a high capacity card and switch to block + addresses if possible. + This method is based on "How to support SDC Ver2 and high capacity cards" + by ElmChan.*/ + if (send_command_R3(mmcp, MMCSD_CMD_SEND_IF_COND, + MMCSD_CMD8_PATTERN, r3) != 0x05) { + + /* Switch to SDHC mode.*/ + i = 0; + while (TRUE) { + if ((send_command_R1(mmcp, MMCSD_CMD_APP_CMD, 0) == 0x01) && + (send_command_R3(mmcp, MMCSD_CMD_APP_OP_COND, + 0x400001aa, r3) == 0x00)) + break; + + if (++i >= MMC_ACMD41_RETRY) + goto failed; + chThdSleepMilliseconds(10); + } + + /* Execute dedicated read on OCR register */ + send_command_R3(mmcp, MMCSD_CMD_READ_OCR, 0, r3); + + /* Check if CCS is set in response. Card operates in block mode if set.*/ + if (r3[0] & 0x40) + mmcp->block_addresses = TRUE; + } + + /* Initialization.*/ + i = 0; + while (TRUE) { + uint8_t b = send_command_R1(mmcp, MMCSD_CMD_INIT, 0); + if (b == 0x00) + break; + if (b != 0x01) + goto failed; + if (++i >= MMC_CMD1_RETRY) + goto failed; + chThdSleepMilliseconds(10); + } + + /* Initialization complete, full speed.*/ + spiStart(mmcp->config->spip, mmcp->config->hscfg); + + /* Setting block size.*/ + if (send_command_R1(mmcp, MMCSD_CMD_SET_BLOCKLEN, + MMCSD_BLOCK_SIZE) != 0x00) + goto failed; + + /* Determine capacity.*/ + if (read_CxD(mmcp, MMCSD_CMD_SEND_CSD, mmcp->csd)) + goto failed; + mmcp->capacity = mmcsdGetCapacity(mmcp->csd); + if (mmcp->capacity == 0) + goto failed; + + if (read_CxD(mmcp, MMCSD_CMD_SEND_CID, mmcp->cid)) + goto failed; + + mmcp->state = BLK_READY; + return CH_SUCCESS; + + /* Connection failed, state reset to BLK_ACTIVE.*/ +failed: + spiStop(mmcp->config->spip); + mmcp->state = BLK_ACTIVE; + return CH_FAILED; +} + +/** + * @brief Brings the driver in a state safe for card removal. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The operation status. + * + * @retval CH_SUCCESS the operation succeeded and the driver is now + * in the @p MMC_INSERTED state. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcDisconnect(MMCDriver *mmcp) { + + chDbgCheck(mmcp != NULL, "mmcDisconnect"); + + chSysLock(); + chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), + "mmcDisconnect(), #1", "invalid state"); + if (mmcp->state == BLK_ACTIVE) { + chSysUnlock(); + return CH_SUCCESS; + } + mmcp->state = BLK_DISCONNECTING; + chSysUnlock(); + + /* Wait for the pending write operations to complete.*/ + spiStart(mmcp->config->spip, mmcp->config->hscfg); + sync(mmcp); + + spiStop(mmcp->config->spip); + mmcp->state = BLK_ACTIVE; + return CH_SUCCESS; +} + +/** + * @brief Starts a sequential read. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] startblk first block to read + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) { + + chDbgCheck(mmcp != NULL, "mmcStartSequentialRead"); + chDbgAssert(mmcp->state == BLK_READY, + "mmcStartSequentialRead(), #1", "invalid state"); + + /* Read operation in progress.*/ + mmcp->state = BLK_READING; + + /* (Re)starting the SPI in case it has been reprogrammed externally, it can + happen if the SPI bus is shared among multiple peripherals.*/ + spiStart(mmcp->config->spip, mmcp->config->hscfg); + spiSelect(mmcp->config->spip); + + if (mmcp->block_addresses) + send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk); + else + send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk * MMCSD_BLOCK_SIZE); + + if (recvr1(mmcp) != 0x00) { + spiStop(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_FAILED; + } + return CH_SUCCESS; +} + +/** + * @brief Reads a block within a sequential read operation. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to the read buffer + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) { + int i; + + chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead"); + + if (mmcp->state != BLK_READING) + return CH_FAILED; + + for (i = 0; i < MMC_WAIT_DATA; i++) { + spiReceive(mmcp->config->spip, 1, buffer); + if (buffer[0] == 0xFE) { + spiReceive(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer); + /* CRC ignored. */ + spiIgnore(mmcp->config->spip, 2); + return CH_SUCCESS; + } + } + /* Timeout.*/ + spiUnselect(mmcp->config->spip); + spiStop(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_FAILED; +} + +/** + * @brief Stops a sequential read gracefully. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcStopSequentialRead(MMCDriver *mmcp) { + static const uint8_t stopcmd[] = {0x40 | MMCSD_CMD_STOP_TRANSMISSION, + 0, 0, 0, 0, 1, 0xFF}; + + chDbgCheck(mmcp != NULL, "mmcStopSequentialRead"); + + if (mmcp->state != BLK_READING) + return CH_FAILED; + + spiSend(mmcp->config->spip, sizeof(stopcmd), stopcmd); +/* result = recvr1(mmcp) != 0x00;*/ + /* Note, ignored r1 response, it can be not zero, unknown issue.*/ + (void) recvr1(mmcp); + + /* Read operation finished.*/ + spiUnselect(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_SUCCESS; +} + +/** + * @brief Starts a sequential write. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] startblk first block to write + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) { + + chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite"); + chDbgAssert(mmcp->state == BLK_READY, + "mmcStartSequentialWrite(), #1", "invalid state"); + + /* Write operation in progress.*/ + mmcp->state = BLK_WRITING; + + spiStart(mmcp->config->spip, mmcp->config->hscfg); + spiSelect(mmcp->config->spip); + if (mmcp->block_addresses) + send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, startblk); + else + send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, + startblk * MMCSD_BLOCK_SIZE); + + if (recvr1(mmcp) != 0x00) { + spiStop(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_FAILED; + } + return CH_SUCCESS; +} + +/** + * @brief Writes a block within a sequential write operation. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to the write buffer + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) { + static const uint8_t start[] = {0xFF, 0xFC}; + uint8_t b[1]; + + chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite"); + + if (mmcp->state != BLK_WRITING) + return CH_FAILED; + + spiSend(mmcp->config->spip, sizeof(start), start); /* Data prologue. */ + spiSend(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer);/* Data. */ + spiIgnore(mmcp->config->spip, 2); /* CRC ignored. */ + spiReceive(mmcp->config->spip, 1, b); + if ((b[0] & 0x1F) == 0x05) { + wait(mmcp); + return CH_SUCCESS; + } + + /* Error.*/ + spiUnselect(mmcp->config->spip); + spiStop(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_FAILED; +} + +/** + * @brief Stops a sequential write gracefully. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcStopSequentialWrite(MMCDriver *mmcp) { + static const uint8_t stop[] = {0xFD, 0xFF}; + + chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite"); + + if (mmcp->state != BLK_WRITING) + return CH_FAILED; + + spiSend(mmcp->config->spip, sizeof(stop), stop); + spiUnselect(mmcp->config->spip); + + /* Write operation finished.*/ + mmcp->state = BLK_READY; + return CH_SUCCESS; +} + +/** + * @brief Waits for card idle condition. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcSync(MMCDriver *mmcp) { + + chDbgCheck(mmcp != NULL, "mmcSync"); + + if (mmcp->state != BLK_READY) + return CH_FAILED; + + /* Synchronization operation in progress.*/ + mmcp->state = BLK_SYNCING; + + spiStart(mmcp->config->spip, mmcp->config->hscfg); + sync(mmcp); + + /* Synchronization operation finished.*/ + mmcp->state = BLK_READY; + return CH_SUCCESS; +} + +/** + * @brief Returns the media info. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] bdip pointer to a @p BlockDeviceInfo structure + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) { + + chDbgCheck((mmcp != NULL) && (bdip != NULL), "mmcGetInfo"); + + if (mmcp->state != BLK_READY) + return CH_FAILED; + + bdip->blk_num = mmcp->capacity; + bdip->blk_size = MMCSD_BLOCK_SIZE; + + return CH_SUCCESS; +} + +/** + * @brief Erases blocks. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] startblk starting block number + * @param[in] endblk ending block number + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) { + + chDbgCheck((mmcp != NULL), "mmcErase"); + + /* Erase operation in progress.*/ + mmcp->state = BLK_WRITING; + + /* Handling command differences between HC and normal cards.*/ + if (!mmcp->block_addresses) { + startblk *= MMCSD_BLOCK_SIZE; + endblk *= MMCSD_BLOCK_SIZE; + } + + if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_START, startblk)) + goto failed; + + if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_END, endblk)) + goto failed; + + if (send_command_R1(mmcp, MMCSD_CMD_ERASE, 0)) + goto failed; + + mmcp->state = BLK_READY; + return CH_SUCCESS; + + /* Command failed, state reset to BLK_ACTIVE.*/ +failed: + spiStop(mmcp->config->spip); + mmcp->state = BLK_READY; + return CH_FAILED; +} + +#endif /* HAL_USE_MMC_SPI */ + +/** @} */ diff --git a/os/hal/src/mmcsd.c b/os/hal/src/mmcsd.c new file mode 100644 index 000000000..c83095981 --- /dev/null +++ b/os/hal/src/mmcsd.c @@ -0,0 +1,114 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file mmcsd.c + * @brief MMC/SD cards common code. + * + * @addtogroup MMCSD + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Gets a bit field from a words array. + * @note The bit zero is the LSb of the first word. + * + * @param[in] data pointer to the words array + * @param[in] end bit offset of the last bit of the field, inclusive + * @param[in] start bit offset of the first bit of the field, inclusive + * + * @return The bits field value, left aligned. + * + * @notapi + */ +static uint32_t mmcsd_get_slice(uint32_t *data, uint32_t end, uint32_t start) { + unsigned startidx, endidx, startoff; + uint32_t endmask; + + chDbgCheck((end >= start) && ((end - start) < 32), "mmcsd_get_slice"); + + startidx = start / 32; + startoff = start % 32; + endidx = end / 32; + endmask = (1 << ((end % 32) + 1)) - 1; + + /* One or two pieces?*/ + if (startidx < endidx) + return (data[startidx] >> startoff) | /* Two pieces case. */ + ((data[endidx] & endmask) << (32 - startoff)); + return (data[startidx] & endmask) >> startoff; /* One piece case. */ +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Extract card capacity from a CSD. + * @details The capacity is returned as number of available blocks. + * + * @param[in] csd the CSD record + * + * @return The card capacity. + * @retval 0 CSD format error + */ +uint32_t mmcsdGetCapacity(uint32_t csd[4]) { + + switch (csd[3] >> 30) { + uint32_t a, b, c; + case 0: + /* CSD version 1.0 */ + a = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE); + b = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE); + c = mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE); + return (a + 1) << (b + 2) << (c - 9); /* 2^9 == MMCSD_BLOCK_SIZE. */ + case 1: + /* CSD version 2.0.*/ + return 1024 * (mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1); + default: + /* Reserved value detected.*/ + return 0; + } +} + +#endif /* HAL_USE_MMC_SPI || HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/src/pal.c b/os/hal/src/pal.c new file mode 100644 index 000000000..cc382edab --- /dev/null +++ b/os/hal/src/pal.c @@ -0,0 +1,127 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file pal.c + * @brief I/O Ports Abstraction Layer code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Read from an I/O bus. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The function internally uses the @p palReadGroup() macro. The use + * of this function is preferred when you value code size, readability + * and error checking over speed. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @return The bus logical states. + * + * @api + */ +ioportmask_t palReadBus(IOBus *bus) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palReadBus"); + + return palReadGroup(bus->portid, bus->mask, bus->offset); +} + +/** + * @brief Write to an I/O bus. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @param[in] bits the bits to be written on the I/O bus. Values exceeding + * the bus width are masked so most significant bits are + * lost. + * + * @api + */ +void palWriteBus(IOBus *bus, ioportmask_t bits) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palWriteBus"); + + palWriteGroup(bus->portid, bus->mask, bus->offset, bits); +} + +/** + * @brief Programs a bus with the specified mode. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @param[in] mode the mode + * + * @api + */ +void palSetBusMode(IOBus *bus, iomode_t mode) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palSetBusMode"); + + palSetGroupMode(bus->portid, bus->mask, bus->offset, mode); +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/src/pwm.c b/os/hal/src/pwm.c new file mode 100644 index 000000000..c6843a928 --- /dev/null +++ b/os/hal/src/pwm.c @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file pwm.c + * @brief PWM Driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief PWM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void pwmInit(void) { + + pwm_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p PWMDriver structure. + * + * @param[out] pwmp pointer to a @p PWMDriver object + * + * @init + */ +void pwmObjectInit(PWMDriver *pwmp) { + + pwmp->state = PWM_STOP; + pwmp->config = NULL; +#if defined(PWM_DRIVER_EXT_INIT_HOOK) + PWM_DRIVER_EXT_INIT_HOOK(pwmp); +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] config pointer to a @p PWMConfig object + * + * @api + */ +void pwmStart(PWMDriver *pwmp, const PWMConfig *config) { + + chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart"); + + chSysLock(); + chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), + "pwmStart(), #1", "invalid state"); + pwmp->config = config; + pwmp->period = config->period; + pwm_lld_start(pwmp); + pwmp->state = PWM_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @api + */ +void pwmStop(PWMDriver *pwmp) { + + chDbgCheck(pwmp != NULL, "pwmStop"); + + chSysLock(); + chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), + "pwmStop(), #1", "invalid state"); + pwm_lld_stop(pwmp); + pwmp->state = PWM_STOP; + chSysUnlock(); +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @api + */ +void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) { + + chDbgCheck(pwmp != NULL, "pwmChangePeriod"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmChangePeriod(), #1", "invalid state"); + pwmChangePeriodI(pwmp, period); + chSysUnlock(); +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @api + */ +void pwmEnableChannel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), + "pwmEnableChannel"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmEnableChannel(), #1", "not ready"); + pwm_lld_enable_channel(pwmp, channel, width); + chSysUnlock(); +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @api + */ +void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) { + + chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), + "pwmEnableChannel"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmDisableChannel(), #1", "not ready"); + pwm_lld_disable_channel(pwmp, channel); + chSysUnlock(); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c new file mode 100644 index 000000000..e0a1c227b --- /dev/null +++ b/os/hal/src/rtc.c @@ -0,0 +1,186 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file rtc.c + * @brief RTC Driver code. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief RTC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void rtcInit(void) { + + rtc_lld_init(); +} + +/** + * @brief Set current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) { + + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime"); + + chSysLock(); + rtcSetTimeI(rtcp, timespec); + chSysUnlock(); +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) { + + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime"); + + chSysLock(); + rtcGetTimeI(rtcp, timespec); + chSysUnlock(); +} + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL + * + * @api + */ +void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm"); + + chSysLock(); + rtcSetAlarmI(rtcp, alarm, alarmspec); + chSysUnlock(); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @api + */ +void rtcGetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL), + "rtcGetAlarm"); + + chSysLock(); + rtcGetAlarmI(rtcp, alarm, alarmspec); + chSysUnlock(); +} +#endif /* RTC_ALARMS > 0 */ + +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables the callback, use a @p NULL + * pointer in order to disable it. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @api + */ +void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) { + + chDbgCheck((rtcp != NULL), "rtcSetCallback"); + + chSysLock(); + rtcSetCallbackI(rtcp, callback); + chSysUnlock(); +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/** + * @brief Get current time in format suitable for usage in FatFS. + * + * @param[in] rtcp pointer to RTC driver structure + * @return FAT time value. + * + * @api + */ +uint32_t rtcGetTimeFat(RTCDriver *rtcp) { + + chDbgCheck((rtcp != NULL), "rtcSetTime"); + return rtc_lld_get_time_fat(rtcp); +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/src/sdc.c b/os/hal/src/sdc.c new file mode 100644 index 000000000..f95331d44 --- /dev/null +++ b/os/hal/src/sdc.c @@ -0,0 +1,575 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file sdc.c + * @brief SDC Driver code. + * + * @addtogroup SDC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Virtual methods table. + */ +static const struct SDCDriverVMT sdc_vmt = { + (bool_t (*)(void *))sdc_lld_is_card_inserted, + (bool_t (*)(void *))sdc_lld_is_write_protected, + (bool_t (*)(void *))sdcConnect, + (bool_t (*)(void *))sdcDisconnect, + (bool_t (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead, + (bool_t (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite, + (bool_t (*)(void *))sdcSync, + (bool_t (*)(void *, BlockDeviceInfo *))sdcGetInfo +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for the card to complete pending operations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp) { + uint32_t resp[1]; + + while (TRUE) { + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS, + sdcp->rca, resp) || + MMCSD_R1_ERROR(resp[0])) + return CH_FAILED; + switch (MMCSD_R1_STS(resp[0])) { + case MMCSD_STS_TRAN: + return CH_SUCCESS; + case MMCSD_STS_DATA: + case MMCSD_STS_RCV: + case MMCSD_STS_PRG: +#if SDC_NICE_WAITING + chThdSleepMilliseconds(1); +#endif + continue; + default: + /* The card should have been initialized so any other state is not + valid and is reported as an error.*/ + return CH_FAILED; + } + } + /* If something going too wrong.*/ + return CH_FAILED; +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SDC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdcInit(void) { + + sdc_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p SDCDriver structure. + * + * @param[out] sdcp pointer to the @p SDCDriver object + * + * @init + */ +void sdcObjectInit(SDCDriver *sdcp) { + + sdcp->vmt = &sdc_vmt; + sdcp->state = BLK_STOP; + sdcp->errors = SDC_NO_ERROR; + sdcp->config = NULL; + sdcp->capacity = 0; +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if + * the driver supports a default configuration or + * requires no configuration + * + * @api + */ +void sdcStart(SDCDriver *sdcp, const SDCConfig *config) { + + chDbgCheck(sdcp != NULL, "sdcStart"); + + chSysLock(); + chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), + "sdcStart(), #1", "invalid state"); + sdcp->config = config; + sdc_lld_start(sdcp); + sdcp->state = BLK_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @api + */ +void sdcStop(SDCDriver *sdcp) { + + chDbgCheck(sdcp != NULL, "sdcStop"); + + chSysLock(); + chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), + "sdcStop(), #1", "invalid state"); + sdc_lld_stop(sdcp); + sdcp->state = BLK_STOP; + chSysUnlock(); +} + +/** + * @brief Performs the initialization procedure on the inserted card. + * @details This function should be invoked when a card is inserted and + * brings the driver in the @p BLK_READY state where it is possible + * to perform read and write operations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +bool_t sdcConnect(SDCDriver *sdcp) { + uint32_t resp[1]; + + chDbgCheck(sdcp != NULL, "sdcConnect"); + chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), + "mmcConnect(), #1", "invalid state"); + + /* Connection procedure in progress.*/ + sdcp->state = BLK_CONNECTING; + + /* Card clock initialization.*/ + sdc_lld_start_clk(sdcp); + + /* Enforces the initial card state.*/ + sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); + + /* V2.0 cards detection.*/ + if (!sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_IF_COND, + MMCSD_CMD8_PATTERN, resp)) { + sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20; + /* Voltage verification.*/ + if (((resp[0] >> 8) & 0xF) != 1) + goto failed; + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + } + else { +#if SDC_MMC_SUPPORT + /* MMC or SD V1.1 detection.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || + MMCSD_R1_ERROR(resp[0])) + sdcp->cardmode = SDC_MODE_CARDTYPE_MMC; + else +#endif /* SDC_MMC_SUPPORT */ + sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11; + } + +#if SDC_MMC_SUPPORT + if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) { + /* TODO: MMC initialization.*/ + goto failed; + } + else +#endif /* SDC_MMC_SUPPORT */ + { + unsigned i; + uint32_t ocr; + + /* SD initialization.*/ + if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20) + ocr = 0xC0100000; + else + ocr = 0x80100000; + + /* SD-type initialization. */ + i = 0; + while (TRUE) { + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_APP_OP_COND, ocr, resp)) + goto failed; + if ((resp[0] & 0x80000000) != 0) { + if (resp[0] & 0x40000000) + sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY; + break; + } + if (++i >= SDC_INIT_RETRY) + goto failed; + chThdSleepMilliseconds(10); + } + } + + /* Reads CID.*/ + if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_ALL_SEND_CID, 0, sdcp->cid)) + goto failed; + + /* Asks for the RCA.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_RELATIVE_ADDR, + 0, &sdcp->rca)) + goto failed; + + /* Reads CSD.*/ + if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_SEND_CSD, + sdcp->rca, sdcp->csd)) + goto failed; + + /* Switches to high speed.*/ + sdc_lld_set_data_clk(sdcp); + + /* Selects the card for operations.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEL_DESEL_CARD, + sdcp->rca, resp)) + goto failed; + + /* Block length fixed at 512 bytes.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BLOCKLEN, + MMCSD_BLOCK_SIZE, resp) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + + /* Switches to wide bus mode.*/ + switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) { + case SDC_MODE_CARDTYPE_SDV11: + case SDC_MODE_CARDTYPE_SDV20: + sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT); + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, sdcp->rca, resp) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BUS_WIDTH, 2, resp) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + break; + } + + /* Determine capacity.*/ + sdcp->capacity = mmcsdGetCapacity(sdcp->csd); + if (sdcp->capacity == 0) + goto failed; + + /* Initialization complete.*/ + sdcp->state = BLK_READY; + return CH_SUCCESS; + + /* Connection failed, state reset to BLK_ACTIVE.*/ +failed: + sdc_lld_stop_clk(sdcp); + sdcp->state = BLK_ACTIVE; + return CH_FAILED; +} + +/** + * @brief Brings the driver in a state safe for card removal. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +bool_t sdcDisconnect(SDCDriver *sdcp) { + + chDbgCheck(sdcp != NULL, "sdcDisconnect"); + + chSysLock(); + chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), + "sdcDisconnect(), #1", "invalid state"); + if (sdcp->state == BLK_ACTIVE) { + chSysUnlock(); + return CH_SUCCESS; + } + sdcp->state = BLK_DISCONNECTING; + chSysUnlock(); + + /* Waits for eventual pending operations completion.*/ + if (_sdc_wait_for_transfer_state(sdcp)) { + sdc_lld_stop_clk(sdcp); + sdcp->state = BLK_ACTIVE; + return CH_FAILED; + } + + /* Card clock stopped.*/ + sdc_lld_stop_clk(sdcp); + sdcp->state = BLK_ACTIVE; + return CH_SUCCESS; +} + +/** + * @brief Reads one or more blocks. + * @pre The driver must be in the @p BLK_READY state after a successful + * sdcConnect() invocation. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + bool_t status; + + chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcRead"); + chDbgAssert(sdcp->state == BLK_READY, "sdcRead(), #1", "invalid state"); + + if ((startblk + n - 1) > sdcp->capacity){ + sdcp->errors |= SDC_OVERFLOW_ERROR; + return CH_FAILED; + } + + /* Read operation in progress.*/ + sdcp->state = BLK_READING; + + status = sdc_lld_read(sdcp, startblk, buf, n); + + /* Read operation finished.*/ + sdcp->state = BLK_READY; + return status; +} + +/** + * @brief Writes one or more blocks. + * @pre The driver must be in the @p BLK_READY state after a successful + * sdcConnect() invocation. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @api + */ +bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + bool_t status; + + chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcWrite"); + chDbgAssert(sdcp->state == BLK_READY, "sdcWrite(), #1", "invalid state"); + + if ((startblk + n - 1) > sdcp->capacity){ + sdcp->errors |= SDC_OVERFLOW_ERROR; + return CH_FAILED; + } + + /* Write operation in progress.*/ + sdcp->state = BLK_WRITING; + + status = sdc_lld_write(sdcp, startblk, buf, n); + + /* Write operation finished.*/ + sdcp->state = BLK_READY; + return status; +} + +/** + * @brief Returns the errors mask associated to the previous operation. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The errors mask. + * + * @api + */ +sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) { + sdcflags_t flags; + + chDbgCheck(sdcp != NULL, "sdcGetAndClearErrors"); + chDbgAssert(sdcp->state == BLK_READY, + "sdcGetAndClearErrors(), #1", "invalid state"); + + chSysLock(); + flags = sdcp->errors; + sdcp->errors = SDC_NO_ERROR; + chSysUnlock(); + return flags; +} + +/** + * @brief Waits for card idle condition. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t sdcSync(SDCDriver *sdcp) { + bool_t result; + + chDbgCheck(sdcp != NULL, "sdcSync"); + + if (sdcp->state != BLK_READY) + return CH_FAILED; + + /* Synchronization operation in progress.*/ + sdcp->state = BLK_SYNCING; + + result = sdc_lld_sync(sdcp); + + /* Synchronization operation finished.*/ + sdcp->state = BLK_READY; + return result; +} + +/** + * @brief Returns the media info. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[out] bdip pointer to a @p BlockDeviceInfo structure + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) { + + chDbgCheck((sdcp != NULL) && (bdip != NULL), "sdcGetInfo"); + + if (sdcp->state != BLK_READY) + return CH_FAILED; + + bdip->blk_num = sdcp->capacity; + bdip->blk_size = MMCSD_BLOCK_SIZE; + + return CH_SUCCESS; +} + + +/** + * @brief Erases the supplied blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk starting block number + * @param[in] endblk ending block number + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) { + uint32_t resp[1]; + + chDbgCheck((sdcp != NULL), "sdcErase"); + chDbgAssert(sdcp->state == BLK_READY, "sdcErase(), #1", "invalid state"); + + /* Erase operation in progress.*/ + sdcp->state = BLK_WRITING; + + /* Handling command differences between HC and normal cards.*/ + if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) { + startblk *= MMCSD_BLOCK_SIZE; + endblk *= MMCSD_BLOCK_SIZE; + } + + _sdc_wait_for_transfer_state(sdcp); + + if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START, + startblk, resp) != CH_SUCCESS) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + + if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END, + endblk, resp) != CH_SUCCESS) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + + if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE, + 0, resp) != CH_SUCCESS) || + MMCSD_R1_ERROR(resp[0])) + goto failed; + + /* Quick sleep to allow it to transition to programming or receiving state */ + /* TODO: ??????????????????????????? */ + + /* Wait for it to return to transfer state to indicate it has finished erasing */ + _sdc_wait_for_transfer_state(sdcp); + + sdcp->state = BLK_READY; + return CH_SUCCESS; + +failed: + sdcp->state = BLK_READY; + return CH_FAILED; +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/src/serial.c b/os/hal/src/serial.c new file mode 100644 index 000000000..fdb802ccc --- /dev/null +++ b/os/hal/src/serial.c @@ -0,0 +1,246 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file serial.c + * @brief Serial Driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation, the following functions just invoke the equivalent + * queue-level function or macro. + */ + +static size_t write(void *ip, const uint8_t *bp, size_t n) { + + return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, + n, TIME_INFINITE); +} + +static size_t read(void *ip, uint8_t *bp, size_t n) { + + return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, + n, TIME_INFINITE); +} + +static msg_t put(void *ip, uint8_t b) { + + return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE); +} + +static msg_t get(void *ip) { + + return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE); +} + +static msg_t putt(void *ip, uint8_t b, systime_t timeout) { + + return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout); +} + +static msg_t gett(void *ip, systime_t timeout) { + + return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + + return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time); +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time); +} + +static const struct SerialDriverVMT vmt = { + write, read, put, get, + putt, gett, writet, readt +}; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdInit(void) { + + sd_lld_init(); +} + +/** + * @brief Initializes a generic full duplex driver object. + * @details The HW dependent part of the initialization has to be performed + * outside, usually in the hardware initialization code. + * + * @param[out] sdp pointer to a @p SerialDriver structure + * @param[in] inotify pointer to a callback function that is invoked when + * some data is read from the Queue. The value can be + * @p NULL. + * @param[in] onotify pointer to a callback function that is invoked when + * some data is written in the Queue. The value can be + * @p NULL. + * + * @init + */ +void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) { + + sdp->vmt = &vmt; + chEvtInit(&sdp->event); + sdp->state = SD_STOP; + chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp); + chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp); +} + +/** + * @brief Configures and starts the driver. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @api + */ +void sdStart(SerialDriver *sdp, const SerialConfig *config) { + + chDbgCheck(sdp != NULL, "sdStart"); + + chSysLock(); + chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), + "sdStart(), #1", + "invalid state"); + sd_lld_start(sdp, config); + sdp->state = SD_READY; + chSysUnlock(); +} + +/** + * @brief Stops the driver. + * @details Any thread waiting on the driver's queues will be awakened with + * the message @p Q_RESET. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @api + */ +void sdStop(SerialDriver *sdp) { + + chDbgCheck(sdp != NULL, "sdStop"); + + chSysLock(); + chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), + "sdStop(), #1", + "invalid state"); + sd_lld_stop(sdp); + sdp->state = SD_STOP; + chOQResetI(&sdp->oqueue); + chIQResetI(&sdp->iqueue); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Handles incoming data. + * @details This function must be called from the input interrupt service + * routine in order to enqueue incoming data and generate the + * related events. + * @note The incoming data event is only generated when the input queue + * becomes non-empty. + * @note In order to gain some performance it is suggested to not use + * this function directly but copy this code directly into the + * interrupt service routine. + * + * @param[in] sdp pointer to a @p SerialDriver structure + * @param[in] b the byte to be written in the driver's Input Queue + * + * @iclass + */ +void sdIncomingDataI(SerialDriver *sdp, uint8_t b) { + + chDbgCheckClassI(); + chDbgCheck(sdp != NULL, "sdIncomingDataI"); + + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + if (chIQPutI(&sdp->iqueue, b) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); +} + +/** + * @brief Handles outgoing data. + * @details Must be called from the output interrupt service routine in order + * to get the next byte to be transmitted. + * @note In order to gain some performance it is suggested to not use + * this function directly but copy this code directly into the + * interrupt service routine. + * + * @param[in] sdp pointer to a @p SerialDriver structure + * @return The byte value read from the driver's output queue. + * @retval Q_EMPTY if the queue is empty (the lower driver usually + * disables the interrupt source when this happens). + * + * @iclass + */ +msg_t sdRequestDataI(SerialDriver *sdp) { + msg_t b; + + chDbgCheckClassI(); + chDbgCheck(sdp != NULL, "sdRequestDataI"); + + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/src/serial_usb.c b/os/hal/src/serial_usb.c new file mode 100644 index 000000000..ff6e94b07 --- /dev/null +++ b/os/hal/src/serial_usb.c @@ -0,0 +1,414 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file serial_usb.c + * @brief Serial over USB Driver code. + * + * @addtogroup SERIAL_USB + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/* + * Current Line Coding. + */ +static cdc_linecoding_t linecoding = { + {0x00, 0x96, 0x00, 0x00}, /* 38400. */ + LC_STOP_1, LC_PARITY_NONE, 8 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation. + */ + +static size_t write(void *ip, const uint8_t *bp, size_t n) { + + return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, + n, TIME_INFINITE); +} + +static size_t read(void *ip, uint8_t *bp, size_t n) { + + return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, + n, TIME_INFINITE); +} + +static msg_t put(void *ip, uint8_t b) { + + return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, TIME_INFINITE); +} + +static msg_t get(void *ip) { + + return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, TIME_INFINITE); +} + +static msg_t putt(void *ip, uint8_t b, systime_t timeout) { + + return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout); +} + +static msg_t gett(void *ip, systime_t timeout) { + + return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + + return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time); +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time); +} + +static const struct SerialUSBDriverVMT vmt = { + write, read, put, get, + putt, gett, writet, readt +}; + +/** + * @brief Notification of data removed from the input queue. + */ +static void inotify(GenericQueue *qp) { + size_t n, maxsize; + SerialUSBDriver *sdup = chQGetLink(qp); + + /* If the USB driver is not in the appropriate state then transactions + must not be started.*/ + if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || + (sdup->state != SDU_READY)) + return; + + /* If there is in the queue enough space to hold at least one packet and + a transaction is not yet started then a new transaction is started for + the available space.*/ + maxsize = sdup->config->usbp->epc[sdup->config->bulk_out]->out_maxsize; + if (!usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_out) && + ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize)) { + chSysUnlock(); + + n = (n / maxsize) * maxsize; + usbPrepareQueuedReceive(sdup->config->usbp, + sdup->config->bulk_out, + &sdup->iqueue, n); + + chSysLock(); + usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out); + } +} + +/** + * @brief Notification of data inserted into the output queue. + */ +static void onotify(GenericQueue *qp) { + size_t n; + SerialUSBDriver *sdup = chQGetLink(qp); + + /* If the USB driver is not in the appropriate state then transactions + must not be started.*/ + if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || + (sdup->state != SDU_READY)) + return; + + /* If there is not an ongoing transaction and the output queue contains + data then a new transaction is started.*/ + if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in) && + ((n = chOQGetFullI(&sdup->oqueue)) > 0)) { + chSysUnlock(); + + usbPrepareQueuedTransmit(sdup->config->usbp, + sdup->config->bulk_in, + &sdup->oqueue, n); + + chSysLock(); + usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in); + } +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sduInit(void) { +} + +/** + * @brief Initializes a generic full duplex driver object. + * @details The HW dependent part of the initialization has to be performed + * outside, usually in the hardware initialization code. + * + * @param[out] sdup pointer to a @p SerialUSBDriver structure + * + * @init + */ +void sduObjectInit(SerialUSBDriver *sdup) { + + sdup->vmt = &vmt; + chEvtInit(&sdup->event); + sdup->state = SDU_STOP; + chIQInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify, sdup); + chOQInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify, sdup); +} + +/** + * @brief Configures and starts the driver. + * + * @param[in] sdup pointer to a @p SerialUSBDriver object + * @param[in] config the serial over USB driver configuration + * + * @api + */ +void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) { + USBDriver *usbp = config->usbp; + + chDbgCheck(sdup != NULL, "sduStart"); + + chSysLock(); + chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), + "sduStart(), #1", + "invalid state"); + usbp->in_params[config->bulk_in - 1] = sdup; + usbp->out_params[config->bulk_out - 1] = sdup; + usbp->in_params[config->int_in - 1] = sdup; + sdup->config = config; + sdup->state = SDU_READY; + chSysUnlock(); +} + +/** + * @brief Stops the driver. + * @details Any thread waiting on the driver's queues will be awakened with + * the message @p Q_RESET. + * + * @param[in] sdup pointer to a @p SerialUSBDriver object + * + * @api + */ +void sduStop(SerialUSBDriver *sdup) { + USBDriver *usbp = sdup->config->usbp; + + chDbgCheck(sdup != NULL, "sdStop"); + + chSysLock(); + + chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), + "sduStop(), #1", + "invalid state"); + + /* Driver in stopped state.*/ + usbp->in_params[sdup->config->bulk_in - 1] = NULL; + usbp->out_params[sdup->config->bulk_out - 1] = NULL; + usbp->in_params[sdup->config->int_in - 1] = NULL; + sdup->state = SDU_STOP; + + /* Queues reset in order to signal the driver stop to the application.*/ + chnAddFlagsI(sdup, CHN_DISCONNECTED); + chIQResetI(&sdup->iqueue); + chOQResetI(&sdup->oqueue); + chSchRescheduleS(); + + chSysUnlock(); +} + +/** + * @brief USB device configured handler. + * + * @param[in] sdup pointer to a @p SerialUSBDriver object + * + * @iclass + */ +void sduConfigureHookI(SerialUSBDriver *sdup) { + USBDriver *usbp = sdup->config->usbp; + + chIQResetI(&sdup->iqueue); + chOQResetI(&sdup->oqueue); + chnAddFlagsI(sdup, CHN_CONNECTED); + + /* Starts the first OUT transaction immediately.*/ + usbPrepareQueuedReceive(usbp, sdup->config->bulk_out, &sdup->iqueue, + usbp->epc[sdup->config->bulk_out]->out_maxsize); + usbStartReceiveI(usbp, sdup->config->bulk_out); +} + +/** + * @brief Default requests hook. + * @details Applications wanting to use the Serial over USB driver can use + * this function as requests hook in the USB configuration. + * The following requests are emulated: + * - CDC_GET_LINE_CODING. + * - CDC_SET_LINE_CODING. + * - CDC_SET_CONTROL_LINE_STATE. + * . + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The hook status. + * @retval TRUE Message handled internally. + * @retval FALSE Message not handled. + */ +bool_t sduRequestsHook(USBDriver *usbp) { + + if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) { + switch (usbp->setup[1]) { + case CDC_GET_LINE_CODING: + usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); + return TRUE; + case CDC_SET_LINE_CODING: + usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); + return TRUE; + case CDC_SET_CONTROL_LINE_STATE: + /* Nothing to do, there are no control lines.*/ + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + default: + return FALSE; + } + } + return FALSE; +} + +/** + * @brief Default data transmitted callback. + * @details The application must use this function as callback for the IN + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduDataTransmitted(USBDriver *usbp, usbep_t ep) { + size_t n; + SerialUSBDriver *sdup = usbp->in_params[ep - 1]; + + if (sdup == NULL) + return; + + chSysLockFromIsr(); + chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY); + + if ((n = chOQGetFullI(&sdup->oqueue)) > 0) { + /* The endpoint cannot be busy, we are in the context of the callback, + so it is safe to transmit without a check.*/ + chSysUnlockFromIsr(); + + usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, n); + + chSysLockFromIsr(); + usbStartTransmitI(usbp, ep); + } + else if ((usbp->epc[ep]->in_state->txsize > 0) && + !(usbp->epc[ep]->in_state->txsize & + (usbp->epc[ep]->in_maxsize - 1))) { + /* Transmit zero sized packet in case the last one has maximum allowed + size. Otherwise the recipient may expect more data coming soon and + not return buffered data to app. See section 5.8.3 Bulk Transfer + Packet Size Constraints of the USB Specification document.*/ + chSysUnlockFromIsr(); + + usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, 0); + + chSysLockFromIsr(); + usbStartTransmitI(usbp, ep); + } + + chSysUnlockFromIsr(); +} + +/** + * @brief Default data received callback. + * @details The application must use this function as callback for the OUT + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduDataReceived(USBDriver *usbp, usbep_t ep) { + size_t n, maxsize; + SerialUSBDriver *sdup = usbp->out_params[ep - 1]; + + if (sdup == NULL) + return; + + chSysLockFromIsr(); + chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE); + + /* Writes to the input queue can only happen when there is enough space + to hold at least one packet.*/ + maxsize = usbp->epc[ep]->out_maxsize; + if ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize) { + /* The endpoint cannot be busy, we are in the context of the callback, + so a packet is in the buffer for sure.*/ + chSysUnlockFromIsr(); + + n = (n / maxsize) * maxsize; + usbPrepareQueuedReceive(usbp, ep, &sdup->iqueue, n); + + chSysLockFromIsr(); + usbStartReceiveI(usbp, ep); + } + + chSysUnlockFromIsr(); +} + +/** + * @brief Default data received callback. + * @details The application must use this function as callback for the IN + * interrupt endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/src/spi.c b/os/hal/src/spi.c new file mode 100644 index 000000000..2dc0cc6ee --- /dev/null +++ b/os/hal/src/spi.c @@ -0,0 +1,439 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file spi.c + * @brief SPI Driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SPI Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void spiInit(void) { + + spi_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p SPIDriver structure. + * + * @param[out] spip pointer to the @p SPIDriver object + * + * @init + */ +void spiObjectInit(SPIDriver *spip) { + + spip->state = SPI_STOP; + spip->config = NULL; +#if SPI_USE_WAIT + spip->thread = NULL; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&spip->mutex); +#else + chSemInit(&spip->semaphore, 1); +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_INIT_HOOK) + SPI_DRIVER_EXT_INIT_HOOK(spip); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] config pointer to the @p SPIConfig object + * + * @api + */ +void spiStart(SPIDriver *spip, const SPIConfig *config) { + + chDbgCheck((spip != NULL) && (config != NULL), "spiStart"); + + chSysLock(); + chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), + "spiStart(), #1", "invalid state"); + spip->config = config; + spi_lld_start(spip); + spip->state = SPI_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the SPI peripheral. + * @note Deactivating the peripheral also enforces a release of the slave + * select line. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiStop(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiStop"); + + chSysLock(); + chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), + "spiStop(), #1", "invalid state"); + spi_lld_stop(spip); + spip->state = SPI_STOP; + chSysUnlock(); +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiSelect(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiSelect"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiSelect(), #1", "not ready"); + spiSelectI(spip); + chSysUnlock(); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiUnselect(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiUnselect"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiUnselect(), #1", "not ready"); + spiUnselectI(spip); + chSysUnlock(); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @api + */ +void spiStartIgnore(SPIDriver *spip, size_t n) { + + chDbgCheck((spip != NULL) && (n > 0), "spiStartIgnore"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartIgnore(), #1", "not ready"); + spiStartIgnoreI(spip, n); + chSysUnlock(); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiStartExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), + "spiStartExchange"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartExchange(), #1", "not ready"); + spiStartExchangeI(spip, n, txbuf, rxbuf); + chSysUnlock(); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), + "spiStartSend"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartSend(), #1", "not ready"); + spiStartSendI(spip, n, txbuf); + chSysUnlock(); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), + "spiStartReceive"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartReceive(), #1", "not ready"); + spiStartReceiveI(spip, n, rxbuf); + chSysUnlock(); +} + +#if SPI_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Ignores data on the SPI bus. + * @details This synchronous function performs the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @api + */ +void spiIgnore(SPIDriver *spip, size_t n) { + + chDbgCheck((spip != NULL) && (n > 0), "spiIgnoreWait"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiIgnore(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, "spiIgnore(), #2", "has callback"); + spiStartIgnoreI(spip, n); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This synchronous function performs a simultaneous transmit/receive + * operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), + "spiExchange"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiExchange(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, + "spiExchange(), #2", "has callback"); + spiStartExchangeI(spip, n, txbuf, rxbuf); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Sends data over the SPI bus. + * @details This synchronous function performs a transmit operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void spiSend(SPIDriver *spip, size_t n, const void *txbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), "spiSend"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiSend(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, "spiSend(), #2", "has callback"); + spiStartSendI(spip, n, txbuf); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Receives data from the SPI bus. + * @details This synchronous function performs a receive operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), + "spiReceive"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiReceive(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, + "spiReceive(), #2", "has callback"); + spiStartReceiveI(spip, n, rxbuf); + _spi_wait_s(spip); + chSysUnlock(); +} +#endif /* SPI_USE_WAIT */ + +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the SPI bus. + * @details This function tries to gain ownership to the SPI bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiAcquireBus(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&spip->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&spip->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the SPI bus. + * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiReleaseBus(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiReleaseBus"); + +#if CH_USE_MUTEXES + (void)spip; + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&spip->semaphore); +#endif +} +#endif /* SPI_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/src/tm.c b/os/hal/src/tm.c new file mode 100644 index 000000000..5b002cd90 --- /dev/null +++ b/os/hal/src/tm.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file tm.c + * @brief Time Measurement driver code. + * + * @addtogroup TM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_TM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Subsystem calibration value. + */ +static halrtcnt_t measurement_offset; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Starts a measurement. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @notapi + */ +static void tm_start(TimeMeasurement *tmp) { + + tmp->last = halGetCounterValue(); +} + +/** + * @brief Stops a measurement. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @notapi + */ +static void tm_stop(TimeMeasurement *tmp) { + + halrtcnt_t now = halGetCounterValue(); + tmp->last = now - tmp->last - measurement_offset; + if (tmp->last > tmp->worst) + tmp->worst = tmp->last; + else if (tmp->last < tmp->best) + tmp->best = tmp->last; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the Time Measurement unit. + * + * @init + */ +void tmInit(void) { + TimeMeasurement tm; + + /* Time Measurement subsystem calibration, it does a null measurement + and calculates the call overhead which is subtracted to real + measurements.*/ + measurement_offset = 0; + tmObjectInit(&tm); + tmStartMeasurement(&tm); + tmStopMeasurement(&tm); + measurement_offset = tm.last; +} + +/** + * @brief Initializes a @p TimeMeasurement object. + * + * @param[out] tmp pointer to a @p TimeMeasurement structure + * + * @init + */ +void tmObjectInit(TimeMeasurement *tmp) { + + tmp->start = tm_start; + tmp->stop = tm_stop; + tmp->last = (halrtcnt_t)0; + tmp->worst = (halrtcnt_t)0; + tmp->best = (halrtcnt_t)-1; +} + +#endif /* HAL_USE_TM */ + +/** @} */ diff --git a/os/hal/src/uart.c b/os/hal/src/uart.c new file mode 100644 index 000000000..71869538d --- /dev/null +++ b/os/hal/src/uart.c @@ -0,0 +1,353 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file uart.c + * @brief UART Driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief UART Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void uartInit(void) { + + uart_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p UARTDriver structure. + * + * @param[out] uartp pointer to the @p UARTDriver object + * + * @init + */ +void uartObjectInit(UARTDriver *uartp) { + + uartp->state = UART_STOP; + uartp->txstate = UART_TX_IDLE; + uartp->rxstate = UART_RX_IDLE; + uartp->config = NULL; + /* Optional, user-defined initializer.*/ +#if defined(UART_DRIVER_EXT_INIT_HOOK) + UART_DRIVER_EXT_INIT_HOOK(uartp); +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] config pointer to the @p UARTConfig object + * + * @api + */ +void uartStart(UARTDriver *uartp, const UARTConfig *config) { + + chDbgCheck((uartp != NULL) && (config != NULL), "uartStart"); + + chSysLock(); + chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), + "uartStart(), #1", "invalid state"); + + uartp->config = config; + uart_lld_start(uartp); + uartp->state = UART_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @api + */ +void uartStop(UARTDriver *uartp) { + + chDbgCheck(uartp != NULL, "uartStop"); + + chSysLock(); + chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), + "uartStop(), #1", "invalid state"); + + uart_lld_stop(uartp); + uartp->state = UART_STOP; + uartp->txstate = UART_TX_IDLE; + uartp->rxstate = UART_RX_IDLE; + chSysUnlock(); +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) { + + chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), + "uartStartSend"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, + "uartStartSend(), #1", "is active"); + chDbgAssert(uartp->txstate != UART_TX_ACTIVE, + "uartStartSend(), #2", "tx active"); + + uart_lld_start_send(uartp, n, txbuf); + uartp->txstate = UART_TX_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @iclass + */ +void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) { + + chDbgCheckClassI(); + chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), + "uartStartSendI"); + chDbgAssert(uartp->state == UART_READY, + "uartStartSendI(), #1", "is active"); + chDbgAssert(uartp->txstate != UART_TX_ACTIVE, + "uartStartSendI(), #2", "tx active"); + + uart_lld_start_send(uartp, n, txbuf); + uartp->txstate = UART_TX_ACTIVE; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * @retval 0 There was no transmit operation in progress. + * + * @api + */ +size_t uartStopSend(UARTDriver *uartp) { + size_t n; + + chDbgCheck(uartp != NULL, "uartStopSend"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, "uartStopSend(), #1", "not active"); + + if (uartp->txstate == UART_TX_ACTIVE) { + n = uart_lld_stop_send(uartp); + uartp->txstate = UART_TX_IDLE; + } + else + n = 0; + chSysUnlock(); + return n; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * @retval 0 There was no transmit operation in progress. + * + * @iclass + */ +size_t uartStopSendI(UARTDriver *uartp) { + + chDbgCheckClassI(); + chDbgCheck(uartp != NULL, "uartStopSendI"); + chDbgAssert(uartp->state == UART_READY, "uartStopSendI(), #1", "not active"); + + if (uartp->txstate == UART_TX_ACTIVE) { + size_t n = uart_lld_stop_send(uartp); + uartp->txstate = UART_TX_IDLE; + return n; + } + return 0; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] rxbuf the pointer to the receive buffer + * + * @api + */ +void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) { + + chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), + "uartStartReceive"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, + "uartStartReceive(), #1", "is active"); + chDbgAssert(uartp->rxstate != UART_RX_ACTIVE, + "uartStartReceive(), #2", "rx active"); + + uart_lld_start_receive(uartp, n, rxbuf); + uartp->rxstate = UART_RX_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) { + + chDbgCheckClassI(); + chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), + "uartStartReceiveI"); + chDbgAssert(uartp->state == UART_READY, + "uartStartReceiveI(), #1", "is active"); + chDbgAssert(uartp->rxstate != UART_RX_ACTIVE, + "uartStartReceiveI(), #2", "rx active"); + + uart_lld_start_receive(uartp, n, rxbuf); + uartp->rxstate = UART_RX_ACTIVE; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * @retval 0 There was no receive operation in progress. + * + * @api + */ +size_t uartStopReceive(UARTDriver *uartp) { + size_t n; + + chDbgCheck(uartp != NULL, "uartStopReceive"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, + "uartStopReceive(), #1", "not active"); + + if (uartp->rxstate == UART_RX_ACTIVE) { + n = uart_lld_stop_receive(uartp); + uartp->rxstate = UART_RX_IDLE; + } + else + n = 0; + chSysUnlock(); + return n; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * @retval 0 There was no receive operation in progress. + * + * @iclass + */ +size_t uartStopReceiveI(UARTDriver *uartp) { + + chDbgCheckClassI(); + chDbgCheck(uartp != NULL, "uartStopReceiveI"); + chDbgAssert(uartp->state == UART_READY, + "uartStopReceiveI(), #1", "not active"); + + if (uartp->rxstate == UART_RX_ACTIVE) { + size_t n = uart_lld_stop_receive(uartp); + uartp->rxstate = UART_RX_IDLE; + return n; + } + return 0; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/src/usb.c b/os/hal/src/usb.c new file mode 100644 index 000000000..1da532abf --- /dev/null +++ b/os/hal/src/usb.c @@ -0,0 +1,780 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file usb.c + * @brief USB Driver code. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "usb.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t zero_status[] = {0x00, 0x00}; +static const uint8_t active_status[] ={0x00, 0x00}; +static const uint8_t halted_status[] = {0x01, 0x00}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief SET ADDRESS transaction callback. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void set_address(USBDriver *usbp) { + + usbp->address = usbp->setup[2]; + usb_lld_set_address(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS); + usbp->state = USB_SELECTED; +} + +/** + * @brief Standard requests handler. + * @details This is the standard requests default handler, most standard + * requests are handled here, the user can override the standard + * handling using the @p requests_hook_cb hook in the + * @p USBConfig structure. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The request handling exit code. + * @retval FALSE Request not recognized by the handler or error. + * @retval TRUE Request handled. + */ +static bool_t default_handler(USBDriver *usbp) { + const USBDescriptor *dp; + + /* Decoding the request.*/ + switch (((usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK | + USB_RTYPE_TYPE_MASK)) | + (usbp->setup[1] << 8))) { + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_STATUS << 8): + /* Just returns the current status word.*/ + usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_CLEAR_FEATURE << 8): + /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature + number is handled as an error.*/ + if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { + usbp->status &= ~2; + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + } + return FALSE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_FEATURE << 8): + /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature + number is handled as an error.*/ + if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { + usbp->status |= 2; + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + } + return FALSE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_ADDRESS << 8): + /* The SET_ADDRESS handling can be performed here or postponed after + the status packed depending on the USB_SET_ADDRESS_MODE low + driver setting.*/ +#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS + if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) && + (usbp->setup[1] == USB_REQ_SET_ADDRESS)) + set_address(usbp); + usbSetupTransfer(usbp, NULL, 0, NULL); +#else + usbSetupTransfer(usbp, NULL, 0, set_address); +#endif + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_DESCRIPTOR << 8): + /* Handling descriptor requests from the host.*/ + dp = usbp->config->get_descriptor_cb( + usbp, usbp->setup[3], usbp->setup[2], + usbFetchWord(&usbp->setup[4])); + if (dp == NULL) + return FALSE; + usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_CONFIGURATION << 8): + /* Returning the last selected configuration.*/ + usbSetupTransfer(usbp, &usbp->configuration, 1, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_CONFIGURATION << 8): + /* Handling configuration selection from the host.*/ + usbp->configuration = usbp->setup[2]; + if (usbp->configuration == 0) + usbp->state = USB_SELECTED; + else + usbp->state = USB_ACTIVE; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED); + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_STATUS << 8): + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SYNCH_FRAME << 8): + /* Just sending two zero bytes, the application can change the behavior + using a hook..*/ + usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_GET_STATUS << 8): + /* Sending the EP status.*/ + if (usbp->setup[4] & 0x80) { + switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0F)) { + case EP_STATUS_STALLED: + usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); + return TRUE; + case EP_STATUS_ACTIVE: + usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); + return TRUE; + default: + return FALSE; + } + } + else { + switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0F)) { + case EP_STATUS_STALLED: + usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); + return TRUE; + case EP_STATUS_ACTIVE: + usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); + return TRUE; + default: + return FALSE; + } + } + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_CLEAR_FEATURE << 8): + /* Only ENDPOINT_HALT is handled as feature.*/ + if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) + return FALSE; + /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/ + if ((usbp->setup[4] & 0x0F) > 0) { + if (usbp->setup[4] & 0x80) + usb_lld_clear_in(usbp, usbp->setup[4] & 0x0F); + else + usb_lld_clear_out(usbp, usbp->setup[4] & 0x0F); + } + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SET_FEATURE << 8): + /* Only ENDPOINT_HALT is handled as feature.*/ + if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) + return FALSE; + /* Stalling the EP, not valid for EP0, it is ignored in that case.*/ + if ((usbp->setup[4] & 0x0F) > 0) { + if (usbp->setup[4] & 0x80) + usb_lld_stall_in(usbp, usbp->setup[4] & 0x0F); + else + usb_lld_stall_out(usbp, usbp->setup[4] & 0x0F); + } + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_DESCRIPTOR << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_CLEAR_FEATURE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_FEATURE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_INTERFACE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_INTERFACE << 8): + /* All the above requests are not handled here, if you need them then + use the hook mechanism and provide handling.*/ + default: + return FALSE; + } +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief USB Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void usbInit(void) { + + usb_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p USBDriver structure. + * + * @param[out] usbp pointer to the @p USBDriver object + * + * @init + */ +void usbObjectInit(USBDriver *usbp) { + unsigned i; + + usbp->state = USB_STOP; + usbp->config = NULL; + for (i = 0; i < USB_MAX_ENDPOINTS; i++) { + usbp->in_params[i] = NULL; + usbp->out_params[i] = NULL; + } + usbp->transmitting = 0; + usbp->receiving = 0; +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] config pointer to the @p USBConfig object + * + * @api + */ +void usbStart(USBDriver *usbp, const USBConfig *config) { + unsigned i; + + chDbgCheck((usbp != NULL) && (config != NULL), "usbStart"); + + chSysLock(); + chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY), + "usbStart(), #1", "invalid state"); + usbp->config = config; + for (i = 0; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + usb_lld_start(usbp); + usbp->state = USB_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @api + */ +void usbStop(USBDriver *usbp) { + + chDbgCheck(usbp != NULL, "usbStop"); + + chSysLock(); + chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) || + (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE), + "usbStop(), #1", "invalid state"); + usb_lld_stop(usbp); + usbp->state = USB_STOP; + chSysUnlock(); +} + +/** + * @brief Enables an endpoint. + * @details This function enables an endpoint, both IN and/or OUT directions + * depending on the configuration structure. + * @note This function must be invoked in response of a SET_CONFIGURATION + * or SET_INTERFACE message. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] epcp the endpoint configuration + * + * @iclass + */ +void usbInitEndpointI(USBDriver *usbp, usbep_t ep, + const USBEndpointConfig *epcp) { + + chDbgCheckClassI(); + chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI"); + chDbgAssert(usbp->state == USB_ACTIVE, + "usbEnableEndpointI(), #1", "invalid state"); + chDbgAssert(usbp->epc[ep] == NULL, + "usbEnableEndpointI(), #2", "already initialized"); + + /* Logically enabling the endpoint in the USBDriver structure.*/ + if (epcp->in_state != NULL) + memset(epcp->in_state, 0, sizeof(USBInEndpointState)); + if (epcp->out_state != NULL) + memset(epcp->out_state, 0, sizeof(USBOutEndpointState)); + + usbp->epc[ep] = epcp; + + /* Low level endpoint activation.*/ + usb_lld_init_endpoint(usbp, ep); +} + +/** + * @brief Disables all the active endpoints. + * @details This function disables all the active endpoints except the + * endpoint zero. + * @note This function must be invoked in response of a SET_CONFIGURATION + * message with configuration number zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @iclass + */ +void usbDisableEndpointsI(USBDriver *usbp) { + unsigned i; + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbDisableEndpointsI"); + chDbgAssert(usbp->state == USB_SELECTED, + "usbDisableEndpointsI(), #1", "invalid state"); + + usbp->transmitting &= ~1; + usbp->receiving &= ~1; + for (i = 1; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + + /* Low level endpoints deactivation.*/ + usb_lld_disable_endpoints(usbp); +} + +/** + * @brief Prepares for a receive transaction on an OUT endpoint. + * @post The endpoint is ready for @p usbStartReceiveI(). + * @note This function can be called both in ISR and thread context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the received data + * @param[in] n transaction size + * + * @special + */ +void usbPrepareReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n) { + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + osp->rxqueued = FALSE; + osp->mode.linear.rxbuf = buf; + osp->rxsize = n; + osp->rxcnt = 0; + + usb_lld_prepare_receive(usbp, ep); +} + +/** + * @brief Prepares for a transmit transaction on an IN endpoint. + * @post The endpoint is ready for @p usbStartTransmitI(). + * @note This function can be called both in ISR and thread context. + * @note The queue must contain at least the amount of data specified + * as transaction size. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the data to be transmitted + * @param[in] n transaction size + * + * @special + */ +void usbPrepareTransmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + isp->txqueued = FALSE; + isp->mode.linear.txbuf = buf; + isp->txsize = n; + isp->txcnt = 0; + + usb_lld_prepare_transmit(usbp, ep); +} + +/** + * @brief Prepares for a receive transaction on an OUT endpoint. + * @post The endpoint is ready for @p usbStartReceiveI(). + * @note This function can be called both in ISR and thread context. + * @note The queue must have enough free space to accommodate the + * specified transaction size rounded to the next packet size + * boundary. For example if the transaction size is 1 and the + * packet size is 64 then the queue must have space for at least + * 64 bytes. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] iqp input queue to be filled with incoming data + * @param[in] n transaction size + * + * @special + */ +void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep, + InputQueue *iqp, size_t n) { + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + osp->rxqueued = TRUE; + osp->mode.queue.rxqueue = iqp; + osp->rxsize = n; + osp->rxcnt = 0; + + usb_lld_prepare_receive(usbp, ep); +} + +/** + * @brief Prepares for a transmit transaction on an IN endpoint. + * @post The endpoint is ready for @p usbStartTransmitI(). + * @note This function can be called both in ISR and thread context. + * @note The transmit transaction size is equal to the data contained + * in the queue. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] oqp output queue to be fetched for outgoing data + * @param[in] n transaction size + * + * @special + */ +void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep, + OutputQueue *oqp, size_t n) { + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + isp->txqueued = TRUE; + isp->mode.queue.txqueue = oqp; + isp->txsize = n; + isp->txcnt = 0; + + usb_lld_prepare_transmit(usbp, ep); +} + +/** + * @brief Starts a receive transaction on an OUT endpoint. + * @post The endpoint callback is invoked when the transfer has been + * completed. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @return The operation status. + * @retval FALSE Operation started successfully. + * @retval TRUE Endpoint busy, operation not started. + * + * @iclass + */ +bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStartReceiveI"); + + if (usbGetReceiveStatusI(usbp, ep)) + return TRUE; + + usbp->receiving |= (1 << ep); + usb_lld_start_out(usbp, ep); + return FALSE; +} + +/** + * @brief Starts a transmit transaction on an IN endpoint. + * @post The endpoint callback is invoked when the transfer has been + * completed. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @return The operation status. + * @retval FALSE Operation started successfully. + * @retval TRUE Endpoint busy, operation not started. + * + * @iclass + */ +bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStartTransmitI"); + + if (usbGetTransmitStatusI(usbp, ep)) + return TRUE; + + usbp->transmitting |= (1 << ep); + usb_lld_start_in(usbp, ep); + return FALSE; +} + +/** + * @brief Stalls an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @return The operation status. + * @retval FALSE Endpoint stalled. + * @retval TRUE Endpoint busy, not stalled. + * + * @iclass + */ +bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStallReceiveI"); + + if (usbGetReceiveStatusI(usbp, ep)) + return TRUE; + + usb_lld_stall_out(usbp, ep); + return FALSE; +} + +/** + * @brief Stalls an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @return The operation status. + * @retval FALSE Endpoint stalled. + * @retval TRUE Endpoint busy, not stalled. + * + * @iclass + */ +bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStallTransmitI"); + + if (usbGetTransmitStatusI(usbp, ep)) + return TRUE; + + usb_lld_stall_in(usbp, ep); + return FALSE; +} + +/** + * @brief USB reset routine. + * @details This function must be invoked when an USB bus reset condition is + * detected. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void _usb_reset(USBDriver *usbp) { + unsigned i; + + usbp->state = USB_READY; + usbp->status = 0; + usbp->address = 0; + usbp->configuration = 0; + usbp->transmitting = 0; + usbp->receiving = 0; + + /* Invalidates all endpoints into the USBDriver structure.*/ + for (i = 0; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + + /* EP0 state machine initialization.*/ + usbp->ep0state = USB_EP0_WAITING_SETUP; + + /* Low level reset.*/ + usb_lld_reset(usbp); +} + +/** + * @brief Default EP0 SETUP callback. + * @details This function is used by the low level driver as default handler + * for EP0 SETUP events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { + size_t max; + + usbp->ep0state = USB_EP0_WAITING_SETUP; + usbReadSetup(usbp, ep, usbp->setup); + + /* First verify if the application has an handler installed for this + request.*/ + if (!(usbp->config->requests_hook_cb) || + !(usbp->config->requests_hook_cb(usbp))) { + /* Invoking the default handler, if this fails then stalls the + endpoint zero as error.*/ + if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) || + !default_handler(usbp)) { + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; + return; + } + } + + /* Transfer preparation. The request handler must have populated + correctly the fields ep0next, ep0n and ep0endcb using the macro + usbSetupTransfer().*/ + max = usbFetchWord(&usbp->setup[6]); + /* The transfer size cannot exceed the specified amount.*/ + if (usbp->ep0n > max) + usbp->ep0n = max; + if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) { + /* IN phase.*/ + if (usbp->ep0n > 0) { + /* Starts the transmit phase.*/ + usbp->ep0state = USB_EP0_TX; + usbPrepareTransmit(usbp, 0, usbp->ep0next, usbp->ep0n); + chSysLockFromIsr(); + usbStartTransmitI(usbp, 0); + chSysUnlockFromIsr(); + } + else { + /* No transmission phase, directly receiving the zero sized status + packet.*/ + usbp->ep0state = USB_EP0_WAITING_STS; + usbPrepareReceive(usbp, 0, NULL, 0); + chSysLockFromIsr(); + usbStartReceiveI(usbp, 0); + chSysUnlockFromIsr(); + } + } + else { + /* OUT phase.*/ + if (usbp->ep0n > 0) { + /* Starts the receive phase.*/ + usbp->ep0state = USB_EP0_RX; + usbPrepareReceive(usbp, 0, usbp->ep0next, usbp->ep0n); + chSysLockFromIsr(); + usbStartReceiveI(usbp, 0); + chSysUnlockFromIsr(); + } + else { + /* No receive phase, directly sending the zero sized status + packet.*/ + usbp->ep0state = USB_EP0_SENDING_STS; + usbPrepareTransmit(usbp, 0, NULL, 0); + chSysLockFromIsr(); + usbStartTransmitI(usbp, 0); + chSysUnlockFromIsr(); + } + } +} + +/** + * @brief Default EP0 IN callback. + * @details This function is used by the low level driver as default handler + * for EP0 IN events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0in(USBDriver *usbp, usbep_t ep) { + size_t max; + + (void)ep; + switch (usbp->ep0state) { + case USB_EP0_TX: + max = usbFetchWord(&usbp->setup[6]); + /* If the transmitted size is less than the requested size and it is a + multiple of the maximum packet size then a zero size packet must be + transmitted.*/ + if ((usbp->ep0n < max) && ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) { + usbPrepareTransmit(usbp, 0, NULL, 0); + chSysLockFromIsr(); + usbStartTransmitI(usbp, 0); + chSysUnlockFromIsr(); + usbp->ep0state = USB_EP0_WAITING_TX0; + return; + } + /* Falls into, it is intentional.*/ + case USB_EP0_WAITING_TX0: + /* Transmit phase over, receiving the zero sized status packet.*/ + usbp->ep0state = USB_EP0_WAITING_STS; + usbPrepareReceive(usbp, 0, NULL, 0); + chSysLockFromIsr(); + usbStartReceiveI(usbp, 0); + chSysUnlockFromIsr(); + return; + case USB_EP0_SENDING_STS: + /* Status packet sent, invoking the callback if defined.*/ + if (usbp->ep0endcb != NULL) + usbp->ep0endcb(usbp); + usbp->ep0state = USB_EP0_WAITING_SETUP; + return; + default: + ; + } + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; +} + +/** + * @brief Default EP0 OUT callback. + * @details This function is used by the low level driver as default handler + * for EP0 OUT events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0out(USBDriver *usbp, usbep_t ep) { + + (void)ep; + switch (usbp->ep0state) { + case USB_EP0_RX: + /* Receive phase over, sending the zero sized status packet.*/ + usbp->ep0state = USB_EP0_SENDING_STS; + usbPrepareTransmit(usbp, 0, NULL, 0); + chSysLockFromIsr(); + usbStartTransmitI(usbp, 0); + chSysUnlockFromIsr(); + return; + case USB_EP0_WAITING_STS: + /* Status packet received, it must be zero sized, invoking the callback + if defined.*/ + if (usbGetReceiveTransactionSizeI(usbp, 0) != 0) + break; + if (usbp->ep0endcb != NULL) + usbp->ep0endcb(usbp); + usbp->ep0state = USB_EP0_WAITING_SETUP; + return; + default: + ; + } + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/templates/adc_lld.c b/os/hal/templates/adc_lld.c new file mode 100644 index 000000000..e6826d9ed --- /dev/null +++ b/os/hal/templates/adc_lld.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/adc_lld.c + * @brief ADC Driver subsystem low level driver source template. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ADC1 driver identifier. + */ +#if PLATFORM_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if PLATFORM_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); +#endif /* PLATFORM_ADC_USE_ADC1 */ +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + if (adcp->state == ADC_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + + } +#endif /* PLATFORM_ADC_USE_ADC1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + if (adcp->state == ADC_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + + } +#endif /* PLATFORM_ADC_USE_ADC1 */ + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + + (void)adcp; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + (void)adcp; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/templates/adc_lld.h b/os/hal/templates/adc_lld.h new file mode 100644 index 000000000..c7b4ca9cf --- /dev/null +++ b/os/hal/templates/adc_lld.h @@ -0,0 +1,213 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/adc_lld.h + * @brief ADC Driver subsystem low level driver header template. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define PLATFORM_ADC_USE_ADC1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/can_lld.c b/os/hal/templates/can_lld.c new file mode 100644 index 000000000..d095a645e --- /dev/null +++ b/os/hal/templates/can_lld.c @@ -0,0 +1,243 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/can_lld.c + * @brief CAN Driver subsystem low level driver source template. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief CAN1 driver identifier. + */ +#if PLATFORM_CAN_USE_CAN1 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if PLATFORM_CAN_USE_CAN1 + /* Driver initialization.*/ + canObjectInit(&CAND1); +#endif /* PLATFORM_CAN_USE_CAN1 */ +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + if (canp->state == CAN_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_CAN_USE_CAN1 + if (&CAND1 == canp) { + + } +#endif /* PLATFORM_CAN_USE_CAN1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + if (canp->state == CAN_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_CAN_USE_CAN1 + if (&CAND1 == canp) { + + } +#endif /* PLATFORM_CAN_USE_CAN1 */ + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + + (void)canp; + + switch (mailbox) { + case CAN_ANY_MAILBOX: + return FALSE; + case 1: + return FALSE; + case 2: + return FALSE; + case 3: + return FALSE; + default: + return FALSE; + } +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp) { + + (void)canp; + (void)mailbox; + (void)ctfp; + +} + +/** + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + + (void)canp; + (void)mailbox; + + switch (mailbox) { + case CAN_ANY_MAILBOX: + return FALSE; + case 1: + return FALSE; + case 2: + return FALSE; + default: + return FALSE; + } +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp) { + + (void)canp; + (void)mailbox; + (void)crfp; + +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + + (void)canp; + +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + + (void)canp; + +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/os/hal/templates/can_lld.h b/os/hal/templates/can_lld.h new file mode 100644 index 000000000..bfa9bb1e5 --- /dev/null +++ b/os/hal/templates/can_lld.h @@ -0,0 +1,255 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/can_lld.h + * @brief CAN Driver subsystem low level driver header template. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with automatic an wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP TRUE + +/** + * @brief This implementation supports three transmit mailboxes. + */ +#define CAN_TX_MAILBOXES 3 + +/** + * @brief This implementation supports two receive mailboxes. + */ +#define CAN_RX_MAILBOXES 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for CAN1 is included. + */ +#if !defined(PLATFORM_CAN_USE_CAN1) || defined(__DOXYGEN__) +#define PLATFORM_CAN_USE_CAN1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a transmission mailbox index. + */ +typedef uint32_t canmbx_t; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + * @note It could not be present on some architectures. + */ +typedef struct { + uint32_t dummy; +} CANFilter; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p chReceive() when listening to this event. + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + * @note The flags associated to the listeners will indicate which + * receive mailboxes become non-empty. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the listeners will indicate which + * transmit mailboxes become empty. + * + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + * @note The flags associated to the listeners will indicate the + * error(s) that have occurred. + */ + EventSource error_event; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_CAN_USE_CAN1 && !defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_is_tx_empty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *crfp); + bool_t can_lld_is_rx_nonempty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c new file mode 100644 index 000000000..e6e79e952 --- /dev/null +++ b/os/hal/templates/ext_lld.c @@ -0,0 +1,148 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/ext_lld.c + * @brief EXT Driver subsystem low level driver source template. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXT1 driver identifier. + */ +#if PLATFORM_EXT_USE_EXT1 || defined(__DOXYGEN__) +EXTDriver EXTD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + +#if PLATFORM_EXT_USE_EXT1 + /* Driver initialization.*/ + extObjectInit(&EXTD1); +#endif /* PLATFORM_EXT_USE_EXT1 */ +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + + if (extp->state == EXT_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_EXT_USE_EXT1 + if (&EXTD1 == extp) { + + } +#endif /* PLATFORM_EXT_USE_EXT1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_EXT_USE_EXT1 + if (&EXTD1 == extp) { + + } +#endif /* PLATFORM_EXT_USE_EXT1 */ + } +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/templates/ext_lld.h b/os/hal/templates/ext_lld.h new file mode 100644 index 000000000..ca020a7a6 --- /dev/null +++ b/os/hal/templates/ext_lld.h @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/ext_lld.h + * @brief EXT Driver subsystem low level driver header template. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 20 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXT driver enable switch. + * @details If set to @p TRUE the support for EXT1 is included. + */ +#if !defined(PLATFORM_EXT_USE_EXT1) || defined(__DOXYGEN__) +#define PLATFORM_EXT_USE_EXT1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_EXT_USE_EXT1 && !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/gpt_lld.c b/os/hal/templates/gpt_lld.c new file mode 100644 index 000000000..4f16b0239 --- /dev/null +++ b/os/hal/templates/gpt_lld.c @@ -0,0 +1,164 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/gpt_lld.c + * @brief GPT Driver subsystem low level driver source template. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + */ +#if PLATFORM_GPT_USE_GPT1 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if PLATFORM2_GPT_USE_TIM1 + /* Driver initialization.*/ + gptObjectInit(&GPTD1); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + + if (gptp->state == GPT_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_GPT_USE_GPT1 + if (&GPTD1 == gptp) { + + } +#endif /* PLATFORM_GPT_USE_GPT1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_GPT_USE_GPT1 + if (&GPTD1 == gptp) { + + } +#endif /* PLATFORM_GPT_USE_GPT1 */ + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + (void)gptp; + (void)interval; + +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + (void)gptp; + +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + (void)gptp; + (void)interval; + +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/templates/gpt_lld.h b/os/hal/templates/gpt_lld.h new file mode 100644 index 000000000..13251eb47 --- /dev/null +++ b/os/hal/templates/gpt_lld.h @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/gpt_lld.h + * @brief GPT Driver subsystem low level driver header template. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) { \ + (void)gptp; \ + (void)interval; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/hal_lld.c b/os/hal/templates/hal_lld.c new file mode 100644 index 000000000..68a1c02a0 --- /dev/null +++ b/os/hal/templates/hal_lld.c @@ -0,0 +1,74 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/hal_lld.c + * @brief HAL Driver subsystem low level driver source template. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + +} + +/** + * @brief Platform early initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function is meant to be invoked early during the system + * initialization, it is usually invoked from the file + * @p board.c. + * + * @special + */ +void platform_early_init(void) { + +} + +/** @} */ diff --git a/os/hal/templates/hal_lld.h b/os/hal/templates/hal_lld.h new file mode 100644 index 000000000..9fd763613 --- /dev/null +++ b/os/hal/templates/hal_lld.h @@ -0,0 +1,114 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() 0 + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() 0 + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h new file mode 100644 index 000000000..d61f89d56 --- /dev/null +++ b/os/hal/templates/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY TRUE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT TRUE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/os/hal/templates/i2c_lld.c b/os/hal/templates/i2c_lld.c new file mode 100644 index 000000000..318686b27 --- /dev/null +++ b/os/hal/templates/i2c_lld.c @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/i2c_lld.c + * @brief I2C Driver subsystem low level driver source template. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver identifier. + */ +#if PLATFORM_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if PLATFORM_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); +#endif /* PLATFORM_I2C_USE_I2C1 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + + if (i2cp->state == I2C_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + + } +#endif /* PLATFORM_I2C_USE_I2C1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + if (i2cp->state != I2C_STOP) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + + } +#endif /* PLATFORM_I2C_USE_I2C1 */ + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on STM32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + + (void)i2cp; + (void)addr; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + + return RDY_OK; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + + (void)i2cp; + (void)addr; + (void)txbuf; + (void)txbytes; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + + return RDY_OK; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/templates/i2c_lld.h b/os/hal/templates/i2c_lld.h new file mode 100644 index 000000000..83da65c11 --- /dev/null +++ b/os/hal/templates/i2c_lld.h @@ -0,0 +1,164 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/i2c_lld.h + * @brief I2C Driver subsystem low level driver header template. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define PLATFORM_I2C_USE_I2C1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief Type of I2C Driver condition flags. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ + +/** + * @brief Driver configuration structure. + */ +typedef struct { + uint32_t dummy; +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if PLATFORM_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/icu_lld.c b/os/hal/templates/icu_lld.c new file mode 100644 index 000000000..7685d39b9 --- /dev/null +++ b/os/hal/templates/icu_lld.c @@ -0,0 +1,178 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/icu_lld.c + * @brief ICU Driver subsystem low level driver source template. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICU1 driver identifier. + */ +#if PLATFORM_ICU_USE_ICU1 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + +#if PLATFORM_ICU_USE_ICU1 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); +#endif /* PLATFORM_ICU_USE_ICU1 */ +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + if (icup->state == ICU_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_ICU_USE_ICU1 + if (&ICUD1 == icup) { + + } +#endif /* PLATFORM_ICU_USE_ICU1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_ICU_USE_ICU1 + if (&ICUD1 == icup) { + + } +#endif /* PLATFORM_ICU_USE_ICU1 */ + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + (void)icup; + +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + (void)icup; + +} + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +icucnt_t icu_lld_get_width(ICUDriver *icup) { + + (void)icup; + + return 0; +} + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +icucnt_t icu_lld_get_period(ICUDriver *icup) { + + (void)icup; + + return 0; +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/templates/icu_lld.h b/os/hal/templates/icu_lld.h new file mode 100644 index 000000000..099601164 --- /dev/null +++ b/os/hal/templates/icu_lld.h @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Fabio Utzig and + Xo Wang. + */ + +/** + * @file templates/icu_lld.h + * @brief ICU Driver subsystem low level driver header template. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICU driver enable switch. + * @details If set to @p TRUE the support for ICU1 is included. + */ +#if !defined(PLATFORM_ICU_USE_ICU1) || defined(__DOXYGEN__) +#define PLATFORM_ICU_USE_ICU1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_ICU_USE_ICU1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); + icucnt_t icu_lld_get_width(ICUDriver *icup); + icucnt_t icu_lld_get_period(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/mac_lld.c b/os/hal/templates/mac_lld.c new file mode 100644 index 000000000..d4de2ce5c --- /dev/null +++ b/os/hal/templates/mac_lld.c @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/mac_lld.c + * @brief MAC Driver subsystem low level driver source template. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief MAC1 driver identifier. + */ +#if PLATFORM_MAC_USE_MAC1 || defined(__DOXYGEN__) +MACDriver ETHD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + +#if PLATFORM_MAC_USE_MAC1 + /* Driver initialization.*/ + macObjectInit(&MACD1); +#endif /* PLATFORM_MAC_USE_MAC1 */ +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + + if (macp->state == MAC_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_MAC_USE_MAC1 + if (&MACD1 == macp) { + + } +#endif /* PLATFORM_MAC_USE_MAC1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + if (macp->state == MAC_ACTIVE) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_MAC_USE_MAC1 + if (&MACD1 == macp) { + + } +#endif /* PLATFORM_MAC_USE_MAC1 */ + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + + (void)macp; + (void)tdp; + + return RDY_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + (void)tdp; + +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + + (void)macp; + (void)rdp; + + return RDY_OK; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + + (void)rdp; + +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + + (void)macp; + + return FALSE; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + (void)tdp; + (void)buf; + + return size; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + (void)rdp; + (void)buf; + + return size; +} + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * Note that a returned size lower than the amount + * requested means that more buffers must be requested + * in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep) { + + (void)tdp; + (void)size; + (void)sizep; + + return NULL; +} + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep) { + + (void)rdp; + (void)sizep; + + return NULL; +} +#endif /* MAC_USE_ZERO_COPY */ + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/templates/mac_lld.h b/os/hal/templates/mac_lld.h new file mode 100644 index 000000000..ed278f514 --- /dev/null +++ b/os/hal/templates/mac_lld.h @@ -0,0 +1,180 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/mac_lld.h + * @brief MAC Driver subsystem low level driver header template. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief MAC driver enable switch. + * @details If set to @p TRUE the support for MAC1 is included. + */ +#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__) +#define PLATFORM_MAC_USE_MAC1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_MAC_USE_MAC1 && !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/mcuconf.h b/os/hal/templates/mcuconf.h new file mode 100644 index 000000000..c5a797157 --- /dev/null +++ b/os/hal/templates/mcuconf.h @@ -0,0 +1,25 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * Platform drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#define PLATFORM_MCUCONF diff --git a/os/hal/templates/meta/driver.c b/os/hal/templates/meta/driver.c new file mode 100644 index 000000000..6eb9caf0f --- /dev/null +++ b/os/hal/templates/meta/driver.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file xxx.c + * @brief XXX Driver code. + * + * @addtogroup XXX + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief XXX Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void xxxInit(void) { + + xxx_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p XXXDriver structure. + * + * @param[out] xxxp pointer to the @p XXXDriver object + * + * @init + */ +void xxxObjectInit(XXXDriver *xxxp) { + + xxxp->state = XXX_STOP; + xxxp->config = NULL; +} + +/** + * @brief Configures and activates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * @param[in] config pointer to the @p XXXConfig object + * + * @api + */ +void xxxStart(XXXDriver *xxxp, const XXXConfig *config) { + + chDbgCheck((xxxp != NULL) && (config != NULL), "xxxStart"); + + chSysLock(); + chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY), + "xxxStart(), #1", "invalid state"); + xxxp->config = config; + xxx_lld_start(xxxp); + xxxp->state = XXX_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @api + */ +void xxxStop(XXXDriver *xxxp) { + + chDbgCheck(xxxp != NULL, "xxxStop"); + + chSysLock(); + chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY), + "xxxStop(), #1", "invalid state"); + xxx_lld_stop(xxxp); + xxxp->state = XXX_STOP; + chSysUnlock(); +} + +#endif /* HAL_USE_XXX */ + +/** @} */ diff --git a/os/hal/templates/meta/driver.h b/os/hal/templates/meta/driver.h new file mode 100644 index 000000000..84b81e009 --- /dev/null +++ b/os/hal/templates/meta/driver.h @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file xxx.h + * @brief XXX Driver macros and structures. + * + * @addtogroup XXX + * @{ + */ + +#ifndef _XXX_H_ +#define _XXX_H_ + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + XXX_UNINIT = 0, /**< Not initialized. */ + XXX_STOP = 1, /**< Stopped. */ + XXX_READY = 2, /**< Ready. */ +} xxxstate_t; + +/** + * @brief Type of a structure representing a XXX driver. + */ +typedef struct XXXDriver XXXDriver; + +#include "xxx_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void xxxInit(void); + void xxxObjectInit(XXXDriver *xxxp); + void xxxStart(XXXDriver *xxxp, const XXXConfig *config); + void xxxStop(XXXDriver *xxxp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_XXX */ + +#endif /* _XXX_H_ */ + +/** @} */ diff --git a/os/hal/templates/meta/driver_lld.c b/os/hal/templates/meta/driver_lld.c new file mode 100644 index 000000000..b01ef3fb6 --- /dev/null +++ b/os/hal/templates/meta/driver_lld.c @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/xxx_lld.c + * @brief XXX Driver subsystem low level driver source template. + * + * @addtogroup XXX + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief XXX1 driver identifier. + */ +#if PLATFORM_XXX_USE_XXX1 || defined(__DOXYGEN__) +XXXDriver XXXD1; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level XXX driver initialization. + * + * @notapi + */ +void xxx_lld_init(void) { + +#if PLATFORM_XXX_USE_XXX1 + /* Driver initialization.*/ + xxxObjectInit(&XXXD1); +#endif /* PLATFORM_XXX_USE_XXX1 */ +} + +/** + * @brief Configures and activates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @notapi + */ +void xxx_lld_start(XXXDriver *xxxp) { + + if (xxxp->state == XXX_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_XXX_USE_XXX1 + if (&XXXD1 == xxxp) { + + } +#endif /* PLATFORM_XXX_USE_XXX1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @notapi + */ +void xxx_lld_stop(XXXDriver *xxxp) { + + if (xxxp->state == XXX_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_XXX_USE_XXX1 + if (&XXXD1 == xxxp) { + + } +#endif /* PLATFORM_XXX_USE_XXX1 */ + } +} + +#endif /* HAL_USE_XXX */ + +/** @} */ diff --git a/os/hal/templates/meta/driver_lld.h b/os/hal/templates/meta/driver_lld.h new file mode 100644 index 000000000..bca5a521c --- /dev/null +++ b/os/hal/templates/meta/driver_lld.h @@ -0,0 +1,113 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/xxx_lld.h + * @brief XXX Driver subsystem low level driver header template. + * + * @addtogroup XXX + * @{ + */ + +#ifndef _XXX_LLD_H_ +#define _XXX_LLD_H_ + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief XXX driver enable switch. + * @details If set to @p TRUE the support for XXX1 is included. + */ +#if !defined(PLATFORM_XXX_USE_XXX1) || defined(__DOXYGEN__) +#define PLATFORM_XXX_USE_XXX1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an XXX driver. + */ +typedef struct XXXDriver XXXDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + +} XXXConfig; + +/** + * @brief Structure representing an XXX driver. + */ +struct XXXDriver { + /** + * @brief Driver state. + */ + xxxstate_t state; + /** + * @brief Current configuration data. + */ + const XXXConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_XXX_USE_XXX1 && !defined(__DOXYGEN__) +extern XXXDriver XXXD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void xxx_lld_init(void); + void xxx_lld_start(XXXDriver *xxxp); + void xxx_lld_stop(XXXDriver *xxxp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_XXX */ + +#endif /* _XXX_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/pal_lld.c b/os/hal/templates/pal_lld.c new file mode 100644 index 000000000..ac0bdca44 --- /dev/null +++ b/os/hal/templates/pal_lld.c @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/pal_lld.c + * @brief PAL subsystem low level driver template. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 I/O ports configuration. + * @details Ports A-D(E, F, G, H) clocks enabled. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + (void)config; + +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + (void)port; + (void)mask; + (void)mode; + +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/templates/pal_lld.h b/os/hal/templates/pal_lld.h new file mode 100644 index 000000000..e69c2ca2e --- /dev/null +++ b/os/hal/templates/pal_lld.h @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/pal_lld.h + * @brief PAL subsystem low level driver header template. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief First I/O port identifier. + * @details Low level drivers can define multiple ports, it is suggested to + * use this naming convention. + */ +#define IOPORT1 0 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) 0 + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) 0 + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @notapi + */ +#define pal_lld_toggleport(port, bits) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) 0 + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) (void)bits + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) PAL_LOW + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/platform.mk b/os/hal/templates/platform.mk new file mode 100644 index 000000000..80624fa14 --- /dev/null +++ b/os/hal/templates/platform.mk @@ -0,0 +1,19 @@ +# List of all the template platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/templates/hal_lld.c \ + ${CHIBIOS}/os/hal/templates/adc_lld.c \ + ${CHIBIOS}/os/hal/templates/can_lld.c \ + ${CHIBIOS}/os/hal/templates/ext_lld.c \ + ${CHIBIOS}/os/hal/templates/gpt_lld.c \ + ${CHIBIOS}/os/hal/templates/i2c_lld.c \ + ${CHIBIOS}/os/hal/templates/icu_lld.c \ + ${CHIBIOS}/os/hal/templates/mac_lld.c \ + ${CHIBIOS}/os/hal/templates/pal_lld.c \ + ${CHIBIOS}/os/hal/templates/pwm_lld.c \ + ${CHIBIOS}/os/hal/templates/sdc_lld.c \ + ${CHIBIOS}/os/hal/templates/serial_lld.c \ + ${CHIBIOS}/os/hal/templates/spi_lld.c \ + ${CHIBIOS}/os/hal/templates/uart_lld.c \ + ${CHIBIOS}/os/hal/templates/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/templates diff --git a/os/hal/templates/pwm_lld.c b/os/hal/templates/pwm_lld.c new file mode 100644 index 000000000..a38290334 --- /dev/null +++ b/os/hal/templates/pwm_lld.c @@ -0,0 +1,186 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/pwm_lld.c + * @brief PWM Driver subsystem low level driver source template. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWM1 driver identifier. + */ +#if PLATFORM_PWM_USE_PWM1 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if PLATFORM_PWM_USE_PWM1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); +#endif /* PLATFORM_PWM_USE_PWM1 */ +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + if (pwmp->state == PWM_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_PWM_USE_PWM1 + if (&PWMD1 == pwmp) { + + } +#endif /* PLATFORM_PWM_USE_PWM1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + if (pwmp->state == PWM_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_PWM_USE_PWM1 + if (&PWMD1 == pwmp) { + + } +#endif /* PLATFORM_PWM_USE_PWM1 */ + } +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + + (void)pwmp; + (void)period; + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + (void)pwmp; + (void)channel; + (void)width; + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + (void)pwmp; + (void)channel; + +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/templates/pwm_lld.h b/os/hal/templates/pwm_lld.h new file mode 100644 index 000000000..46e357fd4 --- /dev/null +++ b/os/hal/templates/pwm_lld.h @@ -0,0 +1,195 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/pwm_lld.h + * @brief PWM Driver subsystem low level driver header template. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 4 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWM driver enable switch. + * @details If set to @p TRUE the support for PWM1 is included. + */ +#if !defined(PLATFORM_PWM_USE_PWM1) || defined(__DOXYGEN__) +#define PLATFORM_PWM_USE_PWM1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns a PWM channel status. + * @pre The PWM unit must have been activated using @p pwmStart(). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +#define pwm_lld_is_channel_enabled(pwmp, channel) FALSE + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_PWM_USE_PWM1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/sdc_lld.c b/os/hal/templates/sdc_lld.c new file mode 100644 index 000000000..c0d311b87 --- /dev/null +++ b/os/hal/templates/sdc_lld.c @@ -0,0 +1,322 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/sdc_lld.c + * @brief SDC Driver subsystem low level driver source template. + * + * @addtogroup SDC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SDCD1 driver identifier. + */ +#if PLATFORM_SDC_USE_SDC1 || defined(__DOXYGEN__) +SDCDriver SDCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + if (sdcp->state == BLK_STOP) { + + } +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if (sdcp->state != BLK_STOP) { + + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + (void)sdcp; +} + +/** + * @brief Sets the SDIO clock to data mode (25MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp) { + + (void)sdcp; +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + (void)sdcp; +} + +/** + * @brief Switches the bus to 4 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + + (void)sdcp; + + switch (mode) { + case SDC_MODE_1BIT: + + break; + case SDC_MODE_4BIT: + + break; + case SDC_MODE_8BIT: + + break; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + (void)sdcp; + (void)cmd; + (void)arg; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; + + return CH_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; + + return CH_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; + + return CH_SUCCESS; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + + (void)sdcp; + (void)startblk; + (void)buf; + (void)n; + + return CH_SUCCESS; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval CH_SUCCESS operation succeeded. + * @retval CH_FAILED operation failed. + * + * @notapi + */ +bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + + (void)sdcp; + (void)startblk; + (void)buf; + (void)n; + + return CH_SUCCESS; +} + +/** + * @brief Waits for card idle condition. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval CH_SUCCESS the operation succeeded. + * @retval CH_FAILED the operation failed. + * + * @api + */ +bool_t sdc_lld_sync(SDCDriver *sdcp) { + + (void)sdcp; + + return CH_SUCCESS; +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/templates/sdc_lld.h b/os/hal/templates/sdc_lld.h new file mode 100644 index 000000000..aa3c7effd --- /dev/null +++ b/os/hal/templates/sdc_lld.h @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/sdc_lld.h + * @brief SDC Driver subsystem low level driver header template. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_LLD_H_ +#define _SDC_LLD_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SDC driver enable switch. + * @details If set to @p TRUE the support for SDC1 is included. + */ +#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__) +#define PLATFORM_SDC_USE_SDC1 TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of SDIO bus mode. + */ +typedef enum { + SDC_MODE_1BIT = 0, + SDC_MODE_4BIT, + SDC_MODE_8BIT +} sdcbusmode_t; + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief SDC Driver condition flags type. + */ +typedef uint32_t sdcflags_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} SDCConfig; + +/** + * @brief @p SDCDriver specific methods. + */ +#define _sdc_driver_methods \ + _mmcsd_block_device_methods + +/** + * @extends MMCSDBlockDeviceVMT + * + * @brief @p SDCDriver virtual methods table. + */ +struct SDCDriverVMT { + _sdc_driver_methods +}; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Virtual Methods Table. + */ + const struct SDCDriverVMT *vmt; + _mmcsd_block_device_data + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Errors flags. + */ + sdcflags_t errors; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name R1 response utilities + * @{ + */ +/** + * @brief Evaluates to @p TRUE if the R1 response contains error flags. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0) + +/** + * @brief Returns the status field of an R1 response. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15) + +/** + * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_SDC_USE_SDC1 && !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n); + bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n); + bool_t sdc_lld_sync(SDCDriver *sdcp); + bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/serial_lld.c b/os/hal/templates/serial_lld.c new file mode 100644 index 000000000..d6b861c12 --- /dev/null +++ b/os/hal/templates/serial_lld.c @@ -0,0 +1,133 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/serial_lld.c + * @brief Serial Driver subsystem low level driver source template. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SD1 driver identifier. + */ +#if PLATFORM_SERIAL_USE_SD1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + 38400 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if PLATFORM_SERIAL_USE_SD1 + /* Driver initialization.*/ + sdObjectInit(&SD1); +#endif /* PLATFORM_SERIAL_USE_SD1 */ +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_SERIAL_USE_SD1 + if (&SD1 == sdp) { + + } +#endif /* PLATFORM_SD_USE_SD1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_SERIAL_USE_SD1 + if (&SD1 == sdp) { + + } +#endif /* PLATFORM_SERIAL_USE_SD1 */ + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/templates/serial_lld.h b/os/hal/templates/serial_lld.h new file mode 100644 index 000000000..0e019948d --- /dev/null +++ b/os/hal/templates/serial_lld.h @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/serial_lld.h + * @brief Serial Driver subsystem low level driver header template. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SD1 driver enable switch. + * @details If set to @p TRUE the support for SD1 is included. + */ +#if !defined(PLATFORM_SERIAL_USE_SD1) || defined(__DOXYGEN__) +#define PLATFORM_SERIAL_USE_SD1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /* End of the mandatory fields.*/ +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_SERIAL_USE_SD1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/spi_lld.c b/os/hal/templates/spi_lld.c new file mode 100644 index 000000000..a53f1ef43 --- /dev/null +++ b/os/hal/templates/spi_lld.c @@ -0,0 +1,250 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/spi_lld.c + * @brief SPI Driver subsystem low level driver source template. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver identifier. + */ +#if PLATFORM_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if PLATFORM_SPI_USE_SPI1 + /* Driver initialization.*/ + spiObjectInit(&SPID1); +#endif /* PLATFORM_SPI_USE_SPI1 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_SPI_USE_SPI1 + if (&SPID1 == spip) { + + } +#endif /* PLATFORM_SPI_USE_SPI1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state == SPI_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_SPI_USE_SPI1 + if (&SPID1 == spip) { + + } +#endif /* PLATFORM_SPI_USE_SPI1 */ + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + (void)spip; + +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + (void)spip; + +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + (void)spip; + (void)n; + +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + (void)spip; + (void)n; + (void)txbuf; + (void)rxbuf; + +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + (void)spip; + (void)n; + (void)txbuf; + +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + (void)spip; + (void)n; + (void)rxbuf; + +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + (void)spip; + (void)frame; + + return 0; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/templates/spi_lld.h b/os/hal/templates/spi_lld.h new file mode 100644 index 000000000..690054f43 --- /dev/null +++ b/os/hal/templates/spi_lld.h @@ -0,0 +1,155 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/spi_lld.h + * @brief SPI Driver subsystem low level driver header template. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + */ +#if !defined(PLATFORM_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define PLATFORM_SPI_USE_SPI1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Operation complete callback. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ +} SPIConfig; + +/** + * @brief Structure representing an SPI driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/uart_lld.c b/os/hal/templates/uart_lld.c new file mode 100644 index 000000000..cc6fc27d4 --- /dev/null +++ b/os/hal/templates/uart_lld.c @@ -0,0 +1,192 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/uart_lld.c + * @brief UART Driver subsystem low level driver source template. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief UART1 driver identifier. + */ +#if PLATFORM_UART_USE_UART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if PLATFORM_UART_USE_UART1 + /* Driver initialization.*/ + uartObjectInit(&UARTD1); +#endif /* PLATFORM_UART_USE_UART1 */ +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_UART_USE_UART1 + if (&UARTD1 == uartp) { + + } +#endif /* PLATFORM_UART_USE_UART1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_UART_USE_UART1 + if (&UARTD1 == uartp) { + + } +#endif /* PLATFORM_UART_USE_UART1 */ + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + (void)uartp; + (void)n; + (void)txbuf; + +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + (void)uartp; + + return 0; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + (void)uartp; + (void)n; + (void)rxbuf; + +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + + (void)uartp; + + return 0; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/templates/uart_lld.h b/os/hal/templates/uart_lld.h new file mode 100644 index 000000000..6e34fa108 --- /dev/null +++ b/os/hal/templates/uart_lld.h @@ -0,0 +1,181 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/uart_lld.h + * @brief UART Driver subsystem low level driver header template. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + */ +#if !defined(PLATFORM_UART_USE_UART1) || defined(__DOXYGEN__) +#define PLATFORM_UART_USE_UART1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Type of structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_UART_USE_UART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/usb_lld.c b/os/hal/templates/usb_lld.c new file mode 100644 index 000000000..9a63b149c --- /dev/null +++ b/os/hal/templates/usb_lld.c @@ -0,0 +1,391 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/usb_lld.c + * @brief USB Driver subsystem low level driver source template. + * + * @addtogroup USB + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver identifier. + */ +#if PLATFORM_USB_USE_USB1 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers and threads. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + +#if PLATFORM_USB_USE_USB1 + /* Driver initialization.*/ + usbObjectInit(&USBD1); +#endif /* PLATFORM_USB_USE_USB1 */ +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_USB_USE_USB1 + if (&USBD1 == usbp) { + + } +#endif /* PLATFORM_USB_USE_USB1 */ + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + + if (usbp->state == USB_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_USB_USE_USB1 + if (&USBD1 == usbp) { + + } +#endif /* PLATFORM_USB_USE_USB1 */ + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + + /* Post reset initialization.*/ + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + + (void)usbp; + +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + + (void)usbp; + +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + + return EP_STATUS_DISABLED; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + + return EP_STATUS_DISABLED; +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + + (void)usbp; + (void)ep; + (void)buf; + +} + +/** + * @brief Prepares for a receive operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Prepares for a transmit operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; + +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/templates/usb_lld.h b/os/hal/templates/usb_lld.h new file mode 100644 index 000000000..7dbf8b4b9 --- /dev/null +++ b/os/hal/templates/usb_lld.h @@ -0,0 +1,365 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/usb_lld.h + * @brief USB Driver subsystem low level driver header template. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS 4 + +/** + * @brief The address can be changed immediately upon packet reception. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief USB driver enable switch. + * @details If set to @p TRUE the support for USB1 is included. + */ +#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__) +#define PLATFORM_USB_USE_USB1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t txqueued; + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + union { + struct { + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; + } linear; + struct { + /** + * @brief Pointer to the output queue. + */ + OutputQueue *txqueue; + } queue; + } mode; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t rxqueued; + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + union { + struct { + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; + } linear; + struct { + /** + * @brief Pointer to the input queue. + */ + InputQueue *rxqueue; + } queue; + } mode; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if PLATFORM_USB_USE_USB1 && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/os/kernel/include/ch.h b/os/kernel/include/ch.h new file mode 100644 index 000000000..db7c45501 --- /dev/null +++ b/os/kernel/include/ch.h @@ -0,0 +1,143 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ch.h + * @brief ChibiOS/RT main include file. + * @details This header includes all the required kernel headers so it is the + * only kernel header you usually want to include in your application. + * + * @addtogroup kernel_info + * @details Kernel related info. + * @{ + */ + +#ifndef _CH_H_ +#define _CH_H_ + +/** + * @brief ChibiOS/RT identification macro. + */ +#define _CHIBIOS_RT_ + +/** + * @brief Kernel version string. + */ +#define CH_KERNEL_VERSION "2.7.0unstable" + +/** + * @name Kernel version + * @{ + */ +/** + * @brief Kernel version major number. + */ +#define CH_KERNEL_MAJOR 2 + +/** + * @brief Kernel version minor number. + */ +#define CH_KERNEL_MINOR 7 + +/** + * @brief Kernel version patch number. + */ +#define CH_KERNEL_PATCH 0 +/** @} */ + +/** + * @name Common constants + */ +/** + * @brief Generic 'false' boolean constant. + */ +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +/** + * @brief Generic 'true' boolean constant. + */ +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE (!FALSE) +#endif + +/** + * @brief Generic success constant. + * @details This constant is functionally equivalent to @p FALSE but more + * readable, it can be used as return value of all those functions + * returning a @p bool_t as a status indicator. + */ +#if !defined(CH_SUCCESS) || defined(__DOXYGEN__) +#define CH_SUCCESS FALSE +#endif + +/** + * @brief Generic failure constant. + * @details This constant is functionally equivalent to @p TRUE but more + * readable, it can be used as return value of all those functions + * returning a @p bool_t as a status indicator. + */ +#if !defined(CH_FAILED) || defined(__DOXYGEN__) +#define CH_FAILED TRUE +#endif +/** @} */ + +#include "chconf.h" +#include "chtypes.h" +#include "chlists.h" +#include "chcore.h" +#include "chsys.h" +#include "chvt.h" +#include "chschd.h" +#include "chsem.h" +#include "chbsem.h" +#include "chmtx.h" +#include "chcond.h" +#include "chevents.h" +#include "chmsg.h" +#include "chmboxes.h" +#include "chmemcore.h" +#include "chheap.h" +#include "chmempools.h" +#include "chthreads.h" +#include "chdynamic.h" +#include "chregistry.h" +#include "chinline.h" +#include "chqueues.h" +#include "chstreams.h" +#include "chfiles.h" +#include "chdebug.h" + +#if !defined(__DOXYGEN__) +extern WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _idle_thread(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _CH_H_ */ + +/** @} */ diff --git a/os/kernel/include/chbsem.h b/os/kernel/include/chbsem.h new file mode 100644 index 000000000..856a3c3b3 --- /dev/null +++ b/os/kernel/include/chbsem.h @@ -0,0 +1,251 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chbsem.h + * @brief Binary semaphores structures and macros. + * + * @addtogroup binary_semaphores + * @details Binary semaphores related APIs and services. + * + *

    Operation mode

    + * Binary semaphores are implemented as a set of macros that use the + * existing counting semaphores primitives. The difference between + * counting and binary semaphores is that the counter of binary + * semaphores is not allowed to grow above the value 1. Repeated + * signal operation are ignored. A binary semaphore can thus have + * only two defined states: + * - Taken, when its counter has a value of zero or lower + * than zero. A negative number represent the number of threads + * queued on the binary semaphore. + * - Not taken, when its counter has a value of one. + * . + * Binary semaphores are different from mutexes because there is no + * the concept of ownership, a binary semaphore can be taken by a + * thread and signaled by another thread or an interrupt handler, + * mutexes can only be taken and released by the same thread. Another + * difference is that binary semaphores, unlike mutexes, do not + * implement the priority inheritance protocol.
    + * In order to use the binary semaphores APIs the @p CH_USE_SEMAPHORES + * option must be enabled in @p chconf.h. + * @{ + */ + +#ifndef _CHBSEM_H_ +#define _CHBSEM_H_ + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +/** + * @extends Semaphore + * + * @brief Binary semaphore type. + */ +typedef struct { + Semaphore bs_sem; +} BinarySemaphore; + +/** + * @brief Data part of a static semaphore initializer. + * @details This macro should be used when statically initializing a semaphore + * that is part of a bigger structure. + * + * @param[in] name the name of the semaphore variable + * @param[in] taken the semaphore initial state + */ +#define _BSEMAPHORE_DATA(name, taken) \ + {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))} + +/** + * @brief Static semaphore initializer. + * @details Statically initialized semaphores require no explicit + * initialization using @p chSemInit(). + * + * @param[in] name the name of the semaphore variable + * @param[in] taken the semaphore initial state + */ +#define BSEMAPHORE_DECL(name, taken) \ + BinarySemaphore name = _BSEMAPHORE_DATA(name, taken) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Initializes a binary semaphore. + * + * @param[out] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken initial state of the binary semaphore: + * - @a FALSE, the initial state is not taken. + * - @a TRUE, the initial state is taken. + * . + * + * @init + */ +#define chBSemInit(bsp, taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @api + */ +#define chBSemWait(bsp) chSemWait(&(bsp)->bs_sem) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @sclass + */ +#define chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset + * within the specified timeout. + * + * @api + */ +#define chBSemWaitTimeout(bsp, time) chSemWaitTimeout(&(bsp)->bs_sem, (time)) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset + * within the specified timeout. + * + * @sclass + */ +#define chBSemWaitTimeoutS(bsp, time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time)) + +/** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p bsemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @api + */ +#define chBSemReset(bsp, taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p bsemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * @note This function does not reschedule. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @iclass + */ +#define chBSemResetI(bsp, taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Performs a signal operation on a binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * + * @api + */ +#define chBSemSignal(bsp) { \ + chSysLock(); \ + chBSemSignalI((bsp)); \ + chSchRescheduleS(); \ + chSysUnlock(); \ +} + +/** + * @brief Performs a signal operation on a binary semaphore. + * @note This function does not reschedule. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * + * @iclass + */ +#define chBSemSignalI(bsp) { \ + if ((bsp)->bs_sem.s_cnt < 1) \ + chSemSignalI(&(bsp)->bs_sem); \ +} + +/** + * @brief Returns the binary semaphore current state. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return The binary semaphore current state. + * @retval FALSE if the binary semaphore is not taken. + * @retval TRUE if the binary semaphore is taken. + * + * @iclass + */ +#define chBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE) +/** @} */ + +#endif /* CH_USE_SEMAPHORES */ + +#endif /* _CHBSEM_H_ */ + +/** @} */ diff --git a/os/kernel/include/chcond.h b/os/kernel/include/chcond.h new file mode 100644 index 000000000..7557243cd --- /dev/null +++ b/os/kernel/include/chcond.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Leon Woestenberg. + */ + +/** + * @file chcond.h + * @brief Condition Variables macros and structures. + * + * @addtogroup condvars + * @{ + */ + +#ifndef _CHCOND_H_ +#define _CHCOND_H_ + +#if CH_USE_CONDVARS || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_MUTEXES +#error "CH_USE_CONDVARS requires CH_USE_MUTEXES" +#endif + +/** + * @brief CondVar structure. + */ +typedef struct CondVar { + ThreadsQueue c_queue; /**< @brief CondVar threads queue.*/ +} CondVar; + +#ifdef __cplusplus +extern "C" { +#endif + void chCondInit(CondVar *cp); + void chCondSignal(CondVar *cp); + void chCondSignalI(CondVar *cp); + void chCondBroadcast(CondVar *cp); + void chCondBroadcastI(CondVar *cp); + msg_t chCondWait(CondVar *cp); + msg_t chCondWaitS(CondVar *cp); +#if CH_USE_CONDVARS_TIMEOUT + msg_t chCondWaitTimeout(CondVar *cp, systime_t time); + msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static condition variable initializer. + * @details This macro should be used when statically initializing a condition + * variable that is part of a bigger structure. + * + * @param[in] name the name of the condition variable + */ +#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)} + +/** + * @brief Static condition variable initializer. + * @details Statically initialized condition variables require no explicit + * initialization using @p chCondInit(). + * + * @param[in] name the name of the condition variable + */ +#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name) + +#endif /* CH_USE_CONDVARS */ + +#endif /* _CHCOND_H_ */ + +/** @} */ diff --git a/os/kernel/include/chdebug.h b/os/kernel/include/chdebug.h new file mode 100644 index 000000000..4a75474e2 --- /dev/null +++ b/os/kernel/include/chdebug.h @@ -0,0 +1,247 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chdebug.h + * @brief Debug macros and structures. + * + * @addtogroup debug + * @{ + */ + +#ifndef _CHDEBUG_H_ +#define _CHDEBUG_H_ + +#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || \ + CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK +#define CH_DBG_ENABLED TRUE +#else +#define CH_DBG_ENABLED FALSE +#endif + +#define __QUOTE_THIS(p) #p + +/*===========================================================================*/ +/** + * @name Debug related settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Trace buffer entries. + */ +#ifndef CH_TRACE_BUFFER_SIZE +#define CH_TRACE_BUFFER_SIZE 64 +#endif + +/** + * @brief Fill value for thread stack area in debug mode. + */ +#ifndef CH_STACK_FILL_VALUE +#define CH_STACK_FILL_VALUE 0x55 +#endif + +/** + * @brief Fill value for thread area in debug mode. + * @note The chosen default value is 0xFF in order to make evident which + * thread fields were not initialized when inspecting the memory with + * a debugger. A uninitialized field is not an error in itself but it + * better to know it. + */ +#ifndef CH_THREAD_FILL_VALUE +#define CH_THREAD_FILL_VALUE 0xFF +#endif + +/** @} */ + +/*===========================================================================*/ +/* System state checker related code and variables. */ +/*===========================================================================*/ + +#if !CH_DBG_SYSTEM_STATE_CHECK +#define dbg_enter_lock() +#define dbg_leave_lock() +#define dbg_check_disable() +#define dbg_check_suspend() +#define dbg_check_enable() +#define dbg_check_lock() +#define dbg_check_unlock() +#define dbg_check_lock_from_isr() +#define dbg_check_unlock_from_isr() +#define dbg_check_enter_isr() +#define dbg_check_leave_isr() +#define chDbgCheckClassI(); +#define chDbgCheckClassS(); +#else +#define dbg_enter_lock() (dbg_lock_cnt = 1) +#define dbg_leave_lock() (dbg_lock_cnt = 0) +#endif + +/*===========================================================================*/ +/* Trace related structures and macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) +/** + * @brief Trace buffer record. + */ +typedef struct { + systime_t se_time; /**< @brief Time of the switch event. */ + Thread *se_tp; /**< @brief Switched in thread. */ + void *se_wtobjp; /**< @brief Object where going to sleep.*/ + uint8_t se_state; /**< @brief Switched out thread state. */ +} ch_swc_event_t; + +/** + * @brief Trace buffer header. + */ +typedef struct { + unsigned tb_size; /**< @brief Trace buffer size (entries).*/ + ch_swc_event_t *tb_ptr; /**< @brief Pointer to the buffer front.*/ + /** @brief Ring buffer.*/ + ch_swc_event_t tb_buffer[CH_TRACE_BUFFER_SIZE]; +} ch_trace_buffer_t; + +#if !defined(__DOXYGEN__) +extern ch_trace_buffer_t dbg_trace_buffer; +#endif + +#endif /* CH_DBG_ENABLE_TRACE */ + +#if !CH_DBG_ENABLE_TRACE +/* When the trace feature is disabled this function is replaced by an empty + macro.*/ +#define dbg_trace(otp) +#endif + +/*===========================================================================*/ +/* Parameters checking related macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_CHECKS || defined(__DOXYGEN__) +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Function parameters check. + * @details If the condition check fails then the kernel panics and halts. + * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch + * is specified in @p chconf.h else the macro does nothing. + * + * @param[in] c the condition to be verified to be true + * @param[in] func the undecorated function name + * + * @api + */ +#if !defined(chDbgCheck) +#define chDbgCheck(c, func) { \ + if (!(c)) \ + chDbgPanic(__QUOTE_THIS(func)"()"); \ +} +#endif /* !defined(chDbgCheck) */ +/** @} */ +#else /* !CH_DBG_ENABLE_CHECKS */ +#define chDbgCheck(c, func) { \ + (void)(c), (void)__QUOTE_THIS(func)"()"; \ +} +#endif /* !CH_DBG_ENABLE_CHECKS */ + +/*===========================================================================*/ +/* Assertions related macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__) +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Condition assertion. + * @details If the condition check fails then the kernel panics with the + * specified message and halts. + * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch + * is specified in @p chconf.h else the macro does nothing. + * @note The convention for the message is the following:
    + * @(), #@ + * @note The remark string is not currently used except for putting a + * comment in the code about the assertion. + * + * @param[in] c the condition to be verified to be true + * @param[in] m the text message + * @param[in] r a remark string + * + * @api + */ +#if !defined(chDbgAssert) +#define chDbgAssert(c, m, r) { \ + if (!(c)) \ + chDbgPanic(m); \ +} +#endif /* !defined(chDbgAssert) */ +/** @} */ +#else /* !CH_DBG_ENABLE_ASSERTS */ +#define chDbgAssert(c, m, r) {(void)(c);} +#endif /* !CH_DBG_ENABLE_ASSERTS */ + +/*===========================================================================*/ +/* Panic related macros. */ +/*===========================================================================*/ + +#if !CH_DBG_ENABLED +/* When the debug features are disabled this function is replaced by an empty + macro.*/ +#define chDbgPanic(msg) {} +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + extern cnt_t dbg_isr_cnt; + extern cnt_t dbg_lock_cnt; + void dbg_check_disable(void); + void dbg_check_suspend(void); + void dbg_check_enable(void); + void dbg_check_lock(void); + void dbg_check_unlock(void); + void dbg_check_lock_from_isr(void); + void dbg_check_unlock_from_isr(void); + void dbg_check_enter_isr(void); + void dbg_check_leave_isr(void); + void chDbgCheckClassI(void); + void chDbgCheckClassS(void); +#endif +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) + void _trace_init(void); + void dbg_trace(Thread *otp); +#endif +#if CH_DBG_ENABLED + extern const char *dbg_panic_msg; + void chDbgPanic(const char *msg); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _CHDEBUG_H_ */ + +/** @} */ diff --git a/os/kernel/include/chdynamic.h b/os/kernel/include/chdynamic.h new file mode 100644 index 000000000..3ac79a5f4 --- /dev/null +++ b/os/kernel/include/chdynamic.h @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chdynamic.h + * @brief Dynamic threads macros and structures. + * + * @addtogroup dynamic_threads + * @{ + */ + +#ifndef _CHDYNAMIC_H_ +#define _CHDYNAMIC_H_ + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT +#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT" +#endif +#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS +#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS" +#endif + +/* + * Dynamic threads APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + Thread *chThdAddRef(Thread *tp); + void chThdRelease(Thread *tp); +#if CH_USE_HEAP + Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); +#endif +#if CH_USE_MEMPOOLS + Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, + tfunc_t pf, void *arg); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_DYNAMIC */ + +#endif /* _CHDYNAMIC_H_ */ + +/** @} */ diff --git a/os/kernel/include/chevents.h b/os/kernel/include/chevents.h new file mode 100644 index 000000000..ec5c1cb93 --- /dev/null +++ b/os/kernel/include/chevents.h @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Scott (skute). + */ + +/** + * @file chevents.h + * @brief Events macros and structures. + * + * @addtogroup events + * @{ + */ + +#ifndef _CHEVENTS_H_ +#define _CHEVENTS_H_ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + +typedef struct EventListener EventListener; + +/** + * @brief Event Listener structure. + */ +struct EventListener { + EventListener *el_next; /**< @brief Next Event Listener + registered on the Event + Source. */ + Thread *el_listener; /**< @brief Thread interested in the + Event Source. */ + eventmask_t el_mask; /**< @brief Event flags mask associated + by the thread to the Event + Source. */ + flagsmask_t el_flags; /**< @brief Flags added to the listener + by the event source.*/ +}; + +/** + * @brief Event Source structure. + */ +typedef struct EventSource { + EventListener *es_next; /**< @brief First Event Listener + registered on the Event + Source. */ +} EventSource; + +/** + * @brief Event Handler callback function. + */ +typedef void (*evhandler_t)(eventid_t); + +/** + * @brief Data part of a static event source initializer. + * @details This macro should be used when statically initializing an event + * source that is part of a bigger structure. + * @param name the name of the event source variable + */ +#define _EVENTSOURCE_DATA(name) {(void *)(&name)} + +/** + * @brief Static event source initializer. + * @details Statically initialized event sources require no explicit + * initialization using @p chEvtInit(). + * + * @param name the name of the event source variable + */ +#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) + +/** + * @brief All events allowed mask. + */ +#define ALL_EVENTS ((eventmask_t)-1) + +/** + * @brief Returns an event mask from an event identifier. + */ +#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Registers an Event Listener on an Event Source. + * @note Multiple Event Listeners can use the same event identifier, the + * listener will share the callback function. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[out] elp pointer to the @p EventListener structure + * @param[in] eid numeric identifier assigned to the Event Listener. The + * identifier is used as index for the event callback + * function. + * The value must range between zero and the size, in bit, + * of the @p eventid_t type minus one. + * + * @api + */ +#define chEvtRegister(esp, elp, eid) \ + chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) + +/** + * @brief Initializes an Event Source. + * @note This function can be invoked before the kernel is initialized + * because it just prepares a @p EventSource structure. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @init + */ +#define chEvtInit(esp) \ + ((esp)->es_next = (EventListener *)(void *)(esp)) + +/** + * @brief Verifies if there is at least one @p EventListener registered. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @iclass + */ +#define chEvtIsListeningI(esp) \ + ((void *)(esp) != (void *)(esp)->es_next) + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @api + */ +#define chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0) + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @iclass + */ +#define chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + void chEvtRegisterMask(EventSource *esp, + EventListener *elp, + eventmask_t mask); + void chEvtUnregister(EventSource *esp, EventListener *elp); + eventmask_t chEvtGetAndClearEvents(eventmask_t mask); + eventmask_t chEvtAddEvents(eventmask_t mask); + flagsmask_t chEvtGetAndClearFlags(EventListener *elp); + flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp); + void chEvtSignal(Thread *tp, eventmask_t mask); + void chEvtSignalI(Thread *tp, eventmask_t mask); + void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags); + void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags); + void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask); +#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT + eventmask_t chEvtWaitOne(eventmask_t mask); + eventmask_t chEvtWaitAny(eventmask_t mask); + eventmask_t chEvtWaitAll(eventmask_t mask); +#endif +#if CH_USE_EVENTS_TIMEOUT + eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time); + eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time); + eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time); +#endif +#ifdef __cplusplus +} +#endif + +#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT +#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE) +#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE) +#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE) +#endif + +#endif /* CH_USE_EVENTS */ + +#endif /* _CHEVENTS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chfiles.h b/os/kernel/include/chfiles.h new file mode 100644 index 000000000..ad2974ad8 --- /dev/null +++ b/os/kernel/include/chfiles.h @@ -0,0 +1,165 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chfiles.h + * @brief Data files. + * @details This header defines abstract interfaces useful to access generic + * data files in a standardized way. + * + * @addtogroup data_files + * @details This module define an abstract interface for generic data files by + * extending the @p BaseSequentialStream interface. Note that no code + * is present, data files are just abstract interface-like structures, + * you should look at the systems as to a set of abstract C++ classes + * (even if written in C). This system has the advantage to make the + * access to streams independent from the implementation logic.
    + * The data files interface can be used as base class for high level + * object types such as an API for a File System implementation. + * @{ + */ + +#ifndef _CHFILES_H_ +#define _CHFILES_H_ + +/** + * @brief No error return code. + */ +#define FILE_OK 0 + +/** + * @brief Error code from the file stream methods. + */ +#define FILE_ERROR 0xFFFFFFFFUL + +/** + * @brief File offset type. + */ +typedef uint32_t fileoffset_t; + +/** + * @brief BaseFileStream specific methods. + */ +#define _base_file_stream_methods \ + _base_sequential_stream_methods \ + /* File close method.*/ \ + uint32_t (*close)(void *instance); \ + /* Get last error code method.*/ \ + int (*geterror)(void *instance); \ + /* File get size method.*/ \ + fileoffset_t (*getsize)(void *instance); \ + /* File get current position method.*/ \ + fileoffset_t (*getposition)(void *instance); \ + /* File seek method.*/ \ + uint32_t (*lseek)(void *instance, fileoffset_t offset); + +/** + * @brief @p BaseFileStream specific data. + * @note It is empty because @p BaseFileStream is only an interface + * without implementation. + */ +#define _base_file_stream_data \ + _base_sequential_stream_data + +/** + * @extends BaseSequentialStreamVMT + * + * @brief @p BaseFileStream virtual methods table. + */ +struct BaseFileStreamVMT { + _base_file_stream_methods +}; + +/** + * @extends BaseSequentialStream + * + * @brief Base file stream class. + * @details This class represents a generic file data stream. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseFileStreamVMT *vmt; + _base_file_stream_data +} BaseFileStream; + +/** + * @name Macro Functions (BaseFileStream) + * @{ + */ +/** + * @brief Base file Stream close. + * @details The function closes a file stream. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The operation status. + * @retval FILE_OK no error. + * @retval FILE_ERROR operation failed. + * + * @api + */ +#define chFileStreamClose(ip) ((ip)->vmt->close(ip)) + +/** + * @brief Returns an implementation dependent error code. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return Implementation dependent error code. + * + * @api + */ +#define chFileStreamGetError(ip) ((ip)->vmt->geterror(ip)) + +/** + * @brief Returns the current file size. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The file size. + * + * @api + */ +#define chFileStreamGetSize(ip) ((ip)->vmt->getsize(ip)) + +/** + * @brief Returns the current file pointer position. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The current position inside the file. + * + * @api + */ +#define chFileStreamGetPosition(ip) ((ip)->vmt->getposition(ip)) + +/** + * @brief Moves the file current pointer to an absolute position. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @param[in] offset new absolute position + * @return The operation status. + * @retval FILE_OK no error. + * @retval FILE_ERROR operation failed. + * + * @api + */ +#define chFileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset)) +/** @} */ + +#endif /* _CHFILES_H_ */ + +/** @} */ diff --git a/os/kernel/include/chheap.h b/os/kernel/include/chheap.h new file mode 100644 index 000000000..8a54d7290 --- /dev/null +++ b/os/kernel/include/chheap.h @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chheap.h + * @brief Heaps macros and structures. + * + * @addtogroup heaps + * @{ + */ + +#ifndef _CHHEAP_H_ +#define _CHHEAP_H_ + +#if CH_USE_HEAP || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP +#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP" +#endif + +#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +typedef struct memory_heap MemoryHeap; + +/** + * @brief Memory heap block header. + */ +union heap_header { + stkalign_t align; + struct { + union { + union heap_header *next; /**< @brief Next block in free list. */ + MemoryHeap *heap; /**< @brief Block owner heap. */ + } u; /**< @brief Overlapped fields. */ + size_t size; /**< @brief Size of the memory block. */ + } h; +}; + +/** + * @brief Structure describing a memory heap. + */ +struct memory_heap { + memgetfunc_t h_provider; /**< @brief Memory blocks provider for + this heap. */ + union heap_header h_free; /**< @brief Free blocks list header. */ +#if CH_USE_MUTEXES + Mutex h_mtx; /**< @brief Heap access mutex. */ +#else + Semaphore h_sem; /**< @brief Heap access semaphore. */ +#endif +}; + +#ifdef __cplusplus +extern "C" { +#endif + void _heap_init(void); +#if !CH_USE_MALLOC_HEAP + void chHeapInit(MemoryHeap *heapp, void *buf, size_t size); +#endif + void *chHeapAlloc(MemoryHeap *heapp, size_t size); + void chHeapFree(void *p); + size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_HEAP */ + +#endif /* _CHHEAP_H_ */ + +/** @} */ diff --git a/os/kernel/include/chinline.h b/os/kernel/include/chinline.h new file mode 100644 index 000000000..46ac45a84 --- /dev/null +++ b/os/kernel/include/chinline.h @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chinline.h + * @brief Kernel inlined functions. + * @details In this file there are a set of inlined functions if the + * @p CH_OPTIMIZE_SPEED is enabled. + */ + +#ifndef _CHINLINE_H_ +#define _CHINLINE_H_ + +/* If the performance code path has been chosen then all the following + functions are inlined into the various kernel modules.*/ +#if CH_OPTIMIZE_SPEED +static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) { + + Thread *cp = (Thread *)tqp; + do { + cp = cp->p_next; + } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; +} + +static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) { + + tp->p_next = (Thread *)tqp; + tp->p_prev = tqp->p_prev; + tp->p_prev->p_next = tqp->p_prev = tp; +} + +static INLINE Thread *fifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_next; + + (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; + return tp; +} + +static INLINE Thread *lifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_prev; + + (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; + return tp; +} + +static INLINE Thread *dequeue(Thread *tp) { + + tp->p_prev->p_next = tp->p_next; + tp->p_next->p_prev = tp->p_prev; + return tp; +} + +static INLINE void list_insert(Thread *tp, ThreadsList *tlp) { + + tp->p_next = tlp->p_next; + tlp->p_next = tp; +} + +static INLINE Thread *list_remove(ThreadsList *tlp) { + + Thread *tp = tlp->p_next; + tlp->p_next = tp->p_next; + return tp; +} +#endif /* CH_OPTIMIZE_SPEED */ + +#endif /* _CHINLINE_H_ */ diff --git a/os/kernel/include/chlists.h b/os/kernel/include/chlists.h new file mode 100644 index 000000000..caf2560b4 --- /dev/null +++ b/os/kernel/include/chlists.h @@ -0,0 +1,127 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chlists.h + * @brief Thread queues/lists macros and structures. + * @note All the macros present in this module, while public, are not + * an OS API and should not be directly used in the user applications + * code. + * + * @addtogroup internals + * @{ + */ + +#ifndef _CHLISTS_H_ +#define _CHLISTS_H_ + +typedef struct Thread Thread; + +/** + * @brief Threads queue initialization. + * + * @notapi + */ +#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); + +/** + * @brief Threads list initialization. + * + * @notapi + */ +#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) + +/** + * @brief Evaluates to @p TRUE if the specified threads queue or list is + * empty. + * + * @notapi + */ +#define isempty(p) ((p)->p_next == (Thread *)(p)) + +/** + * @brief Evaluates to @p TRUE if the specified threads queue or list is + * not empty. + * + * @notapi + */ +#define notempty(p) ((p)->p_next != (Thread *)(p)) + +/** + * @brief Data part of a static threads queue initializer. + * @details This macro should be used when statically initializing a threads + * queue that is part of a bigger structure. + * + * @param[in] name the name of the threads queue variable + */ +#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} + +/** + * @brief Static threads queue initializer. + * @details Statically initialized threads queues require no explicit + * initialization using @p queue_init(). + * + * @param[in] name the name of the threads queue variable + */ +#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) + +/** + * @extends ThreadsList + * + * @brief Generic threads bidirectional linked list header and element. + */ +typedef struct { + Thread *p_next; /**< First @p Thread in the queue, or + @p ThreadQueue when empty. */ + Thread *p_prev; /**< Last @p Thread in the queue, or + @p ThreadQueue when empty. */ +} ThreadsQueue; + +/** + * @brief Generic threads single link list, it works like a stack. + */ +typedef struct { + + Thread *p_next; /**< Last pushed @p Thread on the stack + list, or pointer to itself if + empty. */ +} ThreadsList; + +#if !CH_OPTIMIZE_SPEED + +#ifdef __cplusplus +extern "C" { +#endif + void prio_insert(Thread *tp, ThreadsQueue *tqp); + void queue_insert(Thread *tp, ThreadsQueue *tqp); + Thread *fifo_remove(ThreadsQueue *tqp); + Thread *lifo_remove(ThreadsQueue *tqp); + Thread *dequeue(Thread *tp); + void list_insert(Thread *tp, ThreadsList *tlp); + Thread *list_remove(ThreadsList *tlp); +#ifdef __cplusplus +} +#endif + +#endif /* !CH_OPTIMIZE_SPEED */ + +#endif /* _CHLISTS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chmboxes.h b/os/kernel/include/chmboxes.h new file mode 100644 index 000000000..85192e804 --- /dev/null +++ b/os/kernel/include/chmboxes.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmboxes.h + * @brief Mailboxes macros and structures. + * + * @addtogroup mailboxes + * @{ + */ + +#ifndef _CHMBOXES_H_ +#define _CHMBOXES_H_ + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_SEMAPHORES +#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES" +#endif + +/** + * @brief Structure representing a mailbox object. + */ +typedef struct { + msg_t *mb_buffer; /**< @brief Pointer to the mailbox + buffer. */ + msg_t *mb_top; /**< @brief Pointer to the location + after the buffer. */ + msg_t *mb_wrptr; /**< @brief Write pointer. */ + msg_t *mb_rdptr; /**< @brief Read pointer. */ + Semaphore mb_fullsem; /**< @brief Full counter + @p Semaphore. */ + Semaphore mb_emptysem; /**< @brief Empty counter + @p Semaphore. */ +} Mailbox; + +#ifdef __cplusplus +extern "C" { +#endif + void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n); + void chMBReset(Mailbox *mbp); + msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostI(Mailbox *mbp, msg_t msg); + msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg); + msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout); + msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout); + msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp); +#ifdef __cplusplus +} +#endif + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the mailbox buffer size. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * + * @iclass + */ +#define chMBSizeI(mbp) \ + ((mbp)->mb_top - (mbp)->mb_buffer) + +/** + * @brief Returns the number of free message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a locked + * state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @return The number of empty message slots. + * + * @iclass + */ +#define chMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem) + +/** + * @brief Returns the number of used message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a locked + * state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @return The number of queued messages. + * + * @iclass + */ +#define chMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem) + +/** + * @brief Returns the next message in the queue without removing it. + * @pre A message must be waiting in the queue for this function to work + * or it would return garbage. The correct way to use this macro is + * to use @p chMBGetFullCountI() and then use this macro, all within + * a lock state. + * + * @iclass + */ +#define chMBPeekI(mbp) (*(mbp)->mb_rdptr) +/** @} */ + +/** + * @brief Data part of a static mailbox initializer. + * @details This macro should be used when statically initializing a + * mailbox that is part of a bigger structure. + * + * @param[in] name the name of the mailbox variable + * @param[in] buffer pointer to the mailbox buffer area + * @param[in] size size of the mailbox buffer area + */ +#define _MAILBOX_DATA(name, buffer, size) { \ + (msg_t *)(buffer), \ + (msg_t *)(buffer) + size, \ + (msg_t *)(buffer), \ + (msg_t *)(buffer), \ + _SEMAPHORE_DATA(name.mb_fullsem, 0), \ + _SEMAPHORE_DATA(name.mb_emptysem, size), \ +} + +/** + * @brief Static mailbox initializer. + * @details Statically initialized mailboxes require no explicit + * initialization using @p chMBInit(). + * + * @param[in] name the name of the mailbox variable + * @param[in] buffer pointer to the mailbox buffer area + * @param[in] size size of the mailbox buffer area + */ +#define MAILBOX_DECL(name, buffer, size) \ + Mailbox name = _MAILBOX_DATA(name, buffer, size) + +#endif /* CH_USE_MAILBOXES */ + +#endif /* _CHMBOXES_H_ */ + +/** @} */ diff --git a/os/kernel/include/chmemcore.h b/os/kernel/include/chmemcore.h new file mode 100644 index 000000000..4f75bd043 --- /dev/null +++ b/os/kernel/include/chmemcore.h @@ -0,0 +1,86 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmemcore.h + * @brief Core memory manager macros and structures. + * + * @addtogroup memcore + * @{ + */ + +#ifndef _CHMEMCORE_H_ +#define _CHMEMCORE_H_ + +/** + * @brief Memory get function. + * @note This type must be assignment compatible with the @p chMemAlloc() + * function. + */ +typedef void *(*memgetfunc_t)(size_t size); + +/** + * @name Alignment support macros + */ +/** + * @brief Alignment size constant. + */ +#define MEM_ALIGN_SIZE sizeof(stkalign_t) + +/** + * @brief Alignment mask constant. + */ +#define MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1) + +/** + * @brief Alignment helper macro. + */ +#define MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) + +/** + * @brief Alignment helper macro. + */ +#define MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) + +/** + * @brief Returns whatever a pointer or memory size is aligned to + * the type @p align_t. + */ +#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) +/** @} */ + +#if CH_USE_MEMCORE || defined(__DOXYGEN__) + +#ifdef __cplusplus +extern "C" { +#endif + void _core_init(void); + void *chCoreAlloc(size_t size); + void *chCoreAllocI(size_t size); + size_t chCoreStatus(void); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MEMCORE */ + +#endif /* _CHMEMCORE_H_ */ + +/** @} */ diff --git a/os/kernel/include/chmempools.h b/os/kernel/include/chmempools.h new file mode 100644 index 000000000..80d6eeaf2 --- /dev/null +++ b/os/kernel/include/chmempools.h @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmempools.h + * @brief Memory Pools macros and structures. + * + * @addtogroup pools + * @{ + */ + +#ifndef _CHMEMPOOLS_H_ +#define _CHMEMPOOLS_H_ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + +/** + * @brief Memory pool free object header. + */ +struct pool_header { + struct pool_header *ph_next; /**< @brief Pointer to the next pool + header in the list. */ +}; + +/** + * @brief Memory pool descriptor. + */ +typedef struct { + struct pool_header *mp_next; /**< @brief Pointer to the header. */ + size_t mp_object_size; /**< @brief Memory pool objects + size. */ + memgetfunc_t mp_provider; /**< @brief Memory blocks provider for + this pool. */ +} MemoryPool; + +/** + * @brief Data part of a static memory pool initializer. + * @details This macro should be used when statically initializing a + * memory pool that is part of a bigger structure. + * + * @param[in] name the name of the memory pool variable + * @param[in] size size of the memory pool contained objects + * @param[in] provider memory provider function for the memory pool + */ +#define _MEMORYPOOL_DATA(name, size, provider) \ + {NULL, size, provider} + +/** + * @brief Static memory pool initializer in hungry mode. + * @details Statically initialized memory pools require no explicit + * initialization using @p chPoolInit(). + * + * @param[in] name the name of the memory pool variable + * @param[in] size size of the memory pool contained objects + * @param[in] provider memory provider function for the memory pool or @p NULL + * if the pool is not allowed to grow automatically + */ +#define MEMORYPOOL_DECL(name, size, provider) \ + MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Adds an object to a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The added object must be of the right size for the specified + * memory pool. + * @pre The added object must be memory aligned to the size of + * @p stkalign_t type. + * @note This function is just an alias for @p chPoolFree() and has been + * added for clarity. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be added + * + * @api + */ +#define chPoolAdd(mp, objp) chPoolFree(mp, objp) + +/** + * @brief Adds an object to a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The added object must be of the right size for the specified + * memory pool. + * @pre The added object must be memory aligned to the size of + * @p stkalign_t type. + * @note This function is just an alias for @p chPoolFree() and has been + * added for clarity. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be added + * + * @iclass + */ +#define chPoolAddI(mp, objp) chPoolFreeI(mp, objp) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider); + void chPoolLoadArray(MemoryPool *mp, void *p, size_t n); + void *chPoolAllocI(MemoryPool *mp); + void *chPoolAlloc(MemoryPool *mp); + void chPoolFreeI(MemoryPool *mp, void *objp); + void chPoolFree(MemoryPool *mp, void *objp); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MEMPOOLS */ + +#endif /* _CHMEMPOOLS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chmsg.h b/os/kernel/include/chmsg.h new file mode 100644 index 000000000..e613a6aad --- /dev/null +++ b/os/kernel/include/chmsg.h @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmsg.h + * @brief Messages macros and structures. + * + * @addtogroup messages + * @{ + */ + +#ifndef _CHMSG_H_ +#define _CHMSG_H_ + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Evaluates to TRUE if the thread has pending messages. + * + * @iclass + */ +#define chMsgIsPendingI(tp) \ + ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue) + +/** + * @brief Returns the message carried by the specified thread. + * @pre This function must be invoked immediately after exiting a call + * to @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @return The message carried by the sender. + * + * @api + */ +#define chMsgGet(tp) ((tp)->p_msg) + +/** + * @brief Releases the thread waiting on top of the messages queue. + * @pre Invoke this function only after a message has been received + * using @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @param[in] msg message to be returned to the sender + * + * @sclass + */ +#define chMsgReleaseS(tp, msg) chSchWakeupS(tp, msg) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + msg_t chMsgSend(Thread *tp, msg_t msg); + Thread * chMsgWait(void); + void chMsgRelease(Thread *tp, msg_t msg); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MESSAGES */ + +#endif /* _CHMSG_H_ */ + +/** @} */ diff --git a/os/kernel/include/chmtx.h b/os/kernel/include/chmtx.h new file mode 100644 index 000000000..124127a88 --- /dev/null +++ b/os/kernel/include/chmtx.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmtx.h + * @brief Mutexes macros and structures. + * + * @addtogroup mutexes + * @{ + */ + +#ifndef _CHMTX_H_ +#define _CHMTX_H_ + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + +/** + * @brief Mutex structure. + */ +typedef struct Mutex { + ThreadsQueue m_queue; /**< @brief Queue of the threads sleeping + on this Mutex. */ + Thread *m_owner; /**< @brief Owner @p Thread pointer or + @p NULL. */ + struct Mutex *m_next; /**< @brief Next @p Mutex into an + owner-list or @p NULL. */ +} Mutex; + +#ifdef __cplusplus +extern "C" { +#endif + void chMtxInit(Mutex *mp); + void chMtxLock(Mutex *mp); + void chMtxLockS(Mutex *mp); + bool_t chMtxTryLock(Mutex *mp); + bool_t chMtxTryLockS(Mutex *mp); + Mutex *chMtxUnlock(void); + Mutex *chMtxUnlockS(void); + void chMtxUnlockAll(void); +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static mutex initializer. + * @details This macro should be used when statically initializing a mutex + * that is part of a bigger structure. + * + * @param[in] name the name of the mutex variable + */ +#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} + +/** + * @brief Static mutex initializer. + * @details Statically initialized mutexes require no explicit initialization + * using @p chMtxInit(). + * + * @param[in] name the name of the mutex variable + */ +#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns @p TRUE if the mutex queue contains at least a waiting + * thread. + * + * @sclass + */ +#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) +/** @} */ + +#endif /* CH_USE_MUTEXES */ + +#endif /* _CHMTX_H_ */ + +/** @} */ diff --git a/os/kernel/include/chqueues.h b/os/kernel/include/chqueues.h new file mode 100644 index 000000000..507f020d1 --- /dev/null +++ b/os/kernel/include/chqueues.h @@ -0,0 +1,369 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chqueues.h + * @brief I/O Queues macros and structures. + * + * @addtogroup io_queues + * @{ + */ + +#ifndef _CHQUEUES_H_ +#define _CHQUEUES_H_ + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + +/** + * @name Queue functions returned status value + * @{ + */ +#define Q_OK RDY_OK /**< @brief Operation successful. */ +#define Q_TIMEOUT RDY_TIMEOUT /**< @brief Timeout condition. */ +#define Q_RESET RDY_RESET /**< @brief Queue has been reset. */ +#define Q_EMPTY -3 /**< @brief Queue empty. */ +#define Q_FULL -4 /**< @brief Queue full, */ +/** @} */ + +/** + * @brief Type of a generic I/O queue structure. + */ +typedef struct GenericQueue GenericQueue; + +/** @brief Queue notification callback type.*/ +typedef void (*qnotify_t)(GenericQueue *qp); + +/** + * @brief Generic I/O queue structure. + * @details This structure represents a generic Input or Output asymmetrical + * queue. The queue is asymmetrical because one end is meant to be + * accessed from a thread context, and thus can be blocking, the other + * end is accessible from interrupt handlers or from within a kernel + * lock zone (see I-Locked and S-Locked states in + * @ref system_states) and is non-blocking. + */ +struct GenericQueue { + ThreadsQueue q_waiting; /**< @brief Queue of waiting threads. */ + size_t q_counter; /**< @brief Resources counter. */ + uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ + uint8_t *q_top; /**< @brief Pointer to the first location + after the buffer. */ + uint8_t *q_wrptr; /**< @brief Write pointer. */ + uint8_t *q_rdptr; /**< @brief Read pointer. */ + qnotify_t q_notify; /**< @brief Data notification callback. */ + void *q_link; /**< @brief Application defined field. */ +}; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the queue's buffer size. + * + * @param[in] qp pointer to a @p GenericQueue structure. + * @return The buffer size. + * + * @iclass + */ +#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer)) + +/** + * @brief Queue space. + * @details Returns the used space if used on an input queue or the empty + * space if used on an output queue. + * + * @param[in] qp pointer to a @p GenericQueue structure. + * @return The buffer space. + * + * @iclass + */ +#define chQSpaceI(qp) ((qp)->q_counter) + +/** + * @brief Returns the queue application-defined link. + * @note This function can be called in any context. + * + * @param[in] qp pointer to a @p GenericQueue structure. + * @return The application-defined link. + * + * @special + */ +#define chQGetLink(qp) ((qp)->q_link) +/** @} */ + +/** + * @extends GenericQueue + * + * @brief Type of an input queue structure. + * @details This structure represents a generic asymmetrical input queue. + * Writing to the queue is non-blocking and can be performed from + * interrupt handlers or from within a kernel lock zone (see + * I-Locked and S-Locked states in @ref system_states). + * Reading the queue can be a blocking operation and is supposed to + * be performed by a system thread. + */ +typedef GenericQueue InputQueue; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the filled space into an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ +#define chIQGetFullI(iqp) chQSpaceI(iqp) + +/** + * @brief Returns the empty space into an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ +#define chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp)) + +/** + * @brief Evaluates to @p TRUE if the specified input queue is empty. + * + * @param[in] iqp pointer to an @p InputQueue structure. + * @return The queue status. + * @retval FALSE if the queue is not empty. + * @retval TRUE if the queue is empty. + * + * @iclass + */ +#define chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0)) + +/** + * @brief Evaluates to @p TRUE if the specified input queue is full. + * + * @param[in] iqp pointer to an @p InputQueue structure. + * @return The queue status. + * @retval FALSE if the queue is not full. + * @retval TRUE if the queue is full. + * + * @iclass + */ +#define chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && \ + ((iqp)->q_counter != 0))) + +/** + * @brief Input queue read. + * @details This function reads a byte value from an input queue. If the queue + * is empty then the calling thread is suspended until a byte arrives + * in the queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return A byte value from the queue. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) +/** @} */ + +/** + * @brief Data part of a static input queue initializer. + * @details This macro should be used when statically initializing an + * input queue that is part of a bigger structure. + * + * @param[in] name the name of the input queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] inotify input notification callback pointer + * @param[in] link application defined pointer + */ +#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) { \ + _THREADSQUEUE_DATA(name), \ + 0, \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer) + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer), \ + (inotify), \ + (link) \ +} + +/** + * @brief Static input queue initializer. + * @details Statically initialized input queues require no explicit + * initialization using @p chIQInit(). + * + * @param[in] name the name of the input queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] inotify input notification callback pointer + * @param[in] link application defined pointer + */ +#define INPUTQUEUE_DECL(name, buffer, size, inotify, link) \ + InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link) + +/** + * @extends GenericQueue + * + * @brief Type of an output queue structure. + * @details This structure represents a generic asymmetrical output queue. + * Reading from the queue is non-blocking and can be performed from + * interrupt handlers or from within a kernel lock zone (see + * I-Locked and S-Locked states in @ref system_states). + * Writing the queue can be a blocking operation and is supposed to + * be performed by a system thread. + */ +typedef GenericQueue OutputQueue; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the filled space into an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ +#define chOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp)) + +/** + * @brief Returns the empty space into an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ +#define chOQGetEmptyI(oqp) chQSpaceI(oqp) + +/** + * @brief Evaluates to @p TRUE if the specified output queue is empty. + * + * @param[in] oqp pointer to an @p OutputQueue structure. + * @return The queue status. + * @retval FALSE if the queue is not empty. + * @retval TRUE if the queue is empty. + * + * @iclass + */ +#define chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && \ + ((oqp)->q_counter != 0))) + +/** + * @brief Evaluates to @p TRUE if the specified output queue is full. + * + * @param[in] oqp pointer to an @p OutputQueue structure. + * @return The queue status. + * @retval FALSE if the queue is not full. + * @retval TRUE if the queue is full. + * + * @iclass + */ +#define chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0)) + +/** + * @brief Output queue write. + * @details This function writes a byte value to an output queue. If the queue + * is full then the calling thread is suspended until there is space + * in the queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE) + /** @} */ + +/** + * @brief Data part of a static output queue initializer. + * @details This macro should be used when statically initializing an + * output queue that is part of a bigger structure. + * + * @param[in] name the name of the output queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] onotify output notification callback pointer + * @param[in] link application defined pointer + */ +#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) { \ + _THREADSQUEUE_DATA(name), \ + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer) + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer), \ + (onotify), \ + (link) \ +} + +/** + * @brief Static output queue initializer. + * @details Statically initialized output queues require no explicit + * initialization using @p chOQInit(). + * + * @param[in] name the name of the output queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] onotify output notification callback pointer + * @param[in] link application defined pointer + */ +#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link) \ + OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) + +#ifdef __cplusplus +extern "C" { +#endif + void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy, + void *link); + void chIQResetI(InputQueue *iqp); + msg_t chIQPutI(InputQueue *iqp, uint8_t b); + msg_t chIQGetTimeout(InputQueue *iqp, systime_t time); + size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, + size_t n, systime_t time); + + void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy, + void *link); + void chOQResetI(OutputQueue *oqp); + msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time); + msg_t chOQGetI(OutputQueue *oqp); + size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, + size_t n, systime_t time); +#ifdef __cplusplus +} +#endif +#endif /* CH_USE_QUEUES */ + +#endif /* _CHQUEUES_H_ */ + +/** @} */ diff --git a/os/kernel/include/chregistry.h b/os/kernel/include/chregistry.h new file mode 100644 index 000000000..446de7aca --- /dev/null +++ b/os/kernel/include/chregistry.h @@ -0,0 +1,130 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chregistry.h + * @brief Threads registry macros and structures. + * + * @addtogroup registry + * @{ + */ + +#ifndef _CHREGISTRY_H_ +#define _CHREGISTRY_H_ + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + +/** + * @brief ChibiOS/RT memory signature record. + */ +typedef struct { + char ch_identifier[4]; /**< @brief Always set to "main". */ + uint8_t ch_zero; /**< @brief Must be zero. */ + uint8_t ch_size; /**< @brief Size of this structure. */ + uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */ + uint8_t ch_ptrsize; /**< @brief Size of a pointer. */ + uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */ + uint8_t ch_threadsize; /**< @brief Size of a @p Thread struct. */ + uint8_t cf_off_prio; /**< @brief Offset of @p p_prio field. */ + uint8_t cf_off_ctx; /**< @brief Offset of @p p_ctx field. */ + uint8_t cf_off_newer; /**< @brief Offset of @p p_newer field. */ + uint8_t cf_off_older; /**< @brief Offset of @p p_older field. */ + uint8_t cf_off_name; /**< @brief Offset of @p p_name field. */ + uint8_t cf_off_stklimit; /**< @brief Offset of @p p_stklimit + field. */ + uint8_t cf_off_state; /**< @brief Offset of @p p_state field. */ + uint8_t cf_off_flags; /**< @brief Offset of @p p_flags field. */ + uint8_t cf_off_refs; /**< @brief Offset of @p p_refs field. */ + uint8_t cf_off_preempt; /**< @brief Offset of @p p_preempt + field. */ + uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */ +} chdebug_t; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Sets the current thread name. + * @pre This function only stores the pointer to the name if the option + * @p CH_USE_REGISTRY is enabled else no action is performed. + * + * @param[in] p thread name as a zero terminated string + * + * @api + */ +#define chRegSetThreadName(p) (currp->p_name = (p)) + +/** + * @brief Returns the name of the specified thread. + * @pre This function only returns the pointer to the name if the option + * @p CH_USE_REGISTRY is enabled else @p NULL is returned. + * + * @param[in] tp pointer to the thread + * + * @return Thread name as a zero terminated string. + * @retval NULL if the thread name has not been set. + */ +#define chRegGetThreadName(tp) ((tp)->p_name) +/** @} */ +#else /* !CH_USE_REGISTRY */ +#define chRegSetThreadName(p) +#define chRegGetThreadName(tp) NULL +#endif /* !CH_USE_REGISTRY */ + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) +/** + * @brief Removes a thread from the registry list. + * @note This macro is not meant for use in application code. + * + * @param[in] tp thread to remove from the registry + */ +#define REG_REMOVE(tp) { \ + (tp)->p_older->p_newer = (tp)->p_newer; \ + (tp)->p_newer->p_older = (tp)->p_older; \ +} + +/** + * @brief Adds a thread to the registry list. + * @note This macro is not meant for use in application code. + * + * @param[in] tp thread to add to the registry + */ +#define REG_INSERT(tp) { \ + (tp)->p_newer = (Thread *)&rlist; \ + (tp)->p_older = rlist.r_older; \ + (tp)->p_older->p_newer = rlist.r_older = (tp); \ +} + +#ifdef __cplusplus +extern "C" { +#endif + extern ROMCONST chdebug_t ch_debug; + Thread *chRegFirstThread(void); + Thread *chRegNextThread(Thread *tp); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_REGISTRY */ + +#endif /* _CHREGISTRY_H_ */ + +/** @} */ diff --git a/os/kernel/include/chschd.h b/os/kernel/include/chschd.h new file mode 100644 index 000000000..37e457c31 --- /dev/null +++ b/os/kernel/include/chschd.h @@ -0,0 +1,237 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chschd.h + * @brief Scheduler macros and structures. + * + * @addtogroup scheduler + * @{ + */ + +#ifndef _CHSCHD_H_ +#define _CHSCHD_H_ + +/** + * @name Wakeup status codes + * @{ + */ +#define RDY_OK 0 /**< @brief Normal wakeup message. */ +#define RDY_TIMEOUT -1 /**< @brief Wakeup caused by a timeout + condition. */ +#define RDY_RESET -2 /**< @brief Wakeup caused by a reset + condition. */ +/** @} */ + +/** + * @name Priority constants + * @{ + */ +#define NOPRIO 0 /**< @brief Ready list header priority. */ +#define IDLEPRIO 1 /**< @brief Idle thread priority. */ +#define LOWPRIO 2 /**< @brief Lowest user priority. */ +#define NORMALPRIO 64 /**< @brief Normal user priority. */ +#define HIGHPRIO 127 /**< @brief Highest user priority. */ +#define ABSPRIO 255 /**< @brief Greatest possible priority. */ +/** @} */ + +/** + * @name Special time constants + * @{ + */ +/** + * @brief Zero time specification for some functions with a timeout + * specification. + * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, + * see the specific function documentation. + */ +#define TIME_IMMEDIATE ((systime_t)0) + +/** + * @brief Infinite time specification for all functions with a timeout + * specification. + */ +#define TIME_INFINITE ((systime_t)-1) +/** @} */ + +/** + * @brief Returns the priority of the first thread on the given ready list. + * + * @notapi + */ +#define firstprio(rlp) ((rlp)->p_next->p_prio) + +/** + * @extends ThreadsQueue + * + * @brief Ready list header. + */ +#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__) +typedef struct { + ThreadsQueue r_queue; /**< @brief Threads queue. */ + tprio_t r_prio; /**< @brief This field must be + initialized to zero. */ + struct context r_ctx; /**< @brief Not used, present because + offsets. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + Thread *r_newer; /**< @brief Newer registry element. */ + Thread *r_older; /**< @brief Older registry element. */ +#endif + /* End of the fields shared with the Thread structure.*/ + Thread *r_current; /**< @brief The currently running + thread. */ +} ReadyList; +#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */ + +#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__) +extern ReadyList rlist; +#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */ + +/** + * @brief Current thread pointer access macro. + * @note This macro is not meant to be used in the application code but + * only from within the kernel, use the @p chThdSelf() API instead. + * @note It is forbidden to use this macro in order to change the pointer + * (currp = something), use @p setcurrp() instead. + */ +#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__) +#define currp rlist.r_current +#endif /* !defined(PORT_OPTIMIZED_CURRP) */ + +/** + * @brief Current thread pointer change macro. + * @note This macro is not meant to be used in the application code but + * only from within the kernel. + * + * @notapi + */ +#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__) +#define setcurrp(tp) (currp = (tp)) +#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */ + +/* + * Scheduler APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + void _scheduler_init(void); +#if !defined(PORT_OPTIMIZED_READYI) + Thread *chSchReadyI(Thread *tp); +#endif +#if !defined(PORT_OPTIMIZED_GOSLEEPS) + void chSchGoSleepS(tstate_t newstate); +#endif +#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) + msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time); +#endif +#if !defined(PORT_OPTIMIZED_WAKEUPS) + void chSchWakeupS(Thread *tp, msg_t msg); +#endif +#if !defined(PORT_OPTIMIZED_RESCHEDULES) + void chSchRescheduleS(void); +#endif +#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) + bool_t chSchIsPreemptionRequired(void); +#endif +#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__) + void chSchDoRescheduleBehind(void); +#endif +#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__) + void chSchDoRescheduleAhead(void); +#endif +#if !defined(PORT_OPTIMIZED_DORESCHEDULE) + void chSchDoReschedule(void); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Determines if the current thread must reschedule. + * @details This function returns @p TRUE if there is a ready thread with + * higher priority. + * + * @iclass + */ +#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__) +#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */ + +/** + * @brief Determines if yielding is possible. + * @details This function returns @p TRUE if there is a ready thread with + * equal or higher priority. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__) +#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) +#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */ + +/** + * @brief Yields the time slot. + * @details Yields the CPU control to the next thread in the ready list with + * equal or higher priority, if any. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__) +#define chSchDoYieldS() { \ + if (chSchCanYieldS()) \ + chSchDoRescheduleBehind(); \ +} +#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */ + +/** + * @brief Inline-able preemption code. + * @details This is the common preemption code, this function must be invoked + * exclusively from the port layer. + * + * @special + */ +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +#define chSchPreemption() { \ + tprio_t p1 = firstprio(&rlist.r_queue); \ + tprio_t p2 = currp->p_prio; \ + if (currp->p_preempt) { \ + if (p1 > p2) \ + chSchDoRescheduleAhead(); \ + } \ + else { \ + if (p1 >= p2) \ + chSchDoRescheduleBehind(); \ + } \ +} +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchPreemption() { \ + if (p1 >= p2) \ + chSchDoRescheduleAhead(); \ +} +#endif /* CH_TIME_QUANTUM == 0 */ +/** @} */ + +#endif /* _CHSCHD_H_ */ + +/** @} */ diff --git a/os/kernel/include/chsem.h b/os/kernel/include/chsem.h new file mode 100644 index 000000000..b5036af7c --- /dev/null +++ b/os/kernel/include/chsem.h @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chsem.h + * @brief Semaphores macros and structures. + * + * @addtogroup semaphores + * @{ + */ + +#ifndef _CHSEM_H_ +#define _CHSEM_H_ + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +/** + * @brief Semaphore structure. + */ +typedef struct Semaphore { + ThreadsQueue s_queue; /**< @brief Queue of the threads sleeping + on this semaphore. */ + cnt_t s_cnt; /**< @brief The semaphore counter. */ +} Semaphore; + +#ifdef __cplusplus +extern "C" { +#endif + void chSemInit(Semaphore *sp, cnt_t n); + void chSemReset(Semaphore *sp, cnt_t n); + void chSemResetI(Semaphore *sp, cnt_t n); + msg_t chSemWait(Semaphore *sp); + msg_t chSemWaitS(Semaphore *sp); + msg_t chSemWaitTimeout(Semaphore *sp, systime_t time); + msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time); + void chSemSignal(Semaphore *sp); + void chSemSignalI(Semaphore *sp); + void chSemAddCounterI(Semaphore *sp, cnt_t n); +#if CH_USE_SEMSW + msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static semaphore initializer. + * @details This macro should be used when statically initializing a semaphore + * that is part of a bigger structure. + * + * @param[in] name the name of the semaphore variable + * @param[in] n the counter initial value, this value must be + * non-negative + */ +#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n} + +/** + * @brief Static semaphore initializer. + * @details Statically initialized semaphores require no explicit + * initialization using @p chSemInit(). + * + * @param[in] name the name of the semaphore variable + * @param[in] n the counter initial value, this value must be + * non-negative + */ +#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Decreases the semaphore counter. + * @details This macro can be used when the counter is known to be positive. + * + * @iclass + */ +#define chSemFastWaitI(sp) ((sp)->s_cnt--) + +/** + * @brief Increases the semaphore counter. + * @details This macro can be used when the counter is known to be not + * negative. + * + * @iclass + */ +#define chSemFastSignalI(sp) ((sp)->s_cnt++) + +/** + * @brief Returns the semaphore counter current value. + * + * @iclass + */ +#define chSemGetCounterI(sp) ((sp)->s_cnt) +/** @} */ + +#endif /* CH_USE_SEMAPHORES */ + +#endif /* _CHSEM_H_ */ + +/** @} */ diff --git a/os/kernel/include/chstreams.h b/os/kernel/include/chstreams.h new file mode 100644 index 000000000..b9c40cac2 --- /dev/null +++ b/os/kernel/include/chstreams.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chstreams.h + * @brief Data streams. + * @details This header defines abstract interfaces useful to access generic + * data streams in a standardized way. + * + * @addtogroup data_streams + * @details This module define an abstract interface for generic data streams. + * Note that no code is present, just abstract interfaces-like + * structures, you should look at the system as to a set of + * abstract C++ classes (even if written in C). This system + * has then advantage to make the access to data streams + * independent from the implementation logic.
    + * The stream interface can be used as base class for high level + * object types such as files, sockets, serial ports, pipes etc. + * @{ + */ + +#ifndef _CHSTREAMS_H_ +#define _CHSTREAMS_H_ + +/** + * @brief BaseSequentialStream specific methods. + */ +#define _base_sequential_stream_methods \ + /* Stream write buffer method.*/ \ + size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ + /* Stream read buffer method.*/ \ + size_t (*read)(void *instance, uint8_t *bp, size_t n); \ + /* Channel put method, blocking.*/ \ + msg_t (*put)(void *instance, uint8_t b); \ + /* Channel get method, blocking.*/ \ + msg_t (*get)(void *instance); \ + +/** + * @brief @p BaseSequentialStream specific data. + * @note It is empty because @p BaseSequentialStream is only an interface + * without implementation. + */ +#define _base_sequential_stream_data + +/** + * @brief @p BaseSequentialStream virtual methods table. + */ +struct BaseSequentialStreamVMT { + _base_sequential_stream_methods +}; + +/** + * @brief Base stream class. + * @details This class represents a generic blocking unbuffered sequential + * data stream. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseSequentialStreamVMT *vmt; + _base_sequential_stream_data +} BaseSequentialStream; + +/** + * @name Macro Functions (BaseSequentialStream) + * @{ + */ +/** + * @brief Sequential Stream write. + * @details The function writes data from a buffer to a stream. + * + * @param[in] ip pointer to a @p BaseSequentialStream or derived class + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if an + * end-of-file condition has been met. + * + * @api + */ +#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) + +/** + * @brief Sequential Stream read. + * @details The function reads data from a stream into a buffer. + * + * @param[in] ip pointer to a @p BaseSequentialStream or derived class + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if an + * end-of-file condition has been met. + * + * @api + */ +#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) + +/** + * @brief Sequential Stream blocking byte write. + * @details This function writes a byte value to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] b the byte value to be written to the channel + * + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if an end-of-file condition has been met. + * + * @api + */ +#define chSequentialStreamPut(ip, b) ((ip)->vmt->put(ip, b)) + +/** + * @brief Sequential Stream blocking byte read. + * @details This function reads a byte value from a channel. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * + * @return A byte value from the queue. + * @retval Q_RESET if an end-of-file condition has been met. + * + * @api + */ +#define chSequentialStreamGet(ip) ((ip)->vmt->get(ip)) +/** @} */ + +#endif /* _CHSTREAMS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chsys.h b/os/kernel/include/chsys.h new file mode 100644 index 000000000..a1f59f38e --- /dev/null +++ b/os/kernel/include/chsys.h @@ -0,0 +1,247 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chsys.h + * @brief System related macros and structures. + * + * @addtogroup system + * @{ + */ + +#ifndef _CHSYS_H_ +#define _CHSYS_H_ + +/** + * @name Macro Functions + * @{ + */ +#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the idle thread. + * @pre In order to use this function the option @p CH_NO_IDLE_THREAD + * must be disabled. + * @note The reference counter of the idle thread is not incremented but + * it is not strictly required being the idle thread a static + * object. + * + * @return Pointer to the idle thread. + * + * @api + */ +#define chSysGetIdleThread() (rlist.r_queue.p_prev) +#endif + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected, for example because a programming + * error in the application code that triggers an assertion while + * in debug mode. + * @note Can be invoked from any system state. + * + * @special + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define chSysHalt() port_halt() +#else +#define chSysHalt() { \ + SYSTEM_HALT_HOOK(); \ + port_halt(); \ +} +#endif + +/** + * @brief Performs a context switch. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + * + * @special + */ +#define chSysSwitch(ntp, otp) { \ + dbg_trace(otp); \ + THREAD_CONTEXT_SWITCH_HOOK(ntp, otp); \ + port_switch(ntp, otp); \ +} + +/** + * @brief Raises the system interrupt priority mask to the maximum level. + * @details All the maskable interrupt sources are disabled regardless their + * hardware priority. + * @note Do not invoke this API from within a kernel lock. + * + * @special + */ +#define chSysDisable() { \ + port_disable(); \ + dbg_check_disable(); \ +} + +/** + * @brief Raises the system interrupt priority mask to system level. + * @details The interrupt sources that should not be able to preempt the kernel + * are disabled, interrupt sources with higher priority are still + * enabled. + * @note Do not invoke this API from within a kernel lock. + * @note This API is no replacement for @p chSysLock(), the @p chSysLock() + * could do more than just disable the interrupts. + * + * @special + */ +#define chSysSuspend() { \ + port_suspend(); \ + dbg_check_suspend(); \ +} + +/** + * @brief Lowers the system interrupt priority mask to user level. + * @details All the interrupt sources are enabled. + * @note Do not invoke this API from within a kernel lock. + * @note This API is no replacement for @p chSysUnlock(), the + * @p chSysUnlock() could do more than just enable the interrupts. + * + * @special + */ +#define chSysEnable() { \ + dbg_check_enable(); \ + port_enable(); \ +} + +/** + * @brief Enters the kernel lock mode. + * + * @special + */ +#define chSysLock() { \ + port_lock(); \ + dbg_check_lock(); \ +} + +/** + * @brief Leaves the kernel lock mode. + * + * @special + */ +#define chSysUnlock() { \ + dbg_check_unlock(); \ + port_unlock(); \ +} + +/** + * @brief Enters the kernel lock mode from within an interrupt handler. + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
    + * It is good practice to invoke this API before invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ +#define chSysLockFromIsr() { \ + port_lock_from_isr(); \ + dbg_check_lock_from_isr(); \ +} + +/** + * @brief Leaves the kernel lock mode from within an interrupt handler. + * + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
    + * It is good practice to invoke this API after invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ +#define chSysUnlockFromIsr() { \ + dbg_check_unlock_from_isr(); \ + port_unlock_from_isr(); \ +} +/** @} */ + +/** + * @name ISRs abstraction macros + */ +/** + * @brief IRQ handler enter code. + * @note Usually IRQ handlers functions are also declared naked. + * @note On some architectures this macro can be empty. + * + * @special + */ +#define CH_IRQ_PROLOGUE() \ + PORT_IRQ_PROLOGUE(); \ + dbg_check_enter_isr(); + +/** + * @brief IRQ handler exit code. + * @note Usually IRQ handlers function are also declared naked. + * @note This macro usually performs the final reschedule by using + * @p chSchIsPreemptionRequired() and @p chSchDoReschedule(). + * + * @special + */ +#define CH_IRQ_EPILOGUE() \ + dbg_check_leave_isr(); \ + PORT_IRQ_EPILOGUE(); + +/** + * @brief Standard normal IRQ handler declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * + * @special + */ +#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) +/** @} */ + +/** + * @name Fast ISRs abstraction macros + */ +/** + * @brief Standard fast IRQ handler declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * @note Not all architectures support fast interrupts. + * + * @special + */ +#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + void chSysInit(void); + void chSysTimerHandlerI(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHSYS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chthreads.h b/os/kernel/include/chthreads.h new file mode 100644 index 000000000..77f72caca --- /dev/null +++ b/os/kernel/include/chthreads.h @@ -0,0 +1,380 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chthreads.h + * @brief Threads macros and structures. + * + * @addtogroup threads + * @{ + */ + +#ifndef _CHTHREADS_H_ +#define _CHTHREADS_H_ + +/** + * @name Thread states + * @{ + */ +#define THD_STATE_READY 0 /**< @brief Waiting on the ready list. */ +#define THD_STATE_CURRENT 1 /**< @brief Currently running. */ +#define THD_STATE_SUSPENDED 2 /**< @brief Created in suspended state. */ +#define THD_STATE_WTSEM 3 /**< @brief Waiting on a semaphore. */ +#define THD_STATE_WTMTX 4 /**< @brief Waiting on a mutex. */ +#define THD_STATE_WTCOND 5 /**< @brief Waiting on a condition + variable. */ +#define THD_STATE_SLEEPING 6 /**< @brief Waiting in @p chThdSleep() + or @p chThdSleepUntil(). */ +#define THD_STATE_WTEXIT 7 /**< @brief Waiting in @p chThdWait(). */ +#define THD_STATE_WTOREVT 8 /**< @brief Waiting for an event. */ +#define THD_STATE_WTANDEVT 9 /**< @brief Waiting for several events. */ +#define THD_STATE_SNDMSGQ 10 /**< @brief Sending a message, in queue.*/ +#define THD_STATE_SNDMSG 11 /**< @brief Sent a message, waiting + answer. */ +#define THD_STATE_WTMSG 12 /**< @brief Waiting for a message. */ +#define THD_STATE_WTQUEUE 13 /**< @brief Waiting on an I/O queue. */ +#define THD_STATE_FINAL 14 /**< @brief Thread terminated. */ + +/** + * @brief Thread states as array of strings. + * @details Each element in an array initialized with this macro can be + * indexed using the numeric thread state values. + */ +#define THD_STATE_NAMES \ + "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", \ + "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \ + "FINAL" +/** @} */ + +/** + * @name Thread flags and attributes + * @{ + */ +#define THD_MEM_MODE_MASK 3 /**< @brief Thread memory mode mask. */ +#define THD_MEM_MODE_STATIC 0 /**< @brief Static thread. */ +#define THD_MEM_MODE_HEAP 1 /**< @brief Thread allocated from a + Memory Heap. */ +#define THD_MEM_MODE_MEMPOOL 2 /**< @brief Thread allocated from a + Memory Pool. */ +#define THD_TERMINATE 4 /**< @brief Termination requested flag. */ +/** @} */ + +/** + * @extends ThreadsQueue + * + * @brief Structure representing a thread. + * @note Not all the listed fields are always needed, by switching off some + * not needed ChibiOS/RT subsystems it is possible to save RAM space + * by shrinking the @p Thread structure. + */ +struct Thread { + Thread *p_next; /**< @brief Next in the list/queue. */ + /* End of the fields shared with the ThreadsList structure. */ + Thread *p_prev; /**< @brief Previous in the queue. */ + /* End of the fields shared with the ThreadsQueue structure. */ + tprio_t p_prio; /**< @brief Thread priority. */ + struct context p_ctx; /**< @brief Processor context. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + Thread *p_newer; /**< @brief Newer registry element. */ + Thread *p_older; /**< @brief Older registry element. */ +#endif + /* End of the fields shared with the ReadyList structure. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + /** + * @brief Thread name or @p NULL. + */ + const char *p_name; +#endif +#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) + /** + * @brief Thread stack boundary. + */ + stkalign_t *p_stklimit; +#endif + /** + * @brief Current thread state. + */ + tstate_t p_state; + /** + * @brief Various thread flags. + */ + tmode_t p_flags; +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + /** + * @brief References to this thread. + */ + trefs_t p_refs; +#endif + /** + * @brief Number of ticks remaining to this thread. + */ +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) + tslices_t p_preempt; +#endif +#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) + /** + * @brief Thread consumed time in ticks. + * @note This field can overflow. + */ + volatile systime_t p_time; +#endif + /** + * @brief State-specific fields. + * @note All the fields declared in this union are only valid in the + * specified state or condition and are thus volatile. + */ + union { + /** + * @brief Thread wakeup code. + * @note This field contains the low level message sent to the thread + * by the waking thread or interrupt handler. The value is valid + * after exiting the @p chSchWakeupS() function. + */ + msg_t rdymsg; + /** + * @brief Thread exit code. + * @note The thread termination code is stored in this field in order + * to be retrieved by the thread performing a @p chThdWait() on + * this thread. + */ + msg_t exitcode; + /** + * @brief Pointer to a generic "wait" object. + * @note This field is used to get a generic pointer to a synchronization + * object and is valid when the thread is in one of the wait + * states. + */ + void *wtobjp; +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Enabled events mask. + * @note This field is only valid while the thread is in the + * @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states. + */ + eventmask_t ewmask; +#endif + } p_u; +#if CH_USE_WAITEXIT || defined(__DOXYGEN__) + /** + * @brief Termination waiting list. + */ + ThreadsList p_waiting; +#endif +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + /** + * @brief Messages queue. + */ + ThreadsQueue p_msgqueue; + /** + * @brief Thread message. + */ + msg_t p_msg; +#endif +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Pending events mask. + */ + eventmask_t p_epending; +#endif +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief List of the mutexes owned by this thread. + * @note The list is terminated by a @p NULL in this field. + */ + Mutex *p_mtxlist; + /** + * @brief Thread's own, non-inherited, priority. + */ + tprio_t p_realprio; +#endif +#if (CH_USE_DYNAMIC && CH_USE_MEMPOOLS) || defined(__DOXYGEN__) + /** + * @brief Memory Pool where the thread workspace is returned. + */ + void *p_mpool; +#endif +#if defined(THREAD_EXT_FIELDS) + /* Extra fields defined in chconf.h.*/ + THREAD_EXT_FIELDS +#endif +}; + +/** + * @brief Thread function. + */ +typedef msg_t (*tfunc_t)(void *); + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns a pointer to the current @p Thread. + * @note Can be invoked in any context. + * + * @special + */ +#define chThdSelf() currp + +/** + * @brief Returns the current thread priority. + * @note Can be invoked in any context. + * + * @special + */ +#define chThdGetPriority() (currp->p_prio) + +/** + * @brief Returns the number of ticks consumed by the specified thread. + * @note This function is only available when the + * @p CH_DBG_THREADS_PROFILING configuration option is enabled. + * @note Can be invoked in any context. + * + * @param[in] tp pointer to the thread + * + * @special + */ +#define chThdGetTicks(tp) ((tp)->p_time) + +/** + * @brief Returns the pointer to the @p Thread local storage area, if any. + * @note Can be invoked in any context. + * + * @special + */ +#define chThdLS() (void *)(currp + 1) + +/** + * @brief Verifies if the specified thread is in the @p THD_STATE_FINAL state. + * @note Can be invoked in any context. + * + * @param[in] tp pointer to the thread + * @retval TRUE thread terminated. + * @retval FALSE thread not terminated. + * + * @special + */ +#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) + +/** + * @brief Verifies if the current thread has a termination request pending. + * @note Can be invoked in any context. + * + * @retval TRUE termination request pending. + * @retval FALSE termination request not pending. + * + * @special + */ +#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) + +/** + * @brief Resumes a thread created with @p chThdCreateI(). + * + * @param[in] tp pointer to the thread + * + * @iclass + */ +#define chThdResumeI(tp) chSchReadyI(tp) + +/** + * @brief Suspends the invoking thread for the specified time. + * + * @param[in] time the delay in system ticks, the special values are + * handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * + * @sclass + */ +#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) + +/** + * @brief Delays the invoking thread for the specified number of seconds. + * @note The specified time is rounded up to a value allowed by the real + * system tick clock. + * @note The maximum specifiable value is implementation dependent. + * + * @param[in] sec time in seconds, must be different from zero + * + * @api + */ +#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) + +/** + * @brief Delays the invoking thread for the specified number of + * milliseconds. + * @note The specified time is rounded up to a value allowed by the real + * system tick clock. + * @note The maximum specifiable value is implementation dependent. + * + * @param[in] msec time in milliseconds, must be different from zero + * + * @api + */ +#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) + +/** + * @brief Delays the invoking thread for the specified number of + * microseconds. + * @note The specified time is rounded up to a value allowed by the real + * system tick clock. + * @note The maximum specifiable value is implementation dependent. + * + * @param[in] usec time in microseconds, must be different from zero + * + * @api + */ +#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) +/** @} */ + +/* + * Threads APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + Thread *_thread_init(Thread *tp, tprio_t prio); +#if CH_DBG_FILL_THREADS + void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v); +#endif + Thread *chThdCreateI(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); + Thread *chThdCreateStatic(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); + tprio_t chThdSetPriority(tprio_t newprio); + Thread *chThdResume(Thread *tp); + void chThdTerminate(Thread *tp); + void chThdSleep(systime_t time); + void chThdSleepUntil(systime_t time); + void chThdYield(void); + void chThdExit(msg_t msg); + void chThdExitS(msg_t msg); +#if CH_USE_WAITEXIT + msg_t chThdWait(Thread *tp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _CHTHREADS_H_ */ + +/** @} */ diff --git a/os/kernel/include/chvt.h b/os/kernel/include/chvt.h new file mode 100644 index 000000000..97a04d81e --- /dev/null +++ b/os/kernel/include/chvt.h @@ -0,0 +1,228 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chvt.h + * @brief Time macros and structures. + * + * @addtogroup time + * @{ + */ + +#ifndef _CHVT_H_ +#define _CHVT_H_ + +/** + * @name Time conversion utilities + * @{ + */ +/** + * @brief Seconds to system ticks. + * @details Converts from seconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] sec number of seconds + * @return The number of ticks. + * + * @api + */ +#define S2ST(sec) \ + ((systime_t)((sec) * CH_FREQUENCY)) + +/** + * @brief Milliseconds to system ticks. + * @details Converts from milliseconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] msec number of milliseconds + * @return The number of ticks. + * + * @api + */ +#define MS2ST(msec) \ + ((systime_t)((((msec) * CH_FREQUENCY - 1L) / 1000L) + 1L)) + +/** + * @brief Microseconds to system ticks. + * @details Converts from microseconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] usec number of microseconds + * @return The number of ticks. + * + * @api + */ +#define US2ST(usec) \ + ((systime_t)((((usec) * CH_FREQUENCY - 1L) / 1000000L) + 1L)) +/** @} */ + +/** + * @brief Virtual Timer callback function. + */ +typedef void (*vtfunc_t)(void *); + +/** + * @brief Virtual Timer structure type. + */ +typedef struct VirtualTimer VirtualTimer; + +/** + * @extends VTList + * + * @brief Virtual Timer descriptor structure. + */ +struct VirtualTimer { + VirtualTimer *vt_next; /**< @brief Next timer in the delta + list. */ + VirtualTimer *vt_prev; /**< @brief Previous timer in the delta + list. */ + systime_t vt_time; /**< @brief Time delta before timeout. */ + vtfunc_t vt_func; /**< @brief Timer callback function + pointer. */ + void *vt_par; /**< @brief Timer callback function + parameter. */ +}; + +/** + * @brief Virtual timers list header. + * @note The delta list is implemented as a double link bidirectional list + * in order to make the unlink time constant, the reset of a virtual + * timer is often used in the code. + */ +typedef struct { + VirtualTimer *vt_next; /**< @brief Next timer in the delta + list. */ + VirtualTimer *vt_prev; /**< @brief Last timer in the delta + list. */ + systime_t vt_time; /**< @brief Must be initialized to -1. */ + volatile systime_t vt_systime; /**< @brief System Time counter. */ +} VTList; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Virtual timers ticker. + * @note The system lock is released before entering the callback and + * re-acquired immediately after. It is callback's responsibility + * to acquire the lock if needed. This is done in order to reduce + * interrupts jitter when many timers are in use. + * + * @iclass + */ +#define chVTDoTickI() { \ + vtlist.vt_systime++; \ + if (&vtlist != (VTList *)vtlist.vt_next) { \ + VirtualTimer *vtp; \ + \ + --vtlist.vt_next->vt_time; \ + while (!(vtp = vtlist.vt_next)->vt_time) { \ + vtfunc_t fn = vtp->vt_func; \ + vtp->vt_func = (vtfunc_t)NULL; \ + vtp->vt_next->vt_prev = (void *)&vtlist; \ + (&vtlist)->vt_next = vtp->vt_next; \ + chSysUnlockFromIsr(); \ + fn(vtp->vt_par); \ + chSysLockFromIsr(); \ + } \ + } \ +} + +/** + * @brief Returns @p TRUE if the specified timer is armed. + * + * @iclass + */ +#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) + +/** + * @brief Enables a virtual timer. + * @note The associated function is invoked from interrupt context. + * + * @param[out] vtp the @p VirtualTimer structure pointer + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE is allowed but interpreted as a + * normal time specification. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @param[in] vtfunc the timer callback function. After invoking the + * callback the timer is disabled and the structure can + * be disposed or reused. + * @param[in] par a parameter that will be passed to the callback + * function + * + * @api + */ +#define chVTSet(vtp, time, vtfunc, par) { \ + chSysLock(); \ + chVTSetI(vtp, time, vtfunc, par); \ + chSysUnlock(); \ +} + +/** + * @brief Disables a Virtual Timer. + * @note The timer is first checked and disabled only if armed. + * + * @param[in] vtp the @p VirtualTimer structure pointer + * + * @api + */ +#define chVTReset(vtp) { \ + chSysLock(); \ + if (chVTIsArmedI(vtp)) \ + chVTResetI(vtp); \ + chSysUnlock(); \ +} + +/** + * @brief Current system time. + * @details Returns the number of system ticks since the @p chSysInit() + * invocation. + * @note The counter can reach its maximum and then restart from zero. + * @note This function is designed to work with the @p chThdSleepUntil(). + * + * @return The system time in ticks. + * + * @api + */ +#define chTimeNow() (vtlist.vt_systime) +/** @} */ + +extern VTList vtlist; + +/* + * Virtual Timers APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + void _vt_init(void); + void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par); + void chVTResetI(VirtualTimer *vtp); + bool_t chTimeIsWithin(systime_t start, systime_t end); +#ifdef __cplusplus +} +#endif + +#endif /* _CHVT_H_ */ + +/** @} */ diff --git a/os/kernel/kernel.dox b/os/kernel/kernel.dox new file mode 100644 index 000000000..05753a8f6 --- /dev/null +++ b/os/kernel/kernel.dox @@ -0,0 +1,173 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup kernel Kernel + * @details The kernel is the portable part of ChibiOS/RT, this section + * documents the various kernel subsystems. + */ + +/** + * @defgroup kernel_info Version Numbers and Identification + * @ingroup kernel + */ + +/** + * @defgroup config Configuration + * @ingroup kernel + */ + +/** + * @defgroup types Types + * @details The system types are defined into the port layer, please refer to + * the core port implementation section. + * @ingroup kernel + */ + +/** + * @defgroup base Base Kernel Services + * @details Base kernel services, the base subsystems are always included in + * the OS builds. + * @ingroup kernel + */ + +/** + * @defgroup system System Management + * @ingroup base + */ + +/** + * @defgroup scheduler Scheduler + * @ingroup base + */ + +/** + * @defgroup threads Threads + * @ingroup base + */ + +/** + * @defgroup time Time and Virtual Timers + * @ingroup base + */ + +/** + * @defgroup synchronization Synchronization + * @details Synchronization services. + * @ingroup kernel + */ + +/** + * @defgroup semaphores Counting Semaphores + * @ingroup synchronization + */ + +/** + * @defgroup binary_semaphores Binary Semaphores + * @ingroup synchronization + */ + +/** + * @defgroup mutexes Mutexes + * @ingroup synchronization + */ + +/** + * @defgroup condvars Condition Variables + * @ingroup synchronization + */ + +/** + * @defgroup events Event Flags + * @ingroup synchronization + */ + +/** + * @defgroup messages Synchronous Messages + * @ingroup synchronization + */ + +/** + * @defgroup mailboxes Mailboxes + * @ingroup synchronization + */ + +/** + * @defgroup io_queues I/O Queues + * @ingroup synchronization + */ + +/** + * @defgroup memory Memory Management + * @details Memory Management services. + * @ingroup kernel + */ + +/** + * @defgroup memcore Core Memory Manager + * @ingroup memory + */ + +/** + * @defgroup heaps Heaps + * @ingroup memory + */ + +/** + * @defgroup pools Memory Pools + * @ingroup memory + */ + +/** + * @defgroup dynamic_threads Dynamic Threads + * @ingroup memory + */ + + /** + * @defgroup streams Streams and Files + * @details Stream and Files interfaces. + * @ingroup kernel + */ + +/** + * @defgroup data_streams Abstract Sequential Streams + * @ingroup streams + */ + +/** + * @defgroup data_files Abstract File Streams + * @ingroup streams + */ + +/** + * @defgroup registry Registry + * @ingroup kernel + */ + +/** + * @defgroup debug Debug + * @ingroup kernel + */ + +/** + * @defgroup internals Internals + * @ingroup kernel + */ + diff --git a/os/kernel/kernel.mk b/os/kernel/kernel.mk new file mode 100644 index 000000000..3ebf2ed98 --- /dev/null +++ b/os/kernel/kernel.mk @@ -0,0 +1,23 @@ +# List of all the ChibiOS/RT kernel files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing chconf.h. +KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \ + ${CHIBIOS}/os/kernel/src/chdebug.c \ + ${CHIBIOS}/os/kernel/src/chlists.c \ + ${CHIBIOS}/os/kernel/src/chvt.c \ + ${CHIBIOS}/os/kernel/src/chschd.c \ + ${CHIBIOS}/os/kernel/src/chthreads.c \ + ${CHIBIOS}/os/kernel/src/chdynamic.c \ + ${CHIBIOS}/os/kernel/src/chregistry.c \ + ${CHIBIOS}/os/kernel/src/chsem.c \ + ${CHIBIOS}/os/kernel/src/chmtx.c \ + ${CHIBIOS}/os/kernel/src/chcond.c \ + ${CHIBIOS}/os/kernel/src/chevents.c \ + ${CHIBIOS}/os/kernel/src/chmsg.c \ + ${CHIBIOS}/os/kernel/src/chmboxes.c \ + ${CHIBIOS}/os/kernel/src/chqueues.c \ + ${CHIBIOS}/os/kernel/src/chmemcore.c \ + ${CHIBIOS}/os/kernel/src/chheap.c \ + ${CHIBIOS}/os/kernel/src/chmempools.c + +# Required include directories +KERNINC = ${CHIBIOS}/os/kernel/include diff --git a/os/kernel/src/chcond.c b/os/kernel/src/chcond.c new file mode 100644 index 000000000..c217bf6fd --- /dev/null +++ b/os/kernel/src/chcond.c @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Leon Woestenberg. + */ + +/** + * @file chcond.c + * @brief Condition Variables code. + * + * @addtogroup condvars Condition Variables + * @details This module implements the Condition Variables mechanism. Condition + * variables are an extensions to the Mutex subsystem and cannot + * work alone. + *

    Operation mode

    + * The condition variable is a synchronization object meant to be + * used inside a zone protected by a @p Mutex. Mutexes and CondVars + * together can implement a Monitor construct. + * @pre In order to use the condition variable APIs the @p CH_USE_CONDVARS + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if (CH_USE_CONDVARS && CH_USE_MUTEXES) || defined(__DOXYGEN__) + +/** + * @brief Initializes s @p CondVar structure. + * + * @param[out] cp pointer to a @p CondVar structure + * + * @init + */ +void chCondInit(CondVar *cp) { + + chDbgCheck(cp != NULL, "chCondInit"); + + queue_init(&cp->c_queue); +} + +/** + * @brief Signals one thread that is waiting on the condition variable. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @api + */ +void chCondSignal(CondVar *cp) { + + chDbgCheck(cp != NULL, "chCondSignal"); + + chSysLock(); + if (notempty(&cp->c_queue)) + chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK); + chSysUnlock(); +} + +/** + * @brief Signals one thread that is waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @iclass + */ +void chCondSignalI(CondVar *cp) { + + chDbgCheckClassI(); + chDbgCheck(cp != NULL, "chCondSignalI"); + + if (notempty(&cp->c_queue)) + chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK; +} + +/** + * @brief Signals all threads that are waiting on the condition variable. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @api + */ +void chCondBroadcast(CondVar *cp) { + + chSysLock(); + chCondBroadcastI(cp); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Signals all threads that are waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @iclass + */ +void chCondBroadcastI(CondVar *cp) { + + chDbgCheckClassI(); + chDbgCheck(cp != NULL, "chCondBroadcastI"); + + /* Empties the condition variable queue and inserts all the Threads into the + ready list in FIFO order. The wakeup message is set to @p RDY_RESET in + order to make a chCondBroadcast() detectable from a chCondSignal().*/ + while (cp->c_queue.p_next != (void *)&cp->c_queue) + chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @param[in] cp pointer to the @p CondVar structure + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @api + */ +msg_t chCondWait(CondVar *cp) { + msg_t msg; + + chSysLock(); + msg = chCondWaitS(cp); + chSysUnlock(); + return msg; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @param[in] cp pointer to the @p CondVar structure + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @sclass + */ +msg_t chCondWaitS(CondVar *cp) { + Thread *ctp = currp; + Mutex *mp; + msg_t msg; + + chDbgCheckClassS(); + chDbgCheck(cp != NULL, "chCondWaitS"); + chDbgAssert(ctp->p_mtxlist != NULL, + "chCondWaitS(), #1", + "not owning a mutex"); + + mp = chMtxUnlockS(); + ctp->p_u.wtobjp = cp; + prio_insert(ctp, &cp->c_queue); + chSchGoSleepS(THD_STATE_WTCOND); + msg = ctp->p_u.rdymsg; + chMtxLockS(mp); + return msg; +} + +#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled + * in order to use this function. + * @post Exiting the function because a timeout does not re-acquire the + * mutex, the mutex ownership is lost. + * + * @param[in] cp pointer to the @p CondVar structure + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE no timeout. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar has not been signaled within the + * specified timeout. + * + * @api + */ +msg_t chCondWaitTimeout(CondVar *cp, systime_t time) { + msg_t msg; + + chSysLock(); + msg = chCondWaitTimeoutS(cp, time); + chSysUnlock(); + return msg; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled + * in order to use this function. + * @post Exiting the function because a timeout does not re-acquire the + * mutex, the mutex ownership is lost. + * + * @param[in] cp pointer to the @p CondVar structure + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE no timeout. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar has not been signaled within the + * specified timeout. + * + * @sclass + */ +msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) { + Mutex *mp; + msg_t msg; + + chDbgCheckClassS(); + chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE), "chCondWaitTimeoutS"); + chDbgAssert(currp->p_mtxlist != NULL, + "chCondWaitTimeoutS(), #1", + "not owning a mutex"); + + mp = chMtxUnlockS(); + currp->p_u.wtobjp = cp; + prio_insert(currp, &cp->c_queue); + msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time); + if (msg != RDY_TIMEOUT) + chMtxLockS(mp); + return msg; +} +#endif /* CH_USE_CONDVARS_TIMEOUT */ + +#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */ + +/** @} */ diff --git a/os/kernel/src/chdebug.c b/os/kernel/src/chdebug.c new file mode 100644 index 000000000..c69ce8f3f --- /dev/null +++ b/os/kernel/src/chdebug.c @@ -0,0 +1,271 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chdebug.c + * @brief ChibiOS/RT Debug code. + * + * @addtogroup debug + * @details Debug APIs and services: + * - Runtime system state and call protocol check. The following + * panic messages can be generated: + * - SV#1, misplaced @p chSysDisable(). + * - SV#2, misplaced @p chSysSuspend() + * - SV#3, misplaced @p chSysEnable(). + * - SV#4, misplaced @p chSysLock(). + * - SV#5, misplaced @p chSysUnlock(). + * - SV#6, misplaced @p chSysLockFromIsr(). + * - SV#7, misplaced @p chSysUnlockFromIsr(). + * - SV#8, misplaced @p CH_IRQ_PROLOGUE(). + * - SV#9, misplaced @p CH_IRQ_EPILOGUE(). + * - SV#10, misplaced I-class function. + * - SV#11, misplaced S-class function. + * . + * - Trace buffer. + * - Parameters check. + * - Kernel assertions. + * - Kernel panics. + * . + * @note Stack checks are not implemented in this module but in the port + * layer in an architecture-dependent way. + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* System state checker related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__) + +/** + * @brief ISR nesting level. + */ +cnt_t dbg_isr_cnt; + +/** + * @brief Lock nesting level. + */ +cnt_t dbg_lock_cnt; + +/** + * @brief Guard code for @p chSysDisable(). + * + * @notapi + */ +void dbg_check_disable(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#1"); +} + +/** + * @brief Guard code for @p chSysSuspend(). + * + * @notapi + */ +void dbg_check_suspend(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#2"); +} + +/** + * @brief Guard code for @p chSysEnable(). + * + * @notapi + */ +void dbg_check_enable(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#3"); +} + +/** + * @brief Guard code for @p chSysLock(). + * + * @notapi + */ +void dbg_check_lock(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#4"); + dbg_enter_lock(); +} + +/** + * @brief Guard code for @p chSysUnlock(). + * + * @notapi + */ +void dbg_check_unlock(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#5"); + dbg_leave_lock(); +} + +/** + * @brief Guard code for @p chSysLockFromIsr(). + * + * @notapi + */ +void dbg_check_lock_from_isr(void) { + + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#6"); + dbg_enter_lock(); +} + +/** + * @brief Guard code for @p chSysUnlockFromIsr(). + * + * @notapi + */ +void dbg_check_unlock_from_isr(void) { + + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#7"); + dbg_leave_lock(); +} + +/** + * @brief Guard code for @p CH_IRQ_PROLOGUE(). + * + * @notapi + */ +void dbg_check_enter_isr(void) { + + port_lock_from_isr(); + if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#8"); + dbg_isr_cnt++; + port_unlock_from_isr(); +} + +/** + * @brief Guard code for @p CH_IRQ_EPILOGUE(). + * + * @notapi + */ +void dbg_check_leave_isr(void) { + + port_lock_from_isr(); + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#9"); + dbg_isr_cnt--; + port_unlock_from_isr(); +} + +/** + * @brief I-class functions context check. + * @details Verifies that the system is in an appropriate state for invoking + * an I-class API function. A panic is generated if the state is + * not compatible. + * + * @api + */ +void chDbgCheckClassI(void) { + + if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#10"); +} + +/** + * @brief S-class functions context check. + * @details Verifies that the system is in an appropriate state for invoking + * an S-class API function. A panic is generated if the state is + * not compatible. + * + * @api + */ +void chDbgCheckClassS(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#11"); +} + +#endif /* CH_DBG_SYSTEM_STATE_CHECK */ + +/*===========================================================================*/ +/* Trace related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) +/** + * @brief Public trace buffer. + */ +ch_trace_buffer_t dbg_trace_buffer; + +/** + * @brief Trace circular buffer subsystem initialization. + * @note Internal use only. + */ +void _trace_init(void) { + + dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE; + dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; +} + +/** + * @brief Inserts in the circular debug trace buffer a context switch record. + * + * @param[in] otp the thread being switched out + * + * @notapi + */ +void dbg_trace(Thread *otp) { + + dbg_trace_buffer.tb_ptr->se_time = chTimeNow(); + dbg_trace_buffer.tb_ptr->se_tp = currp; + dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; + dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; + if (++dbg_trace_buffer.tb_ptr >= + &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE]) + dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; +} +#endif /* CH_DBG_ENABLE_TRACE */ + +/*===========================================================================*/ +/* Panic related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLED || defined(__DOXYGEN__) +/** + * @brief Pointer to the panic message. + * @details This pointer is meant to be accessed through the debugger, it is + * written once and then the system is halted. + */ +const char *dbg_panic_msg; + +/** + * @brief Prints a panic message on the console and then halts the system. + * + * @param[in] msg the pointer to the panic message string + */ +void chDbgPanic(const char *msg) { + + dbg_panic_msg = msg; + chSysHalt(); +} +#endif /* CH_DBG_ENABLED */ + +/** @} */ diff --git a/os/kernel/src/chdynamic.c b/os/kernel/src/chdynamic.c new file mode 100644 index 000000000..632367ca1 --- /dev/null +++ b/os/kernel/src/chdynamic.c @@ -0,0 +1,204 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chdynamic.c + * @brief Dynamic threads code. + * + * @addtogroup dynamic_threads + * @details Dynamic threads related APIs and services. + * @{ + */ + +#include "ch.h" + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + +/** + * @brief Adds a reference to a thread object. + * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order + * to use this function. + * + * @param[in] tp pointer to the thread + * @return The same thread pointer passed as parameter + * representing the new reference. + * + * @api + */ +Thread *chThdAddRef(Thread *tp) { + + chSysLock(); + chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references"); + tp->p_refs++; + chSysUnlock(); + return tp; +} + +/** + * @brief Releases a reference to a thread object. + * @details If the references counter reaches zero and the thread + * is in the @p THD_STATE_FINAL state then the thread's memory is + * returned to the proper allocator. + * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order + * to use this function. + * @note Static threads are not affected. + * + * @param[in] tp pointer to the thread + * + * @api + */ +void chThdRelease(Thread *tp) { + trefs_t refs; + + chSysLock(); + chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced"); + refs = --tp->p_refs; + chSysUnlock(); + + /* If the references counter reaches zero and the thread is in its + terminated state then the memory can be returned to the proper + allocator. Of course static threads are not affected.*/ + if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) { + switch (tp->p_flags & THD_MEM_MODE_MASK) { +#if CH_USE_HEAP + case THD_MEM_MODE_HEAP: +#if CH_USE_REGISTRY + REG_REMOVE(tp); +#endif + chHeapFree(tp); + break; +#endif +#if CH_USE_MEMPOOLS + case THD_MEM_MODE_MEMPOOL: +#if CH_USE_REGISTRY + REG_REMOVE(tp); +#endif + chPoolFree(tp->p_mpool, tp); + break; +#endif + } + } +} + +#if CH_USE_HEAP || defined(__DOXYGEN__) +/** + * @brief Creates a new thread allocating the memory from the heap. + * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_HEAP + * must be enabled in order to use this function. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note The memory allocated for the thread is not released when the thread + * terminates but when a @p chThdWait() is performed. + * + * @param[in] heapp heap from which allocate the memory or @p NULL for the + * default heap + * @param[in] size size of the working area to be allocated + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * @retval NULL if the memory cannot be allocated. + * + * @api + */ +Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + void *wsp; + Thread *tp; + + wsp = chHeapAlloc(heapp, size); + if (wsp == NULL) + return NULL; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + size, + CH_STACK_FILL_VALUE); +#endif + + chSysLock(); + tp = chThdCreateI(wsp, size, prio, pf, arg); + tp->p_flags = THD_MEM_MODE_HEAP; + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} +#endif /* CH_USE_HEAP */ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +/** + * @brief Creates a new thread allocating the memory from the specified + * memory pool. + * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_MEMPOOLS + * must be enabled in order to use this function. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note The memory allocated for the thread is not released when the thread + * terminates but when a @p chThdWait() is performed. + * + * @param[in] mp pointer to the memory pool object + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * @retval NULL if the memory pool is empty. + * + * @api + */ +Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, + tfunc_t pf, void *arg) { + void *wsp; + Thread *tp; + + chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool"); + + wsp = chPoolAlloc(mp); + if (wsp == NULL) + return NULL; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + mp->mp_object_size, + CH_STACK_FILL_VALUE); +#endif + + chSysLock(); + tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg); + tp->p_flags = THD_MEM_MODE_MEMPOOL; + tp->p_mpool = mp; + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} +#endif /* CH_USE_MEMPOOLS */ + +#endif /* CH_USE_DYNAMIC */ + +/** @} */ diff --git a/os/kernel/src/chevents.c b/os/kernel/src/chevents.c new file mode 100644 index 000000000..1a2285779 --- /dev/null +++ b/os/kernel/src/chevents.c @@ -0,0 +1,548 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + Concepts and parts of this file have been contributed by Scott (skute). + */ + +/** + * @file chevents.c + * @brief Events code. + * + * @addtogroup events + * @details Event Flags, Event Sources and Event Listeners. + *

    Operation mode

    + * Each thread has a mask of pending event flags inside its @p Thread + * structure. + * Operations defined for event flags: + * - Wait, the invoking thread goes to sleep until a certain + * AND/OR combination of event flags becomes pending. + * - Clear, a mask of event flags is cleared from the pending + * events mask, the cleared event flags mask is returned (only the + * flags that were actually pending and then cleared). + * - Signal, an event mask is directly ORed to the mask of the + * signaled thread. + * - Broadcast, each thread registered on an Event Source is + * signaled with the event flags specified in its Event Listener. + * - Dispatch, an events mask is scanned and for each bit set + * to one an associated handler function is invoked. Bit masks are + * scanned from bit zero upward. + * . + * An Event Source is a special object that can be "broadcasted" by + * a thread or an interrupt service routine. Broadcasting an Event + * Source has the effect that all the threads registered on the + * Event Source will be signaled with an events mask.
    + * An unlimited number of Event Sources can exists in a system and + * each thread can be listening on an unlimited number of + * them. + * @pre In order to use the Events APIs the @p CH_USE_EVENTS option must be + * enabled in @p chconf.h. + * @post Enabling events requires 1-4 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_EVENTS || defined(__DOXYGEN__) +/** + * @brief Registers an Event Listener on an Event Source. + * @details Once a thread has registered as listener on an event source it + * will be notified of all events broadcasted there. + * @note Multiple Event Listeners can specify the same bits to be ORed to + * different threads. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] elp pointer to the @p EventListener structure + * @param[in] mask the mask of event flags to be ORed to the thread when + * the event source is broadcasted + * + * @api + */ +void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) { + + chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask"); + + chSysLock(); + elp->el_next = esp->es_next; + esp->es_next = elp; + elp->el_listener = currp; + elp->el_mask = mask; + elp->el_flags = 0; + chSysUnlock(); +} + +/** + * @brief Unregisters an Event Listener from its Event Source. + * @note If the event listener is not registered on the specified event + * source then the function does nothing. + * @note For optimal performance it is better to perform the unregister + * operations in inverse order of the register operations (elements + * are found on top of the list). + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] elp pointer to the @p EventListener structure + * + * @api + */ +void chEvtUnregister(EventSource *esp, EventListener *elp) { + EventListener *p; + + chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister"); + + p = (EventListener *)esp; + chSysLock(); + while (p->el_next != (EventListener *)esp) { + if (p->el_next == elp) { + p->el_next = elp->el_next; + break; + } + p = p->el_next; + } + chSysUnlock(); +} + +/** + * @brief Clears the pending events specified in the mask. + * + * @param[in] mask the events to be cleared + * @return The pending events that were cleared. + * + * @api + */ +eventmask_t chEvtGetAndClearEvents(eventmask_t mask) { + eventmask_t m; + + chSysLock(); + + m = currp->p_epending & mask; + currp->p_epending &= ~mask; + + chSysUnlock(); + return m; +} + +/** + * @brief Adds (OR) a set of event flags on the current thread, this is + * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal(). + * + * @param[in] mask the event flags to be added + * @return The current pending events mask. + * + * @api + */ +eventmask_t chEvtAddEvents(eventmask_t mask) { + + chSysLock(); + + mask = (currp->p_epending |= mask); + + chSysUnlock(); + return mask; +} + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @details This function variants ORs the specified event flags to all the + * threads registered on the @p EventSource in addition to the event + * flags specified by the threads themselves in the + * @p EventListener objects. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] flags the flags set to be added to the listener flags mask + * + * @iclass + */ +void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags) { + EventListener *elp; + + chDbgCheckClassI(); + chDbgCheck(esp != NULL, "chEvtBroadcastMaskI"); + + elp = esp->es_next; + while (elp != (EventListener *)esp) { + elp->el_flags |= flags; + chEvtSignalI(elp->el_listener, elp->el_mask); + elp = elp->el_next; + } +} + +/** + * @brief Returns the flags associated to an @p EventListener. + * @details The flags are returned and the @p EventListener flags mask is + * cleared. + * + * @param[in] elp pointer to the @p EventListener structure + * @return The flags added to the listener by the associated + * event source. + * + * @iclass + */ +flagsmask_t chEvtGetAndClearFlags(EventListener *elp) { + flagsmask_t flags; + + chSysLock(); + + flags = elp->el_flags; + elp->el_flags = 0; + + chSysUnlock(); + return flags; +} + +/** + * @brief Adds a set of event flags directly to specified @p Thread. + * + * @param[in] tp the thread to be signaled + * @param[in] mask the event flags set to be ORed + * + * @api + */ +void chEvtSignal(Thread *tp, eventmask_t mask) { + + chDbgCheck(tp != NULL, "chEvtSignal"); + + chSysLock(); + chEvtSignalI(tp, mask); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Adds a set of event flags directly to specified @p Thread. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] tp the thread to be signaled + * @param[in] mask the event flags set to be ORed + * + * @iclass + */ +void chEvtSignalI(Thread *tp, eventmask_t mask) { + + chDbgCheckClassI(); + chDbgCheck(tp != NULL, "chEvtSignalI"); + + tp->p_epending |= mask; + /* Test on the AND/OR conditions wait states.*/ + if (((tp->p_state == THD_STATE_WTOREVT) && + ((tp->p_epending & tp->p_u.ewmask) != 0)) || + ((tp->p_state == THD_STATE_WTANDEVT) && + ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) + chSchReadyI(tp)->p_u.rdymsg = RDY_OK; +} + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @details This function variants ORs the specified event flags to all the + * threads registered on the @p EventSource in addition to the event + * flags specified by the threads themselves in the + * @p EventListener objects. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] flags the flags set to be added to the listener flags mask + * + * @api + */ +void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags) { + + chSysLock(); + chEvtBroadcastFlagsI(esp, flags); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Returns the flags associated to an @p EventListener. + * @details The flags are returned and the @p EventListener flags mask is + * cleared. + * + * @param[in] elp pointer to the @p EventListener structure + * @return The flags added to the listener by the associated + * event source. + * + * @iclass + */ +flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp) { + flagsmask_t flags; + + flags = elp->el_flags; + elp->el_flags = 0; + + return flags; +} + +/** + * @brief Invokes the event handlers associated to an event flags mask. + * + * @param[in] mask mask of the event flags to be dispatched + * @param[in] handlers an array of @p evhandler_t. The array must have size + * equal to the number of bits in eventmask_t. + * + * @api + */ +void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) { + eventid_t eid; + + chDbgCheck(handlers != NULL, "chEvtDispatch"); + + eid = 0; + while (mask) { + if (mask & EVENT_MASK(eid)) { + chDbgAssert(handlers[eid] != NULL, + "chEvtDispatch(), #1", + "null handler"); + mask &= ~EVENT_MASK(eid); + handlers[eid](eid); + } + eid++; + } +} + +#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits for exactly one of the specified events. + * @details The function waits for one event among those specified in + * @p mask to become pending then the event is cleared and returned. + * @note One and only one event is served in the function, the one with the + * lowest event id. The function is meant to be invoked into a loop in + * order to serve all the pending events.
    + * This means that Event Listeners with a lower event identifier have + * an higher priority. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @return The mask of the lowest id served and cleared event. + * + * @api + */ +eventmask_t chEvtWaitOne(eventmask_t mask) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTOREVT); + m = ctp->p_epending & mask; + } + m &= -m; + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p mask to become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @return The mask of the served and cleared events. + * + * @api + */ +eventmask_t chEvtWaitAny(eventmask_t mask) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTOREVT); + m = ctp->p_epending & mask; + } + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for all the specified events. + * @details The function waits for all the events specified in @p mask to + * become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS requires all the events + * @return The mask of the served and cleared events. + * + * @api + */ +eventmask_t chEvtWaitAll(eventmask_t mask) { + Thread *ctp = currp; + + chSysLock(); + + if ((ctp->p_epending & mask) != mask) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTANDEVT); + } + ctp->p_epending &= ~mask; + + chSysUnlock(); + return mask; +} +#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */ + +#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits for exactly one of the specified events. + * @details The function waits for one event among those specified in + * @p mask to become pending then the event is cleared and returned. + * @note One and only one event is served in the function, the one with the + * lowest event id. The function is meant to be invoked into a loop in + * order to serve all the pending events.
    + * This means that Event Listeners with a lower event identifier have + * an higher priority. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the lowest id served and cleared event. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + m = ctp->p_epending & mask; + } + m &= -m; + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p mask to become pending then the events are cleared and + * returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the served and cleared events. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + m = ctp->p_epending & mask; + } + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for all the specified events. + * @details The function waits for all the events specified in @p mask to + * become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS requires all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the served and cleared events. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + + chSysLock(); + + if ((ctp->p_epending & mask) != mask) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + } + ctp->p_epending &= ~mask; + + chSysUnlock(); + return mask; +} +#endif /* CH_USE_EVENTS_TIMEOUT */ + +#endif /* CH_USE_EVENTS */ + +/** @} */ diff --git a/os/kernel/src/chheap.c b/os/kernel/src/chheap.c new file mode 100644 index 000000000..23bcff6b4 --- /dev/null +++ b/os/kernel/src/chheap.c @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chheap.c + * @brief Heaps code. + * + * @addtogroup heaps + * @details Heap Allocator related APIs. + *

    Operation mode

    + * The heap allocator implements a first-fit strategy and its APIs + * are functionally equivalent to the usual @p malloc() and @p free() + * library functions. The main difference is that the OS heap APIs + * are guaranteed to be thread safe.
    + * By enabling the @p CH_USE_MALLOC_HEAP option the heap manager + * will use the runtime-provided @p malloc() and @p free() as + * back end for the heap APIs instead of the system provided + * allocator. + * @pre In order to use the heap APIs the @p CH_USE_HEAP option must + * be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_HEAP || defined(__DOXYGEN__) + +#if !CH_USE_MALLOC_HEAP || defined(__DOXYGEN__) + +/* + * Defaults on the best synchronization mechanism available. + */ +#if CH_USE_MUTEXES || defined(__DOXYGEN__) +#define H_LOCK(h) chMtxLock(&(h)->h_mtx) +#define H_UNLOCK(h) chMtxUnlock() +#else +#define H_LOCK(h) chSemWait(&(h)->h_sem) +#define H_UNLOCK(h) chSemSignal(&(h)->h_sem) +#endif + +/** + * @brief Default heap descriptor. + */ +static MemoryHeap default_heap; + +/** + * @brief Initializes the default heap. + * + * @notapi + */ +void _heap_init(void) { + default_heap.h_provider = chCoreAlloc; + default_heap.h_free.h.u.next = (union heap_header *)NULL; + default_heap.h_free.h.size = 0; +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + chMtxInit(&default_heap.h_mtx); +#else + chSemInit(&default_heap.h_sem, 1); +#endif +} + +/** + * @brief Initializes a memory heap from a static memory area. + * @pre Both the heap buffer base and the heap size must be aligned to + * the @p stkalign_t type size. + * @pre In order to use this function the option @p CH_USE_MALLOC_HEAP + * must be disabled. + * + * @param[out] heapp pointer to the memory heap descriptor to be initialized + * @param[in] buf heap buffer base + * @param[in] size heap size + * + * @init + */ +void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) { + union heap_header *hp; + + chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit"); + + heapp->h_provider = (memgetfunc_t)NULL; + heapp->h_free.h.u.next = hp = buf; + heapp->h_free.h.size = 0; + hp->h.u.next = NULL; + hp->h.size = size - sizeof(union heap_header); +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + chMtxInit(&heapp->h_mtx); +#else + chSemInit(&heapp->h_sem, 1); +#endif +} + +/** + * @brief Allocates a block of memory from the heap by using the first-fit + * algorithm. + * @details The allocated block is guaranteed to be properly aligned for a + * pointer data type (@p stkalign_t). + * + * @param[in] heapp pointer to a heap descriptor or @p NULL in order to + * access the default heap. + * @param[in] size the size of the block to be allocated. Note that the + * allocated block may be a bit bigger than the requested + * size for alignment and fragmentation reasons. + * @return A pointer to the allocated block. + * @retval NULL if the block cannot be allocated. + * + * @api + */ +void *chHeapAlloc(MemoryHeap *heapp, size_t size) { + union heap_header *qp, *hp, *fp; + + if (heapp == NULL) + heapp = &default_heap; + + size = MEM_ALIGN_NEXT(size); + qp = &heapp->h_free; + H_LOCK(heapp); + + while (qp->h.u.next != NULL) { + hp = qp->h.u.next; + if (hp->h.size >= size) { + if (hp->h.size < size + sizeof(union heap_header)) { + /* Gets the whole block even if it is slightly bigger than the + requested size because the fragment would be too small to be + useful.*/ + qp->h.u.next = hp->h.u.next; + } + else { + /* Block bigger enough, must split it.*/ + fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size); + fp->h.u.next = hp->h.u.next; + fp->h.size = hp->h.size - sizeof(union heap_header) - size; + qp->h.u.next = fp; + hp->h.size = size; + } + hp->h.u.heap = heapp; + + H_UNLOCK(heapp); + return (void *)(hp + 1); + } + qp = hp; + } + + H_UNLOCK(heapp); + + /* More memory is required, tries to get it from the associated provider + else fails.*/ + if (heapp->h_provider) { + hp = heapp->h_provider(size + sizeof(union heap_header)); + if (hp != NULL) { + hp->h.u.heap = heapp; + hp->h.size = size; + hp++; + return (void *)hp; + } + } + return NULL; +} + +#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \ + sizeof(union heap_header) + \ + (p)->h.size) + +/** + * @brief Frees a previously allocated memory block. + * + * @param[in] p pointer to the memory block to be freed + * + * @api + */ +void chHeapFree(void *p) { + union heap_header *qp, *hp; + MemoryHeap *heapp; + + chDbgCheck(p != NULL, "chHeapFree"); + + hp = (union heap_header *)p - 1; + heapp = hp->h.u.heap; + qp = &heapp->h_free; + H_LOCK(heapp); + + while (TRUE) { + chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), + "chHeapFree(), #1", + "within free block"); + + if (((qp == &heapp->h_free) || (hp > qp)) && + ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) { + /* Insertion after qp.*/ + hp->h.u.next = qp->h.u.next; + qp->h.u.next = hp; + /* Verifies if the newly inserted block should be merged.*/ + if (LIMIT(hp) == hp->h.u.next) { + /* Merge with the next block.*/ + hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header); + hp->h.u.next = hp->h.u.next->h.u.next; + } + if ((LIMIT(qp) == hp)) { + /* Merge with the previous block.*/ + qp->h.size += hp->h.size + sizeof(union heap_header); + qp->h.u.next = hp->h.u.next; + } + break; + } + qp = qp->h.u.next; + } + + H_UNLOCK(heapp); + return; +} + +/** + * @brief Reports the heap status. + * @note This function is meant to be used in the test suite, it should + * not be really useful for the application code. + * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP + * configuration option is used (it always returns zero). + * + * @param[in] heapp pointer to a heap descriptor or @p NULL in order to + * access the default heap. + * @param[in] sizep pointer to a variable that will receive the total + * fragmented free space + * @return The number of fragments in the heap. + * + * @api + */ +size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { + union heap_header *qp; + size_t n, sz; + + if (heapp == NULL) + heapp = &default_heap; + + H_LOCK(heapp); + + sz = 0; + for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next) + sz += qp->h.u.next->h.size; + if (sizep) + *sizep = sz; + + H_UNLOCK(heapp); + return n; +} + +#else /* CH_USE_MALLOC_HEAP */ + +#include + +#if CH_USE_MUTEXES +#define H_LOCK() chMtxLock(&hmtx) +#define H_UNLOCK() chMtxUnlock() +static Mutex hmtx; +#elif CH_USE_SEMAPHORES +#define H_LOCK() chSemWait(&hsem) +#define H_UNLOCK() chSemSignal(&hsem) +static Semaphore hsem; +#endif + +void _heap_init(void) { + +#if CH_USE_MUTEXES + chMtxInit(&hmtx); +#else + chSemInit(&hsem, 1); +#endif +} + +void *chHeapAlloc(MemoryHeap *heapp, size_t size) { + void *p; + + chDbgCheck(heapp == NULL, "chHeapAlloc"); + + H_LOCK(); + p = malloc(size); + H_UNLOCK(); + return p; +} + +void chHeapFree(void *p) { + + chDbgCheck(p != NULL, "chHeapFree"); + + H_LOCK(); + free(p); + H_UNLOCK(); +} + +size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { + + chDbgCheck(heapp == NULL, "chHeapStatus"); + + if (sizep) + *sizep = 0; + return 0; +} + +#endif /* CH_USE_MALLOC_HEAP */ + +#endif /* CH_USE_HEAP */ + +/** @} */ diff --git a/os/kernel/src/chlists.c b/os/kernel/src/chlists.c new file mode 100644 index 000000000..8ee309200 --- /dev/null +++ b/os/kernel/src/chlists.c @@ -0,0 +1,156 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chlists.c + * @brief Thread queues/lists code. + * + * @addtogroup internals + * @details All the functions present in this module, while public, are not + * OS APIs and should not be directly used in the user applications + * code. + * @{ + */ +#include "ch.h" + +#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +/** + * @brief Inserts a thread into a priority ordered queue. + * @note The insertion is done by scanning the list from the highest + * priority toward the lowest. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tqp the pointer to the threads list header + * + * @notapi + */ +void prio_insert(Thread *tp, ThreadsQueue *tqp) { + + /* cp iterates over the queue.*/ + Thread *cp = (Thread *)tqp; + do { + /* Iterate to next thread in queue.*/ + cp = cp->p_next; + /* Not end of queue? and cp has equal or higher priority than tp?.*/ + } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); + /* Insertion on p_prev.*/ + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; +} + +/** + * @brief Inserts a Thread into a queue. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tqp the pointer to the threads list header + * + * @notapi + */ +void queue_insert(Thread *tp, ThreadsQueue *tqp) { + + tp->p_next = (Thread *)tqp; + tp->p_prev = tqp->p_prev; + tp->p_prev->p_next = tqp->p_prev = tp; +} + +/** + * @brief Removes the first-out Thread from a queue and returns it. + * @note If the queue is priority ordered then this function returns the + * thread with the highest priority. + * + * @param[in] tqp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *fifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_next; + + (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; + return tp; +} + +/** + * @brief Removes the last-out Thread from a queue and returns it. + * @note If the queue is priority ordered then this function returns the + * thread with the lowest priority. + * + * @param[in] tqp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *lifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_prev; + + (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; + return tp; +} + +/** + * @brief Removes a Thread from a queue and returns it. + * @details The thread is removed from the queue regardless of its relative + * position and regardless the used insertion method. + * + * @param[in] tp the pointer to the thread to be removed from the queue + * @return The removed thread pointer. + * + * @notapi + */ +Thread *dequeue(Thread *tp) { + + tp->p_prev->p_next = tp->p_next; + tp->p_next->p_prev = tp->p_prev; + return tp; +} + +/** + * @brief Pushes a Thread on top of a stack list. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tlp the pointer to the threads list header + * + * @notapi + */ +void list_insert(Thread *tp, ThreadsList *tlp) { + + tp->p_next = tlp->p_next; + tlp->p_next = tp; +} + +/** + * @brief Pops a Thread from the top of a stack list and returns it. + * @pre The list must be non-empty before calling this function. + * + * @param[in] tlp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *list_remove(ThreadsList *tlp) { + + Thread *tp = tlp->p_next; + tlp->p_next = tp->p_next; + return tp; +} +#endif /* CH_OPTIMIZE_SPEED */ + +/** @} */ diff --git a/os/kernel/src/chmboxes.c b/os/kernel/src/chmboxes.c new file mode 100644 index 000000000..6f09a8d26 --- /dev/null +++ b/os/kernel/src/chmboxes.c @@ -0,0 +1,376 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmboxes.c + * @brief Mailboxes code. + * + * @addtogroup mailboxes + * @details Asynchronous messages. + *

    Operation mode

    + * A mailbox is an asynchronous communication mechanism.
    + * Operations defined for mailboxes: + * - Post: Posts a message on the mailbox in FIFO order. + * - Post Ahead: Posts a message on the mailbox with urgent + * priority. + * - Fetch: A message is fetched from the mailbox and removed + * from the queue. + * - Reset: The mailbox is emptied and all the stored messages + * are lost. + * . + * A message is a variable of type msg_t that is guaranteed to have + * the same size of and be compatible with (data) pointers (anyway an + * explicit cast is needed). + * If larger messages need to be exchanged then a pointer to a + * structure can be posted in the mailbox but the posting side has + * no predefined way to know when the message has been processed. A + * possible approach is to allocate memory (from a memory pool for + * example) from the posting side and free it on the fetching side. + * Another approach is to set a "done" flag into the structure pointed + * by the message. + * @pre In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option + * must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) +/** + * @brief Initializes a Mailbox object. + * + * @param[out] mbp the pointer to the Mailbox structure to be initialized + * @param[in] buf pointer to the messages buffer as an array of @p msg_t + * @param[in] n number of elements in the buffer array + * + * @init + */ +void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) { + + chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit"); + + mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf; + mbp->mb_top = &buf[n]; + chSemInit(&mbp->mb_emptysem, n); + chSemInit(&mbp->mb_fullsem, 0); +} + +/** + * @brief Resets a Mailbox object. + * @details All the waiting threads are resumed with status @p RDY_RESET and + * the queued messages are lost. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * + * @api + */ +void chMBReset(Mailbox *mbp) { + + chDbgCheck(mbp != NULL, "chMBReset"); + + chSysLock(); + mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer; + chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer); + chSemResetI(&mbp->mb_fullsem, 0); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBPostS(mbp, msg, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck(mbp != NULL, "chMBPostS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); + if (rdymsg == RDY_OK) { + *mbp->mb_wrptr++ = msg; + if (mbp->mb_wrptr >= mbp->mb_top) + mbp->mb_wrptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_fullsem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Posts a message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ +msg_t chMBPostI(Mailbox *mbp, msg_t msg) { + + chDbgCheckClassI(); + chDbgCheck(mbp != NULL, "chMBPostI"); + + if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_emptysem); + *mbp->mb_wrptr++ = msg; + if (mbp->mb_wrptr >= mbp->mb_top) + mbp->mb_wrptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_fullsem); + return RDY_OK; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBPostAheadS(mbp, msg, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck(mbp != NULL, "chMBPostAheadS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); + if (rdymsg == RDY_OK) { + if (--mbp->mb_rdptr < mbp->mb_buffer) + mbp->mb_rdptr = mbp->mb_top - 1; + *mbp->mb_rdptr = msg; + chSemSignalI(&mbp->mb_fullsem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ +msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg) { + + chDbgCheckClassI(); + chDbgCheck(mbp != NULL, "chMBPostAheadI"); + + if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_emptysem); + if (--mbp->mb_rdptr < mbp->mb_buffer) + mbp->mb_rdptr = mbp->mb_top - 1; + *mbp->mb_rdptr = msg; + chSemSignalI(&mbp->mb_fullsem); + return RDY_OK; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the mailbox + * or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBFetchS(mbp, msgp, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the mailbox + * or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time); + if (rdymsg == RDY_OK) { + *msgp = *mbp->mb_rdptr++; + if (mbp->mb_rdptr >= mbp->mb_top) + mbp->mb_rdptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_emptysem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is empty. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be + * fetched. + * + * @iclass + */ +msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) { + + chDbgCheckClassI(); + chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchI"); + + if (chSemGetCounterI(&mbp->mb_fullsem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_fullsem); + *msgp = *mbp->mb_rdptr++; + if (mbp->mb_rdptr >= mbp->mb_top) + mbp->mb_rdptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_emptysem); + return RDY_OK; +} +#endif /* CH_USE_MAILBOXES */ + +/** @} */ diff --git a/os/kernel/src/chmemcore.c b/os/kernel/src/chmemcore.c new file mode 100644 index 000000000..0ff26bc76 --- /dev/null +++ b/os/kernel/src/chmemcore.c @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmemcore.c + * @brief Core memory manager code. + * + * @addtogroup memcore + * @details Core Memory Manager related APIs and services. + *

    Operation mode

    + * The core memory manager is a simplified allocator that only + * allows to allocate memory blocks without the possibility to + * free them.
    + * This allocator is meant as a memory blocks provider for the + * other allocators such as: + * - C-Runtime allocator (through a compiler specific adapter module). + * - Heap allocator (see @ref heaps). + * - Memory pools allocator (see @ref pools). + * . + * By having a centralized memory provider the various allocators + * can coexist and share the main memory.
    + * This allocator, alone, is also useful for very simple + * applications that just require a simple way to get memory + * blocks. + * @pre In order to use the core memory manager APIs the @p CH_USE_MEMCORE + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MEMCORE || defined(__DOXYGEN__) + +static uint8_t *nextmem; +static uint8_t *endmem; + +/** + * @brief Low level memory manager initialization. + * + * @notapi + */ +void _core_init(void) { +#if CH_MEMCORE_SIZE == 0 + extern uint8_t __heap_base__[]; + extern uint8_t __heap_end__[]; + nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__); + endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__); +#else + static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; + nextmem = (uint8_t *)&buffer[0]; + endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; +#endif +} + +/** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less + * than MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @api + */ +void *chCoreAlloc(size_t size) { + void *p; + + chSysLock(); + p = chCoreAllocI(size); + chSysUnlock(); + return p; +} + +/** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less than + * MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated. + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @iclass + */ +void *chCoreAllocI(size_t size) { + void *p; + + chDbgCheckClassI(); + + size = MEM_ALIGN_NEXT(size); + if ((size_t)(endmem - nextmem) < size) + return NULL; + p = nextmem; + nextmem += size; + return p; +} + +/** + * @brief Core memory status. + * + * @return The size, in bytes, of the free core memory. + * + * @api + */ +size_t chCoreStatus(void) { + + return (size_t)(endmem - nextmem); +} +#endif /* CH_USE_MEMCORE */ + +/** @} */ diff --git a/os/kernel/src/chmempools.c b/os/kernel/src/chmempools.c new file mode 100644 index 000000000..44faa057a --- /dev/null +++ b/os/kernel/src/chmempools.c @@ -0,0 +1,173 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmempools.c + * @brief Memory Pools code. + * + * @addtogroup pools + * @details Memory Pools related APIs and services. + *

    Operation mode

    + * The Memory Pools APIs allow to allocate/free fixed size objects in + * constant time and reliably without memory fragmentation + * problems.
    + * Memory Pools do not enforce any alignment constraint on the + * contained object however the objects must be properly aligned + * to contain a pointer to void. + * @pre In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option + * must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +/** + * @brief Initializes an empty memory pool. + * + * @param[out] mp pointer to a @p MemoryPool structure + * @param[in] size the size of the objects contained in this memory pool, + * the minimum accepted size is the size of a pointer to + * void. + * @param[in] provider memory provider function for the memory pool or + * @p NULL if the pool is not allowed to grow + * automatically + * + * @init + */ +void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) { + + chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit"); + + mp->mp_next = NULL; + mp->mp_object_size = size; + mp->mp_provider = provider; +} + +/** + * @brief Loads a memory pool with an array of static objects. + * @pre The memory pool must be already been initialized. + * @pre The array elements must be of the right size for the specified + * memory pool. + * @post The memory pool contains the elements of the input array. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] p pointer to the array first element + * @param[in] n number of elements in the array + * + * @api + */ +void chPoolLoadArray(MemoryPool *mp, void *p, size_t n) { + + chDbgCheck((mp != NULL) && (n != 0), "chPoolLoadArray"); + + while (n) { + chPoolAdd(mp, p); + p = (void *)(((uint8_t *)p) + mp->mp_object_size); + n--; + } +} + +/** + * @brief Allocates an object from a memory pool. + * @pre The memory pool must be already been initialized. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @iclass + */ +void *chPoolAllocI(MemoryPool *mp) { + void *objp; + + chDbgCheckClassI(); + chDbgCheck(mp != NULL, "chPoolAllocI"); + + if ((objp = mp->mp_next) != NULL) + mp->mp_next = mp->mp_next->ph_next; + else if (mp->mp_provider != NULL) + objp = mp->mp_provider(mp->mp_object_size); + return objp; +} + +/** + * @brief Allocates an object from a memory pool. + * @pre The memory pool must be already been initialized. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @api + */ +void *chPoolAlloc(MemoryPool *mp) { + void *objp; + + chSysLock(); + objp = chPoolAllocI(mp); + chSysUnlock(); + return objp; +} + +/** + * @brief Releases an object into a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The freed object must be of the right size for the specified + * memory pool. + * @pre The object must be properly aligned to contain a pointer to void. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be released + * + * @iclass + */ +void chPoolFreeI(MemoryPool *mp, void *objp) { + struct pool_header *php = objp; + + chDbgCheckClassI(); + chDbgCheck((mp != NULL) && (objp != NULL), "chPoolFreeI"); + + php->ph_next = mp->mp_next; + mp->mp_next = php; +} + +/** + * @brief Releases an object into a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The freed object must be of the right size for the specified + * memory pool. + * @pre The object must be properly aligned to contain a pointer to void. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be released + * + * @api + */ +void chPoolFree(MemoryPool *mp, void *objp) { + + chSysLock(); + chPoolFreeI(mp, objp); + chSysUnlock(); +} + +#endif /* CH_USE_MEMPOOLS */ + +/** @} */ diff --git a/os/kernel/src/chmsg.c b/os/kernel/src/chmsg.c new file mode 100644 index 000000000..ad97da79c --- /dev/null +++ b/os/kernel/src/chmsg.c @@ -0,0 +1,132 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmsg.c + * @brief Messages code. + * + * @addtogroup messages + * @details Synchronous inter-thread messages APIs and services. + *

    Operation Mode

    + * Synchronous messages are an easy to use and fast IPC mechanism, + * threads can both act as message servers and/or message clients, + * the mechanism allows data to be carried in both directions. Note + * that messages are not copied between the client and server threads + * but just a pointer passed so the exchange is very time + * efficient.
    + * Messages are scalar data types of type @p msg_t that are guaranteed + * to be size compatible with data pointers. Note that on some + * architectures function pointers can be larger that @p msg_t.
    + * Messages are usually processed in FIFO order but it is possible to + * process them in priority order by enabling the + * @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.
    + * @pre In order to use the message APIs the @p CH_USE_MESSAGES option + * must be enabled in @p chconf.h. + * @post Enabling messages requires 6-12 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + +#if CH_USE_MESSAGES_PRIORITY +#define msg_insert(tp, qp) prio_insert(tp, qp) +#else +#define msg_insert(tp, qp) queue_insert(tp, qp) +#endif + +/** + * @brief Sends a message to the specified thread. + * @details The sender is stopped until the receiver executes a + * @p chMsgRelease()after receiving the message. + * + * @param[in] tp the pointer to the thread + * @param[in] msg the message + * @return The answer message from @p chMsgRelease(). + * + * @api + */ +msg_t chMsgSend(Thread *tp, msg_t msg) { + Thread *ctp = currp; + + chDbgCheck(tp != NULL, "chMsgSend"); + + chSysLock(); + ctp->p_msg = msg; + ctp->p_u.wtobjp = &tp->p_msgqueue; + msg_insert(ctp, &tp->p_msgqueue); + if (tp->p_state == THD_STATE_WTMSG) + chSchReadyI(tp); + chSchGoSleepS(THD_STATE_SNDMSGQ); + msg = ctp->p_u.rdymsg; + chSysUnlock(); + return msg; +} + +/** + * @brief Suspends the thread and waits for an incoming message. + * @post After receiving a message the function @p chMsgGet() must be + * called in order to retrieve the message and then @p chMsgRelease() + * must be invoked in order to acknowledge the reception and send + * the answer. + * @note If the message is a pointer then you can assume that the data + * pointed by the message is stable until you invoke @p chMsgRelease() + * because the sending thread is suspended until then. + * + * @return A reference to the thread carrying the message. + * + * @api + */ +Thread *chMsgWait(void) { + Thread *tp; + + chSysLock(); + if (!chMsgIsPendingI(currp)) + chSchGoSleepS(THD_STATE_WTMSG); + tp = fifo_remove(&currp->p_msgqueue); + tp->p_state = THD_STATE_SNDMSG; + chSysUnlock(); + return tp; +} + +/** + * @brief Releases a sender thread specifying a response message. + * @pre Invoke this function only after a message has been received + * using @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @param[in] msg message to be returned to the sender + * + * @api + */ +void chMsgRelease(Thread *tp, msg_t msg) { + + chSysLock(); + chDbgAssert(tp->p_state == THD_STATE_SNDMSG, + "chMsgRelease(), #1", "invalid state"); + chMsgReleaseS(tp, msg); + chSysUnlock(); +} + +#endif /* CH_USE_MESSAGES */ + +/** @} */ diff --git a/os/kernel/src/chmtx.c b/os/kernel/src/chmtx.c new file mode 100644 index 000000000..84d7e53a6 --- /dev/null +++ b/os/kernel/src/chmtx.c @@ -0,0 +1,393 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chmtx.c + * @brief Mutexes code. + * + * @addtogroup mutexes + * @details Mutexes related APIs and services. + * + *

    Operation mode

    + * A mutex is a threads synchronization object that can be in two + * distinct states: + * - Not owned (unlocked). + * - Owned by a thread (locked). + * . + * Operations defined for mutexes: + * - Lock: The mutex is checked, if the mutex is not owned by + * some other thread then it is associated to the locking thread + * else the thread is queued on the mutex in a list ordered by + * priority. + * - Unlock: The mutex is released by the owner and the highest + * priority thread waiting in the queue, if any, is resumed and made + * owner of the mutex. + * . + *

    Constraints

    + * In ChibiOS/RT the Unlock operations are always performed in + * lock-reverse order. The unlock API does not even have a parameter, + * the mutex to unlock is selected from an internal, per-thread, stack + * of owned mutexes. This both improves the performance and is + * required for an efficient implementation of the priority + * inheritance mechanism. + * + *

    The priority inversion problem

    + * The mutexes in ChibiOS/RT implements the full priority + * inheritance mechanism in order handle the priority inversion + * problem.
    + * When a thread is queued on a mutex, any thread, directly or + * indirectly, holding the mutex gains the same priority of the + * waiting thread (if their priority was not already equal or higher). + * The mechanism works with any number of nested mutexes and any + * number of involved threads. The algorithm complexity (worst case) + * is N with N equal to the number of nested mutexes. + * @pre In order to use the mutex APIs the @p CH_USE_MUTEXES option + * must be enabled in @p chconf.h. + * @post Enabling mutexes requires 5-12 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + +/** + * @brief Initializes s @p Mutex structure. + * + * @param[out] mp pointer to a @p Mutex structure + * + * @init + */ +void chMtxInit(Mutex *mp) { + + chDbgCheck(mp != NULL, "chMtxInit"); + + queue_init(&mp->m_queue); + mp->m_owner = NULL; +} + +/** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * + * @param[in] mp pointer to the @p Mutex structure + * + * @api + */ +void chMtxLock(Mutex *mp) { + + chSysLock(); + + chMtxLockS(mp); + + chSysUnlock(); +} + +/** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * + * @param[in] mp pointer to the @p Mutex structure + * + * @sclass + */ +void chMtxLockS(Mutex *mp) { + Thread *ctp = currp; + + chDbgCheckClassS(); + chDbgCheck(mp != NULL, "chMtxLockS"); + + /* Is the mutex already locked? */ + if (mp->m_owner != NULL) { + /* Priority inheritance protocol; explores the thread-mutex dependencies + boosting the priority of all the affected threads to equal the priority + of the running thread requesting the mutex.*/ + Thread *tp = mp->m_owner; + /* Does the running thread have higher priority than the mutex + owning thread? */ + while (tp->p_prio < ctp->p_prio) { + /* Make priority of thread tp match the running thread's priority.*/ + tp->p_prio = ctp->p_prio; + /* The following states need priority queues reordering.*/ + switch (tp->p_state) { + case THD_STATE_WTMTX: + /* Re-enqueues the mutex owner with its new priority.*/ + prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); + tp = ((Mutex *)tp->p_u.wtobjp)->m_owner; + continue; +#if CH_USE_CONDVARS | \ + (CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY) | \ + (CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY) +#if CH_USE_CONDVARS + case THD_STATE_WTCOND: +#endif +#if CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY + case THD_STATE_WTSEM: +#endif +#if CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY + case THD_STATE_SNDMSGQ: +#endif + /* Re-enqueues tp with its new priority on the queue.*/ + prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); + break; +#endif + case THD_STATE_READY: +#if CH_DBG_ENABLE_ASSERTS + /* Prevents an assertion in chSchReadyI().*/ + tp->p_state = THD_STATE_CURRENT; +#endif + /* Re-enqueues tp with its new priority on the ready list.*/ + chSchReadyI(dequeue(tp)); + break; + } + break; + } + /* Sleep on the mutex.*/ + prio_insert(ctp, &mp->m_queue); + ctp->p_u.wtobjp = mp; + chSchGoSleepS(THD_STATE_WTMTX); + /* It is assumed that the thread performing the unlock operation assigns + the mutex to this thread.*/ + chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner"); + chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned"); + } + else { + /* It was not owned, inserted in the owned mutexes list.*/ + mp->m_owner = ctp; + mp->m_next = ctp->p_mtxlist; + ctp->p_mtxlist = mp; + } +} + +/** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * locked by another thread then the function exits without waiting. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @param[in] mp pointer to the @p Mutex structure + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @api + */ +bool_t chMtxTryLock(Mutex *mp) { + bool_t b; + + chSysLock(); + + b = chMtxTryLockS(mp); + + chSysUnlock(); + return b; +} + +/** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * taken by another thread then the function exits without waiting. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @param[in] mp pointer to the @p Mutex structure + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @sclass + */ +bool_t chMtxTryLockS(Mutex *mp) { + + chDbgCheckClassS(); + chDbgCheck(mp != NULL, "chMtxTryLockS"); + + if (mp->m_owner != NULL) + return FALSE; + mp->m_owner = currp; + mp->m_next = currp->p_mtxlist; + currp->p_mtxlist = mp; + return TRUE; +} + +/** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * + * @return A pointer to the unlocked mutex. + * + * @api + */ +Mutex *chMtxUnlock(void) { + Thread *ctp = currp; + Mutex *ump, *mp; + + chSysLock(); + chDbgAssert(ctp->p_mtxlist != NULL, + "chMtxUnlock(), #1", + "owned mutexes list empty"); + chDbgAssert(ctp->p_mtxlist->m_owner == ctp, + "chMtxUnlock(), #2", + "ownership failure"); + /* Removes the top Mutex from the Thread's owned mutexes list and marks it + as not owned.*/ + ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + /* If a thread is waiting on the mutex then the fun part begins.*/ + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp; + + /* Recalculates the optimal thread priority by scanning the owned + mutexes list.*/ + tprio_t newprio = ctp->p_realprio; + mp = ctp->p_mtxlist; + while (mp != NULL) { + /* If the highest priority thread waiting in the mutexes list has a + greater priority than the current thread base priority then the final + priority will have at least that priority.*/ + if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) + newprio = mp->m_queue.p_next->p_prio; + mp = mp->m_next; + } + /* Assigns to the current thread the highest priority among all the + waiting threads.*/ + ctp->p_prio = newprio; + /* Awakens the highest priority thread waiting for the unlocked mutex and + assigns the mutex to it.*/ + tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchWakeupS(tp, RDY_OK); + } + else + ump->m_owner = NULL; + chSysUnlock(); + return ump; +} + +/** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. + * + * @return A pointer to the unlocked mutex. + * + * @sclass + */ +Mutex *chMtxUnlockS(void) { + Thread *ctp = currp; + Mutex *ump, *mp; + + chDbgCheckClassS(); + chDbgAssert(ctp->p_mtxlist != NULL, + "chMtxUnlockS(), #1", + "owned mutexes list empty"); + chDbgAssert(ctp->p_mtxlist->m_owner == ctp, + "chMtxUnlockS(), #2", + "ownership failure"); + + /* Removes the top Mutex from the owned mutexes list and marks it as not + owned.*/ + ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + /* If a thread is waiting on the mutex then the fun part begins.*/ + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp; + + /* Recalculates the optimal thread priority by scanning the owned + mutexes list.*/ + tprio_t newprio = ctp->p_realprio; + mp = ctp->p_mtxlist; + while (mp != NULL) { + /* If the highest priority thread waiting in the mutexes list has a + greater priority than the current thread base priority then the final + priority will have at least that priority.*/ + if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) + newprio = mp->m_queue.p_next->p_prio; + mp = mp->m_next; + } + ctp->p_prio = newprio; + /* Awakens the highest priority thread waiting for the unlocked mutex and + assigns the mutex to it.*/ + tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchReadyI(tp); + } + else + ump->m_owner = NULL; + return ump; +} + +/** + * @brief Unlocks all the mutexes owned by the invoking thread. + * @post The stack of owned mutexes is emptied and all the found + * mutexes are unlocked. + * @note This function is MUCH MORE efficient than releasing the + * mutexes one by one and not just because the call overhead, + * this function does not have any overhead related to the priority + * inheritance mechanism. + * + * @api + */ +void chMtxUnlockAll(void) { + Thread *ctp = currp; + + chSysLock(); + if (ctp->p_mtxlist != NULL) { + do { + Mutex *ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchReadyI(tp); + } + else + ump->m_owner = NULL; + } while (ctp->p_mtxlist != NULL); + ctp->p_prio = ctp->p_realprio; + chSchRescheduleS(); + } + chSysUnlock(); +} + +#endif /* CH_USE_MUTEXES */ + +/** @} */ diff --git a/os/kernel/src/chqueues.c b/os/kernel/src/chqueues.c new file mode 100644 index 000000000..871e499a0 --- /dev/null +++ b/os/kernel/src/chqueues.c @@ -0,0 +1,431 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chqueues.c + * @brief I/O Queues code. + * + * @addtogroup io_queues + * @details ChibiOS/RT queues are mostly used in serial-like device drivers. + * The device drivers are usually designed to have a lower side + * (lower driver, it is usually an interrupt service routine) and an + * upper side (upper driver, accessed by the application threads).
    + * There are several kind of queues:
    + * - Input queue, unidirectional queue where the writer is the + * lower side and the reader is the upper side. + * - Output queue, unidirectional queue where the writer is the + * upper side and the reader is the lower side. + * - Full duplex queue, bidirectional queue. Full duplex queues + * are implemented by pairing an input queue and an output queue + * together. + * . + * @pre In order to use the I/O queues the @p CH_USE_QUEUES option must + * be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + +/** + * @brief Puts the invoking thread into the queue's threads queue. + * + * @param[out] qp pointer to an @p GenericQueue structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from threads queue. + * @retval Q_OK is the normal exit, thread signaled. + * @retval Q_RESET if the queue has been reset. + * @retval Q_TIMEOUT if the queue operation timed out. + */ +static msg_t qwait(GenericQueue *qp, systime_t time) { + + if (TIME_IMMEDIATE == time) + return Q_TIMEOUT; + currp->p_u.wtobjp = qp; + queue_insert(currp, &qp->q_waiting); + return chSchGoSleepTimeoutS(THD_STATE_WTQUEUE, time); +} + +/** + * @brief Initializes an input queue. + * @details A Semaphore is internally initialized and works as a counter of + * the bytes contained in the queue. + * @note The callback is invoked from within the S-Locked system state, + * see @ref system_states. + * + * @param[out] iqp pointer to an @p InputQueue structure + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] infy pointer to a callback function that is invoked when + * data is read from the queue. The value can be @p NULL. + * @param[in] link application defined pointer + * + * @init + */ +void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy, + void *link) { + + queue_init(&iqp->q_waiting); + iqp->q_counter = 0; + iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp; + iqp->q_top = bp + size; + iqp->q_notify = infy; + iqp->q_link = link; +} + +/** + * @brief Resets an input queue. + * @details All the data in the input queue is erased and lost, any waiting + * thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order to + * obtain immediate attention from the high level layers. + * + * @param[in] iqp pointer to an @p InputQueue structure + * + * @iclass + */ +void chIQResetI(InputQueue *iqp) { + + chDbgCheckClassI(); + + iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer; + iqp->q_counter = 0; + while (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_RESET; +} + +/** + * @brief Input queue write. + * @details A byte value is written into the low end of an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation has been completed with success. + * @retval Q_FULL if the queue is full and the operation cannot be + * completed. + * + * @iclass + */ +msg_t chIQPutI(InputQueue *iqp, uint8_t b) { + + chDbgCheckClassI(); + + if (chIQIsFullI(iqp)) + return Q_FULL; + + iqp->q_counter++; + *iqp->q_wrptr++ = b; + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + + if (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; + + return Q_OK; +} + +/** + * @brief Input queue read with timeout. + * @details This function reads a byte value from an input queue. If the queue + * is empty then the calling thread is suspended until a byte arrives + * in the queue or a timeout occurs. + * @note The callback is invoked before reading the character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A byte value from the queue. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { + uint8_t b; + + chSysLock(); + if (iqp->q_notify) + iqp->q_notify(iqp); + + while (chIQIsEmptyI(iqp)) { + msg_t msg; + if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) { + chSysUnlock(); + return msg; + } + } + + iqp->q_counter--; + b = *iqp->q_rdptr++; + if (iqp->q_rdptr >= iqp->q_top) + iqp->q_rdptr = iqp->q_buffer; + + chSysUnlock(); + return b; +} + +/** + * @brief Input queue read with timeout. + * @details The function reads data from an input queue into a buffer. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is suggested + * to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked before reading each character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ +size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, + size_t n, systime_t time) { + qnotify_t nfy = iqp->q_notify; + size_t r = 0; + + chDbgCheck(n > 0, "chIQReadTimeout"); + + chSysLock(); + while (TRUE) { + if (nfy) + nfy(iqp); + + while (chIQIsEmptyI(iqp)) { + if (qwait((GenericQueue *)iqp, time) != Q_OK) { + chSysUnlock(); + return r; + } + } + + iqp->q_counter--; + *bp++ = *iqp->q_rdptr++; + if (iqp->q_rdptr >= iqp->q_top) + iqp->q_rdptr = iqp->q_buffer; + + chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ + r++; + if (--n == 0) + return r; + + chSysLock(); + } +} + +/** + * @brief Initializes an output queue. + * @details A Semaphore is internally initialized and works as a counter of + * the free bytes in the queue. + * @note The callback is invoked from within the S-Locked system state, + * see @ref system_states. + * + * @param[out] oqp pointer to an @p OutputQueue structure + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] onfy pointer to a callback function that is invoked when + * data is written to the queue. The value can be @p NULL. + * @param[in] link application defined pointer + * + * @init + */ +void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy, + void *link) { + + queue_init(&oqp->q_waiting); + oqp->q_counter = size; + oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp; + oqp->q_top = bp + size; + oqp->q_notify = onfy; + oqp->q_link = link; +} + +/** + * @brief Resets an output queue. + * @details All the data in the output queue is erased and lost, any waiting + * thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order to + * obtain immediate attention from the high level layers. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * + * @iclass + */ +void chOQResetI(OutputQueue *oqp) { + + chDbgCheckClassI(); + + oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer; + oqp->q_counter = chQSizeI(oqp); + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_RESET; +} + +/** + * @brief Output queue write with timeout. + * @details This function writes a byte value to an output queue. If the queue + * is full then the calling thread is suspended until there is space + * in the queue or a timeout occurs. + * @note The callback is invoked after writing the character into the + * buffer. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[in] b the byte value to be written in the queue + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) { + + chSysLock(); + while (chOQIsFullI(oqp)) { + msg_t msg; + + if ((msg = qwait((GenericQueue *)oqp, time)) < Q_OK) { + chSysUnlock(); + return msg; + } + } + + oqp->q_counter--; + *oqp->q_wrptr++ = b; + if (oqp->q_wrptr >= oqp->q_top) + oqp->q_wrptr = oqp->q_buffer; + + if (oqp->q_notify) + oqp->q_notify(oqp); + + chSysUnlock(); + return Q_OK; +} + +/** + * @brief Output queue read. + * @details A byte value is read from the low end of an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The byte value from the queue. + * @retval Q_EMPTY if the queue is empty. + * + * @iclass + */ +msg_t chOQGetI(OutputQueue *oqp) { + uint8_t b; + + chDbgCheckClassI(); + + if (chOQIsEmptyI(oqp)) + return Q_EMPTY; + + oqp->q_counter++; + b = *oqp->q_rdptr++; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + + if (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + + return b; +} + +/** + * @brief Output queue write with timeout. + * @details The function writes data from a buffer to an output queue. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is suggested + * to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked after writing each character into the + * buffer. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ +size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, + size_t n, systime_t time) { + qnotify_t nfy = oqp->q_notify; + size_t w = 0; + + chDbgCheck(n > 0, "chOQWriteTimeout"); + + chSysLock(); + while (TRUE) { + while (chOQIsFullI(oqp)) { + if (qwait((GenericQueue *)oqp, time) != Q_OK) { + chSysUnlock(); + return w; + } + } + oqp->q_counter--; + *oqp->q_wrptr++ = *bp++; + if (oqp->q_wrptr >= oqp->q_top) + oqp->q_wrptr = oqp->q_buffer; + + if (nfy) + nfy(oqp); + + chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ + w++; + if (--n == 0) + return w; + chSysLock(); + } +} +#endif /* CH_USE_QUEUES */ + +/** @} */ diff --git a/os/kernel/src/chregistry.c b/os/kernel/src/chregistry.c new file mode 100644 index 000000000..645172833 --- /dev/null +++ b/os/kernel/src/chregistry.c @@ -0,0 +1,156 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chregistry.c + * @brief Threads registry code. + * + * @addtogroup registry + * @details Threads Registry related APIs and services. + * + *

    Operation mode

    + * The Threads Registry is a double linked list that holds all the + * active threads in the system.
    + * Operations defined for the registry: + * - First, returns the first, in creation order, active thread + * in the system. + * - Next, returns the next, in creation order, active thread + * in the system. + * . + * The registry is meant to be mainly a debug feature, for example, + * using the registry a debugger can enumerate the active threads + * in any given moment or the shell can print the active threads + * and their state.
    + * Another possible use is for centralized threads memory management, + * terminating threads can pulse an event source and an event handler + * can perform a scansion of the registry in order to recover the + * memory. + * @pre In order to use the threads registry the @p CH_USE_REGISTRY option + * must be enabled in @p chconf.h. + * @{ + */ +#include "ch.h" + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + +#define _offsetof(st, m) \ + ((size_t)((char *)&((st *)0)->m - (char *)0)) + +/* + * OS signature in ROM plus debug-related information. + */ +ROMCONST chdebug_t ch_debug = { + "main", + (uint8_t)0, + (uint8_t)sizeof (chdebug_t), + (uint16_t)((CH_KERNEL_MAJOR << 11) | + (CH_KERNEL_MINOR << 6) | + (CH_KERNEL_PATCH) << 0), + (uint8_t)sizeof (void *), + (uint8_t)sizeof (systime_t), + (uint8_t)sizeof (Thread), + (uint8_t)_offsetof(Thread, p_prio), + (uint8_t)_offsetof(Thread, p_ctx), + (uint8_t)_offsetof(Thread, p_newer), + (uint8_t)_offsetof(Thread, p_older), + (uint8_t)_offsetof(Thread, p_name), +#if CH_DBG_ENABLE_STACK_CHECK + (uint8_t)_offsetof(Thread, p_stklimit), +#else + (uint8_t)0, +#endif + (uint8_t)_offsetof(Thread, p_state), + (uint8_t)_offsetof(Thread, p_flags), +#if CH_USE_DYNAMIC + (uint8_t)_offsetof(Thread, p_refs), +#else + (uint8_t)0, +#endif +#if CH_TIME_QUANTUM > 0 + (uint8_t)_offsetof(Thread, p_preempt), +#else + (uint8_t)0, +#endif +#if CH_DBG_THREADS_PROFILING + (uint8_t)_offsetof(Thread, p_time) +#else + (uint8_t)0 +#endif +}; + +/** + * @brief Returns the first thread in the system. + * @details Returns the most ancient thread in the system, usually this is + * the main thread unless it terminated. A reference is added to the + * returned thread in order to make sure its status is not lost. + * @note This function cannot return @p NULL because there is always at + * least one thread in the system. + * + * @return A reference to the most ancient thread. + * + * @api + */ +Thread *chRegFirstThread(void) { + Thread *tp; + + chSysLock(); + tp = rlist.r_newer; +#if CH_USE_DYNAMIC + tp->p_refs++; +#endif + chSysUnlock(); + return tp; +} + +/** + * @brief Returns the thread next to the specified one. + * @details The reference counter of the specified thread is decremented and + * the reference counter of the returned thread is incremented. + * + * @param[in] tp pointer to the thread + * @return A reference to the next thread. + * @retval NULL if there is no next thread. + * + * @api + */ +Thread *chRegNextThread(Thread *tp) { + Thread *ntp; + + chSysLock(); + ntp = tp->p_newer; + if (ntp == (Thread *)&rlist) + ntp = NULL; +#if CH_USE_DYNAMIC + else { + chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1", + "too many references"); + ntp->p_refs++; + } +#endif + chSysUnlock(); +#if CH_USE_DYNAMIC + chThdRelease(tp); +#endif + return ntp; +} + +#endif /* CH_USE_REGISTRY */ + +/** @} */ diff --git a/os/kernel/src/chschd.c b/os/kernel/src/chschd.c new file mode 100644 index 000000000..1106cf03f --- /dev/null +++ b/os/kernel/src/chschd.c @@ -0,0 +1,378 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chschd.c + * @brief Scheduler code. + * + * @addtogroup scheduler + * @details This module provides the default portable scheduler code, + * scheduler functions can be individually captured by the port + * layer in order to provide architecture optimized equivalents. + * When a function is captured its default code is not built into + * the OS image, the optimized version is included instead. + * @{ + */ + +#include "ch.h" + +/** + * @brief Ready list header. + */ +#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__) +ReadyList rlist; +#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */ + +/** + * @brief Scheduler initialization. + * + * @notapi + */ +void _scheduler_init(void) { + + queue_init(&rlist.r_queue); + rlist.r_prio = NOPRIO; +#if CH_USE_REGISTRY + rlist.r_newer = rlist.r_older = (Thread *)&rlist; +#endif +} + +/** + * @brief Inserts a thread in the Ready List. + * @details The thread is positioned behind all threads with higher or equal + * priority. + * @pre The thread must not be already inserted in any list through its + * @p p_next and @p p_prev or list corruption would occur. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] tp the thread to be made ready + * @return The thread pointer. + * + * @iclass + */ +#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__) +Thread *chSchReadyI(Thread *tp) { + Thread *cp; + + chDbgCheckClassI(); + + /* Integrity checks.*/ + chDbgAssert((tp->p_state != THD_STATE_READY) && + (tp->p_state != THD_STATE_FINAL), + "chSchReadyI(), #1", + "invalid state"); + + tp->p_state = THD_STATE_READY; + cp = (Thread *)&rlist.r_queue; + do { + cp = cp->p_next; + } while (cp->p_prio >= tp->p_prio); + /* Insertion on p_prev.*/ + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; + return tp; +} +#endif /* !defined(PORT_OPTIMIZED_READYI) */ + +/** + * @brief Puts the current thread to sleep into the specified state. + * @details The thread goes into a sleeping state. The possible + * @ref thread_states are defined into @p threads.h. + * + * @param[in] newstate the new thread state + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__) +void chSchGoSleepS(tstate_t newstate) { + Thread *otp; + + chDbgCheckClassS(); + + (otp = currp)->p_state = newstate; +#if CH_TIME_QUANTUM > 0 + /* The thread is renouncing its remaining time slices so it will have a new + time quantum when it will wakeup.*/ + otp->p_preempt = CH_TIME_QUANTUM; +#endif + setcurrp(fifo_remove(&rlist.r_queue)); + currp->p_state = THD_STATE_CURRENT; + chSysSwitch(currp, otp); +} +#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */ + +#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__) +/* + * Timeout wakeup callback. + */ +static void wakeup(void *p) { + Thread *tp = (Thread *)p; + + chSysLockFromIsr(); + switch (tp->p_state) { + case THD_STATE_READY: + /* Handling the special case where the thread has been made ready by + another thread with higher priority.*/ + chSysUnlockFromIsr(); + return; +#if CH_USE_SEMAPHORES || CH_USE_QUEUES || \ + (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT) +#if CH_USE_SEMAPHORES + case THD_STATE_WTSEM: + chSemFastSignalI((Semaphore *)tp->p_u.wtobjp); + /* Falls into, intentional. */ +#endif +#if CH_USE_QUEUES + case THD_STATE_WTQUEUE: +#endif +#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT + case THD_STATE_WTCOND: +#endif + /* States requiring dequeuing.*/ + dequeue(tp); +#endif + } + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + chSysUnlockFromIsr(); +} + +/** + * @brief Puts the current thread to sleep into the specified state with + * timeout specification. + * @details The thread goes into a sleeping state, if it is not awakened + * explicitly within the specified timeout then it is forcibly + * awakened with a @p RDY_TIMEOUT low level message. The possible + * @ref thread_states are defined into @p threads.h. + * + * @param[in] newstate the new thread state + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state, this is equivalent to invoking + * @p chSchGoSleepS() but, of course, less efficient. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return The wakeup message. + * @retval RDY_TIMEOUT if a timeout occurs. + * + * @sclass + */ +msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) { + + chDbgCheckClassS(); + + if (TIME_INFINITE != time) { + VirtualTimer vt; + + chVTSetI(&vt, time, wakeup, currp); + chSchGoSleepS(newstate); + if (chVTIsArmedI(&vt)) + chVTResetI(&vt); + } + else + chSchGoSleepS(newstate); + return currp->p_u.rdymsg; +} +#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */ + +/** + * @brief Wakes up a thread. + * @details The thread is inserted into the ready list or immediately made + * running depending on its relative priority compared to the current + * thread. + * @pre The thread must not be already inserted in any list through its + * @p p_next and @p p_prev or list corruption would occur. + * @note It is equivalent to a @p chSchReadyI() followed by a + * @p chSchRescheduleS() but much more efficient. + * @note The function assumes that the current thread has the highest + * priority. + * + * @param[in] ntp the Thread to be made ready + * @param[in] msg message to the awakened thread + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__) +void chSchWakeupS(Thread *ntp, msg_t msg) { + + chDbgCheckClassS(); + + ntp->p_u.rdymsg = msg; + /* If the waken thread has a not-greater priority than the current + one then it is just inserted in the ready list else it made + running immediately and the invoking thread goes in the ready + list instead.*/ + if (ntp->p_prio <= currp->p_prio) + chSchReadyI(ntp); + else { + Thread *otp = chSchReadyI(currp); + setcurrp(ntp); + ntp->p_state = THD_STATE_CURRENT; + chSysSwitch(ntp, otp); + } +} +#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */ + +/** + * @brief Performs a reschedule if a higher priority thread is runnable. + * @details If a thread with a higher priority than the current thread is in + * the ready list then make the higher priority thread running. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__) +void chSchRescheduleS(void) { + + chDbgCheckClassS(); + + if (chSchIsRescRequiredI()) + chSchDoRescheduleAhead(); +} +#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */ + +/** + * @brief Evaluates if preemption is required. + * @details The decision is taken by comparing the relative priorities and + * depending on the state of the round robin timeout counter. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @retval TRUE if there is a thread that must go in running state + * immediately. + * @retval FALSE if preemption is not required. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) || defined(__DOXYGEN__) +bool_t chSchIsPreemptionRequired(void) { + tprio_t p1 = firstprio(&rlist.r_queue); + tprio_t p2 = currp->p_prio; +#if CH_TIME_QUANTUM > 0 + /* If the running thread has not reached its time quantum, reschedule only + if the first thread on the ready queue has a higher priority. + Otherwise, if the running thread has used up its time quantum, reschedule + if the first thread on the ready queue has equal or higher priority.*/ + return currp->p_preempt ? p1 > p2 : p1 >= p2; +#else + /* If the round robin preemption feature is not enabled then performs a + simpler comparison.*/ + return p1 > p2; +#endif +} +#endif /* !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) */ + +/** + * @brief Switches to the first thread on the runnable queue. + * @details The current thread is positioned in the ready list behind all + * threads having the same priority. The thread regains its time + * quantum. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__) +void chSchDoRescheduleBehind(void) { + Thread *otp; + + otp = currp; + /* Picks the first thread from the ready queue and makes it current.*/ + setcurrp(fifo_remove(&rlist.r_queue)); + currp->p_state = THD_STATE_CURRENT; +#if CH_TIME_QUANTUM > 0 + otp->p_preempt = CH_TIME_QUANTUM; +#endif + chSchReadyI(otp); + chSysSwitch(currp, otp); +} +#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) */ + +/** + * @brief Switches to the first thread on the runnable queue. + * @details The current thread is positioned in the ready list ahead of all + * threads having the same priority. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__) +void chSchDoRescheduleAhead(void) { + Thread *otp, *cp; + + otp = currp; + /* Picks the first thread from the ready queue and makes it current.*/ + setcurrp(fifo_remove(&rlist.r_queue)); + currp->p_state = THD_STATE_CURRENT; + + otp->p_state = THD_STATE_READY; + cp = (Thread *)&rlist.r_queue; + do { + cp = cp->p_next; + } while (cp->p_prio > otp->p_prio); + /* Insertion on p_prev.*/ + otp->p_next = cp; + otp->p_prev = cp->p_prev; + otp->p_prev->p_next = cp->p_prev = otp; + + chSysSwitch(currp, otp); +} +#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) */ + +/** + * @brief Switches to the first thread on the runnable queue. + * @details The current thread is positioned in the ready list behind or + * ahead of all threads having the same priority depending on + * if it used its whole time slice. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_DORESCHEDULE) || defined(__DOXYGEN__) +void chSchDoReschedule(void) { + +#if CH_TIME_QUANTUM > 0 + /* If CH_TIME_QUANTUM is enabled then there are two different scenarios to + handle on preemption: time quantum elapsed or not.*/ + if (currp->p_preempt == 0) { + /* The thread consumed its time quantum so it is enqueued behind threads + with same priority level, however, it acquires a new time quantum.*/ + chSchDoRescheduleBehind(); + } + else { + /* The thread didn't consume all its time quantum so it is put ahead of + threads with equal priority and does not acquire a new time quantum.*/ + chSchDoRescheduleAhead(); + } +#else /* !(CH_TIME_QUANTUM > 0) */ + /* If the round-robin mechanism is disabled then the thread goes always + ahead of its peers.*/ + chSchDoRescheduleAhead(); +#endif /* !(CH_TIME_QUANTUM > 0) */ +} +#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULE) */ + +/** @} */ diff --git a/os/kernel/src/chsem.c b/os/kernel/src/chsem.c new file mode 100644 index 000000000..2dc7ee354 --- /dev/null +++ b/os/kernel/src/chsem.c @@ -0,0 +1,393 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chsem.c + * @brief Semaphores code. + * + * @addtogroup semaphores + * @details Semaphores related APIs and services. + * + *

    Operation mode

    + * Semaphores are a flexible synchronization primitive, ChibiOS/RT + * implements semaphores in their "counting semaphores" variant as + * defined by Edsger Dijkstra plus several enhancements like: + * - Wait operation with timeout. + * - Reset operation. + * - Atomic wait+signal operation. + * - Return message from the wait operation (OK, RESET, TIMEOUT). + * . + * The binary semaphores variant can be easily implemented using + * counting semaphores.
    + * Operations defined for semaphores: + * - Signal: The semaphore counter is increased and if the + * result is non-positive then a waiting thread is removed from + * the semaphore queue and made ready for execution. + * - Wait: The semaphore counter is decreased and if the result + * becomes negative the thread is queued in the semaphore and + * suspended. + * - Reset: The semaphore counter is reset to a non-negative + * value and all the threads in the queue are released. + * . + * Semaphores can be used as guards for mutual exclusion zones + * (note that mutexes are recommended for this kind of use) but + * also have other uses, queues guards and counters for example.
    + * Semaphores usually use a FIFO queuing strategy but it is possible + * to make them order threads by priority by enabling + * @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h. + * @pre In order to use the semaphore APIs the @p CH_USE_SEMAPHORES + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +#if CH_USE_SEMAPHORES_PRIORITY +#define sem_insert(tp, qp) prio_insert(tp, qp) +#else +#define sem_insert(tp, qp) queue_insert(tp, qp) +#endif + +/** + * @brief Initializes a semaphore with the specified counter value. + * + * @param[out] sp pointer to a @p Semaphore structure + * @param[in] n initial value of the semaphore counter. Must be + * non-negative. + * + * @init + */ +void chSemInit(Semaphore *sp, cnt_t n) { + + chDbgCheck((sp != NULL) && (n >= 0), "chSemInit"); + + queue_init(&sp->s_queue); + sp->s_cnt = n; +} + +/** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is set + * to the specified, non negative, value. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p chSemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n the new value of the semaphore counter. The value must + * be non-negative. + * + * @api + */ +void chSemReset(Semaphore *sp, cnt_t n) { + + chSysLock(); + chSemResetI(sp, n); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is set + * to the specified, non negative, value. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p chSemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n the new value of the semaphore counter. The value must + * be non-negative. + * + * @iclass + */ +void chSemResetI(Semaphore *sp, cnt_t n) { + cnt_t cnt; + + chDbgCheckClassI(); + chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemResetI(), #1", + "inconsistent semaphore"); + + cnt = sp->s_cnt; + sp->s_cnt = n; + while (++cnt <= 0) + chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET; +} + +/** + * @brief Performs a wait operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @api + */ +msg_t chSemWait(Semaphore *sp) { + msg_t msg; + + chSysLock(); + msg = chSemWaitS(sp); + chSysUnlock(); + return msg; +} + +/** + * @brief Performs a wait operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @sclass + */ +msg_t chSemWaitS(Semaphore *sp) { + + chDbgCheckClassS(); + chDbgCheck(sp != NULL, "chSemWaitS"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemWaitS(), #1", + "inconsistent semaphore"); + + if (--sp->s_cnt < 0) { + currp->p_u.wtobjp = sp; + sem_insert(currp, &sp->s_queue); + chSchGoSleepS(THD_STATE_WTSEM); + return currp->p_u.rdymsg; + } + return RDY_OK; +} + +/** + * @brief Performs a wait operation on a semaphore with timeout specification. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within + * the specified timeout. + * + * @api + */ +msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) { + msg_t msg; + + chSysLock(); + msg = chSemWaitTimeoutS(sp, time); + chSysUnlock(); + return msg; +} + +/** + * @brief Performs a wait operation on a semaphore with timeout specification. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within + * the specified timeout. + * + * @sclass + */ +msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) { + + chDbgCheckClassS(); + chDbgCheck(sp != NULL, "chSemWaitTimeoutS"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemWaitTimeoutS(), #1", + "inconsistent semaphore"); + + if (--sp->s_cnt < 0) { + if (TIME_IMMEDIATE == time) { + sp->s_cnt++; + return RDY_TIMEOUT; + } + currp->p_u.wtobjp = sp; + sem_insert(currp, &sp->s_queue); + return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time); + } + return RDY_OK; +} + +/** + * @brief Performs a signal operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * + * @api + */ +void chSemSignal(Semaphore *sp) { + + chDbgCheck(sp != NULL, "chSemSignal"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemSignal(), #1", + "inconsistent semaphore"); + + chSysLock(); + if (++sp->s_cnt <= 0) + chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK); + chSysUnlock(); +} + +/** + * @brief Performs a signal operation on a semaphore. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] sp pointer to a @p Semaphore structure + * + * @iclass + */ +void chSemSignalI(Semaphore *sp) { + + chDbgCheckClassI(); + chDbgCheck(sp != NULL, "chSemSignalI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemSignalI(), #1", + "inconsistent semaphore"); + + if (++sp->s_cnt <= 0) { + /* Note, it is done this way in order to allow a tail call on + chSchReadyI().*/ + Thread *tp = fifo_remove(&sp->s_queue); + tp->p_u.rdymsg = RDY_OK; + chSchReadyI(tp); + } +} + +/** + * @brief Adds the specified value to the semaphore counter. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n value to be added to the semaphore counter. The value + * must be positive. + * + * @iclass + */ +void chSemAddCounterI(Semaphore *sp, cnt_t n) { + + chDbgCheckClassI(); + chDbgCheck((sp != NULL) && (n > 0), "chSemAddCounterI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemAddCounterI(), #1", + "inconsistent semaphore"); + + while (n > 0) { + if (++sp->s_cnt <= 0) + chSchReadyI(fifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK; + n--; + } +} + +#if CH_USE_SEMSW +/** + * @brief Performs atomic signal and wait operations on two semaphores. + * @pre The configuration option @p CH_USE_SEMSW must be enabled in order + * to use this function. + * + * @param[in] sps pointer to a @p Semaphore structure to be signaled + * @param[in] spw pointer to a @p Semaphore structure to wait on + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @api + */ +msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) { + msg_t msg; + + chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait"); + chDbgAssert(((sps->s_cnt >= 0) && isempty(&sps->s_queue)) || + ((sps->s_cnt < 0) && notempty(&sps->s_queue)), + "chSemSignalWait(), #1", + "inconsistent semaphore"); + chDbgAssert(((spw->s_cnt >= 0) && isempty(&spw->s_queue)) || + ((spw->s_cnt < 0) && notempty(&spw->s_queue)), + "chSemSignalWait(), #2", + "inconsistent semaphore"); + + chSysLock(); + if (++sps->s_cnt <= 0) + chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK; + if (--spw->s_cnt < 0) { + Thread *ctp = currp; + sem_insert(ctp, &spw->s_queue); + ctp->p_u.wtobjp = spw; + chSchGoSleepS(THD_STATE_WTSEM); + msg = ctp->p_u.rdymsg; + } + else { + chSchRescheduleS(); + msg = RDY_OK; + } + chSysUnlock(); + return msg; +} +#endif /* CH_USE_SEMSW */ + +#endif /* CH_USE_SEMAPHORES */ + +/** @} */ diff --git a/os/kernel/src/chsys.c b/os/kernel/src/chsys.c new file mode 100644 index 000000000..a6f1d15ba --- /dev/null +++ b/os/kernel/src/chsys.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chsys.c + * @brief System related code. + * + * @addtogroup system + * @details System related APIs and services: + * - Initialization. + * - Locks. + * - Interrupt Handling. + * - Power Management. + * - Abnormal Termination. + * . + * @{ + */ + +#include "ch.h" + +#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) +/** + * @brief Idle thread working area. + */ +WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); + +/** + * @brief This function implements the idle thread infinite loop. + * @details The function puts the processor in the lowest power mode capable + * to serve interrupts.
    + * The priority is internally set to the minimum system value so + * that this thread is executed only if there are no other ready + * threads in the system. + * + * @param[in] p the thread parameter, unused in this scenario + */ +void _idle_thread(void *p) { + + (void)p; + chRegSetThreadName("idle"); + while (TRUE) { + port_wait_for_interrupt(); + IDLE_LOOP_HOOK(); + } +} +#endif /* CH_NO_IDLE_THREAD */ + +/** + * @brief ChibiOS/RT initialization. + * @details After executing this function the current instructions stream + * becomes the main thread. + * @pre Interrupts must be still disabled when @p chSysInit() is invoked + * and are internally enabled. + * @post The main thread is created with priority @p NORMALPRIO. + * @note This function has special, architecture-dependent, requirements, + * see the notes into the various port reference manuals. + * + * @special + */ +void chSysInit(void) { + static Thread mainthread; +#if CH_DBG_ENABLE_STACK_CHECK + extern stkalign_t __main_thread_stack_base__; +#endif + + port_init(); + _scheduler_init(); + _vt_init(); +#if CH_USE_MEMCORE + _core_init(); +#endif +#if CH_USE_HEAP + _heap_init(); +#endif +#if CH_DBG_ENABLE_TRACE + _trace_init(); +#endif + + /* Now this instructions flow becomes the main thread.*/ + setcurrp(_thread_init(&mainthread, NORMALPRIO)); + currp->p_state = THD_STATE_CURRENT; +#if CH_DBG_ENABLE_STACK_CHECK + /* This is a special case because the main thread Thread structure is not + adjacent to its stack area.*/ + currp->p_stklimit = &__main_thread_stack_base__; +#endif + chSysEnable(); + + /* Note, &ch_debug points to the string "main" if the registry is + active, else the parameter is ignored.*/ + chRegSetThreadName((const char *)&ch_debug); + +#if !CH_NO_IDLE_THREAD + /* This thread has the lowest priority in the system, its role is just to + serve interrupts in its context while keeping the lowest energy saving + mode compatible with the system status.*/ + chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO, + (tfunc_t)_idle_thread, NULL); +#endif +} + +/** + * @brief Handles time ticks for round robin preemption and timer increments. + * @details Decrements the remaining time quantum of the running thread + * and preempts it when the quantum is used up. Increments system + * time and manages the timers. + * @note The frequency of the timer determines the system tick granularity + * and, together with the @p CH_TIME_QUANTUM macro, the round robin + * interval. + * + * @iclass + */ +void chSysTimerHandlerI(void) { + + chDbgCheckClassI(); + +#if CH_TIME_QUANTUM > 0 + /* Running thread has not used up quantum yet? */ + if (currp->p_preempt > 0) + /* Decrement remaining quantum.*/ + currp->p_preempt--; +#endif +#if CH_DBG_THREADS_PROFILING + currp->p_time++; +#endif + chVTDoTickI(); +#if defined(SYSTEM_TICK_EVENT_HOOK) + SYSTEM_TICK_EVENT_HOOK(); +#endif +} + +/** @} */ diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c new file mode 100644 index 000000000..9f6973c90 --- /dev/null +++ b/os/kernel/src/chthreads.c @@ -0,0 +1,436 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chthreads.c + * @brief Threads code. + * + * @addtogroup threads + * @details Threads related APIs and services. + * + *

    Operation mode

    + * A thread is an abstraction of an independent instructions flow. + * In ChibiOS/RT a thread is represented by a "C" function owning + * a processor context, state informations and a dedicated stack + * area. In this scenario static variables are shared among all + * threads while automatic variables are local to the thread.
    + * Operations defined for threads: + * - Create, a thread is started on the specified thread + * function. This operation is available in multiple variants, + * both static and dynamic. + * - Exit, a thread terminates by returning from its top + * level function or invoking a specific API, the thread can + * return a value that can be retrieved by other threads. + * - Wait, a thread waits for the termination of another + * thread and retrieves its return value. + * - Resume, a thread created in suspended state is started. + * - Sleep, the execution of a thread is suspended for the + * specified amount of time or the specified future absolute time + * is reached. + * - SetPriority, a thread changes its own priority level. + * - Yield, a thread voluntarily renounces to its time slot. + * . + * The threads subsystem is implicitly included in kernel however + * some of its part may be excluded by disabling them in @p chconf.h, + * see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration + * options. + * @{ + */ + +#include "ch.h" + +/** + * @brief Initializes a thread structure. + * @note This is an internal functions, do not use it in application code. + * + * @param[in] tp pointer to the thread + * @param[in] prio the priority level for the new thread + * @return The same thread pointer passed as parameter. + * + * @notapi + */ +Thread *_thread_init(Thread *tp, tprio_t prio) { + + tp->p_prio = prio; + tp->p_state = THD_STATE_SUSPENDED; + tp->p_flags = THD_MEM_MODE_STATIC; +#if CH_TIME_QUANTUM > 0 + tp->p_preempt = CH_TIME_QUANTUM; +#endif +#if CH_USE_MUTEXES + tp->p_realprio = prio; + tp->p_mtxlist = NULL; +#endif +#if CH_USE_EVENTS + tp->p_epending = 0; +#endif +#if CH_DBG_THREADS_PROFILING + tp->p_time = 0; +#endif +#if CH_USE_DYNAMIC + tp->p_refs = 1; +#endif +#if CH_USE_REGISTRY + tp->p_name = NULL; + REG_INSERT(tp); +#endif +#if CH_USE_WAITEXIT + list_init(&tp->p_waiting); +#endif +#if CH_USE_MESSAGES + queue_init(&tp->p_msgqueue); +#endif +#if CH_DBG_ENABLE_STACK_CHECK + tp->p_stklimit = (stkalign_t *)(tp + 1); +#endif +#if defined(THREAD_EXT_INIT_HOOK) + THREAD_EXT_INIT_HOOK(tp); +#endif + return tp; +} + +#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__) +/** + * @brief Memory fill utility. + * + * @param[in] startp first address to fill + * @param[in] endp last address to fill +1 + * @param[in] v filler value + * + * @notapi + */ +void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { + + while (startp < endp) + *startp++ = v; +} +#endif /* CH_DBG_FILL_THREADS */ + +/** + * @brief Creates a new thread into a static memory area. + * @details The new thread is initialized but not inserted in the ready list, + * the initial state is @p THD_STATE_SUSPENDED. + * @post The initialized thread can be subsequently started by invoking + * @p chThdResume(), @p chThdResumeI() or @p chSchWakeupS() + * depending on the execution context. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note Threads created using this function do not obey to the + * @p CH_DBG_FILL_THREADS debug option because it would keep + * the kernel locked for too much time. + * + * @param[out] wsp pointer to a working area dedicated to the thread stack + * @param[in] size size of the working area + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * + * @iclass + */ +Thread *chThdCreateI(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + /* Thread structure is laid out in the lower part of the thread workspace.*/ + Thread *tp = wsp; + + chDbgCheckClassI(); + + chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) && + (prio <= HIGHPRIO) && (pf != NULL), + "chThdCreateI"); + SETUP_CONTEXT(wsp, size, pf, arg); + return _thread_init(tp, prio); +} + +/** + * @brief Creates a new thread into a static memory area. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * + * @param[out] wsp pointer to a working area dedicated to the thread stack + * @param[in] size size of the working area + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * + * @api + */ +Thread *chThdCreateStatic(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + Thread *tp; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + size, + CH_STACK_FILL_VALUE); +#endif + chSysLock(); + chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK); + chSysUnlock(); + return tp; +} + +/** + * @brief Changes the running thread priority level then reschedules if + * necessary. + * @note The function returns the real thread priority regardless of the + * current priority that could be higher than the real priority + * because the priority inheritance mechanism. + * + * @param[in] newprio the new priority level of the running thread + * @return The old priority level. + * + * @api + */ +tprio_t chThdSetPriority(tprio_t newprio) { + tprio_t oldprio; + + chDbgCheck(newprio <= HIGHPRIO, "chThdSetPriority"); + + chSysLock(); +#if CH_USE_MUTEXES + oldprio = currp->p_realprio; + if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio)) + currp->p_prio = newprio; + currp->p_realprio = newprio; +#else + oldprio = currp->p_prio; + currp->p_prio = newprio; +#endif + chSchRescheduleS(); + chSysUnlock(); + return oldprio; +} + +/** + * @brief Resumes a suspended thread. + * @pre The specified thread pointer must refer to an initialized thread + * in the @p THD_STATE_SUSPENDED state. + * @post The specified thread is immediately started or put in the ready + * list depending on the relative priority levels. + * @note Use this function to start threads created with @p chThdCreateI(). + * + * @param[in] tp pointer to the thread + * @return The pointer to the thread. + * + * @api + */ +Thread *chThdResume(Thread *tp) { + + chSysLock(); + chDbgAssert(tp->p_state == THD_STATE_SUSPENDED, + "chThdResume(), #1", + "thread not in THD_STATE_SUSPENDED state"); + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} + +/** + * @brief Requests a thread termination. + * @pre The target thread must be written to invoke periodically + * @p chThdShouldTerminate() and terminate cleanly if it returns + * @p TRUE. + * @post The specified thread will terminate after detecting the termination + * condition. + * + * @param[in] tp pointer to the thread + * + * @api + */ +void chThdTerminate(Thread *tp) { + + chSysLock(); + tp->p_flags |= THD_TERMINATE; + chSysUnlock(); +} + +/** + * @brief Suspends the invoking thread for the specified time. + * + * @param[in] time the delay in system ticks, the special values are + * handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * + * @api + */ +void chThdSleep(systime_t time) { + + chDbgCheck(time != TIME_IMMEDIATE, "chThdSleep"); + + chSysLock(); + chThdSleepS(time); + chSysUnlock(); +} + +/** + * @brief Suspends the invoking thread until the system time arrives to the + * specified value. + * + * @param[in] time absolute system time + * + * @api + */ +void chThdSleepUntil(systime_t time) { + + chSysLock(); + if ((time -= chTimeNow()) > 0) + chThdSleepS(time); + chSysUnlock(); +} + +/** + * @brief Yields the time slot. + * @details Yields the CPU control to the next thread in the ready list with + * equal priority, if any. + * + * @api + */ +void chThdYield(void) { + + chSysLock(); + chSchDoYieldS(); + chSysUnlock(); +} + +/** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @api + */ +void chThdExit(msg_t msg) { + + chSysLock(); + chThdExitS(msg); + /* The thread never returns here.*/ +} + +/** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @sclass + */ +void chThdExitS(msg_t msg) { + Thread *tp = currp; + + tp->p_u.exitcode = msg; +#if defined(THREAD_EXT_EXIT_HOOK) + THREAD_EXT_EXIT_HOOK(tp); +#endif +#if CH_USE_WAITEXIT + while (notempty(&tp->p_waiting)) + chSchReadyI(list_remove(&tp->p_waiting)); +#endif +#if CH_USE_REGISTRY + /* Static threads are immediately removed from the registry because + there is no memory to recover.*/ + if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC) + REG_REMOVE(tp); +#endif + chSchGoSleepS(THD_STATE_FINAL); + /* The thread never returns here.*/ + chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse"); +} + +#if CH_USE_WAITEXIT || defined(__DOXYGEN__) +/** + * @brief Blocks the execution of the invoking thread until the specified + * thread terminates then the exit code is returned. + * @details This function waits for the specified thread to terminate then + * decrements its reference counter, if the counter reaches zero then + * the thread working area is returned to the proper allocator.
    + * The memory used by the exited thread is handled in different ways + * depending on the API that spawned the thread: + * - If the thread was spawned by @p chThdCreateStatic() or by + * @p chThdCreateI() then nothing happens and the thread working + * area is not released or modified in any way. This is the + * default, totally static, behavior. + * - If the thread was spawned by @p chThdCreateFromHeap() then + * the working area is returned to the system heap. + * - If the thread was spawned by @p chThdCreateFromMemoryPool() + * then the working area is returned to the owning memory pool. + * . + * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in + * order to use this function. + * @post Enabling @p chThdWait() requires 2-4 (depending on the + * architecture) extra bytes in the @p Thread structure. + * @post After invoking @p chThdWait() the thread pointer becomes invalid + * and must not be used as parameter for further system calls. + * @note If @p CH_USE_DYNAMIC is not specified this function just waits for + * the thread termination, no memory allocators are involved. + * + * @param[in] tp pointer to the thread + * @return The exit code from the terminated thread. + * + * @api + */ +msg_t chThdWait(Thread *tp) { + msg_t msg; + + chDbgCheck(tp != NULL, "chThdWait"); + + chSysLock(); + chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self"); +#if CH_USE_DYNAMIC + chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced"); +#endif + if (tp->p_state != THD_STATE_FINAL) { + list_insert(currp, &tp->p_waiting); + chSchGoSleepS(THD_STATE_WTEXIT); + } + msg = tp->p_u.exitcode; + chSysUnlock(); +#if CH_USE_DYNAMIC + chThdRelease(tp); +#endif + return msg; +} +#endif /* CH_USE_WAITEXIT */ + +/** @} */ diff --git a/os/kernel/src/chvt.c b/os/kernel/src/chvt.c new file mode 100644 index 000000000..a8e3ce499 --- /dev/null +++ b/os/kernel/src/chvt.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chvt.c + * @brief Time and Virtual Timers related code. + * + * @addtogroup time + * @details Time and Virtual Timers related APIs and services. + * @{ + */ + +#include "ch.h" + +/** + * @brief Virtual timers delta list header. + */ +VTList vtlist; + +/** + * @brief Virtual Timers initialization. + * @note Internal use only. + * + * @notapi + */ +void _vt_init(void) { + + vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist; + vtlist.vt_time = (systime_t)-1; + vtlist.vt_systime = 0; +} + +/** + * @brief Enables a virtual timer. + * @note The associated function is invoked from interrupt context. + * + * @param[out] vtp the @p VirtualTimer structure pointer + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE is allowed but interpreted as a + * normal time specification. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @param[in] vtfunc the timer callback function. After invoking the + * callback the timer is disabled and the structure can + * be disposed or reused. + * @param[in] par a parameter that will be passed to the callback + * function + * + * @iclass + */ +void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) { + VirtualTimer *p; + + chDbgCheckClassI(); + chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_IMMEDIATE), + "chVTSetI"); + + vtp->vt_par = par; + vtp->vt_func = vtfunc; + p = vtlist.vt_next; + while (p->vt_time < time) { + time -= p->vt_time; + p = p->vt_next; + } + + vtp->vt_prev = (vtp->vt_next = p)->vt_prev; + vtp->vt_prev->vt_next = p->vt_prev = vtp; + vtp->vt_time = time; + if (p != (void *)&vtlist) + p->vt_time -= time; +} + +/** + * @brief Disables a Virtual Timer. + * @note The timer MUST be active when this function is invoked. + * + * @param[in] vtp the @p VirtualTimer structure pointer + * + * @iclass + */ +void chVTResetI(VirtualTimer *vtp) { + + chDbgCheckClassI(); + chDbgCheck(vtp != NULL, "chVTResetI"); + chDbgAssert(vtp->vt_func != NULL, + "chVTResetI(), #1", + "timer not set or already triggered"); + + if (vtp->vt_next != (void *)&vtlist) + vtp->vt_next->vt_time += vtp->vt_time; + vtp->vt_prev->vt_next = vtp->vt_next; + vtp->vt_next->vt_prev = vtp->vt_prev; + vtp->vt_func = (vtfunc_t)NULL; +} + +/** + * @brief Checks if the current system time is within the specified time + * window. + * @note When start==end then the function returns always true because the + * whole time range is specified. + * + * @param[in] start the start of the time window (inclusive) + * @param[in] end the end of the time window (non inclusive) + * @retval TRUE current time within the specified time window. + * @retval FALSE current time not within the specified time window. + * + * @api + */ +bool_t chTimeIsWithin(systime_t start, systime_t end) { + + systime_t time = chTimeNow(); + return end > start ? (time >= start) && (time < end) : + (time >= start) || (time < end); +} + +/** @} */ diff --git a/os/kernel/templates/chconf.h b/os/kernel/templates/chconf.h new file mode 100644 index 000000000..ae54d3edf --- /dev/null +++ b/os/kernel/templates/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/os/kernel/templates/chcore.c b/os/kernel/templates/chcore.c new file mode 100644 index 000000000..7639d9dd7 --- /dev/null +++ b/os/kernel/templates/chcore.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chcore.c + * @brief Port related template code. + * @details This file is a template of the system driver functions provided by + * a port. Some of the following functions may be implemented as + * macros in chcore.h if the implementer decides that there is an + * advantage in doing so, for example because performance concerns. + * + * @addtogroup core + * @details Non portable code templates. + * @{ + */ + +#include "ch.h" + +/** + * @brief Port-related initialization code. + * @note This function is usually empty. + */ +void port_init(void) { +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + */ +void port_lock(void) { +} + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + */ +void port_unlock(void) { +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + */ +void port_lock_from_isr(void) { +} + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + */ +void port_unlock_from_isr(void) { +} + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + */ +void port_disable(void) { +} + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + */ +void port_suspend(void) { +} + +/** + * @brief Enables all the interrupt sources. + */ +void port_enable(void) { +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + */ +void port_wait_for_interrupt(void) { +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +void port_switch(Thread *ntp, Thread *otp) { +} + +/** @} */ diff --git a/os/kernel/templates/chcore.h b/os/kernel/templates/chcore.h new file mode 100644 index 000000000..f73b3b0c8 --- /dev/null +++ b/os/kernel/templates/chcore.h @@ -0,0 +1,213 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chcore.h + * @brief Port related template macros and structures. + * @details This file is a template of the system driver macros provided by + * a port. + * + * @addtogroup core + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 0 +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_XXX + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_ARCHITECTURE_VARIANT_NAME "" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack and memory alignment. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * @note Not all architectures support fast interrupts, in this case this + * macro must be omitted. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void port_lock(void); + void port_unlock(void); + void port_lock_from_isr(void); + void port_unlock_from_isr(void); + void port_disable(void); + void port_suspend(void); + void port_enable(void); + void port_wait_for_interrupt(void); + void port_halt(void); + void port_switch(Thread *ntp, Thread *otp); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/kernel/templates/chtypes.h b/os/kernel/templates/chtypes.h new file mode 100644 index 000000000..52efee447 --- /dev/null +++ b/os/kernel/templates/chtypes.h @@ -0,0 +1,130 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chtypes.h + * @brief System types template. + * @details The types defined in this file may change depending on the target + * architecture. You may also try to optimize the size of the various + * types in order to privilege size or performance, be careful in + * doing so. + * + * @addtogroup types + * @details System types and macros. + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +/** + * @brief Boolean, recommended the fastest signed. + */ +typedef int32_t bool_t; + +/** + * @brief Thread mode flags, uint8_t is ok. + */ +typedef uint8_t tmode_t; + +/** + * @brief Thread state, uint8_t is ok. + */ +typedef uint8_t tstate_t; + +/** + * @brief Thread references counter, uint8_t is ok. + */ +typedef uint8_t trefs_t; + +/** + * @brief Priority, use the fastest unsigned type. + */ +typedef uint32_t tprio_t; + +/** + * @brief Message, use signed pointer equivalent. + */ +typedef int32_t msg_t; + +/** + * @brief Event Id, use fastest signed. + */ +typedef int32_t eventid_t; + +/** + * @brief Event Mask, recommended fastest unsigned. + */ +typedef uint32_t eventmask_t; + +/** + * @brief System Time, recommended fastest unsigned. + */ +typedef uint32_t systime_t; + +/** + * @brief Counter, recommended fastest signed. + */ +typedef int32_t cnt_t; + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note This is required because some compilers require a custom keyword, + * usually this macro is just set to "const" for the GCC compiler. + * @note This macro is not used to place constants in different address + * spaces (like AVR requires for example) because it is assumed that + * a pointer to a ROMCONST constant is compatible with a pointer + * to a normal variable. It is just like the "const" keyword but + * requires that the constant is placed in ROM if the architecture + * supports it. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARM/AT91SAM7/armparams.h b/os/ports/GCC/ARM/AT91SAM7/armparams.h new file mode 100644 index 000000000..a8c2256a1 --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/armparams.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/AT91SAM7/armparams.h + * @brief ARM7 AT91SAM7 Specific Parameters. + * + * @defgroup ARM_AT91SAM7 AT91SAM7 Specific Parameters + * @ingroup ARM_SPECIFIC + * @details This file contains the ARM specific parameters for the + * AT91SAM7 platform. + * @{ + */ + +#ifndef _ARMPARAMS_H_ +#define _ARMPARAMS_H_ + +/** + * @brief ARM core model. + */ +#define ARM_CORE ARM_CORE_ARM7TDMI + +/** + * @brief AT91SAM7-specific wait for interrupt. + * @details This implementation writes 1 into the PMC_SCDR register. + */ +#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__) +#if ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + (*((volatile uint32_t *)0xFFFFFC04)) = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _ARMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld new file mode 100644 index 000000000..81934247b --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7A3 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 32k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld new file mode 100644 index 000000000..763d50b16 --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7S256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld new file mode 100644 index 000000000..6c61ff6f0 --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/os/ports/GCC/ARM/AT91SAM7/port.mk b/os/ports/GCC/ARM/AT91SAM7/port.mk new file mode 100644 index 000000000..2cafd01aa --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/port.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS/RT ARM7 AT91SAM7 port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ + ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ + ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/vectors.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ + ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7 + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/ld diff --git a/os/ports/GCC/ARM/AT91SAM7/vectors.s b/os/ports/GCC/ARM/AT91SAM7/vectors.s new file mode 100644 index 000000000..c9ab881ad --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/vectors.s @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/AT91SAM7/vectors.s + * @brief Interrupt vectors for the AT91SAM7 family. + * + * @defgroup ARM_AT91SAM7_VECTORS AT91SAM7 Interrupt Vectors + * @ingroup ARM_SPECIFIC + * @details Interrupt vectors for the AT91SAM7 family. + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +void _unhandled_exception(void) {} +#endif + +#if !defined(__DOXYGEN__) + +.section vectors +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + ldr pc, _reset + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xF20] /* AIC - AIC_IVR */ + ldr pc, [pc,#-0xF20] /* AIC - AIC_FVR */ + +_reset: + .word ResetHandler /* In crt0.s */ +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler + .word 0 + .word 0 + .word 0 + +.text +.code 32 +.balign 4 + +/* + * Default exceptions handlers. The handlers are declared weak in order to be + * replaced by the real handling code. Everything is defaulted to an infinite + * loop. + */ +.weak UndHandler +UndHandler: + +.weak SwiHandler +SwiHandler: + +.weak PrefetchHandler +PrefetchHandler: + +.weak AbortHandler +AbortHandler: + +.weak FiqHandler +FiqHandler: + +.global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif + +/** @} */ diff --git a/os/ports/GCC/ARM/AT91SAM7/wfi.h b/os/ports/GCC/ARM/AT91SAM7/wfi.h new file mode 100644 index 000000000..1cb7e6f40 --- /dev/null +++ b/os/ports/GCC/ARM/AT91SAM7/wfi.h @@ -0,0 +1,36 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _WFI_H_ +#define _WFI_H_ + +#include "board.h" + +#ifndef port_wait_for_interrupt +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + AT91C_BASE_SYS->PMC_SCDR = AT91C_PMC_PCK; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _WFI_H_ */ diff --git a/os/ports/GCC/ARM/LPC214x/armparams.h b/os/ports/GCC/ARM/LPC214x/armparams.h new file mode 100644 index 000000000..d22063d36 --- /dev/null +++ b/os/ports/GCC/ARM/LPC214x/armparams.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/LPC214x/armparams.h + * @brief ARM7 LPC214x Specific Parameters. + * + * @defgroup ARM_LPC214x LPC214x Specific Parameters + * @ingroup ARM_SPECIFIC + * @details This file contains the ARM specific parameters for the + * LPC214x platform. + * @{ + */ + +#ifndef _ARMPARAMS_H_ +#define _ARMPARAMS_H_ + +/** + * @brief ARM core model. + */ +#define ARM_CORE ARM_CORE_ARM7TDMI + +/** + * @brief LPC214x-specific wait for interrupt code. + * @details This implementation writes 1 into the PCON register. + */ +#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__) +#if ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + (*((volatile uint32_t *)0xE01FC0C0)) = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _ARMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld b/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld new file mode 100644 index 000000000..8b15a3a16 --- /dev/null +++ b/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/os/ports/GCC/ARM/LPC214x/port.mk b/os/ports/GCC/ARM/LPC214x/port.mk new file mode 100644 index 000000000..339f1d66a --- /dev/null +++ b/os/ports/GCC/ARM/LPC214x/port.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS/RT ARM7 LPC214x port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ + ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ + ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/vectors.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ + ${CHIBIOS}/os/ports/GCC/ARM/LPC214x + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/ld diff --git a/os/ports/GCC/ARM/LPC214x/vectors.s b/os/ports/GCC/ARM/LPC214x/vectors.s new file mode 100644 index 000000000..bd554d6b9 --- /dev/null +++ b/os/ports/GCC/ARM/LPC214x/vectors.s @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/LPC214x/vectors.s + * @brief Interrupt vectors for the LPC214x family. + * + * @defgroup ARM_LPC214x_VECTORS LPC214x Interrupt Vectors + * @ingroup ARM_SPECIFIC + * @details Interrupt vectors for the LPC214x family. + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +void _unhandled_exception(void) {} +#endif + +#if !defined(__DOXYGEN__) + +.section vectors +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + ldr pc, _reset + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ + ldr pc, _fiq + +_reset: + .word ResetHandler /* In crt0.s */ +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler + .word 0 + .word 0 + +/* + * Default exceptions handlers. The handlers are declared weak in order to be + * replaced by the real handling code. Everything is defaulted to an infinite + * loop. + */ +.weak UndHandler +UndHandler: + +.weak SwiHandler +SwiHandler: + +.weak PrefetchHandler +PrefetchHandler: + +.weak AbortHandler +AbortHandler: + +.weak FiqHandler +FiqHandler: + +.global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif + +/** @} */ diff --git a/os/ports/GCC/ARM/LPC214x/wfi.h b/os/ports/GCC/ARM/LPC214x/wfi.h new file mode 100644 index 000000000..765e6499d --- /dev/null +++ b/os/ports/GCC/ARM/LPC214x/wfi.h @@ -0,0 +1,36 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _WFI_H_ +#define _WFI_H_ + +#include "lpc214x.h" + +#ifndef port_wait_for_interrupt +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + PCON = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _WFI_H_ */ diff --git a/os/ports/GCC/ARM/chcore.c b/os/ports/GCC/ARM/chcore.c new file mode 100644 index 000000000..3c348c964 --- /dev/null +++ b/os/ports/GCC/ARM/chcore.c @@ -0,0 +1,44 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/chcore.c + * @brief ARM7/9 architecture port code. + * + * @addtogroup ARM_CORE + * @{ + */ + +#include "ch.h" + +/** + * Halts the system. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h new file mode 100644 index 000000000..d1b6a1e12 --- /dev/null +++ b/os/ports/GCC/ARM/chcore.h @@ -0,0 +1,478 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/chcore.h + * @brief ARM7/9 architecture port macros and structures. + * + * @addtogroup ARM_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/* Core variants identifiers.*/ +#define ARM_CORE_ARM7TDMI 7 /**< ARM77TDMI core identifier. */ +#define ARM_CORE_ARM9 9 /**< ARM9 core identifier. */ + +/* Inclusion of the ARM implementation specific parameters.*/ +#include "armparams.h" + +/* ARM core check, only ARM7TDMI and ARM9 supported right now.*/ +#if (ARM_CORE == ARM_CORE_ARM7TDMI) || (ARM_CORE == ARM_CORE_ARM9) +#else +#error "unknown or unsupported ARM core" +#endif + +/*===========================================================================*/ +/* Port statically derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief If enabled allows the idle thread to enter a low power mode. + */ +#ifndef ARM_ENABLE_WFI_IDLE +#define ARM_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +#if defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + * @note This macro is for documentation only, the real name changes + * depending on the selected architecture, the possible names are: + * - CH_ARCHITECTURE_ARM7TDMI. + * - CH_ARCHITECTURE_ARM9. + * . + */ +#define CH_ARCHITECTURE_ARMx + +/** + * @brief Name of the implemented architecture. + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARM7". + * - "ARM9". + * . + */ +#define CH_ARCHITECTURE_NAME "ARMx" + +/** + * @brief Name of the architecture variant (optional). + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARM7TDMI" + * - "ARM9" + * . + */ +#define CH_CORE_VARIANT_NAME "ARMxy" + +/** + * @brief Port-specific information string. + * @note The value is for documentation only, the real value changes + * depending on the selected options, the possible values are: + * - "Pure ARM" + * - "Pure THUMB" + * - "Interworking" + * . + */ +#define CH_PORT_INFO "ARM|THUMB|Interworking" + +#elif ARM_CORE == ARM_CORE_ARM7TDMI +#define CH_ARCHITECTURE_ARM7TDMI +#define CH_ARCHITECTURE_NAME "ARM7" +#define CH_CORE_VARIANT_NAME "ARM7TDMI" + +#elif ARM_MODEL == ARM_VARIANT_ARM9 +#define CH_ARCHITECTURE_ARM9 +#define CH_ARCHITECTURE_NAME "ARM9" +#define CH_CORE_VARIANT_NAME "ARM9" +#endif + +#if THUMB_PRESENT +#if THUMB_NO_INTERWORKING +#define CH_PORT_INFO "Pure THUMB mode" +#else /* !THUMB_NO_INTERWORKING */ +#define CH_PORT_INFO "Interworking mode" +#endif /* !THUMB_NO_INTERWORKING */ +#else /* !THUMB_PRESENT */ +#define CH_PORT_INFO "Pure ARM mode" +#endif /* !THUMB_PRESENT */ + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/** + * @brief 32 bits stack and memory alignment enforcement. + */ +typedef uint32_t stkalign_t; + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { + regarm_t spsr_irq; + regarm_t lr_irq; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_usr; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = _port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 4 because the idle thread does have + * a stack frame when compiling without optimizations. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 4 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port 0x10 is a safe value, it can be reduced after careful + * analysis of the generated code. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 0x10 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + * @note This macro has a different implementation depending if compiled in + * ARM or THUMB mode. + * @note The THUMB implementation starts with ARM code because interrupt + * vectors are always invoked in ARM mode regardless the bit 0 + * value. The switch in THUMB mode is done in the function prologue so + * it is transparent to the user code. + */ +#if !defined(PORT_IRQ_PROLOGUE) +#ifdef THUMB +#define PORT_IRQ_PROLOGUE() { \ + asm volatile (".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t" \ + "add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16" : : : "memory"); \ +} +#else /* !THUMB */ +#define PORT_IRQ_PROLOGUE() { \ + asm volatile ("stmfd sp!, {r0-r3, r12, lr}" : : : "memory"); \ +} +#endif /* !THUMB */ +#endif /* !defined(PORT_IRQ_PROLOGUE) */ + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + * @note This macro has a different implementation depending if compiled in + * ARM or THUMB mode. + */ +#if !defined(PORT_IRQ_EPILOGUE) +#ifdef THUMB +#define PORT_IRQ_EPILOGUE() { \ + asm volatile ("ldr r0, =_port_irq_common \n\t" \ + "bx r0" : : : "memory"); \ +} +#else /* !THUMB */ +#define PORT_IRQ_EPILOGUE() { \ + asm volatile ("b _port_irq_common" : : : "memory"); \ +} +#endif /* !THUMB */ +#endif /* !defined(PORT_IRQ_EPILOGUE) */ + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#if !defined(PORT_IRQ_HANDLER) +#define PORT_IRQ_HANDLER(id) __attribute__((naked)) void id(void) +#endif /* !defined(PORT_IRQ_HANDLER) */ + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#if !defined(PORT_FAST_IRQ_HANDLER) +#define PORT_FAST_IRQ_HANDLER(id) \ + __attribute__((interrupt("FIQ"))) void id(void) +#endif /* !defined(PORT_FAST_IRQ_HANDLER) */ + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port it disables the IRQ sources and keeps FIQ sources + * enabled. + */ +#ifdef THUMB +#define port_lock() { \ + asm volatile ("bl _port_lock_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_lock() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port it enables both the IRQ and FIQ sources. + */ +#ifdef THUMB +#define port_unlock() { \ + asm volatile ("bl _port_unlock_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_unlock() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables both the IRQ and FIQ sources. + * @note Implements a workaround for spurious interrupts taken from the NXP + * LPC214x datasheet. + */ +#ifdef THUMB +#define port_disable() { \ + asm volatile ("bl _port_disable_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_disable() { \ + asm volatile ("mrs r3, CPSR \n\t" \ + "orr r3, #0x80 \n\t" \ + "msr CPSR_c, r3 \n\t" \ + "orr r3, #0x40 \n\t" \ + "msr CPSR_c, r3" : : : "r3", "memory"); \ +} +#endif /* !THUMB */ + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it disables the IRQ sources and enables the + * FIQ sources. + */ +#ifdef THUMB +#define port_suspend() { \ + asm volatile ("bl _port_suspend_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_suspend() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it enables both the IRQ and FIQ sources. + */ +#ifdef THUMB +#define port_enable() { \ + asm volatile ("bl _port_enable_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_enable() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * @note Implemented as inlined code for performance reasons. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#ifdef THUMB +#if CH_DBG_ENABLE_STACK_CHECK +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch_thumb(ntp, otp); \ +} +#else /* !CH_DBG_ENABLE_STACK_CHECK */ +#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp) +#endif /* !CH_DBG_ENABLE_STACK_CHECK */ +#else /* !THUMB */ +#if CH_DBG_ENABLE_STACK_CHECK +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch_arm(ntp, otp); \ +} +#else /* !CH_DBG_ENABLE_STACK_CHECK */ +#define port_switch(ntp, otp) _port_switch_arm(ntp, otp) +#endif /* !CH_DBG_ENABLE_STACK_CHECK */ +#endif /* !THUMB */ + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); +#ifdef THUMB + void _port_switch_thumb(Thread *ntp, Thread *otp); +#else /* !THUMB */ + void _port_switch_arm(Thread *ntp, Thread *otp); +#endif /* !THUMB */ + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARM/chcoreasm.s b/os/ports/GCC/ARM/chcoreasm.s new file mode 100644 index 000000000..221ae4aec --- /dev/null +++ b/os/ports/GCC/ARM/chcoreasm.s @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/chcoreasm.s + * @brief ARM7/9 architecture port low level code. + * + * @addtogroup ARM_CORE + * @{ + */ + +#include "chconf.h" + +#define FALSE 0 +#define TRUE 1 + +#if !defined(__DOXYGEN__) + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text + +/* + * Interrupt enable/disable functions, only present if there is THUMB code in + * the system because those are inlined in ARM code. + */ +#ifdef THUMB_PRESENT +.balign 16 +.code 16 +.thumb_func +.global _port_disable_thumb +_port_disable_thumb: + mov r3, pc + bx r3 +.code 32 + mrs r3, CPSR + orr r3, #I_BIT + msr CPSR_c, r3 + orr r3, #F_BIT + msr CPSR_c, r3 + bx lr + +.balign 16 +.code 16 +.thumb_func +.global _port_suspend_thumb +_port_suspend_thumb: +.thumb_func +.global _port_lock_thumb +_port_lock_thumb: + mov r3, pc + bx r3 +.code 32 + msr CPSR_c, #MODE_SYS | I_BIT + bx lr + +.balign 16 +.code 16 +.thumb_func +.global _port_enable_thumb +_port_enable_thumb: +.thumb_func +.global _port_unlock_thumb +_port_unlock_thumb: + mov r3, pc + bx r3 +.code 32 + msr CPSR_c, #MODE_SYS + bx lr + +#endif + +.balign 16 +#ifdef THUMB_PRESENT +.code 16 +.thumb_func +.global _port_switch_thumb +_port_switch_thumb: + mov r2, pc + bx r2 + // Jumps into _port_switch_arm in ARM mode +#endif +.code 32 +.global _port_switch_arm +_port_switch_arm: +#ifdef CH_CURRP_REGISTER_CACHE + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r1, #12] + ldr sp, [r0, #12] +#ifdef THUMB_PRESENT + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr +#else /* !THUMB_PRESENT */ + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} +#endif /* !THUMB_PRESENT */ +#else /* !CH_CURRP_REGISTER_CACHE */ + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r1, #12] + ldr sp, [r0, #12] +#ifdef THUMB_PRESENT + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr +#else /* !THUMB_PRESENT */ + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} +#endif /* !THUMB_PRESENT */ +#endif /* !CH_CURRP_REGISTER_CACHE */ + +/* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | LR_USR | -+ + * | R12 | | + * | R3 | | + * | R2 | | External context: IRQ handler frame + * | R1 | | + * | R0 | | + * | PC | | (user code return address) + * | PSR_USR | -+ (user code status) + * | .... | <- chSchDoReschedule() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: chSysSwitch() frame + * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +.balign 16 +#ifdef THUMB_NO_INTERWORKING +.code 16 +.thumb_func +.globl _port_irq_common +_port_irq_common: + bl chSchIsPreemptionRequired + mov lr, pc + bx lr +.code 32 +#else /* !THUMB_NO_INTERWORKING */ +.code 32 +.globl _port_irq_common +_port_irq_common: + bl chSchIsPreemptionRequired +#endif /* !THUMB_NO_INTERWORKING */ + cmp r0, #0 // Simply returns if a + ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not + subeqs pc, lr, #4 // required. + + // Saves the IRQ mode registers in the system stack. + ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. + msr CPSR_c, #MODE_IRQ | I_BIT + mrs r0, SPSR + mov r1, lr + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. + + // Context switch. +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + mov lr, pc + bx lr +.code 32 +#else /* !THUMB_NO_INTERWORKING */ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#endif /* !THUMB_NO_INTERWORKING */ + + // Re-establish the IRQ conditions again. + ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. + msr CPSR_c, #MODE_IRQ | I_BIT + msr SPSR_fsxc, r0 + mov lr, r1 + msr CPSR_c, #MODE_SYS | I_BIT + ldmfd sp!, {r0-r3, r12, lr} + msr CPSR_c, #MODE_IRQ | I_BIT + subs pc, lr, #4 + +/* + * Threads trampoline code. + * NOTE: The threads always start in ARM mode and then switches to the + * thread-function mode. + */ +.balign 16 +.code 32 +.globl _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + mov r0, #0 + ldr r1, =dbg_lock_cnt + str r0, [r1] +#endif + msr CPSR_c, #MODE_SYS +#ifndef THUMB_NO_INTERWORKING + mov r0, r5 + mov lr, pc + bx r4 + bl chThdExit +#else /* !THUMB_NO_INTERWORKING */ + add r0, pc, #1 + bx r0 +.code 16 + mov r0, r5 + bl jmpr4 + bl chThdExit +jmpr4: + bx r4 +#endif /* !THUMB_NO_INTERWORKING */ + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/ARM/chtypes.h b/os/ports/GCC/ARM/chtypes.h new file mode 100644 index 000000000..36bebf14f --- /dev/null +++ b/os/ports/GCC/ARM/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/chtypes.h + * @brief ARM7/9 architecture port system types. + * + * @addtogroup ARM_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARM/crt0.s b/os/ports/GCC/ARM/crt0.s new file mode 100644 index 000000000..74df7f74e --- /dev/null +++ b/os/ports/GCC/ARM/crt0.s @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/crt0.s + * @brief Generic ARM7/9 startup file for ChibiOS/RT. + * + * @addtogroup ARM_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + .set MODE_USR, 0x10 + .set MODE_FIQ, 0x11 + .set MODE_IRQ, 0x12 + .set MODE_SVC, 0x13 + .set MODE_ABT, 0x17 + .set MODE_UND, 0x1B + .set MODE_SYS, 0x1F + + .set I_BIT, 0x80 + .set F_BIT, 0x40 + + .text + .code 32 + .balign 4 + +/* + * Reset handler. + */ + .global ResetHandler +ResetHandler: + /* + * Stack pointers initialization. + */ + ldr r0, =__ram_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 +// ldr r1, =__sys_stack_size__ +// sub r0, r0, r1 + /* + * Early initialization. + */ +#ifndef THUMB_NO_INTERWORKING + bl __early_init +#else + add r0, pc, #1 + bx r0 + .code 16 + bl __early_init + mov r0, pc + bx r0 + .code 32 +#endif + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata +dataloop: + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end +bssloop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Main program invocation. + */ +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 + .code 16 + bl main + ldr r1, =_main_exit_handler + bx r1 + .code 32 +#else + bl main + b _main_exit_handler +#endif + +/* + * Default main function exit handler. + */ + .weak _main_exit_handler + .global _main_exit_handler +_main_exit_handler: +.loop: b .loop + +/* + * Default early initialization code. It is declared weak in order to be + * replaced by the real initialization code. + * Early initialization is performed just after reset before BSS and DATA + * segments initialization. + */ +#ifdef THUMB_NO_INTERWORKING + .thumb_func + .code 16 +#endif + .weak __early_init +hwinit0: + bx lr + .code 32 +#endif + +/** @} */ diff --git a/os/ports/GCC/ARM/port.dox b/os/ports/GCC/ARM/port.dox new file mode 100644 index 000000000..5f866d2c2 --- /dev/null +++ b/os/ports/GCC/ARM/port.dox @@ -0,0 +1,226 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup ARM ARM7/9 + * @details ARM7/9 port for the GCC compiler. + * + * @section ARM_INTRO Introduction + * The ARM7/9-GCC port supports the ARM7/9 core in the following three modes: + * - Pure ARM mode, this is the preferred mode for code speed, this + * mode increases the memory footprint however. This mode is enabled when + * all the modules are compiled in ARM mode, see the Makefiles. + * - Pure THUMB mode, this is the preferred mode for code size. In + * this mode the execution speed is slower than the ARM mode. This mode + * is enabled when all the modules are compiled in THUMB mode, see the + * Makefiles. + * - Interworking mode, when in the system there are ARM modules mixed + * with THUMB modules then the interworking compiler option is enabled. + * This is usually the slowest mode and the code size is not as good as + * in pure THUMB mode. + * . + * @section ARM_STATES Mapping of the System States in the ARM7/9 port + * The ChibiOS/RT logical system states are mapped as follow in the ARM7/9 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated, usually the CPU goes through several + * hardware states during the startup phase. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the CPU has both the interrupt sources + * (IRQ and FIQ) enabled and is running in ARM System Mode. + * - Suspended. In this state the IRQ sources are disabled but the FIQ + * sources are served, the core is running in ARM System Mode. + * - Disabled. Both the IRQ and FIQ sources are disabled, the core is + * running in ARM System Mode. + * - Sleep. ARM7/9 cores does not have an explicit built-in low power + * mode but there are clock stop modes implemented in custom ways by the + * various silicon vendors. This state is implemented in each microcontroller + * support code in a different way, the core is running (or freezed...) + * in ARM System Mode. + * - S-Locked. IRQ sources disabled, core running in ARM System Mode. + * - I-Locked. IRQ sources disabled, core running in ARM IRQ Mode. Note + * that this state is not different from the SRI state in this port, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. IRQ sources disabled, core running in + * ARM IRQ Mode. See also the I-Locked state. + * - Serving Fast Interrupt. IRQ and FIQ sources disabled, core running + * in ARM FIQ Mode. + * - Serving Non-Maskable Interrupt. There are no asynchronous NMI + * sources in ARM7/9 architecture but synchronous SVC, ABT and UND exception + * handlers can be seen as belonging to this category. + * - Halted. Implemented as an infinite loop after disabling both IRQ + * and FIQ sources. The ARM state is whatever the processor was running when + * @p chSysHalt() was invoked. + * . + * @section ARM_NOTES The ARM7/9 port notes + * The ARM7/9 port is organized as follow: + * - The @p main() function is invoked in system mode. + * - Each thread has a private user/system stack, the system has a single + * interrupt stack where all the interrupts are processed. + * - The threads are started in system mode. + * - The threads code can run in system mode or user mode, however the + * code running in user mode cannot invoke the ChibiOS/RT APIs directly + * because privileged instructions are used inside.
    + * The kernel APIs can be eventually invoked by using a SWI entry point + * that handles the switch in system mode and the return in user mode. + * - Other modes are not preempt-able because the system code assumes the + * threads running in system mode. When running in supervisor or other + * modes make sure that the interrupts are globally disabled. + * - Interrupts nesting is not supported in the ARM7/9 port because their + * implementation, even if possible, is not really efficient in this + * architecture. + * - FIQ sources can preempt the kernel (by design) so it is not possible to + * invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not + * affected by the kernel activity so there is not added jitter. + * . + * @section ARM_IH ARM7/9 Interrupt Handlers + * In the current implementation the ARM7/9 Interrupt handlers do not save + * function-saved registers so you need to make sure your code saves them + * or does not use them (this happens because in the ARM7/9 port all the + * OS interrupt handler functions are declared naked).
    + * Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the + * system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().
    + * The easiest way to ensure this is to just invoke a normal function from + * within the interrupt handler, the function code will save all the required + * registers.
    + * Example: + * @code + * CH_IRQ_HANDLER(irq_handler) { + * CH_IRQ_PROLOGUE(); + * + * serve_interrupt(); + * + * VICVectAddr = 0; // This is LPC214x-specific. + * CH_IRQ_EPILOGUE(); + * } + * @endcode + * This is not a bug but an implementation choice, this solution allows to + * have interrupt handlers compiled in thumb mode without have to use an + * interworking mode (the mode switch is hidden in the macros), this + * greatly improves code efficiency and size. You can look at the serial + * driver for real examples of interrupt handlers.
    + * It is important that the serve_interrupt() interrupt function is not + * inlined by the compiler into the ISR or the code could still modify + * the unsaved registers, this can be accomplished using GCC by adding + * the attribute "noinline" to the function: + * @code + * #if defined(__GNUC__) + * __attribute__((noinline)) + * #endif + * static void serve_interrupt(void) { + * } + * @endcode + * Note that several commercial compilers support a GNU-like functions + * attribute mechanism.
    + * Alternative ways are to use an appropriate pragma directive or disable + * inlining optimizations in the modules containing the interrupt handlers. + * + * @ingroup gcc + */ + +/** + * @defgroup ARM_CONF Configuration Options + * @details ARM7/9 specific configuration options. The ARM7/9 port allows some + * architecture-specific configurations settings that can be overridden by + * redefining them in @p chconf.h. Usually there is no need to change the + * default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures.
    + * In practice this value is the stack space used by the chSchDoReschedule() + * stack frame.
    + * This value can be affected by a variety of external things like compiler + * version, compiler options, kernel settings (speed/size) and so on.
    + * The default for this value is @p 0x10 which should be a safe value, you + * can trim this down by defining the macro externally. This would save + * some valuable RAM space for each thread present in the system.
    + * The default value is set into ./os/ports/GCC/ARM/chcore.h. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p ARM_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * an implementation-specific clock stop mode from within the idle loop. + * This option is defaulted to FALSE because it can create problems with + * some debuggers. Setting this option to TRUE reduces the system power + * requirements. + * . + * @ingroup ARM + */ + +/** + * @defgroup ARM_CORE Core Port Implementation + * @details ARM7/9 specific port code, structures and macros. + * + * @ingroup ARM + */ + +/** + * @defgroup ARM_STARTUP Startup Support + * @details ARM7/9 startup code support. ChibiOS/RT provides its own generic + * startup file for the ARM7/9 port. Of course it is not mandatory to use it + * but care should be taken about the startup phase details. + * + * @section ARM_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# The stacks are initialized by assigning them the sizes defined in the + * linker script (usually named @p ch.ld). Stack areas are allocated from + * the highest RAM location downward. + * -# The ARM state is switched to System with both IRQ and FIQ sources + * disabled. + * -# An early initialization routine @p hwinit0 is invoked, if the symbol is + * not defined then an empty default routine is executed (weak symbol). + * -# DATA and BSS segments are initialized. + * -# A late initialization routine @p hwinit1 is invoked, if the symbol not + * defined then an empty default routine is executed (weak symbol).
    + * This late initialization function is also the proper place for a + * @a bootloader, if your application requires one. + * -# The @p main() function is invoked with the parameters @p argc and @p argv + * set to zero. + * -# Should the @p main() function return a branch is performed to the weak + * symbol _main_exit_handler. The default code is an endless empty loop. + * . + * @section ARM_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p ResetHandler and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__ RAM end location +1. + * - @p __und_stack_size__ Undefined Instruction stack size. + * - @p __abt_stack_size__ Memory Abort stack size. + * - @p __fiq_stack_size__ FIQ service stack size. + * - @p __irq_stack_size__ IRQ service stack size. + * - @p __svc_stack_size__ SVC service stack size. + * - @p __sys_stack_size__ System/User stack size. This is the stack area used + * by the @p main() function. + * - @p _textdata address of the data segment source read only data. + * - @p _data data segment start location. + * - @p _edata data segment end location +1. + * - @p _bss_start BSS start location. + * - @p _bss_end BSS end location +1. + * . + * @ingroup ARM + */ + +/** + * @defgroup ARM_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup ARM + */ diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk new file mode 100644 index 000000000..40fa8c9e2 --- /dev/null +++ b/os/ports/GCC/ARM/rules.mk @@ -0,0 +1,220 @@ +# ARM7/9 common makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +endif + +$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +%.elf: $(OBJS) $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else + @echo Linking $@ + @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif + +%.hex: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(HEX) $< $@ +else + @echo Creating $@ + @$(HEX) $< $@ +endif + +%.bin: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(BIN) $< $@ +else + @echo Creating $@ + @$(BIN) $< $@ +endif + +%.dmp: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(OD) $(ODFLAGS) $< > $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 000000000..d2a8fbf3a --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld new file mode 100644 index 000000000..bbd5c3e80 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld new file mode 100644 index 000000000..1022db9ab --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC11C24 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld new file mode 100644 index 000000000..be3e83952 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC11U14 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 4k + usbram : org = 0x20004000, len = 2k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk new file mode 100644 index 000000000..8bfd25ad3 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC11xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx/ld diff --git a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c new file mode 100644 index 000000000..4ab02d632 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC11xx/vectors.c + * @brief Interrupt vectors for the LPC11xx family. + * + * @defgroup ARMCMx_LPC11xx_VECTORS LPC11xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC11xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief LPC11xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC122x/cmparams.h b/os/ports/GCC/ARMCMx/LPC122x/cmparams.h new file mode 100644 index 000000000..b70ce42a3 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC122x/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M0 LPC122x Specific Parameters. + * + * @defgroup ARMCMx_LPC122x LPC122x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC122x platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld b/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld new file mode 100644 index 000000000..b7171526d --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1227 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 128k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC122x/port.mk b/os/ports/GCC/ARMCMx/LPC122x/port.mk new file mode 100644 index 000000000..475861ee2 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC122x/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC122x port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC122x + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC122x/ld diff --git a/os/ports/GCC/ARMCMx/LPC122x/vectors.c b/os/ports/GCC/ARMCMx/LPC122x/vectors.c new file mode 100644 index 000000000..39e4007a3 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC122x/vectors.c @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC122x/vectors.c + * @brief Interrupt vectors for the LPC122x family. + * + * @defgroup ARMCMx_LPC122x_VECTORS LPC122x Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC122x family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief LPC11xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 000000000..6804ea993 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 LPC13xx Specific Parameters. + * + * @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld new file mode 100644 index 000000000..dfc1d94fe --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1343 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/os/ports/GCC/ARMCMx/LPC13xx/port.mk new file mode 100644 index 000000000..fa392c5d5 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC13xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC13xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx/ld diff --git a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c new file mode 100644 index 000000000..1537dc13f --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c @@ -0,0 +1,257 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC13xx/vectors.c + * @brief Interrupt vectors for the LPC13xx family. + * + * @defgroup ARMCMx_LPC13xx_VECTORS LPC13xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC13xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[58]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +#endif + +/** + * @brief LPC13xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h new file mode 100644 index 000000000..da25ac6a2 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC8xx/cmparams.h + * @brief ARM Cortex-M0+ parameters for the LPC8xx. + * + * @defgroup ARMCMx_LPC8xx LPC8xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0+ specific parameters for the + * LPC8xx platform. + * (Taken from the device header file where possible) + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +#include "LPC8xx.h" + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL __CORTEX_M + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU __MPU_PRESENT + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS __NVIC_PRIO_BITS + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld b/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld new file mode 100644 index 000000000..6973f6ddb --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC812 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; + +MEMORY +{ + flash : org = 0x00000000, len = 16k + ram : org = 0x10000000, len = 4k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC8xx/port.mk b/os/ports/GCC/ARMCMx/LPC8xx/port.mk new file mode 100644 index 000000000..9353ee68b --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC8xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC8xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx/ld diff --git a/os/ports/GCC/ARMCMx/LPC8xx/vectors.c b/os/ports/GCC/ARMCMx/LPC8xx/vectors.c new file mode 100644 index 000000000..f4685dae8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/vectors.c @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC8xx/vectors.c + * @brief Interrupt vectors for the LPC8xx family. + * + * @defgroup ARMCMx_LPC8xx_VECTORS LPC8xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC8xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void Vector10(void); +extern void Vector14(void); +extern void Vector18(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void Vector30(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); + +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief LPC8xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + Vector10, Vector14, Vector18, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + Vector30, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector18(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector30(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/SAM4L/cmparams.h b/os/ports/GCC/ARMCMx/SAM4L/cmparams.h new file mode 100644 index 000000000..18553d53c --- /dev/null +++ b/os/ports/GCC/ARMCMx/SAM4L/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/SAM4L/cmparams.h + * @brief ARM Cortex-M4 parameters for the ATSAM4L. + * + * @defgroup ARMCMx_SAM4L ATSAM4L Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * ATSAM4L platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld b/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld new file mode 100644 index 000000000..9d363f929 --- /dev/null +++ b/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ATSAM4LC4C memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x00000000, len = 256k + ram : org = 0x20000000, len = 32k + ram2 : org = 0x21000000, len = 2k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/SAM4L/port.mk b/os/ports/GCC/ARMCMx/SAM4L/port.mk new file mode 100644 index 000000000..296a45d45 --- /dev/null +++ b/os/ports/GCC/ARMCMx/SAM4L/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M4 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/SAM4L/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/SAM4L + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/SAM4L/ld diff --git a/os/ports/GCC/ARMCMx/SAM4L/vectors.c b/os/ports/GCC/ARMCMx/SAM4L/vectors.c new file mode 100644 index 000000000..e7a3290ef --- /dev/null +++ b/os/ports/GCC/ARMCMx/SAM4L/vectors.c @@ -0,0 +1,306 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/SAM4L/vectors.c + * @brief Interrupt vectors for the ATSAM4L family. + * + * @defgroup ARMCMx_SAM4L_VECTORS ATSAM4L Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the ATSAM4L family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[80]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void HFLASHC_Handler(void); +extern void PDCA_0_Handler(void); +extern void PDCA_1_Handler(void); +extern void PDCA_2_Handler(void); +extern void PDCA_3_Handler(void); +extern void PDCA_4_Handler(void); +extern void PDCA_5_Handler(void); +extern void PDCA_6_Handler(void); +extern void PDCA_7_Handler(void); +extern void PDCA_8_Handler(void); +extern void PDCA_9_Handler(void); +extern void PDCA_10_Handler(void); +extern void PDCA_11_Handler(void); +extern void PDCA_12_Handler(void); +extern void PDCA_13_Handler(void); +extern void PDCA_14_Handler(void); +extern void PDCA_15_Handler(void); +extern void CRCCU_Handler(void); +extern void USBC_Handler(void); +extern void PEVC_TR_Handler(void); +extern void PEVC_OV_Handler(void); +extern void AESA_Handler(void); +extern void PM_Handler(void); +extern void SCIF_Handler(void); +extern void FREQM_Handler(void); +extern void GPIO_0_Handler(void); +extern void GPIO_1_Handler(void); +extern void GPIO_2_Handler(void); +extern void GPIO_3_Handler(void); +extern void GPIO_4_Handler(void); +extern void GPIO_5_Handler(void); +extern void GPIO_6_Handler(void); +extern void GPIO_7_Handler(void); +extern void GPIO_8_Handler(void); +extern void GPIO_9_Handler(void); +extern void GPIO_10_Handler(void); +extern void GPIO_11_Handler(void); +extern void BPM_Handler(void); +extern void BSCIF_Handler(void); +extern void AST_ALARM_Handler(void); +extern void AST_PER_Handler(void); +extern void AST_OVF_Handler(void); +extern void AST_READY_Handler(void); +extern void AST_CLKREADY_Handler(void); +extern void WDT_Handler(void); +extern void EIC_1_Handler(void); +extern void EIC_2_Handler(void); +extern void EIC_3_Handler(void); +extern void EIC_4_Handler(void); +extern void EIC_5_Handler(void); +extern void EIC_6_Handler(void); +extern void EIC_7_Handler(void); +extern void EIC_8_Handler(void); +extern void IISC_Handler(void); +extern void SPI_Handler(void); +extern void TC00_Handler(void); +extern void TC01_Handler(void); +extern void TC02_Handler(void); +extern void TC010_Handler(void); +extern void TC011_Handler(void); +extern void TC012_Handler(void); +extern void TWIM0_Handler(void); +extern void TWIS0_Handler(void); +extern void TWIM1_Handler(void); +extern void TWIS1_Handler(void); +extern void USART0_Handler(void); +extern void USART1_Handler(void); +extern void USART2_Handler(void); +extern void USART3_Handler(void); +extern void ADCIFE_Handler(void); +extern void DACC_Handler(void); +extern void ACIFC_Handler(void); +extern void ABDACB_Handler(void); +extern void TRNG_Handler(void); +extern void PARC_Handler(void); +extern void CATB_Handler(void); +extern void Dummy_Handler(void); +extern void TWIM2_Handler(void); +extern void TWIM3_Handler(void); +extern void LCDCA_Handler(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + HFLASHC_Handler, PDCA_0_Handler, PDCA_1_Handler, PDCA_2_Handler, + PDCA_3_Handler, PDCA_4_Handler, PDCA_5_Handler, PDCA_6_Handler, + PDCA_7_Handler, PDCA_8_Handler, PDCA_9_Handler, PDCA_10_Handler, + PDCA_11_Handler, PDCA_12_Handler, PDCA_13_Handler, PDCA_14_Handler, + PDCA_15_Handler, CRCCU_Handler, USBC_Handler, PEVC_TR_Handler, + PEVC_OV_Handler, AESA_Handler, PM_Handler, SCIF_Handler, + FREQM_Handler, GPIO_0_Handler, GPIO_1_Handler, GPIO_2_Handler, + GPIO_3_Handler, GPIO_4_Handler, GPIO_5_Handler, GPIO_6_Handler, + GPIO_7_Handler, GPIO_8_Handler, GPIO_9_Handler, GPIO_10_Handler, + GPIO_11_Handler, BPM_Handler, BSCIF_Handler, AST_ALARM_Handler, + AST_PER_Handler, AST_OVF_Handler, AST_READY_Handler, AST_CLKREADY_Handler, + WDT_Handler, EIC_1_Handler, EIC_2_Handler, EIC_3_Handler, + EIC_4_Handler, EIC_5_Handler, EIC_6_Handler, EIC_7_Handler, + EIC_8_Handler, IISC_Handler, SPI_Handler, TC00_Handler, + TC01_Handler, TC02_Handler, TC010_Handler, TC011_Handler, + TC012_Handler, TWIM0_Handler, TWIS0_Handler, TWIM1_Handler, + TWIS1_Handler, USART0_Handler, USART1_Handler, USART2_Handler, + USART3_Handler, ADCIFE_Handler, DACC_Handler, ACIFC_Handler, + ABDACB_Handler, TRNG_Handler, PARC_Handler, CATB_Handler, + Dummy_Handler, TWIM2_Handler, TWIM3_Handler, LCDCA_Handler + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HFLASHC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_0_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_2_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_3_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_4_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_5_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_6_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_7_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_8_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_9_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_10_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_11_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_12_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_13_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_14_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PDCA_15_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void CRCCU_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void USBC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PEVC_TR_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PEVC_OV_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AESA_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PM_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void SCIF_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void FREQM_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_0_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_2_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_3_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_4_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_5_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_6_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_7_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_8_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_9_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_10_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void GPIO_11_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void BPM_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void BSCIF_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AST_ALARM_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AST_PER_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AST_OVF_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AST_READY_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void AST_CLKREADY_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void WDT_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_2_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_3_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_4_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_5_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_6_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_7_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void EIC_8_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void IISC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void SPI_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC00_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC01_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC02_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC010_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC011_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TC012_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIM0_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIS0_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIM1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIS1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void USART0_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void USART1_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void USART2_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void USART3_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void ADCIFE_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void DACC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void ACIFC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void ABDACB_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TRNG_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void PARC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void CATB_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void Dummy_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIM2_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void TWIM3_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); +void LCDCA_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h new file mode 100644 index 000000000..d94591461 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F0xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the STM32F0xx. + * + * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * STM32F0xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld b/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld new file mode 100644 index 000000000..31c34bbf2 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F051x8 memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 64k + ram : org = 0x20000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/port.mk b/os/ports/GCC/ARMCMx/STM32F0xx/port.mk new file mode 100644 index 000000000..5cb296a2b --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F0xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c new file mode 100644 index 000000000..5bd49cde8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F0xx/vectors.c + * @brief Interrupt vectors for the STM32F0xx family. + * + * @defgroup ARMCMx_STM32F0xx_VECTORS STM32F0xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F0xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 000000000..6a7d9113b --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld new file mode 100644 index 000000000..b33f6da63 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F100xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld new file mode 100644 index 000000000..4f29f6702 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld new file mode 100644 index 000000000..01dda22b8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103xE memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 384k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld new file mode 100644 index 000000000..fe5662ab8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103xE memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 512k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld new file mode 100644 index 000000000..8bb4a5c9b --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1m + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld new file mode 100644 index 000000000..51789d096 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F107xC memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/os/ports/GCC/ARMCMx/STM32F1xx/port.mk new file mode 100644 index 000000000..1ba6c672e --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c new file mode 100644 index 000000000..3fe2ab33e --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F1xx/vectors.c + * @brief Interrupt vectors for the STM32F1xx family. + * + * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F1xx family. + * One of the following macros must be defined on the + * compiler command line or in a file named board.h: + * - @p STM32F10X_LD + * - @p STM32F10X_LD_VL + * - @p STM32F10X_MD + * - @p STM32F10X_MD_VL + * - @p STM32F10X_HD + * - @p STM32F10X_XL + * - @p STM32F10X_CL + * . + * This is required in order to include a vectors table with + * the correct length for the specified STM32 model. + * @{ + */ + +#include "ch.h" + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#include "board.h" +#endif + +#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) +#define NUM_VECTORS 46 +#elif defined(STM32F10X_HD) || defined(STM32F10X_XL) +#define NUM_VECTORS 60 +#elif defined(STM32F10X_CL) +#define NUM_VECTORS 68 +#else +#define NUM_VECTORS 43 +#endif + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[NUM_VECTORS]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +#endif +#if defined(STM32F10X_CL) +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +#endif +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + VectorEC, VectorF0, VectorF4, +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + VectorF8, VectorFC, Vector100, Vector104, + Vector108, Vector10C, Vector110, Vector114, + Vector118, Vector11C, Vector120, Vector124, + Vector128, Vector12C, +#endif +#if defined(STM32F10X_CL) + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C +#endif + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif +#if defined(STM32F10X_CL) +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h new file mode 100644 index 000000000..3bb30ff07 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F2xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F2xx. + * + * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F2xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld new file mode 100644 index 000000000..03e741c6d --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F205xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld new file mode 100644 index 000000000..df4b4f2ad --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F207xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/port.mk b/os/ports/GCC/ARMCMx/STM32F2xx/port.mk new file mode 100644 index 000000000..95104160c --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F2xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c new file mode 100644 index 000000000..f516f1ab8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c @@ -0,0 +1,309 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F2xx/vectors.c + * @brief Interrupt vectors for the STM32F2xx family. + * + * @defgroup ARMCMx_STM32F2xx_VECTORS STM32F2xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F2xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[81]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h new file mode 100644 index 000000000..3fce69ce0 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F3xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F3xx. + * + * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F3xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld new file mode 100644 index 000000000..44ae0958d --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F303xC memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 40k + ccmram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld new file mode 100644 index 000000000..4caf87011 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F373xC memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 32k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/port.mk b/os/ports/GCC/ARMCMx/STM32F3xx/port.mk new file mode 100644 index 000000000..09cc8dfd6 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F3xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M4 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c new file mode 100644 index 000000000..20de7cc18 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c @@ -0,0 +1,311 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F3xx/vectors.c + * @brief Interrupt vectors for the STM32F3xx family. + * + * @defgroup ARMCMx_STM32F3xx_VECTORS STM32F3xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F3xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[82]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +extern void Vector184(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180, Vector184 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector184(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..f4dab3e57 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M4 parameters for the STM32F4xx. + * + * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld new file mode 100644 index 000000000..ca33d5779 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F405xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld new file mode 100644 index 000000000..c3cd57687 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld new file mode 100644 index 000000000..e970140f0 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ccmram + + .ccm : + { + PROVIDE(_cmm_start = .); + . = ALIGN(4); + *(.bss.mainthread.*) + . = ALIGN(4); + *(.bss._idle_thread_wa) + . = ALIGN(4); + *(.bss.rlist) + . = ALIGN(4); + *(.bss.vtlist) + . = ALIGN(4); + *(.bss.endmem) + . = ALIGN(4); + *(.bss.nextmem) + . = ALIGN(4); + *(.bss.default_heap) + . = ALIGN(4); + PROVIDE(_cmm_end = .); + } > ccmram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk new file mode 100644 index 000000000..743f825e9 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M4 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c new file mode 100644 index 000000000..6c9cfcff6 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c @@ -0,0 +1,311 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F4xx/vectors.c + * @brief Interrupt vectors for the STM32F4xx family. + * + * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F4xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[82]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +extern void Vector184(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180, Vector184 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector184(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 000000000..67bbb5344 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld b/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld new file mode 100644 index 000000000..1fe4375d7 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32L1152xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 16k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/port.mk b/os/ports/GCC/ARMCMx/STM32L1xx/port.mk new file mode 100644 index 000000000..93b177563 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32L1xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32L1xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c b/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c new file mode 100644 index 000000000..eaf7e0e9d --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c @@ -0,0 +1,228 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32L1xx/vectors.c + * @brief Interrupt vectors for the STM32 family. + * + * @defgroup ARMCMx_STM32L1xx_VECTORS STM32L1xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32L1xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[45]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief STM32L1xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore.c b/os/ports/GCC/ARMCMx/chcore.c new file mode 100644 index 000000000..cd78a287f --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore.c @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h new file mode 100644 index 000000000..5ab33f607 --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -0,0 +1,188 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#warning "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \ + (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c new file mode 100644 index 000000000..599164612 --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp++; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp++; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp--; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (void *)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (void *)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + } +} + +/** + * @brief Post-IRQ switch code. + * @details The switch is performed in thread context then an NMI exception + * is enforced in order to return to the exact point before the + * preemption. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch_from_isr(void) { + + dbg_check_lock(); + chSchDoReschedule(); + dbg_check_unlock(); + asm volatile ("_port_exit_from_isr:" : : : "memory"); +#if CORTEX_ALTERNATE_SWITCH + SCB_ICSR = ICSR_PENDSVSET; + port_unlock(); +#else + SCB_ICSR = ICSR_NMIPENDSET; +#endif + /* The following loop should never be executed, the exception will kick in + immediately.*/ + while (TRUE) + ; +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch(Thread *ntp, Thread *otp) { + register struct intctx *r13 asm ("r13"); + + asm volatile ("push {r4, r5, r6, r7, lr} \n\t" + "mov r4, r8 \n\t" + "mov r5, r9 \n\t" + "mov r6, r10 \n\t" + "mov r7, r11 \n\t" + "push {r4, r5, r6, r7}" : : : "memory"); + + otp->p_ctx.r13 = r13; + r13 = ntp->p_ctx.r13; + + asm volatile ("pop {r4, r5, r6, r7} \n\t" + "mov r8, r4 \n\t" + "mov r9, r5 \n\t" + "mov r10, r6 \n\t" + "mov r11, r7 \n\t" + "pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov r0, r5 \n\t" + "blx r4 \n\t" + "bl chThdExit"); +} + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h new file mode 100644 index 000000000..955778f42 --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -0,0 +1,376 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief Maximum usable priority for normal ISRs. + */ +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#else +#define CORTEX_MAX_KERNEL_PRIORITY 0 +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (void *)(pf); \ + tp->p_ctx.r13->r5 = (void *)(arg); \ + tp->p_ctx.r13->lr = (void *)(_port_thread_start); \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() \ + regarm_t _saved_lr; \ + asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory") + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() asm volatile ("cpsie i" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() asm volatile ("cpsie i" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c new file mode 100644 index 000000000..ad92a9f07 --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -0,0 +1,260 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +#if !CH_OPTIMIZE_SPEED +void _port_lock(void) { + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); +} + +void _port_unlock(void) { + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); +} +#endif + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (void *)_port_switch_from_isr; +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory"); +#endif + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (void *)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** + * @brief Post-IRQ switch code. + * @details Exception handlers return here for context switching. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch_from_isr(void) { + + dbg_check_lock(); + chSchDoReschedule(); + dbg_check_unlock(); + asm volatile ("_port_exit_from_isr:" : : : "memory"); +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) + asm volatile ("svc #0"); +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + SCB_ICSR = ICSR_PENDSVSET; + port_unlock(); + while (TRUE) + ; +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch(Thread *ntp, Thread *otp) { + + asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" + : : : "memory"); +#if CORTEX_USE_FPU + asm volatile ("vpush {s16-s31}" : : : "memory"); +#endif + + asm volatile ("str sp, [%1, #12] \n\t" + "ldr sp, [%0, #12]" : : "r" (ntp), "r" (otp)); + +#if CORTEX_USE_FPU + asm volatile ("vpop {s16-s31}" : : : "memory"); +#endif + asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" + : : : "memory"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov r0, r5 \n\t" + "blx r4 \n\t" + "bl chThdExit"); +} + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h new file mode 100644 index 000000000..86921ee64 --- /dev/null +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -0,0 +1,525 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/** + * @brief NVIC PRIGROUP initialization expression. + * @details The default assigns all available priority bits as preemption + * priority with no sub-priority. + */ +#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) +#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief Maximum usable priority for normal ISRs. + */ +#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) +#else + +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (void *)(pf); \ + tp->p_ctx.r13->r5 = (void *)(arg); \ + tp->p_ctx.r13->lr = (void *)(_port_thread_start); \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +#define port_lock() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ +} +#else /* !CH_OPTIMIZE_SPEED */ +#define port_lock() { \ + asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \ +} +#endif /* !CH_OPTIMIZE_SPEED */ +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() asm volatile ("cpsid i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +#define port_unlock() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ +} +#else /* !CH_OPTIMIZE_SPEED */ +#define port_unlock() { \ + asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \ +} +#endif /* !CH_OPTIMIZE_SPEED */ +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() asm volatile ("cpsie i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ + asm volatile ("msr BASEPRI, %0 \n\t" \ + "cpsie i" : : "r" (tmp) : "memory"); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() asm volatile ("cpsid i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ + asm volatile ("msr BASEPRI, %0 \n\t" \ + "cpsie i" : : "r" (tmp) : "memory"); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() asm volatile ("cpsie i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + asm volatile ("wfi" : : : "memory"); \ +} +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#if !CH_OPTIMIZE_SPEED + void _port_lock(void); + void _port_unlock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/chtypes.h b/os/ports/GCC/ARMCMx/chtypes.h new file mode 100644 index 000000000..a94ae24ae --- /dev/null +++ b/os/ports/GCC/ARMCMx/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c new file mode 100644 index 000000000..5151de43e --- /dev/null +++ b/os/ports/GCC/ARMCMx/crt0.c @@ -0,0 +1,354 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/crt0.c + * @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT. + * + * @addtogroup ARMCMx_STARTUP + * @{ + */ + +#include + +#if !defined(FALSE) +#define FALSE 0 +#endif + +#if !defined(TRUE) +#define TRUE (!FALSE) +#endif + +#define SCB_CPACR *((uint32_t *)0xE000ED88U) +#define SCB_FPCCR *((uint32_t *)0xE000EF34U) +#define SCB_FPDSCR *((uint32_t *)0xE000EF3CU) +#define FPCCR_ASPEN (0x1U << 31) +#define FPCCR_LSPEN (0x1U << 30) + +typedef void (*funcp_t)(void); +typedef funcp_t * funcpp_t; + +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +/* + * Area fill code, it is a macro because here functions cannot be called + * until stacks are initialized. + */ +#define fill32(start, end, filler) { \ + uint32_t *p1 = start; \ + uint32_t *p2 = end; \ + while (p1 < p2) \ + *p1++ = filler; \ +} + +/*===========================================================================*/ +/** + * @name Startup settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Control special register initialization value. + * @details The system is setup to run in privileged mode using the PSP + * stack (dual stack mode). + */ +#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) +#define CRT0_CONTROL_INIT 0x00000002 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) +#define CRT0_STACKS_FILL_PATTERN 0x55555555 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) +#define CRT0_INIT_STACKS TRUE +#endif + +/** + * @brief DATA segment initialization switch. + */ +#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) +#define CRT0_INIT_DATA TRUE +#endif + +/** + * @brief BSS segment initialization switch. + */ +#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) +#define CRT0_INIT_BSS TRUE +#endif + +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS TRUE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Symbols from the scatter file + */ +/*===========================================================================*/ + +/** + * @brief Main stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the main stack lower boundary. + */ +extern uint32_t __main_stack_base__; + +/** + * + * @brief Main stack initial position. + * @details This symbol must be exported by the linker script and represents + * the main stack initial position. + */ +extern uint32_t __main_stack_end__; + +/** + * @brief Process stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the process stack lower boundary. + */ +extern uint32_t __process_stack_base__; + +/** + * @brief Process stack initial position. + * @details This symbol must be exported by the linker script and represents + * the process stack initial position. + */ +extern uint32_t __process_stack_end__; + +/** + * @brief ROM image of the data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _textdata; + +/** + * @brief Data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _data; + +/** + * @brief Data segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _edata; + +/** + * @brief BSS segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_start; + +/** + * @brief BSS segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_end; + +/** + * @brief Constructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_start; + +/** + * @brief Constructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_end; + +/** + * @brief Destructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_start; + +/** + * @brief Destructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_end; + +/** @} */ + +/** + * @brief Application @p main() function. + */ +extern void main(void); + +/** + * @brief Early initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __early_init(void) {} + +/** + * @brief Late initialization. + * @details This hook is invoked after the DATA and BSS segments + * initialization and before any static constructor. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __late_init(void) {} + +/** + * @brief Default @p main() function exit handler. + * @details This handler is invoked or the @p main() function exit. The + * default behavior is to enter an infinite loop. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak, naked)) +#endif +void _default_exit(void) { + while (1) + ; +} + +/** + * @brief Reset vector. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void ResetHandler(void) { + uint32_t psp, reg; + + /* Process Stack initialization, it is allocated starting from the + symbol __process_stack_end__ and its lower limit is the symbol + __process_stack_base__.*/ + asm volatile ("cpsid i"); + psp = SYMVAL(__process_stack_end__); + asm volatile ("msr PSP, %0" : : "r" (psp)); + +#if CORTEX_USE_FPU + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access.*/ + SCB_CPACR |= 0x00F00000; + + /* FPSCR and FPDSCR initially zero.*/ + reg = 0; + asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory"); + SCB_FPDSCR = reg; + + /* CPU mode initialization, enforced FPCA bit.*/ + reg = CRT0_CONTROL_INIT | 4; +#else + /* CPU mode initialization.*/ + reg = CRT0_CONTROL_INIT; +#endif + asm volatile ("msr CONTROL, %0" : : "r" (reg)); + asm volatile ("isb"); + +#if CRT0_INIT_STACKS + /* Main and Process stacks initialization.*/ + fill32(&__main_stack_base__, + &__main_stack_end__, + CRT0_STACKS_FILL_PATTERN); + fill32(&__process_stack_base__, + &__process_stack_end__, + CRT0_STACKS_FILL_PATTERN); +#endif + + /* Early initialization hook invocation.*/ + __early_init(); + +#if CRT0_INIT_DATA + /* DATA segment initialization.*/ + { + uint32_t *tp, *dp; + + tp = &_textdata; + dp = &_data; + while (dp < &_edata) + *dp++ = *tp++; + } +#endif + +#if CRT0_INIT_BSS + /* BSS segment initialization.*/ + fill32(&_bss_start, &_bss_end, 0); +#endif + + /* Late initialization hook invocation.*/ + __late_init(); + +#if CRT0_CALL_CONSTRUCTORS + /* Constructors invocation.*/ + { + funcpp_t fpp = &__init_array_start; + while (fpp < &__init_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking application main() function.*/ + main(); + +#if CRT0_CALL_DESTRUCTORS + /* Destructors invocation.*/ + { + funcpp_t fpp = &__fini_array_start; + while (fpp < &__fini_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking the exit handler.*/ + _default_exit(); +} + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox new file mode 100644 index 000000000..4f209e654 --- /dev/null +++ b/os/ports/GCC/ARMCMx/port.dox @@ -0,0 +1,251 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the GCC compiler. + * + * @section ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
    + * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section ARMCMx_NOTES ARM Cortex-Mx/GCC port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/GCC/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * . + * @ingroup gcc + */ + +/** + * @defgroup ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup ARMCMx_CORE + */ + +/** + * @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup ARMCMx_CORE + */ + +/** + * @defgroup ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in + * the linker script (also known as scatter file). + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# DATA and BSS segments are initialized. + * -# Constructors are invoked. + * -# The @p main() function is invoked with no parameters. + * -# Destructors are invoked. + * -# A branch is performed to the weak symbol @p _default_exit(). The + * default code is an endless empty loop. + * . + * @section ARMCMx_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p ResetHandler and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__, end of RAM. + * - @p __main_stack_base__, main stack lower boundary. + * - @p __main_stack_end__, main stack initial position. + * - @p __process_stack_base__, process stack lower boundary. + * - @p __process_stack_end__, process stack initial position. + * - @p _textdata, address of the data segment source read only data. + * - @p _data, start of the data segment. + * - @p _edata, end of the data segment end location. + * - @p _bss_start, start of the BSS. + * - @p _bss_end, end of the BSS segment. + * - @p __init_array_start, start of the constructors array. + * - @p __init_array_end, end of the constructors array. + * - @p __fini_array_start, start of the destructors array. + * - @p __fini_array_end, end of the destructors array. + * . + * Additionally the kernel expects the following symbols: + * - @p __main_thread_stack_base__, this symbol is required when the + * stack checking is enabled (CH_DBG_ENABLE_STACK_CHECK==TRUE), + * it is an alias of @p __process_stack_base__ in this port. + * - @p __heap_base__ and @p __heap_end__, those symbols are required + * if the memory core manager is enabled (CH_USE_MEMCORE==TRUE) + * with a default core size set to zero (CH_MEMCORE_SIZE==0). + * . + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup ARMCMx + */ diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk new file mode 100644 index 000000000..33531d201 --- /dev/null +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -0,0 +1,220 @@ +# ARM Cortex-Mx common makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections -fno-common +endif + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/os/ports/GCC/AVR/chcore.c b/os/ports/GCC/AVR/chcore.c new file mode 100644 index 000000000..d7a33ecad --- /dev/null +++ b/os/ports/GCC/AVR/chcore.c @@ -0,0 +1,133 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AVR/chcore.c + * @brief AVR architecture port code. + * + * @addtogroup AVR_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked, weak)) +#endif +void port_switch(Thread *ntp, Thread *otp) { + + asm volatile ("push r2"); + asm volatile ("push r3"); + asm volatile ("push r4"); + asm volatile ("push r5"); + asm volatile ("push r6"); + asm volatile ("push r7"); + asm volatile ("push r8"); + asm volatile ("push r9"); + asm volatile ("push r10"); + asm volatile ("push r11"); + asm volatile ("push r12"); + asm volatile ("push r13"); + asm volatile ("push r14"); + asm volatile ("push r15"); + asm volatile ("push r16"); + asm volatile ("push r17"); + asm volatile ("push r28"); + asm volatile ("push r29"); + + asm volatile ("movw r30, r22"); + asm volatile ("in r0, 0x3d"); + asm volatile ("std Z+5, r0"); + asm volatile ("in r0, 0x3e"); + asm volatile ("std Z+6, r0"); + + asm volatile ("movw r30, r24"); + asm volatile ("ldd r0, Z+5"); + asm volatile ("out 0x3d, r0"); + asm volatile ("ldd r0, Z+6"); + asm volatile ("out 0x3e, r0"); + + asm volatile ("pop r29"); + asm volatile ("pop r28"); + asm volatile ("pop r17"); + asm volatile ("pop r16"); + asm volatile ("pop r15"); + asm volatile ("pop r14"); + asm volatile ("pop r13"); + asm volatile ("pop r12"); + asm volatile ("pop r11"); + asm volatile ("pop r10"); + asm volatile ("pop r9"); + asm volatile ("pop r8"); + asm volatile ("pop r7"); + asm volatile ("pop r6"); + asm volatile ("pop r5"); + asm volatile ("pop r4"); + asm volatile ("pop r3"); + asm volatile ("pop r2"); + asm volatile ("ret"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("movw r24, r4"); + asm volatile ("movw r30, r2"); + asm volatile ("icall"); + asm volatile ("call chThdExit"); +} + +/** @} */ diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h new file mode 100644 index 000000000..203c6886f --- /dev/null +++ b/os/ports/GCC/AVR/chcore.h @@ -0,0 +1,325 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AVR/chcore.h + * @brief AVR architecture port macros and structures. + * + * @addtogroup AVR_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * @brief If enabled allows the idle thread to enter a low power mode. + */ +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 +#endif + +/** + * @brief Macro defining the AVR architecture. + */ +#define CH_ARCHITECTURE_AVR + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "AVR" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "MegaAVR" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/** + * @brief 8 bits stack and memory alignment enforcement. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The field @p _next is not part of the context, it represents the + * offset of the structure relative to the stack pointer. + */ +struct extctx { + uint8_t _next; + uint8_t r31; + uint8_t r30; + uint8_t r27; + uint8_t r26; + uint8_t r25; + uint8_t r24; + uint8_t r23; + uint8_t r22; + uint8_t r21; + uint8_t r20; + uint8_t r19; + uint8_t r18; + uint8_t sr; + uint8_t r1; + uint8_t r0; + uint16_t pc; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + * @note The field @p _next is not part of the context, it represents the + * offset of the structure relative to the stack pointer. + */ +struct intctx { + uint8_t _next; + uint8_t r29; + uint8_t r28; + uint8_t r17; + uint8_t r16; + uint8_t r15; + uint8_t r14; + uint8_t r13; + uint8_t r12; + uint8_t r11; + uint8_t r10; + uint8_t r9; + uint8_t r8; + uint8_t r7; + uint8_t r6; + uint8_t r5; + uint8_t r4; + uint8_t r3; + uint8_t r2; + uint8_t pcl; + uint8_t pch; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In the AVR port this structure just holds a pointer to the + * @p intctx structure representing the stack pointer at the time + * of the context switch. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.sp->r2 = (int)pf; \ + tp->p_ctx.sp->r3 = (int)pf >> 8; \ + tp->p_ctx.sp->r4 = (int)arg; \ + tp->p_ctx.sp->r5 = (int)arg >> 8; \ + tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \ + tp->p_ctx.sp->pch = (int)_port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 8. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 8 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port the default is 32 bytes per thread. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + * @note This code tricks the compiler to save all the specified registers + * by "touching" them. + */ +#define PORT_IRQ_PROLOGUE() { \ + asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \ + "r25", "r26", "r27", "r30", "r31"); \ +} + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) ISR(id) + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + * @note Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("cli" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + * @note Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile ("sei" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("cli" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("cli" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("sei" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note This port function is implemented as inlined code for performance + * reasons. + */ +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + asm volatile ("sleep" : : : "memory"); \ +} +#else +#define port_wait_for_interrupt() +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_switch(Thread *ntp, Thread *otp); + void port_halt(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/AVR/chtypes.h b/os/ports/GCC/AVR/chtypes.h new file mode 100644 index 000000000..59d896af4 --- /dev/null +++ b/os/ports/GCC/AVR/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AVR/chtypes.h + * @brief AVR architecture port system types. + * + * @addtogroup AVR_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint8_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef uint8_t eventid_t; /**< Event Id. */ +typedef uint8_t eventmask_t; /**< Event mask. */ +typedef uint8_t flagsmask_t; /**< Event flags. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int8_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/AVR/port.dox b/os/ports/GCC/AVR/port.dox new file mode 100644 index 000000000..002a37bbc --- /dev/null +++ b/os/ports/GCC/AVR/port.dox @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup AVR MegaAVR + * @details AVR port for the GCC compiler. + * + * @section AVR_STATES Mapping of the System States in the AVR port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the AVR + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. This state is entered with the execution of the specific + * instruction @p sleep. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. Not present in this architecture. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section AVR_NOTES The AVR port notes + * - The AVR does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./ports/AVR/chcore.h. + * . + * @ingroup gcc + */ + +/** + * @defgroup AVR_CONF Configuration Options + * @details AVR Configuration Options. The AVR port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
    + * The default for this value is @p 32, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * . + * @ingroup AVR + */ + +/** + * @defgroup AVR_CORE Core Port Implementation + * @details AVR specific port code, structures and macros. + * + * @ingroup AVR + */ + + /** + * @defgroup AVR_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the AVR, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup AVR + */ diff --git a/os/ports/GCC/AVR/port.mk b/os/ports/GCC/AVR/port.mk new file mode 100644 index 000000000..7cafb56b2 --- /dev/null +++ b/os/ports/GCC/AVR/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT AVR port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/AVR/chcore.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/GCC/AVR diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h new file mode 100644 index 000000000..22dde173d --- /dev/null +++ b/os/ports/GCC/MSP430/chcore.h @@ -0,0 +1,315 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/chcore.h + * @brief MSP430 architecture port macros and structures. + * + * @addtogroup MSP430_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * @brief Enables the use of a wait state in the idle thread loop. + */ +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 +#endif + +/** + * @brief Macro defining the MSP430 architecture. + */ +#define CH_ARCHITECTURE_MSP430 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "MSP430" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "MSP430" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/** + * @brief 16 bits stack and memory alignment enforcement. + */ +typedef uint16_t stkalign_t; + +/** + * @brief Generic MSP430 register. + */ +typedef void *regmsp_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { + regmsp_t r12; + regmsp_t r13; + regmsp_t r14; + regmsp_t r15; + regmsp_t sr; + regmsp_t pc; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { + regmsp_t r4; + regmsp_t r5; + regmsp_t r6; + regmsp_t r7; + regmsp_t r8; + regmsp_t r9; + regmsp_t r10; + regmsp_t r11; + regmsp_t pc; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.sp->r10 = pf; \ + tp->p_ctx.sp->r11 = arg; \ + tp->p_ctx.sp->pc = _port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port the default is 32 bytes per thread. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +#define ISRNAME(pre, id) pre##id + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) ISR(id, ISRNAME(vect, id)) + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + * @note Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("dint" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + * @note Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile ("eint" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependen#define PORT_IRQ_EPILOGUE() { \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ +} + * t, + * in its simplest form it is void. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("dint" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("dint" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("eint" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note This port function is implemented as inlined code for performance + * reasons. + * @note The port code does not define a low power mode, this macro has to + * be defined externally. The default implementation is a "nop", not + * a real low power mode. + */ +#if ENABLE_WFI_IDLE != 0 +#ifndef port_wait_for_interrupt +#define port_wait_for_interrupt() { \ + asm volatile ("nop" : : : "memory"); \ +} +#endif +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Wrapper of the assembler @p _port_switch() function. + */ +#define port_switch(ntp, otp) _port_switch(ntp, otp) + +/** + * @brief Wrapper of the assembler @p _port_halt() function. + */ +#define port_halt() _port_halt() + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *ntp, Thread *otp); + void _port_halt(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/MSP430/chcoreasm.s b/os/ports/GCC/MSP430/chcoreasm.s new file mode 100644 index 000000000..8c42d0856 --- /dev/null +++ b/os/ports/GCC/MSP430/chcoreasm.s @@ -0,0 +1,66 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "chconf.h" + +#define FALSE 0 +#define TRUE 1 + + .text + .p2align 1, 0 + .weak _port_switch +_port_switch: + push r11 + push r10 + push r9 + push r8 + push r7 + push r6 + push r5 + push r4 + mov r1, 6(r14) + mov 6(r15), r1 + pop r4 + pop r5 + pop r6 + pop r7 + pop r8 + pop r9 + pop r10 + pop r11 + ret + + .p2align 1, 0 + .weak _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + call #dbg_check_unlock +#endif + eint + mov r11, r15 + call r10 + call #chThdExit + ; Falls into _port_halt + + .p2align 1, 0 + .weak _port_halt +_port_halt: + dint +.L1: jmp .L1 diff --git a/os/ports/GCC/MSP430/chtypes.h b/os/ports/GCC/MSP430/chtypes.h new file mode 100644 index 000000000..84ced2aaf --- /dev/null +++ b/os/ports/GCC/MSP430/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/chtypes.h + * @brief MSP430 architecture port system types. + * + * @addtogroup MSP430_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint16_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef int16_t eventid_t; /**< Event Id. */ +typedef uint16_t eventmask_t; /**< Event mask. */ +typedef uint16_t flagsmask_t; /**< Event flags. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int16_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/MSP430/port.dox b/os/ports/GCC/MSP430/port.dox new file mode 100644 index 000000000..8f316d0c4 --- /dev/null +++ b/os/ports/GCC/MSP430/port.dox @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup MSP430 MSP430 + * @details MSP430 port for the GCC compiler. + * + * @section MSP430_INTRO Introduction + * This port supports all the cores implementing the MSP430 architecture. + * + * @section MSP430_STATES Mapping of the System States in the MSP430 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the MSP430 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Not yet implemented. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The MSP430 has several non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section MSP430_NOTES The MSP430 port notes + * - The MSP430 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK configuration options. + * - The state of the hardware multiplier is not saved in the thread context, + * make sure to use it in Suspended state (interrupts masked). + * - The port code does not define the switch to a low power mode for the + * idle thread because the MSP430 has several low power modes. You can + * select the proper low power mode for you application by defining the + * macro @p port_wait_for_interrupt(). + * . + * @ingroup gcc + */ + +/** + * @defgroup MSP430_CONF Configuration Options + * @details MSP430 Configuration Options. The MSP430 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
    + * The default for this value is @p 32, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * . + * @ingroup MSP430 + */ + +/** + * @defgroup MSP430_CORE Core Port Implementation + * @details MSP430 specific port code, structures and macros. + * + * @ingroup MSP430 + */ + + /** + * @defgroup MSP430_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the MSP430, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup MSP430 + */ diff --git a/os/ports/GCC/MSP430/port.mk b/os/ports/GCC/MSP430/port.mk new file mode 100644 index 000000000..8291fa9d9 --- /dev/null +++ b/os/ports/GCC/MSP430/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT MSP430 port files. +PORTSRC = + +PORTASM = ${CHIBIOS}/os/ports/GCC/MSP430/chcoreasm.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/MSP430 diff --git a/os/ports/GCC/MSP430/rules.mk b/os/ports/GCC/MSP430/rules.mk new file mode 100644 index 000000000..e5df10916 --- /dev/null +++ b/os/ports/GCC/MSP430/rules.mk @@ -0,0 +1,87 @@ +# MSP430 makefile scripts and rules. + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# Source files groups +SRC = $(CSRC)$(CPPSRC) + +# Object files groups +COBJS = $(CSRC:.c=.o) +CPPOBJS = $(CPPSRC:.cpp=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(COBJS) $(CPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +MCFLAGS = -mmcu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(CPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(COBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) + -rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/os/ports/GCC/PPC/SPC560BCxx/bam.s b/os/ports/GCC/PPC/SPC560BCxx/bam.s new file mode 100644 index 000000000..f62c854dd --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/bam.s @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/bam.s + * @brief SPC560BCxx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560BCxx/core.s b/os/ports/GCC/PPC/SPC560BCxx/core.s new file mode 100644 index 000000000..e4de3d453 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/core.s @@ -0,0 +1,214 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/core.s + * @brief e200z0 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld new file mode 100644 index 000000000..2b81984d1 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560B44 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 384k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 28k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 4KB because the IVPR register + requires an alignment of 4KB and the first 4KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 4KB by using special sections.*/ + . = ALIGN(0x00001000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld new file mode 100644 index 000000000..7ccede017 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560B50 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 512k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 32k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 4KB because the IVPR register + requires an alignment of 4KB and the first 4KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 4KB by using special sections.*/ + . = ALIGN(0x00001000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560BCxx/port.mk b/os/ports/GCC/PPC/SPC560BCxx/port.mk new file mode 100644 index 000000000..c798e2886 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC560BCxx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/ld diff --git a/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h b/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h new file mode 100644 index 000000000..5d4d9a37e --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/ppcparams.h + * @brief PowerPC parameters for the SPC560B/Cxx. + * + * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560BCxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 20 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560BCxx/vectors.h b/os/ports/GCC/PPC/SPC560BCxx/vectors.h new file mode 100644 index 000000000..4a54e0f70 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 217 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560BCxx/vectors.s b/os/ports/GCC/PPC/SPC560BCxx/vectors.s new file mode 100644 index 000000000..1ed6ddde3 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560BCxx/vectors.s @@ -0,0 +1,379 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/vectors.s + * @brief SPC560BCxx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154, vector155 + .long vector156, vector157, vector158, vector159 + .long vector160, vector161, vector162, vector163 + .long vector164, vector165, vector166, vector167 + .long vector168, vector169, vector170, vector171 + .long vector172, vector173, vector174, vector175 + .long vector176, vector177, vector178, vector179 + .long vector180, vector181, vector182, vector183 + .long vector184, vector185, vector186, vector187 + .long vector188, vector189, vector190, vector191 + .long vector192, vector193, vector194, vector195 + .long vector196, vector197, vector198, vector199 + .long vector200, vector201, vector202, vector203 + .long vector204, vector205, vector206, vector207 + .long vector208, vector209, vector210, vector211 + .long vector212, vector213, vector214, vector215 + .long vector216 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154, vector155 + .weak vector156, vector157, vector158, vector159 + .weak vector160, vector161, vector162, vector163 + .weak vector164, vector165, vector166, vector167 + .weak vector168, vector169, vector170, vector171 + .weak vector172, vector173, vector174, vector175 + .weak vector176, vector177, vector178, vector179 + .weak vector180, vector181, vector182, vector183 + .weak vector184, vector185, vector186, vector187 + .weak vector188, vector189, vector190, vector191 + .weak vector192, vector193, vector194, vector195 + .weak vector196, vector197, vector198, vector199 + .weak vector200, vector201, vector202, vector203 + .weak vector204, vector205, vector206, vector207 + .weak vector208, vector209, vector210, vector211 + .weak vector212, vector213, vector214, vector215 + .weak vector216 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: +vector155: +vector156: +vector157: +vector158: +vector159: +vector160: +vector161: +vector162: +vector163: +vector164: +vector165: +vector166: +vector167: +vector168: +vector169: +vector170: +vector171: +vector172: +vector173: +vector174: +vector175: +vector176: +vector177: +vector178: +vector179: +vector180: +vector181: +vector182: +vector183: +vector184: +vector185: +vector186: +vector187: +vector188: +vector189: +vector190: +vector191: +vector192: +vector193: +vector194: +vector195: +vector196: +vector197: +vector198: +vector199: +vector200: +vector201: +vector202: +vector203: +vector204: +vector205: +vector206: +vector207: +vector208: +vector209: +vector210: +vector211: +vector212: +vector213: +vector214: +vector215: +vector216: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Dxx/bam.s b/os/ports/GCC/PPC/SPC560Dxx/bam.s new file mode 100644 index 000000000..28792c3c3 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/bam.s @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Dxx/bam.s + * @brief SPC560Dxx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Dxx/core.s b/os/ports/GCC/PPC/SPC560Dxx/core.s new file mode 100644 index 000000000..434f96fa3 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/core.s @@ -0,0 +1,214 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Dxx/core.s + * @brief e200z0 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld new file mode 100644 index 000000000..78a18c527 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560D30 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 128k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 12k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 4KB because the IVPR register + requires an alignment of 4KB and the first 4KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 4KB by using special sections.*/ + . = ALIGN(0x00001000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld new file mode 100644 index 000000000..7283994bf --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560D40 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 256k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 16k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 4KB because the IVPR register + requires an alignment of 4KB and the first 4KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 4KB by using special sections.*/ + . = ALIGN(0x00001000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560Dxx/port.mk b/os/ports/GCC/PPC/SPC560Dxx/port.mk new file mode 100644 index 000000000..e0756b8c2 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC560Dxx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/ld diff --git a/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h new file mode 100644 index 000000000..5d4d9a37e --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/ppcparams.h + * @brief PowerPC parameters for the SPC560B/Cxx. + * + * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560BCxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 20 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Dxx/vectors.h b/os/ports/GCC/PPC/SPC560Dxx/vectors.h new file mode 100644 index 000000000..4347796d5 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 155 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Dxx/vectors.s b/os/ports/GCC/PPC/SPC560Dxx/vectors.s new file mode 100644 index 000000000..2536e51ce --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Dxx/vectors.s @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Dxx/vectors.s + * @brief SPC560Dxx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/bam.s b/os/ports/GCC/PPC/SPC560Pxx/bam.s new file mode 100644 index 000000000..d1feed8d3 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/bam.s @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Pxx/bam.s + * @brief SPC560Pxx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/core.s b/os/ports/GCC/PPC/SPC560Pxx/core.s new file mode 100644 index 000000000..43d145ddd --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/core.s @@ -0,0 +1,214 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Pxx/core.s + * @brief e200z0 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld new file mode 100644 index 000000000..de3e0bc37 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560P44 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 384k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 36k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 64KB because the IVPR register + requires an alignment of 64KB and the first 64KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 64KB by using special sections.*/ + . = ALIGN(0x00010000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld new file mode 100644 index 000000000..e02b092a5 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560P44 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 512k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 40k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x00000800); + KEEP(*(.vectors)) + /* Note, have to waste the first 64KB because the IVPR register + requires an alignment of 64KB and the first 64KB cannot be used, + IVOR0 would conflict with the BAM word. Applications could + allocate code or data in the first 64KB by using special sections.*/ + . = ALIGN(0x00010000); + __ivpr_base__ = .; + KEEP(*(.ivors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC560Pxx/port.mk b/os/ports/GCC/PPC/SPC560Pxx/port.mk new file mode 100644 index 000000000..112728112 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC560Pxx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/ld diff --git a/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h new file mode 100644 index 000000000..febb90017 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Pxx/ppcparams.h + * @brief PowerPC parameters for the SPC560Pxx. + * + * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560Pxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/vectors.h b/os/ports/GCC/PPC/SPC560Pxx/vectors.h new file mode 100644 index 000000000..fc2f6e47c --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Pxx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 261 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/vectors.s b/os/ports/GCC/PPC/SPC560Pxx/vectors.s new file mode 100644 index 000000000..8fcbb27d9 --- /dev/null +++ b/os/ports/GCC/PPC/SPC560Pxx/vectors.s @@ -0,0 +1,445 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Pxx/vectors.s + * @brief SPC560Pxx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154, vector155 + .long vector156, vector157, vector158, vector159 + .long vector160, vector161, vector162, vector163 + .long vector164, vector165, vector166, vector167 + .long vector168, vector169, vector170, vector171 + .long vector172, vector173, vector174, vector175 + .long vector176, vector177, vector178, vector179 + .long vector180, vector181, vector182, vector183 + .long vector184, vector185, vector186, vector187 + .long vector188, vector189, vector190, vector191 + .long vector192, vector193, vector194, vector195 + .long vector196, vector197, vector198, vector199 + .long vector200, vector201, vector202, vector203 + .long vector204, vector205, vector206, vector207 + .long vector208, vector209, vector210, vector211 + .long vector212, vector213, vector214, vector215 + .long vector216, vector217, vector218, vector219 + .long vector220, vector221, vector222, vector223 + .long vector224, vector225, vector226, vector227 + .long vector228, vector229, vector230, vector231 + .long vector232, vector233, vector234, vector235 + .long vector236, vector237, vector238, vector239 + .long vector240, vector241, vector242, vector243 + .long vector244, vector245, vector246, vector247 + .long vector248, vector249, vector250, vector251 + .long vector252, vector253, vector254, vector255 + .long vector256, vector257, vector258, vector259 + .long vector260 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154, vector155 + .weak vector156, vector157, vector158, vector159 + .weak vector160, vector161, vector162, vector163 + .weak vector164, vector165, vector166, vector167 + .weak vector168, vector169, vector170, vector171 + .weak vector172, vector173, vector174, vector175 + .weak vector176, vector177, vector178, vector179 + .weak vector180, vector181, vector182, vector183 + .weak vector184, vector185, vector186, vector187 + .weak vector188, vector189, vector190, vector191 + .weak vector192, vector193, vector194, vector195 + .weak vector196, vector197, vector198, vector199 + .weak vector200, vector201, vector202, vector203 + .weak vector204, vector205, vector206, vector207 + .weak vector208, vector209, vector210, vector211 + .weak vector212, vector213, vector214, vector215 + .weak vector216, vector217, vector218, vector219 + .weak vector220, vector221, vector222, vector223 + .weak vector224, vector225, vector226, vector227 + .weak vector228, vector229, vector230, vector231 + .weak vector232, vector233, vector234, vector235 + .weak vector236, vector237, vector238, vector239 + .weak vector240, vector241, vector242, vector243 + .weak vector244, vector245, vector246, vector247 + .weak vector248, vector249, vector250, vector251 + .weak vector252, vector253, vector254, vector255 + .weak vector256, vector257, vector258, vector259 + .weak vector260 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: +vector155: +vector156: +vector157: +vector158: +vector159: +vector160: +vector161: +vector162: +vector163: +vector164: +vector165: +vector166: +vector167: +vector168: +vector169: +vector170: +vector171: +vector172: +vector173: +vector174: +vector175: +vector176: +vector177: +vector178: +vector179: +vector180: +vector181: +vector182: +vector183: +vector184: +vector185: +vector186: +vector187: +vector188: +vector189: +vector190: +vector191: +vector192: +vector193: +vector194: +vector195: +vector196: +vector197: +vector198: +vector199: +vector200: +vector201: +vector202: +vector203: +vector204: +vector205: +vector206: +vector207: +vector208: +vector209: +vector210: +vector211: +vector212: +vector213: +vector214: +vector215: +vector216: +vector217: +vector218: +vector219: +vector220: +vector221: +vector222: +vector223: +vector224: +vector225: +vector226: +vector227: +vector228: +vector229: +vector230: +vector231: +vector232: +vector233: +vector234: +vector235: +vector236: +vector237: +vector238: +vector239: +vector240: +vector241: +vector242: +vector243: +vector244: +vector245: +vector246: +vector247: +vector248: +vector249: +vector250: +vector251: +vector252: +vector253: +vector254: +vector255: +vector256: +vector257: +vector258: +vector259: +vector260: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/bam.s b/os/ports/GCC/PPC/SPC563Mxx/bam.s new file mode 100644 index 000000000..19ce1e014 --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/bam.s @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/bam.s + * @brief SPC563Mxx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" +#if PPC_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/core.s b/os/ports/GCC/PPC/SPC563Mxx/core.s new file mode 100644 index 000000000..a1b3ca37b --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/core.s @@ -0,0 +1,191 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/core.s + * @brief e200z3 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld b/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld new file mode 100644 index 000000000..25fe1143b --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC563M64 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 1536k + ram : org = 0x40000000, len = 94k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.crt0)) + KEEP(*(.handlers)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC563Mxx/port.mk b/os/ports/GCC/PPC/SPC563Mxx/port.mk new file mode 100644 index 000000000..5f5a1b309 --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC563Mxx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/ld diff --git a/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h b/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h new file mode 100644 index 000000000..94aa98ffd --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/ppcparams.h + * @brief PowerPC parameters for the SPC563Mxx. + * + * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC563Mxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z3 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/vectors.h b/os/ports/GCC/PPC/SPC563Mxx/vectors.h new file mode 100644 index 000000000..9d6d744f6 --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 360 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/vectors.s b/os/ports/GCC/PPC/SPC563Mxx/vectors.s new file mode 100644 index 000000000..dc4cbdfef --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/vectors.s @@ -0,0 +1,592 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/vectors.s + * @brief SPC563Mxx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154, vector155 + .long vector156, vector157, vector158, vector159 + .long vector160, vector161, vector162, vector163 + .long vector164, vector165, vector166, vector167 + .long vector168, vector169, vector170, vector171 + .long vector172, vector173, vector174, vector175 + .long vector176, vector177, vector178, vector179 + .long vector180, vector181, vector182, vector183 + .long vector184, vector185, vector186, vector187 + .long vector188, vector189, vector190, vector191 + .long vector192, vector193, vector194, vector195 + .long vector196, vector197, vector198, vector199 + .long vector200, vector201, vector202, vector203 + .long vector204, vector205, vector206, vector207 + .long vector208, vector209, vector210, vector211 + .long vector212, vector213, vector214, vector215 + .long vector216, vector217, vector218, vector219 + .long vector220, vector221, vector222, vector223 + .long vector224, vector225, vector226, vector227 + .long vector228, vector229, vector230, vector231 + .long vector232, vector233, vector234, vector235 + .long vector236, vector237, vector238, vector239 + .long vector240, vector241, vector242, vector243 + .long vector244, vector245, vector246, vector247 + .long vector248, vector249, vector250, vector251 + .long vector252, vector253, vector254, vector255 + .long vector256, vector257, vector258, vector259 + .long vector260, vector261, vector262, vector263 + .long vector264, vector265, vector266, vector267 + .long vector268, vector269, vector270, vector271 + .long vector272, vector273, vector274, vector275 + .long vector276, vector277, vector278, vector279 + .long vector280, vector281, vector282, vector283 + .long vector284, vector285, vector286, vector287 + .long vector288, vector289, vector290, vector291 + .long vector292, vector293, vector294, vector295 + .long vector296, vector297, vector298, vector299 + .long vector300, vector301, vector302, vector303 + .long vector304, vector305, vector306, vector307 + .long vector308, vector309, vector310, vector311 + .long vector312, vector313, vector314, vector315 + .long vector316, vector317, vector318, vector319 + .long vector320, vector321, vector322, vector323 + .long vector324, vector325, vector326, vector327 + .long vector328, vector329, vector330, vector331 + .long vector332, vector333, vector334, vector335 + .long vector336, vector337, vector338, vector339 + .long vector340, vector341, vector342, vector343 + .long vector344, vector345, vector346, vector347 + .long vector348, vector349, vector350, vector351 + .long vector352, vector353, vector354, vector355 + .long vector356, vector357, vector358, vector359 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154, vector155 + .weak vector156, vector157, vector158, vector159 + .weak vector160, vector161, vector162, vector163 + .weak vector164, vector165, vector166, vector167 + .weak vector168, vector169, vector170, vector171 + .weak vector172, vector173, vector174, vector175 + .weak vector176, vector177, vector178, vector179 + .weak vector180, vector181, vector182, vector183 + .weak vector184, vector185, vector186, vector187 + .weak vector188, vector189, vector190, vector191 + .weak vector192, vector193, vector194, vector195 + .weak vector196, vector197, vector198, vector199 + .weak vector200, vector201, vector202, vector203 + .weak vector204, vector205, vector206, vector207 + .weak vector208, vector209, vector210, vector211 + .weak vector212, vector213, vector214, vector215 + .weak vector216, vector217, vector218, vector219 + .weak vector220, vector221, vector222, vector223 + .weak vector224, vector225, vector226, vector227 + .weak vector228, vector229, vector230, vector231 + .weak vector232, vector233, vector234, vector235 + .weak vector236, vector237, vector238, vector239 + .weak vector240, vector241, vector242, vector243 + .weak vector244, vector245, vector246, vector247 + .weak vector248, vector249, vector250, vector251 + .weak vector252, vector253, vector254, vector255 + .weak vector256, vector257, vector258, vector259 + .weak vector260, vector261, vector262, vector263 + .weak vector264, vector265, vector266, vector267 + .weak vector268, vector269, vector270, vector271 + .weak vector272, vector273, vector274, vector275 + .weak vector276, vector277, vector278, vector279 + .weak vector280, vector281, vector282, vector283 + .weak vector284, vector285, vector286, vector287 + .weak vector288, vector289, vector290, vector291 + .weak vector292, vector293, vector294, vector295 + .weak vector296, vector297, vector298, vector299 + .weak vector300, vector301, vector302, vector303 + .weak vector304, vector305, vector306, vector307 + .weak vector308, vector309, vector310, vector311 + .weak vector312, vector313, vector314, vector315 + .weak vector316, vector317, vector318, vector319 + .weak vector320, vector321, vector322, vector323 + .weak vector324, vector325, vector326, vector327 + .weak vector328, vector329, vector330, vector331 + .weak vector332, vector333, vector334, vector335 + .weak vector336, vector337, vector338, vector339 + .weak vector340, vector341, vector342, vector343 + .weak vector344, vector345, vector346, vector347 + .weak vector348, vector349, vector350, vector351 + .weak vector352, vector353, vector354, vector355 + .weak vector356, vector357, vector358, vector359 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: +vector155: +vector156: +vector157: +vector158: +vector159: +vector160: +vector161: +vector162: +vector163: +vector164: +vector165: +vector166: +vector167: +vector168: +vector169: +vector170: +vector171: +vector172: +vector173: +vector174: +vector175: +vector176: +vector177: +vector178: +vector179: +vector180: +vector181: +vector182: +vector183: +vector184: +vector185: +vector186: +vector187: +vector188: +vector189: +vector190: +vector191: +vector192: +vector193: +vector194: +vector195: +vector196: +vector197: +vector198: +vector199: +vector200: +vector201: +vector202: +vector203: +vector204: +vector205: +vector206: +vector207: +vector208: +vector209: +vector210: +vector211: +vector212: +vector213: +vector214: +vector215: +vector216: +vector217: +vector218: +vector219: +vector220: +vector221: +vector222: +vector223: +vector224: +vector225: +vector226: +vector227: +vector228: +vector229: +vector230: +vector231: +vector232: +vector233: +vector234: +vector235: +vector236: +vector237: +vector238: +vector239: +vector240: +vector241: +vector242: +vector243: +vector244: +vector245: +vector246: +vector247: +vector248: +vector249: +vector250: +vector251: +vector252: +vector253: +vector254: +vector255: +vector256: +vector257: +vector258: +vector259: +vector260: +vector261: +vector262: +vector263: +vector264: +vector265: +vector266: +vector267: +vector268: +vector269: +vector270: +vector271: +vector272: +vector273: +vector274: +vector275: +vector276: +vector277: +vector278: +vector279: +vector280: +vector281: +vector282: +vector283: +vector284: +vector285: +vector286: +vector287: +vector288: +vector289: +vector290: +vector291: +vector292: +vector293: +vector294: +vector295: +vector296: +vector297: +vector298: +vector299: +vector300: +vector301: +vector302: +vector303: +vector304: +vector305: +vector306: +vector307: +vector308: +vector309: +vector310: +vector311: +vector312: +vector313: +vector314: +vector315: +vector316: +vector317: +vector318: +vector319: +vector320: +vector321: +vector322: +vector323: +vector324: +vector325: +vector326: +vector327: +vector328: +vector329: +vector330: +vector331: +vector332: +vector333: +vector334: +vector335: +vector336: +vector337: +vector338: +vector339: +vector340: +vector341: +vector342: +vector343: +vector344: +vector345: +vector346: +vector347: +vector348: +vector349: +vector350: +vector351: +vector352: +vector353: +vector354: +vector355: +vector356: +vector357: +vector358: +vector359: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC564Axx/bam.s b/os/ports/GCC/PPC/SPC564Axx/bam.s new file mode 100644 index 000000000..316724abf --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/bam.s @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/bam.s + * @brief SPC564Axx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" +#if PPC_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC564Axx/core.s b/os/ports/GCC/PPC/SPC564Axx/core.s new file mode 100644 index 000000000..bd6ad0fed --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/core.s @@ -0,0 +1,479 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/core.s + * @brief e200z4 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name TLB default settings + * @{ + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) +#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) +#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name LICSR1 default settings + * @{ + */ +#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + /* + * Invalidating all TLBs except TLB1. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB0 allocated to internal RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * *Finally* the TLB1 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, LICSR1_DEFAULT@h + ori %r3, %r3, LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld new file mode 100644 index 000000000..adcb41763 --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC564A70 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 2M + ram : org = 0x40000000, len = 128k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.crt0)) + KEEP(*(.handlers)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld new file mode 100644 index 000000000..ab503114e --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC564A80 memory setup. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 4M + ram : org = 0x40000000, len = 192k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.crt0)) + KEEP(*(.handlers)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC564Axx/port.mk b/os/ports/GCC/PPC/SPC564Axx/port.mk new file mode 100644 index 000000000..81422d7c6 --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC564Axx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/ld diff --git a/os/ports/GCC/PPC/SPC564Axx/ppcparams.h b/os/ports/GCC/PPC/SPC564Axx/ppcparams.h new file mode 100644 index 000000000..4525b168c --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/ppcparams.h @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/ppcparams.h + * @brief PowerPC parameters for the SPC564Axx. + * + * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC564Axx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z4 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC564Axx/vectors.h b/os/ports/GCC/PPC/SPC564Axx/vectors.h new file mode 100644 index 000000000..2e8ab38a1 --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 486 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC564Axx/vectors.s b/os/ports/GCC/PPC/SPC564Axx/vectors.s new file mode 100644 index 000000000..7ac668d35 --- /dev/null +++ b/os/ports/GCC/PPC/SPC564Axx/vectors.s @@ -0,0 +1,782 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/vectors.s + * @brief SPC564Axx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154, vector155 + .long vector156, vector157, vector158, vector159 + .long vector160, vector161, vector162, vector163 + .long vector164, vector165, vector166, vector167 + .long vector168, vector169, vector170, vector171 + .long vector172, vector173, vector174, vector175 + .long vector176, vector177, vector178, vector179 + .long vector180, vector181, vector182, vector183 + .long vector184, vector185, vector186, vector187 + .long vector188, vector189, vector190, vector191 + .long vector192, vector193, vector194, vector195 + .long vector196, vector197, vector198, vector199 + .long vector200, vector201, vector202, vector203 + .long vector204, vector205, vector206, vector207 + .long vector208, vector209, vector210, vector211 + .long vector212, vector213, vector214, vector215 + .long vector216, vector217, vector218, vector219 + .long vector220, vector221, vector222, vector223 + .long vector224, vector225, vector226, vector227 + .long vector228, vector229, vector230, vector231 + .long vector232, vector233, vector234, vector235 + .long vector236, vector237, vector238, vector239 + .long vector240, vector241, vector242, vector243 + .long vector244, vector245, vector246, vector247 + .long vector248, vector249, vector250, vector251 + .long vector252, vector253, vector254, vector255 + .long vector256, vector257, vector258, vector259 + .long vector260, vector261, vector262, vector263 + .long vector264, vector265, vector266, vector267 + .long vector268, vector269, vector270, vector271 + .long vector272, vector273, vector274, vector275 + .long vector276, vector277, vector278, vector279 + .long vector280, vector281, vector282, vector283 + .long vector284, vector285, vector286, vector287 + .long vector288, vector289, vector290, vector291 + .long vector292, vector293, vector294, vector295 + .long vector296, vector297, vector298, vector299 + .long vector300, vector301, vector302, vector303 + .long vector304, vector305, vector306, vector307 + .long vector308, vector309, vector310, vector311 + .long vector312, vector313, vector314, vector315 + .long vector316, vector317, vector318, vector319 + .long vector320, vector321, vector322, vector323 + .long vector324, vector325, vector326, vector327 + .long vector328, vector329, vector330, vector331 + .long vector332, vector333, vector334, vector335 + .long vector336, vector337, vector338, vector339 + .long vector340, vector341, vector342, vector343 + .long vector344, vector345, vector346, vector347 + .long vector348, vector349, vector350, vector351 + .long vector352, vector353, vector354, vector355 + .long vector356, vector357, vector358, vector359 + .long vector360, vector361, vector362, vector363 + .long vector364, vector365, vector366, vector367 + .long vector368, vector369, vector370, vector371 + .long vector372, vector373, vector374, vector375 + .long vector376, vector377, vector378, vector379 + .long vector380, vector381, vector382, vector383 + .long vector384, vector385, vector386, vector387 + .long vector388, vector389, vector390, vector391 + .long vector392, vector393, vector394, vector395 + .long vector396, vector397, vector398, vector399 + .long vector400, vector401, vector402, vector403 + .long vector404, vector405, vector406, vector407 + .long vector408, vector409, vector410, vector411 + .long vector412, vector413, vector414, vector415 + .long vector416, vector417, vector418, vector419 + .long vector420, vector421, vector422, vector423 + .long vector424, vector425, vector426, vector427 + .long vector428, vector429, vector430, vector431 + .long vector432, vector433, vector434, vector435 + .long vector436, vector437, vector438, vector439 + .long vector440, vector441, vector442, vector443 + .long vector444, vector445, vector446, vector447 + .long vector448, vector449, vector450, vector451 + .long vector452, vector453, vector454, vector455 + .long vector456, vector457, vector458, vector459 + .long vector460, vector461, vector462, vector463 + .long vector464, vector465, vector466, vector467 + .long vector468, vector469, vector470, vector471 + .long vector472, vector473, vector474, vector475 + .long vector476, vector477, vector478, vector479 + .long vector480, vector481, vector482, vector483 + .long vector484, vector485 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154, vector155 + .weak vector156, vector157, vector158, vector159 + .weak vector160, vector161, vector162, vector163 + .weak vector164, vector165, vector166, vector167 + .weak vector168, vector169, vector170, vector171 + .weak vector172, vector173, vector174, vector175 + .weak vector176, vector177, vector178, vector179 + .weak vector180, vector181, vector182, vector183 + .weak vector184, vector185, vector186, vector187 + .weak vector188, vector189, vector190, vector191 + .weak vector192, vector193, vector194, vector195 + .weak vector196, vector197, vector198, vector199 + .weak vector200, vector201, vector202, vector203 + .weak vector204, vector205, vector206, vector207 + .weak vector208, vector209, vector210, vector211 + .weak vector212, vector213, vector214, vector215 + .weak vector216, vector217, vector218, vector219 + .weak vector220, vector221, vector222, vector223 + .weak vector224, vector225, vector226, vector227 + .weak vector228, vector229, vector230, vector231 + .weak vector232, vector233, vector234, vector235 + .weak vector236, vector237, vector238, vector239 + .weak vector240, vector241, vector242, vector243 + .weak vector244, vector245, vector246, vector247 + .weak vector248, vector249, vector250, vector251 + .weak vector252, vector253, vector254, vector255 + .weak vector256, vector257, vector258, vector259 + .weak vector260, vector261, vector262, vector263 + .weak vector264, vector265, vector266, vector267 + .weak vector268, vector269, vector270, vector271 + .weak vector272, vector273, vector274, vector275 + .weak vector276, vector277, vector278, vector279 + .weak vector280, vector281, vector282, vector283 + .weak vector284, vector285, vector286, vector287 + .weak vector288, vector289, vector290, vector291 + .weak vector292, vector293, vector294, vector295 + .weak vector296, vector297, vector298, vector299 + .weak vector300, vector301, vector302, vector303 + .weak vector304, vector305, vector306, vector307 + .weak vector308, vector309, vector310, vector311 + .weak vector312, vector313, vector314, vector315 + .weak vector316, vector317, vector318, vector319 + .weak vector320, vector321, vector322, vector323 + .weak vector324, vector325, vector326, vector327 + .weak vector328, vector329, vector330, vector331 + .weak vector332, vector333, vector334, vector335 + .weak vector336, vector337, vector338, vector339 + .weak vector340, vector341, vector342, vector343 + .weak vector344, vector345, vector346, vector347 + .weak vector348, vector349, vector350, vector351 + .weak vector352, vector353, vector354, vector355 + .weak vector356, vector357, vector358, vector359 + .weak vector360, vector361, vector362, vector363 + .weak vector364, vector365, vector366, vector367 + .weak vector368, vector369, vector370, vector371 + .weak vector372, vector373, vector374, vector375 + .weak vector376, vector377, vector378, vector379 + .weak vector380, vector381, vector382, vector383 + .weak vector384, vector385, vector386, vector387 + .weak vector388, vector389, vector390, vector391 + .weak vector392, vector393, vector394, vector395 + .weak vector396, vector397, vector398, vector399 + .weak vector400, vector401, vector402, vector403 + .weak vector404, vector405, vector406, vector407 + .weak vector408, vector409, vector410, vector411 + .weak vector412, vector413, vector414, vector415 + .weak vector416, vector417, vector418, vector419 + .weak vector420, vector421, vector422, vector423 + .weak vector424, vector425, vector426, vector427 + .weak vector428, vector429, vector430, vector431 + .weak vector432, vector433, vector434, vector435 + .weak vector436, vector437, vector438, vector439 + .weak vector440, vector441, vector442, vector443 + .weak vector444, vector445, vector446, vector447 + .weak vector448, vector449, vector450, vector451 + .weak vector452, vector453, vector454, vector455 + .weak vector456, vector457, vector458, vector459 + .weak vector460, vector461, vector462, vector463 + .weak vector464, vector465, vector466, vector467 + .weak vector468, vector469, vector470, vector471 + .weak vector472, vector473, vector474, vector475 + .weak vector476, vector477, vector478, vector479 + .weak vector480, vector481, vector482, vector483 + .weak vector484, vector485 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: +vector155: +vector156: +vector157: +vector158: +vector159: +vector160: +vector161: +vector162: +vector163: +vector164: +vector165: +vector166: +vector167: +vector168: +vector169: +vector170: +vector171: +vector172: +vector173: +vector174: +vector175: +vector176: +vector177: +vector178: +vector179: +vector180: +vector181: +vector182: +vector183: +vector184: +vector185: +vector186: +vector187: +vector188: +vector189: +vector190: +vector191: +vector192: +vector193: +vector194: +vector195: +vector196: +vector197: +vector198: +vector199: +vector200: +vector201: +vector202: +vector203: +vector204: +vector205: +vector206: +vector207: +vector208: +vector209: +vector210: +vector211: +vector212: +vector213: +vector214: +vector215: +vector216: +vector217: +vector218: +vector219: +vector220: +vector221: +vector222: +vector223: +vector224: +vector225: +vector226: +vector227: +vector228: +vector229: +vector230: +vector231: +vector232: +vector233: +vector234: +vector235: +vector236: +vector237: +vector238: +vector239: +vector240: +vector241: +vector242: +vector243: +vector244: +vector245: +vector246: +vector247: +vector248: +vector249: +vector250: +vector251: +vector252: +vector253: +vector254: +vector255: +vector256: +vector257: +vector258: +vector259: +vector260: +vector261: +vector262: +vector263: +vector264: +vector265: +vector266: +vector267: +vector268: +vector269: +vector270: +vector271: +vector272: +vector273: +vector274: +vector275: +vector276: +vector277: +vector278: +vector279: +vector280: +vector281: +vector282: +vector283: +vector284: +vector285: +vector286: +vector287: +vector288: +vector289: +vector290: +vector291: +vector292: +vector293: +vector294: +vector295: +vector296: +vector297: +vector298: +vector299: +vector300: +vector301: +vector302: +vector303: +vector304: +vector305: +vector306: +vector307: +vector308: +vector309: +vector310: +vector311: +vector312: +vector313: +vector314: +vector315: +vector316: +vector317: +vector318: +vector319: +vector320: +vector321: +vector322: +vector323: +vector324: +vector325: +vector326: +vector327: +vector328: +vector329: +vector330: +vector331: +vector332: +vector333: +vector334: +vector335: +vector336: +vector337: +vector338: +vector339: +vector340: +vector341: +vector342: +vector343: +vector344: +vector345: +vector346: +vector347: +vector348: +vector349: +vector350: +vector351: +vector352: +vector353: +vector354: +vector355: +vector356: +vector357: +vector358: +vector359: +vector360: +vector361: +vector362: +vector363: +vector364: +vector365: +vector366: +vector367: +vector368: +vector369: +vector370: +vector371: +vector372: +vector373: +vector374: +vector375: +vector376: +vector377: +vector378: +vector379: +vector380: +vector381: +vector382: +vector383: +vector384: +vector385: +vector386: +vector387: +vector388: +vector389: +vector390: +vector391: +vector392: +vector393: +vector394: +vector395: +vector396: +vector397: +vector398: +vector399: +vector400: +vector401: +vector402: +vector403: +vector404: +vector405: +vector406: +vector407: +vector408: +vector409: +vector410: +vector411: +vector412: +vector413: +vector414: +vector415: +vector416: +vector417: +vector418: +vector419: +vector420: +vector421: +vector422: +vector423: +vector424: +vector425: +vector426: +vector427: +vector428: +vector429: +vector430: +vector431: +vector432: +vector433: +vector434: +vector435: +vector436: +vector437: +vector438: +vector439: +vector440: +vector441: +vector442: +vector443: +vector444: +vector445: +vector446: +vector447: +vector448: +vector449: +vector450: +vector451: +vector452: +vector453: +vector454: +vector455: +vector456: +vector457: +vector458: +vector459: +vector460: +vector461: +vector462: +vector463: +vector464: +vector465: +vector466: +vector467: +vector468: +vector469: +vector470: +vector471: +vector472: +vector473: +vector474: +vector475: +vector476: +vector477: +vector478: +vector479: +vector480: +vector481: +vector482: +vector483: +vector484: +vector485: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/bam.s b/os/ports/GCC/PPC/SPC56ELxx/bam.s new file mode 100644 index 000000000..623428ce3 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/bam.s @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ELxx/bam.s + * @brief SPC56ELxx boot assistant record. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .bam, "ax" +#if PPC_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + + b _boot_address + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s new file mode 100644 index 000000000..0675cd20d --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/core.s @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ELxx/core.s + * @brief e200z4 core configuration. + * + * @addtogroup PPC_CORE + * @{ + */ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name TLB default settings + * @{ + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M) +#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_128K) +#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) +#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) +/** @} */ + +/** + * @name BUCSR default settings + * @{ + */ +#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +/** @} */ + +/** + * @name LICSR1 default settings + * @{ + */ +#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/** + * @name MSR default settings + * @{ + */ +#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +/** @} */ + +#if !defined(__DOXYGEN__) + + .section .coreinit, "ax" + + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 + .globl _coreinit + .type _coreinit, @function +_coreinit: + /* + * Invalidating all TLBs except TLB0. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB1 allocated to internal RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB5 allocated to on-platform peripherals. + */ + lis %r3, TLB5_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB5_MAS1@h + ori %r3, %r3, TLB5_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB5_MAS2@h + ori %r3, %r3, TLB5_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB5_MAS3@h + ori %r3, %r3, TLB5_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Special function registers clearing, required in order to avoid + * possible problems with lockstep mode. + */ + mtcrf 0xFF, %r31 + mtspr 9, %r31 /* CTR */ + mtspr 22, %r31 /* DEC */ + mtspr 26, %r31 /* SRR0-1 */ + mtspr 27, %r31 + mtspr 54, %r31 /* DECAR */ + mtspr 58, %r31 /* CSRR0-1 */ + mtspr 59, %r31 + mtspr 61, %r31 /* DEAR */ + mtspr 256, %r31 /* USPRG0 */ + mtspr 272, %r31 /* SPRG1-7 */ + mtspr 273, %r31 + mtspr 274, %r31 + mtspr 275, %r31 + mtspr 276, %r31 + mtspr 277, %r31 + mtspr 278, %r31 + mtspr 279, %r31 + mtspr 285, %r31 /* TBU */ + mtspr 284, %r31 /* TBL */ +#if 0 + mtspr 318, %r31 /* DVC1-2 */ + mtspr 319, %r31 +#endif + mtspr 562, %r31 /* DBCNT */ + mtspr 570, %r31 /* MCSRR0 */ + mtspr 571, %r31 /* MCSRR1 */ + mtspr 604, %r31 /* SPRG8-9 */ + mtspr 605, %r31 + + /* + * *Finally* the TLB0 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, LICSR1_DEFAULT@h + ori %r3, %r3, LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr + + /* + * Exception vectors initialization. + */ + .global _ivinit + .type _ivinit, @function +_ivinit: + /* MSR initialization.*/ + lis %r3, MSR_DEFAULT@h + ori %r3, %r3, MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld new file mode 100644 index 000000000..592c435f5 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC56EL54 memory setup in LSM mode. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 768k + ram : org = 0x40000000, len = 128k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld new file mode 100644 index 000000000..193c21c05 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC56EL60 memory setup in LSM mode. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 1M + ram : org = 0x40000000, len = 128k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld new file mode 100644 index 000000000..7afb4bf78 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC56EL70 memory setup in LSM mode. + */ +__irq_stack_size__ = 0x0000; /* Not yet used.*/ +__process_stack_size__ = 0x0800; + +MEMORY +{ + flash : org = 0x00000000, len = 2M + ram : org = 0x40000000, len = 192k +} + +ENTRY(_reset_address) + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + .boot : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.coreinit)) + KEEP(*(.handlers)) + KEEP(*(.crt0)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/ports/GCC/PPC/SPC56ELxx/port.mk b/os/ports/GCC/PPC/SPC56ELxx/port.mk new file mode 100644 index 000000000..5a81771db --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT SPC56ELxx port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/bam.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/core.s \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ + ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx + +PORTLD = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/ld diff --git a/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h b/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h new file mode 100644 index 000000000..c09b0b875 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ELxx/ppcparams.h + * @brief PowerPC parameters for the SPC56ELxx. + * + * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC56ELxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z4 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/vectors.h b/os/ports/GCC/PPC/SPC56ELxx/vectors.h new file mode 100644 index 000000000..628b075b5 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/vectors.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ELxx/vectors.h + * @brief ISR vector module header. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @brief Number of ISR vectors available. + */ +#define VECTORS_NUMBER 256 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +#if !defined(__DOXYGEN__) +extern uint32_t _vectors[VECTORS_NUMBER]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _unhandled_irq(void); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _OSAL_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/vectors.s b/os/ports/GCC/PPC/SPC56ELxx/vectors.s new file mode 100644 index 000000000..22a35f1d5 --- /dev/null +++ b/os/ports/GCC/PPC/SPC56ELxx/vectors.s @@ -0,0 +1,436 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ELxx/vectors.s + * @brief SPC56ELxx vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + /* Software vectors table. The vectors are accessed from the IVOR4 + handler only. In order to declare an interrupt handler just create + a function withe the same name of a vector, the symbol will + override the weak symbol declared here.*/ + .section .vectors, "ax" + .align 4 + .globl _vectors +_vectors: + .long vector0, vector1, vector2, vector3 + .long vector4, vector5, vector6, vector7 + .long vector8, vector9, vector10, vector11 + .long vector12, vector13, vector14, vector15 + .long vector16, vector17, vector18, vector19 + .long vector20, vector21, vector22, vector23 + .long vector24, vector25, vector26, vector27 + .long vector28, vector29, vector30, vector31 + .long vector32, vector33, vector34, vector35 + .long vector36, vector37, vector38, vector39 + .long vector40, vector41, vector42, vector43 + .long vector44, vector45, vector46, vector47 + .long vector48, vector49, vector50, vector51 + .long vector52, vector53, vector54, vector55 + .long vector56, vector57, vector58, vector59 + .long vector60, vector61, vector62, vector63 + .long vector64, vector65, vector66, vector67 + .long vector68, vector69, vector70, vector71 + .long vector72, vector73, vector74, vector75 + .long vector76, vector77, vector78, vector79 + .long vector80, vector81, vector82, vector83 + .long vector84, vector85, vector86, vector87 + .long vector88, vector89, vector90, vector91 + .long vector92, vector93, vector94, vector95 + .long vector96, vector97, vector98, vector99 + .long vector100, vector101, vector102, vector103 + .long vector104, vector105, vector106, vector107 + .long vector108, vector109, vector110, vector111 + .long vector112, vector113, vector114, vector115 + .long vector116, vector117, vector118, vector119 + .long vector120, vector121, vector122, vector123 + .long vector124, vector125, vector126, vector127 + .long vector128, vector129, vector130, vector131 + .long vector132, vector133, vector134, vector135 + .long vector136, vector137, vector138, vector139 + .long vector140, vector141, vector142, vector143 + .long vector144, vector145, vector146, vector147 + .long vector148, vector149, vector150, vector151 + .long vector152, vector153, vector154, vector155 + .long vector156, vector157, vector158, vector159 + .long vector160, vector161, vector162, vector163 + .long vector164, vector165, vector166, vector167 + .long vector168, vector169, vector170, vector171 + .long vector172, vector173, vector174, vector175 + .long vector176, vector177, vector178, vector179 + .long vector180, vector181, vector182, vector183 + .long vector184, vector185, vector186, vector187 + .long vector188, vector189, vector190, vector191 + .long vector192, vector193, vector194, vector195 + .long vector196, vector197, vector198, vector199 + .long vector200, vector201, vector202, vector203 + .long vector204, vector205, vector206, vector207 + .long vector208, vector209, vector210, vector211 + .long vector212, vector213, vector214, vector215 + .long vector216, vector217, vector218, vector219 + .long vector220, vector221, vector222, vector223 + .long vector224, vector225, vector226, vector227 + .long vector228, vector229, vector230, vector231 + .long vector232, vector233, vector234, vector235 + .long vector236, vector237, vector238, vector239 + .long vector240, vector241, vector242, vector243 + .long vector244, vector245, vector246, vector247 + .long vector248, vector249, vector250, vector251 + .long vector252, vector253, vector254, vector255 + + .text + .align 2 + + .weak vector0, vector1, vector2, vector3 + .weak vector4, vector5, vector6, vector7 + .weak vector8, vector9, vector10, vector11 + .weak vector12, vector13, vector14, vector15 + .weak vector16, vector17, vector18, vector19 + .weak vector20, vector21, vector22, vector23 + .weak vector24, vector25, vector26, vector27 + .weak vector28, vector29, vector30, vector31 + .weak vector32, vector33, vector34, vector35 + .weak vector36, vector37, vector38, vector39 + .weak vector40, vector41, vector42, vector43 + .weak vector44, vector45, vector46, vector47 + .weak vector48, vector49, vector50, vector51 + .weak vector52, vector53, vector54, vector55 + .weak vector56, vector57, vector58, vector59 + .weak vector60, vector61, vector62, vector63 + .weak vector64, vector65, vector66, vector67 + .weak vector68, vector69, vector70, vector71 + .weak vector72, vector73, vector74, vector75 + .weak vector76, vector77, vector78, vector79 + .weak vector80, vector81, vector82, vector83 + .weak vector84, vector85, vector86, vector87 + .weak vector88, vector89, vector90, vector91 + .weak vector92, vector93, vector94, vector95 + .weak vector96, vector97, vector98, vector99 + .weak vector100, vector101, vector102, vector103 + .weak vector104, vector105, vector106, vector107 + .weak vector108, vector109, vector110, vector111 + .weak vector112, vector113, vector114, vector115 + .weak vector116, vector117, vector118, vector119 + .weak vector120, vector121, vector122, vector123 + .weak vector124, vector125, vector126, vector127 + .weak vector128, vector129, vector130, vector131 + .weak vector132, vector133, vector134, vector135 + .weak vector136, vector137, vector138, vector139 + .weak vector140, vector141, vector142, vector143 + .weak vector144, vector145, vector146, vector147 + .weak vector148, vector149, vector150, vector151 + .weak vector152, vector153, vector154, vector155 + .weak vector156, vector157, vector158, vector159 + .weak vector160, vector161, vector162, vector163 + .weak vector164, vector165, vector166, vector167 + .weak vector168, vector169, vector170, vector171 + .weak vector172, vector173, vector174, vector175 + .weak vector176, vector177, vector178, vector179 + .weak vector180, vector181, vector182, vector183 + .weak vector184, vector185, vector186, vector187 + .weak vector188, vector189, vector190, vector191 + .weak vector192, vector193, vector194, vector195 + .weak vector196, vector197, vector198, vector199 + .weak vector200, vector201, vector202, vector203 + .weak vector204, vector205, vector206, vector207 + .weak vector208, vector209, vector210, vector211 + .weak vector212, vector213, vector214, vector215 + .weak vector216, vector217, vector218, vector219 + .weak vector220, vector221, vector222, vector223 + .weak vector224, vector225, vector226, vector227 + .weak vector228, vector229, vector230, vector231 + .weak vector232, vector233, vector234, vector235 + .weak vector236, vector237, vector238, vector239 + .weak vector240, vector241, vector242, vector243 + .weak vector244, vector245, vector246, vector247 + .weak vector248, vector249, vector250, vector251 + .weak vector252, vector253, vector254, vector255 + +vector0: +vector1: +vector2: +vector3: +vector4: +vector5: +vector6: +vector7: +vector8: +vector9: +vector10: +vector11: +vector12: +vector13: +vector14: +vector15: +vector16: +vector17: +vector18: +vector19: +vector20: +vector21: +vector22: +vector23: +vector24: +vector25: +vector26: +vector27: +vector28: +vector29: +vector30: +vector31: +vector32: +vector33: +vector34: +vector35: +vector36: +vector37: +vector38: +vector39: +vector40: +vector41: +vector42: +vector43: +vector44: +vector45: +vector46: +vector47: +vector48: +vector49: +vector50: +vector51: +vector52: +vector53: +vector54: +vector55: +vector56: +vector57: +vector58: +vector59: +vector60: +vector61: +vector62: +vector63: +vector64: +vector65: +vector66: +vector67: +vector68: +vector69: +vector70: +vector71: +vector72: +vector73: +vector74: +vector75: +vector76: +vector77: +vector78: +vector79: +vector80: +vector81: +vector82: +vector83: +vector84: +vector85: +vector86: +vector87: +vector88: +vector89: +vector90: +vector91: +vector92: +vector93: +vector94: +vector95: +vector96: +vector97: +vector98: +vector99: +vector100: +vector101: +vector102: +vector103: +vector104: +vector105: +vector106: +vector107: +vector108: +vector109: +vector110: +vector111: +vector112: +vector113: +vector114: +vector115: +vector116: +vector117: +vector118: +vector119: +vector120: +vector121: +vector122: +vector123: +vector124: +vector125: +vector126: +vector127: +vector128: +vector129: +vector130: +vector131: +vector132: +vector133: +vector134: +vector135: +vector136: +vector137: +vector138: +vector139: +vector140: +vector141: +vector142: +vector143: +vector144: +vector145: +vector146: +vector147: +vector148: +vector149: +vector150: +vector151: +vector152: +vector153: +vector154: +vector155: +vector156: +vector157: +vector158: +vector159: +vector160: +vector161: +vector162: +vector163: +vector164: +vector165: +vector166: +vector167: +vector168: +vector169: +vector170: +vector171: +vector172: +vector173: +vector174: +vector175: +vector176: +vector177: +vector178: +vector179: +vector180: +vector181: +vector182: +vector183: +vector184: +vector185: +vector186: +vector187: +vector188: +vector189: +vector190: +vector191: +vector192: +vector193: +vector194: +vector195: +vector196: +vector197: +vector198: +vector199: +vector200: +vector201: +vector202: +vector203: +vector204: +vector205: +vector206: +vector207: +vector208: +vector209: +vector210: +vector211: +vector212: +vector213: +vector214: +vector215: +vector216: +vector217: +vector218: +vector219: +vector220: +vector221: +vector222: +vector223: +vector224: +vector225: +vector226: +vector227: +vector228: +vector229: +vector230: +vector231: +vector232: +vector233: +vector234: +vector235: +vector236: +vector237: +vector238: +vector239: +vector240: +vector241: +vector242: +vector243: +vector244: +vector245: +vector246: +vector247: +vector248: +vector249: +vector250: +vector251: +vector252: +vector253: +vector254: +vector255: + + .weak _unhandled_irq + .type _unhandled_irq, @function +_unhandled_irq: + b _unhandled_irq + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/chcore.c b/os/ports/GCC/PPC/chcore.c new file mode 100644 index 000000000..4644376cf --- /dev/null +++ b/os/ports/GCC/PPC/chcore.c @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file PPC/chcore.c + * @brief PowerPC architecture port code. + * + * @addtogroup PPC_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Kernel port layer initialization. + * @details IVOR4 and IVOR10 initialization. + */ +void port_init(void) { +#if PPC_SUPPORTS_IVORS + /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10 + and the initialization is performed here.*/ + asm volatile ("li %%r3, _IVOR4@l \t\n" + "mtIVOR4 %%r3 \t\n" + "li %%r3, _IVOR10@l \t\n" + "mtIVOR10 %%r3" : : : "memory"); +#endif +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while + * in debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void port_dummy1(void) { + + asm (".global _port_switch"); + asm ("_port_switch:"); + asm ("subi %sp, %sp, 80"); /* Size of the intctx structure. */ + asm ("mflr %r0"); + asm ("stw %r0, 84(%sp)"); /* LR into the caller frame. */ + asm ("mfcr %r0"); + asm ("stw %r0, 0(%sp)"); /* CR. */ + asm ("stmw %r14, 4(%sp)"); /* GPR14...GPR31. */ + + asm ("stw %sp, 12(%r4)"); /* Store swapped-out stack. */ + asm ("lwz %sp, 12(%r3)"); /* Load swapped-in stack. */ + + asm ("lmw %r14, 4(%sp)"); /* GPR14...GPR31. */ + asm ("lwz %r0, 0(%sp)"); /* CR. */ + asm ("mtcr %r0"); + asm ("lwz %r0, 84(%sp)"); /* LR from the caller frame. */ + asm ("mtlr %r0"); + asm ("addi %sp, %sp, 80"); /* Size of the intctx structure. */ + asm ("blr"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void port_dummy2(void) { + + asm (".global _port_thread_start"); + asm ("_port_thread_start:"); + chSysUnlock(); + asm ("mr %r3, %r31"); /* Thread parameter. */ + asm ("mtctr %r30"); + asm ("bctrl"); /* Invoke thread function. */ + asm ("bl chThdExit"); /* Thread termination on exit. */ +} + +/** @} */ diff --git a/os/ports/GCC/PPC/chcore.h b/os/ports/GCC/PPC/chcore.h new file mode 100644 index 000000000..b689026e5 --- /dev/null +++ b/os/ports/GCC/PPC/chcore.h @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file PPC/chcore.h + * @brief PowerPC architecture port macros and structures. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +/** + * @name Supported core variants + * @{ + */ +#define PPC_VARIANT_e200z0 200 +#define PPC_VARIANT_e200z3 203 +#define PPC_VARIANT_e200z4 204 +/** @} */ + +#include "vectors.h" +#include "ppcparams.h" + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/** + * @brief Use VLE instruction set. + * @note This parameter is usually set in the Makefile. + */ +#if !defined(PPC_USE_VLE) +#define PPC_USE_VLE TRUE +#endif + +/** + * @brief Enables the use of the @p WFI instruction. + */ +#if !defined(PPC_ENABLE_WFI_IDLE) +#define PPC_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +#if PPC_USE_VLE && !PPC_SUPPORTS_VLE +#error "the selected MCU does not support VLE instructions set" +#endif + +#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE +#error "the selected MCU does not support BookE instructions set" +#endif + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_PPC + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "Power Architecture" + +/** + * @brief Name of the architecture variant. + */ +#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "e200z0" +#elif PPC_VARIANT == PPC_VARIANT_e200z3 +#define CH_CORE_VARIANT_NAME "e200z3" +#elif PPC_VARIANT == PPC_VARIANT_e200z4 +#define CH_CORE_VARIANT_NAME "e200z4" +#else +#error "unknown or unsupported PowerPC variant specified" +#endif + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#if PPC_USE_VLE +#define CH_PORT_INFO "VLE mode" +#else +#define CH_PORT_INFO "Book-E mode" +#endif + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Base type for stack and memory alignment. + */ +typedef struct { + uint8_t a[8]; +} stkalign_t __attribute__((aligned(8))); + +/** + * @brief Generic PPC register. + */ +typedef void *regppc_t; + +/** + * @brief Mandatory part of a stack frame. + */ +struct eabi_frame { + regppc_t slink; /**< Stack back link. */ + regppc_t shole; /**< Stack hole for LR storage. */ +}; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note R2 and R13 are not saved because those are assumed to be immutable + * during the system life cycle. + */ +struct extctx { + struct eabi_frame frame; + /* Start of the e_stmvsrrw frame (offset 8).*/ + regppc_t pc; + regppc_t msr; + /* Start of the e_stmvsprw frame (offset 16).*/ + regppc_t cr; + regppc_t lr; + regppc_t ctr; + regppc_t xer; + /* Start of the e_stmvgprw frame (offset 32).*/ + regppc_t r0; + regppc_t r3; + regppc_t r4; + regppc_t r5; + regppc_t r6; + regppc_t r7; + regppc_t r8; + regppc_t r9; + regppc_t r10; + regppc_t r11; + regppc_t r12; + regppc_t padding; + }; + + /** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + * @note R2 and R13 are not saved because those are assumed to be immutable + * during the system life cycle. + * @note LR is stored in the caller contex so it is not present in this + * structure. + */ +struct intctx { + regppc_t cr; /* Part of it is not volatile... */ + regppc_t r14; + regppc_t r15; + regppc_t r16; + regppc_t r17; + regppc_t r18; + regppc_t r19; + regppc_t r20; + regppc_t r21; + regppc_t r22; + regppc_t r23; + regppc_t r24; + regppc_t r25; + regppc_t r26; + regppc_t r27; + regppc_t r28; + regppc_t r29; + regppc_t r30; + regppc_t r31; + regppc_t padding; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame); \ + ((struct eabi_frame *)sp)->slink = 0; \ + ((struct eabi_frame *)sp)->shole = _port_thread_start; \ + tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx)); \ + tp->p_ctx.sp->r31 = arg; \ + tp->p_ctx.sp->r30 = pf; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 32 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 256 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @details Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile("wrteei 1" : : : "memory") + +/** + * @details Implemented as global interrupt disable. + */ +#define port_lock_from_isr() /*asm ("wrteei 0")*/ + +/** + * @details Implemented as global interrupt enable. + */ +#define port_unlock_from_isr() /*asm ("wrteei 1")*/ + +/** + * @details Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("wrteei 1" : : : "memory") + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + register struct intctx *sp asm ("%r1"); \ + if ((stkalign_t *)(sp - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +/** + * @brief Writes to a special register. + * + * @param[in] spr special register number + * @param[in] val value to be written + */ +#define port_mtspr(spr, val) \ + asm volatile ("mtspr %0,%1" : : "n" (spr), "r" (val)) + +/** + * @details This port function is implemented as inlined code for performance + * reasons. + */ +#if PPC_ENABLE_WFI_IDLE +#if !defined(port_wait_for_interrupt) +#define port_wait_for_interrupt() { \ + asm volatile ("wait" : : : "memory"); \ +} +#endif +#else +#define port_wait_for_interrupt() +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void port_halt(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/chtypes.h b/os/ports/GCC/PPC/chtypes.h new file mode 100644 index 000000000..37f4419f6 --- /dev/null +++ b/os/ports/GCC/PPC/chtypes.h @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file PPC/chtypes.h + * @brief PowerPC architecture port system types. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +/* + * Derived generic types. + */ +typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */ +typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */ +typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */ +typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */ +typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */ +typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */ + +/* + * Kernel types. + */ +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter.*/ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/PPC/crt0.s b/os/ports/GCC/PPC/crt0.s new file mode 100644 index 000000000..07e870451 --- /dev/null +++ b/os/ports/GCC/PPC/crt0.s @@ -0,0 +1,126 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file PPC/crt0.s + * @brief Generic PowerPC startup file for ChibiOS/RT. + * + * @addtogroup PPC_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + .section .crt0, "ax" + .align 2 + .globl _boot_address + .type _boot_address, @function +_boot_address: + /* + * Stack setup. + */ + lis %r1, __process_stack_end__@h + ori %r1, %r1, __process_stack_end__@l + li %r0, 0 + stwu %r0, -8(%r1) + /* + * Small sections registers initialization. + */ + lis %r2, __sdata2_start__@h + ori %r2, %r2, __sdata2_start__@l + lis %r13, __sdata_start__@h + ori %r13, %r13, __sdata_start__@l + /* + * Early initialization. + */ + bl __early_init + /* + * BSS clearing. + */ + lis %r4, __bss_start__@h + ori %r4, %r4, __bss_start__@l + lis %r5, __bss_end__@h + ori %r5, %r5, __bss_end__@l + li %r7, 0 +.bssloop: + cmpl cr0, %r4, %r5 + bge cr0, .bssend + stw %r7, 0(%r4) + addi %r4, %r4, 4 + b .bssloop +.bssend: + /* + * DATA initialization. + */ + lis %r4, __romdata_start__@h + ori %r4, %r4, __romdata_start__@l + lis %r5, __data_start__@h + ori %r5, %r5, __data_start__@l + lis %r6, __data_end__@h + ori %r6, %r6, __data_end__@l +.dataloop: + cmpl cr0, %r5, %r6 + bge cr0, .dataend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .dataloop +.dataend: + /* + * Late initialization. + */ + bl __late_init + /* + * Main program invocation. + */ + bl main + b _main_exit_handler + + /* + * Default main exit code, infinite loop. + */ + .weak _main_exit_handler + .globl _main_exit_handler + .type _main_exit_handler, @function +_main_exit_handler: + b _main_exit_handler + + /* + * Default early initialization code, none. + */ + .weak __early_init + .globl __early_init + .type __early_init, @function +__early_init: + blr + + /* + * Default late initialization code, none. + */ + .weak __late_init + .globl __late_init + .type __late_init, @function +__late_init: + blr + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/ivor.s b/os/ports/GCC/PPC/ivor.s new file mode 100644 index 000000000..46dc66bf5 --- /dev/null +++ b/os/ports/GCC/PPC/ivor.s @@ -0,0 +1,224 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file PPC/ivor.s + * @brief Kernel ISRs. + * + * @addtogroup PPC_CORE + * @{ + */ + +/* + * Imports the PPC configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + /* + * INTC registers address. + */ + .equ INTC_IACKR, 0xfff48010 + .equ INTC_EOIR, 0xfff48018 + + .section .handlers, "ax" + +#if PPC_SUPPORTS_DECREMENTER + /* + * _IVOR10 handler (Book-E decrementer). + */ + .align 4 + .globl _IVOR10 + .type _IVOR10, @function +_IVOR10: + /* Creation of the external stack frame (extctx structure).*/ + stwu %sp, -80(%sp) /* Size of the extctx structure.*/ +#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI + e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ + e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ + e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ +#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + stw %r0, 32(%sp) /* Saves GPR0. */ + mfSRR0 %r0 + stw %r0, 8(%sp) /* Saves PC. */ + mfSRR1 %r0 + stw %r0, 12(%sp) /* Saves MSR. */ + mfCR %r0 + stw %r0, 16(%sp) /* Saves CR. */ + mfLR %r0 + stw %r0, 20(%sp) /* Saves LR. */ + mfCTR %r0 + stw %r0, 24(%sp) /* Saves CTR. */ + mfXER %r0 + stw %r0, 28(%sp) /* Saves XER. */ + stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ + stw %r4, 40(%sp) + stw %r5, 44(%sp) + stw %r6, 48(%sp) + stw %r7, 52(%sp) + stw %r8, 56(%sp) + stw %r9, 60(%sp) + stw %r10, 64(%sp) + stw %r11, 68(%sp) + stw %r12, 72(%sp) +#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + + /* Reset DIE bit in TSR register.*/ + lis %r3, 0x0800 /* DIS bit mask. */ + mtspr 336, %r3 /* TSR register. */ + +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_enter_isr + bl dbg_check_lock_from_isr +#endif + bl chSysTimerHandlerI +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock_from_isr + bl dbg_check_leave_isr +#endif + + /* System tick handler invocation.*/ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchIsPreemptionRequired + cmpli cr0, %r3, 0 + beq cr0, _ivor_exit + bl chSchDoReschedule + b _ivor_exit +#endif /* PPC_SUPPORTS_DECREMENTER */ + + /* + * _IVOR4 handler (Book-E external interrupt). + */ + .align 4 + .globl _IVOR4 + .type _IVOR4, @function +_IVOR4: + /* Creation of the external stack frame (extctx structure).*/ + stwu %sp, -80(%sp) /* Size of the extctx structure.*/ +#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI + e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ + e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ + e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ +#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + stw %r0, 32(%sp) /* Saves GPR0. */ + mfSRR0 %r0 + stw %r0, 8(%sp) /* Saves PC. */ + mfSRR1 %r0 + stw %r0, 12(%sp) /* Saves MSR. */ + mfCR %r0 + stw %r0, 16(%sp) /* Saves CR. */ + mfLR %r0 + stw %r0, 20(%sp) /* Saves LR. */ + mfCTR %r0 + stw %r0, 24(%sp) /* Saves CTR. */ + mfXER %r0 + stw %r0, 28(%sp) /* Saves XER. */ + stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ + stw %r4, 40(%sp) + stw %r5, 44(%sp) + stw %r6, 48(%sp) + stw %r7, 52(%sp) + stw %r8, 56(%sp) + stw %r9, 60(%sp) + stw %r10, 64(%sp) + stw %r11, 68(%sp) + stw %r12, 72(%sp) +#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + + /* Software vector address from the INTC register.*/ + lis %r3, INTC_IACKR@h + ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */ + lwz %r3, 0(%r3) /* IACKR register value. */ + lwz %r3, 0(%r3) + mtCTR %r3 /* Software handler address. */ + +#if PPC_USE_IRQ_PREEMPTION + /* Allows preemption while executing the software handler.*/ + wrteei 1 +#endif + + /* Exectes the software handler.*/ + bctrl + +#if PPC_USE_IRQ_PREEMPTION + /* Prevents preemption again.*/ + wrteei 0 +#endif + + /* Informs the INTC that the interrupt has been served.*/ + mbar 0 + lis %r3, INTC_EOIR@h + ori %r3, %r3, INTC_EOIR@l + stw %r3, 0(%r3) /* Writing any value should do. */ + + /* Verifies if a reschedule is required.*/ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchIsPreemptionRequired + cmpli cr0, %r3, 0 + beq cr0, _ivor_exit + bl chSchDoReschedule + + /* Context restore.*/ + .globl _ivor_exit +_ivor_exit: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI + e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */ + e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */ + e_lmvsrrw 8(%sp) /* Restores PC, MSR. */ +#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ + lwz %r4, 40(%sp) + lwz %r5, 44(%sp) + lwz %r6, 48(%sp) + lwz %r7, 52(%sp) + lwz %r8, 56(%sp) + lwz %r9, 60(%sp) + lwz %r10, 64(%sp) + lwz %r11, 68(%sp) + lwz %r12, 72(%sp) + lwz %r0, 8(%sp) + mtSRR0 %r0 /* Restores PC. */ + lwz %r0, 12(%sp) + mtSRR1 %r0 /* Restores MSR. */ + lwz %r0, 16(%sp) + mtCR %r0 /* Restores CR. */ + lwz %r0, 20(%sp) + mtLR %r0 /* Restores LR. */ + lwz %r0, 24(%sp) + mtCTR %r0 /* Restores CTR. */ + lwz %r0, 28(%sp) + mtXER %r0 /* Restores XER. */ + lwz %r0, 32(%sp) /* Restores GPR0. */ +#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ + addi %sp, %sp, 80 /* Back to the previous frame. */ + rfi + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/ports/GCC/PPC/port.dox b/os/ports/GCC/PPC/port.dox new file mode 100644 index 000000000..9ea2c0449 --- /dev/null +++ b/os/ports/GCC/PPC/port.dox @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup PPC Power Architecture + * @details Power Architecture port for the GCC compiler. + * + * @section PPC_INTRO Introduction + * This port supports cores implementing a 32 bits Power Architecture. + * + * @section PPC_STATES Mapping of the System States in the Power Architecture port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * PowerPC port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wait. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The PowerPC has several non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section PPC_NOTES The PowerPC port notes + * The PowerPC port is organized as follow: + * - The @p main() function is invoked in privileged mode. + * - Each thread has a private stack with extra storage for interrupts + * servicing. + * - The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick. + * - Interrupt nesting is not currently supported. + * . + * @ingroup gcc + */ + +/** + * @defgroup PPC_CONF Configuration Options + * @details PowerPC Configuration Options. The PowerPC port allows some + * architecture-specific configurations settings that can be overridden by + * redefining them in @p chconf.h. Usually there is no need to change the + * default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * The default for this value is @p 128 bytes, this space is allocated for + * each thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * - @p ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the @p wait + * instruction from within the idle loop. This is defaulted to 0 because + * it can create problems with some debuggers. Setting this option to 1 + * reduces the system power requirements. + * . + * @ingroup PPC + */ + +/** + * @defgroup PPC_CORE Core Port Implementation + * @brief PowerPC specific port code, structures and macros. + * + * @ingroup PPC + */ + +/** + * @defgroup PPC_STARTUP Startup Support + * @brief + * @details PPC startup code support. ChibiOS/RT provides its own generic + * startup file for the PowerPC port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section PPC_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# The stacks pointer is initialized into the area defined in the linker + * script. + * -# The IVPR register is setup according to the linker script. + * -# The R2 and R13 registers are set to pointer to the SDA areas according + * to the EABI specification. + * -# An early initialization routine @p hwinit0 is invoked, if the symbol is + * not defined then an empty default routine is executed (weak symbol). + * -# DATA and BSS segments are initialized. + * -# A late initialization routine @p hwinit1 is invoked, if the symbol not + * defined then an empty default routine is executed (weak symbol).
    + * This late initialization function is also the proper place for a + * @a bootloader, if your application requires one. + * -# The @p main() function is invoked with the parameters @p argc and @p argv + * set to zero. + * -# Should the @p main() function return a branch is performed to the weak + * symbol @p _main_exit_handler. The default code is an endless empty loop. + * . + * @section PPC_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p _boot_address and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__ RAM end location +1. + * - @p __sdata2_start__ small constants data area + * - @p __sdata_start__ small variables data area + * - @p __romdata_start__ address of the data segment source read only data. + * - @p __data_start__ data segment start location. + * - @p __data_end__ data segment end location +1. + * - @p __bss_start__ BSS start location. + * - @p __bss_end__ BSS end location +1. + * - @p __ivpr_base__ IVPR register initialization address. + * . + * @ingroup PPC + */ + +/** + * @defgroup PPC_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup PPC + */ diff --git a/os/ports/GCC/PPC/rules.mk b/os/ports/GCC/PPC/rules.mk new file mode 100644 index 000000000..4b765c5b7 --- /dev/null +++ b/os/ports/GCC/PPC/rules.mk @@ -0,0 +1,182 @@ +# PPC makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# VLE option handling. +ifeq ($(USE_VLE),yes) + DDEFS += -DPPC_USE_VLE=1 + DADEFS += -DPPC_USE_VLE=1 + MCU += -mvle +else + DDEFS += -DPPC_USE_VLE=0 + DADEFS += -DPPC_USE_VLE=0 +endif + +# Source files groups and paths +SRC = $(CSRC)$(CPPSRC) +SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o))) +CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) +GCLDFLAGS = ,--gc-sections +else +GCLDFLAGS = +endif +ifneq ($(USE_LDOPT),) +XLDFLAGS =,$(USE_LDOPT) +else +XLDFLAGS = +endif +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch$(GCLDFLAGS)$(XLDFLAGS) $(LLIBDIR) + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/os/ports/GCC/SIMIA32/chcore.c b/os/ports/GCC/SIMIA32/chcore.c new file mode 100644 index 000000000..c8f0f36f4 --- /dev/null +++ b/os/ports/GCC/SIMIA32/chcore.c @@ -0,0 +1,86 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup SIMIA32_CORE + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +/** + * Performs a context switch between two threads. + * @param otp the thread to be switched out + * @param ntp the thread to be switched in + */ +__attribute__((used)) +static void __dummy(Thread *ntp, Thread *otp) { + (void)ntp; (void)otp; + + asm volatile ( +#if defined(WIN32) + ".globl @port_switch@8 \n\t" + "@port_switch@8:" +#elif defined(__APPLE__) + ".globl _port_switch \n\t" + "_port_switch:" +#else + ".globl port_switch \n\t" + "port_switch:" +#endif + "push %ebp \n\t" + "push %esi \n\t" + "push %edi \n\t" + "push %ebx \n\t" + "movl %esp, 12(%edx) \n\t" + "movl 12(%ecx), %esp \n\t" + "pop %ebx \n\t" + "pop %edi \n\t" + "pop %esi \n\t" + "pop %ebp \n\t" + "ret"); +} + +/** + * Halts the system. In this implementation it just exits the simulation. + */ +__attribute__((fastcall)) +void port_halt(void) { + + exit(2); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +__attribute__((cdecl, noreturn)) +void _port_thread_start(msg_t (*pf)(void *), void *p) { + + chSysUnlock(); + chThdExit(pf(p)); + while(1); +} + +/** @} */ diff --git a/os/ports/GCC/SIMIA32/chcore.h b/os/ports/GCC/SIMIA32/chcore.h new file mode 100644 index 000000000..5161688da --- /dev/null +++ b/os/ports/GCC/SIMIA32/chcore.h @@ -0,0 +1,243 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup SIMIA32_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * Macro defining the a simulated architecture into x86. + */ +#define CH_ARCHITECTURE_SIMIA32 + +/** + * Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "Simulator" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "x86 (integer only)" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "No preemption" + +/** + * 16 bytes stack alignment. + */ +typedef struct { + uint8_t a[16]; +} stkalign_t __attribute__((aligned(16))); + +/** + * Generic x86 register. + */ +typedef void *regx86; + +/** + * Interrupt saved context. + * This structure represents the stack frame saved during a preemption-capable + * interrupt handler. + */ +struct extctx { +}; + +/** + * System saved context. + * @note In this demo the floating point registers are not saved. + */ +struct intctx { + regx86 ebx; + regx86 edi; + regx86 esi; + regx86 ebp; + regx86 eip; +}; + +/** + * Platform dependent part of the @p Thread structure. + * This structure usually contains just the saved stack pointer defined as a + * pointer to a @p intctx structure. + */ +struct context { + struct intctx volatile *esp; +}; + +#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) + +/* Darwin requires the stack to be aligned to a 16-byte boundary at + * the time of a call instruction (in case the called function needs + * to save MMX registers). This aligns to 'mod' module 16, so that we'll end + * up with the right alignment after pushing the args. */ +#define AALIGN(p, mask, mod) p = (void *)((((uintptr_t)(p) - mod) & ~mask) + mod) + +/** + * Platform dependent part of the @p chThdCreateI() API. + * This code usually setup the context switching frame represented by a + * @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + uint8_t *esp = (uint8_t *)workspace + wsize; \ + APUSH(esp, 0); \ + uint8_t *savebp = esp; \ + AALIGN(esp, 15, 8); \ + APUSH(esp, arg); \ + APUSH(esp, pf); \ + APUSH(esp, 0); \ + esp -= sizeof(struct intctx); \ + ((struct intctx *)esp)->eip = _port_thread_start; \ + ((struct intctx *)esp)->ebx = 0; \ + ((struct intctx *)esp)->edi = 0; \ + ((struct intctx *)esp)->esi = 0; \ + ((struct intctx *)esp)->ebp = savebp; \ + tp->p_ctx.esp = (struct intctx *)esp; \ +} + +/** + * Stack size for the system idle thread. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 256 +#endif + +/** + * Per-thread stack overhead for interrupts servicing, it is used in the + * calculation of the correct working area size. + * It requires stack space because the simulated "interrupt handlers" can + * invoke host library functions inside so it better have a lot of space. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 16384 +#endif + +/** + * Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + + /** + * Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(void *) * 4 + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * Macro used to allocate a thread working area aligned as both position and + * size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * IRQ prologue code, inserted at the start of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * IRQ handler function declaration. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * Simulator initialization. + */ +#define port_init() + +/** + * Does nothing in this simulator. + */ +#define port_lock() asm volatile("nop") + +/** + * Does nothing in this simulator. + */ +#define port_unlock() asm volatile("nop") + +/** + * Does nothing in this simulator. + */ +#define port_lock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_unlock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_disable() + +/** + * Does nothing in this simulator. + */ +#define port_suspend() + +/** + * Does nothing in this simulator. + */ +#define port_enable() + +/** + * In the simulator this does a polling pass on the simulated interrupt + * sources. + */ +#define port_wait_for_interrupt() ChkIntSources() + +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((fastcall)) void port_switch(Thread *ntp, Thread *otp); + __attribute__((fastcall)) void port_halt(void); + __attribute__((cdecl, noreturn)) void _port_thread_start(msg_t (*pf)(void *), + void *p); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/SIMIA32/chtypes.h b/os/ports/GCC/SIMIA32/chtypes.h new file mode 100644 index 000000000..b10eed325 --- /dev/null +++ b/os/ports/GCC/SIMIA32/chtypes.h @@ -0,0 +1,70 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ diff --git a/os/ports/GCC/SIMIA32/port.mk b/os/ports/GCC/SIMIA32/port.mk new file mode 100644 index 000000000..8f053abc4 --- /dev/null +++ b/os/ports/GCC/SIMIA32/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT SIMIA32 port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/SIMIA32/chcore.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/GCC/SIMIA32 diff --git a/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 000000000..4283ae860 --- /dev/null +++ b/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup IAR_ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/LPC11xx/vectors.s b/os/ports/IAR/ARMCMx/LPC11xx/vectors.s new file mode 100644 index 000000000..633313f52 --- /dev/null +++ b/os/ports/IAR/ARMCMx/LPC11xx/vectors.s @@ -0,0 +1,187 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +_unhandled_exception + b _unhandled_exception + + END diff --git a/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 000000000..5019bacda --- /dev/null +++ b/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the LPC13xx. + * + * @defgroup IAR_ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/LPC13xx/vectors.s b/os/ports/IAR/ARMCMx/LPC13xx/vectors.s new file mode 100644 index 000000000..21ea588c3 --- /dev/null +++ b/os/ports/IAR/ARMCMx/LPC13xx/vectors.s @@ -0,0 +1,265 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +_unhandled_exception + b _unhandled_exception + + END diff --git a/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 000000000..4f44a6827 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s b/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s new file mode 100644 index 000000000..1d660d55d --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s @@ -0,0 +1,310 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#define _FROM_ASM_ +#include "board.h" +#endif + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorEC + DCD VectorF0 + DCD VectorF4 +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C +#endif +#if defined(STM32F10X_CL) + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C +#endif + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBWEAK Vector128 + PUBWEAK Vector12C + PUBWEAK Vector130 + PUBWEAK Vector134 + PUBWEAK Vector138 + PUBWEAK Vector13C + PUBWEAK Vector140 + PUBWEAK Vector144 + PUBWEAK Vector148 + PUBWEAK Vector14C + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +_unhandled_exception + b _unhandled_exception + + END diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..2d56050c2 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s b/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 000000000..3021cd421 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,337 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBWEAK Vector128 + PUBWEAK Vector12C + PUBWEAK Vector130 + PUBWEAK Vector134 + PUBWEAK Vector138 + PUBWEAK Vector13C + PUBWEAK Vector140 + PUBWEAK Vector144 + PUBWEAK Vector148 + PUBWEAK Vector14C + PUBWEAK Vector150 + PUBWEAK Vector154 + PUBWEAK Vector158 + PUBWEAK Vector15C + PUBWEAK Vector160 + PUBWEAK Vector164 + PUBWEAK Vector168 + PUBWEAK Vector16C + PUBWEAK Vector170 + PUBWEAK Vector174 + PUBWEAK Vector178 + PUBWEAK Vector17C + PUBWEAK Vector180 + PUBWEAK Vector184 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 +_unhandled_exception + b _unhandled_exception + + END diff --git a/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 000000000..9cd591e03 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup IAR_ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s b/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s new file mode 100644 index 000000000..85f9d390f --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s @@ -0,0 +1,231 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32L1XX_MD) +#define _FROM_ASM_ +#include "board.h" +#endif + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +_unhandled_exception + b _unhandled_exception + + END diff --git a/os/ports/IAR/ARMCMx/chcore.c b/os/ports/IAR/ARMCMx/chcore.c new file mode 100644 index 000000000..e89084c97 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore.c @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__weak +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcore.h b/os/ports/IAR/ARMCMx/chcore.h new file mode 100644 index 000000000..0ea154f00 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore.h @@ -0,0 +1,189 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#error "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \ + (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "IAR" + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.c b/os/ports/IAR/ARMCMx/chcore_v6m.c new file mode 100644 index 000000000..5a3c8ca0c --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore_v6m.c @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup IAR_ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp++; + __set_PSP((unsigned long)ctxp); + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp++; + __set_PSP((unsigned long)ctxp); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp--; + __set_PSP((unsigned long)ctxp); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + } +} + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h new file mode 100644 index 000000000..d1d5caeb6 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -0,0 +1,379 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup IAR_ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief Maximum usable priority for normal ISRs. + */ +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#else +#define CORTEX_MAX_KERNEL_PRIORITY 0 +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__get_LR() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() __disable_interrupt() + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() __enable_interrupt() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() __disable_interrupt() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() __disable_interrupt() + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() __enable_interrupt() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm ("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.c b/os/ports/IAR/ARMCMx/chcore_v7m.c new file mode 100644 index 000000000..c9d45b1a6 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore_v7m.c @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + __set_PSP((unsigned long)ctxp); + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + __set_PSP((unsigned long)ctxp); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); + +#if CORTEX_USE_FPU + { + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access.*/ + SCB_CPACR |= 0x00F00000; + + /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/ + __set_CONTROL(__get_CONTROL() | 4); + + /* FPSCR and FPDSCR initially zero.*/ + __set_FPSCR(0); + SCB_FPDSCR = 0; + } +#endif + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + __set_PSP((unsigned long)ctxp); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + (void)__get_FPSCR(); +#endif + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h new file mode 100644 index 000000000..112c52a35 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -0,0 +1,504 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/** + * @brief NVIC PRIGROUP initialization expression. + * @details The default assigns all available priority bits as preemption + * priority with no sub-priority. + */ +#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) +#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief Maximum usable priority for normal ISRs. + */ +#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) +#else + +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL) +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() __disable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED) +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() __enable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() __disable_interrupt() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + __set_BASEPRI(CORTEX_BASEPRI_KERNEL); \ + __enable_interrupt(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() __disable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + __set_BASEPRI(CORTEX_BASEPRI_DISABLED); \ + __enable_interrupt(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() __enable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm ("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s new file mode 100644 index 000000000..d2149ea59 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?chcoreasm_v6m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere: + b waithere + + END diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s new file mode 100644 index 000000000..ca077431d --- /dev/null +++ b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?chcoreasm_v7m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 +ICSR_PENDSVSET SET 0x10000000 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #LWRD SCB_ICSR + movt r3, #HWRD SCB_ICSR + mov r2, #ICSR_PENDSVSET + str r2, [r3] + cpsie i +.L3: b .L3 +#else + svc #0 +#endif + + END diff --git a/os/ports/IAR/ARMCMx/chtypes.h b/os/ports/IAR/ARMCMx/chtypes.h new file mode 100644 index 000000000..9855c4e00 --- /dev/null +++ b/os/ports/IAR/ARMCMx/chtypes.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN __packed + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/cstartup.s b/os/ports/IAR/ARMCMx/cstartup.s new file mode 100644 index 000000000..3ee52d0a1 --- /dev/null +++ b/os/ports/IAR/ARMCMx/cstartup.s @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?cstartup + +CONTROL_MODE_PRIVILEGED SET 0 +CONTROL_MODE_UNPRIVILEGED SET 1 +CONTROL_USE_MSP SET 0 +CONTROL_USE_PSP SET 2 + + AAPCS INTERWORK, VFP_COMPATIBLE, ROPI + PRESERVE8 + + SECTION .intvec:CODE:NOROOT(3) + + SECTION CSTACK:DATA:NOROOT(3) + PUBLIC __main_thread_stack_base__ +__main_thread_stack_base__: + PUBLIC __heap_end__ +__heap_end__: + + SECTION SYSHEAP:DATA:NOROOT(3) + PUBLIC __heap_base__ +__heap_base__: + + PUBLIC __iar_program_start + EXTERN __vector_table + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + EXTERN __cmain + + SECTION .text:CODE:REORDER(2) + REQUIRE __vector_table + THUMB +__iar_program_start: + cpsid i + ldr r0, =SFE(CSTACK) + msr PSP, r0 + movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP + msr CONTROL, r0 + isb + bl __early_init + bl __iar_init_core + bl __iar_init_vfp + b __cmain + + PUBWEAK __early_init +__early_init: + bx lr + + END diff --git a/os/ports/IAR/ARMCMx/port.dox b/os/ports/IAR/ARMCMx/port.dox new file mode 100644 index 000000000..5336c14cf --- /dev/null +++ b/os/ports/IAR/ARMCMx/port.dox @@ -0,0 +1,228 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup IAR_ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the IAR compiler. + + * @section IAR_ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section IAR_ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
    + * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/IAR/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * . + * @ingroup iar + */ + +/** + * @defgroup IAR_ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section IAR_ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section IAR_ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx_CORE + */ + +/** + * @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx_CORE + */ + +/** + * @defgroup IAR_ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section IAR_ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in the + * linker script (usually named @p ch.icf). + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# Control is passed to the C runtime entry point @p __cmain that performs + * the required initializations before invoking the @p main() function. + * . + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup IAR_ARMCMx + */ diff --git a/os/ports/IAR/STM8/chcore.c b/os/ports/IAR/STM8/chcore.c new file mode 100644 index 000000000..020c1cfb0 --- /dev/null +++ b/os/ports/IAR/STM8/chcore.c @@ -0,0 +1,55 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cosmic/STM8/chcore.c + * @brief STM8 (Cosmic) architecture port code. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#include "ch.h" + +__tiny ReadyList rlist; + +/** + * @brief Thread start code. + */ +__task void _port_thread_start(void) { + chSysUnlock(); + asm("popw x"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/IAR/STM8/chcore.h b/os/ports/IAR/STM8/chcore.h new file mode 100644 index 000000000..29bf5087c --- /dev/null +++ b/os/ports/IAR/STM8/chcore.h @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cosmic/STM8/chcore.h + * @brief STM8 (Cosmic) architecture port macros and structures. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef STM8_ENABLE_WFI_IDLE +#define STM8_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_STM8 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "STM8" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "IAR" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack alignment. + * @note No alignment constraints so uint8_t. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Generic STM8 function pointer. + * @note It is used to allocate the proper size for return addresses in + * context-related structures. + */ +typedef void (*stm8func_t)(void); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct extctx { + uint8_t _next; + uint16_t w3; + uint16_t w2; + uint16_t w1; + uint16_t w0; + uint8_t cc; + uint8_t a; + uint16_t x; + uint16_t y; + uint8_t pce; + uint8_t pch; + uint8_t pcl; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching.. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct intctx { + uint8_t _next; + uint16_t w7; + uint16_t w6; + uint16_t w5; + uint16_t w4; + stm8func_t pc; /* Function pointer sized return address. */ +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Start context. + * @details This context is the stack organization for the trampoline code + * @p _port_thread_start(). + */ +struct stm8_startctx { + uint8_t saved_vreg[8]; // saved virtual registers to restore + uint8_t _next; + stm8func_t ts; /* Trampoline address. */ + void *arg; /* Thread argument. */ + stm8func_t pc; /* Thread function address. */ + stm8func_t ret; /* chThdExit() address. */ +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + struct stm8_startctx *scp; \ + scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ + sizeof(struct stm8_startctx)); \ + scp->ts = (stm8func_t)_port_thread_start; \ + scp->arg = (void *)arg; \ + scp->pc = (stm8func_t)pf; \ + scp->ret = (stm8func_t)chThdExit; \ + tp->p_ctx.sp = (struct intctx *)scp; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This is a safe value, you may trim it down after reading the + * right size in the map file. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 48 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) \ + _Pragma(VECTOR_ID((id)+2)) __interrupt void vector##id(void) + +/** + * @brief Port-related initialization code. + * @note None in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @note Implemented as global interrupts disable. + */ +#define port_lock() asm("sim") + +/** + * @brief Kernel-unlock action. + * @note Implemented as global interrupts enable. + */ +#define port_unlock() asm("rim") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Implemented as global interrupts disable. + * @note Of course non-maskable interrupt sources are not included. + */ +#define port_disable() asm("sim") + +/** + * @brief Disables the interrupt sources that are not supposed to preempt + * the kernel. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm("sim") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() asm("rim") + +/** + * @brief Enters an architecture-dependent halt mode. + * @note Implemented with the specific "wfi" instruction. + */ +#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note Implemented as a call to a low level assembler routine. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(otp) + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *otp); + __task void _port_thread_start(void); + void port_halt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Scheduler captured code. */ +/*===========================================================================*/ + +#define PORT_OPTIMIZED_RLIST_VAR +#define PORT_OPTIMIZED_RLIST_EXT +#define PORT_OPTIMIZED_READYLIST_STRUCT + +typedef struct { + ThreadsQueue r_queue; + tprio_t r_prio; + Thread *r_current; +#if CH_USE_REGISTRY + Thread *r_newer; + Thread *r_older; +#endif + /* End of the fields shared with the Thread structure.*/ +#if CH_TIME_QUANTUM > 0 + cnt_t r_preempt; +#endif +} ReadyList; + +extern __tiny ReadyList rlist; + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/IAR/STM8/chcore_stm8.s b/os/ports/IAR/STM8/chcore_stm8.s new file mode 100644 index 000000000..6dc719c5c --- /dev/null +++ b/os/ports/IAR/STM8/chcore_stm8.s @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +; Get definitions for virtual registers used by the compiler +#include "vregs.inc" + + SECTION .near_func.text:code + EXTERN rlist + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push ?b8 + push ?b9 + push ?b10 + push ?b11 + push ?b12 + push ?b13 + push ?b14 + push ?b15 + + ldw y,sp + ldw (5,x),y + ldw x, rlist + 5 + ldw x,(5,x) + ldw sp,x + + pop ?b15 + pop ?b14 + pop ?b13 + pop ?b12 + pop ?b11 + pop ?b10 + pop ?b9 + pop ?b8 + ret + + END diff --git a/os/ports/IAR/STM8/chtypes.h b/os/ports/IAR/STM8/chtypes.h new file mode 100644 index 000000000..f418256e1 --- /dev/null +++ b/os/ports/IAR/STM8/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/STM8/chtypes.h + * @brief STM8 (IAR) port system types. + * + * @addtogroup STM8_IAR_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint8_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef int8_t eventid_t; /**< Event Id. */ +typedef uint8_t eventmask_t; /**< Event mask. */ +typedef uint8_t flagsmask_t; /**< Event flags. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int8_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note Uses the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/IAR/STM8/port.dox b/os/ports/IAR/STM8/port.dox new file mode 100644 index 000000000..c0eb35cdd --- /dev/null +++ b/os/ports/IAR/STM8/port.dox @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup STM8_IAR STM8 + * @details STM8 port for the Cosmic C compiler. + * + * @section STM8_IAR_INTRO Introduction + * This port supports all STM8 8 bits MCUs. + * + * @section STM8_IAR_STATES Mapping of the System States in the STM8 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Implemented with "wait" instruction insertion in the idle + * loop. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The STM8 ha non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section STM8_IAR_NOTES The STM8 port notes + * - The STM8 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./os/ports/IAR/STM8/chcore.h. + * - The kernel currently supports only the small memory model so the + * kernel files should be loaded in the first 64K. Note that this is not + * a problem because upper addresses can be used by the user code, the + * kernel can context switch code running there. + * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported + * because the missing support of the @p inline "C" keyword in the + * compiler. + * . + * @ingroup iar + */ + +/** + * @defgroup STM8_IAR_CONF Configuration Options + * @details STM8 Configuration Options. The STM8 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
    + * The default for this value is @p 48, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * . + * @ingroup STM8_IAR + */ + +/** + * @defgroup STM8_IAR_CORE Core Port Implementation + * @details STM8 specific port code, structures and macros. + * + * @ingroup STM8_IAR + */ + + /** + * @defgroup STM8_IAR_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the STM8, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup STM8_IAR + */ diff --git a/os/ports/RC/STM8/chcore.c b/os/ports/RC/STM8/chcore.c new file mode 100644 index 000000000..1b4c1d0a4 --- /dev/null +++ b/os/ports/RC/STM8/chcore.c @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RC/STM8/chcore.c + * @brief STM8 (Raisonance) architecture port code. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ +#pragma SRC("tmp.asm") + +#include "ch.h" + +page0 ReadyList rlist; + +/** + * @brief Performs a context switch between two threads. + * + * @param otp the thread to be switched out + */ +void _port_switch(Thread *otp) { + + (void)otp; + /* Asm because unoptimal code would generated by using _getSP_().*/ +#pragma ASM + LDW Y,SP ; old context pointer + LDW (5,X),Y ; SP saved in otp->p_ctx.sp + LDW X,rlist + 5 ; r_current (currp) field + LDW X,(5,X) ; currp->p_ctx.sp + LDW SP,X ; new context pointer +#pragma ENDASM +} + +/** + * @brief Thread start code. + */ +void _port_thread_start(void) { + + chSysUnlock(); +#pragma ASM + POPW X +#pragma ENDASM +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/RC/STM8/chcore.h b/os/ports/RC/STM8/chcore.h new file mode 100644 index 000000000..716c8ff74 --- /dev/null +++ b/os/ports/RC/STM8/chcore.h @@ -0,0 +1,334 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RC/STM8/chcore.h + * @brief STM8 (Raisonance) architecture port macros and structures. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef STM8_ENABLE_WFI_IDLE +#define STM8_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_STM8 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "STM8" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "Raisonance" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack alignment. + * @note No alignment constraints so uint8_t. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Generic STM8 function pointer. + * @note It is used to allocate the proper size for return addresses in + * context-related structures. + */ +typedef void (*stm8func_t)(void); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct extctx { + uint8_t _next; + uint16_t cx; + uint16_t bx; + uint8_t cc; + uint8_t a; + uint16_t x; + uint16_t y; + uint8_t pce; + uint8_t pch; + uint8_t pcl; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching.. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct intctx { + uint8_t _next; + stm8func_t pc; /* Function pointer sized return address. */ +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Start context. + * @details This context is the stack organization for the trampoline code + * @p _port_thread_start(). + */ +struct stm8_startctx { + uint8_t _next; + stm8func_t ts; /* Trampoline address. */ + void *arg; /* Thread argument. */ + stm8func_t pc; /* Thread function address. */ + stm8func_t ret; /* chThdExit() address. */ +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + struct stm8_startctx *scp; \ + scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ + sizeof(struct stm8_startctx)); \ + scp->ts = _port_thread_start; \ + scp->arg = arg; \ + scp->pc = (stm8func_t)pf; \ + scp->ret = (stm8func_t)chThdExit; \ + tp->p_ctx.sp = (struct intctx *)scp; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This is a safe value, you may trim it down after reading the + * right size in the map file. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 48 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() { \ +} + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void vector##id(void) interrupt id + +/** + * @brief Port-related initialization code. + * @note None in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @note Implemented as global interrupts disable. + */ +#define port_lock() _sim_() + +/** + * @brief Kernel-unlock action. + * @note Implemented as global interrupts enable. + */ +#define port_unlock() _rim_() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Implemented as global interrupts disable. + * @note Of course non-maskable interrupt sources are not included. + */ +#define port_disable() _sim_() + +/** + * @brief Disables the interrupt sources that are not supposed to preempt + * the kernel. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() _sim_() + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() _rim_() + +/** + * @brief Enters an architecture-dependent halt mode. + * @note Implemented with the specific "wfi" instruction. + */ +#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() _wfi_() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note Implemented as a call to a low level assembler routine. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(otp) + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *otp); + void _port_thread_start(void); + void port_halt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Scheduler captured code. */ +/*===========================================================================*/ + +#define PORT_OPTIMIZED_RLIST_VAR +#define PORT_OPTIMIZED_RLIST_EXT +#define PORT_OPTIMIZED_READYLIST_STRUCT + +typedef struct { + ThreadsQueue r_queue; + tprio_t r_prio; + Thread *r_current; +#if CH_USE_REGISTRY + Thread *r_newer; + Thread *r_older; +#endif + /* End of the fields shared with the Thread structure.*/ +#if CH_TIME_QUANTUM > 0 + cnt_t r_preempt; +#endif +} ReadyList; + +page0 extern ReadyList rlist; + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/RC/STM8/chtypes.h b/os/ports/RC/STM8/chtypes.h new file mode 100644 index 000000000..ffc972f14 --- /dev/null +++ b/os/ports/RC/STM8/chtypes.h @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RC/STM8/chtypes.h + * @brief STM8 (Raisonance) port system types. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include + +typedef unsigned char uint8t; /**< C99-style boolean. */ +typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */ +typedef signed char int8_t; /**< C99-style 8 bits signed. */ +typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */ +typedef signed int int16_t; /**< C99-style 16 bits signed. */ +typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */ +typedef signed long int32_t; /**< C99-style 32 bits signed. */ +typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */ +typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */ +typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */ + +#if !defined(false) || defined(__DOXYGEN__) +#define false 0 +#endif + +#if !defined(true) || defined(__DOXYGEN__) +#define true (!false) +#endif + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint8_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef int8_t eventid_t; /**< Event Id. */ +typedef uint8_t eventmask_t; /**< Event mask. */ +typedef uint8_t flagsmask_t; /**< Event flags. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int8_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note Uses the "const" keyword in this port. + */ +#define ROMCONST code + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/RC/STM8/port.dox b/os/ports/RC/STM8/port.dox new file mode 100644 index 000000000..8dc4ba259 --- /dev/null +++ b/os/ports/RC/STM8/port.dox @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup STM8_RAISONANCE STM8 + * @details STM8 port for the Raisonance C compiler. + * + * @section STM8_RAISONANCE_INTRO Introduction + * This port supports all STM8 8 bits MCUs. + * + * @section STM8_RAISONANCE_STATES Mapping of the System States in the STM8 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Implemented with "wait" instruction insertion in the idle + * loop. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The STM8 ha non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section STM8_RAISONANCE_NOTES The STM8 port notes + * - The STM8 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./os/ports/RC/STM8/chcore.h. + * - The kernel currently supports only the small memory model so the + * kernel files should be loaded in the first 64K. Note that this is not + * a problem because upper addresses can be used by the user code, the + * kernel can context switch code running there. + * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported + * because the missing support of the @p inline "C" keyword in the + * compiler. + * . + * @ingroup raisonance + */ + +/** + * @defgroup STM8_RAISONANCE_CONF Configuration Options + * @details STM8 Configuration Options. The STM8 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
    + * The default for this value is @p 48, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * . + * @ingroup STM8_RAISONANCE + */ + +/** + * @defgroup STM8_RAISONANCE_CORE Core Port Implementation + * @details STM8 specific port code, structures and macros. + * + * @ingroup STM8_RAISONANCE + */ + + /** + * @defgroup STM8_RAISONANCE_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the STM8, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup STM8_RAISONANCE + */ diff --git a/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 000000000..e60e06771 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup RVCT_ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s b/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s new file mode 100644 index 000000000..0c08b902c --- /dev/null +++ b/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s @@ -0,0 +1,183 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 000000000..76cfe70e1 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the LPC13xx. + * + * @defgroup RVCT_ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s b/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s new file mode 100644 index 000000000..dd027d879 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s @@ -0,0 +1,261 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 000000000..b1057616f --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup RVCT_ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s new file mode 100644 index 000000000..f3a303543 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s @@ -0,0 +1,306 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorEC + DCD VectorF0 + DCD VectorF4 +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C +#endif +#if defined(STM32F10X_CL) + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C +#endif + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..8c040789f --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup RVCT_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 000000000..6a912c5af --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32F4XX) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + EXPORT Vector150 [WEAK] + EXPORT Vector154 [WEAK] + EXPORT Vector158 [WEAK] + EXPORT Vector15C [WEAK] + EXPORT Vector160 [WEAK] + EXPORT Vector164 [WEAK] + EXPORT Vector168 [WEAK] + EXPORT Vector16C [WEAK] + EXPORT Vector170 [WEAK] + EXPORT Vector174 [WEAK] + EXPORT Vector178 [WEAK] + EXPORT Vector17C [WEAK] + EXPORT Vector180 [WEAK] + EXPORT Vector184 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 000000000..61916a722 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup RVCT_ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s new file mode 100644 index 000000000..da0f368c0 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s @@ -0,0 +1,227 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32L1XX_MD) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/chcore.c b/os/ports/RVCT/ARMCMx/chcore.c new file mode 100644 index 000000000..cb5993577 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore.c @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h new file mode 100644 index 000000000..5ba5a1eb5 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -0,0 +1,188 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#error "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \ + (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "RVCT" + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.c b/os/ports/RVCT/ARMCMx/chcore_v6m.c new file mode 100644 index 000000000..d8183cdd4 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)psp; + ctxp++; + psp = (uint32_t)ctxp; + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)psp; + ctxp++; + psp = (uint32_t)ctxp; +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp = (struct extctx *)psp; + ctxp--; + psp = (uint32_t)ctxp; + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + } +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h new file mode 100644 index 000000000..2ed119dd3 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -0,0 +1,380 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief Maximum usable priority for normal ISRs. + */ +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#else +#define CORTEX_MAX_KERNEL_PRIORITY 0 +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__return_address() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() __disable_irq() + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() __enable_irq() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() __disable_irq() + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() __enable_irq() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + uint8_t *r13 = (uint8_t *)__current_sp(); \ + if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.c b/os/ports/RVCT/ARMCMx/chcore_v7m.c new file mode 100644 index 000000000..9912e3cb2 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.c @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup RVCT_ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + psp = (uint32_t)ctxp; + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + psp = (uint32_t)ctxp; +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); + +#if CORTEX_USE_FPU + { + register uint32_t control __asm("control"); + register uint32_t fpscr __asm("fpscr"); + + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access in the startup code.*/ +/* SCB_CPACR |= 0x00F00000;*/ + + /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/ + control |= 4; + + /* FPSCR and FPDSCR initially zero.*/ + fpscr = 0; + SCB_FPDSCR = 0; + } +#endif + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + psp = (uint32_t)ctxp; + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + register uint32_t fpscr __asm("fpscr"); + ctxp->r0 = (regarm_t)fpscr; +#endif + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h new file mode 100644 index 000000000..677a4dfc0 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -0,0 +1,512 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup RVCT_ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 32 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/** + * @brief NVIC PRIGROUP initialization expression. + * @details The default assigns all available priority bits as preemption + * priority with no sub-priority. + */ +#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) +#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief Maximum usable priority for normal ISRs. + */ +#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) +#else + +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_lock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_unlock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ + __enable_irq(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + uint8_t *r13 = (uint8_t *)__current_sp(); \ + if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s new file mode 100644 index 000000000..282ac547d --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET EQU 12 +SCB_ICSR EQU 0xE000ED04 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT dbg_check_unlock + IMPORT dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere b waithere + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s new file mode 100644 index 000000000..e9404daba --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET EQU 12 +SCB_ICSR EQU 0xE000ED04 +ICSR_PENDSVSET EQU 0x10000000 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT dbg_check_unlock + IMPORT dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #SCB_ICSR :AND: 0xFFFF + movt r3, #SCB_ICSR :SHR: 16 + mov r2, #ICSR_PENDSVSET + str r2, [r3, #0] + cpsie i +waithere b waithere +#else + svc #0 +#endif + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/chtypes.h b/os/ports/RVCT/ARMCMx/chtypes.h new file mode 100644 index 000000000..b3f19f674 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chtypes.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE __inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN __packed + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s new file mode 100644 index 000000000..e0c6b85ee --- /dev/null +++ b/os/ports/RVCT/ARMCMx/cstartup.s @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// Main Stack Configuration (IRQ Stack) +;// Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +main_stack_size EQU 0x00000400 + +;// Process Stack Configuration +;// Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +proc_stack_size EQU 0x00000400 + +;// C-runtime heap size +;// C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +heap_size EQU 0x00000400 + + AREA MSTACK, NOINIT, READWRITE, ALIGN=3 +main_stack_mem SPACE main_stack_size + EXPORT __initial_msp +__initial_msp + + AREA CSTACK, NOINIT, READWRITE, ALIGN=3 +__main_thread_stack_base__ + EXPORT __main_thread_stack_base__ +proc_stack_mem SPACE proc_stack_size + EXPORT __initial_sp +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE heap_size +__heap_limit + +CONTROL_MODE_PRIVILEGED EQU 0 +CONTROL_MODE_UNPRIVILEGED EQU 1 +CONTROL_USE_MSP EQU 0 +CONTROL_USE_PSP EQU 2 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +/* + * Reset handler. + */ + IMPORT __main + EXPORT Reset_Handler +Reset_Handler PROC + cpsid i + ldr r0, =__initial_sp + msr PSP, r0 + movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP + msr CONTROL, r0 + isb + bl __early_init + + IF {CPU} = "Cortex-M4.fp" + LDR R0, =0xE000ED88 ; Enable CP10,CP11 + LDR R1, [R0] + ORR R1, R1, #(0xF << 20) + STR R1, [R0] + ENDIF + + ldr r0, =__main + bx r0 + ENDP + +__early_init PROC + EXPORT __early_init [WEAK] + bx lr + ENDP + + ALIGN + +/* + * User Initial Stack & Heap. + */ + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + ldr r0, =Heap_Mem + ldr r1, =(proc_stack_mem + proc_stack_size) + ldr r2, =(Heap_Mem + heap_size) + ldr r3, =proc_stack_mem + bx lr + + ALIGN + + ENDIF + + END diff --git a/os/ports/RVCT/ARMCMx/port.dox b/os/ports/RVCT/ARMCMx/port.dox new file mode 100644 index 000000000..66f9ec23f --- /dev/null +++ b/os/ports/RVCT/ARMCMx/port.dox @@ -0,0 +1,233 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup RVCT_ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the RVCT compiler. + + * @section RVCT_ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section RVCT_ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section RVCT_ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section RVCT_ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
    + * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section RVCT_ARMCMx_NOTES ARM Cortex-Mx/RVCT port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/RVCT/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * - The free uVision is not able to handle scatter files, the following + * options are required in the project options under "Preprocesso symbols" + * in order to use the unused RAM as heap automatically: + * __heap_base__=Image$$RW_IRAM1$$ZI$$Limit + * __heap_end__=Image$$RW_IRAM2$$Base + * . + * @ingroup rvct + */ + +/** + * @defgroup RVCT_ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section RVCT_ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section RVCT_ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section RVCT_ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in + * cstartup.s file and accessible through the configuration wizard. + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# Control is passed to the C runtime entry point @p __main that performs + * the required initializations before invoking the @p main() function. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup RVCT_ARMCMx + */ diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h b/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h new file mode 100644 index 000000000..5fd6ff4af --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h @@ -0,0 +1,38 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef[6144]; +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_math.h b/os/ports/common/ARMCMx/CMSIS/include/arm_math.h new file mode 100644 index 000000000..266dbfc91 --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/arm_math.h @@ -0,0 +1,7578 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * $Date: 15. February 2012 + * $Revision: V1.1.0 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.1.0 2012/02/15 + * Updated with more optimizations, bug fixes and minor API changes. + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.23. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* CHIBIOS FIX BEGIN */ +#include "board.h" +#if defined(STM32F4XX) +#define ARM_MATH_CM4 +#define __FPU_PRESENT 1 +#elif (defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ + defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(STM32F10X_CL)) +#define ARM_MATH_CM3 +#elif defined(STM32F0XX) +#define ARM_MATH_CM0 +#endif +/* CHIBIOS FIX END */ + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined (__GNUC__) + #define __SIMD32(addr) (*( int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr)) +#else + #define __SIMD32(addr) (*(__packed int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr)) +#endif + + #define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && defined ( __TASKING__ ) +/* No need to redefine __CLZ */ +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) ) + + __STATIC_INLINE uint32_t __CLZ(q31_t data); + + + __STATIC_INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the f32 FFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the f32 IFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen 1/fftLenfth + * @return none. + */ + + void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + +#ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + +#else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + +#endif + +#ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc); + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + /* CHIBIOS FIX BEGIN */ + else if(i >= (int32_t)S->nValues) + /* CHIBIOS FIX END */ + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + /* CHIBIOS FIX BEGIN */ + if(index >= ((int32_t)nValues - 1)) + /* CHIBIOS FIX END */ + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + /* CHIBIOS FIX BEGIN */ + if(index >= ((int32_t)nValues - 1)) + /* CHIBIOS FIX END */ + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + /* CHIBIOS FIX BEGIN */ + if(index >= ((int32_t)nValues - 1)) + /* CHIBIOS FIX END */ + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #elif (__FPU_USED == 1) && defined ( __TMS_740 ) + *pOut = __builtin_sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h new file mode 100644 index 000000000..0d7cfd85e --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h @@ -0,0 +1,667 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 13. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h new file mode 100644 index 000000000..cf92fb7fe --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h @@ -0,0 +1,778 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h new file mode 100644 index 000000000..db1716ad9 --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h @@ -0,0 +1,1612 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h new file mode 100644 index 000000000..024302e4a --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h @@ -0,0 +1,1757 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h new file mode 100644 index 000000000..b5140073f --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h @@ -0,0 +1,649 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h new file mode 100644 index 000000000..585d2bb56 --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +/* CHIBIOS FIX BEGIN */ +#else + (void)fpscr; +/* CHIBIOS FIX END */ +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h new file mode 100644 index 000000000..624c175fd --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/os/ports/common/ARMCMx/CMSIS/readme.txt b/os/ports/common/ARMCMx/CMSIS/readme.txt new file mode 100644 index 000000000..6e2172455 --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/readme.txt @@ -0,0 +1,6 @@ +CMSIS is Copyright (C) 2011 ARM Limited. All rights reserved. + +This directory contains only part of the CMSIS package. If you need the whole +package please download it from: + +http://www.onarm.com diff --git a/os/ports/common/ARMCMx/nvic.c b/os/ports/common/ARMCMx/nvic.c new file mode 100644 index 000000000..3cf80fbfc --- /dev/null +++ b/os/ports/common/ARMCMx/nvic.c @@ -0,0 +1,74 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file common/ARMCMx/nvic.c + * @brief Cortex-Mx NVIC support code. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#include "ch.h" +#include "nvic.h" + +/** + * @brief Sets the priority of an interrupt handler and enables it. + * @note The parameters are not tested for correctness. + * + * @param[in] n the interrupt number + * @param[in] prio the interrupt priority mask + */ +void nvicEnableVector(uint32_t n, uint32_t prio) { + unsigned sh = (n & 3) << 3; + + NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); + NVIC_ICPR(n >> 5) = 1 << (n & 0x1F); + NVIC_ISER(n >> 5) = 1 << (n & 0x1F); +} + +/** + * @brief Disables an interrupt handler. + * @note The parameters are not tested for correctness. + * + * @param[in] n the interrupt number + */ +void nvicDisableVector(uint32_t n) { + unsigned sh = (n & 3) << 3; + + NVIC_ICER(n >> 5) = 1 << (n & 0x1F); + NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh); +} + +/** + * @brief Changes the priority of a system handler. + * @note The parameters are not tested for correctness. + * + * @param[in] handler the system handler number + * @param[in] prio the system handler priority mask + */ +void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { + unsigned sh = (handler & 3) * 8; + + SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & + ~(0xFF << sh)) | (prio << sh); +} + +/** @} */ diff --git a/os/ports/common/ARMCMx/nvic.h b/os/ports/common/ARMCMx/nvic.h new file mode 100644 index 000000000..5ebff94cd --- /dev/null +++ b/os/ports/common/ARMCMx/nvic.h @@ -0,0 +1,293 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file common/ARMCMx/nvic.h + * @brief Cortex-Mx NVIC support macros and structures. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#ifndef _NVIC_H_ +#define _NVIC_H_ + +/** + * @name System vector numbers + * @{ + */ +#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ +#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ +#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ +#define HANDLER_RESERVED_3 3 +#define HANDLER_RESERVED_4 4 +#define HANDLER_RESERVED_5 5 +#define HANDLER_RESERVED_6 6 +#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ +#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ +#define HANDLER_RESERVED_9 9 +#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ +#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ +/** @} */ + +typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ +typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ + +/** + * @brief NVIC ITCR register. + */ +#define NVIC_ITCR (*((IOREG32 *)0xE000E004U)) + +/** + * @brief Structure representing the SYSTICK I/O space. + */ +typedef struct { + IOREG32 CSR; + IOREG32 RVR; + IOREG32 CVR; + IOREG32 CBVR; +} CMx_ST; + +/** + * @brief SYSTICK peripheral base address. + */ +#define STBase ((CMx_ST *)0xE000E010U) +#define ST_CSR (STBase->CSR) +#define ST_RVR (STBase->RVR) +#define ST_CVR (STBase->CVR) +#define ST_CBVR (STBase->CBVR) + +#define CSR_ENABLE_MASK (0x1U << 0) +#define ENABLE_OFF_BITS (0U << 0) +#define ENABLE_ON_BITS (1U << 0) +#define CSR_TICKINT_MASK (0x1U << 1) +#define TICKINT_DISABLED_BITS (0U << 1) +#define TICKINT_ENABLED_BITS (1U << 1) +#define CSR_CLKSOURCE_MASK (0x1U << 2) +#define CLKSOURCE_EXT_BITS (0U << 2) +#define CLKSOURCE_CORE_BITS (1U << 2) +#define CSR_COUNTFLAG_MASK (0x1U << 16) + +#define RVR_RELOAD_MASK (0xFFFFFFU << 0) + +#define CVR_CURRENT_MASK (0xFFFFFFU << 0) + +#define CBVR_TENMS_MASK (0xFFFFFFU << 0) +#define CBVR_SKEW_MASK (0x1U << 30) +#define CBVR_NOREF_MASK (0x1U << 31) + +/** + * @brief Structure representing the NVIC I/O space. + */ +typedef struct { + IOREG32 ISER[8]; + IOREG32 unused1[24]; + IOREG32 ICER[8]; + IOREG32 unused2[24]; + IOREG32 ISPR[8]; + IOREG32 unused3[24]; + IOREG32 ICPR[8]; + IOREG32 unused4[24]; + IOREG32 IABR[8]; + IOREG32 unused5[56]; + IOREG32 IPR[60]; + IOREG32 unused6[644]; + IOREG32 STIR; +} CMx_NVIC; + +/** + * @brief NVIC peripheral base address. + */ +#define NVICBase ((CMx_NVIC *)0xE000E100U) +#define NVIC_ISER(n) (NVICBase->ISER[n]) +#define NVIC_ICER(n) (NVICBase->ICER[n]) +#define NVIC_ISPR(n) (NVICBase->ISPR[n]) +#define NVIC_ICPR(n) (NVICBase->ICPR[n]) +#define NVIC_IABR(n) (NVICBase->IABR[n]) +#define NVIC_IPR(n) (NVICBase->IPR[n]) +#define NVIC_STIR (NVICBase->STIR) + +/** + * @brief Structure representing the System Control Block I/O space. + */ +typedef struct { + IOREG32 CPUID; + IOREG32 ICSR; + IOREG32 VTOR; + IOREG32 AIRCR; + IOREG32 SCR; + IOREG32 CCR; + IOREG32 SHPR[3]; + IOREG32 SHCSR; + IOREG32 CFSR; + IOREG32 HFSR; + IOREG32 DFSR; + IOREG32 MMFAR; + IOREG32 BFAR; + IOREG32 AFSR; + IOREG32 PFR[2]; + IOREG32 DFR; + IOREG32 ADR; + IOREG32 MMFR[4]; + IOREG32 SAR[5]; + IOREG32 unused1[5]; + IOREG32 CPACR; +} CMx_SCB; + +/** + * @brief SCB peripheral base address. + */ +#define SCBBase ((CMx_SCB *)0xE000ED00U) +#define SCB_CPUID (SCBBase->CPUID) +#define SCB_ICSR (SCBBase->ICSR) +#define SCB_VTOR (SCBBase->VTOR) +#define SCB_AIRCR (SCBBase->AIRCR) +#define SCB_SCR (SCBBase->SCR) +#define SCB_CCR (SCBBase->CCR) +#define SCB_SHPR(n) (SCBBase->SHPR[n]) +#define SCB_SHCSR (SCBBase->SHCSR) +#define SCB_CFSR (SCBBase->CFSR) +#define SCB_HFSR (SCBBase->HFSR) +#define SCB_DFSR (SCBBase->DFSR) +#define SCB_MMFAR (SCBBase->MMFAR) +#define SCB_BFAR (SCBBase->BFAR) +#define SCB_AFSR (SCBBase->AFSR) +#define SCB_PFR(n) (SCBBase->PFR[n]) +#define SCB_DFR (SCBBase->DFR) +#define SCB_ADR (SCBBase->ADR) +#define SCB_MMFR(n) (SCBBase->MMFR[n]) +#define SCB_SAR(n) (SCBBase->SAR[n]) +#define SCB_CPACR (SCBBase->CPACR) + +#define ICSR_VECTACTIVE_MASK (0x1FFU << 0) +#define ICSR_RETTOBASE (0x1U << 11) +#define ICSR_VECTPENDING_MASK (0x1FFU << 12) +#define ICSR_ISRPENDING (0x1U << 22) +#define ICSR_ISRPREEMPT (0x1U << 23) +#define ICSR_PENDSTCLR (0x1U << 25) +#define ICSR_PENDSTSET (0x1U << 26) +#define ICSR_PENDSVCLR (0x1U << 27) +#define ICSR_PENDSVSET (0x1U << 28) +#define ICSR_NMIPENDSET (0x1U << 31) + +#define AIRCR_VECTKEY 0x05FA0000U +#define AIRCR_PRIGROUP_MASK (0x7U << 8) +#define AIRCR_PRIGROUP(n) ((n) << 8) + +/** + * @brief Structure representing the FPU I/O space. + */ +typedef struct { + IOREG32 unused1[1]; + IOREG32 FPCCR; + IOREG32 FPCAR; + IOREG32 FPDSCR; + IOREG32 MVFR0; + IOREG32 MVFR1; +} CMx_FPU; + +/** + * @brief FPU peripheral base address. + */ +#define FPUBase ((CMx_FPU *)0xE000EF30U) +#define SCB_FPCCR (FPUBase->FPCCR) +#define SCB_FPCAR (FPUBase->FPCAR) +#define SCB_FPDSCR (FPUBase->FPDSCR) +#define SCB_MVFR0 (FPUBase->MVFR0) +#define SCB_MVFR1 (FPUBase->MVFR1) + +#define FPCCR_ASPEN (0x1U << 31) +#define FPCCR_LSPEN (0x1U << 30) +#define FPCCR_MONRDY (0x1U << 8) +#define FPCCR_BFRDY (0x1U << 6) +#define FPCCR_MMRDY (0x1U << 5) +#define FPCCR_HFRDY (0x1U << 4) +#define FPCCR_THREAD (0x1U << 3) +#define FPCCR_USER (0x1U << 1) +#define FPCCR_LSPACT (0x1U << 0) + +#define FPDSCR_AHP (0x1U << 26) +#define FPDSCR_DN (0x1U << 25) +#define FPDSCR_FZ (0x1U << 24) +#define FPDSCR_RMODE(n) ((n##U) << 22) + +/** + * @brief Structure representing the SCS I/O space. + */ +typedef struct { + IOREG32 DHCSR; + IOREG32 DCRSR; + IOREG32 DCRDR; + IOREG32 DEMCR; +} CMx_SCS; + +/** + * @brief SCS peripheral base address. + */ +#define SCSBase ((CMx_SCS *)0xE000EDF0U) +#define SCS_DHCSR (SCSBase->DHCSR) +#define SCS_DCRSR (SCSBase->DCRSR) +#define SCS_DCRDR (SCSBase->DCRDR) +#define SCS_DEMCR (SCSBase->DEMCR) + +#define SCS_DEMCR_TRCENA (0x1U << 24) + +/** + * @brief Structure representing the DWT I/O space. + */ +typedef struct { + IOREG32 CTRL; + IOREG32 CYCCNT; + IOREG32 CPICNT; + IOREG32 EXCCNT; + IOREG32 SLEEPCNT; + IOREG32 LSUCNT; + IOREG32 FOLDCNT; + IOREG32 PCSR; +} CMx_DWT; + +/** + * @brief DWT peripheral base address. + */ +#define DWTBase ((CMx_DWT *)0xE0001000U) +#define DWT_CTRL (DWTBase->CTRL) +#define DWT_CYCCNT (DWTBase->CYCCNT) +#define DWT_CPICNT (DWTBase->CPICNT) +#define DWT_EXCCNT (DWTBase->EXCCNT) +#define DWT_SLEEPCNT (DWTBase->SLEEPCNT) +#define DWT_LSUCNT (DWTBase->LSUCNT) +#define DWT_FOLDCNT (DWTBase->FOLDCNT) +#define DWT_PCSR (DWTBase->PCSR) + +#define DWT_CTRL_CYCCNTENA (0x1U << 0) + +#ifdef __cplusplus +extern "C" { +#endif + void nvicEnableVector(uint32_t n, uint32_t prio); + void nvicDisableVector(uint32_t n); + void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio); +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_H_ */ + +/** @} */ diff --git a/os/ports/common/ARMCMx/port.dox b/os/ports/common/ARMCMx/port.dox new file mode 100644 index 000000000..abb6a42e7 --- /dev/null +++ b/os/ports/common/ARMCMx/port.dox @@ -0,0 +1,34 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup COMMON_ARMCMx ARM Cortex-Mx Common Code + * @ingroup port_common + */ + +/** + * @defgroup COMMON_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup COMMON_ARMCMx + */ + + /** @} */ + diff --git a/os/ports/cosmic/STM8/chcore.c b/os/ports/cosmic/STM8/chcore.c new file mode 100644 index 000000000..69fce38de --- /dev/null +++ b/os/ports/cosmic/STM8/chcore.c @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cosmic/STM8/chcore.c + * @brief STM8 (Cosmic) architecture port code. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#include "ch.h" + +@tiny ReadyList rlist; + +/** + * @brief Performs a context switch between two threads. + * + * @param otp the thread to be switched out + */ +void _port_switch(Thread *otp) { + + _asm(" xref _rlist \n" + " ldw y,sp \n" + " ldw (5,x),y \n" + " ldw x,_rlist+5 \n" + " ldw x,(5,x) \n" + " ldw sp,x \n", otp); +} + +/** + * @brief Thread start code. + */ +void _port_thread_start(void) { + + chSysUnlock(); + _asm(" popw x \n"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/cosmic/STM8/chcore.h b/os/ports/cosmic/STM8/chcore.h new file mode 100644 index 000000000..2cb5ddeeb --- /dev/null +++ b/os/ports/cosmic/STM8/chcore.h @@ -0,0 +1,332 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cosmic/STM8/chcore.h + * @brief STM8 (Cosmic) architecture port macros and structures. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef STM8_ENABLE_WFI_IDLE +#define STM8_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_STM8 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "STM8" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "Cosmic" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack alignment. + * @note No alignment constraints so uint8_t. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Generic STM8 function pointer. + * @note It is used to allocate the proper size for return addresses in + * context-related structures. + */ +typedef void (*stm8func_t)(void); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct extctx { + uint8_t _next; + uint8_t c_lreg[4]; + uint8_t c_y[3]; + uint8_t c_x[3]; + uint8_t cc; + uint8_t a; + uint16_t x; + uint16_t y; + uint8_t pce; + uint8_t pch; + uint8_t pcl; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching.. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct intctx { + uint8_t _next; + stm8func_t pc; /* Function pointer sized return address. */ +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Start context. + * @details This context is the stack organization for the trampoline code + * @p _port_thread_start(). + */ +struct stm8_startctx { + uint8_t _next; + stm8func_t ts; /* Trampoline address. */ + void *arg; /* Thread argument. */ + stm8func_t pc; /* Thread function address. */ + stm8func_t ret; /* chThdExit() address. */ +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + struct stm8_startctx *scp; \ + scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ + sizeof(struct stm8_startctx)); \ + scp->ts = _port_thread_start; \ + scp->arg = arg; \ + scp->pc = (stm8func_t)pf; \ + scp->ret = (stm8func_t)chThdExit; \ + tp->p_ctx.sp = (struct intctx *)scp; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This is a safe value, you may trim it down after reading the + * right size in the map file. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 48 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) @far @interrupt @svlreg void vector##id(void) + +/** + * @brief Port-related initialization code. + * @note None in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @note Implemented as global interrupts disable. + */ +#define port_lock() _asm("sim") + +/** + * @brief Kernel-unlock action. + * @note Implemented as global interrupts enable. + */ +#define port_unlock() _asm("rim") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Implemented as global interrupts disable. + * @note Of course non-maskable interrupt sources are not included. + */ +#define port_disable() _asm("sim") + +/** + * @brief Disables the interrupt sources that are not supposed to preempt + * the kernel. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() _asm("sim") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() _asm("rim") + +/** + * @brief Enters an architecture-dependent halt mode. + * @note Implemented with the specific "wfi" instruction. + */ +#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() _asm("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note Implemented as a call to a low level assembler routine. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(otp) + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *otp); + void _port_thread_start(void); + void port_halt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Scheduler captured code. */ +/*===========================================================================*/ + +#define PORT_OPTIMIZED_RLIST_VAR +#define PORT_OPTIMIZED_RLIST_EXT +#define PORT_OPTIMIZED_READYLIST_STRUCT + +typedef struct { + ThreadsQueue r_queue; + tprio_t r_prio; + Thread *r_current; +#if CH_USE_REGISTRY + Thread *r_newer; + Thread *r_older; +#endif + /* End of the fields shared with the Thread structure.*/ +#if CH_TIME_QUANTUM > 0 + cnt_t r_preempt; +#endif +} ReadyList; + +@tiny extern ReadyList rlist; + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/cosmic/STM8/chtypes.h b/os/ports/cosmic/STM8/chtypes.h new file mode 100644 index 000000000..efd25964e --- /dev/null +++ b/os/ports/cosmic/STM8/chtypes.h @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cosmic/STM8/chtypes.h + * @brief STM8 (Cosmic) port system types. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include + +typedef unsigned char uint8t; /**< C99-style boolean. */ +typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */ +typedef signed char int8_t; /**< C99-style 8 bits signed. */ +typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */ +typedef signed int int16_t; /**< C99-style 16 bits signed. */ +typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */ +typedef signed long int32_t; /**< C99-style 32 bits signed. */ +typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */ +typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */ +typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */ + +#if !defined(false) || defined(__DOXYGEN__) +#define false 0 +#endif + +#if !defined(true) || defined(__DOXYGEN__) +#define true (!false) +#endif + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint8_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef int8_t eventid_t; /**< Event Id. */ +typedef uint8_t eventmask_t; /**< Event mask. */ +typedef uint8_t flagsmask_t; /**< Event flags. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int8_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE @inline + +/** + * @brief ROM constant modifier. + * @note Uses the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/cosmic/STM8/port.dox b/os/ports/cosmic/STM8/port.dox new file mode 100644 index 000000000..f19f26cb2 --- /dev/null +++ b/os/ports/cosmic/STM8/port.dox @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup STM8_COSMIC STM8 + * @details STM8 port for the Cosmic C compiler. + * + * @section STM8_COSMIC_INTRO Introduction + * This port supports all STM8 8 bits MCUs. + * + * @section STM8_COSMIC_STATES Mapping of the System States in the STM8 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Implemented with "wait" instruction insertion in the idle + * loop. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The STM8 ha non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section STM8_COSMIC_NOTES The STM8 port notes + * - The STM8 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./os/ports/cosmic/STM8/chcore.h. + * - The kernel currently supports only the small memory model so the + * kernel files should be loaded in the first 64K. Note that this is not + * a problem because upper addresses can be used by the user code, the + * kernel can context switch code running there. + * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported + * because the missing support of the @p inline "C" keyword in the + * compiler. + * . + * @ingroup cosmic + */ + +/** + * @defgroup STM8_COSMIC_CONF Configuration Options + * @details STM8 Configuration Options. The STM8 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
    + * The default for this value is @p 48, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * . + * @ingroup STM8_COSMIC + */ + +/** + * @defgroup STM8_COSMIC_CORE Core Port Implementation + * @details STM8 specific port code, structures and macros. + * + * @ingroup STM8_COSMIC + */ + + /** + * @defgroup STM8_COSMIC_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the STM8, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup STM8_COSMIC + */ diff --git a/os/ports/ports.dox b/os/ports/ports.dox new file mode 100644 index 000000000..e2f834441 --- /dev/null +++ b/os/ports/ports.dox @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup ports Ports + * This section describes the technical details of the various supported + * ChibiOS/RT ports. + */ + +/** + * @defgroup port_common Common Code + * Code common to all compilers. + * + * @ingroup ports + */ + +/** + * @defgroup gcc GCC Ports + * Ports for the GCC compiler or derivatives. + * + * @ingroup ports + */ + +/** + * @defgroup iar IAR Ports + * Ports for the IAR compiler. + * + * @ingroup ports + */ + +/** + * @defgroup rvct RVCT Ports + * Ports for the RVCT compiler. + * + * @ingroup ports + */ + +/** + * @defgroup cosmic Cosmic Compiler Ports + * Ports for the Compiler compiler. + * + * @ingroup ports + */ + +/** + * @defgroup raisonance Raisonance Compiler Ports + * Ports for the Raisonance compiler. + * + * @ingroup ports + */ diff --git a/os/various/chprintf.c b/os/various/chprintf.c new file mode 100644 index 000000000..d712b98ab --- /dev/null +++ b/os/various/chprintf.c @@ -0,0 +1,263 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Fabio Utzig. + */ + +/** + * @file chprintf.c + * @brief Mini printf-like functionality. + * + * @addtogroup chprintf + * @{ + */ + +#include + +#include "ch.h" +#include "chprintf.h" + +#define MAX_FILLER 11 +#define FLOAT_PRECISION 100000 + +static char *long_to_string_with_divisor(char *p, + long num, + unsigned radix, + long divisor) { + int i; + char *q; + long l, ll; + + l = num; + if (divisor == 0) { + ll = num; + } else { + ll = divisor; + } + + q = p + MAX_FILLER; + do { + i = (int)(l % radix); + i += '0'; + if (i > '9') + i += 'A' - '0' - 10; + *--q = i; + l /= radix; + } while ((ll /= radix) != 0); + + i = (int)(p + MAX_FILLER - q); + do + *p++ = *q++; + while (--i); + + return p; +} + +static char *ltoa(char *p, long num, unsigned radix) { + + return long_to_string_with_divisor(p, num, radix, 0); +} + +#if CHPRINTF_USE_FLOAT +static char *ftoa(char *p, double num) { + long l; + unsigned long precision = FLOAT_PRECISION; + + l = num; + p = long_to_string_with_divisor(p, l, 10, 0); + *p++ = '.'; + l = (num - l) * precision; + return long_to_string_with_divisor(p, l, 10, precision / 10); +} +#endif + +/** + * @brief System formatted output function. + * @details This function implements a minimal @p printf() like functionality + * with output on a @p BaseSequentialStream. + * The general parameters format is: %[-][width|*][.precision|*][l|L]p. + * The following parameter types (p) are supported: + * - x hexadecimal integer. + * - X hexadecimal long. + * - o octal integer. + * - O octal long. + * - d decimal signed integer. + * - D decimal signed long. + * - u decimal unsigned integer. + * - U decimal unsigned long. + * - c character. + * - s string. + * . + * + * @param[in] chp pointer to a @p BaseSequentialStream implementing object + * @param[in] fmt formatting string + */ +void chprintf(BaseSequentialStream *chp, const char *fmt, ...) { + va_list ap; + char *p, *s, c, filler; + int i, precision, width; + bool_t is_long, left_align; + long l; +#if CHPRINTF_USE_FLOAT + float f; + char tmpbuf[2*MAX_FILLER + 1]; +#else + char tmpbuf[MAX_FILLER + 1]; +#endif + + va_start(ap, fmt); + while (TRUE) { + c = *fmt++; + if (c == 0) { + va_end(ap); + return; + } + if (c != '%') { + chSequentialStreamPut(chp, (uint8_t)c); + continue; + } + p = tmpbuf; + s = tmpbuf; + left_align = FALSE; + if (*fmt == '-') { + fmt++; + left_align = TRUE; + } + filler = ' '; + if ((*fmt == '.') || (*fmt == '0')) { + fmt++; + filler = '0'; + } + width = 0; + while (TRUE) { + c = *fmt++; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c == '*') + c = va_arg(ap, int); + else + break; + width = width * 10 + c; + } + precision = 0; + if (c == '.') { + while (TRUE) { + c = *fmt++; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c == '*') + c = va_arg(ap, int); + else + break; + precision *= 10; + precision += c; + } + } + /* Long modifier.*/ + if (c == 'l' || c == 'L') { + is_long = TRUE; + if (*fmt) + c = *fmt++; + } + else + is_long = (c >= 'A') && (c <= 'Z'); + + /* Command decoding.*/ + switch (c) { + case 'c': + filler = ' '; + *p++ = va_arg(ap, int); + break; + case 's': + filler = ' '; + if ((s = va_arg(ap, char *)) == 0) + s = "(null)"; + if (precision == 0) + precision = 32767; + for (p = s; *p && (--precision >= 0); p++) + ; + break; + case 'D': + case 'd': + case 'I': + case 'i': + if (is_long) + l = va_arg(ap, long); + else + l = va_arg(ap, int); + if (l < 0) { + *p++ = '-'; + l = -l; + } + p = ltoa(p, l, 10); + break; +#if CHPRINTF_USE_FLOAT + case 'f': + f = (float) va_arg(ap, double); + if (f < 0) { + *p++ = '-'; + f = -f; + } + p = ftoa(p, f); + break; +#endif + case 'X': + case 'x': + c = 16; + goto unsigned_common; + case 'U': + case 'u': + c = 10; + goto unsigned_common; + case 'O': + case 'o': + c = 8; +unsigned_common: + if (is_long) + l = va_arg(ap, unsigned long); + else + l = va_arg(ap, unsigned int); + p = ltoa(p, l, c); + break; + default: + *p++ = c; + break; + } + i = (int)(p - s); + if ((width -= i) < 0) + width = 0; + if (left_align == FALSE) + width = -width; + if (width < 0) { + if (*s == '-' && filler == '0') { + chSequentialStreamPut(chp, (uint8_t)*s++); + i--; + } + do + chSequentialStreamPut(chp, (uint8_t)filler); + while (++width != 0); + } + while (--i >= 0) + chSequentialStreamPut(chp, (uint8_t)*s++); + + while (width) { + chSequentialStreamPut(chp, (uint8_t)filler); + width--; + } + } +} + +/** @} */ diff --git a/os/various/chprintf.h b/os/various/chprintf.h new file mode 100644 index 000000000..1d758f680 --- /dev/null +++ b/os/various/chprintf.h @@ -0,0 +1,45 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file chprintf.h + * @brief Mini printf-like functionality. + * + * @addtogroup chprintf + * @{ + */ + +#ifndef _CHPRINTF_H_ +#define _CHPRINTF_H_ + +/** + * @brief Float type support. + */ +#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__) +#define CHPRINTF_USE_FLOAT FALSE +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void chprintf(BaseSequentialStream *chp, const char *fmt, ...); +#ifdef __cplusplus +} +#endif + +#endif /* _CHPRINTF_H_ */ + +/** @} */ diff --git a/os/various/chrtclib.c b/os/various/chrtclib.c new file mode 100644 index 000000000..f8a6a86ff --- /dev/null +++ b/os/various/chrtclib.c @@ -0,0 +1,359 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file chrtclib.c + * @brief RTC time conversion utilities code. + * + * @addtogroup chrtclib + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "chrtclib.h" + +#if (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || \ + defined(STM32F30X) || defined(STM32F37X) || \ + defined(STM32F1XX) || defined(STM32F10X_MD) || defined(STM32F10X_LD) || \ + defined(STM32F10X_HD) || defined(LPC122X) || defined(__DOXYGEN__)) +#if STM32_RTC_IS_CALENDAR +/** + * @brief Converts from STM32 BCD to canonicalized time format. + * + * @param[out] timp pointer to a @p tm structure as defined in time.h + * @param[in] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +static void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec) { + uint32_t tv_time = timespec->tv_time; + uint32_t tv_date = timespec->tv_date; + +#if CH_DBG_ENABLE_CHECKS + timp->tm_isdst = 0; + timp->tm_wday = 0; + timp->tm_mday = 0; + timp->tm_yday = 0; + timp->tm_mon = 0; + timp->tm_year = 0; + timp->tm_sec = 0; + timp->tm_min = 0; + timp->tm_hour = 0; +#endif + + timp->tm_isdst = -1; + + timp->tm_wday = (tv_date & RTC_DR_WDU) >> RTC_DR_WDU_OFFSET; + if (timp->tm_wday == 7) + timp->tm_wday = 0; + + timp->tm_mday = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET; + timp->tm_mday += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10; + + timp->tm_mon = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET; + timp->tm_mon += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10; + timp->tm_mon -= 1; + + timp->tm_year = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET; + timp->tm_year += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10; + timp->tm_year += 2000 - 1900; + + timp->tm_sec = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET; + timp->tm_sec += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10; + + timp->tm_min = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET; + timp->tm_min += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10; + + timp->tm_hour = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET; + timp->tm_hour += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10; + timp->tm_hour += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET); +} + +/** + * @brief Converts from canonicalized to STM32 BCD time format. + * + * @param[in] timp pointer to a @p tm structure as defined in time.h + * @param[out] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +static void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec) { + uint32_t v = 0; + + timespec->tv_date = 0; + timespec->tv_time = 0; + + v = timp->tm_year - 100; + timespec->tv_date |= ((v / 10) << RTC_DR_YT_OFFSET) & RTC_DR_YT; + timespec->tv_date |= (v % 10) << RTC_DR_YU_OFFSET; + + if (timp->tm_wday == 0) + v = 7; + else + v = timp->tm_wday; + timespec->tv_date |= (v << RTC_DR_WDU_OFFSET) & RTC_DR_WDU; + + v = timp->tm_mon + 1; + timespec->tv_date |= ((v / 10) << RTC_DR_MT_OFFSET) & RTC_DR_MT; + timespec->tv_date |= (v % 10) << RTC_DR_MU_OFFSET; + + v = timp->tm_mday; + timespec->tv_date |= ((v / 10) << RTC_DR_DT_OFFSET) & RTC_DR_DT; + timespec->tv_date |= (v % 10) << RTC_DR_DU_OFFSET; + + v = timp->tm_hour; + timespec->tv_time |= ((v / 10) << RTC_TR_HT_OFFSET) & RTC_TR_HT; + timespec->tv_time |= (v % 10) << RTC_TR_HU_OFFSET; + + v = timp->tm_min; + timespec->tv_time |= ((v / 10) << RTC_TR_MNT_OFFSET) & RTC_TR_MNT; + timespec->tv_time |= (v % 10) << RTC_TR_MNU_OFFSET; + + v = timp->tm_sec; + timespec->tv_time |= ((v / 10) << RTC_TR_ST_OFFSET) & RTC_TR_ST; + timespec->tv_time |= (v % 10) << RTC_TR_SU_OFFSET; +} + +/** + * @brief Gets raw time from RTC and converts it to canonicalized format. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timp pointer to a @p tm structure as defined in time.h + * + * @api + */ +void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) { +#if STM32_RTC_HAS_SUBSECONDS + RTCTime timespec = {0,0,FALSE,0}; +#else + RTCTime timespec = {0,0,FALSE}; +#endif + + rtcGetTime(rtcp, ×pec); + stm32_rtc_bcd2tm(timp, ×pec); +} + +/** + * @brief Sets RTC time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timp pointer to a @p tm structure as defined in time.h + * + * @api + */ +void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) { +#if STM32_RTC_HAS_SUBSECONDS + RTCTime timespec = {0,0,FALSE,0}; +#else + RTCTime timespec = {0,0,FALSE}; +#endif + + stm32_rtc_tm2bcd(timp, ×pec); + rtcSetTime(rtcp, ×pec); +} + +/** + * @brief Gets raw time from RTC and converts it to unix format. + * + * @param[in] rtcp pointer to RTC driver structure + * @return Unix time value in seconds. + * + * @api + */ +time_t rtcGetTimeUnixSec(RTCDriver *rtcp) { +#if STM32_RTC_HAS_SUBSECONDS + RTCTime timespec = {0,0,FALSE,0}; +#else + RTCTime timespec = {0,0,FALSE}; +#endif + struct tm timp; + + rtcGetTime(rtcp, ×pec); + stm32_rtc_bcd2tm(&timp, ×pec); + + return mktime(&timp); +} + +/** + * @brief Sets RTC time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] tv_sec time specification + * @return Unix time value in seconds. + * + * @api + */ +void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) { +#if STM32_RTC_HAS_SUBSECONDS + RTCTime timespec = {0,0,FALSE,0}; +#else + RTCTime timespec = {0,0,FALSE}; +#endif + struct tm timp; + + localtime_r(&tv_sec, &timp); + stm32_rtc_tm2bcd(&timp, ×pec); + rtcSetTime(rtcp, ×pec); +} + +/** + * @brief Gets raw time from RTC and converts it to unix format. + * + * @param[in] rtcp pointer to RTC driver structure + * @return Unix time value in microseconds. + * + * @api + */ +uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) { +#if STM32_RTC_HAS_SUBSECONDS + uint64_t result = 0; + RTCTime timespec = {0,0,FALSE,0}; + struct tm timp; + + rtcGetTime(rtcp, ×pec); + stm32_rtc_bcd2tm(&timp, ×pec); + + result = (uint64_t)mktime(&timp) * 1000000; + return result + timespec.tv_msec * 1000; +#else + return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000; +#endif +} + +#else /* STM32_RTC_IS_CALENDAR */ +/** + * @brief Gets raw time from RTC and converts it to canonicalized format. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timp pointer to a @p tm structure as defined in time.h + * + * @api + */ +void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) { + RTCTime timespec = {0}; + + rtcGetTime(rtcp, ×pec); + localtime_r((time_t *)&(timespec.tv_sec), timp); +} + +/** + * @brief Sets RTC time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timp pointer to a @p tm structure as defined in time.h + * + * @api + */ +void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) { + RTCTime timespec = {0}; + + timespec.tv_sec = mktime(timp); +#if !defined(LPC122X) + timespec.tv_msec = 0; +#endif + rtcSetTime(rtcp, ×pec); +} + +/** + * @brief Gets raw time from RTC and converts it to unix format. + * + * @param[in] rtcp pointer to RTC driver structure + * @return Unix time value in seconds. + * + * @api + */ +time_t rtcGetTimeUnixSec(RTCDriver *rtcp) { + RTCTime timespec = {0}; + + rtcGetTime(rtcp, ×pec); + return timespec.tv_sec; +} + +/** + * @brief Sets RTC time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] tv_sec time specification + * @return Unix time value in seconds. + * + * @api + */ +void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) { + RTCTime timespec = {0}; + + timespec.tv_sec = tv_sec; +#if !defined(LPC122X) + timespec.tv_msec = 0; +#endif + rtcSetTime(rtcp, ×pec); +} + +/** + * @brief Gets raw time from RTC and converts it to unix format. + * + * @param[in] rtcp pointer to RTC driver structure + * @return Unix time value in microseconds. + * + * @api + */ +uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) { +#if STM32_RTC_HAS_SUBSECONDS + uint64_t result = 0; + RTCTime timespec = {0,0}; + + rtcGetTime(rtcp, ×pec); + result = (uint64_t)timespec.tv_sec * 1000000; + return result + timespec.tv_msec * 1000; +#else + return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000; +#endif +} + +/** + * @brief Get current time in format suitable for usage in FatFS. + * + * @param[in] rtcp pointer to RTC driver structure + * @return FAT time value. + * + * @api + */ +uint32_t rtcGetTimeFatFromCounter(RTCDriver *rtcp) { + uint32_t fattime; + struct tm timp; + + rtcGetTimeTm(rtcp, &timp); + + fattime = (timp.tm_sec) >> 1; + fattime |= (timp.tm_min) << 5; + fattime |= (timp.tm_hour) << 11; + fattime |= (timp.tm_mday) << 16; + fattime |= (timp.tm_mon + 1) << 21; + fattime |= (timp.tm_year - 80) << 25; + + return fattime; +} +#endif /* STM32_RTC_IS_CALENDAR */ +#endif /* (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || defined(STM32F1XX)) */ + +/** @} */ diff --git a/os/various/chrtclib.h b/os/various/chrtclib.h new file mode 100644 index 000000000..895abc1a7 --- /dev/null +++ b/os/various/chrtclib.h @@ -0,0 +1,55 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file chrtclib.h + * @brief RTC time conversion utilities header. + * + * @addtogroup chrtclib + * @{ + */ + +#ifndef CHRTCLIB_H_ +#define CHRTCLIB_H_ + +#include + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#if !STM32_RTC_IS_CALENDAR + uint32_t rtcGetTimeFat(RTCDriver *rtcp); +#endif + void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp); + void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp); + time_t rtcGetTimeUnixSec(RTCDriver *rtcp); + uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp); + void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* CHRTCLIB_H_ */ + +/** @} */ diff --git a/os/various/cpp_wrappers/ch.cpp b/os/various/cpp_wrappers/ch.cpp new file mode 100644 index 000000000..5f2621a61 --- /dev/null +++ b/os/various/cpp_wrappers/ch.cpp @@ -0,0 +1,866 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/** + * @file ch.cpp + * @brief C++ wrapper code. + * + * @addtogroup cpp_library + * @{ + */ + +#include "ch.hpp" + +namespace chibios_rt { + + /*------------------------------------------------------------------------* + * chibios_rt::System * + *------------------------------------------------------------------------*/ + void System::init(void) { + + chSysInit(); + } + + void System::lock(void) { + + chSysLock(); + } + + void System::unlock(void) { + + chSysUnlock(); + } + + void System::lockFromIsr(void) { + + chSysLockFromIsr(); + } + + void System::unlockFromIsr(void) { + + chSysUnlockFromIsr(); + } + + systime_t System::getTime(void) { + + return chTimeNow(); + } + + bool System::isTimeWithin(systime_t start, systime_t end) { + + return (bool)chTimeIsWithin(start, end); + } + + /*------------------------------------------------------------------------* + * chibios_rt::Core * + *------------------------------------------------------------------------*/ + void *Core::alloc(size_t size) { + + return chCoreAlloc(size); + } + + void *Core::allocI(size_t size) { + + return chCoreAllocI(size); + } + + size_t Core::getStatus(void) { + + return chCoreStatus(); + } + + /*------------------------------------------------------------------------* + * chibios_rt::Timer * + *------------------------------------------------------------------------*/ + void Timer::setI(systime_t time, vtfunc_t vtfunc, void *par) { + + chVTSetI(&timer_ref, time, vtfunc, par); + } + + void Timer::resetI() { + + if (chVTIsArmedI(&timer_ref)) + chVTResetI(&timer_ref); + } + + bool Timer::isArmedI(void) { + + return (bool)chVTIsArmedI(&timer_ref); + } + + /*------------------------------------------------------------------------* + * chibios_rt::ThreadReference * + *------------------------------------------------------------------------*/ + + void ThreadReference::stop(void) { + + chDbgPanic("invoked unimplemented method stop()"); + } + + msg_t ThreadReference::suspend(void) { + msg_t msg; + + chSysLock(); + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #1", + "already referenced"); + + thread_ref = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + msg = thread_ref->p_u.rdymsg; + + chSysUnlock(); + return msg; + } + + msg_t ThreadReference::suspendS(void) { + + chDbgAssert(thread_ref == NULL, + "ThreadReference, #2", + "already referenced"); + + thread_ref = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + return thread_ref->p_u.rdymsg; + } + + void ThreadReference::resume(msg_t msg) { + + chSysLock() + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #3", + "not referenced"); + + if (thread_ref) { + Thread *tp = thread_ref; + thread_ref = NULL; + chSchWakeupS(tp, msg); + } + + chSysUnlock(); + } + + void ThreadReference::resumeI(msg_t msg) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #4", + "not referenced"); + + if (thread_ref) { + Thread *tp = thread_ref; + thread_ref = NULL; + tp->p_msg = msg; + chSchReadyI(tp); + } + } + + void ThreadReference::requestTerminate(void) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #5", + "not referenced"); + + chThdTerminate(thread_ref); + } + +#if CH_USE_WAITEXIT + msg_t ThreadReference::wait(void) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #6", + "not referenced"); + + msg_t msg = chThdWait(thread_ref); + thread_ref = NULL; + return msg; + } +#endif /* CH_USE_WAITEXIT */ + +#if CH_USE_MESSAGES + msg_t ThreadReference::sendMessage(msg_t msg) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #7", + "not referenced"); + + return chMsgSend(thread_ref, msg); + } + + bool ThreadReference::isPendingMessage(void) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #7", + "not referenced"); + + return (bool)chMsgIsPendingI(thread_ref); + } + + msg_t ThreadReference::getMessage(void) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #8", + "not referenced"); + + return chMsgGet(thread_ref); + } + + void ThreadReference::releaseMessage(msg_t msg) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #9", + "not referenced"); + + chMsgRelease(thread_ref, msg); + } +#endif /* CH_USE_MESSAGES */ + +#if CH_USE_EVENTS + void ThreadReference::signalEvents(eventmask_t mask) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #10", + "not referenced"); + + chEvtSignal(thread_ref, mask); + } + + void ThreadReference::signalEventsI(eventmask_t mask) { + + chDbgAssert(thread_ref != NULL, + "ThreadReference, #11", + "not referenced"); + + chEvtSignalI(thread_ref, mask); + } +#endif /* CH_USE_EVENTS */ + +#if CH_USE_DYNAMIC +#endif /* CH_USE_DYNAMIC */ + + /*------------------------------------------------------------------------* + * chibios_rt::BaseThread * + *------------------------------------------------------------------------*/ + BaseThread::BaseThread() : ThreadReference(NULL) { + + } + + msg_t BaseThread::main(void) { + + return 0; + } + + ThreadReference BaseThread::start(tprio_t prio) { + + (void)prio; + + return *this; + }; + + msg_t _thd_start(void *arg) { + + return ((BaseThread *)arg)->main(); + } + + void BaseThread::setName(const char *tname) { + + chRegSetThreadName(tname); + } + + tprio_t BaseThread::setPriority(tprio_t newprio) { + + return chThdSetPriority(newprio); + } + + void BaseThread::exit(msg_t msg) { + + chThdExit(msg); + } + + void BaseThread::exitS(msg_t msg) { + + chThdExitS(msg); + } + + bool BaseThread::shouldTerminate(void) { + + return (bool)chThdShouldTerminate(); + } + + void BaseThread::sleep(systime_t interval){ + + chThdSleep(interval); + } + + void BaseThread::sleepUntil(systime_t time) { + + chThdSleepUntil(time); + } + + void BaseThread::yield(void) { + + chThdYield(); + } + +#if CH_USE_MESSAGES + ThreadReference BaseThread::waitMessage(void) { + + ThreadReference tr(chMsgWait()); + return tr; + } +#endif /* CH_USE_MESSAGES */ + +#if CH_USE_EVENTS + eventmask_t BaseThread::getAndClearEvents(eventmask_t mask) { + + return chEvtGetAndClearEvents(mask); + } + + eventmask_t BaseThread::addEvents(eventmask_t mask) { + + return chEvtAddEvents(mask); + } + + eventmask_t BaseThread::waitOneEvent(eventmask_t ewmask) { + + return chEvtWaitOne(ewmask); + } + + eventmask_t BaseThread::waitAnyEvent(eventmask_t ewmask) { + + return chEvtWaitAny(ewmask); + } + + eventmask_t BaseThread::waitAllEvents(eventmask_t ewmask) { + + return chEvtWaitAll(ewmask); + } + +#if CH_USE_EVENTS_TIMEOUT + eventmask_t BaseThread::waitOneEventTimeout(eventmask_t ewmask, + systime_t time) { + + return chEvtWaitOneTimeout(ewmask, time); + } + + eventmask_t BaseThread::waitAnyEventTimeout(eventmask_t ewmask, + systime_t time) { + + return chEvtWaitAnyTimeout(ewmask, time); + } + + eventmask_t BaseThread::waitAllEventsTimeout(eventmask_t ewmask, + systime_t time) { + + return chEvtWaitAllTimeout(ewmask, time); + } +#endif /* CH_USE_EVENTS_TIMEOUT */ + + void BaseThread::dispatchEvents(const evhandler_t handlers[], + eventmask_t mask) { + + chEvtDispatch(handlers, mask); + } +#endif /* CH_USE_EVENTS */ + +#if CH_USE_MUTEXES + void BaseThread::unlockMutex(void) { + + chMtxUnlock(); + } + + void BaseThread::unlockMutexS(void) { + + chMtxUnlockS(); + } + + void BaseThread::unlockAllMutexes(void) { + + chMtxUnlockAll(); + } +#endif /* CH_USE_MUTEXES */ + +#if CH_USE_SEMAPHORES + /*------------------------------------------------------------------------* + * chibios_rt::CounterSemaphore * + *------------------------------------------------------------------------*/ + CounterSemaphore::CounterSemaphore(cnt_t n) { + + chSemInit(&sem, n); + } + + void CounterSemaphore::reset(cnt_t n) { + + chSemReset(&sem, n); + } + + void CounterSemaphore::resetI(cnt_t n) { + + chSemResetI(&sem, n); + } + + msg_t CounterSemaphore::wait(void) { + + return chSemWait(&sem); + } + + msg_t CounterSemaphore::waitS(void) { + + return chSemWaitS(&sem); + } + + msg_t CounterSemaphore::waitTimeout(systime_t time) { + + return chSemWaitTimeout(&sem, time); + } + + msg_t CounterSemaphore::waitTimeoutS(systime_t time) { + + return chSemWaitTimeoutS(&sem, time); + } + + void CounterSemaphore::signal(void) { + + chSemSignal(&sem); + } + + void CounterSemaphore::signalI(void) { + + chSemSignalI(&sem); + } + + void CounterSemaphore::addCounterI(cnt_t n) { + + chSemAddCounterI(&sem, n); + } + + cnt_t CounterSemaphore::getCounterI(void) { + + return chSemGetCounterI(&sem); + } + +#if CH_USE_SEMSW + msg_t CounterSemaphore::signalWait(CounterSemaphore *ssem, + CounterSemaphore *wsem) { + + return chSemSignalWait(&ssem->sem, &wsem->sem); + } +#endif /* CH_USE_SEMSW */ + + /*------------------------------------------------------------------------* + * chibios_rt::BinarySemaphore * + *------------------------------------------------------------------------*/ + BinarySemaphore::BinarySemaphore(bool taken) { + + chBSemInit(&bsem, (bool_t)taken); + } + + msg_t BinarySemaphore::wait(void) { + + return chBSemWait(&bsem); + } + + msg_t BinarySemaphore::waitS(void) { + + return chBSemWaitS(&bsem); + } + + msg_t BinarySemaphore::waitTimeout(systime_t time) { + + return chBSemWaitTimeout(&bsem, time); + } + + msg_t BinarySemaphore::waitTimeoutS(systime_t time) { + + return chBSemWaitTimeoutS(&bsem, time); + } + + void BinarySemaphore::reset(bool taken) { + + chBSemReset(&bsem, (bool_t)taken); + } + + void BinarySemaphore::resetI(bool taken) { + + chBSemResetI(&bsem, (bool_t)taken); + } + + void BinarySemaphore::signal(void) { + + chBSemSignal(&bsem); + } + + void BinarySemaphore::signalI(void) { + + chBSemSignalI(&bsem); + } + + bool BinarySemaphore::getStateI(void) { + + return (bool)chBSemGetStateI(&bsem); + } +#endif /* CH_USE_SEMAPHORES */ + +#if CH_USE_MUTEXES + /*------------------------------------------------------------------------* + * chibios_rt::Mutex * + *------------------------------------------------------------------------*/ + Mutex::Mutex(void) { + + chMtxInit(&mutex); + } + + bool Mutex::tryLock(void) { + + return chMtxTryLock(&mutex); + } + + bool Mutex::tryLockS(void) { + + return chMtxTryLockS(&mutex); + } + + void Mutex::lock(void) { + + chMtxLock(&mutex); + } + + void Mutex::lockS(void) { + + chMtxLockS(&mutex); + } + +#if CH_USE_CONDVARS + /*------------------------------------------------------------------------* + * chibios_rt::CondVar * + *------------------------------------------------------------------------*/ + CondVar::CondVar(void) { + + chCondInit(&condvar); + } + + void CondVar::signal(void) { + + chCondSignal(&condvar); + } + + void CondVar::signalI(void) { + + chCondSignalI(&condvar); + } + + void CondVar::broadcast(void) { + + chCondBroadcast(&condvar); + } + + void CondVar::broadcastI(void) { + + chCondBroadcastI(&condvar); + } + + msg_t CondVar::wait(void) { + + return chCondWait(&condvar); + } + + msg_t CondVar::waitS(void) { + + return chCondWaitS(&condvar); + } + +#if CH_USE_CONDVARS_TIMEOUT + msg_t CondVar::waitTimeout(systime_t time) { + + return chCondWaitTimeout(&condvar, time); + } +#endif /* CH_USE_CONDVARS_TIMEOUT */ +#endif /* CH_USE_CONDVARS */ +#endif /* CH_USE_MUTEXES */ + +#if CH_USE_EVENTS + /*------------------------------------------------------------------------* + * chibios_rt::EvtListener * + *------------------------------------------------------------------------*/ + flagsmask_t EvtListener::getAndClearFlags(void) { + + return chEvtGetAndClearFlags(&ev_listener); + } + + flagsmask_t EvtListener::getAndClearFlagsI(void) { + + return chEvtGetAndClearFlagsI(&ev_listener); + } + + /*------------------------------------------------------------------------* + * chibios_rt::EvtSource * + *------------------------------------------------------------------------*/ + EvtSource::EvtSource(void) { + + chEvtInit(&ev_source); + } + + void EvtSource::registerOne(chibios_rt::EvtListener *elp, + eventid_t eid) { + + chEvtRegister(&ev_source, &elp->ev_listener, eid); + } + + void EvtSource::registerMask(chibios_rt::EvtListener *elp, + eventmask_t emask) { + + chEvtRegisterMask(&ev_source, &elp->ev_listener, emask); + } + + void EvtSource::unregister(chibios_rt::EvtListener *elp) { + + chEvtUnregister(&ev_source, &elp->ev_listener); + } + + void EvtSource::broadcastFlags(flagsmask_t flags) { + + chEvtBroadcastFlags(&ev_source, flags); + } + + void EvtSource::broadcastFlagsI(flagsmask_t flags) { + + chEvtBroadcastFlagsI(&ev_source, flags); + } +#endif /* CH_USE_EVENTS */ + +#if CH_USE_QUEUES + /*------------------------------------------------------------------------* + * chibios_rt::InQueue * + *------------------------------------------------------------------------*/ + InQueue::InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link) { + + chIQInit(&iq, bp, size, infy, link); + } + + size_t InQueue::getFullI(void) { + + return chIQGetFullI(&iq); + } + + size_t InQueue::getEmptyI(void) { + + return chIQGetEmptyI(&iq); + } + + bool InQueue::isEmptyI(void) { + + return (bool)chIQIsEmptyI(&iq); + } + + bool InQueue::isFullI(void) { + + return (bool)chIQIsFullI(&iq); + } + + void InQueue::resetI(void) { + + chIQResetI(&iq); + } + + msg_t InQueue::putI(uint8_t b) { + + return chIQPutI(&iq, b); + } + + msg_t InQueue::get() { + + return chIQGet(&iq); + } + + msg_t InQueue::getTimeout(systime_t time) { + + return chIQGetTimeout(&iq, time); + } + + size_t InQueue::readTimeout(uint8_t *bp, size_t n, systime_t time) { + + return chIQReadTimeout(&iq, bp, n, time); + } + + /*------------------------------------------------------------------------* + * chibios_rt::OutQueue * + *------------------------------------------------------------------------*/ + OutQueue::OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link) { + + chOQInit(&oq, bp, size, onfy, link); + } + + size_t OutQueue::getFullI(void) { + + return chOQGetFullI(&oq); + } + + size_t OutQueue::getEmptyI(void) { + + return chOQGetEmptyI(&oq); + } + + bool OutQueue::isEmptyI(void) { + + return (bool)chOQIsEmptyI(&oq); + } + + bool OutQueue::isFullI(void) { + + return (bool)chOQIsFullI(&oq); + } + + void OutQueue::resetI(void) { + + chOQResetI(&oq); + } + + msg_t OutQueue::put(uint8_t b) { + + return chOQPut(&oq, b); + } + + msg_t OutQueue::putTimeout(uint8_t b, systime_t time) { + + return chOQPutTimeout(&oq, b, time); + } + + msg_t OutQueue::getI(void) { + + return chOQGetI(&oq); + } + + size_t OutQueue::writeTimeout(const uint8_t *bp, size_t n, + systime_t time) { + + return chOQWriteTimeout(&oq, bp, n, time); + } +#endif /* CH_USE_QUEUES */ + +#if CH_USE_MAILBOXES + /*------------------------------------------------------------------------* + * chibios_rt::Mailbox * + *------------------------------------------------------------------------*/ + Mailbox::Mailbox(msg_t *buf, cnt_t n) { + + chMBInit(&mb, buf, n); + } + + void Mailbox::reset(void) { + + chMBReset(&mb); + } + + msg_t Mailbox::post(msg_t msg, systime_t time) { + + return chMBPost(&mb, msg, time); + } + + msg_t Mailbox::postS(msg_t msg, systime_t time) { + + return chMBPostS(&mb, msg, time); + } + + msg_t Mailbox::postI(msg_t msg) { + + return chMBPostI(&mb, msg); + } + + msg_t Mailbox::postAhead(msg_t msg, systime_t time) { + + return chMBPostAhead(&mb, msg, time); + } + + msg_t Mailbox::postAheadS(msg_t msg, systime_t time) { + + return chMBPostAheadS(&mb, msg, time); + } + + msg_t Mailbox::postAheadI(msg_t msg) { + + return chMBPostAheadI(&mb, msg); + } + + msg_t Mailbox::fetch(msg_t *msgp, systime_t time) { + + return chMBFetch(&mb, msgp, time); + } + + msg_t Mailbox::fetchS(msg_t *msgp, systime_t time) { + + return chMBFetchS(&mb, msgp, time); + } + + msg_t Mailbox::fetchI(msg_t *msgp) { + + return chMBFetchI(&mb, msgp); + } + + cnt_t Mailbox::getFreeCountI(void) { + + return chMBGetFreeCountI(&mb); + } + + cnt_t Mailbox::getUsedCountI(void) { + + return chMBGetUsedCountI(&mb); + } +#endif /* CH_USE_MAILBOXES */ + +#if CH_USE_MEMPOOLS + /*------------------------------------------------------------------------* + * chibios_rt::MemoryPool * + *------------------------------------------------------------------------*/ + MemoryPool::MemoryPool(size_t size, memgetfunc_t provider) { + + chPoolInit(&pool, size, provider); + } + + MemoryPool::MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n) { + + chPoolInit(&pool, size, provider); + chPoolLoadArray(&pool, p, n); + } + + + void MemoryPool::loadArray(void *p, size_t n) { + + chPoolLoadArray(&pool, p, n); + } + + void *MemoryPool::allocI(void) { + + return chPoolAllocI(&pool); + } + + void *MemoryPool::alloc(void) { + + return chPoolAlloc(&pool); + } + + void MemoryPool::free(void *objp) { + + chPoolFree(&pool, objp); + } + + void MemoryPool::freeI(void *objp) { + + chPoolFreeI(&pool, objp); + } +#endif /* CH_USE_MEMPOOLS */ +} + +/** @} */ diff --git a/os/various/cpp_wrappers/ch.hpp b/os/various/cpp_wrappers/ch.hpp new file mode 100644 index 000000000..2bc70b55b --- /dev/null +++ b/os/various/cpp_wrappers/ch.hpp @@ -0,0 +1,2282 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ch.hpp + * @brief C++ wrapper classes and definitions. + * + * @addtogroup cpp_library + * @{ + */ + +#include + +#ifndef _CH_HPP_ +#define _CH_HPP_ + +/** + * @brief ChibiOS kernel-related classes and interfaces. + */ +namespace chibios_rt { + + /*------------------------------------------------------------------------* + * chibios_rt::System * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating the base system functionalities. + */ + class System { + public: + /** + * @brief ChibiOS/RT initialization. + * @details After executing this function the current instructions stream + * becomes the main thread. + * @pre Interrupts must be still disabled when @p chSysInit() is invoked + * and are internally enabled. + * @post The main thread is created with priority @p NORMALPRIO. + * @note This function has special, architecture-dependent, requirements, + * see the notes into the various port reference manuals. + * + * @special + */ + static void init(void); + + /** + * @brief Enters the kernel lock mode. + * + * @special + */ + static void lock(void); + + /** + * @brief Leaves the kernel lock mode. + * + * @special + */ + static void unlock(void); + + /** + * @brief Enters the kernel lock mode from within an interrupt handler. + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
    + * It is good practice to invoke this API before invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ + static void lockFromIsr(void); + + /** + * @brief Leaves the kernel lock mode from within an interrupt handler. + * + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
    + * It is good practice to invoke this API after invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ + static void unlockFromIsr(void); + + + /** + * @brief Returns the system time as system ticks. + * @note The system tick time interval is implementation dependent. + * + * @return The system time. + * + * @api + */ + static systime_t getTime(void); + + /** + * @brief Checks if the current system time is within the specified time + * window. + * @note When start==end then the function returns always true because the + * whole time range is specified. + * + * @param[in] start the start of the time window (inclusive) + * @param[in] end the end of the time window (non inclusive) + * @retval true current time within the specified time window. + * @retval false current time not within the specified time window. + * + * @api + */ + static bool isTimeWithin(systime_t start, systime_t end); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::System * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating the base system functionalities. + */ + class Core { + public: + + /** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less + * than MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @api + */ + static void *alloc(size_t size); + + /** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less than + * MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated. + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @iclass + */ + static void *allocI(size_t size); + + /** + * @brief Core memory status. + * + * @return The size, in bytes, of the free core memory. + * + * @api + */ + static size_t getStatus(void); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::Timer * + *------------------------------------------------------------------------*/ + /** + * @brief Timer class. + */ + class Timer { + public: + /** + * @brief Embedded @p VirtualTimer structure. + */ + ::VirtualTimer timer_ref; + + /** + * @brief Enables a virtual timer. + * @note The associated function is invoked from interrupt context. + * + * @param[in] time the number of ticks before the operation timeouts, + * the special values are handled as follow: + * - @a TIME_INFINITE is allowed but interpreted as a + * normal time specification. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @param[in] vtfunc the timer callback function. After invoking the + * callback the timer is disabled and the structure + * can be disposed or reused. + * @param[in] par a parameter that will be passed to the callback + * function + * + * @iclass + */ + void setI(systime_t time, vtfunc_t vtfunc, void *par); + + /** + * @brief Resets the timer, if armed. + * + * @iclass + */ + void resetI(); + + /** + * @brief Returns the timer status. + * + * @retval TRUE The timer is armed. + * @retval FALSE The timer already fired its callback. + * + * @iclass + */ + bool isArmedI(void); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::ThreadReference * + *------------------------------------------------------------------------*/ + /** + * @brief Thread reference class. + * @details This class encapsulates a reference to a system thread. All + * operations involving another thread are performed through + * an object of this type. + */ + class ThreadReference { + public: + /** + * @brief Pointer to the system thread. + */ + ::Thread *thread_ref; + + /** + * @brief Thread reference constructor. + * + * @param[in] tp the target thread. This parameter can be + * @p NULL if the thread is not known at + * creation time. + * + * @init + */ + ThreadReference(Thread *tp) : thread_ref(tp) { + + }; + + /** + * @brief Stops the thread. + * @note The implementation is left to descendant classes and is + * optional. + */ + virtual void stop(void); + + /** + * @brief Suspends the current thread on the reference. + * @details The suspended thread becomes the referenced thread. It is + * possible to use this method only if the thread reference + * was set to @p NULL. + * + * @return The incoming message. + * + * @api + */ + msg_t suspend(void); + + /** + * @brief Suspends the current thread on the reference. + * @details The suspended thread becomes the referenced thread. It is + * possible to use this method only if the thread reference + * was set to @p NULL. + * + * @return The incoming message. + * + * @sclass + */ + msg_t suspendS(void); + + /** + * @brief Resumes the currently referenced thread, if any. + * + * @param[in] msg the wakeup message + * + * @api + */ + void resume(msg_t msg); + + /** + * @brief Resumes the currently referenced thread, if any. + * + * @param[in] msg the wakeup message + * + * @iclass + */ + void resumeI(msg_t msg); + + /** + * @brief Requests a thread termination. + * @pre The target thread must be written to invoke periodically + * @p chThdShouldTerminate() and terminate cleanly if it returns + * @p TRUE. + * @post The specified thread will terminate after detecting the + * termination condition. + * + * @api + */ + void requestTerminate(void); + +#if CH_USE_WAITEXIT || defined(__DOXYGEN__) + /** + * @brief Blocks the execution of the invoking thread until the specified + * thread terminates then the exit code is returned. + * @details This function waits for the specified thread to terminate then + * decrements its reference counter, if the counter reaches zero + * then the thread working area is returned to the proper + * allocator.
    + * The memory used by the exited thread is handled in different + * ways depending on the API that spawned the thread: + * - If the thread was spawned by @p chThdCreateStatic() or by + * @p chThdCreateI() then nothing happens and the thread working + * area is not released or modified in any way. This is the + * default, totally static, behavior. + * - If the thread was spawned by @p chThdCreateFromHeap() then + * the working area is returned to the system heap. + * - If the thread was spawned by @p chThdCreateFromMemoryPool() + * then the working area is returned to the owning memory pool. + * . + * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in + * order to use this function. + * @post Enabling @p chThdWait() requires 2-4 (depending on the + * architecture) extra bytes in the @p Thread structure. + * @post After invoking @p chThdWait() the thread pointer becomes + * invalid and must not be used as parameter for further system + * calls. + * @note If @p CH_USE_DYNAMIC is not specified this function just waits + * for the thread termination, no memory allocators are involved. + * + * @return The exit code from the terminated thread. + * + * @api + */ + msg_t wait(void); +#endif /* CH_USE_WAITEXIT */ + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + /** + * @brief Sends a message to the thread and returns the answer. + * + * @param[in] msg the sent message + * @return The returned message. + * + * @api + */ + msg_t sendMessage(msg_t msg); + + /** + * @brief Returns true if there is at least one message in queue. + * + * @retval true A message is waiting in queue. + * @retval false A message is not waiting in queue. + * + * @api + */ + bool isPendingMessage(void); + + /** + * @brief Returns an enqueued message or @p NULL. + * + * @return The incoming message. + * + * @api + */ + msg_t getMessage(void); + + /** + * @brief Releases the next message in queue with a reply. + * + * @param[in] msg the answer message + * + * @api + */ + void releaseMessage(msg_t msg); +#endif /* CH_USE_MESSAGES */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Adds a set of event flags directly to specified @p Thread. + * + * @param[in] mask the event flags set to be ORed + * + * @api + */ + void signalEvents(eventmask_t mask); + + /** + * @brief Adds a set of event flags directly to specified @p Thread. + * + * @param[in] mask the event flags set to be ORed + * + * @iclass + */ + void signalEventsI(eventmask_t mask); +#endif /* CH_USE_EVENTS */ + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) +#endif /* CH_USE_DYNAMIC */ + }; + + /*------------------------------------------------------------------------* + * chibios_rt::BaseThread * + *------------------------------------------------------------------------*/ + /** + * @brief Abstract base class for a ChibiOS/RT thread. + * @details The thread body is the virtual function @p Main(). + */ + class BaseThread : public ThreadReference { + public: + /** + * @brief BaseThread constructor. + * + * @init + */ + BaseThread(void); + + /** + * @brief Thread body function. + * + * @return The exit message. + * + * @api + */ + virtual msg_t main(void); + + /** + * @brief Creates and starts a system thread. + * + * @param[in] prio thread priority + * @return A reference to the created thread with + * reference counter set to one. + * + * @api + */ + virtual ThreadReference start(tprio_t prio); + + /** + * @brief Sets the current thread name. + * @pre This function only stores the pointer to the name if the option + * @p CH_USE_REGISTRY is enabled else no action is performed. + * + * @param[in] tname thread name as a zero terminated string + * + * @api + */ + static void setName(const char *tname); + + /** + * @brief Changes the running thread priority level then reschedules if + * necessary. + * @note The function returns the real thread priority regardless of the + * current priority that could be higher than the real priority + * because the priority inheritance mechanism. + * + * @param[in] newprio the new priority level of the running thread + * @return The old priority level. + * + * @api + */ + static tprio_t setPriority(tprio_t newprio); + + /** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @api + */ + static void exit(msg_t msg); + + /** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @sclass + */ + static void exitS(msg_t msg); + + /** + * @brief Verifies if the current thread has a termination request + * pending. + * @note Can be invoked in any context. + * + * @retval TRUE termination request pending. + * @retval FALSE termination request not pending. + * + * @special + */ + static bool shouldTerminate(void); + + /** + * @brief Suspends the invoking thread for the specified time. + * + * @param[in] interval the delay in system ticks, the special values are + * handled as follow: + * - @a TIME_INFINITE the thread enters an infinite + * sleep state. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * + * @api + */ + static void sleep(systime_t interval); + + /** + * @brief Suspends the invoking thread until the system time arrives to + * the specified value. + * + * @param[in] time absolute system time + * + * @api + */ + static void sleepUntil(systime_t time); + + /** + * @brief Yields the time slot. + * @details Yields the CPU control to the next thread in the ready list + * with equal priority, if any. + * + * @api + */ + static void yield(void); + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + /** + * @brief Waits for a message. + * + * @return The sender thread. + * + * @api + */ + static ThreadReference waitMessage(void); +#endif /* CH_USE_MESSAGES */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Clears the pending events specified in the mask. + * + * @param[in] mask the events to be cleared + * @return The pending events that were cleared. + * + * @api + */ + static eventmask_t getAndClearEvents(eventmask_t mask); + + /** + * @brief Adds (OR) a set of event flags on the current thread, this is + * @b much faster than using @p chEvtBroadcast() or + * @p chEvtSignal(). + * + * @param[in] mask the event flags to be added + * @return The current pending events mask. + * + * @api + */ + static eventmask_t addEvents(eventmask_t mask); + + /** + * @brief Waits for a single event. + * @details A pending event among those specified in @p ewmask is selected, + * cleared and its mask returned. + * @note One and only one event is served in the function, the one with + * the lowest event id. The function is meant to be invoked into + * a loop in order to serve all the pending events.
    + * This means that Event Listeners with a lower event identifier + * have an higher priority. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @return The mask of the lowest id served and cleared + * event. + * + * @api + */ + static eventmask_t waitOneEvent(eventmask_t ewmask); + + /** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p ewmask to become pending then the events are cleared and + * returned. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @return The mask of the served and cleared events. + * + * @api + */ + static eventmask_t waitAnyEvent(eventmask_t ewmask); + + /** + * @brief Waits for all the specified event flags then clears them. + * @details The function waits for all the events specified in @p ewmask + * to become pending then the events are cleared and returned. + * + * @param[in] ewmask mask of the event ids that the function should + * wait for + * @return The mask of the served and cleared events. + * + * @api + */ + static eventmask_t waitAllEvents(eventmask_t ewmask); + +#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) + /** + * @brief Waits for a single event. + * @details A pending event among those specified in @p ewmask is selected, + * cleared and its mask returned. + * @note One and only one event is served in the function, the one with + * the lowest event id. The function is meant to be invoked into + * a loop in order to serve all the pending events.
    + * This means that Event Listeners with a lower event identifier + * have an higher priority. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * + * @param[in] time the number of ticks before the operation + * timouts + * @return The mask of the lowest id served and cleared + * event. + * @retval 0 if the specified timeout expired. + * + * @api + */ + static eventmask_t waitOneEventTimeout(eventmask_t ewmask, + systime_t time); + + /** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p ewmask to become pending then the events are cleared and + * returned. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation + * timouts + * @return The mask of the served and cleared events. + * @retval 0 if the specified timeout expired. + * + * @api + */ + static eventmask_t waitAnyEventTimeout(eventmask_t ewmask, + systime_t time); + + /** + * @brief Waits for all the specified event flags then clears them. + * @details The function waits for all the events specified in @p ewmask + * to become pending then the events are cleared and returned. + * + * @param[in] ewmask mask of the event ids that the function should + * wait for + * @param[in] time the number of ticks before the operation + * timouts + * @return The mask of the served and cleared events. + * @retval 0 if the specified timeout expired. + * + * @api + */ + static eventmask_t waitAllEventsTimeout(eventmask_t ewmask, + systime_t time); +#endif /* CH_USE_EVENTS_TIMEOUT */ + + /** + * @brief Invokes the event handlers associated to an event flags mask. + * + * @param[in] mask mask of the event flags to be dispatched + * @param[in] handlers an array of @p evhandler_t. The array must have + * size equal to the number of bits in eventmask_t. + * + * @api + */ + static void dispatchEvents(const evhandler_t handlers[], + eventmask_t mask); +#endif /* CH_USE_EVENTS */ + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * + * @return A pointer to the unlocked mutex. + * + * @api + */ + static void unlockMutex(void); + + /** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. + * + * @return A pointer to the unlocked mutex. + * + * @sclass + */ + static void unlockMutexS(void); + + /** + * @brief Unlocks all the mutexes owned by the invoking thread. + * @post The stack of owned mutexes is emptied and all the found + * mutexes are unlocked. + * @note This function is MUCH MORE efficient than releasing the + * mutexes one by one and not just because the call overhead, + * this function does not have any overhead related to the + * priority inheritance mechanism. + * + * @api + */ + static void unlockAllMutexes(void); +#endif /* CH_USE_MUTEXES */ + }; + + /*------------------------------------------------------------------------* + * chibios_rt::BaseStaticThread * + *------------------------------------------------------------------------*/ + /** + * @brief Static threads template class. + * @details This class introduces static working area allocation. + * + * @param N the working area size for the thread class + */ + template + class BaseStaticThread : public BaseThread { + protected: + WORKING_AREA(wa, N); + + public: + /** + * @brief Thread constructor. + * @details The thread object is initialized but the thread is not + * started here. + * + * @init + */ + BaseStaticThread(void) : BaseThread() { + + } + + /** + * @brief Creates and starts a system thread. + * + * @param[in] prio thread priority + * @return A reference to the created thread with + * reference counter set to one. + * + * @api + */ + virtual ThreadReference start(tprio_t prio) { + msg_t _thd_start(void *arg); + + thread_ref = chThdCreateStatic(wa, sizeof(wa), prio, _thd_start, this); + return *this; + } + }; + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::CounterSemaphore * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a semaphore. + */ + class CounterSemaphore { + public: + /** + * @brief Embedded @p ::Semaphore structure. + */ + ::Semaphore sem; + + /** + * @brief CounterSemaphore constructor. + * @details The embedded @p ::Semaphore structure is initialized. + * + * @param[in] n the semaphore counter value, must be greater + * or equal to zero + * + * @init + */ + CounterSemaphore(cnt_t n); + + /** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is + * set to the specified, non negative, value. + * @note The released threads can recognize they were waked up by a + * reset rather than a signal because the @p chSemWait() will + * return @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] n the new value of the semaphore counter. The value + * must be non-negative. + * + * @api + */ + void reset(cnt_t n); + + /** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is + * set to the specified, non negative, value. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note + * that interrupt handlers always reschedule on exit so an + * explicit reschedule must not be performed in ISRs. + * @note The released threads can recognize they were waked up by a + * reset rather than a signal because the @p chSemWait() will + * return @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] n the new value of the semaphore counter. The value + * must be non-negative. + * + * @iclass + */ + void resetI(cnt_t n); + + /** + * @brief Performs a wait operation on a semaphore. + * + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or + * the semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using + * @p chSemReset(). + * + * @api + */ + msg_t wait(void); + + /** + * @brief Performs a wait operation on a semaphore. + * + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or + * the semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using + * @p chSemReset(). + * + * @sclass + */ + msg_t waitS(void); + + /** + * @brief Performs a wait operation on a semaphore with timeout + * specification. + * + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or + * the semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using + * @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset + * within the specified timeout. + * + * @api + */ + msg_t waitTimeout(systime_t time); + + /** + * @brief Performs a wait operation on a semaphore with timeout + * specification. + * + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or + * the semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using + * @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset + * within the specified timeout. + * + * @sclass + */ + msg_t waitTimeoutS(systime_t time); + + /** + * @brief Performs a signal operation on a semaphore. + * + * @api + */ + void signal(void); + + /** + * @brief Performs a signal operation on a semaphore. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note + * that interrupt handlers always reschedule on exit so an + * explicit reschedule must not be performed in ISRs. + * + * @iclass + */ + void signalI(void); + + /** + * @brief Adds the specified value to the semaphore counter. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note + * that interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] n value to be added to the semaphore counter. The + * value must be positive. + * + * @iclass + */ + void addCounterI(cnt_t n); + + /** + * @brief Returns the semaphore counter value. + * + * @return The semaphore counter value. + * + * @iclass + */ + cnt_t getCounterI(void); + +#if CH_USE_SEMSW || defined(__DOXYGEN__) + /** + * @brief Atomic signal and wait operations. + * + * @param[in] ssem @p Semaphore object to be signaled + * @param[in] wsem @p Semaphore object to wait on + * @return A message specifying how the invoking thread + * has been released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore + * or the semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using + * @p chSemReset(). + * + * @api + */ + static msg_t signalWait(CounterSemaphore *ssem, + CounterSemaphore *wsem); +#endif /* CH_USE_SEMSW */ + }; + /*------------------------------------------------------------------------* + * chibios_rt::BinarySemaphore * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a binary semaphore. + */ + class BinarySemaphore { + public: + /** + * @brief Embedded @p ::Semaphore structure. + */ + ::BinarySemaphore bsem; + + /** + * @brief BinarySemaphore constructor. + * @details The embedded @p ::BinarySemaphore structure is initialized. + * + * @param[in] taken initial state of the binary semaphore: + * - @a false, the initial state is not taken. + * - @a true, the initial state is taken. + * . + * + * @init + */ + BinarySemaphore(bool taken); + + /** + * @brief Wait operation on the binary semaphore. + * + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully + * taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @api + */ + msg_t wait(void); + + /** + * @brief Wait operation on the binary semaphore. + * + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully + * taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @sclass + */ + msg_t waitS(void); + + /** + * @brief Wait operation on the binary semaphore. + * + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully + * taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled + * or reset within the specified timeout. + * + * @api + */ + msg_t waitTimeout(systime_t time); + + /** + * @brief Wait operation on the binary semaphore. + * + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has + * been released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully + * taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled + * or reset within the specified timeout. + * + * @sclass + */ + msg_t waitTimeoutS(systime_t time); + + /** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a + * reset rather than a signal because the @p bsemWait() will + * return @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @api + */ + void reset(bool taken); + + /** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a + * reset rather than a signal because the @p bsemWait() will + * return @p RDY_RESET instead of @p RDY_OK. + * @note This function does not reschedule. + * + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @iclass + */ + void resetI(bool taken); + + /** + * @brief Performs a signal operation on a binary semaphore. + * + * @api + */ + void signal(void); + + /** + * @brief Performs a signal operation on a binary semaphore. + * @note This function does not reschedule. + * + * @iclass + */ + void signalI(void); + + /** + * @brief Returns the binary semaphore current state. + * + * @return The binary semaphore current state. + * @retval false if the binary semaphore is not taken. + * @retval true if the binary semaphore is taken. + * + * @iclass + */ + bool getStateI(void); +}; +#endif /* CH_USE_SEMAPHORES */ + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::Mutex * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a mutex. + */ + class Mutex { + public: + /** + * @brief Embedded @p ::Mutex structure. + */ + ::Mutex mutex; + + /** + * @brief Mutex object constructor. + * @details The embedded @p ::Mutex structure is initialized. + * + * @init + */ + Mutex(void); + + /** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * locked by another thread then the function exits without + * waiting. + * @post The mutex is locked and inserted in the per-thread stack of + * owned mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @api + */ + bool tryLock(void); + + /** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * taken by another thread then the function exits without + * waiting. + * @post The mutex is locked and inserted in the per-thread stack of + * owned mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @sclass + */ + bool tryLockS(void); + + /** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of + * owned mutexes. + * + * @api + */ + void lock(void); + + /** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of + * owned mutexes. + * + * @sclass + */ + void lockS(void); + }; + +#if CH_USE_CONDVARS || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::CondVar * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a conditional variable. + */ + class CondVar { + public: + /** + * @brief Embedded @p ::CondVar structure. + */ + ::CondVar condvar; + + /** + * @brief CondVar object constructor. + * @details The embedded @p ::CondVar structure is initialized. + * + * @init + */ + CondVar(void); + + /** + * @brief Signals one thread that is waiting on the condition variable. + * + * @api + */ + void signal(void); + + /** + * @brief Signals one thread that is waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note + * that interrupt handlers always reschedule on exit so an + * explicit reschedule must not be performed in ISRs. + * + * @iclass + */ + void signalI(void); + + /** + * @brief Signals all threads that are waiting on the condition variable. + * + * @api + */ + void broadcast(void); + + /** + * @brief Signals all threads that are waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note + * that interrupt handlers always reschedule on exit so an + * explicit reschedule must not be performed in ISRs. + * + * @iclass + */ + void broadcastI(void); + + /** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the + * sequence is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @return A message specifying how the invoking thread has + * been released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @api + */ + msg_t wait(void); + + /** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the + * sequence is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @return A message specifying how the invoking thread has + * been released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @sclass + */ + msg_t waitS(void); + +#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) + /** + * @brief Waits on the CondVar while releasing the controlling mutex. + * + * @param[in] time the number of ticks before the operation fails + * @return The wakep mode. + * @retval RDY_OK if the condvar was signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar was signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar was not signaled within the + * specified timeout. + * + * @api + */ + msg_t waitTimeout(systime_t time); +#endif /* CH_USE_CONDVARS_TIMEOUT */ + }; +#endif /* CH_USE_CONDVARS */ +#endif /* CH_USE_MUTEXES */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::EvtListener * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating an event listener. + */ + class EvtListener { + public: + /** + * @brief Embedded @p ::EventListener structure. + */ + struct ::EventListener ev_listener; + + /** + * @brief Returns the pending flags from the listener and clears them. + * + * @return The flags added to the listener by the + * associated event source. + * + * @api + */ + flagsmask_t getAndClearFlags(void); + + /** + * @brief Returns the flags associated to an @p EventListener. + * @details The flags are returned and the @p EventListener flags mask is + * cleared. + * + * @return The flags added to the listener by the associated + * event source. + * + * @iclass + */ + flagsmask_t getAndClearFlagsI(void); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::EvtSource * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating an event source. + */ + class EvtSource { + public: + /** + * @brief Embedded @p ::EventSource structure. + */ + struct ::EventSource ev_source; + + /** + * @brief EvtSource object constructor. + * @details The embedded @p ::EventSource structure is initialized. + * + * @init + */ + EvtSource(void); + + /** + * @brief Registers a listener on the event source. + * + * @param[in] elp pointer to the @p EvtListener object + * @param[in] eid numeric identifier assigned to the Event + * Listener + * + * @api + */ + void registerOne(chibios_rt::EvtListener *elp, eventid_t eid); + + /** + * @brief Registers an Event Listener on an Event Source. + * @note Multiple Event Listeners can specify the same bits to be added. + * + * @param[in] elp pointer to the @p EvtListener object + * @param[in] emask the mask of event flags to be pended to the + * thread when the event source is broadcasted + * + * @api + */ + void registerMask(chibios_rt::EvtListener *elp, eventmask_t emask); + + /** + * @brief Unregisters a listener. + * @details The specified listeners is no more signaled by the event + * source. + * + * @param[in] elp the listener to be unregistered + * + * @api + */ + void unregister(chibios_rt::EvtListener *elp); + + /** + * @brief Broadcasts on an event source. + * @details All the listeners registered on the event source are signaled + * and the flags are added to the listener's flags mask. + * + * @param[in] flags the flags set to be added to the listener + * flags mask + * + * @api + */ + void broadcastFlags(flagsmask_t flags); + + /** + * @brief Broadcasts on an event source. + * @details All the listeners registered on the event source are signaled + * and the flags are added to the listener's flags mask. + * + * @param[in] flags the flags set to be added to the listener + * flags mask + * + * @iclass + */ + void broadcastFlagsI(flagsmask_t flags); + }; +#endif /* CH_USE_EVENTS */ + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::InQueue * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating an input queue. + */ + class InQueue { + private: + /** + * @brief Embedded @p ::InputQueue structure. + */ + ::InputQueue iq; + + public: + /** + * @brief InQueue constructor. + * + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] infy pointer to a callback function that is invoked when + * data is read from the queue. The value can be + * @p NULL. + * @param[in] link application defined pointer + * + * @init + */ + InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link); + + /** + * @brief Returns the filled space into an input queue. + * + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ + size_t getFullI(void); + + /** + * @brief Returns the empty space into an input queue. + * + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ + size_t getEmptyI(void); + + /** + * @brief Evaluates to @p TRUE if the specified input queue is empty. + * + * @return The queue status. + * @retval false if the queue is not empty. + * @retval true if the queue is empty. + * + * @iclass + */ + bool isEmptyI(void); + + /** + * @brief Evaluates to @p TRUE if the specified input queue is full. + * + * @return The queue status. + * @retval FALSE if the queue is not full. + * @retval TRUE if the queue is full. + * + * @iclass + */ + bool isFullI(void); + + /** + * @brief Resets an input queue. + * @details All the data in the input queue is erased and lost, any waiting + * thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order to + * obtain immediate attention from the high level layers. + * @iclass + */ + void resetI(void); + + /** + * @brief Input queue write. + * @details A byte value is written into the low end of an input queue. + * + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation has been completed with success. + * @retval Q_FULL if the queue is full and the operation cannot be + * completed. + * + * @iclass + */ + msg_t putI(uint8_t b); + + /** + * @brief Input queue read. + * @details This function reads a byte value from an input queue. If the + * queue is empty then the calling thread is suspended until a + * byte arrives in the queue. + * + * @return A byte value from the queue. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ + msg_t get(); + + /** + * @brief Input queue read with timeout. + * @details This function reads a byte value from an input queue. If the + * queue is empty then the calling thread is suspended until a + * byte arrives in the queue or a timeout occurs. + * @note The callback is invoked before reading the character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A byte value from the queue. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ + msg_t getTimeout(systime_t time); + + /** + * @brief Input queue read with timeout. + * @details The function reads data from an input queue into a buffer. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is + * suggested to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked before reading each character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ + size_t readTimeout(uint8_t *bp, size_t n, systime_t time); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::InQueueBuffer * + *------------------------------------------------------------------------*/ + /** + * @brief Template class encapsulating an input queue and its buffer. + * + * @param N size of the input queue + */ + template + class InQueueBuffer : public InQueue { + private: + uint8_t iq_buf[N]; + + public: + /** + * @brief InQueueBuffer constructor. + * + * @param[in] infy input notify callback function + * @param[in] link parameter to be passed to the callback + * + * @init + */ + InQueueBuffer(qnotify_t infy, void *link) : InQueue(iq_buf, N, + infy, link) { + } + }; + + /*------------------------------------------------------------------------* + * chibios_rt::OutQueue * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating an output queue. + */ + class OutQueue { + private: + /** + * @brief Embedded @p ::OutputQueue structure. + */ + ::OutputQueue oq; + + public: + /** + * @brief OutQueue constructor. + * + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] onfy pointer to a callback function that is invoked when + * data is written to the queue. The value can be + * @p NULL. + * @param[in] link application defined pointer + * + * @init + */ + OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link); + + /** + * @brief Returns the filled space into an output queue. + * + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ + size_t getFullI(void); + + /** + * @brief Returns the empty space into an output queue. + * + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ + size_t getEmptyI(void); + + /** + * @brief Evaluates to @p TRUE if the specified output queue is empty. + * + * @return The queue status. + * @retval false if the queue is not empty. + * @retval true if the queue is empty. + * + * @iclass + */ + bool isEmptyI(void); + + /** + * @brief Evaluates to @p TRUE if the specified output queue is full. + * + * @return The queue status. + * @retval FALSE if the queue is not full. + * @retval TRUE if the queue is full. + * + * @iclass + */ + bool isFullI(void); + + /** + * @brief Resets an output queue. + * @details All the data in the output queue is erased and lost, any + * waiting thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order + * to obtain immediate attention from the high level layers. + * + * @iclass + */ + void resetI(void); + + /** + * @brief Output queue write. + * @details This function writes a byte value to an output queue. If the + * queue is full then the calling thread is suspended until there + * is space in the queue. + * + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ + msg_t put(uint8_t b); + + /** + * @brief Output queue write with timeout. + * @details This function writes a byte value to an output queue. If the + * queue is full then the calling thread is suspended until there + * is space in the queue or a timeout occurs. + * @note The callback is invoked after writing the character into the + * buffer. + * + * @param[in] b the byte value to be written in the queue + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ + msg_t putTimeout(uint8_t b, systime_t time); + + /** + * @brief Output queue read. + * @details A byte value is read from the low end of an output queue. + * + * @return The byte value from the queue. + * @retval Q_EMPTY if the queue is empty. + * + * @iclass + */ + msg_t getI(void); + + /** + * @brief Output queue write with timeout. + * @details The function writes data from a buffer to an output queue. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is + * suggested to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked after writing each character into the + * buffer. + * + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ + size_t writeTimeout(const uint8_t *bp, size_t n, systime_t time); +}; + + /*------------------------------------------------------------------------* + * chibios_rt::OutQueueBuffer * + *------------------------------------------------------------------------*/ + /** + * @brief Template class encapsulating an output queue and its buffer. + * + * @param N size of the output queue + */ + template + class OutQueueBuffer : public OutQueue { + private: + uint8_t oq_buf[N]; + + public: + /** + * @brief OutQueueBuffer constructor. + * + * @param[in] onfy output notify callback function + * @param[in] link parameter to be passed to the callback + * + * @init + */ + OutQueueBuffer(qnotify_t onfy, void *link) : OutQueue(oq_buf, N, + onfy, link) { + } + }; +#endif /* CH_USE_QUEUES */ + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::Mailbox * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a mailbox. + */ + class Mailbox { + public: + /** + * @brief Embedded @p ::Mailbox structure. + */ + ::Mailbox mb; + + /** + * @brief Mailbox constructor. + * @details The embedded @p ::Mailbox structure is initialized. + * + * @param[in] buf pointer to the messages buffer as an array of + * @p msg_t + * @param[in] n number of elements in the buffer array + * + * @init + */ + Mailbox(msg_t *buf, cnt_t n); + + /** + * @brief Resets a Mailbox object. + * @details All the waiting threads are resumed with status @p RDY_RESET + * and the queued messages are lost. + * + * @api + */ + void reset(void); + + /** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox + * becomes available or the specified time runs out. + * + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ + msg_t post(msg_t msg, systime_t time); + + /** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox + * becomes available or the specified time runs out. + * + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ + msg_t postS(msg_t msg, systime_t time); + + /** + * @brief Posts a message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ + msg_t postI(msg_t msg); + + /** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox + * becomes available or the specified time runs out. + * + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ + msg_t postAhead(msg_t msg, systime_t time); + + /** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox + * becomes available or the specified time runs out. + * + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ + msg_t postAheadS(msg_t msg, systime_t time); + + /** + * @brief Posts an high priority message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ + msg_t postAheadI(msg_t msg); + + /** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the + * mailbox or the specified time runs out. + * + * @param[out] msgp pointer to a message variable for the received + * @param[in] time message the number of ticks before the operation + * timeouts, the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ + msg_t fetch(msg_t *msgp, systime_t time); + + /** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the + * mailbox or the specified time runs out. + * + * @param[out] msgp pointer to a message variable for the received + * @param[in] time message the number of ticks before the operation + * timeouts, the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ + msg_t fetchS(msg_t *msgp, systime_t time); + + /** + * @brief Retrieves a message from a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is empty. + * + * @param[out] msgp pointer to a message variable for the received + * message + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be + * fetched. + * + * @iclass + */ + msg_t fetchI(msg_t *msgp); + + /** + * @brief Returns the number of free message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a + * locked state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @return The number of empty message slots. + * + * @iclass + */ + cnt_t getFreeCountI(void); + + /** + * @brief Returns the number of used message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a + * locked state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @return The number of queued messages. + * + * @iclass + */ + cnt_t getUsedCountI(void); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::MailboxBuffer * + *------------------------------------------------------------------------*/ + /** + * @brief Template class encapsulating a mailbox and its messages buffer. + * + * @param N size of the mailbox + */ + template + class MailboxBuffer : public Mailbox { + private: + msg_t mb_buf[N]; + + public: + /** + * @brief BufferMailbox constructor. + * + * @init + */ + MailboxBuffer(void) : Mailbox(mb_buf, + (cnt_t)(sizeof mb_buf / sizeof (msg_t))) { + } + }; +#endif /* CH_USE_MAILBOXES */ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + /*------------------------------------------------------------------------* + * chibios_rt::MemoryPool * + *------------------------------------------------------------------------*/ + /** + * @brief Class encapsulating a mailbox. + */ + class MemoryPool { + public: + /** + * @brief Embedded @p ::MemoryPool structure. + */ + ::MemoryPool pool; + + /** + * @brief MemoryPool constructor. + * + * @param[in] size the size of the objects contained in this memory + * pool, the minimum accepted size is the size of + * a pointer to void. + * @param[in] provider memory provider function for the memory pool or + * @p NULL if the pool is not allowed to grow + * automatically + * + * @init + */ + MemoryPool(size_t size, memgetfunc_t provider); + + /** + * @brief MemoryPool constructor. + * + * @param[in] size the size of the objects contained in this memory + * pool, the minimum accepted size is the size of + * a pointer to void. + * @param[in] provider memory provider function for the memory pool or + * @p NULL if the pool is not allowed to grow + * automatically + * @param[in] p pointer to the array first element + * @param[in] n number of elements in the array + * + * @init + */ + MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n); + + /** + * @brief Loads a memory pool with an array of static objects. + * @pre The memory pool must be already been initialized. + * @pre The array elements must be of the right size for the specified + * memory pool. + * @post The memory pool contains the elements of the input array. + * + * @param[in] p pointer to the array first element + * @param[in] n number of elements in the array + * + * @api + */ + void loadArray(void *p, size_t n); + + /** + * @brief Allocates an object from a memory pool. + * @pre The memory pool must be already been initialized. + * + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @iclass + */ + void *allocI(void); + + /** + * @brief Allocates an object from a memory pool. + * @pre The memory pool must be already been initialized. + * + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @api + */ + void *alloc(void); + + /** + * @brief Releases an object into a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The freed object must be of the right size for the specified + * memory pool. + * @pre The object must be properly aligned to contain a pointer to + * void. + * + * @param[in] objp the pointer to the object to be released + * + * @iclass + */ + void free(void *objp); + + /** + * @brief Adds an object to a memory pool. + * @pre The memory pool must be already been initialized. + * @pre The added object must be of the right size for the specified + * memory pool. + * @pre The added object must be memory aligned to the size of + * @p stkalign_t type. + * @note This function is just an alias for @p chPoolFree() and has been + * added for clarity. + * + * @param[in] objp the pointer to the object to be added + * + * @iclass + */ + void freeI(void *objp); + }; + + /*------------------------------------------------------------------------* + * chibios_rt::ObjectsPool * + *------------------------------------------------------------------------*/ + /** + * @brief Template class encapsulating a memory pool and its elements. + */ + template + class ObjectsPool : public MemoryPool { + private: + /* The buffer is declared as an array of pointers to void for two + reasons: + 1) The objects must be properly aligned to hold a pointer as + first field. + 2) There is no need to invoke constructors for object that are + into the pool.*/ + void *pool_buf[(N * sizeof (T)) / sizeof (void *)]; + + public: + /** + * @brief ObjectsPool constructor. + * + * @init + */ + ObjectsPool(void) : MemoryPool(sizeof (T), NULL) { + + loadArray(pool_buf, N); + } + }; +#endif /* CH_USE_MEMPOOLS */ + + /*------------------------------------------------------------------------* + * chibios_rt::BaseSequentialStreamInterface * + *------------------------------------------------------------------------*/ + /** + * @brief Interface of a ::BaseSequentialStream. + * @note You can cast a ::BaseSequentialStream to this interface and use + * it, the memory layout is the same. + */ + class BaseSequentialStreamInterface { + public: + /** + * @brief Sequential Stream write. + * @details The function writes data from a buffer to a stream. + * + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value + * can be less than the specified number of bytes if + * an end-of-file condition has been met. + * + * @api + */ + virtual size_t write(const uint8_t *bp, size_t n) = 0; + + /** + * @brief Sequential Stream read. + * @details The function reads data from a stream into a buffer. + * + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value + * can be less than the specified number of bytes if + * an end-of-file condition has been met. + * + * @api + */ + virtual size_t read(uint8_t *bp, size_t n) = 0; + + /** + * @brief Sequential Stream blocking byte write. + * @details This function writes a byte value to a channel. If the channel + * is not ready to accept data then the calling thread is + * suspended. + * + * @param[in] b the byte value to be written to the channel + * + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if an end-of-file condition has been met. + * + * @api + */ + virtual msg_t put(uint8_t b) = 0; + + /** + * @brief Sequential Stream blocking byte read. + * @details This function reads a byte value from a channel. If the data + * is not available then the calling thread is suspended. + * + * @return A byte value from the queue. + * @retval Q_RESET if an end-of-file condition has been met. + * + * @api + */ + virtual msg_t get(void) = 0; + }; +} + +#endif /* _CH_HPP_ */ + +/** @} */ diff --git a/os/various/cpp_wrappers/kernel.mk b/os/various/cpp_wrappers/kernel.mk new file mode 100644 index 000000000..6cd787658 --- /dev/null +++ b/os/various/cpp_wrappers/kernel.mk @@ -0,0 +1,4 @@ +# C++ wrapper files. +CHCPPSRC = ${CHIBIOS}/os/various/cpp_wrappers/ch.cpp + +CHCPPINC = ${CHIBIOS}/os/various/cpp_wrappers diff --git a/os/various/devices_lib/accel/lis302dl.c b/os/various/devices_lib/accel/lis302dl.c new file mode 100644 index 000000000..14e2a0ad1 --- /dev/null +++ b/os/various/devices_lib/accel/lis302dl.c @@ -0,0 +1,119 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lis302dl.c + * @brief LIS302DL MEMS interface module through SPI code. + * + * @addtogroup lis302dl + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "lis302dl.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static uint8_t txbuf[2]; +static uint8_t rxbuf[2]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a register value. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI initerface + * @param[in] reg register number + * @return The register value. + */ +uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg) { + + spiSelect(spip); + txbuf[0] = 0x80 | reg; + txbuf[1] = 0xff; + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[1]; +} + +/** + * @brief Writes a value into a register. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI initerface + * @param[in] reg register number + * @param[in] value the value to be written + */ +void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { + + switch (reg) { + default: + /* Reserved register must not be written, according to the datasheet + this could permanently damage the device.*/ + chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register"); + case LIS302DL_WHO_AM_I: + case LIS302DL_HP_FILTER_RESET: + case LIS302DL_STATUS_REG: + case LIS302DL_OUTX: + case LIS302DL_OUTY: + case LIS302DL_OUTZ: + case LIS302DL_FF_WU_SRC1: + case LIS302DL_FF_WU_SRC2: + case LIS302DL_CLICK_SRC: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LIS302DL_CTRL_REG1: + case LIS302DL_CTRL_REG2: + case LIS302DL_CTRL_REG3: + case LIS302DL_FF_WU_CFG1: + case LIS302DL_FF_WU_THS1: + case LIS302DL_FF_WU_DURATION1: + case LIS302DL_FF_WU_CFG2: + case LIS302DL_FF_WU_THS2: + case LIS302DL_FF_WU_DURATION2: + case LIS302DL_CLICK_CFG: + case LIS302DL_CLICK_THSY_X: + case LIS302DL_CLICK_THSZ: + case LIS302DL_CLICK_TIMELIMIT: + case LIS302DL_CLICK_LATENCY: + case LIS302DL_CLICK_WINDOW: + spiSelect(spip); + txbuf[0] = reg; + txbuf[1] = value; + spiSend(spip, 2, txbuf); + spiUnselect(spip); + } +} + +/** @} */ diff --git a/os/various/devices_lib/accel/lis302dl.dox b/os/various/devices_lib/accel/lis302dl.dox new file mode 100644 index 000000000..02f51606a --- /dev/null +++ b/os/various/devices_lib/accel/lis302dl.dox @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup lis302dl Interface module for LIS302DL MEMS + * + * @brief Interface module for LIS302DL MEMS. + * @details This module implements a generic interface for the LIS302DL + * STMicroelectronics MEMS device. The communication is performed + * through a standard SPI driver. + * + * @ingroup accel + */ diff --git a/os/various/devices_lib/accel/lis302dl.h b/os/various/devices_lib/accel/lis302dl.h new file mode 100644 index 000000000..0c6637a0d --- /dev/null +++ b/os/various/devices_lib/accel/lis302dl.h @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lis302dl.h + * @brief LIS302DL MEMS interface module through SPI header. + * + * @addtogroup lis302dl + * @{ + */ + +#ifndef _LIS302DL_H_ +#define _LIS302DL_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name LIS302DL register names + * @{ + */ +#define LIS302DL_WHO_AM_I 0x0F +#define LIS302DL_CTRL_REG1 0x20 +#define LIS302DL_CTRL_REG2 0x21 +#define LIS302DL_CTRL_REG3 0x22 +#define LIS302DL_HP_FILTER_RESET 0x23 +#define LIS302DL_STATUS_REG 0x27 +#define LIS302DL_OUTX 0x29 +#define LIS302DL_OUTY 0x2B +#define LIS302DL_OUTZ 0x2D +#define LIS302DL_FF_WU_CFG1 0x30 +#define LIS302DL_FF_WU_SRC1 0x31 +#define LIS302DL_FF_WU_THS1 0x32 +#define LIS302DL_FF_WU_DURATION1 0x33 +#define LIS302DL_FF_WU_CFG2 0x34 +#define LIS302DL_FF_WU_SRC2 0x35 +#define LIS302DL_FF_WU_THS2 0x36 +#define LIS302DL_FF_WU_DURATION2 0x37 +#define LIS302DL_CLICK_CFG 0x38 +#define LIS302DL_CLICK_SRC 0x39 +#define LIS302DL_CLICK_THSY_X 0x3B +#define LIS302DL_CLICK_THSZ 0x3C +#define LIS302DL_CLICK_TIMELIMIT 0x3D +#define LIS302DL_CLICK_LATENCY 0x3E +#define LIS302DL_CLICK_WINDOW 0x3F +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg); + void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); +#ifdef __cplusplus +} +#endif + +#endif /* _LIS302DL_H_ */ + +/** @} */ diff --git a/os/various/devices_lib/lcd/lcd3310.c b/os/various/devices_lib/lcd/lcd3310.c new file mode 100644 index 000000000..86fee541b --- /dev/null +++ b/os/various/devices_lib/lcd/lcd3310.c @@ -0,0 +1,310 @@ +/* + Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lcd3310.c + * @brief Nokia 3310 LCD interface module through SPI code. + * + * @addtogroup lcd3310 + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "lcd3310.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +const uint8_t Fonts8x5 [][LCD3310_FONT_X_SIZE] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, /* space */ + { 0x00, 0x00, 0x2f, 0x00, 0x00 }, /* ! */ + { 0x00, 0x07, 0x00, 0x07, 0x00 }, /* " */ + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, /* # */ + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, /* $ */ + { 0xc4, 0xc8, 0x10, 0x26, 0x46 }, /* % */ + { 0x36, 0x49, 0x55, 0x22, 0x50 }, /* & */ + { 0x00, 0x05, 0x03, 0x00, 0x00 }, /* ' */ + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, /* ( */ + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, /* ) */ + { 0x14, 0x08, 0x3E, 0x08, 0x14 }, /* * */ + { 0x08, 0x08, 0x3E, 0x08, 0x08 }, /* + */ + { 0x00, 0x00, 0x50, 0x30, 0x00 }, /* , */ + { 0x10, 0x10, 0x10, 0x10, 0x10 }, /* - */ + { 0x00, 0x60, 0x60, 0x00, 0x00 }, /* . */ + { 0x20, 0x10, 0x08, 0x04, 0x02 }, /* / */ + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, /* 0 */ + { 0x00, 0x42, 0x7F, 0x40, 0x00 }, /* 1 */ + { 0x42, 0x61, 0x51, 0x49, 0x46 }, /* 2 */ + { 0x21, 0x41, 0x45, 0x4B, 0x31 }, /* 3 */ + { 0x18, 0x14, 0x12, 0x7F, 0x10 }, /* 4 */ + { 0x27, 0x45, 0x45, 0x45, 0x39 }, /* 5 */ + { 0x3C, 0x4A, 0x49, 0x49, 0x30 }, /* 6 */ + { 0x01, 0x71, 0x09, 0x05, 0x03 }, /* 7 */ + { 0x36, 0x49, 0x49, 0x49, 0x36 }, /* 8 */ + { 0x06, 0x49, 0x49, 0x29, 0x1E }, /* 9 */ + { 0x00, 0x36, 0x36, 0x00, 0x00 }, /* : */ + { 0x00, 0x56, 0x36, 0x00, 0x00 }, /* ; */ + { 0x08, 0x14, 0x22, 0x41, 0x00 }, /* < */ + { 0x14, 0x14, 0x14, 0x14, 0x14 }, /* = */ + { 0x00, 0x41, 0x22, 0x14, 0x08 }, /* > */ + { 0x02, 0x01, 0x51, 0x09, 0x06 }, /* ? */ + { 0x32, 0x49, 0x59, 0x51, 0x3E }, /* @ */ + { 0x7E, 0x11, 0x11, 0x11, 0x7E }, /* A */ + { 0x7F, 0x49, 0x49, 0x49, 0x36 }, /* B */ + { 0x3E, 0x41, 0x41, 0x41, 0x22 }, /* C */ + { 0x7F, 0x41, 0x41, 0x22, 0x1C }, /* D */ + { 0x7F, 0x49, 0x49, 0x49, 0x41 }, /* E */ + { 0x7F, 0x09, 0x09, 0x09, 0x01 }, /* F */ + { 0x3E, 0x41, 0x49, 0x49, 0x7A }, /* G */ + { 0x7F, 0x08, 0x08, 0x08, 0x7F }, /* H */ + { 0x00, 0x41, 0x7F, 0x41, 0x00 }, /* I */ + { 0x20, 0x40, 0x41, 0x3F, 0x01 }, /* J */ + { 0x7F, 0x08, 0x14, 0x22, 0x41 }, /* K */ + { 0x7F, 0x40, 0x40, 0x40, 0x40 }, /* L */ + { 0x7F, 0x02, 0x0C, 0x02, 0x7F }, /* M */ + { 0x7F, 0x04, 0x08, 0x10, 0x7F }, /* N */ + { 0x3E, 0x41, 0x41, 0x41, 0x3E }, /* O */ + { 0x7F, 0x09, 0x09, 0x09, 0x06 }, /* P */ + { 0x3E, 0x41, 0x51, 0x21, 0x5E }, /* Q */ + { 0x7F, 0x09, 0x19, 0x29, 0x46 }, /* R */ + { 0x46, 0x49, 0x49, 0x49, 0x31 }, /* S */ + { 0x01, 0x01, 0x7F, 0x01, 0x01 }, /* T */ + { 0x3F, 0x40, 0x40, 0x40, 0x3F }, /* U */ + { 0x1F, 0x20, 0x40, 0x20, 0x1F }, /* V */ + { 0x3F, 0x40, 0x38, 0x40, 0x3F }, /* W */ + { 0x63, 0x14, 0x08, 0x14, 0x63 }, /* X */ + { 0x07, 0x08, 0x70, 0x08, 0x07 }, /* Y */ + { 0x61, 0x51, 0x49, 0x45, 0x43 }, /* Z */ + { 0x00, 0x7F, 0x41, 0x41, 0x00 }, /* [ */ + { 0x55, 0x2A, 0x55, 0x2A, 0x55 }, /* \ */ + { 0x00, 0x41, 0x41, 0x7F, 0x00 }, /* ] */ + { 0x04, 0x02, 0x01, 0x02, 0x04 }, /* ^ */ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, /* _ */ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, /* ' */ + { 0x20, 0x54, 0x54, 0x54, 0x78 }, /* a */ + { 0x7F, 0x48, 0x44, 0x44, 0x38 }, /* b */ + { 0x38, 0x44, 0x44, 0x44, 0x20 }, /* c */ + { 0x38, 0x44, 0x44, 0x48, 0x7F }, /* d */ + { 0x38, 0x54, 0x54, 0x54, 0x18 }, /* e */ + { 0x08, 0x7E, 0x09, 0x01, 0x02 }, /* f */ + { 0x0C, 0x52, 0x52, 0x52, 0x3E }, /* g */ + { 0x7F, 0x08, 0x04, 0x04, 0x78 }, /* h */ + { 0x00, 0x44, 0x7D, 0x40, 0x00 }, /* i */ + { 0x20, 0x40, 0x44, 0x3D, 0x00 }, /* j */ + { 0x7F, 0x10, 0x28, 0x44, 0x00 }, /* k */ + { 0x00, 0x41, 0x7F, 0x40, 0x00 }, /* l */ + { 0x7C, 0x04, 0x18, 0x04, 0x78 }, /* m */ + { 0x7C, 0x08, 0x04, 0x04, 0x78 }, /* n */ + { 0x38, 0x44, 0x44, 0x44, 0x38 }, /* o */ + { 0x7C, 0x14, 0x14, 0x14, 0x08 }, /* p */ + { 0x08, 0x14, 0x14, 0x18, 0x7C }, /* q */ + { 0x7C, 0x08, 0x04, 0x04, 0x08 }, /* r */ + { 0x48, 0x54, 0x54, 0x54, 0x20 }, /* s */ + { 0x04, 0x3F, 0x44, 0x40, 0x20 }, /* t */ + { 0x3C, 0x40, 0x40, 0x20, 0x7C }, /* u */ + { 0x1C, 0x20, 0x40, 0x20, 0x1C }, /* v */ + { 0x3C, 0x40, 0x30, 0x40, 0x3C }, /* w */ + { 0x44, 0x28, 0x10, 0x28, 0x44 }, /* x */ + { 0x0C, 0x50, 0x50, 0x50, 0x3C }, /* y */ + { 0x44, 0x64, 0x54, 0x4C, 0x44 }, /* z */ + { 0x00, 0x08, 0x36, 0x41, 0x00 }, /* { */ + { 0x00, 0x00, 0x7F, 0x00, 0x00 }, /* | */ + { 0x00, 0x41, 0x36, 0x08, 0x00 }, /* } */ +}; + + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief LCD driver initialization. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + */ +void lcd3310Init(SPIDriver *spip) { + + /* Reset LCD */ + palClearPad(LCD3310_RES_PORT, LCD3310_RES_PIN); + chThdSleepMilliseconds(15); + palSetPad(LCD3310_RES_PORT, LCD3310_RES_PIN); + chThdSleepMilliseconds(15); + + /* Send configuration commands to LCD */ + lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD extended commands */ + lcd3310WriteByte(spip, 0xC8, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */ + lcd3310WriteByte(spip, 0x05, LCD3310_SEND_CMD); /* Set start line S6 to 1 TLS8204 */ + lcd3310WriteByte(spip, 0x40, LCD3310_SEND_CMD); /* Set start line S[5:0] to 0x00 TLS8204 */ + lcd3310WriteByte(spip, 0x12, LCD3310_SEND_CMD); /* LCD bias mode 1:68. */ + lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD standard Commands, horizontal addressing mode. */ + lcd3310WriteByte(spip, 0x08, LCD3310_SEND_CMD); /* LCD blank */ + lcd3310WriteByte(spip, 0x0C, LCD3310_SEND_CMD); /* LCD in normal mode. */ + + lcd3310Clear(spip); /* Clear LCD */ +} + +/** + * @brief Write byte to LCD driver. + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] data data to write + * @param[in] cd select between command or data + */ +void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd) { + + spiSelect(spip); + + if(cd == LCD3310_SEND_DATA) { + palSetPad(LCD3310_DC_PORT, LCD3310_DC_PIN); + } + else { + palClearPad(LCD3310_DC_PORT, LCD3310_DC_PIN); + } + + spiSend(spip, 1, &data); // change to normal spi send + spiUnselect(spip); +} + +/** + * @brief Clear LCD + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + */ +void lcd3310Clear(SPIDriver *spip) { // ok + + uint32_t i, j; + + for (i = 0; i < LCD3310_Y_RES/LCD3310_FONT_Y_SIZE; i++) { + lcd3310SetPosXY(spip, 0, i); + for (j = 0; j < LCD3310_X_RES; j++) + lcd3310WriteByte(spip, 0x00, LCD3310_SEND_DATA); + } + +} + +/** + * @brief Set position + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] x column address in LCD DDRAM, 0 to 83 + * @param[in] y page address in LCD DDRAM, 0 to 5 + */ +void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y) { + + if (y > LCD3310_Y_RES/LCD3310_FONT_Y_SIZE) return; + if (x > LCD3310_X_RES) return; + + lcd3310WriteByte(spip, 0x80 | x, LCD3310_SEND_CMD); /* Set x position */ + lcd3310WriteByte(spip, 0x40 | y, LCD3310_SEND_CMD); /* Set y position */ + +} + +/** + * @brief Write char + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] ch char + */ +void lcd3310WriteChar(SPIDriver *spip, uint8_t ch) { + + uint8_t i; + + for ( i = 0; i < LCD3310_FONT_X_SIZE; i++ ){ + lcd3310WriteByte(spip, Fonts8x5[ch - 32][i], LCD3310_SEND_DATA); + } + +} + +/** + * @brief Set LCD contrast. + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] contrast LCD contrast value + */ +void lcd3310Contrast (SPIDriver *spip, uint8_t contrast) { + + lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD Extended Commands */ + lcd3310WriteByte(spip, 0x80 | contrast, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */ + lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD Standard Commands, horizontal addressing mode */ +} + + +/** + * @brief Write text + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] strp pointer to text + */ +void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp) { + + while ( *strp ) { + lcd3310WriteChar(spip, *strp); + strp++; + } +} + +/** + * @brief Rotate text + * @pre The LCD driver must be initialized. + * + * @param[in] spip pointer to the SPI interface + * @param[in] strp pointer to text + * @param[in] offset text offset + */ +void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset) { + + uint8_t i; + uint8_t n; + uint8_t m; + + for(n = 0; strp[n] != '\0'; n++); /* Count number of char */ + + if (offset >= n) + return; + + for (i = 0; i < LCD3310_X_RES/LCD3310_FONT_X_SIZE; i++) { + m = i + offset; + if ( m < n) + lcd3310WriteChar(spip, strp[m]); + else + lcd3310WriteChar(spip, strp[m - n]); + } +} + +/** @} */ diff --git a/os/various/devices_lib/lcd/lcd3310.h b/os/various/devices_lib/lcd/lcd3310.h new file mode 100644 index 000000000..b3bf90660 --- /dev/null +++ b/os/various/devices_lib/lcd/lcd3310.h @@ -0,0 +1,94 @@ +/* + Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lcd3310.h + * @brief Nokia 3310 LCD interface module through SPI code. + * + * @addtogroup lcd3310 + * @{ + */ + +#ifndef _LCD3310_H_ +#define _LCD3310_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define LCD3310_X_RES 84 +#define LCD3310_Y_RES 48 + +#define LCD3310_FONT_X_SIZE 5 +#define LCD3310_FONT_Y_SIZE 8 + +#define LCD3310_SEND_CMD 0 +#define LCD3310_SEND_DATA 1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(LCD3310_RES_PIN) +#error "LCD3310_RES_PIN not defined!!!" +#endif + +#if !defined(LCD3310_RES_PORT) +#error "LCD3310_RES_PORT not defined!!!" +#endif + +#if !defined(LCD3310_DC_PIN) +#error "LCD3310_DC_PIN not defined!!!" +#endif + +#if!defined(LCD3310_DC_PORT) +#error "LCD3310_DC_PORT not defined!!!" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void lcd3310Init(SPIDriver *spip); + void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd); + void lcd3310Contrast(SPIDriver *spip, uint8_t contrast); + void lcd3310Clear(SPIDriver *spip); + void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y); + void lcd3310WriteChar (SPIDriver *spip, uint8_t ch); + void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp); + void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset); +#ifdef __cplusplus +} +#endif + +#endif /* _LCD3310_H_ */ + +/** @} */ diff --git a/os/various/evtimer.c b/os/various/evtimer.c new file mode 100644 index 000000000..a077529da --- /dev/null +++ b/os/various/evtimer.c @@ -0,0 +1,64 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file evtimer.c + * @brief Events Generator Timer code. + * + * @addtogroup event_timer + * @{ + */ + +#include "ch.h" +#include "evtimer.h" + +static void tmrcb(void *p) { + EvTimer *etp = p; + + chSysLockFromIsr(); + chEvtBroadcastI(&etp->et_es); + chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); + chSysUnlockFromIsr(); +} + +/** + * @brief Starts the timer + * @details If the timer was already running then the function has no effect. + * + * @param etp pointer to an initialized @p EvTimer structure. + */ +void evtStart(EvTimer *etp) { + + chSysLock(); + + if (!chVTIsArmedI(&etp->et_vt)) + chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); + + chSysUnlock(); +} + +/** + * @brief Stops the timer. + * @details If the timer was already stopped then the function has no effect. + * + * @param etp pointer to an initialized @p EvTimer structure. + */ +void evtStop(EvTimer *etp) { + + chVTReset(&etp->et_vt); +} + +/** @} */ diff --git a/os/various/evtimer.h b/os/various/evtimer.h new file mode 100644 index 000000000..613c688a6 --- /dev/null +++ b/os/various/evtimer.h @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file evtimer.h + * @brief Events Generator Timer structures and macros. + * + * @addtogroup event_timer + * @{ + */ + +#ifndef _EVTIMER_H_ +#define _EVTIMER_H_ + + +/* + * Module dependencies check. + */ +#if !CH_USE_EVENTS +#error "Event Timers require CH_USE_EVENTS" +#endif + +/** + * @brief Event timer structure. + */ +typedef struct { + VirtualTimer et_vt; + EventSource et_es; + systime_t et_interval; +} EvTimer; + +#ifdef __cplusplus +extern "C" { +#endif + void evtStart(EvTimer *etp); + void evtStop(EvTimer *etp); +#ifdef __cplusplus +} +#endif + +/** + * @brief Initializes an @p EvTimer structure. + * + * @param etp the EvTimer structure to be initialized + * @param time the interval in system ticks + */ +#define evtInit(etp, time) { \ + chEvtInit(&(etp)->et_es); \ + (etp)->et_vt.vt_func = NULL; \ + (etp)->et_interval = (time); \ +} + +#endif /* _EVTIMER_H_ */ + +/** @} */ diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk new file mode 100644 index 000000000..682091e00 --- /dev/null +++ b/os/various/fatfs_bindings/fatfs.mk @@ -0,0 +1,7 @@ +# FATFS files. +FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \ + ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \ + ${CHIBIOS}/ext/fatfs/src/ff.c \ + ${CHIBIOS}/ext/fatfs/src/option/ccsbcs.c + +FATFSINC = ${CHIBIOS}/ext/fatfs/src diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c new file mode 100644 index 000000000..c724fa5f9 --- /dev/null +++ b/os/various/fatfs_bindings/fatfs_diskio.c @@ -0,0 +1,254 @@ +/*-----------------------------------------------------------------------*/ +/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* This is a stub disk I/O module that acts as front end of the existing */ +/* disk I/O modules and attach it to FatFs module with common interface. */ +/*-----------------------------------------------------------------------*/ + +#include "ch.h" +#include "hal.h" +#include "ffconf.h" +#include "diskio.h" + +#if HAL_USE_MMC_SPI && HAL_USE_SDC +#error "cannot specify both MMC_SPI and SDC drivers" +#endif + +#if HAL_USE_MMC_SPI +extern MMCDriver MMCD1; +#elif HAL_USE_SDC +extern SDCDriver SDCD1; +#else +#error "MMC_SPI or SDC driver must be specified" +#endif + +#if HAL_USE_RTC +#include "chrtclib.h" +extern RTCDriver RTCD1; +#endif + +/*-----------------------------------------------------------------------*/ +/* Correspondence between physical drive number and physical drive. */ + +#define MMC 0 +#define SDC 0 + + + +/*-----------------------------------------------------------------------*/ +/* Inidialize a Drive */ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat; + + switch (drv) { +#if HAL_USE_MMC_SPI + case MMC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MMCD1) != BLK_READY) + stat |= STA_NOINIT; + if (mmcIsWriteProtected(&MMCD1)) + stat |= STA_PROTECT; + return stat; +#else + case SDC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&SDCD1) != BLK_READY) + stat |= STA_NOINIT; + if (sdcIsWriteProtected(&SDCD1)) + stat |= STA_PROTECT; + return stat; +#endif + } + return STA_NODISK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Return Disk Status */ + +DSTATUS disk_status ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat; + + switch (drv) { +#if HAL_USE_MMC_SPI + case MMC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MMCD1) != BLK_READY) + stat |= STA_NOINIT; + if (mmcIsWriteProtected(&MMCD1)) + stat |= STA_PROTECT; + return stat; +#else + case SDC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&SDCD1) != BLK_READY) + stat |= STA_NOINIT; + if (sdcIsWriteProtected(&SDCD1)) + stat |= STA_PROTECT; + return stat; +#endif + } + return STA_NODISK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE *buff, /* Data buffer to store read data */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to read (1..255) */ +) +{ + switch (drv) { +#if HAL_USE_MMC_SPI + case MMC: + if (blkGetDriverState(&MMCD1) != BLK_READY) + return RES_NOTRDY; + if (mmcStartSequentialRead(&MMCD1, sector)) + return RES_ERROR; + while (count > 0) { + if (mmcSequentialRead(&MMCD1, buff)) + return RES_ERROR; + buff += MMCSD_BLOCK_SIZE; + count--; + } + if (mmcStopSequentialRead(&MMCD1)) + return RES_ERROR; + return RES_OK; +#else + case SDC: + if (blkGetDriverState(&SDCD1) != BLK_READY) + return RES_NOTRDY; + if (sdcRead(&SDCD1, sector, buff, count)) + return RES_ERROR; + return RES_OK; +#endif + } + return RES_PARERR; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ + +#if _READONLY == 0 +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to write (1..255) */ +) +{ + switch (drv) { +#if HAL_USE_MMC_SPI + case MMC: + if (blkGetDriverState(&MMCD1) != BLK_READY) + return RES_NOTRDY; + if (mmcIsWriteProtected(&MMCD1)) + return RES_WRPRT; + if (mmcStartSequentialWrite(&MMCD1, sector)) + return RES_ERROR; + while (count > 0) { + if (mmcSequentialWrite(&MMCD1, buff)) + return RES_ERROR; + buff += MMCSD_BLOCK_SIZE; + count--; + } + if (mmcStopSequentialWrite(&MMCD1)) + return RES_ERROR; + return RES_OK; +#else + case SDC: + if (blkGetDriverState(&SDCD1) != BLK_READY) + return RES_NOTRDY; + if (sdcWrite(&SDCD1, sector, buff, count)) + return RES_ERROR; + return RES_OK; +#endif + } + return RES_PARERR; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + switch (drv) { +#if HAL_USE_MMC_SPI + case MMC: + switch (ctrl) { + case CTRL_SYNC: + return RES_OK; + case GET_SECTOR_SIZE: + *((WORD *)buff) = MMCSD_BLOCK_SIZE; + return RES_OK; +#if _USE_ERASE + case CTRL_ERASE_SECTOR: + mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); + return RES_OK; +#endif + default: + return RES_PARERR; + } +#else + case SDC: + switch (ctrl) { + case CTRL_SYNC: + return RES_OK; + case GET_SECTOR_COUNT: + *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1); + return RES_OK; + case GET_SECTOR_SIZE: + *((WORD *)buff) = MMCSD_BLOCK_SIZE; + return RES_OK; + case GET_BLOCK_SIZE: + *((DWORD *)buff) = 256; /* 512b blocks in one erase block */ + return RES_OK; +#if _USE_ERASE + case CTRL_ERASE_SECTOR: + sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); + return RES_OK; +#endif + default: + return RES_PARERR; + } +#endif + } + return RES_PARERR; +} + +DWORD get_fattime(void) { +#if HAL_USE_RTC + return rtcGetTimeFat(&RTCD1); +#else + return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */ +#endif +} + + + diff --git a/os/various/fatfs_bindings/fatfs_syscall.c b/os/various/fatfs_bindings/fatfs_syscall.c new file mode 100644 index 000000000..a42cbcffb --- /dev/null +++ b/os/various/fatfs_bindings/fatfs_syscall.c @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*------------------------------------------------------------------------*/ +/* Sample code of OS dependent controls for FatFs R0.08b */ +/* (C)ChaN, 2011 */ +/*------------------------------------------------------------------------*/ + +#include "ch.h" +#include "ff.h" + +#if _FS_REENTRANT +/*------------------------------------------------------------------------*/ +/* Static array of Synchronization Objects */ +/*------------------------------------------------------------------------*/ +static Semaphore ff_sem[_VOLUMES]; + +/*------------------------------------------------------------------------*/ +/* Create a Synchronization Object */ +/*------------------------------------------------------------------------*/ +int ff_cre_syncobj(BYTE vol, _SYNC_t *sobj) { + + *sobj = &ff_sem[vol]; + chSemInit(*sobj, 1); + return TRUE; +} + +/*------------------------------------------------------------------------*/ +/* Delete a Synchronization Object */ +/*------------------------------------------------------------------------*/ +int ff_del_syncobj(_SYNC_t sobj) { + + chSemReset(sobj, 0); + return TRUE; +} + +/*------------------------------------------------------------------------*/ +/* Request Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +int ff_req_grant(_SYNC_t sobj) { + + msg_t msg = chSemWaitTimeout(sobj, (systime_t)_FS_TIMEOUT); + return msg == RDY_OK; +} + +/*------------------------------------------------------------------------*/ +/* Release Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +void ff_rel_grant(_SYNC_t sobj) { + + chSemSignal(sobj); +} +#endif /* _FS_REENTRANT */ + +#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ +/*------------------------------------------------------------------------*/ +/* Allocate a memory block */ +/*------------------------------------------------------------------------*/ +void *ff_memalloc(UINT size) { + + return chHeapAlloc(NULL, size); +} + +/*------------------------------------------------------------------------*/ +/* Free a memory block */ +/*------------------------------------------------------------------------*/ +void ff_memfree(void *mblock) { + + chHeapFree(mblock); +} +#endif /* _USE_LFN == 3 */ diff --git a/os/various/fatfs_bindings/readme.txt b/os/various/fatfs_bindings/readme.txt new file mode 100644 index 000000000..8735cce54 --- /dev/null +++ b/os/various/fatfs_bindings/readme.txt @@ -0,0 +1,6 @@ +This directory contains the ChibiOS/RT "official" bindings with the FatFS +library by ChaN: http://elm-chan.org + +In order to use FatFS within ChibiOS/RT project, unzip FatFS under +./ext/fatfs then include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +in your makefile. diff --git a/os/various/lwip_bindings/arch/cc.h b/os/various/lwip_bindings/arch/cc.h new file mode 100644 index 000000000..87e900272 --- /dev/null +++ b/os/various/lwip_bindings/arch/cc.h @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __CC_H__ +#define __CC_H__ + +#include + +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef uint32_t mem_ptr_t; + +#define LWIP_PLATFORM_DIAG(x) +#define LWIP_PLATFORM_ASSERT(x) { \ + chSysHalt(); \ +} + +#define BYTE_ORDER LITTLE_ENDIAN +#define LWIP_PROVIDE_ERRNO + +#endif /* __CC_H__ */ diff --git a/os/various/lwip_bindings/arch/perf.h b/os/various/lwip_bindings/arch/perf.h new file mode 100644 index 000000000..81ef4673b --- /dev/null +++ b/os/various/lwip_bindings/arch/perf.h @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START +#define PERF_STOP(x) + +#endif /* __PERF_H__ */ diff --git a/os/various/lwip_bindings/arch/sys_arch.c b/os/various/lwip_bindings/arch/sys_arch.c new file mode 100644 index 000000000..57ed14124 --- /dev/null +++ b/os/various/lwip_bindings/arch/sys_arch.c @@ -0,0 +1,235 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions + +#include "ch.h" + +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/sys.h" +#include "lwip/stats.h" + +#include "arch/cc.h" +#include "arch/sys_arch.h" + +void sys_init(void) { + +} + +err_t sys_sem_new(sys_sem_t *sem, u8_t count) { + + *sem = chHeapAlloc(NULL, sizeof(Semaphore)); + if (*sem == 0) { + SYS_STATS_INC(sem.err); + return ERR_MEM; + } + else { + chSemInit(*sem, (cnt_t)count); + SYS_STATS_INC_USED(sem); + return ERR_OK; + } +} + +void sys_sem_free(sys_sem_t *sem) { + + chHeapFree(*sem); + *sem = SYS_SEM_NULL; + SYS_STATS_DEC(sem.used); +} + +void sys_sem_signal(sys_sem_t *sem) { + + chSemSignal(*sem); +} + +/* CHIBIOS FIX: specific variant of this call to be called from within + a lock.*/ +void sys_sem_signal_S(sys_sem_t *sem) { + + chSemSignalI(*sem); + chSchRescheduleS(); +} + +u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) { + systime_t time, tmo; + + chSysLock(); + tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE; + time = chTimeNow(); + if (chSemWaitTimeoutS(*sem, tmo) != RDY_OK) + time = SYS_ARCH_TIMEOUT; + else + time = chTimeNow() - time; + chSysUnlock(); + return time; +} + +int sys_sem_valid(sys_sem_t *sem) { + return *sem != SYS_SEM_NULL; +} + +// typically called within lwIP after freeing a semaphore +// to make sure the pointer is not left pointing to invalid data +void sys_sem_set_invalid(sys_sem_t *sem) { + *sem = SYS_SEM_NULL; +} + +err_t sys_mbox_new(sys_mbox_t *mbox, int size) { + + *mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size); + if (*mbox == 0) { + SYS_STATS_INC(mbox.err); + return ERR_MEM; + } + else { + chMBInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(Mailbox)), size); + SYS_STATS_INC(mbox.used); + return ERR_OK; + } +} + +void sys_mbox_free(sys_mbox_t *mbox) { + + if (chMBGetUsedCountI(*mbox) != 0) { + // If there are messages still present in the mailbox when the mailbox + // is deallocated, it is an indication of a programming error in lwIP + // and the developer should be notified. + SYS_STATS_INC(mbox.err); + chMBReset(*mbox); + } + chHeapFree(*mbox); + *mbox = SYS_MBOX_NULL; + SYS_STATS_DEC(mbox.used); +} + +void sys_mbox_post(sys_mbox_t *mbox, void *msg) { + + chMBPost(*mbox, (msg_t)msg, TIME_INFINITE); +} + +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) { + + if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) { + SYS_STATS_INC(mbox.err); + return ERR_MEM; + } + return ERR_OK; +} + +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) { + systime_t time, tmo; + + chSysLock(); + tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE; + time = chTimeNow(); + if (chMBFetchS(*mbox, (msg_t *)msg, tmo) != RDY_OK) + time = SYS_ARCH_TIMEOUT; + else + time = chTimeNow() - time; + chSysUnlock(); + return time; +} + +u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) { + + if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) + return SYS_MBOX_EMPTY; + return 0; +} + +int sys_mbox_valid(sys_mbox_t *mbox) { + return *mbox != SYS_MBOX_NULL; +} + +// typically called within lwIP after freeing an mbox +// to make sure the pointer is not left pointing to invalid data +void sys_mbox_set_invalid(sys_mbox_t *mbox) { + *mbox = SYS_MBOX_NULL; +} + +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, + void *arg, int stacksize, int prio) { + + size_t wsz; + void *wsp; + + (void)name; + wsz = THD_WA_SIZE(stacksize); + wsp = chCoreAlloc(wsz); + if (wsp == NULL) + return NULL; + return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg); +} + +sys_prot_t sys_arch_protect(void) { + + chSysLock(); + return 0; +} + +void sys_arch_unprotect(sys_prot_t pval) { + + (void)pval; + chSysUnlock(); +} + +u32_t sys_now(void) { + +#if CH_FREQUENCY == 1000 + return (u32_t)chTimeNow(); +#elif (CH_FREQUENCY / 1000) >= 1 && (CH_FREQUENCY % 1000) == 0 + return ((u32_t)chTimeNow() - 1) / (CH_FREQUENCY / 1000) + 1; +#elif (1000 / CH_FREQUENCY) >= 1 && (1000 % CH_FREQUENCY) == 0 + return ((u32_t)chTimeNow() - 1) * (1000 / CH_FREQUENCY) + 1; +#else + return (u32_t)(((u64_t)(chTimeNow() - 1) * 1000) / CH_FREQUENCY) + 1; +#endif +} diff --git a/os/various/lwip_bindings/arch/sys_arch.h b/os/various/lwip_bindings/arch/sys_arch.h new file mode 100644 index 000000000..6c10607f7 --- /dev/null +++ b/os/various/lwip_bindings/arch/sys_arch.h @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#ifndef __SYS_ARCH_H__ +#define __SYS_ARCH_H__ + +typedef Semaphore * sys_sem_t; +typedef Mailbox * sys_mbox_t; +typedef Thread * sys_thread_t; +typedef int sys_prot_t; + +#define SYS_MBOX_NULL (Mailbox *)0 +#define SYS_THREAD_NULL (Thread *)0 +#define SYS_SEM_NULL (Semaphore *)0 + +/* let sys.h use binary semaphores for mutexes */ +#define LWIP_COMPAT_MUTEX 1 + +#endif /* __SYS_ARCH_H__ */ diff --git a/os/various/lwip_bindings/lwip.mk b/os/various/lwip_bindings/lwip.mk new file mode 100644 index 000000000..afaaf1454 --- /dev/null +++ b/os/various/lwip_bindings/lwip.mk @@ -0,0 +1,54 @@ +# List of the required lwIP files. +LWIP = ${CHIBIOS}/ext/lwip + +LWBINDSRC = \ + $(CHIBIOS)/os/various/lwip_bindings/lwipthread.c \ + $(CHIBIOS)/os/various/lwip_bindings/arch/sys_arch.c + +LWNETIFSRC = \ + ${LWIP}/src/netif/etharp.c + +LWCORESRC = \ + ${LWIP}/src/core/dhcp.c \ + ${LWIP}/src/core/dns.c \ + ${LWIP}/src/core/init.c \ + ${LWIP}/src/core/mem.c \ + ${LWIP}/src/core/memp.c \ + ${LWIP}/src/core/netif.c \ + ${LWIP}/src/core/pbuf.c \ + ${LWIP}/src/core/raw.c \ + ${LWIP}/src/core/stats.c \ + ${LWIP}/src/core/sys.c \ + ${LWIP}/src/core/tcp.c \ + ${LWIP}/src/core/tcp_in.c \ + ${LWIP}/src/core/tcp_out.c \ + ${LWIP}/src/core/udp.c + +LWIPV4SRC = \ + ${LWIP}/src/core/ipv4/autoip.c \ + ${LWIP}/src/core/ipv4/icmp.c \ + ${LWIP}/src/core/ipv4/igmp.c \ + ${LWIP}/src/core/ipv4/inet.c \ + ${LWIP}/src/core/ipv4/inet_chksum.c \ + ${LWIP}/src/core/ipv4/ip.c \ + ${LWIP}/src/core/ipv4/ip_addr.c \ + ${LWIP}/src/core/ipv4/ip_frag.c \ + ${LWIP}/src/core/def.c \ + ${LWIP}/src/core/timers.c + +LWAPISRC = \ + ${LWIP}/src/api/api_lib.c \ + ${LWIP}/src/api/api_msg.c \ + ${LWIP}/src/api/err.c \ + ${LWIP}/src/api/netbuf.c \ + ${LWIP}/src/api/netdb.c \ + ${LWIP}/src/api/netifapi.c \ + ${LWIP}/src/api/sockets.c \ + ${LWIP}/src/api/tcpip.c + +LWSRC = $(LWBINDSRC) $(LWNETIFSRC) $(LWCORESRC) $(LWIPV4SRC) $(LWAPISRC) + +LWINC = \ + $(CHIBIOS)/os/various/lwip_bindings \ + ${LWIP}/src/include \ + ${LWIP}/src/include/ipv4 diff --git a/os/various/lwip_bindings/lwipthread.c b/os/various/lwip_bindings/lwipthread.c new file mode 100644 index 000000000..38ef8cfd2 --- /dev/null +++ b/os/various/lwip_bindings/lwipthread.c @@ -0,0 +1,303 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/** + * @file lwipthread.c + * @brief LWIP wrapper thread code. + * @addtogroup LWIP_THREAD + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "evtimer.h" + +#include "lwipthread.h" + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include +#include "netif/etharp.h" +#include "netif/ppp_oe.h" + +#define PERIODIC_TIMER_ID 1 +#define FRAME_RECEIVED_ID 2 + +/** + * Stack area for the LWIP-MAC thread. + */ +WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); + +/* + * Initialization. + */ +static void low_level_init(struct netif *netif) { + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an Ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Do whatever else is needed to initialize interface. */ +} + +/* + * Transmits a frame. + */ +static err_t low_level_output(struct netif *netif, struct pbuf *p) { + struct pbuf *q; + MACTransmitDescriptor td; + + (void)netif; + if (macWaitTransmitDescriptor(ÐD1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK) + return ERR_TIMEOUT; + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = p; q != NULL; q = q->next) + macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len); + macReleaseTransmitDescriptor(&td); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/* + * Receives a frame. + */ +static struct pbuf *low_level_input(struct netif *netif) { + MACReceiveDescriptor rd; + struct pbuf *p, *q; + u16_t len; + + (void)netif; + if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) == RDY_OK) { + len = (u16_t)rd.size; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = p; q != NULL; q = q->next) + macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len); + macReleaseReceiveDescriptor(&rd); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } + else { + macReleaseReceiveDescriptor(&rd); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + } + return p; + } + return NULL; +} + +/* + * Initialization. + */ +static err_t ethernetif_init(struct netif *netif) { +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED); + + netif->state = NULL; + netif->name[0] = LWIP_IFNAME0; + netif->name[1] = LWIP_IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +/** + * @brief LWIP handling thread. + * + * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL + * @return The function does not return. + */ +msg_t lwip_thread(void *p) { + EvTimer evt; + EventListener el0, el1; + struct ip_addr ip, gateway, netmask; + static struct netif thisif; + static const MACConfig mac_config = {thisif.hwaddr}; + + chRegSetThreadName("lwipthread"); + + /* Initializes the thing.*/ + tcpip_init(NULL, NULL); + + /* TCP/IP parameters, runtime or compile time.*/ + if (p) { + struct lwipthread_opts *opts = p; + unsigned i; + + for (i = 0; i < 6; i++) + thisif.hwaddr[i] = opts->macaddress[i]; + ip.addr = opts->address; + gateway.addr = opts->gateway; + netmask.addr = opts->netmask; + } + else { + thisif.hwaddr[0] = LWIP_ETHADDR_0; + thisif.hwaddr[1] = LWIP_ETHADDR_1; + thisif.hwaddr[2] = LWIP_ETHADDR_2; + thisif.hwaddr[3] = LWIP_ETHADDR_3; + thisif.hwaddr[4] = LWIP_ETHADDR_4; + thisif.hwaddr[5] = LWIP_ETHADDR_5; + LWIP_IPADDR(&ip); + LWIP_GATEWAY(&gateway); + LWIP_NETMASK(&netmask); + } + macStart(ÐD1, &mac_config); + netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); + + netif_set_default(&thisif); + netif_set_up(&thisif); + + /* Setup event sources.*/ + evtInit(&evt, LWIP_LINK_POLL_INTERVAL); + evtStart(&evt); + chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); + chEvtRegisterMask(macGetReceiveEventSource(ÐD1), &el1, FRAME_RECEIVED_ID); + chEvtAddEvents(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(LWIP_THREAD_PRIORITY); + + while (TRUE) { + eventmask_t mask = chEvtWaitAny(ALL_EVENTS); + if (mask & PERIODIC_TIMER_ID) { + bool_t current_link_status = macPollLinkStatus(ÐD1); + if (current_link_status != netif_is_link_up(&thisif)) { + if (current_link_status) + tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up, + &thisif, 0); + else + tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down, + &thisif, 0); + } + } + if (mask & FRAME_RECEIVED_ID) { + struct pbuf *p; + while ((p = low_level_input(&thisif)) != NULL) { + struct eth_hdr *ethhdr = p->payload; + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (thisif.input(p, &thisif) == ERR_OK) + break; + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + default: + pbuf_free(p); + } + } + } + } + return 0; +} + +/** @} */ diff --git a/os/various/lwip_bindings/lwipthread.h b/os/various/lwip_bindings/lwipthread.h new file mode 100644 index 000000000..fe4de2870 --- /dev/null +++ b/os/various/lwip_bindings/lwipthread.h @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lwipthread.h + * @brief LWIP wrapper thread macros and structures. + * @addtogroup LWIP_THREAD + * @{ + */ + +#ifndef _LWIPTHREAD_H_ +#define _LWIPTHREAD_H_ + +#include + +/** @brief MAC thread priority.*/ +#ifndef LWIP_THREAD_PRIORITY +#define LWIP_THREAD_PRIORITY LOWPRIO +#endif + +/** @brief MAC thread stack size. */ +#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define LWIP_THREAD_STACK_SIZE 512 +#endif + +/** @brief Link poll interval. */ +#if !defined(LWIP_LINK_POLL_INTERVAL) || defined(__DOXYGEN__) +#define LWIP_LINK_POLL_INTERVAL S2ST(5) +#endif + +/** @brief IP Address. */ +#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) +#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 20) +#endif + +/** @brief IP Gateway. */ +#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__) +#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1) +#endif + +/** @brief IP netmask. */ +#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__) +#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0) +#endif + +/** @brief Transmission timeout. */ +#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) +#define LWIP_SEND_TIMEOUT 50 +#endif + +/** @brief Link speed. */ +#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__) +#define LWIP_LINK_SPEED 100000000 +#endif + +/** @brief MAC Address byte 0. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_0 0xC2 +#endif + +/** @brief MAC Address byte 1. */ +#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_1 0xAF +#endif + +/** @brief MAC Address byte 2. */ +#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_2 0x51 +#endif + +/** @brief MAC Address byte 3. */ +#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_3 0x03 +#endif + +/** @brief MAC Address byte 4. */ +#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_4 0xCF +#endif + +/** @brief MAC Address byte 5. */ +#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_5 0x46 +#endif + +/** @brief Interface name byte 0. */ +#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__) +#define LWIP_IFNAME0 'm' +#endif + +/** @brief Interface name byte 1. */ +#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__) +#define LWIP_IFNAME1 's' +#endif + +/** + * @brief Runtime TCP/IP settings. + */ +struct lwipthread_opts { + uint8_t *macaddress; + uint32_t address; + uint32_t netmask; + uint32_t gateway; +}; + +extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t lwip_thread(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _LWIPTHREAD_H_ */ + +/** @} */ diff --git a/os/various/lwip_bindings/readme.txt b/os/various/lwip_bindings/readme.txt new file mode 100644 index 000000000..8a7a89e8c --- /dev/null +++ b/os/various/lwip_bindings/readme.txt @@ -0,0 +1,6 @@ +This directory contains the ChibiOS/RT "official" bindings with the lwIP +TCP/IP stack: http://savannah.nongnu.org/projects/lwip + +In order to use FatFS within ChibiOS/RT project, unzip FatFS under +./ext/lwip-1.4.0 then include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +in your makefile. diff --git a/os/various/memstreams.c b/os/various/memstreams.c new file mode 100644 index 000000000..11dd5b8ac --- /dev/null +++ b/os/various/memstreams.c @@ -0,0 +1,113 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file memstreams.c + * @brief Memory streams code. + * + * @addtogroup memory_streams + * @{ + */ + +#include + +#include "ch.h" +#include "memstreams.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + MemoryStream *msp = ip; + + if (msp->size - msp->eos < n) + n = msp->size - msp->eos; + memcpy(msp->buffer + msp->eos, bp, n); + msp->eos += n; + return n; +} + +static size_t reads(void *ip, uint8_t *bp, size_t n) { + MemoryStream *msp = ip; + + if (msp->eos - msp->offset < n) + n = msp->eos - msp->offset; + memcpy(bp, msp->buffer + msp->offset, n); + msp->offset += n; + return n; +} + +static msg_t put(void *ip, uint8_t b) { + MemoryStream *msp = ip; + + if (msp->size - msp->eos <= 0) + return RDY_RESET; + *(msp->buffer + msp->eos) = b; + msp->eos += 1; + return RDY_OK; +} + +static msg_t get(void *ip) { + uint8_t b; + MemoryStream *msp = ip; + + if (msp->eos - msp->offset <= 0) + return RDY_RESET; + b = *(msp->buffer + msp->offset); + msp->offset += 1; + return b; +} + +static const struct MemStreamVMT vmt = {writes, reads, put, get}; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Memory stream object initialization. + * + * @param[out] msp pointer to the @p MemoryStream object to be initialized + * @param[in] buffer pointer to the memory buffer for the memory stream + * @param[in] size total size of the memory stream buffer + * @param[in] eos initial End Of Stream offset. Normally you need to + * put this to zero for RAM buffers or equal to @p size + * for ROM streams. + */ +void msObjectInit(MemoryStream *msp, uint8_t *buffer, + size_t size, size_t eos) { + + msp->vmt = &vmt; + msp->buffer = buffer; + msp->size = size; + msp->eos = eos; + msp->offset = 0; +} + +/** @} */ diff --git a/os/various/memstreams.h b/os/various/memstreams.h new file mode 100644 index 000000000..3daa8ee92 --- /dev/null +++ b/os/various/memstreams.h @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file memstreams.h + * @brief Memory streams structures and macros. + + * @addtogroup memory_streams + * @{ + */ + +#ifndef _MEMSTREAMS_H_ +#define _MEMSTREAMS_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief @p RamStream specific data. + */ +#define _memory_stream_data \ + _base_sequential_stream_data \ + /* Pointer to the stream buffer.*/ \ + uint8_t *buffer; \ + /* Size of the stream.*/ \ + size_t size; \ + /* Current end of stream.*/ \ + size_t eos; \ + /* Current read offset.*/ \ + size_t offset; + +/** + * @brief @p MemStream virtual methods table. + */ +struct MemStreamVMT { + _base_sequential_stream_methods +}; + +/** + * @extends BaseSequentialStream + * + * @brief Memory stream object. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct MemStreamVMT *vmt; + _memory_stream_data +} MemoryStream; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void msObjectInit(MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos); +#ifdef __cplusplus +} +#endif + +#endif /* _MEMSTREAMS_H_ */ + +/** @} */ diff --git a/os/various/shell.c b/os/various/shell.c new file mode 100644 index 000000000..abdfc0b86 --- /dev/null +++ b/os/various/shell.c @@ -0,0 +1,286 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file shell.c + * @brief Simple CLI shell code. + * + * @addtogroup SHELL + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "shell.h" +#include "chprintf.h" + +/** + * @brief Shell termination event source. + */ +EventSource shell_terminated; + +static char *_strtok(char *str, const char *delim, char **saveptr) { + char *token; + if (str) + *saveptr = str; + token = *saveptr; + + if (!token) + return NULL; + + token += strspn(token, delim); + *saveptr = strpbrk(token, delim); + if (*saveptr) + *(*saveptr)++ = '\0'; + + return *token ? token : NULL; +} + +static void usage(BaseSequentialStream *chp, char *p) { + + chprintf(chp, "Usage: %s\r\n", p); +} + +static void list_commands(BaseSequentialStream *chp, const ShellCommand *scp) { + + while (scp->sc_name != NULL) { + chprintf(chp, "%s ", scp->sc_name); + scp++; + } +} + +static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) { + + (void)argv; + if (argc > 0) { + usage(chp, "info"); + return; + } + + chprintf(chp, "Kernel: %s\r\n", CH_KERNEL_VERSION); +#ifdef CH_COMPILER_NAME + chprintf(chp, "Compiler: %s\r\n", CH_COMPILER_NAME); +#endif + chprintf(chp, "Architecture: %s\r\n", CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + chprintf(chp, "Core Variant: %s\r\n", CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + chprintf(chp, "Port Info: %s\r\n", CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + chprintf(chp, "Platform: %s\r\n", PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + chprintf(chp, "Board: %s\r\n", BOARD_NAME); +#endif +#ifdef __DATE__ +#ifdef __TIME__ + chprintf(chp, "Build time: %s%s%s\r\n", __DATE__, " - ", __TIME__); +#endif +#endif +} + +static void cmd_systime(BaseSequentialStream *chp, int argc, char *argv[]) { + + (void)argv; + if (argc > 0) { + usage(chp, "systime"); + return; + } + chprintf(chp, "%lu\r\n", (unsigned long)chTimeNow()); +} + +/** + * @brief Array of the default commands. + */ +static ShellCommand local_commands[] = { + {"info", cmd_info}, + {"systime", cmd_systime}, + {NULL, NULL} +}; + +static bool_t cmdexec(const ShellCommand *scp, BaseSequentialStream *chp, + char *name, int argc, char *argv[]) { + + while (scp->sc_name != NULL) { + if (strcasecmp(scp->sc_name, name) == 0) { + scp->sc_function(chp, argc, argv); + return FALSE; + } + scp++; + } + return TRUE; +} + +/** + * @brief Shell thread function. + * + * @param[in] p pointer to a @p BaseSequentialStream object + * @return Termination reason. + * @retval RDY_OK terminated by command. + * @retval RDY_RESET terminated by reset condition on the I/O channel. + */ +static msg_t shell_thread(void *p) { + int n; + msg_t msg = RDY_OK; + BaseSequentialStream *chp = ((ShellConfig *)p)->sc_channel; + const ShellCommand *scp = ((ShellConfig *)p)->sc_commands; + char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH]; + char *args[SHELL_MAX_ARGUMENTS + 1]; + + chRegSetThreadName("shell"); + chprintf(chp, "\r\nChibiOS/RT Shell\r\n"); + while (TRUE) { + chprintf(chp, "ch> "); + if (shellGetLine(chp, line, sizeof(line))) { + chprintf(chp, "\r\nlogout"); + break; + } + lp = _strtok(line, " \t", &tokp); + cmd = lp; + n = 0; + while ((lp = _strtok(NULL, " \t", &tokp)) != NULL) { + if (n >= SHELL_MAX_ARGUMENTS) { + chprintf(chp, "too many arguments\r\n"); + cmd = NULL; + break; + } + args[n++] = lp; + } + args[n] = NULL; + if (cmd != NULL) { + if (strcasecmp(cmd, "exit") == 0) { + if (n > 0) { + usage(chp, "exit"); + continue; + } + break; + } + else if (strcasecmp(cmd, "help") == 0) { + if (n > 0) { + usage(chp, "help"); + continue; + } + chprintf(chp, "Commands: help exit "); + list_commands(chp, local_commands); + if (scp != NULL) + list_commands(chp, scp); + chprintf(chp, "\r\n"); + } + else if (cmdexec(local_commands, chp, cmd, n, args) && + ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) { + chprintf(chp, "%s", cmd); + chprintf(chp, " ?\r\n"); + } + } + } + /* Atomically broadcasting the event source and terminating the thread, + there is not a chSysUnlock() because the thread terminates upon return.*/ + chSysLock(); + chEvtBroadcastI(&shell_terminated); + chThdExitS(msg); + return 0; /* Never executed.*/ +} + +/** + * @brief Shell manager initialization. + */ +void shellInit(void) { + + chEvtInit(&shell_terminated); +} + +/** + * @brief Spawns a new shell. + * @pre @p CH_USE_MALLOC_HEAP and @p CH_USE_DYNAMIC must be enabled. + * + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] size size of the shell working area to be allocated + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. + * @retval NULL thread creation failed because memory allocation. + */ +#if CH_USE_HEAP && CH_USE_DYNAMIC +Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { + + return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp); +} +#endif + +/** + * @brief Create statically allocated shell thread. + * + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] wsp pointer to a working area dedicated to the shell thread stack + * @param[in] size size of the shell working area + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. + */ +Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio) { + + return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp); +} + +/** + * @brief Reads a whole line from the input channel. + * + * @param[in] chp pointer to a @p BaseSequentialStream object + * @param[in] line pointer to the line buffer + * @param[in] size buffer maximum length + * @return The operation status. + * @retval TRUE the channel was reset or CTRL-D pressed. + * @retval FALSE operation successful. + */ +bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size) { + char *p = line; + + while (TRUE) { + char c; + + if (chSequentialStreamRead(chp, (uint8_t *)&c, 1) == 0) + return TRUE; + if (c == 4) { + chprintf(chp, "^D"); + return TRUE; + } + if (c == 8) { + if (p != line) { + chSequentialStreamPut(chp, c); + chSequentialStreamPut(chp, 0x20); + chSequentialStreamPut(chp, c); + p--; + } + continue; + } + if (c == '\r') { + chprintf(chp, "\r\n"); + *p = 0; + return FALSE; + } + if (c < 0x20) + continue; + if (p < line + size - 1) { + chSequentialStreamPut(chp, c); + *p++ = (char)c; + } + } +} + +/** @} */ diff --git a/os/various/shell.h b/os/various/shell.h new file mode 100644 index 000000000..384a6a200 --- /dev/null +++ b/os/various/shell.h @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file shell.h + * @brief Simple CLI shell header. + * + * @addtogroup SHELL + * @{ + */ + +#ifndef _SHELL_H_ +#define _SHELL_H_ + +/** + * @brief Shell maximum input line length. + */ +#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__) +#define SHELL_MAX_LINE_LENGTH 64 +#endif + +/** + * @brief Shell maximum arguments per command. + */ +#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__) +#define SHELL_MAX_ARGUMENTS 4 +#endif + +/** + * @brief Command handler function type. + */ +typedef void (*shellcmd_t)(BaseSequentialStream *chp, int argc, char *argv[]); + +/** + * @brief Custom command entry type. + */ +typedef struct { + const char *sc_name; /**< @brief Command name. */ + shellcmd_t sc_function; /**< @brief Command function. */ +} ShellCommand; + +/** + * @brief Shell descriptor type. + */ +typedef struct { + BaseSequentialStream *sc_channel; /**< @brief I/O channel associated + to the shell. */ + const ShellCommand *sc_commands; /**< @brief Shell extra commands + table. */ +} ShellConfig; + +#if !defined(__DOXYGEN__) +extern EventSource shell_terminated; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void shellInit(void); + Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio); + Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio); + bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size); +#ifdef __cplusplus +} +#endif + +#endif /* _SHELL_H_ */ + +/** @} */ diff --git a/os/various/syscalls.c b/os/various/syscalls.c new file mode 100644 index 000000000..fd2449b40 --- /dev/null +++ b/os/various/syscalls.c @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* +* **** This file incorporates work covered by the following copyright and **** +* **** permission notice: **** +* +* Copyright (c) 2009 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 28.03.09 mifi First Version, based on the original syscall.c from +* newlib version 1.17.0 +* 17.08.09 gdisirio Modified the file for use under ChibiOS/RT +* 15.11.09 gdisirio Added read and write handling +****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "ch.h" +#if defined(STDOUT_SD) || defined(STDIN_SD) +#include "hal.h" +#endif + +/***************************************************************************/ + +int _read_r(struct _reent *r, int file, char * ptr, int len) +{ + (void)r; +#if defined(STDIN_SD) + if (!len || (file != 0)) { + __errno_r(r) = EINVAL; + return -1; + } + len = sdRead(&STDIN_SD, (uint8_t *)ptr, (size_t)len); + return len; +#else + (void)file; + (void)ptr; + (void)len; + __errno_r(r) = EINVAL; + return -1; +#endif +} + +/***************************************************************************/ + +int _lseek_r(struct _reent *r, int file, int ptr, int dir) +{ + (void)r; + (void)file; + (void)ptr; + (void)dir; + + return 0; +} + +/***************************************************************************/ + +int _write_r(struct _reent *r, int file, char * ptr, int len) +{ + (void)r; + (void)file; + (void)ptr; +#if defined(STDOUT_SD) + if (file != 1) { + __errno_r(r) = EINVAL; + return -1; + } + sdWrite(&STDOUT_SD, (uint8_t *)ptr, (size_t)len); +#endif + return len; +} + +/***************************************************************************/ + +int _close_r(struct _reent *r, int file) +{ + (void)r; + (void)file; + + return 0; +} + +/***************************************************************************/ + +caddr_t _sbrk_r(struct _reent *r, int incr) +{ +#if CH_USE_MEMCORE + void *p; + + chDbgCheck(incr > 0, "_sbrk_r"); + + (void)r; + p = chCoreAlloc((size_t)incr); + if (p == NULL) { + __errno_r(r) = ENOMEM; + return (caddr_t)-1; + } + return (caddr_t)p; +#else + __errno_r(r) = ENOMEM; + return (caddr_t)-1; +#endif +} + +/***************************************************************************/ + +int _fstat_r(struct _reent *r, int file, struct stat * st) +{ + (void)r; + (void)file; + + memset(st, 0, sizeof(*st)); + st->st_mode = S_IFCHR; + return 0; +} + +/***************************************************************************/ + +int _isatty_r(struct _reent *r, int fd) +{ + (void)r; + (void)fd; + + return 1; +} + +/*** EOF ***/ diff --git a/os/various/usb_msc.c b/os/various/usb_msc.c new file mode 100644 index 000000000..61f4202d3 --- /dev/null +++ b/os/various/usb_msc.c @@ -0,0 +1,299 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*-* + * @file usb_msc.c + * @brief USB Mass Storage Class code. + * + * @addtogroup USB_MSC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "usb_msc.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Zero-filled constant buffer. + */ +static const uint8_t zerobuf[4] = {0, 0, 0, 0}; + +/** + * @brief Answer to the INQUIRY command. + */ +static const uint8_t scsi_inquiry_data[] = { + 0x00, /* Direct Access Device. */ + 0x80, /* RMB = 1: Removable Medium. */ + 0x02, /* ISO, ECMA, ANSI = 2. */ + 0x00, /* UFI response format. */ + + 36 - 4, /* Additional Length. */ + 0x00, + 0x00, + 0x00, + /* Vendor Identification */ + 'C', 'h', 'i', 'b', 'i', 'O', 'S', ' ', + /* Product Identification */ + 'S', 'D', ' ', 'F', 'l', 'a', 's', 'h', + ' ', 'D', 'i', 's', 'k', ' ', ' ', ' ', + /* Product Revision Level */ + '1', '.', '0', ' ' +}; + +/** + * @brief Generic buffer. + */ +uint8_t buf[16]; + +/*===========================================================================*/ +/* MMC interface code. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SCSI emulation code. */ +/*===========================================================================*/ + +static uint8_t scsi_read_format_capacities(uint32_t *nblocks, + uint32_t *secsize) { + + *nblocks = 1024; + *secsize = 512; + return 3; /* No Media.*/ +} + +/*===========================================================================*/ +/* Mass Storage Class related code. */ +/*===========================================================================*/ + +/** + * @brief MSC state machine current state. + */ +static mscstate_t msc_state; + +/** + * @brief Received CBW. + */ +static msccbw_t CBW; + +/** + * @brief CSW to be transmitted. + */ +static msccsw_t CSW; + +/** + * @brief MSC state machine initialization. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void msc_reset(USBDriver *usbp) { + + msc_state = MSC_IDLE; + chSysLockFromIsr(); + usbStartReceiveI(usbp, MSC_DATA_OUT_EP, (uint8_t *)&CBW, sizeof CBW); + chSysUnlockFromIsr(); +} + +static void msc_transmit(USBDriver *usbp, const uint8_t *p, size_t n) { + + if (n > CBW.dCBWDataTransferLength) + n = CBW.dCBWDataTransferLength; + CSW.dCSWDataResidue = CBW.dCBWDataTransferLength - (uint32_t)n; + chSysLockFromIsr(); + usbStartTransmitI(usbp, MSC_DATA_IN_EP, p, n); + chSysUnlockFromIsr(); +} + +static void msc_sendstatus(USBDriver *usbp) { + + msc_state = MSC_SENDING_CSW; + chSysLockFromIsr(); + usbStartTransmitI(usbp, MSC_DATA_IN_EP, (uint8_t *)&CSW, sizeof CSW); + chSysUnlockFromIsr(); +} + +static bool_t msc_decode(USBDriver *usbp) { + uint32_t nblocks, secsize; + + switch (CBW.CBWCB[0]) { + case SCSI_REQUEST_SENSE: + break; + case SCSI_INQUIRY: + msc_transmit(usbp, (uint8_t *)&scsi_inquiry_data, + sizeof scsi_inquiry_data); + CSW.bCSWStatus = MSC_CSW_STATUS_PASSED; + break; + case SCSI_READ_FORMAT_CAPACITIES: + buf[8] = scsi_read_format_capacities(&nblocks, &secsize); + buf[0] = buf[1] = buf[2] = 0; + buf[3] = 8; + buf[4] = (uint8_t)(nblocks >> 24); + buf[5] = (uint8_t)(nblocks >> 16); + buf[6] = (uint8_t)(nblocks >> 8); + buf[7] = (uint8_t)(nblocks >> 0); + buf[9] = (uint8_t)(secsize >> 16); + buf[10] = (uint8_t)(secsize >> 8); + buf[11] = (uint8_t)(secsize >> 0); + msc_transmit(usbp, buf, 12); + CSW.bCSWStatus = MSC_CSW_STATUS_PASSED; + break; + default: + return TRUE; + } + return FALSE; +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Default requests hook. + * @details The application must use this function as callback for the + * messages hook. + * The following requests are emulated: + * - MSC_GET_MAX_LUN_COMMAND. + * - MSC_MASS_STORAGE_RESET_COMMAND. + * . + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The hook status. + * @retval TRUE Message handled internally. + * @retval FALSE Message not handled. + */ +bool_t mscRequestsHook(USBDriver *usbp) { + + if ((usbp->setup[0] & (USB_RTYPE_TYPE_MASK | USB_RTYPE_RECIPIENT_MASK)) == + (USB_RTYPE_TYPE_CLASS | USB_RTYPE_RECIPIENT_INTERFACE)) { + switch (usbp->setup[1]) { + case MSC_GET_MAX_LUN_COMMAND: + usbSetupTransfer(usbp, (uint8_t *)zerobuf, 1, NULL); + return TRUE; + case MSC_MASS_STORAGE_RESET_COMMAND: + msc_reset(usbp); + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + default: + return FALSE; + } + } + return FALSE; +} + +/** + * @brief Default data transmitted callback. + * @details The application must use this function as callback for the IN + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void mscDataTransmitted(USBDriver *usbp, usbep_t ep) { + + switch (msc_state) { + case MSC_DATA_IN: + CSW.dCSWSignature = MSC_CSW_SIGNATURE; + CSW.dCSWTag = CBW.dCBWTag; + chSysLockFromIsr(); + usbStartTransmitI(usbp, ep, (uint8_t *)&CSW, sizeof CSW); + chSysUnlockFromIsr(); + msc_state = MSC_SENDING_CSW; + break; + case MSC_SENDING_CSW: + chSysLockFromIsr(); + usbStartReceiveI(usbp, MSC_DATA_OUT_EP, (uint8_t *)&CBW, sizeof CBW); + chSysUnlockFromIsr(); + msc_state = MSC_IDLE; + break; + default: + ; + } +} + +/** + * @brief Default data received callback. + * @details The application must use this function as callback for the OUT + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void mscDataReceived(USBDriver *usbp, usbep_t ep) { + size_t n; + + n = usbGetReceiveTransactionSizeI(usbp, ep); + switch (msc_state) { + case MSC_IDLE: + if ((n != sizeof(msccbw_t)) || (CBW.dCBWSignature != MSC_CBW_SIGNATURE)) + goto stall_out; /* 6.6.1 */ + + /* Decoding SCSI command.*/ + if (msc_decode(usbp)) { + if (CBW.dCBWDataTransferLength == 0) { + CSW.bCSWStatus = MSC_CSW_STATUS_FAILED; + CSW.dCSWDataResidue = 0; + msc_sendstatus(usbp); + return; + } + goto stall_both; + } + + /* Commands with zero transfer length, 5.1.*/ + if (CBW.dCBWDataTransferLength == 0) { + msc_sendstatus(usbp); + return; + } + + /* Transfer direction.*/ + if (CBW.bmCBWFlags & 0x80) { + /* IN, Device to Host.*/ + msc_state = MSC_DATA_IN; + } + else { + /* OUT, Host to Device.*/ + msc_state = MSC_DATA_OUT; + } + break; + case MSC_DATA_OUT: + break; + default: + ; + } + return; +stall_out: + msc_state = MSC_ERROR; + chSysLockFromIsr(); + usbStallReceiveI(usbp, ep); + chSysUnlockFromIsr(); + return; +stall_both: + msc_state = MSC_ERROR; + chSysLockFromIsr(); + usbStallTransmitI(usbp, ep); + usbStallReceiveI(usbp, ep); + chSysUnlockFromIsr(); + return; +} + +/** @} */ diff --git a/os/various/usb_msc.h b/os/various/usb_msc.h new file mode 100644 index 000000000..5e5a80c1f --- /dev/null +++ b/os/various/usb_msc.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*-* + * @file usb_msc.h + * @brief USB Mass Storage Class header. + * + * @addtogroup USB_MSC + * @{ + */ + +#ifndef _USB_MSC_H_ +#define _USB_MSC_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define MSC_CBW_SIGNATURE 0x43425355 +#define MSC_CSW_SIGNATURE 0x53425355 + +#define MSC_GET_MAX_LUN_COMMAND 0xFE +#define MSC_MASS_STORAGE_RESET_COMMAND 0xFF + +#define MSC_CSW_STATUS_PASSED 0 +#define MSC_CSW_STATUS_FAILED 1 +#define MSC_CSW_STATUS_PHASE_ERROR 2 + + +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_MODE_SENSE10 0x5A +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_READ6 0x08 +#define SCSI_READ10 0x28 +#define SCSI_READ12 0xA8 +#define SCSI_READ16 0x88 + +#define SCSI_READ_CAPACITY10 0x25 +#define SCSI_READ_CAPACITY16 0x9E + +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_WRITE6 0x0A +#define SCSI_WRITE10 0x2A +#define SCSI_WRITE12 0xAA +#define SCSI_WRITE16 0x8A + +#define SCSI_VERIFY10 0x2F +#define SCSI_VERIFY12 0xAF +#define SCSI_VERIFY16 0x8F + +#define SCSI_SEND_DIAGNOSTIC 0x1D +#define SCSI_READ_FORMAT_CAPACITIES 0x23 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Endpoint number for bulk IN. + */ +#if !defined(MSC_DATA_IN_EP) || defined(__DOXYGEN__) +#define MSC_DATA_IN_EP 1 +#endif + +/** + * @brief Endpoint number for bulk OUT. + */ +#if !defined(MSC_DATA_OUT_EP) || defined(__DOXYGEN__) +#define MSC_DATA_OUT_EP 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of the MSC possible states. + */ +typedef enum { + MSC_IDLE = 0, + MSC_DATA_OUT, + MSC_DATA_IN, + MSC_SENDING_CSW, + MSC_ERROR +} mscstate_t; + +/** + * @brief CBW structure. + */ +struct CBW { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +}; + +/** + * @brief CSW structure. + */ +struct CSW { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +}; + +/** + * @brief Type of a CBW structure. + */ +typedef struct CBW msccbw_t; + +/** + * @brief Type of a CSW structure. + */ +typedef struct CSW msccsw_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + bool_t mscRequestsHook(USBDriver *usbp); + void mscDataTransmitted(USBDriver *usbp, usbep_t ep); + void mscDataReceived(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* _USB_MSC_H_ */ + +/** @} */ diff --git a/os/various/various.dox b/os/various/various.dox new file mode 100644 index 000000000..57c37829c --- /dev/null +++ b/os/various/various.dox @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup various Various + * + * @brief Utilities Library. + * @details This is a collection of useful library code that is not part of + * the base kernel services. + *

    Notes

    + * The library code does not follow the same naming convention of the + * system APIs in order to make very clear that it is not "core" code.
    + * The main difference is that library code is not formally tested in the + * test suite but through usage in the various demo applications. + */ + +/** + * @defgroup cpp_library C++ Wrapper + * + * @brief C++ wrapper module. + * @details This module allows to use the ChibiOS/RT functionalities + * from C++ as classes and objects rather the traditional "C" APIs. + * + * @ingroup various + */ + +/** + * @defgroup memory_streams Memory Streams + * + * @brief Memory Streams. + * @details This module allows to use a memory area (RAM or ROM) using a + * @ref data_streams interface. + * + * @ingroup various + */ + +/** + * @defgroup event_timer Periodic Events Timer + * + * @brief Periodic Event Timer. + * @details This timer generates an event at regular intervals. The + * listening threads can use the event to perform time related + * activities. Multiple threads can listen to the same timer. + * + * @ingroup various + */ + +/** + * @defgroup SHELL Command Shell + * + * @brief Small extendible command line shell. + * @details This module implements a generic extendible command line interface. + * The CLI just requires an I/O channel (@p BaseChannel), more + * commands can be added to the shell using the configuration + * structure. + * + * @ingroup various + */ + +/** + * @defgroup chrtclib RTC time conversion utilities + * + * @brief RTC time conversion utilities. + * + * @ingroup various + */ + +/** + * @defgroup chprintf System formatted print + * + * @brief System formatted print service. + * @details This module implements printf()-like function able to send data + * to any module implementing a @p BaseSequentialStream interface. + * + * @ingroup various + */ diff --git a/readme.txt b/readme.txt new file mode 100644 index 000000000..89b08a66a --- /dev/null +++ b/readme.txt @@ -0,0 +1,2661 @@ +***************************************************************************** +*** Files Organization *** +***************************************************************************** + +--{root} - ChibiOS/RT directory. + +--readme.txt - This file. + +--documentation.html - Shortcut to the web documentation page. + +--todo.txt - Current plan (development/unstable versions only). + +--license.txt - GPL license text. + +--exception.txt - GPL exception text (stable releases only). + +--boards/ - Board support files. + +--demos/ - Demo projects. + +--docs/ - Documentation. + | +--html/ - Local HTML documentation (after rebuild). + | +--reports/ - Test reports. + | +--src/ - Documentation source files (required for rebuild). + | +--rsc/ - Documentation resource files (required for rebuild). + | +--Doxyfile - Doxygen project file (required for rebuild). + | +--index.html - Local documentation access (after rebuild). + +--ext/ - External libraries, not part of ChibiOS/RT. + +--os/ - ChibiOS/RT files. + | +--hal/ - Hardware Abstraction Layer. + | | +--include/ - HAL high level headers. + | | +--src/ - HAL high level source. + | | +--platforms/ - HAL low level drivers implementations. + | | | +--AT91SAM7/ - Drivers for AT91SAM7 platform. + | | | +--AVR/ - Drivers for AVR platform. + | | | +--LPC11Uxx/ - Drivers for LPC11Uxx platform. + | | | +--LPC11xx/ - Drivers for LPC11xx platform. + | | | +--LPC13xx/ - Drivers for LPC13xx platform. + | | | +--LPC214x/ - Drivers for LPC214x platform. + | | | +--LPC8xx/ - Drivers for LPC8xx platform. + | | | +--MSP430/ - Drivers for MSP430 platform. + | | | +--SPC5xx/ - Drivers for all SPC5xx platform (common). + | | | +--SPC560BCxx/ - Drivers for SPC560BCxx platform. + | | | +--SPC560Pxx/ - Drivers for SPC560Pxx platform. + | | | +--SPC563Mxx/ - Drivers for SPC563Mxx platform. + | | | +--SPC564Axx/ - Drivers for SPC564Axx platform. + | | | +--SPC5ELxx/ - Drivers for SPC56ELxx platform. + | | | +--STM32/ - Drivers for STM32 platform (common). + | | | +--STM32F0xx/ - Drivers for STM32F0xx platform. + | | | +--STM32F1xx/ - Drivers for STM32F1xx platform. + | | | +--STM32F30x/ - Drivers for STM32F30x platform. + | | | +--STM32F37x/ - Drivers for STM32F37x platform. + | | | +--STM32F4xx/ - Drivers for STM32F4xx/STM32F2xx platforms. + | | | +--STM32L1xx/ - Drivers for STM32L1xx platform. + | | | +--STM8L/ - Drivers for STM8L platform. + | | | +--STM8S/ - Drivers for STM8S platform. + | | | +--Posix/ - Drivers for x86 Linux/OSX simulator platform. + | | | +--Win32/ - Drivers for x86 Win32 simulator platform. + | | +--templates/ - Driver template files. + | | +--meta/ - Driver meta templates. + | +--ports/ - Port files for the various architectures. + | | +--GCC/ - Ports for the GCC compiler. + | | | +--ARM/ - Port files for ARM7 and ARM9 architectures. + | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M). + | | | +--PPC/ - Port files for PowerPC architecture. + | | | +--AVR/ - Port files for AVR architecture. + | | | +--MSP430/ - Port files for MSP430 architecture. + | | | +--SIMIA32/ - Port files for SIMIA32 simulator architecture. + | | +--IAR/ - Ports for the IAR compiler. + | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M). + | | | +--STM8/ - Port files for STM8 architecture. + | | +--RVCT/ - Ports for the Keil RVCT compiler. + | | | +--ARMCMx/ - Port files for ARMCMx architectures (ARMv6/7-M). + | | +--cosmic/ - Ports for the Cosmic compiler. + | | | +--STM8/ - Port files for STM8 architecture. + | | +--RC/ - Ports for the Raisonance compiler. + | | +--STM8/ - Port files for STM8 architecture. + | +--kernel/ - Kernel portable files. + | | +--include/ - Kernel headers. + | | +--src/ - Kernel source. + | | +--templates/ - Kernel port template files. + | +--various/ - Various portable support files. + +--test/ - Kernel test suite source code. + | +--coverage/ - Code coverage project. + +--testhal/ - HAL integration test demos. + | +--LPC11xx/ - LPC11xx HAL demos. + | +--LPC13xx/ - LPC11xx HAL demos. + | +--STM32F1xx/ - STM32F1xx HAL demos. + | +--STM32F4xx/ - STM32F4xx HAL demos (valid for STM32F2xx too). + | +--STM32L1xx/ - STM32L1xx HAL demos. + | +--STM8S/ - STM8S HAL demos. + +--tools - Various tools. + +--eclipse - Eclipse enhancements. + +***************************************************************************** +*** Releases *** +***************************************************************************** + +*** 2.7.0 *** +- FIX: Fixed STM32 Serial (v2) driver invalid CR registers size (bug #416) + (backported to 2.6.0). +- FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0, + 2.4.4, 2.2.10, NilRTOS). +- NEW: SPI driver for SPC560Pxx, SPC563Mxx, SPC564Axx, SPC56ELAxx, SPC560Dxx. +- NEW: Support for SPC560Dxx devices. +- NEW: DMA-MUX support for SPC5xx devices. + +*** 2.5.2 *** +- FIX: Fixed lwipthread.h should explicitly include lwip/opts.h (bug #414). +- FIX: Fixed STM32_PLLI2SCLKOUT miscalculated (bug #413)(backported to 2.4.4). +- FIX: Fixed wrong RTC vector name in STM32F1/F4/L1 EXT drivers (bug #412). +- FIX: Fixed fill character error in chprintf (bug #411). +- FIX: Fixed wrong STM32 USBv1 driver behavior (bug #410). +- FIX: Fixed STM32 wrong peripherals reset procedure (bug #409)(backported + to 2.4.4). +- FIX: Fixed STM32 SPIv2 polled exchange (bug #372). +- FIX: Fixed wrong macro in PWM driver (bug #407)(backported to 2.4.4). +- FIX: Fixed USB driver possible deadlock under certain configurations (bug + #406)(backported to 2.4.4). +- FIX: Fixed USB driver cannot be stopped (bug #405)(backported to 2.4.4). +- FIX: Fixed several spelling errors (bug #404). +- FIX: Fixed serial port in STM32F3 discovery test case (bug #402). +- FIX: Fixed add %i to chprintf (bug #401). +- FIX: Fixed STM32F051 various (bug #400). +- FIX: Fixed STM32F103 HSI configuration (bug #399). +- FIX: Fixed patch to allow simulator to be restarted quicker (bug #398). +- FIX: Fixed blkDisconnect macro typo (bug #397). +- FIX: Fixed STM32 SPI (V2) driver hangs (bug 3608241). +- FIX: Fixed fixed I2C malfunction after fixing bug 3607518 (bug 3607549) + (backported to 2.4.4). +- FIX: Fixed spurious interrupt disabling an STM32 DMA stream (bug 3607518) + (backported to 2.4.4). +- FIX: Fixed start of any ADC disables VREF and VBAT (bug 3607467) + (backported to 2.4.4). +- FIX: Fixed surprising non-CRLF lines in source (bug 3607380). +- FIX: Fixed no entry point defined at link time (bug 3607319). +- FIX: Fixed sdc_lld_collect_errors does not collect errors (bug 3606743). +- FIX: Fixed STM32 CAN broadcast typo (bug 3606675). +- FIX: Fixed STM32 CAN mailbox receive for second fifo (bug 3606673). +- FIX: Fixed CAN_USE_SLEEP_MODE compilation problem (bug 3606616)(backported + to 2.4.4)(backported to 2.2.10). +- FIX: Fixed missing HSE bypass option for STM32F103 (bug 3606274). +- FIX: Fixed misplaced brace in icu_lld.c (bug 3605832)(backported to 2.4.4). +- FIX: Fixed errors in MMC_SPI driver state machine (bug 3605794). +- FIX: Fixed deadlock in Serial_USB driver (bug 3605793). +- FIX: Fixed compile Error OLIMEX_SAM7_EX256/board.c (bug 3605058). +- FIX: Fixed bug prevents calling adcStartConversionI() within ISR (bug + 3605053)(backported to 2.4.4). +- FIX: Fixed typo in platforms/STM32/can_lld.c (bug 3604657)(backported + to 2.4.4). +- FIX: Added board files and demo for "WaveShare Open STM32F4 207I-C / 407I-C". + Added ULPI support to the STM32 USB (OTG-HS) driver. + Contributed by Dave Camarillo (bug 3603362). +- FIX: Fixed adcSTM32EnableTSVREFE must be called AFTER adcStart (bug + 3602950). +- FIX: Fixed duplicated code in hal_lld.h (STM32F4xx) (bug 3602544) + (backported to 2.4.4). +- FIX: Fixed #define typo in usb_lld.h (OTGv1) (bug 3602306). +- FIX: Fixed STM32F0 RCC enable/disable/reset functions for CRC and WWDG + (bug 3602150). +- FIX: Fixed missing parenthesis in use of macro arguments (bug 3601638). +- FIX: Fixed compile errors in Posix-GCC demo (bug 3601621)(backported + to 2.4.4). +- FIX: Fixed state checker error in MSP430 port (bug 3601460)(backported + to 2.4.4). +- FIX: Fixed wrong assertion in UART driver (bug 3600789)(backported + to 2.4.4). +- FIX: Fixed small bug in shell argument parsing code in shell_thread (bug + 3599328)(backported to 2.4.4). +- FIX: Fixed wrong condition in checksum offload of STM32 MAC driver (bug + 3598720)(backported to 2.4.4). +- FIX: Fixed error in STM32 MAC driver degrades performance (bug 3598719) + (backported to 2.4.4). +- FIX: Fixed warning in STM32 ICU driver using IAR compiler (bug 3598177) + (backported to 2.4.3). +- FIX: Fixed wrong SPI path in platform_f105_f107.mk (bug 3598151). +- FIX: Fixed PHY powerdown issues not fixed (bug 3596911). +- NEW: Added new pwmIsChannelEnabledI() API to the PWM driver, implemented + in the STM32 driver. +- NEW: Added support for timers 6, 7, 9, 11, 12, 14 to the STM32 GPT driver. +- NEW: Added support for timer 9 to the STM32 PWM and ICU drivers. +- NEW: Relicensed parts of the distribution tree under the Apache 2.0 + license in order to make specific parts of the code more accessible + to the open source community and adopters. +- NEW: Added ADC(EQADC), HAL, ICU, PAL, PWM, Serial drivers for SPC5xx + platforms, tests to be added on the various sub-families. +- NEW: Added support for SPC56ELxx, SPC560BCxx, SPC560Pxx, SPC560Mxx and + SPC564Axx platforms. +- NEW: Added ADC/SDADC driver for the STM32F37x family. +- NEW: Added support for the STM32F37x family. +- NEW: Now the general documentation includes data extracted from the low + level driver templates. Per-platform/architecture documents are no more + required and will be replaced with technical articles and examples for + each specific driver. +- NEW: Added a build test project for low level device driver templates. +- NEW: Enhanced CAN driver model, support for mailboxes has been added. STM32 + driver implementation upgraded. +- NEW: Added ADC and PWM drivers for the AT91SAM7 platform, both donated + by Andrew Hannam. +- NEW: Added kernel support for the SAM4L, an Atmel Studio 6 demo for the + SAM4L-EK board has been added. +- NEW: Added an abstract file system interface written in C++, no + implementations yet. + TODO: Create a descendant interface for hierarchical file systems. + TODO: Create a FatFS wrapper implementing the interface and using a server + thread for synchronization. + TODO: Create an implementation over a read-only file system in code space. +- NEW: CAN2 support for STM32 added. +- NEW: Updated STM32L1xx header to the latest version. +- NEW: Added an option to lwipthread to change the link status poll interval. +- NEW: Added new C++ demo for the STM32F4-Discovery. +- NEW: Updated C++ wrapper with a much more logical classes structure. + TODO: Opdate older C++ demos. +- NEW: ADC driver implementation for the STM32F3xx, the driver supports also + the dual-ADC mode allowing for a very high combined bandwidth. +- NEW: Added zero-copy capability to the STM32 MAC driver (experimental and + not tested yet). +- NEW: Added an optional zero-copy mode API to the MAC driver model. +- NEW: Added EXT driver to the STM32F3xx platform. +- NEW: Improved the STM32 EXT driver to support more than 32 channels. +- NEW: Added support for Olimex board STM32-LCD. +- CHANGE: Removed dependency between crt0.c (GCC-ARMCMx) and the kernel + header ch.h. + +*** 2.5.1 *** +- FIX: Fixed typo in chOQGetEmptyI() macro (bug 3595910)(backported to 2.2.10 + and 2.4.3). +- FIX: Fixed possible false detect of loaded prescaler in RTCv1 driver (bug + 3595489)(backported to 2.4.3). +- FIX: Fixed unneeded RTC initialization when HAL_USE_RTC disabled + (bug 3594620)(backported to 2.4.3). +- FIX: Fixed compilation issue with HAL_USE_RTC disabled (bug 3594083) + (backported to 2.4.3). +- FIX: Fixed wasting of BKP registers in RTCv1 driver (bug 3594005)(backported + to 2.4.3). +- FIX: Fixed potential problem with RTC_CRL_RSF bit (bug 3593972)(backported + to 2.4.3). +- FIX: Fixed STM32F1x rtc_lld_init not functional (bug 3592817)(backported + to 2.4.3). +- FIX: Fixed DMA reconfiguration problem in STM32 SPI driver (bug 3592809) + (backported to 2.4.3). +- FIX: Fixed STM32 UART driver redundant initialization (bug 3592764) + (backported to 2.4.3). +- FIX: Fixed wrong stack initializations in GCC STM32L1xx port files (bug + 3591321)(backported to 2.4.3). +- FIX: Fixed different redefinition for __main_stack_end__ symbol (bug + 3591317)(backported to 2.4.3). +- FIX: Fixed errors in STM32F0xx UART driver (bug 3589412)(backported + to 2.4.3). +- FIX: Fixed MSP430 port_switch code for MSPGCC issue (bug 3587633)(backported + to 2.4.3). +- FIX: Fixed workaround for errata in STM32F4-A devices (bug 3586425) + (backported to 2.4.3). +- FIX: Fixed error in palWritePad() macro (bug 3586230)(backported to 2.2.10 + and 2.4.3). +- FIX: Fixed missing ; in testmbox.c (bug 3585979)(backported to 2.4.3). +- FIX: Fixed STM32F4xx: Wrong CAN1 SCE interrupt number definition (bug + 3581571). +- FIX: Fixed STM32_P407: implement mmc_lld_is_card_inserted (bug 3581929) + (backported to 2.4.3). +- FIX: Fixed double chSysInit() call in MSP430F1611 demo (bug 3581304) + (backported to 2.2.10 and 2.4.3). +- FIX: Fixed patch for various demos (bug 3579734). +- FIX: Fixed bug in abstract file interface (bug 3579660)(backported to + 2.2.10 and 2.4.3). +- FIX: Fixed wrong type for UART config registers (bug 3579434). +- FIX: Fixed various typos and wrong limits in the STM32F4/F2 HAL driver + (bug 3578944)(backported to 2.4.3). +- FIX: Fixed ARM CMx crt0.c fails at low optimization levels (bug 3578927) + (backported to 2.4.3). +- FIX: Fixed compilation issue in chregistry.c (bug 3576776). +- FIX: Fixed compilation issue in syscalls.c (bug 3576771)(backported + to 2.4.3). +- FIX: Fixed Typos in STM32F0xx EXT driver (bug 3576193). +- FIX: Fixed STM32F10X_CL: Wrong CAN1 interrupt number definitions (bug + 3575766). +- FIX: Fixed superfluous pack #defines cause nasty warning (bug 3575662) + (backported to 2.4.3). +- FIX: Fixed mac.c won't compile due to misplaced declarations (bug 3575657) + (backported to 2.4.3). +- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297) + (backported to 2.4.3). +- FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug + 3575098)(backported to 2.4.3). +- FIX: Fixed misplaced declarations in lwip_bindings sys_arch.c (bug 3571053) + (backported to 2.4.3). +- FIX: Fixed double definition of sd1fel and sd2fel breaks Posix simulator + (bug 3570532). +- FIX: Fixed Ethernet PHY power down scheme prevents using LAN8720A (bug + 3570335). +- FIX: Fixed FatFS won't compile with _FS_REENTRANT enabled (bug 3570135) + (backported to 2.4.3). +- FIX: Fixed mmc_spi.c won't compile due to misplaced declaration (bug + 3570035)(backported to 2.4.3). +- FIX: Fixed problem in STM32F1xx USB driver after revision 4598 (bug 3569374). +- FIX: Fixed GPIO glitch during PAL initialization (bug 3569347)(backported + to 2.4.3). +- FIX: Fixed FatFS timestamp incorrect (bug 3568626). +- FIX: Fixed Data available event not generated in serial_usb driver (bug + 3567992). +- FIX: Fixed STM32F1x rtc_lld_init glitches rtc on hard reset (bug 3567597) + (backported to 2.4.3). +- FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342)(backported + to 2.2.10 and 2.4.3). +- NEW: Initial support for STM32F30x (HAL, PAL, CAN, GPT, ICU, PWM, Serial, + SPI, UART, USB). +- NEW: AT91SAM7A3 I2C support. +- NEW: AT91SAM7A3 basic support. +- NEW: Unified the STM32F4xx and STM32F2xx platform code. The STM32F2xx now is + only supported as an STM32F4xx variant and not tested separately. +- NEW: Updated STM32F1, F2, F4, L1 ADC drivers to allow HW triggering. +- NEW: Added a new option STM32_ETH1_CHANGE_PHY_STATE to the STM32 MAC driver, + this change is connected to bug 3570335. +- NEW: Modified the CAN drivers to use the new event flags mechanism, the + previous flags handling has been removed. +- NEW: Modified serial and serial_usb drivers to use the new event flags + mechanism, the previous flags handling in BaseAsynchronousChannel has + been removed. +- NEW: Improved the kernel events subsystem, now event sources can associate + source-specific flags to the listener, the flags can then be retrieved + using the new APIs chEvtGetAndClearFlags() and chEvtGetAndClearFlagsI(). + Some old APIs have been renamed to increase consistency of the module. +- NEW: Added VLE support to the Power Architecture GCC port. +- NEW: Reorganized the Power Architecture GCC port along the lines of the + ARMCMx port, now it can support multiple core types. +- NEW: Updated the Power Architecture rules.mk file to put object and listing + files into a ./build directory like ARM ports already do. +- CHANGE: The STM32 Serial driver has been split in two distinct versions, + one for older devices up the STM32F4xx, the other for new devices starting + from the STM32F0xx. + (TODO: Update IAR and Keil projects because different paths, update + documentation projects). + +*** 2.5.0 *** +- FIX: Fixed anomaly in USB enumeration (bug 3565325)(backported to 2.4.3). +- FIX: Fixed problem with lwIP statistics (bug 3564134)(backported to 2.4.3). +- FIX: Fixed packed structures macros not functional in IAR and RVCT port + (bug 3561279)(backported to 2.4.3 and 2.2.10). +- FIX: Fixed Problem in FatFs demos related to LFN (bug 3560980)(backported + to 2.4.3 and 2.2.10). +- FIX: Fixed problem in STM32 DMA1 stream1 IRQ handler (bug 3538468) + (backported to 2.4.2). +- FIX: Fixed TIM8 not working in STM32 GPT driver (bug 3536523)( +- FIX: Fixed wrong priority assigned to TIM8 in STM32 ICU driver (bug 3536950) + (backported to 2.4.2). +- FIX: Fixed TIM8 not working in STM32 GPT driver (bug 3536523)(backported + to 2.4.2). +- FIX: Fixed timer overflow not working in STM32 ICU driver for TIM1/TIM8 (bug + 3536522)(backported to 2.4.2). +- FIX: Fixed wrong DMA channels on USART2 in STM32F10X_MD_VL devices (bug + 3536070)(backported to 2.4.2). +- FIX: Fixed issue with DMA channel init in STM32 ADC and SPI drivers (bug + 3535938)(backported to 2.2.10 and 2.4.2). +- FIX: Fixed issue debugging mmc_spi (bug 3535887)(trunk only). +- FIX: Fixed unreliable PHY initialization (bug 3534819)(backported to 2.4.2). +- FIX: Fixed wrong ADC callback buffer pointer in ADC driver (bug 3534767) + (backported to 2.2.10 and 2.4.2). +- FIX: Fixed STM32F2 RTC subseconds (bug 3533414)(trunk only). +- FIX: Fixed problem with arm-v6m and state checker (bug 3532591)(backported + to 2.4.2). +- FIX: Fixed wrong MAC divider setting in STM32 MAC driver (bug 3531290) + (backported to 2.4.2). +- FIX: Fixed wrong MCO1 divider in STM32F2/F4 HAL (bug 3531289)(backported + to 2.4.2). +- FIX: Fixed missing "break" in AVR PAL driver (bug 3530924)(backported + to 2.4.2). +- FIX: Fixed timeout related race condition in STM32 I2C driver (bug 3530043) + (backported to 2.4.2). +- FIX: Fixed wrong macro check in STM32 MAC driver (bug 3527179)(backported + to 2.4.2). +- FIX: Fixed error in STM32L-Discovery board.h file (bug 3526918)(backported + to 2.4.2). +- FIX: Fixed inconsistent LPCxxx Internal RC oscillator names (bug 3524138) + (backported to 2.2.10 and 2.4.1). +- FIX: Fixed wrong frequency limit checks vs VDD in STM32F2xx HAL (bug 3524094) + (backported to 2.4.1). +- FIX: Fixed STM32 I2C1 wrong alternate TX DMA setting (bug 3524088) + (backported to 2.4.1). +- FIX: Fixed system state check problem related to FatFS (bug 3523769). +- FIX: Fixed three testhal builds fail (bug 3523322)(backported to 2.4.1). +- FIX: Fixed MAC driver functions with invalid name (bug 3522808)(backported + to 2.2.10 and 2.4.1). +- FIX: Fixed code coverage crashes with Linux/gcc-4.4.5 (bug 3522301) + (backported to 2.4.1). +- FIX: Fixed macro dmaWaitCompletion() fails to compile in STM32 HAL (bug + 3519202)(backported to 2.4.1). +- FIX: Fixed ARM addresses generated in vectors table (bug 3519037)(backported + to 2.2.10 and 2.4.1). +- FIX: Fixed missing serial driver functionality for SAM7S64, SAM7S128 and + SAM7S512 (bug 3517648)(backported to 2.2.10 and 2.4.1). +- FIX: Fixed a few more spelling fixes (bug 3515531)(backported to 2.4.1). +- FIX: Fixed spurious ) char in STM32 serial_lld.h (bug 3514138)(backported + to 2.2.10 and 2.4.1). +- FIX: Fixed problem with FPU initialization in GCC Cortex-M4 port (bug + 3513897)(backported to 2.4.1). +- FIX: Spelling fixes (bug 3510812)(backported to 2.4.1). +- FIX: Fixed STM32 ICUD8 not functional because wrong initialization (bug + 3508758)(backported to 2.4.1). +- FIX: Fixed chMBFetchI does not decrement mb_fullsem (bug 3504450)(backported + to 2.2.9 and 2.4.1). +- FIX: Fixed STM32 PLLI2S initialization error (bug 3503490)(backported + to 2.4.1). +- FIX: Fixed USART3 not working on STM32F2/F4 UART driver (bug 3496981) + (backported to 2.4.1). +- FIX: Fixed stack misalignment on Posix-MacOSX (bug 3495487)(backported + to 2.4.1). +- FIX: Fixed STM8S HSI clock initialization error (bug 3489727)(backported to + 2.2.9 and 2.4.1). +- FIX: Fixed MMC over SPI driver performs an unnecessary SPI read (bug + 3486930)(backported to 2.2.9 and 2.4.1). +- FIX: Fixed Realtime counter initialization in STM32 HALs (bug 3485500) + (backported to 2.4.1). +- FIX: Fixed PPC port broken when CH_DBG_SYSTEM_STATE_CHECK is activated + (bug 3485667)(backported to 2.4.1). +- FIX: Fixed missing PLL3 check in STM32F107 HAL (bug 3485278)(backported + to 2.4.1). +- FIX: Fixed ADC maximum frequency limit in STM32F2/F4 ADC drivers (bug + 3484947)(backported to 2.4.1). +- FIX: Fixed various minor documentation errors (bug 3484942)(backported + to 2.4.1). +- NEW: Added Eclipse project files to most demos. The project are setup to + have paths relative to a variable named CHIBIOS that must point to the + ChibiOS/RT installation path. The variable must be defined under + Window->Preferences->General->Workspace->Linked_Resources and must contain + a path without the trailing slash character. +- NEW: Added memory signature record to the registry in order to simplify + the implementation of ad-hoc debuggers. +- NEW: Small andjustment in chcore.h files under ./os/ports/GCC required by a + difference in GCC 4.7.x. +- NEW: Added another STM32F4-Discovery demo using the on-board MEMS, SPI + and PWM. Removed MEMS handling from the old demo because code size limits + on non-free compilers. +- NEW: Added configuration wizard plugin under ./tools/eclipse/plugins. This + first version is able to configure the board files for STM32F0xx, STM32F4xx + and STM32L1xx. +- NEW: Added USART6 support to the STM32 UARTv1 driver, contributed by Erik + van der Zalm. +- NEW: Added demo for Arduino Mega, contributed by Fabio Utzig. +- NEW: Added support for ATmega1280, contributed by Fabio Utzig. +- NEW: Added I2C driver for AVR, contributed by Fabio Utzig. +- NEW: Added FatFs demo for the Olimex STM32-P107 board. +- NEW: Added support for the Olimex STM32-E407 board. Added an integrated + demo including USB-CDC, lwIP with web server, FatFs and shell, all running + together. +- NEW: Added an experimental and unsupported STM8 port for the IAR compiler, + contributed by "king2". +- NEW: Updated STM8 header files to latest versions from ST. +- NEW: Reorganized the STM32 EXT driver to have a sub-platform specific + part containing all the ISR related code, this has been necessary because + the significant differences among the various sub-families. +- NEW: Validated CAN driver on STM32F2/F4 (backported to 2.4.2). +- NEW: USB implementation for STM32F105/F107/2xx/F4xx devices. +- NEW: Improved SerialUSB driver using the new queued mode, much smaller + than the previous driver. +- NEW: Improved USB driver model supporting also queues for endpoint I/O, + packet mode removed. +- NEW: Added an application-defined field to I/O queues (a void pointer). +- NEW: Added board files for Maple Mini STM32F103, contributed by Wagner + Sartori Junior. +- NEW: Added SSP1 capability to the LPC13xx SPI driver. +- NEW: Updated vendor headers for LPC11xx and LPC13xx, the new headers + support several new devices. +- NEW: Demo for STM32F0-Discovery board. +- NEW: Initial support for STM32F0xx devices, added a specific ADC driver. + Validated EXT, GPT, ICU, PAL, PWM, Serial, SPI, UART drivers. +- NEW: Added a common ancestor class to the SDC and MMC_SPI drivers. This + allows to share code and definitions. +- NEW: Modified the SDC driver to implement the new block devices abstract + interface. +- NEW: Added two new functions to the MMC_SPI driver: mmcSync() and + mmcGetInfo(). Also implemented the new block devices abstract + interface. Moved the configuration parameters from mmcObjectInit() to + the configuration structure saving some RAM space. Updated demos. +- NEW: Added an abstract interface for block devices in the HAL. This + abstraction layer is meant to unify the access protocol to the SDC and + MMC_SPI (and potentially others) device drivers. +- NEW: Added an abstract interface for serial devices in the HAL. This + interface is meant to replace the equivalent class already present in the + kernel. access macros are similar except for the prefix, "chn" instead + of "chIO". +- NEW: Updated the MSP port to work with the latest MSPGCC compiler (4.6.3 + LTS 20120406 unpatched), now the old MSPGCC 3.2.3 is no more supported + (backported to 2.4.1). +- NEW: EXT driver improved, now it is possible to reprogram channels at + runtime without necessarily specifying a new configuration. + TODO: Update AT91SAM7 EXT driver. +- NEW: Integrated FatFS 0.9, now the FatFS integration files are centralized + under ./os/various/fatfs_bindings and shared among all demos. The FatFS + file ffconf.h is now application-specific like all the other configuration + files. +- NEW: Added an new option CORTEX_PRIGROUP_INIT to the Cortex-Mx ports in + order to make priority organization configurable, the default is to + assign all the available priority bits to preemption priority with no + sub-priorities. +- NEW: Added a new function chPoolLoadArray() to the Memory Pools subsystem, + it allows to load an entire array element's into a pool with a single + operation. +- NEW: Addes support for .S patch in the GCC ARM ports, by Ayman El-Khashab. +- NEW: Added a switch to the STM32F4 Makefile files in order to enable or + disable the FPU support in a single place. +- NEW: Added float support (optional) to chprintf(), by Fabio Utzig. +- NEW: Added overflow handling in the ICU driver (contributed by Xo). +- NEW: Updated debug plugin 1.0.8 (backported to 2.4.0). +- NEW: Added more accurate UBRR calculation in AVR serial driver (backported + to 2.4.0). +- NEW: Revision of the round-robin scheduling, now threads do not lose their + time slice when preempted. Each thread has its own time slices counter. + TODO: Seek optimizations. +- NEW: Modified the Virtual Timers management, now the callback is invoked + not in lock mode. This change reduces the interrupt jitter caused by + multiple timers used at same time. +- NEW: Added board files and demo for Olimex LPC-P1343 (contributed by + Johnny Halfmoon). +- NEW: Added handling of input 2 to the STM32 ICU driver (contributed by + Fabio). +- NEW: STM32 Ethernet driver completed. Added STM32F107 and STM32F407 + lwIP demos (backported to 2.4.1). +- NEW: lwIP related code is not centralized into a single place, no need to + duplicate the code in each application or demo (backported to 2.4.1). +- CHANGE: Added two new methods to the BaseSequentialStream interface: + chSequentialStreamPut() and chSequentialStreamGet(). +- CHANGE: Removed the chioch.h header from the kernel, now channels interface + is exported by the HAL. Removed functions chPutWouldBlock() and + chGetWouldBlock(). +- CHANGE: Removed macro chMsgGetS(), chMsgGet() is still available. +- CHANGE: chprintf() now takes a BaseSequentialStream as parameter instead + of a BaseChannel making it more generic. +- CHANGE: Now the shell requires a BaseSequentialStream instead of a + BaseChannel for communications making it more generic. +- CHANGE: Kernel memory pools now do not check the alignment of the inserted + objects, it is responsibility of the application to insert properly + aligned objects. +- CHANGE: The PORT_INT_REQUIRED_STACK parameter for the Cortex-Mx ports has + been increased to 32 from 16 because the stack frame sizes are increased + when compiling with optimizations disabled, which is common during + debugging. In order to save RAM trim back this value when compiling with + optimizations enabled (backported to 2.4.1). +- CHANGE: Renamed Ethernet driver in AT91 HAL ETHD1 (backported to 2.4.1). +- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renamed to icuGetWidth() + and icuGetPeriod(). +- Various documentation fixes and improvements. + +*** 2.3.5 *** +- FIX: Fixed RTC compile problem on STM32F103 (bug 3468445). +- FIX: Fixed PWM with TIM1 and TIM8 broken in STM32 HAL (bug 3458947). +- FIX: Fixed SYSCFG clock not started in STM32L1/F4 HALs (bug 3449139). +- FIX: Fixed wrong definitions in STM32L-Discovery board file (bug 3449076). +- OPT: Improved the exception exit code in the GCC Cortex-Mx ports. +- NEW: Added a DMA stress test application for the STM32F4 in order to assess + robustness of the whole HAL. +- NEW: Added a Time Measurement driver to the HAL, this generic driver uses + the realtime counters abstracted in the HAL driver. +- NEW: Improved the STM32F1xx HAL driver, it now has the same features and + configuration options of the newer STM32s. +- NEW: MMC over SPI driver improved to handle high capacity cards, by + Matthias Blaicher. +- NEW: Added PVD support to the HAL of all STM32s, by Barthess. +- NEW: Added to the HAL driver the handling of an abstract realtime free + running counter, added the capability to all the STM32 HALs. +- NEW: Modified ARM and ARMCMx build rules to allow parallel build. Now the + log outputs one dummy compilation command in order to allow paths discovery + by Eclipse. +- NEW: Added an utility module to access LIS302DL MEMS using a SPI. +- NEW: Updated STM32F2xx support by inheriting the work done on the STM32F4xx, + the whole thing is untested because lack of hardware. +- NEW: Files nvic.c and nvic.h moved under ./os/ports/common/ARMCMx, removed + the duplicated instances under the GCC, IAR and Keil ports. Function names + prefixes changed from "NVIC" to "nvic" because style conventions. +- NEW: Added voltage regulator initialization to the STM32F4xx HAL. +- NEW: Added a linker script that demonstrates how to put stacks and other + critical structures in the CCM RAM instead normal RAM. +- NEW: Added experimental support for the Cortex-M4 FPU (default when the + FPU is present but can be disabled). +- NEW: Improved I2C driver model and STM32 implementation by Barthess. +- CHANGE: Removed the option to change the stack alignment in the GCC + Cortex-Mx ports, now alignment is always 64 bits. +- CHANGE: Modified the function palSetGroupMode() to have an offset parameter + in order to make it similar to other functions operating on groups. +- CHANGE: Increased main and process default stack sizes from 0x100 to 0x200 + in LPC1114 and LPC1343 linker scripts. + +*** 2.3.4 *** +- FIX: Fixed Extra initialization in STM32 SPI driver (bug 3436127) + (backported to 2.2.8). +- FIX: Fixed DMA priority setting error in STM32 UART driver (bug 3436125) + (backported to 2.2.8). +- FIX: Fixed DMA priority setting error in STM32 SPI driver (bug 3436124) + (backported to 2.2.8). +- FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094) + (backported to 2.2.8). +- FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). +- FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added an unified registers file for STM32: stm32.h. This file includes + the appropriate vendor file then adds its own additional definitions. +- NEW: Added demo for the ST STM32F4-Discovery kit. +- NEW: STM32F4xx ADC driver implementation. +- NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) + ports. Also added a port option CORTEX_VTOR_INIT to enforce a different + default value into the register. +- NEW: Removed the warning about the "untested M4 platform", now it is + tested and officially supported. +- NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute + the capability macros into the appropriate file (previously those were all + in the common hal_lld.h). +- NEW: Added HAL, Serial, ADC, EXT, GPT, ICU, PWM, SPI and UART support for + the STM32F4xx sub-family. + TODO: Add CAN and SDC, the drivers need to be ported and tested. +- NEW: Added handling of USART6 to the STM32 serial driver. +- NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. +- NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. + TODO: Test application missing. +- NEW: Updated USB driver model and STM32 implementation and fixed several + problems. + - Changed the API to move buffer copy operations out of critical zones. + - Added usbConnectBus() and usbDisconnectBus() functions. + - Fixed problems with incorrect assertions. +- NEW Updated the SERIAL_USB driver to match the new USB API, also fixed + some problems. + - Fixed incorrect use of input queues, the change required a change in + input queues too. +- NEW: Added a macro THD_STATE_NAMES to chthreads.h. This macro is an + initializer for string arrays containing thread state names. +- NEW: Added memory copy functionality to the STM32 DMA driver. +- NEW: Implemented new makefile system for ARM GCC ports, now objects, + listings and output files are generated into a "build" directory and not + together with sources, also implemented a simplified output log mode. + Now makefiles and load script files are requirements and trigger a + rebuild if touched. +- NEW: Updated AVR demos to use the new PAL driver. +- NEW: Added Keil build files to the STM32L-Discovery demo. +- CHANGE: Now the callback associated to input queues is invoked before + reading each character. Previously it was invoked only before going + to sleep into the THD_STATE_WTQUEUE state. +- CHANGE: Moved the STM32 DMA helper drivers files under the sub-family + specific directories because documentation issues. + +*** 2.3.3 *** +- FIX: Fixed missing UART5 definition in STM32 HAL (bug 3411774)(backported + to 2.2.8). +- FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). +- FIX: Fixed wrong parameter passed to the DMA error hook in STM32 ADC driver, + the DMA error hook has been removed entirely in the new ADC driver model + (bug 3413214). +- FIX: The function chThdExit() triggers an error on shell return when the + system state checker is enabled (bug 3411207)(backported to 2.2.8). +- FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug + 3411180)(backported to 2.2.8). +- FIX: Fixed wrong check on CH_DBG_ENABLE_STACK_CHECK setting (bug 3387671) + (backported to 2.2.7). +- FIX: Fixed wrong APB1 frequency check (bug 3361039)(backported to 2.2.7). +- FIX: Fixed missing state in shell demos (bug 3351556)(backported to 2.2.7). +- FIX: Fixed race condition in Cortex-Mx ports (bug 3317500)(backported + to 2.2.6). +- FIX: Fixed wrong macro check in STM32 UART driver (bug 3311999)(backported + to 2.2.6). +- FIX: Fixed wrong macro definition in ARMv6-M architecture files (bug + 3310084). +- FIX: Fixed race condition in output queues (bug 3303908)(backported + to 2.2.4). +- FIX: Fixed CH_USE_HEAP and CH_USE_MALLOC_HEAP conflict (bug 3303841) + (backported to 2.2.4). +- FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) + (backported to 2.2.4). +- NEW: Added AVR implementation of the PAL driver contributed by Leszek. +- NEW: STM32L ADC driver implementation. +- NEW: Improved ADC driver model, now it is possible to handle error + conditions during the conversion process. +- NEW: STM32L1xx sub-family support, all STM32 drivers adapted and re-tested + on the new platform except ADC that will need a specific implementation. +- NEW: Added new API chThdExitS() in order to allow atomic operations on + thread exit (backported to 2.2.8). +- NEW: New EXT driver model and STM32 implementation. +- NEW: New I2C driver model and STM32 implementation. + (evaluate the option to change the API to a synchronous model) +- NEW: New RTC driver model and STM32 implementation. + (API and functionality review) +- NEW: Improved MAC driver model, it now follows the same template of other + drivers. + TODO: implement macStop() in AT91SAM7X implementation. +- NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies + the use of the RCC resources and hides most differences found among the + various STM32 sub-families. +- NEW: New DMA helper driver for STM32, it simplifies the use of the DMA + resources and hides most differences with the new enhanced DMA units + found in the STM32F2xx sub-family. +- NEW: Now an error is generated at compile time when trying to enable the + options CH_DBG_ENABLE_STACK_CHECK on ports that do not support it. +- NEW: Added a kernel-only Cortex-Mx demo as reference project for users not + interested in the HAL but just want to use the ChibiOS/RT kernel. + The demo is named ARMCM3-GENERIC-KERNEL and is defaulted to the STM32, in + order to use it on other families or on the ARM Cortex-M0 just change the + inclusion paths in the makefile. +- NEW: Integrated new FatFs version 0.8b. +- NEW: Added a new hook THREAD_CONTEXT_SWITCH_HOOK() that allows to insert + code just before a context switch. For example this hook could be used + in oder to implement advanced power management schemes. +- NEW: Added a new debug option CH_DBG_SYSTEM_STATE_CHECK that ensures the + correct API call protocol. If an API is invoked out of the correct context + then the kernel panics with a debug message. +- NEW: The ARMCMx startup file (crt0.c) now is able to fill the stack areas + with a filler (default behavior). This is required in order to easily assess + the stack usage at runtime. +- NEW: Added the new CMSIS 2.1 headers, now CMSIS resides into a shared + location: ./os/ports/common/ARMCMx/CMSIS. Old CMSIS files have been + removed from the various platforms. +- NEW: Removed all the ch.ld files from the ARMCMx demos, now the makefiles + point to common ld files under the various ports. Less duplication and + easier maintenance. +- NEW: Improved stack checking and reorganized memory map for the Cortex-Mx + demos. Now stacks are allocated at the start of the RAM, an overflow of the + exception stack now triggers an exception (it could go unnoticed before). + The process stack is organized to be checked on context switch like other + threads. Now all threads have an explicit stack boundary pointer. +- NEW: Added debug plugin for Eclipse under ./tools/eclipse (backported to + 2.2.7). +- NEW: The debug macros chDbgCheck() and chDbgAssert() now can be externally + redefined. The macro chDbgCheck() no more includes the line number in the + description because incompatibility with the Cosmic compiler (backported to + 2.2.7). +- NEW: Added provisional support for STM32F2xx. Because of this some + directories related to the STM32 have been renamed, your makefiles may + require adjustments. +- NEW: Added a custom rule to the various rules.mk files, now it is possible + to add an user rule into the Makefiles. +- NEW: Improvements to the trace buffer, now it stores a full thread pointer + and event time, changed names to debug variables by adding the "dbg_" + prefix (backported to 2.2.7). +- NEW: Added a new functionality to the registry subsystem, now it is possible + to associate a name to the threads using chRegSetThreadName. The main and + idle threads have their name assigned by default (backported to 2.2.7). +- NEW: Added TIM8 support to the STM32 GPT, ICU and PWM drivers. +- NEW: Updated the STM32 header file to the latest version 3.5.0 and fixed + it in order to correct several bugs related to the XL family. +- NEW: Added a chprintf() function to ./os/various, it can print on any + BaseChannel. +- NEW: Improved the mini shell, enhanced info command, optimizations and + removed the shellPrint() and shellPrintLine() functions, now it uses + chprintf() for output. +- NEW: lwIP 1.4.0 has been integrated, this new version does not require + custom hooks into the Thread structure and is thus much lighter. +- NEW: FatFs demo for the STM32F103ZG using the SDC driver. +- NEW: Now the STM32 SDC driver supports unaligned buffers transparently. + Optimized the driver for single block read and write operations. Optimized + the driver state machine. +- NEW: Finished the reorganization of the Cortex-Mx ports, now also the + IAR and RVCT ports support the new Compact mode. +- NEW: Added to the ARMv6-M sub-port an option to use the PendSV exception + instead of NMI for preemption (backported to 2.2.5). +- NEW: Reorganization of the Cortex-Mx ports in order to reduced code and + comments duplication in the various headers (backported to 2.2.5). +- NEW: Improved the ARMv7-M sub-port now there are two modes: Compact and + Advanced. + The advanced mode is equivalent to the previous versions, the compact mode + is new and makes the kernel *much* smaller and generally faster but does + not support fast interrupts (backported to 2.2.5). +- NEW: Now the port layer exports info regarding the compiler and the port + options. The info are printed into the test reports. Date and time also + added. +- CHANGE: Removed the option CH_USE_NESTED_LOCK, lwIP no more requires it and + it would have conflicted with CH_DBG_SYSTEM_STATE_CHECK which is far more + useful. +- CHANGE: Renamed the scheduler functions chSchIsRescRequiredExI() to + chSchIsPreemptionRequired(), chSchDoRescheduleI() to chSchDoReschedule(), + chSysSwitchI() to chSysSwitch(). All those functions were special cases + and not regular I-class APIs. +- CHANGE: Renamed the macros IDLE_THREAD_STACK_SIZE and INT_REQUIRED_STACK + to PORT_IDLE_THREAD_STACK_SIZE and PORT_INT_REQUIRED_STACK for consistency. +- CHANGE: Removed the "old" Cortex-M3 port from the code, the current port + has no drawbacks and the old port is now just a maintenance cost. +- CHANGE: Removed the CH_CURRP_REGISTER_CACHE option, it is GCC-specific so + it does not belong to the kernel options. The feature will be eventually + reimplemented as a port-specific option. +- CHANGE: chiQGetFullI() and chOQGetFullI() become macros. The queues + subsystem has been optimized and is no more dependent on semaphores. + Note that the queues callbacks invocation policy has been slightly + changed, see the documentation (backported to 2.2.4). + +*** 2.3.2 *** +- FIX: Fixed invalid BRR() macro in AVR serial driver (bug 3299306)(backported + to 2.2.4). +- FIX: Fixed missing IRQ vectors amicable names for STM32 XL devices (bug + 3298889)(backported to 2.2.4). +- FIX: Fixed wrong identifier in AVR serial driver (bug 3292084)(backported + to 2.2.4). +- FIX: Fixed wrong macro check for STM32 XL devices (bug 3291898)(backported + to 2.2.4). +- FIX: Fixed SPI driver restart in STM32 SPI driver implementation, also + applied the same fix to the STM8S SPI driver (bug 3288758)(backported to + 2.2.4). +- FIX: Fixed missing state transition in ADC driver (bug 3288149)(backported + to 2.2.4). +- FIX: Fixed missing state transition in SPI driver (bug 3288112)(backported + to 2.2.4). +- FIX: Fixed spurious characters generated by Serial over USB driver (bug + 3276379). +- NEW: Added an option to the kernel to not spawn the Idle Thread from within + chSysInit(), this way the application can spawn a custom idle thread or + even use the main() thread as idle thread (backported to 2.2.4). +- NEW: Added new SDC driver model, Secure Digital Card. +- NEW: SDC driver implementation for STM32. +- NEW: Updated the STM32 header file to the latest version 3.4.0, had to + fix a bug regarding the STM32 XL sub-family. +- NEW: New unified GCC startup file for Cortex-Mx processors, it is written + in C instead of asm and supports constructors/destructors. Improved the + Cortex-Mx linker scripts in all the GCC demos. +- NEW: Now it is possible to share DMA channels in the STM32 HAL thanks + to a centralized manager. Channels are allocated when the driver is + started and released when it is stopped. +- NEW: Added an STM32 C++ demo for the GNU compiler. +- NEW: Added an STM32F103ZG demo for the STM3210E-EVAL evaluation board. +- OPT: STM32 PWM driver implementation simplified. +- CHANGE: Now pwmChangePeriod() does not implicitly disable the active + PWM channels. +- CHANGE: Renamed the chSemSetCounterI() function to chSemAddCounterI() and + changed its behavior. +- CHANGE: Modified the STM32 USB-CDC test demo to spawn a shell over the USB + serial connection. + +*** 2.3.1 *** +- FIX: Fixed insufficient idle thread stack in Cortex-M0-GCC port (bug 3226671) + (backported to 2.2.3). +- FIX: Fixed stack checking in Cortex-M0-GCC port (bug 3226657)(backported + to 2.2.3). +- FIX: Fixed wrong checks in PAL driver (bug 3224681)(backported to 2.2.3). +- FIX: Fixed wrong checks in I/O Queues (bug 3219197)(backported to 2.2.3). +- FIX: Fixed invalid assertion in adcConvert() (bug 3205410)(backported + to 2.2.3). +- NEW: Improvements to the PWM driver model: + - Easier configuration similar to the GPT driver initializations, macros + are no more required. + - Added a new function that allows to change the PWM period on the fly, + even from within callbacks. Formerly it was required to stop and restart + the driver. + - Improved driver documentation. +- NEW: Added advanced mode to the STM32 PWM driver (TIM1 only). +- NEW: Added new ICU driver model, Input Capture Unit. +- NEW: ICU driver implementation for STM32. +- NEW: Implemented stack checking in the Cortex-Mx RVCT port (backported + to 2.2.3). +- NEW: Added support for PLL3 in STM32 HAL driver. Note, the format of the + mcuconf.h file is changed for STM32F105/STM32F107 devices. +- NEW: Added board files for the Olimex STM32-P107. +- NEW: Improved setup packets handling in the USB driver through a specific + callback. +- NEW: Improvements to the PAL driver and various implementation in order + to make them more parenthesis friendly. +- OPT: Simplified Serial over USB driver configuration. +- CHANGE: Renamed the demo ARMCM3-STM32F107-GCC in ARMCM3-STM32F107 and added + IAR and Keil projects. +- CHANGE: Now the ARMCM3-STM32F107 demo targets the board Olimex STM32-P107 + as default. +- CHANGE: Removed all the prefixes from the structure/union field names + in the HAL subsystem. +- CHANGE: Updated the documentation to use Doxygen 1.7.4 which produces a much + more readable output. Also modified the documentation layout to put functions + and variables ahead of everything else in the group pages. + Doxygen version below 1.7.4 cannot be used anymore because differences in + templates. Note that now there are two Doxygen projects, one for generating + the CHM file the other for plain HTML. + +*** 2.3.0 *** +- FIX: Fixed race condition in CM0 ports, the fix also improves the + ISR latency (bug 3193062)(backported to 2.2.2). +- FIX: Fixed Cortex-Mx linker scripts alignment of __heap_base__, the + correct alignment is now enforced at runtime into core_init() in order + to make the OS integration easier (bug 3191112)(backported to 2.2.2). +- FIX: Fixed error in function chCoreAllocI() function documentation (bug + 3191107)(backported to 2.2.2). +- FIX: Fixed minor problem with memory pools (bug 3190512)(backported to + 2.2.2). +- FIX: Stack overflow in CM0 ports when nearing interrupts saturation (bug + 3187105)(backported to 2.2.1). +- FIX: Fixed error in _BSEMAPHORE_DATA macro (bug 3184139)(backported to + 2.2.1). +- FIX: Error in MAC driver (bug 3179783)(backported to 2.2.1). +- FIX: Fixed wrong serial driver macros (bug 3173336)(backported to 2.2.1). +- NEW: Improved preemption implementation for the Cortex-M0, now it uses + the NMI vector in order to restore the original context. The change makes + IRQ handling faster and also saves some RAM/ROM space. The GCC port code + now does not inline the epilogue code in each ISR saving significant ROM + space for each interrupt handler in the system (backported to 2.2.3). +- NEW: Added "IRQ STORM" long duration tests for the STM32, LPC11xx and + LPC11xx. The test demonstrates the system stability in a thread-intensive, + progressively CPU-saturating, IRQ-intensive long duration test. +- NEW: Added two new functions to the events subsystem: chEvtBroadcastFlags() + and chEvtBroadcastFlagsI(). The old chEvtBroadcast() and chEvtBroadcastI() + become macros. The new functions allow to add the same flags to all the + registered listener threads. +- NEW: Added I-Class functions to the MailBoxes subsystem, now it is + possible to use them as a transport layer between ISRs and Threads + (backported to 2.2.2). +- NEW: Added new USB driver model, probably it will evolve in next + releases. +- NEW: USB driver implementation for STM32. +- NEW: Added "serial over USB" driver, it implements a Communication + Device Class exposing it as a normal serial driver to applications, + probably it will evolve in next releases. +- NEW: Added STM32 USB CDC loopback test application. +- NEW: Added new GPT driver model, General Purpose Timer. The driver + allows to access the available timers in an abstract way. +- NEW: GTP driver implementation for STM32, LPC13xx and LPC11xx. +- NEW: Added STM32 GPT test application. +- NEW: Implemented new event IO_TRANSMISSION_END in the generic serial + driver. This event marks the physical transmission end of a data stream. +- NEW: Implemented the new IO_TRANSMISSION_END event in the STM32 serial + driver. +- NEW: Added explicit reset of all peripherals inside the STM32 HAL driver. + Removed the separate resets on initialization from the various other + drivers saving significant space. +- OPT: Removed TIMx reset on system startup in the STM32 PWM driver, the + timers are already reset on driver startup. +- CHANGE: The functions chEvtSignal() and chEvtSignalI() have been renamed + to chEvtSignalFlags() and chEvtSignalFlagsI() for consistency. +- CHANGE: Swapped the numeric values of the TIME_IMMEDIATE and TIME_INFINITE + constants. Fixed the relative documentation in various places (backported + to 2.2.2). +- Many documentation improvements. + +*** 2.1.8 *** +- FIX: Fixed error in STM32 ADC driver macro names (bug 3160306)(backported + to 2.0.11). +- FIX: Fixed IAR Cortex-Mx port memory organization problem (bug 3158776). +- FIX: Fixed STM32F103 demo's incorrect clock settings (bug 3153746). +- NEW: Added OTG clock setting to the STM32 HAL. +- NEW: Added stack check support to the IAR Cortex-Mx port. +- CHANGE: Removed .uvopt files from the Keil projects. + +*** 2.1.7 *** +- FIX: Fixed various errors in the HAL documentation (bug 3153591). +- FIX: Fixed error in chIOGetxxxxxEventSource() macros (bug 3153550) + (backported to 2.0.10) +- FIX: Fixed error in STM32 unbuffered UART driver (bug 3153437). +- FIX: Fixed wrong macro check in LPC214x driver (bug 3152510). +- FIX: Fixed switch condition error in STM32 PWM driver (bug 3152482) + (backported to 2.0.10). +- FIX: Fixed error in output queues static initializer (bug 3149141) + (backported to 2.0.9). +- FIX: Fixed extra notifications in input queues (bug 3148525)(backported + to 2.0.9). +- NEW: New ARM Cortex-Mx port for RVCT compiler. +- NEW: Integrated the various Cortex-Mx GCC, IAR and RVCT demos in unified + demos with multiple project files, the code is exactly the same. Renamed + the directories removing the compiler suffix. +- NEW: Added an USB clock configuration in the STM32 HAL driver (LD, MD, HD). +- NEW: New semaphore API chSemSetCounterI(). +- NEW: New queue APIs chIQGetFullI() and chOQGetFullI(). +- CHANGE: Serial drivers now have a single event source instead of three, + the event source is located in the superclass, this allows to create + alternative implementations of the serial driver while keeping compatibility, + the change also allowed to save 8/4 RAM bytes per serial driver. +- CHANGE: Modified the ADC and CAN drivers to allow a NULL pointer for + the configuration structure if it is not required by the implementation. +- CHANGE: Modified the MMC_SPI driver to *require* a NULL as pointer to + the configuration. +- CHANGE: Removed enforced inlining for the chSchReadyI() function when + the CH_OPTIMIZE_SPEED is enabled. Now the matter is left to the compiler + specific settings. This change is meant to increase compatibility with + compilers that have a different inlining semantic than GCC when not in + C99 mode. +- CHANGE: Changed the declaration of the main() function in all demos + without arguments. Removed the clearing of arguments from the startup + files and saved some space. +- CHANGE: Queues callbacks now have as parameter a pointer to the queue, + there were no parameters previously. +- Documentation related fixes. + +*** 2.1.6 *** +- FIX: Fixed error in sdPutTimeout() macro (bug 3138763)(backported in 2.0.9). +- NEW: New ARM Cortex-Mx port for IAR compiler. +- NEW: Now the STM32 CAN driver puts the lower half word of the ESR + register in the upper half word of the can status word for easier + debug. +- CHANGE: Changes in the board files organization, now the board + initialization is invoked from within halInit() after all the device + drivers have been initialized. Now applications are required to + explicitly invoke halInit() and chSysInit() from within their main(). +- CHANGE: Removed the CMSIS files from the ARMCMx port, added the headers + into the various HAL platforms requiring them. The change is required + because the port layer must not have vendor specific dependencies and + there is the possibility that the various vendors would use different + CMSIS versions now that CMSIS 2.x has been released. +- CHANGE: Modified the start of the ADC in the STM32 ADC driver, now it is + no more required to specify ADC_CR2_EXTSEL_SWSTART and ADC_CR2_CONT + in the CR2 register configuration. Also reordered the start sequence + in order to allows a longer stabilization time for the ADC. +- Documentation improvements. + +*** 2.1.5 *** +- FIX: Fixed references to non-existing SSP1 device in LPC13xx SPI device + driver (bug 3127926). +- FIX: Fixed broken SPI synchronous API (bug 3127921). +- FIX: Fixed missing vector.c files in LPC11xx and LPC13xx ports (bug 3124849). +- FIX: Fixed pwmDisableChannel() now working in STM32 PWM driver (bug 3121246). +- FIX: Fixed problem with PWM channel callbacks (bug 3120785). +- NEW: Added support for TIM5 in the STM32 PWM driver. +- NEW: Added to the ARM port the option to externally redefine the port IRQ + macros in order to accomodate different implementations without have to + change the port layer. +- CHANGE: Modified the STM32_PWM_PWMx_IRQ_PRIORITY macros in the STM32 + PWM driver (and all the STM32 mcuconf.h files) and renamed them in + STM32_PWM_TIMx_IRQ_PRIORITY for consistency. +- Documentation related fixes. + +*** 2.1.4 *** +- FIX: Fixed failed memory recovery by registry scan, improved the related + test case (bug 3116888)(backported to 2.0.8). +- FIX: Fixed failure in STM32 ADC driver when a linear buffer mode is used + (bug 3114696). +- FIX: Fixed PWM channels going to ACTIVE state when the pulse width is + set to zero in the STM32 PWM driver (bug 3114481)(backported to 2.0.8). +- FIX: Fixed PWM channels return to IDLE state in STM32 PWM driver (bug + 3114467)(backported to 2.0.8). +- FIX: Fixed wrong initializer macros in STM32 PWM driver (bug 3114319). +- FIX: Fixed syntax error in STM32 PWM driver(bug 3114266). +- FIX: Fixed typo in board name (bug 3113574)(backported to 2.0.7). +- FIX: Fixed defective event wait functions with timeout (bug 3113443) + (backported to 2.0.7). +- NEW: More improvements to the ADC and SPI drivers, now synchronous + operations can also have callbacks, optimized ISR code paths. +- NEW: Added to the STM32 ADC driver the macros for easy handling of the + sampling time for each channel. +- NEW: Greatly simplified the STM32 PWM driver implementation. +- NEW: Added new macro PWM_FRACTION_TO_WIDTH() to the PWM driver model. +- NEW: ARM7 port reorganization following the same pattern of the ARMCMx + one, on now the port is also supports the ARM9 architecture (but not + tested yet hardware). Removed the dependencies between the port layer + and the vendors-provided headers. +- NEW: Initial STM8L support: HAL, PAL and Serial drivers. +- NEW: Added demo for the ST STM8L-Discovery kit. +- NEW: Added support for the STM32 Value Line to the HAL. +- NEW: Added demo for the ST STM32VL-Discovery kit. +- OPT: STM32 SPI driver implementation improved, reduced latency when + starting a transfer. +- CHANGE: Improved the STM32 HAL to support multiple sub-families, at compile + time now it is possible to test the presence of any single peripheral into + the specified STM32 device. +- CHANGE: Separated dynamic threads code into dedicated files: chdynamic.c + and chdynamic.h. +- CHANGE: Moved the declaration of the variable pal_default_config from + hal_lld.c to the various board.c. That structure is more meaningful in + the board layer because it is related to the board initialization. +- CHANGE: Removed the various assembler files for the STM32 interrupt + vectors, now it is a single vectors.c file. +- CHANGE: Deleted ./os/ports/GCC/ARM. +- CHANGE: Renamed ./os/ports/GCC/ARM7 in ./os/ports/GCC/ARM. +- CHANGE: Renamed ./os/hal/platforms/STM8 in ./os/hal/platforms/STM8S. +- CHANGE: Renamed ./testhal/STM8 in ./testhal/STM8S. +- Added SPI driver to the STM8S documentation, it was missing. +- Improved documentation for the ARM and ARMCMx ports. + +*** 2.1.3 *** +- FIX: Fixed broken STM32 synchronous UART driver (bug 3100946). +- FIX: Broken C++ wrapper (bug 3100925). +- FIX: Broken lwIP/uIP demos (bug 3100901). +- FIX: DMA not initialized under some conditions (bug 3099701). +- FIX: Restored the RIDE7 build files in the STM32F103 demo, note the RIDE7 + build files are not supported so this has not been tracked as a bug. +- NEW: Added an SPI driver to the STM8 platform support. +- NEW: Added a simple STM8 SPI demo under ./testhal/STM8/SPI. +- NEW: Divided the file STM32/vectors.s in several files, one for each + STM32 sub-family. This has been done in order to remove the preprocessor + directives from assembler files and to support all the various STM32 + sub-families. +- CHANGE: Renamed ./os/ports/GCC/ARMCMx/STM32F10x in STM32. +- CHANGE: Divided the file ARMCMx/crt0.s in crt0_v6m.s and crt0_v7m.s in + order to remove the preprocessor directives from assembler files. +- CHANGE: Renamed the HAL settings macro names, removed the CH_ prefix + because it is reserved for the kernel namespace. + NOTE: ****** Make sure to use a mcuconf.h file taken from ****** + ****** this version in your project. ****** + +*** 2.1.2 *** +- FIX: Fixed typo in memstreams.h (bug 3089567)(backported to 2.0.6). +- FIX: Fixed wrong macro check in LPC214x and AT91SAM7 serial drivers (bug + 3088776)(backported to 2.0.6). +- FIX: Fixed non functioning option SPI_USE_MUTUAL_EXCLUSION=FALSE (bug + 3084764)(backported to 2.0.6). +- FIX: Fixed wrong macro check in STM32 serial support (bug 3078891)(backported + to 2.0.6). +- FIX: Fixed non functioning option CH_USE_NESTED_LOCKS (bug 3075544) + (backported to 2.0.6). +- FIX: Incorrect AT91SAM7X initialization, thanks Leszek (bug 3075354) + (backported to 2.0.5). +- FIX: Fixed race condition in function chSchGoSleepTimeoutS(), thanks Bal�zs + (bug 3074984)(backported to 2.0.5). +- FIX: Fixed race condition in threads creation (bug 3069854)(backported + to 2.0.5). +- FIX: Fixed broken CH_DBG_ENABLE_STACK_CHECK option in legacy CM3 port (bug + 3064274)(backported to 2.0.5). +- FIX: Fixed CAN_USE_SLEEP_MODE setting (bug 3064204)(backported to 2.0.5). +- FIX: Fixed potential issue with GCC reorganizing instructions around "asm + volatile" statements (bug 3058731)(backported in 2.0.4). +- FIX: Fixed reduced ARM7 performance with GCC 4.5.x (bug 3056866)(backported + to 2.0.4). +- FIX: Fixed crash of the Posix simulator under Ubuntu 10.4 (bug 3055329) + (backported to 2.0.3). +- FIX: Fixed incorrect PLL2 setting in STM32 HAL (bug 3044770)(backported + in 2.0.3). +- FIX: Fixed wrong check on STM32_HCLK (bug 3044758)(backported to 2.0.3). +- FIX: Fixed wrong condition check in STM32 PWM driver (bug 3041414) + (backported in 2.0.3). +- FIX: Corrupted IRQ stack in Cortex-Mx port (bug 3041117)(backported to + 2.0.3). +- FIX: Fixed a documentation error regarding the ADC driver function + adcStartConversion() (bug 3039890)(backported to 2.0.3). +- NEW: New I2C driver model (not complete and no implementations yet). +- NEW: New SPI driver model, the new model supports both synchronous and + asynchronous operations and, in general, simplifies the implementation of the + low level driver. The new driver also specifies a simplified polled exchange + API, useful for efficiently sending small amount of data over high speed + connections. The driver state diagram changed slightly changed so be careful. +- NEW: New ADC driver model, the new model supports both synchronous and + asynchronous operations and, in general, simplifies the implementation of the + low level driver. The driver state diagram changed slightly changed so be + careful. +- NEW: Improved PWM driver model, added several macros that helps to setup + configuration structures and to specify pulse widths also as percentages or + degrees using a fixed point notation. Added new pwmEnableChannelI() and + pwmDisableChannelI() APIs in order to allow channel reprogramming from + within callbacks or interrupt handlers, the new APIs are implemented as + macros so there is no footprint overhead. +- NEW: Added driver fields and initialization hooks for the callback-based + drivers. The hooks are named XXX_DRIVER_EXT_FIELDS and + XXX_DRIVER_EXT_INIT_HOOK(). +- NEW: Added to the UART driver the capability to return the number of + not yet transferred frames when stopping an operation. +- NEW: Added more compile-time checks to the various STM32 device drivers. +- NEW: Improved LPC214x SPI driver, now it uses IRQs, it implements the + new SPI device driver model. +- NEW: Improved AT91SAM7 SPI driver, now it uses IRQs and DMAs, it implements + the new SPI device driver model. +- NEW: New LPC11xx SPI driver, updated the LPCXpresso demo to use the SPI. +- NEW: New LPC13xx SPI driver, updated the LPCXpresso demo to use the SPI. +- NEW: Added a simple STM32 ADC demo under ./testhal/STM32/ADC. +- NEW: Added a simple STM32 CAN demo under ./testhal/STM32/CAN. +- NEW: Added a simple STM32 PWM demo under ./testhal/STM32/PWM. +- NEW: Added a simple STM32 SPI demo under ./testhal/STM32/SPI. +- NEW: More assertions added to the kernel for improved bug fixing. +- NEW: New kernel hooks: SYSTEM_TICK_EVENT_HOOK(), SYSTEM_HALT_HOOK(). +- NEW: Added board files for the Olimex STM32-H103. +- NEW: New kernel APIs chSysGetIdleThread() and chThdGetTicks(), the new + APIs are simple macros so there is no footprint overhead. +- NEW: Added a generic BaseFileStream interface for future File System + implementations or integrations (untested and not sure if it will stay or + change). +- NEW: Added to the documentation more notes about interrupt handlers in + the ARM7 port. +- NEW: Modified some tests in order to bring back code coverage to 100% + in all modules except chdebug.c. Added a test case covering binary + semaphores. +- OPT: The fix to the bug 3075544 considerably improved the threads creation + benchmarks score. +- OPT: Speed optimizations to the STM32 SPI driver, greatly improved latency. +- OPT: Speed optimizations to the STM32 ADC driver. +- CHANGE: The API chThdInit() has been renamed to chThdCreateI() in order to + make clear it is usable from interrupt handlers. +- CHANGE: The mailboxes macros chMBSize(), chMBGetEmpty(), chMBGetFull(), + chMBPeek() have been renamed to chMBSizeI(), chMBGetFreeCountI(), + chMBGetUsedCountI(), chMBPeekI(). +- CHANGE: The queue APIs chQSize(), chQSpace(), chIQIsEmpty(), chIQIsFull(), + chOQIsEmpty(), chOQIsFull() have been renamed to chQSizeI(), chQSpaceI(), + chIQIsEmptyI(), chIQIsFullI(), chOQIsEmptyI(), chOQIsFullI(). +- CHANGE: The event APIs chEvtPend() and chEvtClear() have been renamed + to chEvtAddFlags() and chEvtClearFlags() for consistency and correct + English. Changed the macro chEvtIsListening() in chEvtIsListeningI(). +- CHANGE: Added a parameter to the PWM driver callbacks, the pointer to the + driver itself. +- CHANGE: Added a parameter to the UART driver callbacks, the pointer to the + driver itself. +- CHANGE: In the UART driver now an error does not automatically brings the + receiver in UART_RX_IDLE state, the receive operation continues unless + explicitly stopped in the error callback handler. This considerably + simplifies the low level driver code. +- CHANGE: Removed a spurious trailing ; after the WORKING_AREA() macro + declaration in several ports. The ; should go after the macro invocation. +- CHANGE: Modified the STM32 ADC driver to use the new DMA infrastructure. +- CHANGE: Modified the STM32 SPI driver to use the new DMA infrastructure. +- CHANGE: Added DMA cleanup code to the STM32 dmaInit() function. +- CHANGE: Simplified preprocessor conditions in the STM32 serial driver. +- CHANGE: Renamed most of the STM32 HAL settings macro names in order to + make names more consistent. + NOTE: ****** Make sure to use a mcuconf.h file taken from ****** + ****** this version in your project. ****** +- CHANGE: Renamed the existing system hooks by adding the _HOOK suffix to + the name in order to make names more consistent. + NOTE: ****** Make sure to use a chconf.h file taken from ****** + ****** this version in your project. ****** +- CHANGE: Extensive documentation improvements, fixed terminology in the + events related documentation and articles. +- CHANGE: The documentation is no more included in the distribution, the + file ./documentation.html redirects to the online documentation page + that contains *much* better documents. + Note that it is still possible to generate the local documentation using + Doxygen, the procedure is very simple and described in ./docs/readme.txt. + +*** 2.1.1 *** +- FIX: Fixed insufficient stack size for idle thread (bug 3033624)(backported + to 2.0.3). +- FIX: Fixed misspelled word in some chioch.h and chstreams.h macros (bug + 3031534)(backported to 2.0.3). +- FIX: Fixed wrong macro check in the STM32 SPI driver (bug 3028562)(backported + to 2.0.3). +- FIX: Fixed invalid context restore in MSP430 port (bug 3027975)(backported + to 2.0.2). +- FIX: Fixed STM32 vectors file (bug 3026528)(backported to 2.0.2). +- FIX: Fixed race condition in STM32 SPI driver (bug 3025854)(backported to + 2.0.2). +- FIX: Fixed H_LOCK and H_UNLOCK redefined with CH_USE_MALLOC_HEAP (bug + 3025549)(backported to 2.0.2). +- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the + Cortex-Mx port (bug 3025133)(backported to 2.0.2). +- NEW: Centralized DMA macros in the STM32 HAL. +- NEW: New UART device driver model, this device driver allows unbuffered, + callback driven access to UART-type devices. +- NEW: UART device driver for STM32 and UART demo application under + ./testhal/STM32/UART. +- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request + 3023944). +- NEW: Added support for SPI3 in the STM32 HAL. +- CHANGE: Redeclared the IRQ handlers in the various STM32 drivers using the + new friendly vector names. +- CHANGE: Moved the STM32 HAL stess test application under + ./testhal/STM32/_stress_test. +- CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The + option is not compatible with the 64 bits stack alignment now default in + the Cortex-Mx port. Note that the 64 bits alignment has a cost both as + performance and as space but it is the "standard". +- OPT: Small speed optimization in the STM32 SPI driver. +- OPT: Optimized DMA clearing in STM32 ADC and SPI drivers, there was no need + to read/modify/write the IFCR DMA register, it is write only. +- Fixed various documentation errors. + +*** 2.1.0 *** +- FIX: Fixed notification order in input queues (bug 3020708)(backported in + 2.0.1). +- FIX: Fixed non functional CH_CURRP_REGISTER_CACHE option in the Cortex-M3 + port (bug 3020702)(backported in 2.0.1). +- FIX: Fixed non functional CH_DBG_ENABLE_STACK_CHECK option in the Cortex-M3 + caused by GCC 4.5.0, the fix also improves the context switch performance + because GCC 4.5.0 apparently was generating useless instructions within the + very critical context switch code (bug 3019738)(backported in 2.0.1). +- FIX: Fixed insufficient stack space assigned to the idle thread in + Cortex-M3 port (bug 3019594)(backported in 2.0.1). +- FIX: Fixed missing check in chIQReadTimeout() and chIQWriteTimeout() (bug + 3019158)(backported in 2.0.1). +- FIX: Fixed instability in Mutexes subsystem (bug 3019099)(backported + in 2.0.1). +- FIX: Fixed broken AVR port (bug 3016619)(backported in 2.0.0). +- FIX: Fixed assertion in adcStop() (bug 3015109)(backported in 2.0.0). +- NEW: Merged the new unified STM8 port, now the port supports both the + Cosmic and Raisonance compilers. +- NEW: Added an STM8-DISCOVERY demo, the demo can be compiled with both the + Cosmic and Raisonance compilers under the STDV IDE. Performance reports + have been added for both compilers. + NOTE: The Raisonance compiler seems to have problems in debugging under + the STDV IDE, if you need to debug using the Raisonance compiler + consider using the RIDE7 IDE instead. + Compiling and executing using the "release" mode under STDV works fine. +- NEW: Added timers clock macros to the STM32 clock tree HAL driver (backported + in 2.0.1). +- NEW: Added Binary Semaphores among the synchronization primitives. The new + subsystem is entirely implemented as macros over the existing and proven + Counting Semaphores thus takes no space (experimental). +- NEW: Added a simplified SPI driver for AT91SAM7 devices, contributed by + Alexander (experimental). +- NEW: Added FatFs demos for AT91SAM7S and AT91SAM7X, contributed by + Alexander (experimental). +- OPT: Simplified the test suite code, now it is smaller. +- Reorganized the documentation, now the description of the device drivers + implementation is under the HAL module instead of the Ports module. + +*** 1.5.9 *** +- FIX: Fixed STM8 baud rate setup error (bug 3010990). +- FIX: Fixed STM8 UART3 driver (bug 3009145). +- NEW: Added a STM8_ENABLE_WFI_IDLE option to the STM8 port, the default + is FALSE. +- OPT: Small size optimization in the semaphores subsystem. +- OPT: Improvements in the STM8 port, the code is now smaller and generally + faster, also saved few bytes of RAM. +- Added explicit casts in chevents.h, chqueues.h, chqueues.c in order to + silence some warnings on a specific compiler. +- Added a section in chconf.h where redefine the port-related configuration + parameters, also added notes into the documentation about this. + +*** 1.5.8 *** +- FIX: Fixed missing files from ST library zip file (bug 3006629). +- NEW: Added a demo for the AT91SAM7S256 and board files for the Olimex + SAM7-P256. The demo has been contributed by Alexander Kozaruk. +- Fixed some wrong paths into the demos readme files. +- Formatting fixes to the port templates. +- Added notes about copyright assignment to the documentation. Fixed some + problems in the licensing FAQ page. +- Added documentation article about events in ChibiOS/RT. + +*** 1.5.7 *** +- FIX: Fixed missing SPI driver reinitialization in the MMC driver (bug + 3005628)(backported in 1.4.4). +- FIX: Fixed wrong inclusion order of board.h and halconf.h into hal.h + (bug 3005041)(backported in 1.4.4). +- FIX: Fixed wrong GPIO ports size in the STM8 PAL driver (bug 3001528). +- NEW: Improved clock initialization for the STM32, now it is possible to + configure the clock using any clock source and any HSE frequency. +- NEW: The STM32 clock tree parameters and checks are now calculated into + a separate file in order to support multiple clock trees for different + sub-families of the STM32 platform. +- NEW: Added separated clock trees for the STM32 LD/MD/HD sub-family and + the CL sub-family. Now the selection of the sub-family is done in the + board.h file, there is no more the need to put -DSTM32F10X_xx into + the makefile. +- NEW: Added the palSetBusMode() capability to the STM8 PAL driver. +- NEW: Added the palSetBusMode() capability to the LPC11xx and LPC13xx + PAL drivers. +- NEW: Updated the STM32 FW Library files to latest version 3.3.0. +- CHANGE: Renamed the STM32, STM8, LPC214x, AT91SAM7x, MSP430 and simulators + PAL configuration structures to PALConfig, it is better to have the same + name for this structure in all ports (like for all the other drivers). +- CHANGE: Modified the linker scripts in the ARM demos in order to increase + compatibility with the CodeSourcery toolchain. +- Tested the STM8 port with the latest RKit-STM8_2.28.10.0092. It works but + the new compiler shows a slight performance regression except in one + test case. +- Added credits page to the documentation, improved the article regarding + timings. +- Performed another documentation revision cycle, fixed more bad English and + few errors. + +*** 1.5.6 *** +- FIX: Fixed centralized ARM makefile (bug 2992747)(backported in 1.4.3). +- FIX: Fixed write problems in MMC_SPI driver (bug 2991714)(backported in + 1.4.3). +- FIX: Fixed wrong macros in chioch.h (bug 2989468). +- FIX: Fixed wrong macro check in serial.h (bug 2989459)(backported in 1.4.3). +- NEW: Added a ROMCONST macro in chtypes.h, this macro must be used for + constant that must be placed in code space, it should not be assumed that + the "const" keyword does that. Note that this macro is not used to place + constants in different address spaces (AVR) because it is assumed that a + pointer to a ROMCONST variable is compatible with a normal pointer. +- NEW: AT91SAM7 HAL support for the DGBU UART peripheral, as SD3. +- NEW: Introduced a new macro CH_FAST_IRQ_HANDLER() for the declaration of + fast interrupt handlers on those architectures that support them. +- OPT: Internal optimization in the serial driver, it now is a bit smaller + and uses less RAM (all architectures). +- CHANGE: Modified the STM32 FatFs demo, now it spawns a command shell or + the serial port SD2, type "help" for the available commands. More commands + can be easily added. +- CHANGE: Renamed the chCoreFree() function in chCoreStatus() because it + might be mistaken for a function that frees memory. +- CHANGE: All ARM demos makefiles now defaults to arm-none-eabi- GNU + toolchains because the latest YAGARTO now uses that setting. It is still + possible to use arm-elf- toolchains by editing the TRGT variable in the + makefiles. +- Various documentation fixes, added new articles covering debugging under + ChibiOS/RT, OS integration, OS stop and restart. Updated the article about + interrupt handlers to cover also fast interrupt sources, updated the article + about the OS porting. +- Long overdue test code cleanup and documentation. +- Added new test cases, now the coverage is again up to 100% except for the + debug module that would require triggering system terminating tests (panics), + the uncovered code is minimal, extremely simple and working anyway. +- ChibiOS/RT has been successfully verified with the latest GCC 4.5.0. + +*** 1.5.5 *** +- FIX: Removed some "dead" code in the old ARMv7-M files (there are new + ones, see below). +- NEW: LPC13xx support, drivers (Serial, PAL, HAL), demo and reports. +- NEW: Added statistic info to the lwIP demo. +- CHANGE: Renamed LPC111x port and platform in LPC11xx, minor fixes to the + platform header files. +- CHANGE: Small documentation fixes and improvements. +- OPT: New Cortex-M3 port code, *huge* performance improvements in all the + context switching related benchmarks (up to 18% depending on the benchmark). + The new code does no more require the use of the PendSV vector that is + thus available to the user, it also saves four RAM bytes for each thread + in the system. The old code is still available as a fall back option while + the new one is being hardened by peer review and time, the two ports are + perfectly interchangeable. + +*** 1.5.4 *** +- FIX: Fixed broken CH_CURRP_REGISTER_CACHE option in the ARM7 port (bug + 2973365). +- FIX: Fixed missing memory recovery on thread reference release in + chRegNextThread() (bug 2971878). +- FIX: Fixed wrong thread state macro in STM32/spi_lld.c (bug 2968142). +- NEW: New unified ARM Cortex-Mx port, this port supports both the ARMv6M + and ARMv7-M architecture (Cortex-M0/M1/M3/M4 so far). The new port also + allow to easily add to new Cortex-M implementations by simply adding a + parameters file (cmparams.h). +- NEW: Embedded Artists LPCxpresso Base Board support files added. +- NEW: LPC111x support, drivers (Serial, PAL, HAL) and demo. +- NEW: The port layer now can "capture" the implementation of individual + scheduler API functions in order to provide architecture-optimized + versions. This is done because further scheduler optimizations are + becoming increasingly pointless without considering architecture and + compiler related constraints. +- NEW: Added support for the STM8 large memory model to the STM8 port. Now + the assembler port code is totally inlined and the chcoreasm.asm file has + been removed. +- NEW: Added RIDE7 project files to the STM32 demo under a ./ride7 + subdirectory, this should make things easier for RIDE7 users. The normal + makefile is still available of course. +- NEW: New articles and guides in the documentation. +- NEW: Documentation improvements, now the description goes on top of each + page, doxygen defaulted it in the middle, not exactly the best for + readability. Improved many descriptions of the various subsystems. Fixed + a misplaced page (STM8 port). +- OPT: Optimization on the interface between scheduler and port layer, now + the kernel is even smaller and the context switch performance improved + quite a bit on all the supported architectures. +- OPT: Simplified the implementation of chSchYieldS() and made it a macro. + The previous implementation was probably overkill and took too much space + even if a bit faster. +- CHANGE: Modified the Cortex-M3 port to be a more generic Cortex-Mx port, + changes were required to the startup code and the port code because the + reduced instruction set of the Cortex-M0 (there are two code paths now, + both optimized). +- CHANGE: Modified the SysTick initialization for STM32 to use the system + clock rather than the external clock. +- CHANGE: Exiting from a chCondWaitTimeout() because a timeout now does not + re-acquire the mutex, ownership is lost. +- CHANGE: The module documentation has been moved from the kernel.dox file + to the various source code files in order to make it easier to maintain + and double as source comments. +- CHANGE: Updated CMSIS files to version 1.3 and fixed the warnings in there, + again... + +*** 1.5.3 *** +- FIX: Removed C99-style variables declarations (bug 2964418)(backported + in 1.4.2). +- FIX: Fixed missing reschedule in chEvtSignal() (bug 2961208)(backported + in 1.4.2). +- NEW: Added STM8 port and demo, the demo targets the Raisonance REva board + with STM8S208RB piggyback. +- NEW: Enhanced the kernel size report to cover more cases. +- NEW: Improvements to the documentation. +- OPT: Minor optimizations in the "compact" code path. + +*** 1.5.2 *** +- FIX: Fixed wrong UART deinitialization sequence in LPC214x serial driver + (bug 2953985)(backported in 1.4.1). +- FIX: Fixed wrong PINSEL2 offset into lpc214x.h (bug 2953981)(backported + in 1.4.1). +- FIX: Fixed invalid UART-related macro in the LPC214x HAL (bug 2953195) + (backported in 1.4.1). +- FIX: Impossible to enforce alignment greater of a pointer size for heap/core + objects (bug 2952961). +- FIX: Wrong prototype in template file chcore.c (bug 2951529)(backported + in 1.4.1). +- NEW: Added an experimental PowerPC port targeting the SPC563M/MPC563xM + ST/Freescale automotive SOCs. The port passed the whole test suite but it + will be developed further in next releases. +- NEW: Added core variant name macro in chcore.h and platform name in + hal_lld.h, the info are printed in the test report and from the "info" + shell command. +- NEW: Added BOARD_NAME macro to the various board.h files. +- NEW: Added a MemoryStream class under ./os/various. +- CHANGE: Removed an instance of a structure without name from test.h for + increased portability of the test suite. +- NEW: Added Mac OS-X support for the simulator. The Linux simulator has + been renamed to Posix simulator in order to include this change in a + single project. +- NEW: New articles, sections and various improvements to the documentation. +- CHANGE: Renamed the kernel header files to match the names of their source + files. The change was also required in order to make the names less + "generic" and less likely to match names in external libraries. + +*** 1.5.1 *** +- FIX: Fixed insufficient stack space for the idle thread in the ARMCM3 port + when compiling without optimizations (bug 2946233)(backported in 1.4.1). +- FIX: Fixed wrong notes on function chThdResume() (bug 2943160)(backported + in 1.4.1). +- NEW: Implemented the concept of thread references, this mechanism ensures + that a dynamic thread's memory is not freed while some other thread still + owns a reference to the thread. Static threads are not affected by the new + mechanism. Two new APIs have been added: chThdAddRef() and chThdRelease(). +- NEW: Now more than one thread can be waiting in chThdWait() as long they + own a reference. +- NEW: Implemented a new threads registry subsystem, the registry allows to + enumerate the active threads at runtime and/or from a debugger. This is + a preparatory step for a dedicated ChibiOS/RT debugger. +- NEW: New chCoreFree() API that returns the core memory left. +- NEW: Added to the simulators shell demos two new commands: threads and mem, + that show the currently active threads (using the new registry) and the + memory allocators state. +- CHANGE: Doxygen tags cleanup in all the system code, comments are better + looking now. +- CHANGE: Documentation improvements. + +*** 1.5.0 *** +- FIX: Fixed missing dependencies check for CH_USE_DYNAMIC (bug 2942757) + (backported in 1.4.1). +- FIX: Fixed swapped thread states descriptions (bug 2938445)(backported in + 1.4.1). +- FIX_ Fixed C99-style variable declaration (bug 2938444)(backported in 1.4.1). +- FIX: Fixed parameter check in sdStart() function (bug 2932922)(backported in + 1.4.0). +- FIX: Fixed missing platform.mk file in MSP430 port (bug 2933735)(backported + in 1.4.0). +- CHANGE: Removed the unnamed union from the thread and heaps structures, + some compilers do not support this non standard construct. +- CHANGE: Removed the empty structures from the streams/channels headers. +- CHANGE: Modified the thread-related constant macros to have a THD_ prefix. +- CHANGE: Modified NULL assignments to function pointers to use an explicit + cast because some compilers issue warnings without the cast. +- OPT: Speed/size optimization to the events subsystem. +- OPT: Speed/size optimization to the mutexes subsystem. +- OPT: Speed/size optimization to the condvars subsystem. +- OPT: Speed/size optimization to the synchronous messages subsystem. +- NEW: Added support for STM32/HD/CL UART4 and UART5, thanks Egon for the + patch. + +*** 1.3.8 *** +- FIX: Fixed dequeuing in lifo_remove() function (bug 2928142). +- FIX: Fixed spurious character generation in MSP430 serial driver (bug + 2926838). +- NEW: Introduced an abstract streams interface BaseSequentialStream. +- NEW: Added timeout specification to the I/O queues read/write primitives. +- NEW: Added support for HD and CL STM32 devices in the vectors table. +- CHANGE: Modified the BaseChannel interface in order to make it a + BaseSequentialStream descendant. +- CHANGE: Updated the serial driver model in order to expose the + BaseSequentialStream methods. +- CHANGE: The behavior of the read/write primitives is changed, now the + functions are synchronous and do not return until the specified number of + bytes have been transferred or a timeout occurs, the old behavior can be + replicated by specifying TIME_IMMEDIATE as timeout. Another difference is + that specifying zero as bytes number is like specifying the largest size_t + plus one, zero was an illegal value before. +- CHANGE: Simplified the LPC214x driver by removing the option to not use the + FIFO preload feature. Setting LPC214x_UART_FIFO_PRELOAD to 1 results in + the same behavior. +- Documentation fixes and improvements, testing strategy explained. +- Added article about waking up threads from IRQ handlers. + +*** 1.3.7 *** +- FIX: Fixed duplicated definition of SPI_USE_MUTUAL_EXCLUSION (bug 2922495). +- FIX: Fixed coverage tool hanging during execution (bug 2921120). +- FIX: Fixed Linux simulator startup message (bug 2921012). +- FIX: Fixed section separators comments into the HAL-related files. Now all + the files should use the same style. +- NEW: Improved HAL configuration file. +- NEW: Introduced a new, per-project, MCU configuration file mcuconf.h that + contains all the drivers related settings. +- NEW: Readability improvements to the channels code. +- NEW: Serial driver model improvements, added states management and checks, + added a new SD_NOISE_ERROR error event. +- NEW: Improvements and optimizations in the various serial driver + implementations. +- Documentation fixes and improvements. + +*** 1.3.6 *** +- FIX: Fixed missing STM32 PWM low level driver error in platform.mk by + adding the driver files (bug 2913560). +- NEW: The Linux simulator now works again, also supports the serial + drivers over TCP/IP and has a command line interface like the Win32 + simulator. +- NEW: STM32 PWM driver implementation. +- NEW: LPC214x SPI driver implementation (SSP only, polled mode, no IRQ), this + driver replaces the old, not HAL compatible, SSP driver. +- NEW: LPC214x FatFS demo added, LPC214x minimal demo removed, LPC214x "normal" + demo reduced to work like all the other generic demos. +- NEW: Added custom mode settings to the STM32 PAL driver: + - PAL_MODE_STM32_ALTERNATE_PUSHPULL + - PAL_MODE_STM32_ALTERNATE_OPENDRAIN +- NEW: Included all the board-specific files into a new directories structure + under ./boards, this allows to not duplicate the board files into each demo. +- CHANGE: Changes to the PWM driver model, made it simpler. +- CHANGE: The STM32 device drivers now no more configure the I/O pins on + initialization. Pins must be configured in board.h, the change was required + in order to support the STM32 AFIO remapping feature. +- CHANGE: Removed the mmcsd.c driver, it is replaced by the generic MMC_SPI + driver present into the HAL. +- CHANGE: Updated the GPL exception text in the documentation, this should be + the final text for the stable version 1.4.x. + +*** 1.3.5 *** +- FIX: Fixed problem with memory core allocator (bug 2912528). +- FIX: Fixed problem with CH_USE_MEMCORE option (bug 2912522). +- FIX: Fixed some problems in the MMC_SPI driver (bugs 2901084 and 2901172). +- NEW: Added a command line shell component, modified the Win32 simulator + in order to use the new shell. The shell can be used under any architecture, + it just requires an I/O channel. Custom commands can be easily added. +- NEW: Unified the initialization of the various drivers from a single HAL + driver. The single drivers can be enabled or disabled from a HAL + configuration file halconf.h. +- NEW: New CAN driver model. +- NEW: New PWM driver model. +- NEW: STM32 ADC driver implementation with DMA support. +- NEW: STM32 CAN driver implementation. +- NEW: Extended the support to all the SAM7X and SAM7S devices thanks to + code contributed by Liam Staskawicz. +- NEW: Improvements to the AT91SAM7 startup code contributed by Liam. +- NEW: Added test report for MSP430 running from the external high speed + oscillator. +- NEW: HAL stress test for STM32 added, the demo is located under + ./testhal/STM32. The demo code also shows how to use the ADC, CAN and SPI + drivers. +- CHANGE: Removed the MII from the standard drivers, now it is part of the + AT91SAM7 support, the header mii.h is still part of the HAL. +- CHANGE: In the STM32 drivers now the DMA errors are handled by hook macros + rather than by events. The default action is to halt the system but users + are able to override this and define custom handling. +- CHANGE: In the Cortex-M3 port, modified the NVICEnableVector() function + to make it clear pending interrupts. +- CHANGE: Minor changes to the ADC driver model. + +*** 1.3.4 *** +- FIX: Fixed bug in STM32 PAL port driver (bug 2897636). +- FIX: Fixed problem with ARM-CM3 context switch when compiled at level + -O0 (bug 2890382). +- FIX: Fixed wrong conditional in chschd.c (bug 2888836). +- FIX: Fixed wrong macro in chheap.c (bug 2888833). +- FIX: Fixed AIC initialization in AT91SAM7X support (bug 2888583). +- NEW: New SPI (master) driver model. +- NEW: SPI driver for STM32 implementing the new SPI driver model. +- NEW: New ADC (streaming capable) driver model. +- NEW: Generic MMC (over SPI) driver. +- NEW: Added a STM32 demo that integrates the MMC driver and the FatFs + file system. +- NEW: Implemented I/O redirection on a serial driver into syscalls.c, now + it is possible (but not recommended) to use printf()/scanf() etc. An usage + example is in the new MMC/FatFs demo. Note the extra -D... into the Makefile. +- CHANGE: Moved the STM32 firmware library under ./ext, this way there is no + need to duplicate it in each demo program. +- CHANGE: Moved the file stm32f10x.h from the demos to the platforms support + directory. + +*** 1.3.3 *** +- FIX: Fixed bug in the LPC2148 PAL driver (bug 2881380). +- FIX: Fixed bug in the AT91SAM7X PAL driver (bug 2879933). +- NEW: New MAC and MII driver models and implementations for the AT91SAM7X. + Removed the old EMAC driver, updated the uIP WEB demo to use the new + driver model. +- NEW: Added a simple lwIP demo (web server) for the AT91SAM7X. +- NEW: Centralized core memory manager. This simple allocator implements a + sbrk()-like API: chCoreAlloc(). The other allocators now use this manager + in order to get memory blocks. +- NEW: The heap allocator has been modified, now it is possible to have + multiple heaps. The default heap gets its memory from the new core memory + manager. +- NEW: Now memory pools can optionally get new objects automatically from the + core memory manager. +- NEW: Added newlib interface file syscalls.c under ./os/various for use with + the newest YAGARTO releases. The file provides bindings between the C + runtime and the core memory manager. +- CHANGE: Because the changes in the allocators some API prototypes changed: + chHeapAlloc(), chHeapStatus(), chThdCreateFromHeap(). +- CHANGE: Because the changes in the allocators some configuration options + changed and some were removed, see the new template chconf.h file. +- CHANGE: renamed ./demos/ARM7-AT91SAM7X-WEB-GCC in ARM7-AT91SAM7X-UIP-GCC. +- FIX: Added the most restrictive GCC warning option to the makefiles (-Wextra) + and fixed some warnings in the code, mostly unused function parameters. + +*** 1.3.2 *** +- FIX: Fixed GCC 4.4.x aliasing warnings (bug 2846336)(backported in stable + branch). +- FIX: Modified linker scripts for GCC 4.4.x (bug 2846302)(backported in stable + branch). +- FIX: Fixed the CH_OPTIMIZE_SPEED option in the CM3 port (bug 2846278) + (backported in stable branch). +- FIX: Fixed GCC 4.4.x related problems in CM3 port (bug 2846162)(backported + in stable branch). +- FIX: Fixed LPC214x UART problem (bug 2841088)(backported in stable branch). +- NEW: Improved the Cortex-M3 preemption code, now less interrupt-related + jitter is generated and all benchmarks scores improved a bit. +- NEW: Added new APIs chSchDoYieldS() and chThdYield(). +- MEW: Added new benchmark about RAM footprint. +- MEW: Added new benchmark about round robin rescheduling. +- NEW: Reorganized and rationalized the distribution tree and the + documentation. +- NEW: Enhanced serial driver. The driver now supports speed change at runtime + and low power stop mode. +- NEW: Serial driver removed from the kernel and added to the I/O subsystems + together with PAL. Note that the related API names changed their prefix from + chFDDxxx to sdxxx because of this. +- NEW: Added standard CMSIS 1.2.0 support to the Cortex-M3 port. The kernel + does not use it (the OS uses its own optimized code) but the functionality + is available to the applications. The CMSIS files were patched in order + to correct some warnings. +- NEW: Updated the STM32 port to use the newest ST firmware library files + (version 3.1.0). Note that now the ST drivers are included in the STM32 + demo directory. +- NEW: Improved makefiles and makefile fragments, now the paths are not fixed, + the fragments can be included also from projects outside the ChibiOS/RT files + structure by simply defining the variable ${CHIBIOS}. +- CHANGE: Removed the CH_USE_SERIAL_FULLDUPLEX configuration option because + the serial driver is no more part of the kernel. +- CHANGE: Reorganized the PAL and Serial identifiers now IOPORT1..N and + SD1..N rather than IOPORT_A..Z and COM1..N, some of the old names were + conflicting with some AVR libraries. + +*** 1.3.1 *** +- FIX: Removed mention of an obsolete option from the documentation (bug + 2799507). +- NEW: Abstract digital I/O ports driver (PAL), this driver defines a common + interface for digital I/O operations, this should help to create more + portable applications and, in general, make easier to work with ChibiOS/RT + on multiple architectures. +- NEW: Port drivers for STM32, LPC214x, AT91SAM7X and MSP430, cleaned up the + initialization code in board.c. All the demos now use PAL for I/O. AVR is + not supported because its "sparse" registers layout, it would not be + efficient enough for my taste. +- Modified the STM32 demo to use the bit definitions in the ST header file, + removed the bit definitions in board.h and stm32_serial.h. +- Documentation section reorganization and fixes. +- Changed the STM32 demo stack sizes, it was incorrectly adjusted in version + 1.3.0 but it did not create problems (not a bug). + +*** 1.3.0 *** +- FIX: Fixed regression in MinGW demo (bug 2745153)(backported in stable + branch). +- FIX: Fixed problem with the timeout constant TIME_IMMEDIATE, added a + specific test in the test suite (bug 2755170)(backported in stable branch). +- FIX: Fixed a problem in semaphores test case #2 (bug 2755195)(backported + in stable branch). +- FIX: Removed unused list functions (bug 2755230)(backported in stable + branch). +- FIX: Added license notice to several files (bug 2772160)(backported in + stable branch). +- FIX: Found new instances of the obsolete function chSysGetTime() in the + C++ wrapper and in the WEB demo (bug 2772237)(backported in stable branch). +- FIX: Fixed macro in test.h (bug 2781176)(backported in stable branch). +- FIX: Fixed sequence assertion in test.c (bug 2789377)(backported in stable + branch). +- FIX: Fixed test_cpu_pulse() incorrect behavior (bug 2789383)(backported in + stable branch). +- FIX: Fixed missing volatile modifier for p_time field in Thread structure + (bug 2789501)(backported in stable branch). +- FIX: Fixed C99-style variable declarations (bug 2792919)(backported in + stable branch). +- FIX: Fixed instance of obsolete CH_USE_TERMINATE option in the C++ wrapper + (bug 2796065)(backported in stable branch). +- FIX: Insufficient stack allocated to the C++ LPC2148 demo (bug 2796069) + (backported in stable branch). +- FIX: Fixed errors in events test case (bug 2796081)(backported in stable + branch). +- NEW: Abstract I/O Channels mechanism introduced. This mechanism allows to + access I/O resources through a standard interface and hides implementation + details. The existing serial drivers were modified to offer a standard + channel interface to the applications (the old APIs are retained as macros). +- NEW: The I/O queues code was improved, now there are 2 separate structures: + InputQueue and OutputQueue. There are some changes in the queue APIs + in order to make them more symmetrical and functional. Improved the queues + documentation. Some of the changes were needed in order to support the new + channels mechanism as a backend for queued serial drivers. +- NEW: Static initializers macros introduced for most kernel objects. The + static initializers allow to not have to chXXXInit() any object and save some + code space. The initialization functions are retained in order to allow + initialization of dynamic objects and re-initializations. +- NEW: Added more test cases in order to improve the test suite code coverage + (it was 74% in version 1.2.0, it is now close to 100%). +- NEW: Added test cases for the improved queues and serial drivers. +- NEW: Added a code coverage analysis application under ./tests/coverage. +- NEW: Added the test suite documentation to the general documentation. +- NEW: Added a new "naked" context switch benchmark that better defines the + real context switch time, previous benchmarks introduced too much overhead + to the measurement. The STM32 performs the context switch in under 1.48uS. +- NEW: Improved priority inheritance test cases. +- NEW: Added architecture name strings to the port code. +- NEW: Linux x86 simulator demo added. It is still work in progress. +- CHANGE: Removed the half duplex queues and half duplex serial drivers because + it was never extensively tested. The code is still available but not as part + of the kernel. +- CHANGE: Removed the chMsgSendWithEvent() function. It is rarely used and + the functionality can be re-created with a compound atomic operation. Also + removed the CH_USE_MESSAGES_EVENT configuration option. +- CHANGE: Modified the test suite assertions in order to save RAM on the AVR + targets. The test suite now uses much less string space. +- CHANGE: Removed the CH_USE_SERIAL_HALFDUPLEX, CH_USE_QUEUES_TIMEOUT, + CH_USE_QUEUES_HALFDUPLEX, CH_USE_SEMAPHORES_TIMEOUT configuration options. +- CHANGE: Made CH_DBG_THREADS_PROFILING default to TRUE in all demos because + the changes to the function test_cpu_pulse(). +- CHANGE: Increased main stack size to 1KiB for all the ARMx demos, 2KiB for + the C++ LPC2148 demo. This should make things easier for unexperienced + users. + +*** 1.2.0 *** +- Added license exception text to the 1.2.0 branch. +- FIX: Fixed serious AVR regression (bug 2731578). +- FIX: Fixed build failure when CH_USE_MUTEXES=FALSE (bug 2730706). +- FIX: Removed reference to an obsolete function (bug 2731661). +- Full test cycle and test reports updated. +- Small fixes to the documentation. + +*** 1.1.3unstable *** +- FIX: Fixed makefile in STM32 demo, this bug was reported fixed in + version 1.1.2 but it was still there (bug 2686451). +- FIX: Fixed makefile in MSP430 demo (bug 2700690). +- FIX: Fixed thumb mode build error in AT91SAM7X demos (bug 2700695). + +*** 1.1.2unstable *** +- FIX: Fixed priority inheritance problem with condvars (bug 2674756) and + added a specific test case to the test suite (backported in stable branch). +- FIX: Fixed a problem in time ranges (bug 2680425)(backported in stable + branch). +- FIX: Build error with option CH_DBG_FILL_THREADS (bug 2683965). +- FIX: Fixed a wrong parameter check in chVTSetI() and chThdSleep() + (bug 2679155). +- FIX: Build error with options CH_USE_NESTED_LOCKS && !CH_OPTIMIZE_SPEED + (bug 2678928). +- FIX: Removed unused chSysPuts() macro (bug 2672678). +- FIX: Renamed function chSysInTimeWindow() as chTimeIsWithin() and renamed + the macro chSysGetTime() in chTimeNow(), the old names are still recognized + but marked as deprecated (fixes the bug 2678953 but goes a bit further by + introducing a new API category "Time"). +- FIX: Fixed makefile problems in the AT91SAM7X256 and STM32 demos (bugs + 2686347 and 2686451). +- FIX: Fixed AT91SAM7X256 EMAC driver (bug 2686349). +- FIX: Fixed small some errors in the documentation (bug 2692510). +- OPT: Small optimization to the Cortex-M3 thread startup code, improved thread + related performance scores and smaller code. +- OPT: Alternative, non-inlined and more compact, implementations for + port_lock() and port_unlock() in the Cortex-M3 port when CH_OPTIMIZE_SPEED + is FALSE. +- OPT: Improved ready list and priority ordered lists code, some space saved, + better context switch performance. +- Modified the test thread function to return the global test result flag. +- Removed testcond.c|h and moved the test cases into testmtx.c. Mutexes and + condvars have to be tested together. +- Added architecture diagram to the documentation. +- Removed from the documentation some references to long gone functions... + +*** 1.1.1unstable *** +- FIX: Fixed a problem into the STACK_ALIGN() macro (backported in stable + branch). +- FIX: Fixed a problem with a wrong declaration of the PLL structure in the + file lpc214x.h (backported in stable branch). +- FIX: Fixed build problem with the C++ demo (bug 2687489). +- FIX: Removed EMAC driver from the AT91SAM7X256 demo makefile (bug 2686347). +- FIX: Removed C++ wrapper from the STM32 demo makefile (bug 2686451). +- FIX: Fixed a problem with some event APIs not showing in the documentation + (backported in stable branch). +- FIX: Fixed wrong assertions in chThdWait() and chHeapFree() (backported in + stable branch). +- FIX: Fixed @file tag in sam7x_serial.c (bug 2788573) (backported in stable + branch). +- FIX: Fixed a small problem in the chcore.c template file. +- NEW: Mailboxes (asynchronous messages) subsystem and test cases added. +- NEW: Most APIs with a timeout specification now accept the constant + TIME_IMMEDIATE (-1) that triggers an immediate timeout when trying to enter + a sleep state. +- NEW: Mode flexible debug configuration options, removed the old CH_USE_DEBUG + and CH_USE_TRACE. Replaced with CH_DBG_ENABLE_CHECKS, SCH_DBG_ENABLE_ASSERTS, + CH_DBG_ENABLE_TRACE and CH_DBG_FILL_THREADS. +- NEW: Added a debug option CH_DBG_THREADS_PROFILING for threads profiling. + A field into the Thread structure counts the consumed time. The information + is not used into the kernel, it is meant for debugging. +- NEW: Added a debug option CH_DBG_ENABLE_STACK_CHECK for stack overflow + checking. The check is not performed in the kernel but in the port code. + Currently only the ARM7 and ARMCM3 ports implements it. +- NEW: Unified makefiles for ARM7, ARMCM3 MSP430 projects, the new makefiles + share a common part making them easier to maintain. Also reorganized the + demo-specific part of the makefile, now it is easier to configure and the + option can be overridden from outside. +- CHANGE: Changed the chSemFastWaitS() macro in chSemFastWaitI() and + chSemGetCounter() in chSemGetCounterI(). +- CHANGE: Removed the port_puts() function from the port templates. It was not + implemented on all ports. +- Improvements to the test suite, added a new level of indirection that allows + to make tests depend on the configuration options without have to put #ifs + into the test main module. New benchmarks about semaphores and mutexes. + +*** 1.1.0unstable *** +- FIX: Modified the default value for the STM32 HSI setup it was 1, it should + be 0x10 (backported in stable branch). +- FIX: Removed an obsolete constant (P_SUSPENDED) from thread.h (backported in + stable branch). +- FIX: Removed unused field mp_grow in the MemoryPool structure (backported in + stable branch). +- NEW: Added to the STM32 demo makefile an option to build ChibiOS/RT with the + full STM32 FWLib 2.03. **NOTE**, except for the makefile option, the + library is not used by the OS nor required (backported in stable branch). +- NEW: Better separation between the port code and the system APIs, now an + architecture-specific "driver" contains all the port related code. + Port functions/macros are no more directly exposed as APIs to the user code. +- NEW: Added a configuration option to enable nested system locks/unlocks. +- NEW: Improved the interrupt handlers related code. Now interrupts are + handled in a very similar way in every architecture. See the "Concepts" + section and the "Writing interrupt handlers under ChibiOS/RT" article in the + documentation. +- NEW: Added the chEvtSignal() and chEvtSignalI() APIs that allows direct + thread signaling, much more efficient that chEvtBroadcast() when the target + is a known single thread. +- NEW: Added a configuration option that enables the priority enqueuing on + semaphores. It is defaulted to off because usually semaphores are used for + I/O related tasks without hard realtime requirements. +- NEW: Now the all the options in chconf.h and the various driver headers + can be overridden externally, for example from within the Makefile. + The options are no mode a simple define but a define with an assigned + TRUE/FALSE value within an #ifndef block. +- NEW: Idle thread hook macro added to the configuration file. +- NEW: Changed the ARM7 and Cortex-M3 startup files, now the action when + the main() function returns can be overridden by redefining the symbol + MainExitHandler. +- OPT: Improved ARM7 thumb port code, thanks to some GCC tricks involving + registers usage now the kernel is much smaller, faster and most OS APIs + use less RAM in stack frames (note, this is an ARM7 thumb mode specific + optimization). +- CHANGE: Now the API chThdSetPriority() returns the old priority instead + of void. +- CHANGE: Modified the signature of the chMsgSendWithEvent() API, it now uses + a more efficient event signaling method. +- CHANGE: Removed the field p_tid from the Thread structure and the related + code, this improved the thread creation scores (~2%) and saves some RAM. + The trace buffer field cse_tid is now populated with a simple hash of the + thread pointer as thread identifier. +- CHANGE: Renamed the macros chSysIRQEnter() and chSysIRQExit() in + CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() in order to make very clear that + those are not functions but inlined code. Also introduced a new macro + CH_IRQ_HANDLER that should be used when declaring an interrupt handler. +- CHANGE: Renamed several internal initialization functions by removing the + "ch" prefix because could not be considered system APIs. +- Improved ARM7 and Cortex-M3 support, new configuration options. +- Introduced the concept of interrupt classes, see the documentation. +- Introduced the concept of system states, see the documentation. +- Huge improvements to the documentation. +- Articles and notes previously in the wiki now merged in the general + documentation and updated, the wiki entries are obsolete and will be removed. +- New application notes and articles added. +- Added kernel size metrics to the test reports. +- Removed the inclusion graph from the documentation because the little + info they add and the size of all the images. It is possible to configure + Doxygen to have them again (and more graph types). + +*** 1.0.0 *** +- License switch, added GPL exception, see exception.txt. +- Full test cycle and test reports updated. +- Renamed some occurrences of "Conditional Variable" in "Condition Variable" in + the documentation. +- FIX: Fixed some images in the documentation because problems when seen in + Internet Explorer. + +*** 1.0.0rc3 *** +- FIX: Fixed a nasty regression to the timeout unified code that affected + some APIs since version 0.5.3. See the bug tracker for more details. + Added a test case about this. +- FIX: Removed the API chThdSuspend() there was a conceptual flaw and I want + to think about the whole concept again before introducing something similar + in future. Anyway, it is possible to replicate the functionality using + chSchGoSleepS(). +- Fixed typos here and there. +- Updated the states diagram in the documentation. + +*** 1.0.0rc2 *** +- FIX: Removed unused variable "retaddr" from the Cortex-M3 port. +- FIX: The macro THD_WA_SIZE was defined wrongly in the file + ./src/templates/chcore.h. +- Fixed some errors in the documentation. + +*** 1.0.0rc1 *** +- NEW: Added new macros CH_KERNEL_VERSION set to "1.0.0rc1", CH_KERNEL_MAJOR + set to 1, CH_KERNEL_MINOR set to 0, CH_KERNEL_PATCH set to 0. + The macros will be updated to reflect the actual kernel version number. +- NEW: Made all the port-specific configuration settings externally + configurable, see the documentation. +- FIX: Disabled the configuration option CH_USE_MESSAGES_PRIORITY from the + MSP430 demo, the default for this option should be off. +- FIX: Fixed a bug that prevented the THREAD_EXT_FIELDS to be compiled into + the Thread structure. +- FIX: Removed some references to deprecated APIs from the test suite. +- FIX: Set the INT_REQUIRED_STACK configuration value for the ARM7 port to a + safer 0x10, it was previously 0 (correct but trimmed to specific compiler + settings). +- FIX: Set the INT_REQUIRED_STACK configuration value for the AVR port to a + safer 32. +- FIX: Fixed the MinGW demo in order to not use any deprecated construct. +- Removed deprecated threads APIs: chThdCreate() and chThdCreateFast(). +- Removed deprecated events APIs: chEvtWait(), chEvtWaitTimeout(), chEvtSend(), + chEvtSendI(), EventMask(). +- Removed deprecated configuration feature CH_USE_EXIT_EVENT and the related + API chThdGetExitEventSource(). The feature can be reimplemented in user code + as shown by the MinGW demo. +- Removed deprecated macros: WorkingArea(), UserStackSize(), StackAlign(). +- Added usage note into the readme of the MinGW demo. +- Added usage notes for programmers to the ARM7 port documentation about + interrupt handlers. +- Port-specific settings added to the documentation. +- Added source browser to the documentation. +- Fixes and improvements through the documentation. + +*** 0.8.3 *** +- NEW: Introduced new API chThdSleepS() as a macro, no real changes in the + kernel code. +- FIX: The MinGW simulated demo now works again after breaking in 0.8.2 + because the changes to the macro names. +- FIX: Adjusted the test suite stack sizes for the MinGW simulated demo, now + the demo passes all the tests. +- FIX: Added fflush(stdout) to the MinGW simulation code output in order to + make the Eclipse console work correctly. +- FIX: Renamed the MinGW demo main source from demo.c to main.c in order to + follow the pattern of all the other demos. +- FIX: Added debug switches to the MinGW simulated demo, not it is possible to + debug the demo (and the kernel) inside Eclipse without a physical board. +- Removed lots of old deprecated constructs from the MinGW simulated demo. + There are still some, the demo will need some rework before version 1.0.0. +- Updated the C++ wrapper with the latest APIs changes and fixed some bugs. +- Small fixes to the documentation. + +*** 0.8.2 *** +- FIX: Included the files that were missing from version 0.8.1 distribution. +- FIX: Duplicated sections in the documentation removed. +- FIX: Minor problem in Cortex-M3 and AVR ports when the kernel is compiled + using G++. +- NEW: Added chPoolAllocI() and chPoolFreeI() APIs in order to allow the use + of memory pools from interrupt handlers and timer callbacks. +- CHANGE: Simplified the code for chThdWait(), it is now both smaller and + faster. Added an important usage note to the documentation of this API. +- CHANGE: The macros WorkingArea(), UserStackSize() and StackAlign() are now + deprecated and will be removed in version 1.0.0. Use the new equivalents + WORKING_AREA(), THD_WA_SIZE() and STACK_ALIGN() instead. +- CHANGE: Renamed the default idle thread function from _IdleThread() to + _idle(). +- Added to the LPC2148 and STM32 load scripts the options "ALIGN(16) + SUBALIGN(16)" to the flash loading section in order to enforce the alignment + for both the code and read only data. This is done in order to obtain more + accurate timings from benchmarks, those families have 16 bytes + prefetch buffers and are very sensitive to alignment changes. + You can remove those options in order to save some flash space if accurate + response time is not on top of your priorities, it mainly depends on your + requirements. + +*** 0.8.1 *** +- FIX: Fixed a regression in version 0.8.0, the configuration switch + CH_USE_EVENTS_TIMEOUT was redefined as CH_USE_EVENT_TIMEOUT and this broke + the code using events timeouts (the LPC2148 C++ demo). + +*** 0.8.0 *** +- NEW: Added condvars mechanism on top of the mutexes subsystem. +- NEW: Improved events subsystems, now it is also possible to use it just as + "event flags" without have to use event handler callbacks. + Some new APIs were introduced: + * chEvtWaitOne() - Wait for a single event. + * chEvtWaitAny() - Wait with OR condition. + * chEvtWaitAll() - Wait with AND condition. + * chEvtDispatch() - Invokes the event handlers associated to a mask. + * chEvtPend() - Quickly self-pends some events. + * chEvtRegisterMask() - Registers a set of flags on a single source. + * EVENT_MASK() - Replaces the old EventMask() macro. + All the "wait"-type APIs have a timeout-capable variant. +- CHANGE: The old EventMask(), chEvtWait() and chEvtWaitTimeout() APIs are + now deprecated and will be removed in version 1.0.0. +- CHANGE: Modified chDbgAssert() to syntax check the condition even when the + CH_USE_DEBUG is disabled, it produces no code but allows to check the + optional code without have to compile twice. +- FIX: Fixed a warning generated by the chEvtIsListening() macro. +- Added new test cases to the test suite about condvars and the new events + APIs. +- Added a new benchmark to the test suite (timers set/reset performance). +- Renamed the macro fifo_init() to queue_init() because it is used to init + both FIFO queues and priority queues. +- Fixes and improvements to the documentation. +- Cleaned demo applications of old events code. + +*** 0.7.3 *** +- FIX: Fixed a bug in chThdSleepUntil(), this API is no more a macro now. +- NEW: New chThdSleepSeconds(), chThdSleepMilliseconds() and + chThdSleepMicroseconds() utility macros. +- CHANGE: Zero is no more a valid time specification for the chVTSetI() API. +- CHANGE: Removed the files chsleep.c and sleep.h. +- CHANGE: Renamed the files chdelta.c and delta.h to chvt.c and vt.h. All the + system time related functions and macros are now there. +- CHANGE: Renamed the structure DeltaList to VTList, it includes the system + time counter too now. +- CHANGE: Removed the CH_USE_SYSTEMTIME and CH_USE_VIRTUAL_TIMER configuration + options in order to make the chconf.h file simpler. The related subsystems + are almost always required and are now always included. +- Small optimization to the MSP430 serial driver. +- Improvements to the test code, now a failed assert terminates the test case. +- Added dependency informations handling to the MSP430 demo Makefile. +- Removed the performance spreadsheet (it was *very* old) and added a + directory containing the test reports ./docs/reports. Each report shows the + results from the latest test run on each target. +- Small fixes to the documentation. + +*** 0.7.2 *** +- NEW: Added a serial driver to the MSP430 port, the MSP430 port now has been + tested on hardware and passes the test suite. +- NEW: Added to the MSP demo program the option to run from the internal DCO + or from an external xtal. The default is the internal DCO. +- NEW: Added macros to convert from seconds, milliseconds and microseconds to + system ticks. This improves application code portability among different + ports. +- CHANGE: Modified the test suite to use the new time conversion macros. +- CHANGE: Modified the CM3 startup file in order to implement an early + initialization phase: hwinit0, the late initialization phase is now named + hwinit1. The demo now initializes the PLL before initializing the BSS and + DATA segments, this greatly optimizes the system start up time. +- NEW: Unified ARM7 startup file, it is shared by the LPC and SAM7 demo + projects. The new startup file implements early and late initialization + phases as described above for the CM3 startup file. + The architecture specific vector tables are now encapsulated into the + vectors.s files. +- Modified the STM32 demo makefile to use the latest YAGARTO toolchain as + default (arm-elf-gcc). +- Documentation improvements, added collaboration diagrams and call graphs. + Added a documentation-related readme under ./docs. + +*** 0.7.1 *** +- NEW: New chThdInit() and chThdCreateStatic() APIs now replace the old + chThdCreate() and chThdCreateFast() that are thus marked as deprecated. + The new APIs use one less parameter and are faster. +- NEW: New dynamic chThdCreateFromHeap() and chthdCreateFromMemoryPool() APIs. + The dynamic APIs are only included if the CH_USE_DYNAMIC option is specified + into the project configuration file. +- NEW: Added an THREAD_EXT_EXIT macro in chconf.h to add finalization code to + the chThdExit() API. +- CHANGE: chThdCreateFast() is now a macro that uses chThdCreateStatic(). +- CHANGE: chThdWait() now releases the memory allocated by + chThdCreateFromHeap() and chthdCreateFromMemoryPool(). Threads created + through the static APIs are not affected thus the behavior is backward + compatible. +- CHANGE: Modified the chThdResume() API to return the resumed thread pointer + instead of void. This allowed few optimization into the threads creation + code. +- CHANGE: The chThdGetExitEventSource() API and the CH_USE_EXIT_EVENT + configuration option and the are now deprecated. Use the THREAD_EXT_EXIT + finalization macro in order to implement a similar functionality if needed. +- FIX: The chThdCreate() had a regression in 0.7.0, the mode parameter was + ignored. +- FIX: Removed duplicated call to chHeapInit() into chSysInit(). +- FIX: Fixed a syntax error in chheap.c triggered by the CH_USE_DEBUG option. +- Added new test cases to the test suite for the new dynamic APIs. +- Documentation fixes. + +*** 0.7.0 *** +- NEW: Memory Heap Allocator functionality added. The allocator implements a + first-fit strategy but there is an option that allow it to wrap the compiler + provided malloc() that may implement a different strategy. The heap + allocator is thread-safe and can use both a mutex or a semaphore as + internal synchronization primitive. +- NEW: Memory Pools functionality added, this mechanism allows constant-time + allocation/freeing of constant-size objects. It can be used to dynamically + allocate kernel objects like Semaphores, Mutexes, Threads etc fully in real + time, of course it is also possible to manage application-defined objects. + The pool allocator is thread-safe. + It is worth remembering that the kernel is still entirely static, it does + not use the allocation services internally, it is up to the application + code to use the allocators in order to use dynamic system objects. + Both the allocators can be disabled and removed from the memory image. +- NEW: Added option macros in chconf.h to add custom fields and initialization + code to the Thread structure. +- FIX: Corrected the wrong definition of the chThdResumeI() macro. +- FIX: The API chSemWaitTimeout() was missing in the documentation. +- CHANGE: Modified the chMtxUnlock() and chMtxUnlockS() APIs to return the + pointer to the released mutex instead of void. +- CHANGE: Now the chThdResume() API asserts that the thread is in PRSUSPEND + state rather than test it. +- CHANGE: Removed the CH_USE_TERMINATE, CH_USE_SLEEP, CH_USE_SUSPEND and + CH_USE_RESUME configuration options in order to make the chconf.h file + simpler. The related functions are very small and almost always required. +- CHANGE: The P_MSGBYPRIO thread option has been removed, now the threads + always serve messages in priority order if the CH_USE_MESSAGES_PRIORITY + configuration option is active. +- Added new test cases to the test suite. + +*** 0.6.10 *** +- FIX: Fixed a case-sensitiveness error in lpc214x_ssp.c, it affected only + linux/unix users. +- FIX: Fixed a regression introduced in version 0.6.9, the queues benchmark + test case was missing from the tests list. +- NEW: Added an option to the ARM7 ports, by specifying -DREENTRANT_LOCKS in + the makefile options makes the chSysLock() and chSysUnlock() become + reentrant. The code becomes a bit larger and slower, use it only if your + application really needs to invoke system API under lock. +- NEW: Added an option to the ARM7 and CM3 makefiles to strip any unused code + and data from the binary file (the default is on). + +*** 0.6.9 *** +- NEW: Added an option to exclude the support for the round robin scheduling, + this can save some extra program space and makes the context switch a bit + faster if the feature is not required. Threads at the same priority level + are still supported when the feature is disabled but the scheduling among + them becomes cooperative. +- OPT: Improved reschedule time by reordering the sequence of operations, + now during enqueuing the ready list contains one less element. This change + also slightly improves the interrupt latency. +- OPT: Optimization to the chSemReset(), reversed the order of dequeuing. +- FIX: Fixed a bug in the chThdSetPriority() API. +- FIX: Modified the structure names into nvic.h in order to not make them + collide with external libraries. +- Added a benchmark to the test suit that measures the mass reschedule + performance. +- Added a test_terminate_threads() function to the test framework. +- Made the Cortex-M3 port preemption code more readable. +- Added a ENABLE_WFI_IDLE option to the chcore.h file in the Cortex-M3 port, + setting this option to 1 enables the kernel to enter a low power mode when + executing the idle thread. Be careful however, this option can be not + compatible with some JTAG probes, it is better to enable it only on final + builds and not when debugging. + +*** 0.6.8 *** +- FIX: Fixed a bug in the priority inheritance mechanism, the bug was only a + problems when the CH_USE_MESSAGES_PRIORITY was enabled, this option is + disabled by default in ChibiOS/RT so it should not affect any user. +- CHANGE: The function chEvtSend() and chEvtSendI() are now renamed in + chEvtBroadcast() and chEvtBroadcastI(), the old names are still available + but are deprecated. +- Made the default BASEPRI levels (CM3 port) configurable into chcore.h. +- Many improvements to the documentation. +- All the fixes and changes in this release were suggested/submitted by + Leon Woestenberg (thank you). + +*** 0.6.7 *** +- NEW: New chThdCreateFast() API, it is a simplified form of chThdCreate() + that allows even faster threads creation. The new API does not support + the "mode" and "arg" parameters (still available in the old API). +- OPT: Removed an unrequired initialization and made other small optimizations + to the chThdCreate(). +- OPT: Improvements to the test framework, now a virtual timer is used instead + of software loops into the benchmarks in order to have more stable results. +- New benchmark added to the test suite. +- Added the C++ wrapper entries to the documentation. +- Fixed the documentation entry for the chThdCreate() API. +- Removed redundant ifdefs from the ch.h header. + +*** 0.6.6 *** +- NEW: Improved test suite, now the suite is divided in modules and the code + is much easier to understand. The new framework simplifies the inclusion of + new test cases and makes possible to verify the exact sequence and the + timing of test events. +- NEW: New API chSysInTimeWindow() that checks if the current system time is + within the specified time window. +- FIX: Mutex test #1 in the test suite corrected, it failed to... fail. +- FIX: Fixed a problem in the STM32 port USART1 driver. +- FIX: Fixed a problem in the MMC/SD driver in the LPC2148 demo. +- Added the definitions for packed structures to the chtypes.h files. +- Improvements to the makefiles, now each source group has its own .mk include + file. Now it is no more required to rewrite everything in each makefile. + +*** 0.6.5 *** +- NEW: Web server demo for the AT91SAM7X256, the demo integrates the uIP + stack and its demo applications. +- NEW: EMAC driver added to the AT91SAM7X port. +- FIX: Small fix to the ARM7 startup files. It used a short jump in the reset + vector and that could fail in some memory configurations. +- Documentation improvements. + +*** 0.6.4 *** +- NEW: MSP430 port, the port code compiles correctly but it is not tested yet. + The port requires the MSPGCC toolchain. +- NEW: Added a CH_ARCHITECTURE_xxx define to the various chcore.h files, it + allows to write port-dependent code. +- NEW: Added to the documentation the technical notes about the currently + supported ports. +- FIX: In the ARM7 and ARMCM3 ports chanced the bool_t base type from int8_t + to int32_t, this produces a bit faster and smaller code. + It is nowhere required the bool_t type to be one byte sized. +- FIX: Small fixes to the template files, there were some leftovers of the old + type names. +- FIX: Modified the ARM demos makefiles in order to make them more compatible + with GCC 4.3.0, it seems the new GCC assumes -mthumb-interworking and + -mabi=apcs by default, at least the builds I tested did so, now the makefiles + explicitly assert -mno-thumb-interworking and -mabi=apcs-gnu in order to + produce better code. +- Added an Ethernet driver for AT91SAM7X EMAC, not complete yet, it will be + required by a uIP web server demo under ChibiOS/RT coming in some next + release. + +*** 0.6.3 *** +- NEW: ARM Cortex-M3 port completed. The demo program targets the STM32F103 + chip from ST Microelectronics on an Olimex STM32-P103 board. +- FIX: Fixed a minor error in ./ports/ARM7-LPC214x/vic.h, it should not affect + anything. +- FIX: Minor fix: in chThdCreate() a working area size equal to + UserStackSize(0) was asserted as an error when in debug mode. It is now + allowed. +- FIX: Increased the stack size for the threads in the test suite to 128 bytes + because THUMB/THUMB2 modes seem to use a lot more stack than ARM mode. + +*** 0.6.2 *** +- NEW: Added C++ wrapper around the ChibiOS/RT core APIs, now it is possible + to use the OS in a fully object oriented application. The wrapper offers + classes that encapsulate threads, semaphores, mutexes, timers etc. Normal C + APIs are still accessible from C++ code as usual. +- NEW: Added a new LPC2148 demo using the new C++ wrapper, it is a good + example of C++ used for an embedded application. The demo does not use RTTI + nor standard libraries so the resulting code is very compact. +- Enhanced the chSemSignalWait() API to return the wakeup message just like + the other "Wait" semaphore functions do. +- Fixed a minor problem in the ARM7 port, the extctx structure definition was + missing one field, the effect was to allocate stacks 4 bytes shorter than + the declared size. +- Fixed a compile time error into the chThdSleepUntil() macro. +- Fixes in various headers to make some macros compatible with both C and C++. +- Fixed a regression in the LPC214x minimal demo that broke interrupt + handling. +- Some fixes to the doxygen documentation. +- More work done on the ARM-CM3 port but it is still not complete. + +*** 0.6.1 *** +- Removed some redundant checks from the scheduler code: improved threads + flyback time, reduced interrupts service time. +- Nice scheduler speed improvement obtained by removing the 2nd parameter to + the chSchReadyI() API and manually assigning the message value only where + is really needed (very few points in the code). +- More space savings and speed improvements obtained by removing the + -fno-strict-aliasing option from the makefiles, now the kernel compiles + without any warning even without this option. +- Removed the -falign-functions=16 option from the AT91SAM7X demo makefiles, + the Atmel chip does not require it, the option is still present on the + LPC21xx demos. This saves significant program space. +- Started work on ARM Cortex-M3 architecture. The target chip is the STM32F103 + on a Olimex STM32-P103 board. +- Added a threads state diagram to the documentation. +- Various fixes to the doxygen documentation. + +*** 0.6.0 *** +- Code refactory, all the old sized-integer definitions like LONG32, UWORD16 + etc are now replaced by the proper definitions provided by the compiler + into stdint.h. +- Code refactory, the previous system types style using a t_ in front of the + name has been replaced with the standard trailing _t. The system now uses + the size_t type defined into stddef.h. Some type names were modified in + order to not match commonly used type names. +- The above changes have an impact on some API prototypes but we can't help + it, the changes were required because the type names were a concern for + some users. +- Implemented a serial driver in the AVR port. +- Implemented a simple HD44780 LCD driver into the AVRmega128 demo. +- Reworked the AVR AT90CAN128 port to share the common AVR code. +- Modified the test suite to be compatible with 8 bit micros. +- MSVC demo dropped, it is still possible to use the MinGW demo as simulator + in Win32. +- Fixed a minor error in sam7x_serial.h and lpc214x_serial.h. +- The kernel is *unchanged* compared to version 0.5.3 except for the type + names but the change is important enough to make this a recommended update. + +*** 0.5.5 *** +- Added an AVRmega128 port. The previous AT90CANx port is still present but + it will be redone after the AVRmega128 port is complete because it will + share most of it. The demo is very simple, it will be expanded in next + releases. +- Reorganized the code of the two ARM7 ports, now all the common ARM7 code + is in ./ports/ARM7. This will make maintenance and new ARM7 ports much much + easier. +- Simplified the directory structure under ./ports. +- Added to the readme a section with our future plans/ideas. +- The kernel is *unchanged* compared to version 0.5.3, just the new port and + the new demo were added. + +*** 0.5.4 *** +- Port for Atmel AT91SAM7X256 introduced, the port should be usable also on + SAM7S and SAM7XC but no tests were performed. Other SAM7 processors should + also be usable with limited changes. + The demo currently just performs basic operations, will be enhanced in next + ChibiOS/RT releases, see the demo readme.txt file. +- Small fix to the thumb mode IRQ code on the LPC214x port, removed some extra + code. +- The kernel is *unchanged* compared to version 0.5.3, just the new port and + the new demo were added. + +*** 0.5.3 *** +- Removed the chMsgSendTimeout() API, it was conceptually flawed because, + after sending a message, the sender *has* to wait for the answer or + the next sender in queue would receive it instead (the messages server has + no way to know that the sender is gone because a timeout). + A workaround would make the messages subsystem much heavier and this is + not acceptable. +- Removed the test case for chMsgSendTimeout() from the test suite. +- Space saved by reorganizing the timeout code into a single scheduler + function chSchGoSleepTimeoutS(). +- Space optimizations in the semaphores code. +- The API chThdSleepUntil() become a macro saving some more code space. +- Because all the above changes the kernel code (ARM) is over 700 bytes + smaller. + +*** 0.5.2 *** +- Fixed a small problem in the main header file ch.h. +- Small reordering in the fields of the Thread structure in order to optimize + the space when messages are not used. + +*** 0.5.1 *** +- NEW: Priority enqueing for messages can be optionally enabled by specifying + the P_MSGBYPRIO option when creating a message server thread. + This change allows the implementation of a priority ceiling protocol into + message servers threads. Threads serving messages by priority and threads + serving messages in FIFO order can exist at the same time in the system. + This feature can be enabled or disabled by toggling the option + CH_USE_MESSAGES_PRIORITY into the chconf.h file (disabled by default, old + behavior). + Note: This option brings a small overhead when sending a message regardless + if in FIFO or priority order, if you don't need priority ordering for your + messages it is better to keep the feature disabled in chconf.h. +- Added to the ARM demos load scripts the capability to load code in RAM + instead flash, the function must be marked as: + __attribute__((section(".ramtext"))) + The option -mlong-calls should be specified in the makefile too or the + function declared with the "long-call" attribute. +- Fixed the MSVC demo project files. +- Fixed some syntax incompatibilities between GCC and MSVC into chmtx.c. + +*** 0.5.0 *** +- NEW: Mutexes, the new mechanism provides a complete implementation of the + "priority inheritance" algorithm as a tool for work around the priority + inversion problem. + The Mutexes are not meant to replace the Semaphores that still are the best + synchronization mechanism between interrupt handlers and high level + code, something that Mutexes cannot do. + Soon an article will be added to the wiki describing pro and cons of the + various mechanisms and the correct use cases. +- RT Semaphores subsystem removed, the Mutexes implements a better solution + for the same problem. +- Fixed a bug in the round robin scheduling mode, see the bug tracker for + details and a fix for previous versions. +- More performance improvements to the scheduler. The ready list insertion + sequence is now reversed, it is scanned starting from the highest priority + end. This has an important side effect into the chSchWakeupS() that makes + most of the ready list insertions happen in constant time (extraction is + done always in constant time). + The worst case is always proportional to the number of threads in the ready + list but the normal case is much more often constant than linear. See the + new benchmarks added to the test suite. +- Added mutexes test cases and new benchmarks to the test suite. +- Modified the test suite in order to have each test case to have the same + alignment enforced on functions. This is done to reduce MAM/Cache alignment + effects on the measurement. +- IRQ entry/exit code is now encapsulated into two new macros, see chcore.h + for details. +- All the asm code previously in chcore2.s is now inline asm code in chcore.c + (ARM port), chcore2.s removed. +- Moved all the board specific definitions/code into two new files: board.c + and board.h. Moved all the files no more board-dependent under ports/ + (ARM port). +- Improved the kernel performance in THUMB mode by better exploiting MAM + locality in some critical functions. The context switch benchmark shows + 5% improved speed. + +*** 0.4.5 *** +- Moved the serial IRQ handlers and VIC vectors initialization inside the + serial drivers. Now the serial-related code is all inside the driver. +- Moved all the other interrupt handlers from chcore2.s into chcore.c as + inline asm code. The interrupt code now is faster because one less call + level. +- Fixed a minor problem in chSysHalt() now it disables FIQ too and makes sure + to keep the processor in the state it had when it was halted. + Note: This is not a kernel bug but something specific with the ARM port, the + other ports are not affected. +- Fixed the macro chThdResumeI(), it had a regression. + +*** 0.4.4 *** +- Fixed a very important bug in the preemption ARM code, important enough to + make this update *mandatory*. + Note: This is not a kernel bug but something specific with the ARM port, the + other ports are not affected. +- Fixed a nasty bug in the pure THUMB mode threads trampoline code (chcore2.s, + threadstart), it failed on THUMB threads returning with a "bx" instruction. + The bug did not affect ARM mode or THUMB with interworking mode. + Note: This is not a kernel bug but something specific with the ARM port, the + other ports are not affected. +- Fixed a bug in chIQGetTimeout(), interrupts were not re-enabled when exiting + the function because a timeout. The problem affected that API only. +- Fixed a potential problem in chSysInit(), it should not affect any past + application. +- Added a chDbgAssert() API to the debug subsystem. +- Cleaned up the kernel source code using chDbgAssert() instead of a lot of + "#ifdef CH_USE_DEBUG", it is much more readable now. +- Now the threads working area is filled with a 0x55 when in debug mode, this + will make easier to track stack usage using a JTAG probe. +- Added an I/O Queues benchmark to the test suite. +- Removed the chSchTimerHandlerI() routine from chschd.c and moved it into + chinit.c renaming it chSysTimerHandlerI() because it is not part of the + scheduler. + +*** 0.4.3 *** +- Size optimization in the events code, now the chEvtWait() reuses the + chEvtWaitTimeout() code if it is enabled. +- Size optimization in the semaphores code, now the chSemWaitTimeout() just + invokes the chSemWaitTimeoutS() inside its system mutex zone. Same thing + done with chSemWait() and chSemWaitS(). +- Size optimization in the queues code. +- Modified the return type of chSemWait() and chSemWaitS() from void to t_msg, + this allows to understand if the semaphore was signaled or reset without + have to access the Thread structure. +- Added a threads create/exit/wait benchmark to the test suite, the system + is capable of 81712 threads started/terminated per second on the reference + LPC2148 board. The figure is inclusive of two context switch operations + for each thread. +- Minor improvement in the LPC214x serial driver, unneeded events were + generated in some rare cases. +- Fixed a chSysInit() documentation error. +- Fixed a chEvtWaitTimeout() documentation error. +- Added a new debug switch: CH_USE_TRACE, previously the trace functionality + was associated to the CH_USE_DEBUG switch. + +*** 0.4.2 *** +- Added a minimal ARM7-LPC demo, you can use this one as template in order to + create your application. It is easier to add subsystems back to the small + demo than remove stuff from the large one. +- Introduced support for "pure" THUMB mode, it is activated when all the + source files are compiled in THUMB mode, the option -mthumb-interworking is + not used in this scenario and this greatly improves both code size and + speed. + It is recommended to either use ARM mode or THUMB mode and not mix them + unless you know exactly what you are doing. Mixing modes is still supported + anyway. +- More optimizations in the scheduler, updated the performance spreadsheet. +- Fixed a problem with the thread working area declarations, the alignment to + 4 bytes boundary was not enforced. Now it is defined a new macro + WorkingArea(name, length) that takes care of both the allocation and the + alignment. + Example: + static WorkingArea(waThread1, 32); + It is expanded as: + ULONG32 waThread1[UserStackSpace(32) >> 2]; + Now the demos use the new declaration style. +- Fixed a small problem in sleep functions introduced in 0.4.1. + +*** 0.4.1 *** +- Modified the initialization code in order to have a dedicated idle thread in + the system, now the main() function behaves like a normal thread after + executing chSysInit() and can use all the ChibiOS/RT APIs (it was required + to run the idle loop in previous versions). + Now it is also possible to use ChibiOS/RT with a single main() thread and + just use it for the I/O capabilities, Virtual Timers and events. Now you + don't have to use multiple threads if you don't really need to. +- Added a spreadsheet in the documentation that describes the advantages + and disadvantages of the various optimization options (both GCC options and + ChibiOS/RT options), very interesting read IMO. +- The GCC option -falign-functions=16 is now default in the Makefile, it is + required because of the MAM unit into the LPC chips, without this option + the code performance is less predictable and can change of some % points + depending on how the code is aligned in the flash memory, unpredictability + is bad for a RTOS. This option however increases the code size slightly + because of the alignment gaps. +- Fine tuning in the scheduler code for improved performance, deeper + inlining and other small changes, about 5% better scheduler performance. +- Increased the default system-mode stack size from 128 to 256 bytes because + some optimizations and the THUMB mode seem to eat more stack space. +- Included a Makefile in the LPC2148 demo that builds in THUMB mode. +- Const-ified a parameter in the chEvtWait() and chEvtWaitTimeout() APIs. +- Removed the CPU register clearing on thread start, it was not really useful, + it is better to maximize performance instead. +- Cleaned up the ARM port code. Now it is easier to understand. +- Cleaned up the LPC2148 demo in main.c, it is now well documented and + explains everything, I assumed too much stuff to be "obvious". + +*** 0.4.0 *** +- NEW, added a benchmark functionality to the test suite. The benchmark + measures the kernel throughput as messages per second and context switches + per second. The benchmark will be useful for fine tuning the compiler + options and the kernel itself. +- NEW, implemented a debug subsystem, it supports debug messages and a context + switch circular trace buffer. The debug code can be enabled/disabled by + using the CH_USE_DEBUG in chconf.h. + The trace buffer is meant to be fetched and decoded by an external tool + (coming soon, it can be accessed using JTAG in the meanwhile). +- Added new API chThdGetPriority() as a macro. +- Implemented panic messages when CH_USE_DEBUG is enabled. +- Added a thread identifier field to the Thread structure, it is used only + for debug. +- Global variable stime modified as volatile. +- API chSysGetTime() reimplemented as a macro. +- Fixed a regression with the CH_CURRP_REGISTER_CACHE option. +- Fixed a problem in the LPC2148 interrupt handling code, a spurious + interrupts fix recommended on the NXP data sheet proved to be a very bad + idea and not about real spurious interrupts also... +- Fixed an harmless warning message in buzzer.c. + +*** 0.3.6 *** +- Added SSP (SPI1) and ext.interrupts definitions to the lpc214x.h file. +- Added SSP driver for the LPC2148. +- Added experimental MMC/SD block driver to the LPC2148 demo in order to + support file systems. The driver features also events generation on card + insert/remove, hot plugging supported. +- Added missing chThdSuspend() declaration in threads.h. + +*** 0.3.5 *** +- Space optimization in events code. +- Changed the behavior of chEvtWaitTimeout() when the timeout parameter is + set to zero, now it is consistent with all the other syscalls that have a + timeout option. +- Reorganized all the kernel inline definitions into a single file (inline.h). +- Fixed a minor problem in the interrupt initialization code for the LPC214x + demo, regrouped the VIC-specific code into vic.c/vic.h. +- Fixed a bug into the LPC2148 serial driver (limited to the serial port 2). +- Implemented HW transmit FIFO preloading in the LPC2148 serial driver in + order to minimize the number of interrupts generated, it is possible to + disable the feature and return to the old code which is a bit smaller, see + the configuration parameters in ./ARM7-LPC214x/GCC/lpc214x_serial.h. +- Some more work done on the AVR port, it is almost complete but not tested + yet because my JTAG probe broke... + +*** 0.3.4 *** +- Fixed a problem in chVTSetI(). +- New API, chVTIsArmedI(), it is a macro in delta.h. +- New API, chThdResumeI(), it is a macro in threads.h. This function is just + an alias for chSchReadyI() but makes the code more readable. +- New API, chThdSuspend(). New switch CH_USE_SUSPEND added to chconf.h. + +*** 0.3.3 *** +- Modified the chVTSetI(), now for the "time" parameter can have value zero + with meaning "infinite". This allows all the APIs with timeout parameters + to be invoked with no timeout. +- Fixes in the documentation. +- Renamed some APIs in the "Sch" group to have an S suffix instead of I. + +*** 0.3.2 *** +- Modified the chSysInit() to give the idle thread absolute priority, the + priority is then lowered to the minimum value into the chSysPause(). This + is done in order to ensure that the initializations performed into the + main() procedure are finished before any thread starts. +- Added chThdSetPriority() new API. +- Added a generic events generator timer module to the library code. +- Modified the ARM7-LPC214x-GCC demo to show the use of the event timer. +- Added the "#ifdef __cplusplus" stuff to the header files. +- Removed an obsolete definition in ./src/templates/chtypes.h. + +*** 0.3.1 *** +- Test program added to the demos. Telnet the MinGW and MSVS demos and type + "test" at the "ch>" prompt. On the LPC214x demo the test is activated by + pressing both the board buttons. The test performs tests on the ChibiOS/RT + functionalities. + The test code is also a good example of APIs usage and ChibiOS/RT behavior. +- Fixed bug in chEvtWaitTimeout(), the timeout code performed an useless + dequeue operation. +- Fixed a bug in chSemWaitTimeoutS() and chSemWaitTimeout(), the semaphore + counter was not atomically updated on a timeout condition. +- Fixed bug on RT semaphores, the priority queuing was broken. +- Fixed a bug in the MinGW demo, the chThdExit() code was not correctly + reported to the thread waiting in chThdWait(). +- Fixed a function declaration in semaphores.h. +- Lists code moved into chlists.c from various other places optimized and + reorganized. +- The list of the threads waiting in chThdWait() is now a single link list, + this saves some space. +- Cleaned the template files code, the files contained some obsolete + declarations. +- Code optimization in chSemWaitTimeoutS(), chSemWaitTimeout() and + chSemSignalWait(). +- Code optimization in chEvtSend(). +- Code optimization in chVTDoTickI(). +- Added a Semaphore pointer to the Thread structure, this allows to know on + which semaphore a thread is waiting on. It takes no space because it is + located in the union inside the Thread structure. This also allowed a minor + optimization inside chSemWaitTimeout() and chSemWaitTimeoutS(). +- Changed the priority type to unsigned in order to make it compatible + with a byte value, this is very important for 8 bits architectures. +- Modified the MinGW and MSVS demos to use 1ms ticks instead of 10ms as + before. + +*** 0.3.0 *** +- ChibiOS/RT goes beta. +- Diet for the threads code, some simple APIs become macros. +- Thread Local Storage implemented as a single API: chThdLS(). + The API simply returns a pointer into the thread working area, see the + documentation on the web site. +- Moved some documentation and images from the web site into the Doxygen + generated HTMLs. + +*** 0.2.1 *** +- Optimizations in the RT semaphores subsystem. The support for this + subsystem should still be considered experimental and further changes may + happen in future versions. +- Bug fix in the virtual timers handling code, now the timers can be re-armed + from within the callback code in order to create periodic virtual timers. +- Modified the t_prio type in the demos to be 32bits wide instead of 16bits, + this results in a better code in critical sections of the kernel. + +*** 0.2.0 *** +- Introduced support for ARM in thumb mode. +- Optimized context switching when thumb-interworking is not required, one + less instruction. +- Minor fixes to the ARM demo. + +*** 0.1.1 *** +- Some fixes into the documentation +- Renamed the makefiles to Makefile, upper case M. + +*** 0.1.0 *** +- First alpha release diff --git a/test/coverage/Makefile b/test/coverage/Makefile new file mode 100644 index 000000000..d19014202 --- /dev/null +++ b/test/coverage/Makefile @@ -0,0 +1,156 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = mingw32- +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp +COV = gcov + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSIMULATOR + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lws2_32 + +# Must be a directory in ${CHIBIOS}/os/hal/platforms +HOST_TYPE = Win32 + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/simulator/board.mk +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/$(HOST_TYPE)/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# List C source files here +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + $(BOARDSRC) \ + ${CHIBIOS}/os/hal/platforms/$(HOST_TYPE)/console.c \ + main.c + +# List ASM source files here +ASRC = + +# List all user directories here +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -ggdb -O0 -fomit-frame-pointer -fprofile-arcs -ftest-coverage + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch -lgcov $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +.PHONY: gcov +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(KERNSRC)) + -mv -f *.gcov ./gcov + +.PHONY: clean +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(SRC:.c=.gcno) + -rm -f $(SRC:.c=.gcda) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/test/coverage/chconf.h b/test/coverage/chconf.h new file mode 100644 index 000000000..8b0f88662 --- /dev/null +++ b/test/coverage/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/test/coverage/halconf.h b/test/coverage/halconf.h new file mode 100644 index 000000000..516a705a2 --- /dev/null +++ b/test/coverage/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/*#include "mcuconf.h"*/ + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/test/coverage/main.c b/test/coverage/main.c new file mode 100644 index 000000000..c4f257f0d --- /dev/null +++ b/test/coverage/main.c @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "console.h" + +/* + * Simulator main. + */ +int main(int argc, char *argv[]) { + msg_t result; + + (void)argc; + (void)argv; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + conInit(); + chSysInit(); + + result = TestThread(&CD1); + if (result) + exit(1); + else + exit(0); +} diff --git a/test/coverage/readme.txt b/test/coverage/readme.txt new file mode 100644 index 000000000..fc3595112 --- /dev/null +++ b/test/coverage/readme.txt @@ -0,0 +1,6 @@ +In order to compute the code coverage: + +- Build the test application: make +- Run the test suite: ch +- Compute the code coverage: make gcov +- Clear everything: make clean diff --git a/test/test.c b/test/test.c new file mode 100644 index 000000000..1de688a28 --- /dev/null +++ b/test/test.c @@ -0,0 +1,390 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file test.c + * @brief Tests support code. + * + * @addtogroup test + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "test.h" +#include "testthd.h" +#include "testsem.h" +#include "testmtx.h" +#include "testmsg.h" +#include "testmbox.h" +#include "testevt.h" +#include "testheap.h" +#include "testpools.h" +#include "testdyn.h" +#include "testqueues.h" +#include "testbmk.h" + +/* + * Array of all the test patterns. + */ +static ROMCONST struct testcase * ROMCONST *patterns[] = { + patternthd, + patternsem, + patternmtx, + patternmsg, + patternmbox, + patternevt, + patternheap, + patternpools, + patterndyn, + patternqueues, + patternbmk, + NULL +}; + +static bool_t local_fail, global_fail; +static unsigned failpoint; +static char tokens_buffer[MAX_TOKENS]; +static char *tokp; + +/* + * Static working areas, the following areas can be used for threads or + * used as temporary buffers. + */ +union test_buffers test; + +/* + * Pointers to the spawned threads. + */ +Thread *threads[MAX_THREADS]; + +/* + * Pointers to the working areas. + */ +void * ROMCONST wa[5] = {test.wa.T0, test.wa.T1, test.wa.T2, + test.wa.T3, test.wa.T4}; + +/* + * Console output. + */ +static BaseSequentialStream *chp; + +/** + * @brief Prints a decimal unsigned number. + * + * @param[in] n the number to be printed + */ +void test_printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(chp, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(chp, *--p); + } +} + +/** + * @brief Prints a line without final end-of-line. + * + * @param[in] msgp the message + */ +void test_print(const char *msgp) { + + while (*msgp) + chSequentialStreamPut(chp, *msgp++); +} + +/** + * @brief Prints a line. + * + * @param[in] msgp the message + */ +void test_println(const char *msgp) { + + test_print(msgp); + chSequentialStreamWrite(chp, (const uint8_t *)"\r\n", 2); +} + +/* + * Tokens. + */ +static void clear_tokens(void) { + + tokp = tokens_buffer; +} + +static void print_tokens(void) { + char *cp = tokens_buffer; + + while (cp < tokp) + chSequentialStreamPut(chp, *cp++); +} + +/** + * @brief Emits a token into the tokens buffer. + * + * @param[in] token the token as a char + */ +void test_emit_token(char token) { + + chSysLock(); + *tokp++ = token; + chSysUnlock(); +} + +/* + * Assertions. + */ +bool_t _test_fail(unsigned point) { + + local_fail = TRUE; + global_fail = TRUE; + failpoint = point; + return TRUE; +} + +bool_t _test_assert(unsigned point, bool_t condition) { + + if (!condition) + return _test_fail(point); + return FALSE; +} + +bool_t _test_assert_sequence(unsigned point, char *expected) { + char *cp = tokens_buffer; + while (cp < tokp) { + if (*cp++ != *expected++) + return _test_fail(point); + } + if (*expected) + return _test_fail(point); + clear_tokens(); + return FALSE; +} + +bool_t _test_assert_time_window(unsigned point, systime_t start, systime_t end) { + + return _test_assert(point, chTimeIsWithin(start, end)); +} + +/* + * Threads utils. + */ + +/** + * @brief Sets a termination request in all the test-spawned threads. + */ +void test_terminate_threads(void) { + int i; + + for (i = 0; i < MAX_THREADS; i++) + if (threads[i]) + chThdTerminate(threads[i]); +} + +/** + * @brief Waits for the completion of all the test-spawned threads. + */ +void test_wait_threads(void) { + int i; + + for (i = 0; i < MAX_THREADS; i++) + if (threads[i] != NULL) { + chThdWait(threads[i]); + threads[i] = NULL; + } +} + +#if CH_DBG_THREADS_PROFILING +/** + * @brief CPU pulse. + * @note The current implementation is not totally reliable. + * + * @param[in] duration CPU pulse duration in milliseconds + */ +void test_cpu_pulse(unsigned duration) { + systime_t start, end, now; + + start = chThdSelf()->p_time; + end = start + MS2ST(duration); + do { + now = chThdSelf()->p_time; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } + while (end > start ? (now >= start) && (now < end) : + (now >= start) || (now < end)); +} +#endif + +/** + * @brief Delays execution until next system time tick. + * + * @return The system time. + */ +systime_t test_wait_tick(void) { + + chThdSleep(1); + return chTimeNow(); +} + +/* + * Timer utils. + */ + +/** + * @brief Set to @p TRUE when the test timer reaches its deadline. + */ +bool_t test_timer_done; + +static VirtualTimer vt; +static void tmr(void *p) { + (void)p; + + test_timer_done = TRUE; +} + +/** + * @brief Starts the test timer. + * + * @param[in] ms time in milliseconds + */ +void test_start_timer(unsigned ms) { + + systime_t duration = MS2ST(ms); + test_timer_done = FALSE; + chVTSet(&vt, duration, tmr, NULL); +} + +/* + * Test suite execution. + */ +static void execute_test(const struct testcase *tcp) { + int i; + + /* Initialization */ + clear_tokens(); + local_fail = FALSE; + for (i = 0; i < MAX_THREADS; i++) + threads[i] = NULL; + + if (tcp->setup != NULL) + tcp->setup(); + tcp->execute(); + if (tcp->teardown != NULL) + tcp->teardown(); + + test_wait_threads(); +} + +static void print_line(void) { + unsigned i; + + for (i = 0; i < 76; i++) + chSequentialStreamPut(chp, '-'); + chSequentialStreamWrite(chp, (const uint8_t *)"\r\n", 2); +} + +/** + * @brief Test execution thread function. + * + * @param[in] p pointer to a @p BaseChannel object for test output + * @return A failure boolean value. + */ +msg_t TestThread(void *p) { + int i, j; + + chp = p; + test_println(""); + test_println("*** ChibiOS/RT test suite"); + test_println("***"); + test_print("*** Kernel: "); + test_println(CH_KERNEL_VERSION); + test_print("*** Compiled: "); + test_println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + test_print("*** Compiler: "); + test_println(CH_COMPILER_NAME); +#endif + test_print("*** Architecture: "); + test_println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + test_print("*** Core Variant: "); + test_println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + test_print("*** Port Info: "); + test_println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + test_print("*** Platform: "); + test_println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + test_print("*** Test Board: "); + test_println(BOARD_NAME); +#endif + test_println(""); + + global_fail = FALSE; + i = 0; + while (patterns[i]) { + j = 0; + while (patterns[i][j]) { + print_line(); + test_print("--- Test Case "); + test_printn(i + 1); + test_print("."); + test_printn(j + 1); + test_print(" ("); + test_print(patterns[i][j]->name); + test_println(")"); +#if DELAY_BETWEEN_TESTS > 0 + chThdSleepMilliseconds(DELAY_BETWEEN_TESTS); +#endif + execute_test(patterns[i][j]); + if (local_fail) { + test_print("--- Result: FAILURE (#"); + test_printn(failpoint); + test_print(" ["); + print_tokens(); + test_println("])"); + } + else + test_println("--- Result: SUCCESS"); + j++; + } + i++; + } + print_line(); + test_println(""); + test_print("Final result: "); + if (global_fail) + test_println("FAILURE"); + else + test_println("SUCCESS"); + + return (msg_t)global_fail; +} + +/** @} */ diff --git a/test/test.dox b/test/test.dox new file mode 100644 index 000000000..87c68320b --- /dev/null +++ b/test/test.dox @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @defgroup test Test Runtime + * @details Runtime code for the test suite execution, this code is not part + * of the OS and should not be included in user applications. + */ + +/** + * @page testsuite Testing Strategy + *

    Description

    + * Most of the ChibiOS/RT demos link a set of software modules (test suite) in + * order to verify the proper working of the kernel, the port and the demo + * itself. + * + *

    Strategy by Component

    + * The OS components are tested in various modes depending on their importance: + * - Kernel. The kernel code is subject to rigorous testing. The test + * suite aims to test all the kernel code and reach a code coverage + * as close to 100% as possible. In addition to the code coverage, the kernel + * code is tested for functionality and benchmarked for speed + * and size before each stable release. In addition to the code + * coverage and functional testing a batch compilation test is + * performed before each release, the kernel is compiled by alternatively + * enabling and disabling all the various configuration options, the + * kernel code is expected to compile without errors nor warnings and + * execute the test suite without failures (a specific simulator is used + * for this execution test, it is done automatically by a script because + * the entire sequence can take hours).
    + * All the tests results are included as reports in the OS distribution + * under ./docs/reports. + * - Ports. The port code is tested by executing the kernel test + * suite on the target hardware. A port is validated only if it passes all + * the tests. Speed and size benchmarks for all the supported architectures + * are performed, both size and speed regressions are monitored. + * - HAL. The HAL high level code and device drivers implementations + * are tested through specific test applications under ./testhal. + * - Various. The miscellaneous code is tested by use in the various + * demos. + * - External Code. Not tested, external libraries or components are + * used as-is or with minor patching where required, problems are usually + * reported upstream. + * . + *

    Kernel Test Suite

    + * The kernel test suite is divided in modules or test sequences. Each Test + * Module performs a series of tests on a specified kernel subsystem or + * subsystems and can report a failure/success status and/or a performance + * index as the test suite output.
    + * The test suite is usually activated in the demo applications by pressing a + * button on the target board, see the readme file into the various demos + * directories. The test suite output is usually sent through a serial port + * and can be examined by using a terminal emulator program. + * + *

    Kernel Test Modules

    + * + * - @subpage test_threads + * - @subpage test_dynamic + * - @subpage test_msg + * - @subpage test_sem + * - @subpage test_mtx + * - @subpage test_events + * - @subpage test_mbox + * - @subpage test_queues + * - @subpage test_heap + * - @subpage test_pools + * - @subpage test_benchmarks + * . + */ diff --git a/test/test.h b/test/test.h new file mode 100644 index 000000000..fbdfa27f0 --- /dev/null +++ b/test/test.h @@ -0,0 +1,173 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file test.h + * @brief Tests support header. + * + * @addtogroup test + * @{ + */ + +#ifndef _TEST_H_ +#define _TEST_H_ + +/** + * @brief Delay inserted between test cases. + */ +#if !defined(DELAY_BETWEEN_TESTS) || defined(__DOXYGEN__) +#define DELAY_BETWEEN_TESTS 200 +#endif + +/** + * @brief If @p TRUE then benchmarks are not included. + */ +#if !defined(TEST_NO_BENCHMARKS) || defined(__DOXYGEN__) +#define TEST_NO_BENCHMARKS FALSE +#endif + +#define MAX_THREADS 5 +#define MAX_TOKENS 16 + +#if defined(CH_ARCHITECTURE_AVR) || defined(CH_ARCHITECTURE_MSP430) +#define THREADS_STACK_SIZE 48 +#elif defined(CH_ARCHITECTURE_STM8) +#define THREADS_STACK_SIZE 64 +#elif defined(CH_ARCHITECTURE_SIMIA32) +#define THREADS_STACK_SIZE 512 +#else +#define THREADS_STACK_SIZE 128 +#endif +#define WA_SIZE THD_WA_SIZE(THREADS_STACK_SIZE) + +/** + * @brief Structure representing a test case. + */ +struct testcase { + const char *name; /**< @brief Test case name. */ + void (*setup)(void); /**< @brief Test case preparation function. */ + void (*teardown)(void); /**< @brief Test case clean up function. */ + void (*execute)(void); /**< @brief Test case execution function. */ +}; + +#ifndef __DOXYGEN__ +union test_buffers { + struct { + WORKING_AREA(T0, THREADS_STACK_SIZE); + WORKING_AREA(T1, THREADS_STACK_SIZE); + WORKING_AREA(T2, THREADS_STACK_SIZE); + WORKING_AREA(T3, THREADS_STACK_SIZE); + WORKING_AREA(T4, THREADS_STACK_SIZE); + } wa; + uint8_t buffer[WA_SIZE * 5]; +}; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + msg_t TestThread(void *p); + void test_printn(uint32_t n); + void test_print(const char *msgp); + void test_println(const char *msgp); + void test_emit_token(char token); + bool_t _test_fail(unsigned point); + bool_t _test_assert(unsigned point, bool_t condition); + bool_t _test_assert_sequence(unsigned point, char *expected); + bool_t _test_assert_time_window(unsigned point, systime_t start, systime_t end); + void test_terminate_threads(void); + void test_wait_threads(void); + systime_t test_wait_tick(void); + void test_start_timer(unsigned ms); +#if CH_DBG_THREADS_PROFILING + void test_cpu_pulse(unsigned duration); +#endif +#if defined(WIN32) + void ChkIntSources(void); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @brief Test failure enforcement. + */ +#define test_fail(point) { \ + _test_fail(point); \ + return; \ +} + +/** + * @brief Test assertion. + * + * @param[in] point numeric assertion identifier + * @param[in] condition a boolean expression that must be verified to be true + * @param[in] msg failure message + */ +#define test_assert(point, condition, msg) { \ + if (_test_assert(point, condition)) \ + return; \ +} + +/** + * @brief Test assertion with lock. + * + * @param[in] point numeric assertion identifier + * @param[in] condition a boolean expression that must be verified to be true + * @param[in] msg failure message + */ +#define test_assert_lock(point, condition, msg) { \ + chSysLock(); \ + if (_test_assert(point, condition)) { \ + chSysUnlock(); \ + return; \ + } \ + chSysUnlock(); \ +} + +/** + * @brief Test sequence assertion. + * + * @param[in] point numeric assertion identifier + * @param[in] expected string to be matched with the tokens buffer + */ +#define test_assert_sequence(point, expected) { \ + if (_test_assert_sequence(point, expected)) \ + return; \ +} + +/** + * @brief Test time window assertion. + * + * @param[in] point numeric assertion identifier + * @param[in] start initial time in the window (included) + * @param[in] end final time in the window (not included) + */ +#define test_assert_time_window(point, start, end) { \ + if (_test_assert_time_window(point, start, end)) \ + return; \ +} + +#if !defined(__DOXYGEN__) +extern Thread *threads[MAX_THREADS]; +extern union test_buffers test; +extern void * ROMCONST wa[]; +extern bool_t test_timer_done; +#endif + +#endif /* _TEST_H_ */ + +/** @} */ diff --git a/test/test.mk b/test/test.mk new file mode 100644 index 000000000..3f740288c --- /dev/null +++ b/test/test.mk @@ -0,0 +1,16 @@ +# List of all the ChibiOS/RT test files. +TESTSRC = ${CHIBIOS}/test/test.c \ + ${CHIBIOS}/test/testthd.c \ + ${CHIBIOS}/test/testsem.c \ + ${CHIBIOS}/test/testmtx.c \ + ${CHIBIOS}/test/testmsg.c \ + ${CHIBIOS}/test/testmbox.c \ + ${CHIBIOS}/test/testevt.c \ + ${CHIBIOS}/test/testheap.c \ + ${CHIBIOS}/test/testpools.c \ + ${CHIBIOS}/test/testdyn.c \ + ${CHIBIOS}/test/testqueues.c \ + ${CHIBIOS}/test/testbmk.c + +# Required include directories +TESTINC = ${CHIBIOS}/test diff --git a/test/testbmk.c b/test/testbmk.c new file mode 100644 index 000000000..5b46023d8 --- /dev/null +++ b/test/testbmk.c @@ -0,0 +1,710 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_benchmarks Kernel Benchmarks + * + * File: @ref testbmk.c + * + *

    Description

    + * This module implements a series of system benchmarks. The benchmarks are + * useful as a stress test and as a reference when comparing ChibiOS/RT + * with similar systems. + * + *

    Objective

    + * Objective of the test module is to provide a performance index for the + * most critical system subsystems. The performance numbers allow to + * discover performance regressions between successive ChibiOS/RT releases. + * + *

    Preconditions

    + * None. + * + *

    Test Cases

    + * - @subpage test_benchmarks_001 + * - @subpage test_benchmarks_002 + * - @subpage test_benchmarks_003 + * - @subpage test_benchmarks_004 + * - @subpage test_benchmarks_005 + * - @subpage test_benchmarks_006 + * - @subpage test_benchmarks_007 + * - @subpage test_benchmarks_008 + * - @subpage test_benchmarks_009 + * - @subpage test_benchmarks_010 + * - @subpage test_benchmarks_011 + * - @subpage test_benchmarks_012 + * - @subpage test_benchmarks_013 + * . + * @file testbmk.c Kernel Benchmarks + * @brief Kernel Benchmarks source file + * @file testbmk.h + * @brief Kernel Benchmarks header file + */ + +static Semaphore sem1; +#if CH_USE_MUTEXES || defined(__DOXYGEN__) +static Mutex mtx1; +#endif + +static msg_t thread1(void *p) { + Thread *tp; + msg_t msg; + + (void)p; + do { + tp = chMsgWait(); + msg = chMsgGet(tp); + chMsgRelease(tp, msg); + } while (msg); + return 0; +} + +#ifdef __GNUC__ +__attribute__((noinline)) +#endif +static unsigned int msg_loop_test(Thread *tp) { + + uint32_t n = 0; + test_wait_tick(); + test_start_timer(1000); + do { + (void)chMsgSend(tp, 1); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + (void)chMsgSend(tp, 0); + return n; +} + +/** + * @page test_benchmarks_001 Messages performance #1 + * + *

    Description

    + * A message server thread is created with a lower priority than the client + * thread, the messages throughput per second is measured and the result + * printed in the output log. + */ + +static void bmk1_execute(void) { + uint32_t n; + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread1, NULL); + n = msg_loop_test(threads[0]); + test_wait_threads(); + test_print("--- Score : "); + test_printn(n); + test_print(" msgs/S, "); + test_printn(n << 1); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk1 = { + "Benchmark, messages #1", + NULL, + NULL, + bmk1_execute +}; + +/** + * @page test_benchmarks_002 Messages performance #2 + * + *

    Description

    + * A message server thread is created with an higher priority than the client + * thread, the messages throughput per second is measured and the result + * printed in the output log. + */ + +static void bmk2_execute(void) { + uint32_t n; + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread1, NULL); + n = msg_loop_test(threads[0]); + test_wait_threads(); + test_print("--- Score : "); + test_printn(n); + test_print(" msgs/S, "); + test_printn(n << 1); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk2 = { + "Benchmark, messages #2", + NULL, + NULL, + bmk2_execute +}; + +static msg_t thread2(void *p) { + + return (msg_t)p; +} + +/** + * @page test_benchmarks_003 Messages performance #3 + * + *

    Description

    + * A message server thread is created with an higher priority than the client + * thread, four lower priority threads crowd the ready list, the messages + * throughput per second is measured while the ready list and the result + * printed in the output log. + */ + +static void bmk3_execute(void) { + uint32_t n; + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread1, NULL); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-2, thread2, NULL); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread2, NULL); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-4, thread2, NULL); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-5, thread2, NULL); + n = msg_loop_test(threads[0]); + test_wait_threads(); + test_print("--- Score : "); + test_printn(n); + test_print(" msgs/S, "); + test_printn(n << 1); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk3 = { + "Benchmark, messages #3", + NULL, + NULL, + bmk3_execute +}; + +/** + * @page test_benchmarks_004 Context Switch performance + * + *

    Description

    + * A thread is created that just performs a @p chSchGoSleepS() into a loop, + * the thread is awakened as fast is possible by the tester thread.
    + * The Context Switch performance is calculated by measuring the number of + * iterations after a second of continuous operations. + */ + +msg_t thread4(void *p) { + msg_t msg; + Thread *self = chThdSelf(); + + (void)p; + chSysLock(); + do { + chSchGoSleepS(THD_STATE_SUSPENDED); + msg = self->p_u.rdymsg; + } while (msg == RDY_OK); + chSysUnlock(); + return 0; +} + +static void bmk4_execute(void) { + Thread *tp; + uint32_t n; + + tp = threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread4, NULL); + n = 0; + test_wait_tick(); + test_start_timer(1000); + do { + chSysLock(); + chSchWakeupS(tp, RDY_OK); + chSchWakeupS(tp, RDY_OK); + chSchWakeupS(tp, RDY_OK); + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + n += 4; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + chSysLock(); + chSchWakeupS(tp, RDY_TIMEOUT); + chSysUnlock(); + + test_wait_threads(); + test_print("--- Score : "); + test_printn(n * 2); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk4 = { + "Benchmark, context switch", + NULL, + NULL, + bmk4_execute +}; + +/** + * @page test_benchmarks_005 Threads performance, full cycle + * + *

    Description

    + * Threads are continuously created and terminated into a loop. A full + * @p chThdCreateStatic() / @p chThdExit() / @p chThdWait() cycle is performed + * in each iteration.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void bmk5_execute(void) { + + uint32_t n = 0; + void *wap = wa[0]; + tprio_t prio = chThdGetPriority() - 1; + test_wait_tick(); + test_start_timer(1000); + do { + chThdWait(chThdCreateStatic(wap, WA_SIZE, prio, thread2, NULL)); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n); + test_println(" threads/S"); +} + +ROMCONST struct testcase testbmk5 = { + "Benchmark, threads, full cycle", + NULL, + NULL, + bmk5_execute +}; + +/** + * @page test_benchmarks_006 Threads performance, create/exit only + * + *

    Description

    + * Threads are continuously created and terminated into a loop. A partial + * @p chThdCreateStatic() / @p chThdExit() cycle is performed in each + * iteration, the @p chThdWait() is not necessary because the thread is + * created at an higher priority so there is no need to wait for it to + * terminate.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void bmk6_execute(void) { + + uint32_t n = 0; + void *wap = wa[0]; + tprio_t prio = chThdGetPriority() + 1; + test_wait_tick(); + test_start_timer(1000); + do { + chThdCreateStatic(wap, WA_SIZE, prio, thread2, NULL); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n); + test_println(" threads/S"); +} + +ROMCONST struct testcase testbmk6 = { + "Benchmark, threads, create only", + NULL, + NULL, + bmk6_execute +}; + +/** + * @page test_benchmarks_007 Mass reschedule performance + * + *

    Description

    + * Five threads are created and atomically rescheduled by resetting the + * semaphore where they are waiting on. The operation is performed into a + * continuous loop.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static msg_t thread3(void *p) { + + (void)p; + while (!chThdShouldTerminate()) + chSemWait(&sem1); + return 0; +} + +static void bmk7_setup(void) { + + chSemInit(&sem1, 0); +} + +static void bmk7_execute(void) { + uint32_t n; + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+5, thread3, NULL); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()+4, thread3, NULL); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()+3, thread3, NULL); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()+2, thread3, NULL); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()+1, thread3, NULL); + + n = 0; + test_wait_tick(); + test_start_timer(1000); + do { + chSemReset(&sem1, 0); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_terminate_threads(); + chSemReset(&sem1, 0); + test_wait_threads(); + + test_print("--- Score : "); + test_printn(n); + test_print(" reschedules/S, "); + test_printn(n * 6); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk7 = { + "Benchmark, mass reschedule, 5 threads", + bmk7_setup, + NULL, + bmk7_execute +}; + +/** + * @page test_benchmarks_008 I/O Round-Robin voluntary reschedule. + * + *

    Description

    + * Five threads are created at equal priority, each thread just increases a + * variable and yields.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static msg_t thread8(void *p) { + + do { + chThdYield(); + chThdYield(); + chThdYield(); + chThdYield(); + (*(uint32_t *)p) += 4; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while(!chThdShouldTerminate()); + return 0; +} + +static void bmk8_execute(void) { + uint32_t n; + + n = 0; + test_wait_tick(); + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); + + chThdSleepSeconds(1); + test_terminate_threads(); + test_wait_threads(); + + test_print("--- Score : "); + test_printn(n); + test_println(" ctxswc/S"); +} + +ROMCONST struct testcase testbmk8 = { + "Benchmark, round robin context switching", + NULL, + NULL, + bmk8_execute +}; + +/** + * @page test_benchmarks_009 I/O Queues throughput + * + *

    Description

    + * Four bytes are written and then read from an @p InputQueue into a continuous + * loop.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void bmk9_execute(void) { + uint32_t n; + static uint8_t ib[16]; + static InputQueue iq; + + chIQInit(&iq, ib, sizeof(ib), NULL, NULL); + n = 0; + test_wait_tick(); + test_start_timer(1000); + do { + chSysLock(); + chIQPutI(&iq, 0); + chIQPutI(&iq, 1); + chIQPutI(&iq, 2); + chIQPutI(&iq, 3); + chSysUnlock(); + (void)chIQGet(&iq); + (void)chIQGet(&iq); + (void)chIQGet(&iq); + (void)chIQGet(&iq); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n * 4); + test_println(" bytes/S"); +} + +ROMCONST struct testcase testbmk9 = { + "Benchmark, I/O Queues throughput", + NULL, + NULL, + bmk9_execute +}; + +/** + * @page test_benchmarks_010 Virtual Timers set/reset performance + * + *

    Description

    + * A virtual timer is set and immediately reset into a continuous loop.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void tmo(void *param) {(void)param;} + +static void bmk10_execute(void) { + static VirtualTimer vt1, vt2; + uint32_t n = 0; + + test_wait_tick(); + test_start_timer(1000); + do { + chSysLock(); + chVTSetI(&vt1, 1, tmo, NULL); + chVTSetI(&vt2, 10000, tmo, NULL); + chVTResetI(&vt1); + chVTResetI(&vt2); + chSysUnlock(); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n * 2); + test_println(" timers/S"); +} + +ROMCONST struct testcase testbmk10 = { + "Benchmark, virtual timers set/reset", + NULL, + NULL, + bmk10_execute +}; + +/** + * @page test_benchmarks_011 Semaphores wait/signal performance + * + *

    Description

    + * A counting semaphore is taken/released into a continuous loop, no Context + * Switch happens because the counter is always non negative.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void bmk11_setup(void) { + + chSemInit(&sem1, 1); +} + +static void bmk11_execute(void) { + uint32_t n = 0; + + test_wait_tick(); + test_start_timer(1000); + do { + chSemWait(&sem1); + chSemSignal(&sem1); + chSemWait(&sem1); + chSemSignal(&sem1); + chSemWait(&sem1); + chSemSignal(&sem1); + chSemWait(&sem1); + chSemSignal(&sem1); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n * 4); + test_println(" wait+signal/S"); +} + +ROMCONST struct testcase testbmk11 = { + "Benchmark, semaphores wait/signal", + bmk11_setup, + NULL, + bmk11_execute +}; + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) +/** + * @page test_benchmarks_012 Mutexes lock/unlock performance + * + *

    Description

    + * A mutex is locked/unlocked into a continuous loop, no Context Switch happens + * because there are no other threads asking for the mutex.
    + * The performance is calculated by measuring the number of iterations after + * a second of continuous operations. + */ + +static void bmk12_setup(void) { + + chMtxInit(&mtx1); +} + +static void bmk12_execute(void) { + uint32_t n = 0; + + test_wait_tick(); + test_start_timer(1000); + do { + chMtxLock(&mtx1); + chMtxUnlock(); + chMtxLock(&mtx1); + chMtxUnlock(); + chMtxLock(&mtx1); + chMtxUnlock(); + chMtxLock(&mtx1); + chMtxUnlock(); + n++; +#if defined(SIMULATOR) + ChkIntSources(); +#endif + } while (!test_timer_done); + test_print("--- Score : "); + test_printn(n * 4); + test_println(" lock+unlock/S"); +} + +ROMCONST struct testcase testbmk12 = { + "Benchmark, mutexes lock/unlock", + bmk12_setup, + NULL, + bmk12_execute +}; +#endif + +/** + * @page test_benchmarks_013 RAM Footprint + * + *

    Description

    + * The memory size of the various kernel objects is printed. + */ + +static void bmk13_execute(void) { + + test_print("--- System: "); + test_printn(sizeof(ReadyList) + sizeof(VTList) + + PORT_IDLE_THREAD_STACK_SIZE + + (sizeof(Thread) + sizeof(struct intctx) + + sizeof(struct extctx) + + PORT_INT_REQUIRED_STACK) * 2); + test_println(" bytes"); + test_print("--- Thread: "); + test_printn(sizeof(Thread)); + test_println(" bytes"); + test_print("--- Timer : "); + test_printn(sizeof(VirtualTimer)); + test_println(" bytes"); + test_print("--- Semaph: "); + test_printn(sizeof(Semaphore)); + test_println(" bytes"); +#if CH_USE_EVENTS || defined(__DOXYGEN__) + test_print("--- EventS: "); + test_printn(sizeof(EventSource)); + test_println(" bytes"); + test_print("--- EventL: "); + test_printn(sizeof(EventListener)); + test_println(" bytes"); +#endif +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + test_print("--- Mutex : "); + test_printn(sizeof(Mutex)); + test_println(" bytes"); +#endif +#if CH_USE_CONDVARS || defined(__DOXYGEN__) + test_print("--- CondV.: "); + test_printn(sizeof(CondVar)); + test_println(" bytes"); +#endif +#if CH_USE_QUEUES || defined(__DOXYGEN__) + test_print("--- Queue : "); + test_printn(sizeof(GenericQueue)); + test_println(" bytes"); +#endif +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + test_print("--- MailB.: "); + test_printn(sizeof(Mailbox)); + test_println(" bytes"); +#endif +} + +ROMCONST struct testcase testbmk13 = { + "Benchmark, RAM footprint", + NULL, + NULL, + bmk13_execute +}; + +/** + * @brief Test sequence for benchmarks. + */ +ROMCONST struct testcase * ROMCONST patternbmk[] = { +#if !TEST_NO_BENCHMARKS + &testbmk1, + &testbmk2, + &testbmk3, + &testbmk4, + &testbmk5, + &testbmk6, + &testbmk7, + &testbmk8, + &testbmk9, + &testbmk10, + &testbmk11, +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + &testbmk12, +#endif + &testbmk13, +#endif + NULL +}; diff --git a/test/testbmk.h b/test/testbmk.h new file mode 100644 index 000000000..8d7514f74 --- /dev/null +++ b/test/testbmk.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTBMK_H_ +#define _TESTBMK_H_ + +extern ROMCONST struct testcase * ROMCONST patternbmk[]; + +#endif /* _TESTBMK_H_ */ diff --git a/test/testdyn.c b/test/testdyn.c new file mode 100644 index 000000000..8e54c81a1 --- /dev/null +++ b/test/testdyn.c @@ -0,0 +1,264 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_dynamic Dynamic APIs test + * + * File: @ref testdyn.c + * + *

    Description

    + * This module implements the test sequence for the dynamic thread creation + * APIs. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the dynamic APIs code. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_DYNAMIC + * - @p CH_USE_HEAP + * - @p CH_USE_MEMPOOLS + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_dynamic_001 + * - @subpage test_dynamic_002 + * - @subpage test_dynamic_003 + * . + * @file testdyn.c + * @brief Dynamic thread APIs test source file + * @file testdyn.h + * @brief Dynamic thread APIs test header file + */ + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +static MemoryHeap heap1; +#endif +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +static MemoryPool mp1; +#endif + +/** + * @page test_dynamic_001 Threads creation from Memory Heap + * + *

    Description

    + * Two threads are started by allocating the memory from the Memory Heap then + * the remaining heap space is arbitrarily allocated and a third tread startup + * is attempted.
    + * The test expects the first two threads to successfully start and the last + * one to fail. + */ + +static msg_t thread(void *p) { + + test_emit_token(*(char *)p); + return 0; +} + +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +static void dyn1_setup(void) { + + chHeapInit(&heap1, test.buffer, sizeof(union test_buffers)); +} + +static void dyn1_execute(void) { + size_t n, sz; + void *p1; + tprio_t prio = chThdGetPriority(); + + (void)chHeapStatus(&heap1, &sz); + /* Starting threads from the heap. */ + threads[0] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), + prio-1, thread, "A"); + threads[1] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), + prio-2, thread, "B"); + /* Allocating the whole heap in order to make the thread creation fail.*/ + (void)chHeapStatus(&heap1, &n); + p1 = chHeapAlloc(&heap1, n); + threads[2] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), + prio-3, thread, "C"); + chHeapFree(p1); + + test_assert(1, (threads[0] != NULL) && + (threads[1] != NULL) && + (threads[2] == NULL) && + (threads[3] == NULL) && + (threads[4] == NULL), + "thread creation failed"); + + /* Claiming the memory from terminated threads. */ + test_wait_threads(); + test_assert_sequence(2, "AB"); + + /* Heap status checked again.*/ + test_assert(3, chHeapStatus(&heap1, &n) == 1, "heap fragmented"); + test_assert(4, n == sz, "heap size changed"); +} + +ROMCONST struct testcase testdyn1 = { + "Dynamic APIs, threads creation from heap", + dyn1_setup, + NULL, + dyn1_execute +}; +#endif /* (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) */ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +/** + * @page test_dynamic_002 Threads creation from Memory Pool + * + *

    Description

    + * Five thread creation are attempted from a pool containing only four + * elements.
    + * The test expects the first four threads to successfully start and the last + * one to fail. + */ + +static void dyn2_setup(void) { + + chPoolInit(&mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); +} + +static void dyn2_execute(void) { + int i; + tprio_t prio = chThdGetPriority(); + + /* Adding the WAs to the pool. */ + for (i = 0; i < 4; i++) + chPoolFree(&mp1, wa[i]); + + /* Starting threads from the memory pool. */ + threads[0] = chThdCreateFromMemoryPool(&mp1, prio-1, thread, "A"); + threads[1] = chThdCreateFromMemoryPool(&mp1, prio-2, thread, "B"); + threads[2] = chThdCreateFromMemoryPool(&mp1, prio-3, thread, "C"); + threads[3] = chThdCreateFromMemoryPool(&mp1, prio-4, thread, "D"); + threads[4] = chThdCreateFromMemoryPool(&mp1, prio-5, thread, "E"); + + test_assert(1, (threads[0] != NULL) && + (threads[1] != NULL) && + (threads[2] != NULL) && + (threads[3] != NULL) && + (threads[4] == NULL), + "thread creation failed"); + + /* Claiming the memory from terminated threads. */ + test_wait_threads(); + test_assert_sequence(2, "ABCD"); + + /* Now the pool must be full again. */ + for (i = 0; i < 4; i++) + test_assert(3, chPoolAlloc(&mp1) != NULL, "pool list empty"); + test_assert(4, chPoolAlloc(&mp1) == NULL, "pool list not empty"); +} + +ROMCONST struct testcase testdyn2 = { + "Dynamic APIs, threads creation from memory pool", + dyn2_setup, + NULL, + dyn2_execute +}; +#endif /* CH_USE_MEMPOOLS */ + +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP && CH_USE_REGISTRY) || \ + defined(__DOXYGEN__) +/** + * @page test_dynamic_003 Registry and References test + * + *

    Description

    + * Registry and Thread References APIs are tested for functionality and + * coverage. + */ + +static bool_t regfind(Thread *tp) { + Thread *ftp; + bool_t found = FALSE; + + ftp = chRegFirstThread(); + do { + found |= ftp == tp; + ftp = chRegNextThread(ftp); + } while (ftp != NULL); + return found; +} + +static void dyn3_setup(void) { + + chHeapInit(&heap1, test.buffer, sizeof(union test_buffers)); +} + +static void dyn3_execute(void) { + Thread *tp; + tprio_t prio = chThdGetPriority(); + + /* Testing references increase/decrease and final detach.*/ + tp = chThdCreateFromHeap(&heap1, WA_SIZE, prio-1, thread, "A"); + test_assert(1, tp->p_refs == 1, "wrong initial reference counter"); + chThdAddRef(tp); + test_assert(2, tp->p_refs == 2, "references increase failure"); + chThdRelease(tp); + test_assert(3, tp->p_refs == 1, "references decrease failure"); + + /* Verify the new threads count.*/ + test_assert(4, regfind(tp), "thread missing from registry"); + test_assert(5, regfind(tp), "thread disappeared"); + + /* Detach and let the thread execute and terminate.*/ + chThdRelease(tp); + test_assert(6, tp->p_refs == 0, "detach failure"); + test_assert(7, tp->p_state == THD_STATE_READY, "invalid state"); + test_assert(8, regfind(tp), "thread disappeared"); + test_assert(9, regfind(tp), "thread disappeared"); + chThdSleepMilliseconds(50); /* The thread just terminates. */ + test_assert(10, tp->p_state == THD_STATE_FINAL, "invalid state"); + + /* Clearing the zombie by scanning the registry.*/ + test_assert(11, regfind(tp), "thread disappeared"); + test_assert(12, !regfind(tp), "thread still in registry"); +} + +ROMCONST struct testcase testdyn3 = { + "Dynamic APIs, registry and references", + dyn3_setup, + NULL, + dyn3_execute +}; +#endif /* CH_USE_HEAP && CH_USE_REGISTRY */ +#endif /* CH_USE_DYNAMIC */ + +/** + * @brief Test sequence for dynamic APIs. + */ +ROMCONST struct testcase * ROMCONST patterndyn[] = { +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) + &testdyn1, +#endif +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + &testdyn2, +#endif +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP && CH_USE_REGISTRY) || \ + defined(__DOXYGEN__) + &testdyn3, +#endif +#endif + NULL +}; diff --git a/test/testdyn.h b/test/testdyn.h new file mode 100644 index 000000000..6b25dbb30 --- /dev/null +++ b/test/testdyn.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTDYN_H_ +#define _TESTDYN_H_ + +extern ROMCONST struct testcase * ROMCONST patterndyn[]; + +#endif /* _TESTDYN_H_ */ diff --git a/test/testevt.c b/test/testevt.c new file mode 100644 index 000000000..0a014374e --- /dev/null +++ b/test/testevt.c @@ -0,0 +1,294 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_events Events test + * + * File: @ref testevt.c + * + *

    Description

    + * This module implements the test sequence for the @ref events subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref events subsystem. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_EVENTS + * - @p CH_USE_EVENTS_TIMEOUT + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_events_001 + * - @subpage test_events_002 + * - @subpage test_events_003 + * . + * @file testevt.c + * @brief Events test source file + * @file testevt.h + * @brief Events test header file + */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + +#define ALLOWED_DELAY MS2ST(5) + +/* + * Note, the static initializers are not really required because the + * variables are explicitly initialized in each test case. It is done in order + * to test the macros. + */ +static EVENTSOURCE_DECL(es1); +static EVENTSOURCE_DECL(es2); + +/** + * @page test_events_001 Events registration and dispatch + * + *

    Description

    + * Two event listeners are registered on an event source and then unregistered + * in the same order.
    + * The test expects that the even source has listeners after the registrations + * and after the first unregistration, then, after the second unegistration, + * the test expects no more listeners.
    + * In the second part the test dispatches three event flags and verifies that + * the associated event handlers are invoked in LSb-first order. + */ + +static void evt1_setup(void) { + + chEvtGetAndClearEvents(ALL_EVENTS); +} + +static void h1(eventid_t id) {(void)id;test_emit_token('A');} +static void h2(eventid_t id) {(void)id;test_emit_token('B');} +static void h3(eventid_t id) {(void)id;test_emit_token('C');} +static ROMCONST evhandler_t evhndl[] = {h1, h2, h3}; + +static void evt1_execute(void) { + EventListener el1, el2; + + /* + * Testing chEvtRegisterMask() and chEvtUnregister(). + */ + chEvtInit(&es1); + chEvtRegisterMask(&es1, &el1, 1); + chEvtRegisterMask(&es1, &el2, 2); + test_assert(1, chEvtIsListeningI(&es1), "no listener"); + chEvtUnregister(&es1, &el1); + test_assert(2, chEvtIsListeningI(&es1), "no listener"); + chEvtUnregister(&es1, &el2); + test_assert(3, !chEvtIsListeningI(&es1), "stuck listener"); + + /* + * Testing chEvtDispatch(). + */ + chEvtDispatch(evhndl, 7); + test_assert_sequence(4, "ABC"); +} + +ROMCONST struct testcase testevt1 = { + "Events, registration and dispatch", + evt1_setup, + NULL, + evt1_execute +}; + +/** + * @page test_events_002 Events wait and broadcast + * + *

    Description

    + * In this test the following APIs are indipently tested by starting threads + * that signal/broadcast events after fixed delays: + * - @p chEvtWaitOne() + * - @p chEvtWaitAny() + * - @p chEvtWaitAll() + * . + * After each test phase the test verifies that the events have been served at + * the expected time and that there are no stuck event flags. + */ + +static void evt2_setup(void) { + + chEvtGetAndClearEvents(ALL_EVENTS); +} + +static msg_t thread1(void *p) { + + chThdSleepMilliseconds(50); + chEvtSignal((Thread *)p, 1); + return 0; +} + +static msg_t thread2(void *p) { + + (void)p; + chEvtBroadcast(&es1); + chThdSleepMilliseconds(50); + chEvtBroadcast(&es2); + return 0; +} + +static void evt2_execute(void) { + eventmask_t m; + EventListener el1, el2; + systime_t target_time; + + /* + * Test on chEvtWaitOne() without wait. + */ + chEvtAddEvents(5); + m = chEvtWaitOne(ALL_EVENTS); + test_assert(1, m == 1, "single event error"); + m = chEvtWaitOne(ALL_EVENTS); + test_assert(2, m == 4, "single event error"); + m = chEvtGetAndClearEvents(ALL_EVENTS); + test_assert(3, m == 0, "stuck event"); + + /* + * Test on chEvtWaitOne() with wait. + */ + test_wait_tick(); + target_time = chTimeNow() + MS2ST(50); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, + thread1, chThdSelf()); + m = chEvtWaitOne(ALL_EVENTS); + test_assert_time_window(4, target_time, target_time + ALLOWED_DELAY); + test_assert(5, m == 1, "single event error"); + m = chEvtGetAndClearEvents(ALL_EVENTS); + test_assert(6, m == 0, "stuck event"); + test_wait_threads(); + + /* + * Test on chEvtWaitAny() without wait. + */ + chEvtAddEvents(5); + m = chEvtWaitAny(ALL_EVENTS); + test_assert(7, m == 5, "unexpected pending bit"); + m = chEvtGetAndClearEvents(ALL_EVENTS); + test_assert(8, m == 0, "stuck event"); + + /* + * Test on chEvtWaitAny() with wait. + */ + test_wait_tick(); + target_time = chTimeNow() + MS2ST(50); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, + thread1, chThdSelf()); + m = chEvtWaitAny(ALL_EVENTS); + test_assert_time_window(9, target_time, target_time + ALLOWED_DELAY); + test_assert(10, m == 1, "single event error"); + m = chEvtGetAndClearEvents(ALL_EVENTS); + test_assert(11, m == 0, "stuck event"); + test_wait_threads(); + + /* + * Test on chEvtWaitAll(). + */ + chEvtInit(&es1); + chEvtInit(&es2); + chEvtRegisterMask(&es1, &el1, 1); + chEvtRegisterMask(&es2, &el2, 4); + test_wait_tick(); + target_time = chTimeNow() + MS2ST(50); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, + thread2, "A"); + m = chEvtWaitAll(5); + test_assert_time_window(12, target_time, target_time + ALLOWED_DELAY); + m = chEvtGetAndClearEvents(ALL_EVENTS); + test_assert(13, m == 0, "stuck event"); + test_wait_threads(); + chEvtUnregister(&es1, &el1); + chEvtUnregister(&es2, &el2); + test_assert(14, !chEvtIsListeningI(&es1), "stuck listener"); + test_assert(15, !chEvtIsListeningI(&es2), "stuck listener"); +} + +ROMCONST struct testcase testevt2 = { + "Events, wait and broadcast", + evt2_setup, + NULL, + evt2_execute +}; + +#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) +/** + * @page test_events_003 Events timeout + * + *

    Description

    + * In this test the following APIs are let to timeout twice: immediatly and + * after 10ms: + * In this test the following APIs are indipently tested by starting threads + * that broadcast events after fixed delays: + * - @p chEvtWaitOneTimeout() + * - @p chEvtWaitAnyTimeout() + * - @p chEvtWaitAllTimeout() + * . + * After each test phase the test verifies that there are no stuck event flags. + */ + +static void evt3_setup(void) { + + chEvtGetAndClearEvents(ALL_EVENTS); +} + +static void evt3_execute(void) { + eventmask_t m; + + /* + * Tests various timeout situations. + */ + m = chEvtWaitOneTimeout(ALL_EVENTS, TIME_IMMEDIATE); + test_assert(1, m == 0, "spurious event"); + m = chEvtWaitAnyTimeout(ALL_EVENTS, TIME_IMMEDIATE); + test_assert(2, m == 0, "spurious event"); + m = chEvtWaitAllTimeout(ALL_EVENTS, TIME_IMMEDIATE); + test_assert(3, m == 0, "spurious event"); + m = chEvtWaitOneTimeout(ALL_EVENTS, 10); + test_assert(4, m == 0, "spurious event"); + m = chEvtWaitAnyTimeout(ALL_EVENTS, 10); + test_assert(5, m == 0, "spurious event"); + m = chEvtWaitAllTimeout(ALL_EVENTS, 10); + test_assert(6, m == 0, "spurious event"); +} + +ROMCONST struct testcase testevt3 = { + "Events, timeouts", + evt3_setup, + NULL, + evt3_execute +}; +#endif /* CH_USE_EVENTS_TIMEOUT */ + +/** + * @brief Test sequence for events. + */ +ROMCONST struct testcase * ROMCONST patternevt[] = { +#if CH_USE_EVENTS || defined(__DOXYGEN__) + &testevt1, + &testevt2, +#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) + &testevt3, +#endif +#endif + NULL +}; + +#endif /* CH_USE_EVENTS */ diff --git a/test/testevt.h b/test/testevt.h new file mode 100644 index 000000000..7d189c17f --- /dev/null +++ b/test/testevt.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTEVT_H_ +#define _TESTEVT_H_ + +extern ROMCONST struct testcase * ROMCONST patternevt[]; + +#endif /* _TESTEVT_H_ */ diff --git a/test/testheap.c b/test/testheap.c new file mode 100644 index 000000000..9baa95d82 --- /dev/null +++ b/test/testheap.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_heap Memory Heap test + * + * File: @ref testheap.c + * + *

    Description

    + * This module implements the test sequence for the @ref heaps subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref heaps subsystem. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_HEAP + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_heap_001 + * . + * @file testheap.c + * @brief Heap test source file + * @file testheap.h + * @brief Heap header file + */ + +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) + +#define SIZE 16 + +static MemoryHeap test_heap; + +/** + * @page test_heap_001 Allocation and fragmentation test + * + *

    Description

    + * Series of allocations/deallocations are performed in carefully designed + * sequences in order to stimulate all the possible code paths inside the + * allocator.
    + * The test expects to find the heap back to the initial status after each + * sequence. + */ + +static void heap1_setup(void) { + + chHeapInit(&test_heap, test.buffer, sizeof(union test_buffers)); +} + +static void heap1_execute(void) { + void *p1, *p2, *p3; + size_t n, sz; + + /* Unrelated, for coverage only.*/ + (void)chCoreStatus(); + + /* + * Test on the default heap in order to cover the core allocator at + * least one time. + */ + (void)chHeapStatus(NULL, &sz); + p1 = chHeapAlloc(NULL, SIZE); + test_assert(1, p1 != NULL, "allocation failed"); + chHeapFree(p1); + p1 = chHeapAlloc(NULL, (size_t)-256); + test_assert(2, p1 == NULL, "allocation not failed"); + + /* Initial local heap state.*/ + (void)chHeapStatus(&test_heap, &sz); + + /* Same order.*/ + p1 = chHeapAlloc(&test_heap, SIZE); + p2 = chHeapAlloc(&test_heap, SIZE); + p3 = chHeapAlloc(&test_heap, SIZE); + chHeapFree(p1); /* Does not merge.*/ + chHeapFree(p2); /* Merges backward.*/ + chHeapFree(p3); /* Merges both sides.*/ + test_assert(3, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); + + /* Reverse order.*/ + p1 = chHeapAlloc(&test_heap, SIZE); + p2 = chHeapAlloc(&test_heap, SIZE); + p3 = chHeapAlloc(&test_heap, SIZE); + chHeapFree(p3); /* Merges forward.*/ + chHeapFree(p2); /* Merges forward.*/ + chHeapFree(p1); /* Merges forward.*/ + test_assert(4, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); + + /* Small fragments handling.*/ + p1 = chHeapAlloc(&test_heap, SIZE + 1); + p2 = chHeapAlloc(&test_heap, SIZE); + chHeapFree(p1); + test_assert(5, chHeapStatus(&test_heap, &n) == 2, "invalid state"); + p1 = chHeapAlloc(&test_heap, SIZE); + /* Note, the first situation happens when the alignment size is smaller + than the header size, the second in the other cases.*/ + test_assert(6, (chHeapStatus(&test_heap, &n) == 1) || + (chHeapStatus(&test_heap, &n) == 2), "heap fragmented"); + chHeapFree(p2); + chHeapFree(p1); + test_assert(7, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); + + /* Skip fragment handling.*/ + p1 = chHeapAlloc(&test_heap, SIZE); + p2 = chHeapAlloc(&test_heap, SIZE); + chHeapFree(p1); + test_assert(8, chHeapStatus(&test_heap, &n) == 2, "invalid state"); + p1 = chHeapAlloc(&test_heap, SIZE * 2); /* Skips first fragment.*/ + chHeapFree(p1); + chHeapFree(p2); + test_assert(9, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); + + /* Allocate all handling.*/ + (void)chHeapStatus(&test_heap, &n); + p1 = chHeapAlloc(&test_heap, n); + test_assert(10, chHeapStatus(&test_heap, &n) == 0, "not empty"); + chHeapFree(p1); + + test_assert(11, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); + test_assert(12, n == sz, "size changed"); +} + +ROMCONST struct testcase testheap1 = { + "Heap, allocation and fragmentation test", + heap1_setup, + NULL, + heap1_execute +}; + +#endif /* CH_USE_HEAP.*/ + +/** + * @brief Test sequence for heap. + */ +ROMCONST struct testcase * ROMCONST patternheap[] = { +#if (CH_USE_HEAP && !CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) + &testheap1, +#endif + NULL +}; diff --git a/test/testheap.h b/test/testheap.h new file mode 100644 index 000000000..24d577445 --- /dev/null +++ b/test/testheap.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTHEAP_H_ +#define _TESTHEAP_H_ + +extern ROMCONST struct testcase * ROMCONST patternheap[]; + +#endif /* _TESTHEAP_H_ */ diff --git a/test/testmbox.c b/test/testmbox.c new file mode 100644 index 000000000..b1fe675cc --- /dev/null +++ b/test/testmbox.c @@ -0,0 +1,239 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_mbox Mailboxes test + * + * File: @ref testmbox.c + * + *

    Description

    + * This module implements the test sequence for the @ref mailboxes subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref mailboxes + * subsystem code.
    + * Note that the @ref mailboxes subsystem depends on the @ref semaphores + * subsystem that has to met its testing objectives as well. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_MAILBOXES + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_mbox_001 + * . + * @file testmbox.c + * @brief Mailboxes test source file + * @file testmbox.h + * @brief Mailboxes header file + */ + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + +#define ALLOWED_DELAY MS2ST(5) +#define MB_SIZE 5 + +/* + * Note, the static initializers are not really required because the + * variables are explicitly initialized in each test case. It is done in order + * to test the macros. + */ +static MAILBOX_DECL(mb1, test.wa.T0, MB_SIZE); + +/** + * @page test_mbox_001 Queuing and timeouts + * + *

    Description

    + * Messages are posted/fetched from a mailbox in carefully designed sequences + * in order to stimulate all the possible code paths inside the mailbox.
    + * The test expects to find a consistent mailbox status after each operation. + */ + +static void mbox1_setup(void) { + + chMBInit(&mb1, (msg_t *)test.wa.T0, MB_SIZE); +} + +static void mbox1_execute(void) { + msg_t msg1, msg2; + unsigned i; + + /* + * Testing initial space. + */ + test_assert(1, chMBGetFreeCountI(&mb1) == MB_SIZE, "wrong size"); + + /* + * Testing enqueuing and backward circularity. + */ + for (i = 0; i < MB_SIZE - 1; i++) { + msg1 = chMBPost(&mb1, 'B' + i, TIME_INFINITE); + test_assert(2, msg1 == RDY_OK, "wrong wake-up message"); + } + msg1 = chMBPostAhead(&mb1, 'A', TIME_INFINITE); + test_assert(3, msg1 == RDY_OK, "wrong wake-up message"); + + /* + * Testing post timeout. + */ + msg1 = chMBPost(&mb1, 'X', 1); + test_assert(4, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + chSysLock(); + msg1 = chMBPostI(&mb1, 'X'); + chSysUnlock(); + test_assert(5, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + msg1 = chMBPostAhead(&mb1, 'X', 1); + test_assert(6, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + chSysLock(); + msg1 = chMBPostAheadI(&mb1, 'X'); + chSysUnlock(); + test_assert(7, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + + /* + * Testing final conditions. + */ + test_assert_lock(8, chMBGetFreeCountI(&mb1) == 0, "still empty"); + test_assert_lock(9, chMBGetUsedCountI(&mb1) == MB_SIZE, "not full"); + test_assert_lock(10, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + + /* + * Testing dequeuing. + */ + for (i = 0; i < MB_SIZE; i++) { + msg1 = chMBFetch(&mb1, &msg2, TIME_INFINITE); + test_assert(11, msg1 == RDY_OK, "wrong wake-up message"); + test_emit_token(msg2); + } + test_assert_sequence(12, "ABCDE"); + + /* + * Testing buffer circularity. + */ + msg1 = chMBPost(&mb1, 'B' + i, TIME_INFINITE); + test_assert(13, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBFetch(&mb1, &msg2, TIME_INFINITE); + test_assert(14, msg1 == RDY_OK, "wrong wake-up message"); + test_assert(15, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base"); + test_assert(16, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base"); + + /* + * Testing fetch timeout. + */ + msg1 = chMBFetch(&mb1, &msg2, 1); + test_assert(17, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + chSysLock(); + msg1 = chMBFetchI(&mb1, &msg2); + chSysUnlock(); + test_assert(18, msg1 == RDY_TIMEOUT, "wrong wake-up message"); + + /* + * Testing final conditions. + */ + test_assert_lock(19, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty"); + test_assert_lock(20, chMBGetUsedCountI(&mb1) == 0, "still full"); + test_assert_lock(21, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + + /* + * Testing I-Class. + */ + chSysLock() + msg1 = chMBPostI(&mb1, 'A'); + test_assert(22, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostI(&mb1, 'B'); + test_assert(23, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostI(&mb1, 'C'); + test_assert(24, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostI(&mb1, 'D'); + test_assert(25, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostI(&mb1, 'E'); + chSysUnlock(); + test_assert(26, msg1 == RDY_OK, "wrong wake-up message"); + test_assert(27, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + for (i = 0; i < MB_SIZE; i++) { + chSysLock(); + msg1 = chMBFetchI(&mb1, &msg2); + chSysUnlock(); + test_assert(28, msg1 == RDY_OK, "wrong wake-up message"); + test_emit_token(msg2); + } + test_assert_sequence(29, "ABCDE"); + test_assert_lock(30, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty"); + test_assert_lock(31, chMBGetUsedCountI(&mb1) == 0, "still full"); + test_assert(32, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + + chSysLock(); + msg1 = chMBPostAheadI(&mb1, 'E'); + test_assert(33, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostAheadI(&mb1, 'D'); + test_assert(34, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostAheadI(&mb1, 'C'); + test_assert(35, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostAheadI(&mb1, 'B'); + test_assert(36, msg1 == RDY_OK, "wrong wake-up message"); + msg1 = chMBPostAheadI(&mb1, 'A'); + chSysUnlock(); + test_assert(37, msg1 == RDY_OK, "wrong wake-up message"); + test_assert(38, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + for (i = 0; i < MB_SIZE; i++) { + chSysLock(); + msg1 = chMBFetchI(&mb1, &msg2); + chSysUnlock(); + test_assert(39, msg1 == RDY_OK, "wrong wake-up message"); + test_emit_token(msg2); + } + test_assert_sequence(40, "ABCDE"); + test_assert_lock(41, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty"); + test_assert_lock(42, chMBGetUsedCountI(&mb1) == 0, "still full"); + test_assert(43, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); + + /* + * Testing reset. + */ + chMBReset(&mb1); + + /* + * Re-testing final conditions. + */ + test_assert_lock(44, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty"); + test_assert_lock(45, chMBGetUsedCountI(&mb1) == 0, "still full"); + test_assert_lock(46, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base"); + test_assert_lock(47, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base"); +} + +ROMCONST struct testcase testmbox1 = { + "Mailboxes, queuing and timeouts", + mbox1_setup, + NULL, + mbox1_execute +}; + +#endif /* CH_USE_MAILBOXES */ + +/** + * @brief Test sequence for mailboxes. + */ +ROMCONST struct testcase * ROMCONST patternmbox[] = { +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + &testmbox1, +#endif + NULL +}; diff --git a/test/testmbox.h b/test/testmbox.h new file mode 100644 index 000000000..5b61ec888 --- /dev/null +++ b/test/testmbox.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTMBOX_H_ +#define _TESTMBOX_H_ + +extern ROMCONST struct testcase * ROMCONST patternmbox[]; + +#endif /* _TESTMBOX_H_ */ diff --git a/test/testmsg.c b/test/testmsg.c new file mode 100644 index 000000000..3ffaa6bf7 --- /dev/null +++ b/test/testmsg.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_msg Messages test + * + * File: @ref testmsg.c + * + *

    Description

    + * This module implements the test sequence for the @ref messages subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref messages + * subsystem code. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_MESSAGES + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_msg_001 + * . + * @file testmsg.c + * @brief Messages test source file + * @file testmsg.h + * @brief Messages header file + */ + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + +/** + * @page test_msg_001 Messages Server loop + * + *

    Description

    + * A thread is spawned that sends four messages back to the tester thread.
    + * The test expect to receive the messages in the correct sequence and to + * not find a fifth message waiting. + */ + +static msg_t thread(void *p) { + + chMsgSend(p, 'A'); + chMsgSend(p, 'B'); + chMsgSend(p, 'C'); + return 0; +} + +static void msg1_execute(void) { + Thread *tp; + msg_t msg; + + /* + * Testing the whole messages loop. + */ + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() + 1, + thread, chThdSelf()); + tp = chMsgWait(); + msg = chMsgGet(tp); + chMsgRelease(tp, msg); + test_emit_token(msg); + tp = chMsgWait(); + msg = chMsgGet(tp); + chMsgRelease(tp, msg); + test_emit_token(msg); + tp = chMsgWait(); + msg = chMsgGet(tp); + chMsgRelease(tp, msg); + test_emit_token(msg); + test_assert_sequence(1, "ABC"); +} + +ROMCONST struct testcase testmsg1 = { + "Messages, loop", + NULL, + NULL, + msg1_execute +}; + +#endif /* CH_USE_MESSAGES */ + +/** + * @brief Test sequence for messages. + */ +ROMCONST struct testcase * ROMCONST patternmsg[] = { +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + &testmsg1, +#endif + NULL +}; diff --git a/test/testmsg.h b/test/testmsg.h new file mode 100644 index 000000000..47f072d14 --- /dev/null +++ b/test/testmsg.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTMSG_H_ +#define _TESTMSG_H_ + +extern ROMCONST struct testcase * ROMCONST patternmsg[]; + +#endif /* _TESTMSG_H_ */ diff --git a/test/testmtx.c b/test/testmtx.c new file mode 100644 index 000000000..149f47d11 --- /dev/null +++ b/test/testmtx.c @@ -0,0 +1,635 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_mtx Mutexes test + * + * File: @ref testmtx.c + * + *

    Description

    + * This module implements the test sequence for the @ref mutexes and + * @ref condvars subsystems.
    + * Tests on those subsystems are particularly critical because the system-wide + * implications of the Priority Inheritance mechanism. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the subsystems code. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_MUTEXES + * - @p CH_USE_CONDVARS + * - @p CH_DBG_THREADS_PROFILING + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_mtx_001 + * - @subpage test_mtx_002 + * - @subpage test_mtx_003 + * - @subpage test_mtx_004 + * - @subpage test_mtx_005 + * - @subpage test_mtx_006 + * - @subpage test_mtx_007 + * - @subpage test_mtx_008 + * . + * @file testmtx.c + * @brief Mutexes and CondVars test source file + * @file testmtx.h + * @brief Mutexes and CondVars test header file + */ + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + +#define ALLOWED_DELAY 5 + +/* + * Note, the static initializers are not really required because the + * variables are explicitly initialized in each test case. It is done in order + * to test the macros. + */ +static MUTEX_DECL(m1); +static MUTEX_DECL(m2); +#if CH_USE_CONDVARS || defined(__DOXYGEN__) +static CONDVAR_DECL(c1); +#endif + +/** + * @page test_mtx_001 Priority enqueuing test + * + *

    Description

    + * Five threads, with increasing priority, are enqueued on a locked mutex then + * the mutex is unlocked.
    + * The test expects the threads to perform their operations in increasing + * priority order regardless of the initial order. + */ + +static void mtx1_setup(void) { + + chMtxInit(&m1); +} + +static msg_t thread1(void *p) { + + chMtxLock(&m1); + test_emit_token(*(char *)p); + chMtxUnlock(); + return 0; +} + +static void mtx1_execute(void) { + + tprio_t prio = chThdGetPriority(); /* Because priority inheritance.*/ + chMtxLock(&m1); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread1, "E"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread1, "D"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread1, "C"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread1, "B"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread1, "A"); + chMtxUnlock(); + test_wait_threads(); + test_assert(1, prio == chThdGetPriority(), "wrong priority level"); + test_assert_sequence(2, "ABCDE"); +} + +ROMCONST struct testcase testmtx1 = { + "Mutexes, priority enqueuing test", + mtx1_setup, + NULL, + mtx1_execute +}; + +#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) +/** + * @page test_mtx_002 Priority inheritance, simple case + * + *

    Description

    + * Three threads are involved in the classic priority inversion scenario, a + * medium priority thread tries to starve an high priority thread by + * blocking a low priority thread into a mutex lock zone.
    + * The test expects the threads to reach their goal in increasing priority + * order by rearranging their priorities in order to avoid the priority + * inversion trap. + * + *

    Scenario

    + * This weird looking diagram should explain what happens in the test case: + * @code + * Time ----> 0 10 20 30 40 50 60 70 80 90 100 + * 0 ......AL++++++++++............2+++++++++++AU0---------------++++++G... + * 1 ..................++++++++++++------------------++++++++++++G......... + * 2 .............................AL..........++++++AUG................... + * ^ ^ + * Legend: + * 0..2 - Priority levels + * +++ - Running + * --- - Ready + * ... - Waiting or Terminated + * xL - Lock operation on mutex 'x' + * xUn - Unlock operation on mutex 'x' with priority returning to level 'n' + * G - Goal + * ^ - Priority transition (boost or return). + * @endcode + */ + +static void mtx2_setup(void) { + + chMtxInit(&m1); +} + +/* Low priority thread */ +static msg_t thread2L(void *p) { + + (void)p; + chMtxLock(&m1); + test_cpu_pulse(40); + chMtxUnlock(); + test_cpu_pulse(10); + test_emit_token('C'); + return 0; +} + +/* Medium priority thread */ +static msg_t thread2M(void *p) { + + (void)p; + chThdSleepMilliseconds(20); + test_cpu_pulse(40); + test_emit_token('B'); + return 0; +} + +/* High priority thread */ +static msg_t thread2H(void *p) { + + (void)p; + chThdSleepMilliseconds(40); + chMtxLock(&m1); + test_cpu_pulse(10); + chMtxUnlock(); + test_emit_token('A'); + return 0; +} + +static void mtx2_execute(void) { + systime_t time; + + test_wait_tick(); + time = chTimeNow(); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread2H, 0); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-2, thread2M, 0); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread2L, 0); + test_wait_threads(); + test_assert_sequence(1, "ABC"); + test_assert_time_window(2, time + MS2ST(100), time + MS2ST(100) + ALLOWED_DELAY); +} + +ROMCONST struct testcase testmtx2 = { + "Mutexes, priority inheritance, simple case", + mtx2_setup, + NULL, + mtx2_execute +}; + +/** + * @page test_mtx_003 Priority inheritance, complex case + * + *

    Description

    + * Five threads are involved in the complex priority inversion scenario, + * please refer to the diagram below for the complete scenario.
    + * The test expects the threads to perform their operations in increasing + * priority order by rearranging their priorities in order to avoid the + * priority inversion trap. + * + *

    Scenario

    + * This weird looking diagram should explain what happens in the test case: + * @code + * Time ----> 0 10 20 30 40 50 60 70 80 90 100 110 + * 0 ......BL++++------------2+++++------4+++++BU0---------------------------G..... + * 1 ............AL++++2+++++BL----------4-----++++++BU4+++AU1---------------G..... + * 2 ..................AL----------------------------------------------++++++AUG... + * 3 ..............................+++++++-----------------------++++++G........... + * 4 ....................................AL................++++++AUG............... + * ^ ^ ^ ^ ^ ^ + * Legend: + * 0..4 - Priority levels + * +++ - Running + * --- - Ready + * ... - Waiting or Terminated + * xL - Lock operation on mutex 'x' + * xUn - Unlock operation on mutex 'x' with priority returning to level 'n' + * ^ - Priority transition (boost or return). + * @endcode + */ + +static void mtx3_setup(void) { + + chMtxInit(&m1); /* Mutex B.*/ + chMtxInit(&m2); /* Mutex A.*/ +} + +/* Lowest priority thread */ +static msg_t thread3LL(void *p) { + + (void)p; + chMtxLock(&m1); + test_cpu_pulse(30); + chMtxUnlock(); + test_emit_token('E'); + return 0; +} + +/* Low priority thread */ +static msg_t thread3L(void *p) { + + (void)p; + chThdSleepMilliseconds(10); + chMtxLock(&m2); + test_cpu_pulse(20); + chMtxLock(&m1); + test_cpu_pulse(10); + chMtxUnlock(); + test_cpu_pulse(10); + chMtxUnlock(); + test_emit_token('D'); + return 0; +} + +/* Medium priority thread */ +static msg_t thread3M(void *p) { + + (void)p; + chThdSleepMilliseconds(20); + chMtxLock(&m2); + test_cpu_pulse(10); + chMtxUnlock(); + test_emit_token('C'); + return 0; +} + +/* High priority thread */ +static msg_t thread3H(void *p) { + + (void)p; + chThdSleepMilliseconds(40); + test_cpu_pulse(20); + test_emit_token('B'); + return 0; +} + +/* Highest priority thread */ +static msg_t thread3HH(void *p) { + + (void)p; + chThdSleepMilliseconds(50); + chMtxLock(&m2); + test_cpu_pulse(10); + chMtxUnlock(); + test_emit_token('A'); + return 0; +} + +static void mtx3_execute(void) { + systime_t time; + + test_wait_tick(); + time = chTimeNow(); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread3LL, 0); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread3L, 0); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread3M, 0); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread3H, 0); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread3HH, 0); + test_wait_threads(); + test_assert_sequence(1, "ABCDE"); + test_assert_time_window(2, time + MS2ST(110), time + MS2ST(110) + ALLOWED_DELAY); +} + +ROMCONST struct testcase testmtx3 = { + "Mutexes, priority inheritance, complex case", + mtx3_setup, + NULL, + mtx3_execute +}; +#endif /* CH_DBG_THREADS_PROFILING */ + +/** + * @page test_mtx_004 Priority return verification + * + *

    Description

    + * Two threads are spawned that try to lock the mutexes locked by the tester + * thread with precise timing.
    + * The test expects that the priority changes caused by the priority + * inheritance algorithm happen at the right moment and with the right values. + */ + +static void mtx4_setup(void) { + + chMtxInit(&m1); + chMtxInit(&m2); +} + +static msg_t thread4a(void *p) { + + (void)p; + chThdSleepMilliseconds(50); + chMtxLock(&m2); + chMtxUnlock(); + return 0; +} + +static msg_t thread4b(void *p) { + + (void)p; + chThdSleepMilliseconds(150); + chMtxLock(&m1); + chMtxUnlock(); + return 0; +} + +static void mtx4_execute(void) { + tprio_t p, p1, p2; + + p = chThdGetPriority(); + p1 = p + 1; + p2 = p + 2; + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, p1, thread4a, "B"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, p2, thread4b, "A"); + chMtxLock(&m2); + test_assert(1, chThdGetPriority() == p, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(2, chThdGetPriority() == p1, "wrong priority level"); + chMtxLock(&m1); + test_assert(3, chThdGetPriority() == p1, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(4, chThdGetPriority() == p2, "wrong priority level"); + chMtxUnlock(); + test_assert(5, chThdGetPriority() == p1, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(6, chThdGetPriority() == p1, "wrong priority level"); + chMtxUnlockAll(); + test_assert(7, chThdGetPriority() == p, "wrong priority level"); + test_wait_threads(); + + /* Test repeated in order to cover chMtxUnlockS().*/ + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, p1, thread4a, "D"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, p2, thread4b, "C"); + chMtxLock(&m2); + test_assert(8, chThdGetPriority() == p, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(9, chThdGetPriority() == p1, "wrong priority level"); + chMtxLock(&m1); + test_assert(10, chThdGetPriority() == p1, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(11, chThdGetPriority() == p2, "wrong priority level"); + chSysLock(); + chMtxUnlockS(); + chSysUnlock(); + test_assert(12, chThdGetPriority() == p1, "wrong priority level"); + chThdSleepMilliseconds(100); + test_assert(13, chThdGetPriority() == p1, "wrong priority level"); + chMtxUnlockAll(); + test_assert(14, chThdGetPriority() == p, "wrong priority level"); + test_wait_threads(); +} + +ROMCONST struct testcase testmtx4 = { + "Mutexes, priority return", + mtx4_setup, + NULL, + mtx4_execute +}; + +/** + * @page test_mtx_005 Mutex status + * + *

    Description

    + * Various tests on the mutex structure status after performing some lock and + * unlock operations.
    + * The test expects that the internal mutex status is consistent after each + * operation. + */ + +static void mtx5_setup(void) { + + chMtxInit(&m1); +} + +static void mtx5_execute(void) { + bool_t b; + tprio_t prio; + + prio = chThdGetPriority(); + + b = chMtxTryLock(&m1); + test_assert(1, b, "already locked"); + + b = chMtxTryLock(&m1); + test_assert(2, !b, "not locked"); + + chSysLock(); + chMtxUnlockS(); + chSysUnlock(); + + test_assert(3, isempty(&m1.m_queue), "queue not empty"); + test_assert(4, m1.m_owner == NULL, "still owned"); + test_assert(5, chThdGetPriority() == prio, "wrong priority level"); + + chMtxLock(&m1); + chMtxUnlockAll(); + test_assert(6, isempty(&m1.m_queue), "queue not empty"); + test_assert(7, m1.m_owner == NULL, "still owned"); +} + +ROMCONST struct testcase testmtx5 = { + "Mutexes, status", + mtx5_setup, + NULL, + mtx5_execute +}; + +#if CH_USE_CONDVARS || defined(__DOXYGEN__) +/** + * @page test_mtx_006 Condition Variable signal test + * + *

    Description

    + * Five threads take a mutex and then enter a conditional variable queue, the + * tester thread then proceeds to signal the conditional variable five times + * atomically.
    + * The test expects the threads to reach their goal in increasing priority + * order regardless of the initial order. + */ + +static void mtx6_setup(void) { + + chCondInit(&c1); + chMtxInit(&m1); +} + +static msg_t thread10(void *p) { + + chMtxLock(&m1); + chCondWait(&c1); + test_emit_token(*(char *)p); + chMtxUnlock(); + return 0; +} + +static void mtx6_execute(void) { + + tprio_t prio = chThdGetPriority(); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread10, "E"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "D"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread10, "C"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread10, "B"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread10, "A"); + chSysLock(); + chCondSignalI(&c1); + chCondSignalI(&c1); + chCondSignalI(&c1); + chCondSignalI(&c1); + chCondSignalI(&c1); + chSchRescheduleS(); + chSysUnlock(); + test_wait_threads(); + test_assert_sequence(1, "ABCDE"); +} + +ROMCONST struct testcase testmtx6 = { + "CondVar, signal test", + mtx6_setup, + NULL, + mtx6_execute +}; + +/** + * @page test_mtx_007 Condition Variable broadcast test + * + *

    Description

    + * Five threads take a mutex and then enter a conditional variable queue, the + * tester thread then proceeds to broadcast the conditional variable.
    + * The test expects the threads to reach their goal in increasing priority + * order regardless of the initial order. + */ + +static void mtx7_setup(void) { + + chCondInit(&c1); + chMtxInit(&m1); +} + +static void mtx7_execute(void) { + + tprio_t prio = chThdGetPriority(); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread10, "E"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "D"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread10, "C"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread10, "B"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread10, "A"); + chCondBroadcast(&c1); + test_wait_threads(); + test_assert_sequence(1, "ABCDE"); +} + +ROMCONST struct testcase testmtx7 = { + "CondVar, broadcast test", + mtx7_setup, + NULL, + mtx7_execute +}; + +/** + * @page test_mtx_008 Condition Variable priority boost test + * + *

    Description

    + * This test case verifies the priority boost of a thread waiting on a + * conditional variable queue. It tests this very specific situation in order + * to complete the code coverage. + */ + +static void mtx8_setup(void) { + + chCondInit(&c1); + chMtxInit(&m1); + chMtxInit(&m2); +} + +static msg_t thread11(void *p) { + + chMtxLock(&m2); + chMtxLock(&m1); +#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) + chCondWaitTimeout(&c1, TIME_INFINITE); +#else + chCondWait(&c1); +#endif + test_emit_token(*(char *)p); + chMtxUnlock(); + chMtxUnlock(); + return 0; +} + +static msg_t thread12(void *p) { + + chMtxLock(&m2); + test_emit_token(*(char *)p); + chMtxUnlock(); + return 0; +} + +static void mtx8_execute(void) { + + tprio_t prio = chThdGetPriority(); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread11, "A"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "C"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread12, "B"); + chCondSignal(&c1); + chCondSignal(&c1); + test_wait_threads(); + test_assert_sequence(1, "ABC"); +} + +ROMCONST struct testcase testmtx8 = { + "CondVar, boost test", + mtx8_setup, + NULL, + mtx8_execute +}; +#endif /* CH_USE_CONDVARS */ +#endif /* CH_USE_MUTEXES */ + +/** + * @brief Test sequence for mutexes. + */ +ROMCONST struct testcase * ROMCONST patternmtx[] = { +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + &testmtx1, +#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) + &testmtx2, + &testmtx3, +#endif + &testmtx4, + &testmtx5, +#if CH_USE_CONDVARS || defined(__DOXYGEN__) + &testmtx6, + &testmtx7, + &testmtx8, +#endif +#endif + NULL +}; diff --git a/test/testmtx.h b/test/testmtx.h new file mode 100644 index 000000000..653c4ad24 --- /dev/null +++ b/test/testmtx.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTMTX_H_ +#define _TESTMTX_H_ + +extern ROMCONST struct testcase * ROMCONST patternmtx[]; + +#endif /* _TESTMTX_H_ */ diff --git a/test/testpools.c b/test/testpools.c new file mode 100644 index 000000000..6515b256f --- /dev/null +++ b/test/testpools.c @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_pools Memory Pools test + * + * File: @ref testpools.c + * + *

    Description

    + * This module implements the test sequence for the @ref pools subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref pools code. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_MEMPOOLS + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_pools_001 + * . + * @file testpools.c + * @brief Memory Pools test source file + * @file testpools.h + * @brief Memory Pools test header file + */ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + +static MEMORYPOOL_DECL(mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); + +/** + * @page test_pools_001 Allocation and enqueuing test + * + *

    Description

    + * Five memory blocks are added to a memory pool then removed.
    + * The test expects to find the pool queue in the proper status after each + * operation. + */ + +static void *null_provider(size_t size) { + + (void)size; + return NULL; +} + +static void pools1_setup(void) { + + chPoolInit(&mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); +} + +static void pools1_execute(void) { + int i; + + /* Adding the WAs to the pool.*/ + chPoolLoadArray(&mp1, wa[0], MAX_THREADS); + + /* Emptying the pool.*/ + for (i = 0; i < MAX_THREADS; i++) + test_assert(1, chPoolAlloc(&mp1) != NULL, "list empty"); + + /* Now must be empty.*/ + test_assert(2, chPoolAlloc(&mp1) == NULL, "list not empty"); + + /* Adding the WAs to the pool, one by one this time.*/ + for (i = 0; i < MAX_THREADS; i++) + chPoolFree(&mp1, wa[i]); + + /* Emptying the pool again.*/ + for (i = 0; i < MAX_THREADS; i++) + test_assert(3, chPoolAlloc(&mp1) != NULL, "list empty"); + + /* Now must be empty again.*/ + test_assert(4, chPoolAlloc(&mp1) == NULL, "list not empty"); + + /* Covering the case where a provider is unable to return more memory.*/ + chPoolInit(&mp1, 16, null_provider); + test_assert(5, chPoolAlloc(&mp1) == NULL, "provider returned memory"); +} + +ROMCONST struct testcase testpools1 = { + "Memory Pools, queue/dequeue", + pools1_setup, + NULL, + pools1_execute +}; + +#endif /* CH_USE_MEMPOOLS */ + +/* + * @brief Test sequence for pools. + */ +ROMCONST struct testcase * ROMCONST patternpools[] = { +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + &testpools1, +#endif + NULL +}; diff --git a/test/testpools.h b/test/testpools.h new file mode 100644 index 000000000..3fe4ed0f6 --- /dev/null +++ b/test/testpools.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTPOOLS_H_ +#define _TESTPOOLS_H_ + +extern ROMCONST struct testcase * ROMCONST patternpools[]; + +#endif /* _TESTPOOLS_H_ */ diff --git a/test/testqueues.c b/test/testqueues.c new file mode 100644 index 000000000..7f682ef8e --- /dev/null +++ b/test/testqueues.c @@ -0,0 +1,244 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_queues I/O Queues test + * + * File: @ref testqueues.c + * + *

    Description

    + * This module implements the test sequence for the @ref io_queues subsystem. + * The tests are performed by inserting and removing data from queues and by + * checking both the queues status and the correct sequence of the extracted + * data. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref io_queues code.
    + * Note that the @ref io_queues subsystem depends on the @ref semaphores + * subsystem that has to met its testing objectives as well. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_QUEUES (and dependent options) + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_queues_001 + * - @subpage test_queues_002 + * . + * @file testqueues.c + * @brief I/O Queues test source file + * @file testqueues.h + * @brief I/O Queues test header file + */ + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + +#define TEST_QUEUES_SIZE 4 + +static void notify(GenericQueue *qp) { + (void)qp; +} + +/* + * Note, the static initializers are not really required because the + * variables are explicitly initialized in each test case. It is done in order + * to test the macros. + */ +static INPUTQUEUE_DECL(iq, test.wa.T0, TEST_QUEUES_SIZE, notify, NULL); +static OUTPUTQUEUE_DECL(oq, test.wa.T1, TEST_QUEUES_SIZE, notify, NULL); + +/** + * @page test_queues_001 Input Queues functionality and APIs + * + *

    Description

    + * This test case tests sysnchronos and asynchronous operations on an + * @p InputQueue object including timeouts. The queue state must remain + * consistent through the whole test. + */ + +static void queues1_setup(void) { + + chIQInit(&iq, wa[0], TEST_QUEUES_SIZE, notify, NULL); +} + +static msg_t thread1(void *p) { + + (void)p; + chIQGetTimeout(&iq, MS2ST(200)); + return 0; +} + +static void queues1_execute(void) { + unsigned i; + size_t n; + + /* Initial empty state */ + test_assert_lock(1, chIQIsEmptyI(&iq), "not empty"); + + /* Queue filling */ + chSysLock(); + for (i = 0; i < TEST_QUEUES_SIZE; i++) + chIQPutI(&iq, 'A' + i); + chSysUnlock(); + test_assert_lock(2, chIQIsFullI(&iq), "still has space"); + test_assert_lock(3, chIQPutI(&iq, 0) == Q_FULL, "failed to report Q_FULL"); + + /* Queue emptying */ + for (i = 0; i < TEST_QUEUES_SIZE; i++) + test_emit_token(chIQGet(&iq)); + test_assert_lock(4, chIQIsEmptyI(&iq), "still full"); + test_assert_sequence(5, "ABCD"); + + /* Queue filling again */ + chSysLock(); + for (i = 0; i < TEST_QUEUES_SIZE; i++) + chIQPutI(&iq, 'A' + i); + chSysUnlock(); + + /* Reading the whole thing */ + n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE * 2, TIME_IMMEDIATE); + test_assert(6, n == TEST_QUEUES_SIZE, "wrong returned size"); + test_assert_lock(7, chIQIsEmptyI(&iq), "still full"); + + /* Queue filling again */ + chSysLock(); + for (i = 0; i < TEST_QUEUES_SIZE; i++) + chIQPutI(&iq, 'A' + i); + chSysUnlock(); + + /* Partial reads */ + n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); + test_assert(8, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); + n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); + test_assert(9, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); + test_assert_lock(10, chIQIsEmptyI(&iq), "still full"); + + /* Testing reset */ + chSysLock(); + chIQPutI(&iq, 0); + chIQResetI(&iq); + chSysUnlock(); + test_assert_lock(11, chIQGetFullI(&iq) == 0, "still full"); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread1, NULL); + test_assert_lock(12, chIQGetFullI(&iq) == 0, "not empty"); + test_wait_threads(); + + /* Timeout */ + test_assert(13, chIQGetTimeout(&iq, 10) == Q_TIMEOUT, "wrong timeout return"); +} + +ROMCONST struct testcase testqueues1 = { + "Queues, input queues", + queues1_setup, + NULL, + queues1_execute +}; + +/** + * @page test_queues_002 Output Queues functionality and APIs + * + *

    Description

    + * This test case tests sysnchronos and asynchronous operations on an + * @p OutputQueue object including timeouts. The queue state must remain + * consistent through the whole test. + */ + +static void queues2_setup(void) { + + chOQInit(&oq, wa[0], TEST_QUEUES_SIZE, notify, NULL); +} + +static msg_t thread2(void *p) { + + (void)p; + chOQPutTimeout(&oq, 0, MS2ST(200)); + return 0; +} + +static void queues2_execute(void) { + unsigned i; + size_t n; + + /* Initial empty state */ + test_assert_lock(1, chOQIsEmptyI(&oq), "not empty"); + + /* Queue filling */ + for (i = 0; i < TEST_QUEUES_SIZE; i++) + chOQPut(&oq, 'A' + i); + test_assert_lock(2, chOQIsFullI(&oq), "still has space"); + + /* Queue emptying */ + for (i = 0; i < TEST_QUEUES_SIZE; i++) { + char c; + + chSysLock(); + c = chOQGetI(&oq); + chSysUnlock(); + test_emit_token(c); + } + test_assert_lock(3, chOQIsEmptyI(&oq), "still full"); + test_assert_sequence(4, "ABCD"); + test_assert_lock(5, chOQGetI(&oq) == Q_EMPTY, "failed to report Q_EMPTY"); + + /* Writing the whole thing */ + n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE * 2, TIME_IMMEDIATE); + test_assert(6, n == TEST_QUEUES_SIZE, "wrong returned size"); + test_assert_lock(7, chOQIsFullI(&oq), "not full"); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread2, NULL); + test_assert_lock(8, chOQGetFullI(&oq) == TEST_QUEUES_SIZE, "not empty"); + test_wait_threads(); + + /* Testing reset */ + chSysLock(); + chOQResetI(&oq); + chSysUnlock(); + test_assert_lock(9, chOQGetFullI(&oq) == 0, "still full"); + + /* Partial writes */ + n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); + test_assert(10, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); + n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); + test_assert(11, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); + test_assert_lock(12, chOQIsFullI(&oq), "not full"); + + /* Timeout */ + test_assert(13, chOQPutTimeout(&oq, 0, 10) == Q_TIMEOUT, "wrong timeout return"); +} + +ROMCONST struct testcase testqueues2 = { + "Queues, output queues", + queues2_setup, + NULL, + queues2_execute +}; +#endif /* CH_USE_QUEUES */ + +/** + * @brief Test sequence for queues. + */ +ROMCONST struct testcase * ROMCONST patternqueues[] = { +#if CH_USE_QUEUES || defined(__DOXYGEN__) + &testqueues1, + &testqueues2, +#endif + NULL +}; diff --git a/test/testqueues.h b/test/testqueues.h new file mode 100644 index 000000000..fdfbc4359 --- /dev/null +++ b/test/testqueues.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTQUEUES_H_ +#define _TESTQUEUES_H_ + +extern ROMCONST struct testcase * ROMCONST patternqueues[]; + +#endif /* _TESTQUEUES_H_ */ diff --git a/test/testsem.c b/test/testsem.c new file mode 100644 index 000000000..d4b990797 --- /dev/null +++ b/test/testsem.c @@ -0,0 +1,302 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_sem Semaphores test + * + * File: @ref testsem.c + * + *

    Description

    + * This module implements the test sequence for the @ref semaphores subsystem. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the @ref semaphores code. + * + *

    Preconditions

    + * The module requires the following kernel options: + * - @p CH_USE_SEMAPHORES + * . + * In case some of the required options are not enabled then some or all tests + * may be skipped. + * + *

    Test Cases

    + * - @subpage test_sem_001 + * - @subpage test_sem_002 + * - @subpage test_sem_003 + * - @subpage test_sem_004 + * . + * @file testsem.c + * @brief Semaphores test source file + * @file testsem.h + * @brief Semaphores test header file + */ + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +#define ALLOWED_DELAY MS2ST(5) + +/* + * Note, the static initializers are not really required because the + * variables are explicitly initialized in each test case. It is done in order + * to test the macros. + */ +static SEMAPHORE_DECL(sem1, 0); + +/** + * @page test_sem_001 Enqueuing test + * + *

    Description

    + * Five threads with randomized priorities are enqueued to a semaphore then + * awakened one at time.
    + * The test expects that the threads reach their goal in FIFO order or + * priority order depending on the CH_USE_SEMAPHORES_PRIORITY configuration + * setting. + */ + +static void sem1_setup(void) { + + chSemInit(&sem1, 0); +} + +static msg_t thread1(void *p) { + + chSemWait(&sem1); + test_emit_token(*(char *)p); + return 0; +} + +static void sem1_execute(void) { + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+5, thread1, "A"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()+1, thread1, "B"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()+3, thread1, "C"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()+4, thread1, "D"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()+2, thread1, "E"); + chSemSignal(&sem1); + chSemSignal(&sem1); + chSemSignal(&sem1); + chSemSignal(&sem1); + chSemSignal(&sem1); + test_wait_threads(); +#if CH_USE_SEMAPHORES_PRIORITY + test_assert_sequence(1, "ADCEB"); +#else + test_assert_sequence(1, "ABCDE"); +#endif + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+5, thread1, "A"); + chSysLock(); + chSemAddCounterI(&sem1, 2); + chSysUnlock(); + test_wait_threads(); + test_assert(2, chSemGetCounterI(&sem1) == 1, "invalid counter"); +} + +ROMCONST struct testcase testsem1 = { + "Semaphores, enqueuing", + sem1_setup, + NULL, + sem1_execute +}; + +/** + * @page test_sem_002 Timeout test + * + *

    Description

    + * The three possible semaphore waiting modes (do not wait, wait with timeout, + * wait without timeout) are explored.
    + * The test expects that the semaphore wait function returns the correct value + * in each of the above scenario and that the semaphore structure status is + * correct after each operation. + */ + +static void sem2_setup(void) { + + chSemInit(&sem1, 0); +} + +static msg_t thread2(void *p) { + + (void)p; + chThdSleepMilliseconds(50); + chSysLock(); + chSemSignalI(&sem1); /* For coverage reasons */ + chSchRescheduleS(); + chSysUnlock(); + return 0; +} + +static void sem2_execute(void) { + int i; + systime_t target_time; + msg_t msg; + + /* + * Testing special case TIME_IMMEDIATE. + */ + msg = chSemWaitTimeout(&sem1, TIME_IMMEDIATE); + test_assert(1, msg == RDY_TIMEOUT, "wrong wake-up message"); + test_assert(2, isempty(&sem1.s_queue), "queue not empty"); + test_assert(3, sem1.s_cnt == 0, "counter not zero"); + + /* + * Testing not timeout condition. + */ + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, + thread2, 0); + msg = chSemWaitTimeout(&sem1, MS2ST(500)); + test_wait_threads(); + test_assert(4, msg == RDY_OK, "wrong wake-up message"); + test_assert(5, isempty(&sem1.s_queue), "queue not empty"); + test_assert(6, sem1.s_cnt == 0, "counter not zero"); + + /* + * Testing timeout condition. + */ + test_wait_tick(); + target_time = chTimeNow() + MS2ST(5 * 500); + for (i = 0; i < 5; i++) { + test_emit_token('A' + i); + msg = chSemWaitTimeout(&sem1, MS2ST(500)); + test_assert(7, msg == RDY_TIMEOUT, "wrong wake-up message"); + test_assert(8, isempty(&sem1.s_queue), "queue not empty"); + test_assert(9, sem1.s_cnt == 0, "counter not zero"); + } + test_assert_sequence(10, "ABCDE"); + test_assert_time_window(11, target_time, target_time + ALLOWED_DELAY); +} + +ROMCONST struct testcase testsem2 = { + "Semaphores, timeout", + sem2_setup, + NULL, + sem2_execute +}; + +#if CH_USE_SEMSW || defined(__DOXYGEN__) +/** + * @page test_sem_003 Atomic signal-wait test + * + *

    Description

    + * This test case explicitly addresses the @p chSemWaitSignal() function. A + * thread is created that performs a wait and a signal operations. + * The tester thread is awakened from an atomic wait/signal operation.
    + * The test expects that the semaphore wait function returns the correct value + * in each of the above scenario and that the semaphore structure status is + * correct after each operation. + */ + +static void sem3_setup(void) { + + chSemInit(&sem1, 0); +} + +static msg_t thread3(void *p) { + + (void)p; + chSemWait(&sem1); + chSemSignal(&sem1); + return 0; +} + +static void sem3_execute(void) { + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread3, 0); + chSemSignalWait(&sem1, &sem1); + test_assert(1, isempty(&sem1.s_queue), "queue not empty"); + test_assert(2, sem1.s_cnt == 0, "counter not zero"); + + chSemSignalWait(&sem1, &sem1); + test_assert(3, isempty(&sem1.s_queue), "queue not empty"); + test_assert(4, sem1.s_cnt == 0, "counter not zero"); +} + +ROMCONST struct testcase testsem3 = { + "Semaphores, atomic signal-wait", + sem3_setup, + NULL, + sem3_execute +}; +#endif /* CH_USE_SEMSW */ + +/** + * @page test_sem_004 Binary Wait and Signal + * + *

    Description

    + * This test case tests the binary semaphores functionality. The test both + * checks the binary semaphore status and the expected status of the underlying + * counting semaphore. + */ +static msg_t thread4(void *p) { + + chBSemSignal((BinarySemaphore *)p); + return 0; +} + +static void sem4_execute(void) { + BinarySemaphore bsem; + + /* Creates a taken binary semaphore.*/ + chBSemInit(&bsem, TRUE); + chBSemReset(&bsem, TRUE); + test_assert(1, chBSemGetStateI(&bsem) == TRUE, "not taken"); + + /* Starts a signaler thread at a lower priority.*/ + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, + chThdGetPriority()-1, thread4, &bsem); + + /* Waits to be signaled.*/ + chBSemWait(&bsem); + + /* The binary semaphore is expected to be taken.*/ + test_assert(2, chBSemGetStateI(&bsem) == TRUE, "not taken"); + + /* Releasing it, check both the binary semaphore state and the underlying + counter semaphore state..*/ + chBSemSignal(&bsem); + test_assert(3, chBSemGetStateI(&bsem) == FALSE, "still taken"); + test_assert(4, chSemGetCounterI(&bsem.bs_sem) == 1, "unexpected counter"); + + /* Checking signaling overflow, the counter must not go beyond 1.*/ + chBSemSignal(&bsem); + test_assert(3, chBSemGetStateI(&bsem) == FALSE, "taken"); + test_assert(5, chSemGetCounterI(&bsem.bs_sem) == 1, "unexpected counter"); +} + +ROMCONST struct testcase testsem4 = { + "Binary Semaphores, functionality", + NULL, + NULL, + sem4_execute +}; +#endif /* CH_USE_SEMAPHORES */ + +/** + * @brief Test sequence for semaphores. + */ +ROMCONST struct testcase * ROMCONST patternsem[] = { +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + &testsem1, + &testsem2, +#if CH_USE_SEMSW || defined(__DOXYGEN__) + &testsem3, +#endif + &testsem4, +#endif + NULL +}; diff --git a/test/testsem.h b/test/testsem.h new file mode 100644 index 000000000..94a8bfca8 --- /dev/null +++ b/test/testsem.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTSEM_H_ +#define _TESTSEM_H_ + +extern ROMCONST struct testcase * ROMCONST patternsem[]; + +#endif /* _TESTSEM_H_ */ diff --git a/test/testthd.c b/test/testthd.c new file mode 100644 index 000000000..35b413acf --- /dev/null +++ b/test/testthd.c @@ -0,0 +1,231 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "test.h" + +/** + * @page test_threads Threads and Scheduler test + * + * File: @ref testthd.c + * + *

    Description

    + * This module implements the test sequence for the @ref scheduler, + * @ref threads and @ref time subsystems.
    + * Note that the tests on those subsystems are formally required but most of + * their functionality is already demonstrated because the test suite itself + * depends on them, anyway double check is good. + * + *

    Objective

    + * Objective of the test module is to cover 100% of the subsystems code. + * + *

    Preconditions

    + * None. + * + *

    Test Cases

    + * - @subpage test_threads_001 + * - @subpage test_threads_002 + * - @subpage test_threads_003 + * - @subpage test_threads_004 + * . + * @file testthd.c + * @brief Threads and Scheduler test source file + * @file testthd.h + * @brief Threads and Scheduler test header file + */ + +/** + * @page test_threads_001 Ready List functionality #1 + * + *

    Description

    + * Five threads, with increasing priority, are enqueued in the ready list + * and atomically executed.
    + * The test expects the threads to perform their operations in increasing + * priority order regardless of the initial order. + */ + +static msg_t thread(void *p) { + + test_emit_token(*(char *)p); + return 0; +} + +static void thd1_execute(void) { + + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread, "E"); + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread, "D"); + threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread, "C"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread, "B"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread, "A"); + test_wait_threads(); + test_assert_sequence(1, "ABCDE"); +} + +ROMCONST struct testcase testthd1 = { + "Threads, enqueuing test #1", + NULL, + NULL, + thd1_execute +}; + +/** + * @page test_threads_002 Ready List functionality #2 + * + *

    Description

    + * Five threads, with pseudo-random priority, are enqueued in the ready list + * and atomically executed.
    + * The test expects the threads to perform their operations in increasing + * priority order regardless of the initial order. + */ + +static void thd2_execute(void) { + + threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread, "D"); + threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread, "E"); + threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread, "A"); + threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread, "B"); + /* Done this way for coverage of chThdCreateI() and chThdResume().*/ + chSysLock(); + threads[2] = chThdCreateI(wa[2], WA_SIZE, chThdGetPriority()-3, thread, "C"); + chSysUnlock(); + chThdResume(threads[2]); + test_wait_threads(); + test_assert_sequence(1, "ABCDE"); +} + +ROMCONST struct testcase testthd2 = { + "Threads, enqueuing test #2", + NULL, + NULL, + thd2_execute +}; + +/** + * @page test_threads_003 Threads priority change test + * + *

    Description

    + * A series of priority changes are performed on the current thread in order + * to verify that the priority change happens as expected.
    + * If the @p CH_USE_MUTEXES option is enabled then the priority changes are + * also tested under priority inheritance boosted priority state. + */ + +static void thd3_execute(void) { + tprio_t prio, p1; + + prio = chThdGetPriority(); + p1 = chThdSetPriority(prio + 1); + test_assert(1, p1 == prio, + "unexpected returned priority level"); + test_assert(2, chThdGetPriority() == prio + 1, + "unexpected priority level"); + p1 = chThdSetPriority(p1); + test_assert(3, p1 == prio + 1, + "unexpected returned priority level"); + test_assert(4, chThdGetPriority() == prio, + "unexpected priority level"); + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /* Simulates a priority boost situation (p_prio > p_realprio).*/ + chSysLock(); + chThdSelf()->p_prio += 2; + chSysUnlock(); + test_assert(5, chThdGetPriority() == prio + 2, + "unexpected priority level"); + + /* Tries to raise but below the boost level. */ + p1 = chThdSetPriority(prio + 1); + test_assert(6, p1 == prio, + "unexpected returned priority level"); + test_assert(7, chThdSelf()->p_prio == prio + 2, + "unexpected priority level"); + test_assert(8, chThdSelf()->p_realprio == prio + 1, + "unexpected returned real priority level"); + + /* Tries to raise above the boost level. */ + p1 = chThdSetPriority(prio + 3); + test_assert(9, p1 == prio + 1, + "unexpected returned priority level"); + test_assert(10, chThdSelf()->p_prio == prio + 3, + "unexpected priority level"); + test_assert(11, chThdSelf()->p_realprio == prio + 3, + "unexpected real priority level"); + + chSysLock(); + chThdSelf()->p_prio = prio; + chThdSelf()->p_realprio = prio; + chSysUnlock(); +#endif +} + +ROMCONST struct testcase testthd3 = { + "Threads, priority change", + NULL, + NULL, + thd3_execute +}; + +/** + * @page test_threads_004 Threads delays test + * + *

    Description

    + * Delay APIs and associated macros are tested, the invoking thread is verified + * to wake up at the exact expected time. + */ + +static void thd4_execute(void) { + systime_t time; + + test_wait_tick(); + + /* Timeouts in microseconds.*/ + time = chTimeNow(); + chThdSleepMicroseconds(100000); + test_assert_time_window(1, time + US2ST(100000), time + US2ST(100000) + 1); + + /* Timeouts in milliseconds.*/ + time = chTimeNow(); + chThdSleepMilliseconds(100); + test_assert_time_window(2, time + MS2ST(100), time + MS2ST(100) + 1); + + /* Timeouts in seconds.*/ + time = chTimeNow(); + chThdSleepSeconds(1); + test_assert_time_window(3, time + S2ST(1), time + S2ST(1) + 1); + + /* Absolute timelines.*/ + time = chTimeNow() + MS2ST(100); + chThdSleepUntil(time); + test_assert_time_window(4, time, time + 1); +} + +ROMCONST struct testcase testthd4 = { + "Threads, delays", + NULL, + NULL, + thd4_execute +}; + +/** + * @brief Test sequence for threads. + */ +ROMCONST struct testcase * ROMCONST patternthd[] = { + &testthd1, + &testthd2, + &testthd3, + &testthd4, + NULL +}; diff --git a/test/testthd.h b/test/testthd.h new file mode 100644 index 000000000..f1e3a9475 --- /dev/null +++ b/test/testthd.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _TESTRDY_H_ +#define _TESTRDY_H_ + +extern ROMCONST struct testcase * ROMCONST patternthd[]; + +#endif /* _TESTRDY_H_ */ diff --git a/testhal/LPC11xx/EXT/Makefile b/testhal/LPC11xx/EXT/Makefile new file mode 100644 index 000000000..2ad18e131 --- /dev/null +++ b/testhal/LPC11xx/EXT/Makefile @@ -0,0 +1,194 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_11C24/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC11C24.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC11xx/EXT/chconf.h b/testhal/LPC11xx/EXT/chconf.h new file mode 100644 index 000000000..fe07600ff --- /dev/null +++ b/testhal/LPC11xx/EXT/chconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/EXT/halconf.h b/testhal/LPC11xx/EXT/halconf.h new file mode 100644 index 000000000..06b4df2cc --- /dev/null +++ b/testhal/LPC11xx/EXT/halconf.h @@ -0,0 +1,314 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/EXT/main.c b/testhal/LPC11xx/EXT/main.c new file mode 100644 index 000000000..bb2ef5aa6 --- /dev/null +++ b/testhal/LPC11xx/EXT/main.c @@ -0,0 +1,92 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + EXT haltest - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void ledoff(void *arg) { + + (void)arg; + palClearPad(GPIO0, GPIO0_LED); +} + +/* Triggered when the button is pressed or released. The LED is set to ON.*/ +static void ext_cb0(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palSetPad(GPIO0, GPIO0_LED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, ext_cb0}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 0. + */ + extStart(&EXTD0, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD0, GPIO0_SW_ISP); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD0, GPIO0_SW_ISP); + } +} diff --git a/testhal/LPC11xx/EXT/mcuconf.h b/testhal/LPC11xx/EXT/mcuconf.h new file mode 100644 index 000000000..b5493dbb7 --- /dev/null +++ b/testhal/LPC11xx/EXT/mcuconf.h @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC11xx_SYSPLL_MUL 4 +#define LPC11xx_SYSPLL_DIV 4 +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC11xx_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC11xx_GPT_USE_CT16B0 FALSE +#define LPC11xx_GPT_USE_CT16B1 FALSE +#define LPC11xx_GPT_USE_CT32B0 FALSE +#define LPC11xx_GPT_USE_CT32B1 FALSE +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 1 +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 3 +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC11xx_SERIAL_USE_UART0 TRUE +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC11xx_SPI_USE_SSP0 TRUE +#define LPC11xx_SPI_USE_SSP1 FALSE +#define LPC11xx_SPI_SSP0CLKDIV 1 +#define LPC11xx_SPI_SSP1CLKDIV 1 +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 + +/* + * EXT driver system settings. + */ +#define LPC11xx_EXT_USE_EXT0 TRUE +#define LPC11xx_EXT_USE_EXT1 FALSE +#define LPC11xx_EXT_USE_EXT2 FALSE +#define LPC11xx_EXT_USE_EXT3 FALSE +#define LPC11xx_EXT_EXTI0_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI1_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI2_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI3_IRQ_PRIORITY 3 + +/* + * I2C driver system settings. + */ +#define LPC11xx_I2C_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define LPC11xx_PWM_USE_CT16B0 FALSE +#define LPC11xx_PWM_USE_CT16B1 TRUE +#define LPC11xx_PWM_USE_CT32B0 FALSE +#define LPC11xx_PWM_USE_CT32B1 FALSE +#define LPC11xx_PWM_USE_CT16B0_CH0 FALSE +#define LPC11xx_PWM_USE_CT16B0_CH1 FALSE +#define LPC11xx_PWM_USE_CT16B1_CH0 TRUE +#define LPC11xx_PWM_USE_CT16B1_CH1 TRUE +#define LPC11xx_PWM_USE_CT32B0_CH0 FALSE +#define LPC11xx_PWM_USE_CT32B0_CH1 FALSE +#define LPC11xx_PWM_USE_CT32B1_CH0 FALSE +#define LPC11xx_PWM_USE_CT32B1_CH1 FALSE +#define LPC11xx_PWM_CT16B0_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT16B1_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT32B0_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT32B1_IRQ_PRIORITY 3 diff --git a/testhal/LPC11xx/IRQ_STORM/Makefile b/testhal/LPC11xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..2dd75ef71 --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1114.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC11xx/IRQ_STORM/chconf.h b/testhal/LPC11xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/IRQ_STORM/halconf.h b/testhal/LPC11xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..d91a792b4 --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/IRQ_STORM/main.c b/testhal/LPC11xx/IRQ_STORM/main.c new file mode 100644 index 000000000..9930abfb1 --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/main.c @@ -0,0 +1,324 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIO0, GPIO0_LED2); + } + } + } +} + +/* + * GPT1 callback. + */ +static void gpt1cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT1 configuration. + */ +static const GPTConfig gpt1cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt1cb /* Timer callback.*/ +}; + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 1 and 2. + */ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + gptStart(&GPTD1, &gpt1cfg); + gptStart(&GPTD2, &gpt2cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(LPC11xx_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD2, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/LPC11xx/IRQ_STORM/mcuconf.h b/testhal/LPC11xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..6db2e6fd2 --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC11xx_SYSPLL_MUL 4 +#define LPC11xx_SYSPLL_DIV 4 +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC11xx_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC11xx_GPT_USE_CT16B0 TRUE +#define LPC11xx_GPT_USE_CT16B1 TRUE +#define LPC11xx_GPT_USE_CT32B0 TRUE +#define LPC11xx_GPT_USE_CT32B1 TRUE +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 1 +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 3 +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC11xx_SERIAL_USE_UART0 TRUE +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC11xx_SPI_USE_SSP0 TRUE +#define LPC11xx_SPI_USE_SSP1 FALSE +#define LPC11xx_SPI_SSP0CLKDIV 1 +#define LPC11xx_SPI_SSP1CLKDIV 1 +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 diff --git a/testhal/LPC11xx/IRQ_STORM/readme.txt b/testhal/LPC11xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..aa22b8f39 --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ-STORM demo for LPC11xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an LPCXpresso LPC1114 board. + +** The Demo ** + +The application demonstrates the use of the LPC11xx GPT, PAL and Serial drivers +in order to implement a system stress demo. + +** Build Procedure ** + +The demo has been tested using the free LPCXpresso toolchain but also with +Codesourcery and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +NXP and are licensed under a different license. + + http://www.nxp.com diff --git a/testhal/LPC11xx/PWM/Makefile b/testhal/LPC11xx/PWM/Makefile new file mode 100644 index 000000000..2ad18e131 --- /dev/null +++ b/testhal/LPC11xx/PWM/Makefile @@ -0,0 +1,194 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_11C24/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC11C24.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC11xx/PWM/chconf.h b/testhal/LPC11xx/PWM/chconf.h new file mode 100644 index 000000000..feb364424 --- /dev/null +++ b/testhal/LPC11xx/PWM/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/PWM/halconf.h b/testhal/LPC11xx/PWM/halconf.h new file mode 100644 index 000000000..78b61cf6a --- /dev/null +++ b/testhal/LPC11xx/PWM/halconf.h @@ -0,0 +1,314 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC11xx/PWM/main.c b/testhal/LPC11xx/PWM/main.c new file mode 100644 index 000000000..1ce05966f --- /dev/null +++ b/testhal/LPC11xx/PWM/main.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwm2pcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIO0, GPIO0_LED); +} + +static void pwm2c0cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIO0, GPIO0_LED); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 1000, /* Initial PWM period 4,8us */ + pwm2pcb, + { + {PWM_OUTPUT_ACTIVE_LOW, pwm2c0cb}, + {PWM_OUTPUT_ACTIVE_LOW, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2. + */ + pwmStart(&PWMD2, &pwmcfg); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 1 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 250); + pwmEnableChannel(&PWMD2, 1, 250); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 1 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 500); + pwmEnableChannel(&PWMD2, 1, 500); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 250); + pwmEnableChannel(&PWMD2, 1, 250); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 500); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 1. + */ + pwmDisableChannel(&PWMD2, 1); + chThdSleepMilliseconds(5000); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/LPC11xx/PWM/mcuconf.h b/testhal/LPC11xx/PWM/mcuconf.h new file mode 100644 index 000000000..21f8c6693 --- /dev/null +++ b/testhal/LPC11xx/PWM/mcuconf.h @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel + - Copyright (C) 2013 mike brown + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC11xx_SYSPLL_MUL 4 +#define LPC11xx_SYSPLL_DIV 4 +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC11xx_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC11xx_GPT_USE_CT16B0 FALSE +#define LPC11xx_GPT_USE_CT16B1 FALSE +#define LPC11xx_GPT_USE_CT32B0 FALSE +#define LPC11xx_GPT_USE_CT32B1 FALSE +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 1 +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 3 +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC11xx_SERIAL_USE_UART0 TRUE +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC11xx_SPI_USE_SSP0 TRUE +#define LPC11xx_SPI_USE_SSP1 FALSE +#define LPC11xx_SPI_SSP0CLKDIV 1 +#define LPC11xx_SPI_SSP1CLKDIV 1 +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 + +/* + * EXT driver system settings. + */ +#define LPC11xx_EXT_USE_EXT0 FALSE +#define LPC11xx_EXT_USE_EXT1 FALSE +#define LPC11xx_EXT_USE_EXT2 FALSE +#define LPC11xx_EXT_USE_EXT3 FALSE +#define LPC11xx_EXT_EXTI0_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI1_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI2_IRQ_PRIORITY 3 +#define LPC11xx_EXT_EXTI3_IRQ_PRIORITY 3 + +/* + * I2C driver system settings. + */ +#define LPC11xx_I2C_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define LPC11xx_PWM_USE_CT16B0 FALSE +#define LPC11xx_PWM_USE_CT16B1 TRUE +#define LPC11xx_PWM_USE_CT32B0 FALSE +#define LPC11xx_PWM_USE_CT32B1 FALSE +#define LPC11xx_PWM_USE_CT16B0_CH0 FALSE +#define LPC11xx_PWM_USE_CT16B0_CH1 FALSE +#define LPC11xx_PWM_USE_CT16B1_CH0 TRUE +#define LPC11xx_PWM_USE_CT16B1_CH1 TRUE +#define LPC11xx_PWM_USE_CT32B0_CH0 FALSE +#define LPC11xx_PWM_USE_CT32B0_CH1 FALSE +#define LPC11xx_PWM_USE_CT32B1_CH0 FALSE +#define LPC11xx_PWM_USE_CT32B1_CH1 FALSE +#define LPC11xx_PWM_CT16B0_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT16B1_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT32B0_IRQ_PRIORITY 3 +#define LPC11xx_PWM_CT32B1_IRQ_PRIORITY 3 diff --git a/testhal/LPC122x/EXT/Makefile b/testhal/LPC122x/EXT/Makefile new file mode 100644 index 000000000..507fe3f00 --- /dev/null +++ b/testhal/LPC122x/EXT/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_LPC-P1227/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC122x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1227.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1227 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC122x/EXT/chconf.h b/testhal/LPC122x/EXT/chconf.h new file mode 100644 index 000000000..04ff997d1 --- /dev/null +++ b/testhal/LPC122x/EXT/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/EXT/halconf.h b/testhal/LPC122x/EXT/halconf.h new file mode 100644 index 000000000..8cb1fcc41 --- /dev/null +++ b/testhal/LPC122x/EXT/halconf.h @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/EXT/main.c b/testhal/LPC122x/EXT/main.c new file mode 100644 index 000000000..76cafce0e --- /dev/null +++ b/testhal/LPC122x/EXT/main.c @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led1off(void *arg) { + + (void)arg; + palSetPad(GPIO1, GPIO1_LED1); +} + +/* Triggered when the button is pressed or released. The LED1 is set to ON.*/ +static void ext2cb12(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palClearPad(GPIO1, GPIO1_LED1); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED1 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led1off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, ext2cb12}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD2, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD2, GPIO2_SW_USER1); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD2, GPIO2_SW_USER1); + } +} diff --git a/testhal/LPC122x/EXT/mcuconf.h b/testhal/LPC122x/EXT/mcuconf.h new file mode 100644 index 000000000..608abf226 --- /dev/null +++ b/testhal/LPC122x/EXT/mcuconf.h @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1227 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC122x_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC122x_SYSPLL_MUL 3 +#define LPC122x_SYSPLL_DIV 8 +#define LPC122x_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC122x_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC122x_GPT_USE_CT16B0 TRUE +#define LPC122x_GPT_USE_CT16B1 TRUE +#define LPC122x_GPT_USE_CT32B0 TRUE +#define LPC122x_GPT_USE_CT32B1 TRUE +#define LPC122x_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC122x_SERIAL_USE_UART0 TRUE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART0CLKDIV 1 +#define LPC122x_SERIAL_UART0_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_TXD0_SELECTOR TXD0_IS_PIO0_2 +#define LPC122x_SERIAL_RXD0_SELECTOR RXD0_IS_PIO0_1 + +#define LPC122x_SERIAL_USE_UART1 FALSE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART1CLKDIV 1 +#define LPC122x_SERIAL_UART1_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_RXD1_SELECTOR RXD1_IS_PIO0_8 +#define LPC122x_SERIAL_TXD1_SELECTOR TXD1_IS_PIO0_9 + +/* + * SPI driver system settings. + */ +#define LPC122x_SPI_USE_SSP0 TRUE +#define LPC122x_SPI_SSP0CLKDIV 1 +#define LPC122x_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC122x_SPI_SSP_ERROR_HOOK(spip) chSysHalt() + +/* + * EXT driver system settings. + */ +#define LPC122x_EXT_USE_EXT0 FALSE +#define LPC122x_EXT_USE_EXT1 FALSE +#define LPC122x_EXT_USE_EXT2 TRUE +#define LPC122x_EXT_EXTI0_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI1_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI2_IRQ_PRIORITY 3 + +/* + * RTC driver system settings. + */ +#define LPC122x_RTCCLK SYSCFG_RTCCLK_1Hz +#define LPC122x_RTC_CLKDIV 0 +#define LPC122x_RTC_USE_ALARM TRUE +#define LPC122x_RTC_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define LPC122x_PWM_USE_CT16B0 FALSE +#define LPC122x_PWM_USE_CT16B1 TRUE +#define LPC122x_PWM_USE_CT32B0 FALSE +#define LPC122x_PWM_USE_CT32B1 FALSE +#define LPC122x_PWM_USE_CT16B0_CH0 FALSE +#define LPC122x_PWM_USE_CT16B0_CH1 FALSE +#define LPC122x_PWM_USE_CT16B1_CH0 TRUE +#define LPC122x_PWM_USE_CT16B1_CH1 TRUE +#define LPC122x_PWM_USE_CT32B0_CH0 FALSE +#define LPC122x_PWM_USE_CT32B0_CH1 FALSE +#define LPC122x_PWM_USE_CT32B1_CH0 FALSE +#define LPC122x_PWM_USE_CT32B1_CH1 FALSE +#define LPC122x_PWM_CT16B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B0_CH0_SELECTOR PWM_CT16B0_CH0_IS_PIO0_28 +#define LPC122x_PWM_CT16B0_CH1_SELECTOR PWM_CT16B0_CH1_IS_PIO0_29 +#define LPC122x_PWM_CT16B1_CH0_SELECTOR PWM_CT16B1_CH0_IS_PIO1_5 +#define LPC122x_PWM_CT16B1_CH1_SELECTOR PWM_CT16B1_CH1_IS_PIO1_6 +#define LPC122x_PWM_CT32B0_CH0_SELECTOR PWM_CT32B0_CH0_IS_PIO2_4 +#define LPC122x_PWM_CT32B0_CH1_SELECTOR PWM_CT32B0_CH1_IS_PIO0_2 +#define LPC122x_PWM_CT32B1_CH0_SELECTOR PWM_CT32B1_CH0_IS_PIO0_6 +#define LPC122x_PWM_CT32B1_CH1_SELECTOR PWM_CT32B1_CH1_IS_PIO0_7 + +/* + * I2C driver system settings. + */ +#define LPC122x_I2C_IRQ_PRIORITY 3 diff --git a/testhal/LPC122x/IRQ_STORM/Makefile b/testhal/LPC122x/IRQ_STORM/Makefile new file mode 100644 index 000000000..507fe3f00 --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_LPC-P1227/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC122x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1227.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1227 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC122x/IRQ_STORM/chconf.h b/testhal/LPC122x/IRQ_STORM/chconf.h new file mode 100644 index 000000000..01463a470 --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + LPC122x - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/IRQ_STORM/halconf.h b/testhal/LPC122x/IRQ_STORM/halconf.h new file mode 100644 index 000000000..1f2b374a7 --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + LPC122x - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/IRQ_STORM/main.c b/testhal/LPC122x/IRQ_STORM/main.c new file mode 100644 index 000000000..ac1c51945 --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/main.c @@ -0,0 +1,324 @@ +/* + LPC122x - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIO1, GPIO1_LED1); + } + } + } +} + +/* + * GPT1 callback. + */ +static void gpt1cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT1 configuration. + */ +static const GPTConfig gpt1cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt1cb /* Timer callback.*/ +}; + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 1 and 2. + */ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + gptStart(&GPTD1, &gpt1cfg); + gptStart(&GPTD2, &gpt2cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(LPC122x_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD2, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/LPC122x/IRQ_STORM/mcuconf.h b/testhal/LPC122x/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..4aa37b83c --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/mcuconf.h @@ -0,0 +1,84 @@ +/* + LPC122x - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1227 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC122x_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC122x_SYSPLL_MUL 3 +#define LPC122x_SYSPLL_DIV 8 +#define LPC122x_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC122x_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC122x_GPT_USE_CT16B0 TRUE +#define LPC122x_GPT_USE_CT16B1 TRUE +#define LPC122x_GPT_USE_CT32B0 TRUE +#define LPC122x_GPT_USE_CT32B1 TRUE +#define LPC122x_GPT_CT16B0_IRQ_PRIORITY 1 +#define LPC122x_GPT_CT16B1_IRQ_PRIORITY 3 +#define LPC122x_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC122x_SERIAL_USE_UART0 TRUE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART0CLKDIV 1 +#define LPC122x_SERIAL_UART0_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_TXD0_SELECTOR TXD0_IS_PIO0_2 +#define LPC122x_SERIAL_RXD0_SELECTOR RXD0_IS_PIO0_1 + +#define LPC122x_SERIAL_USE_UART1 FALSE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART1CLKDIV 1 +#define LPC122x_SERIAL_UART1_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_RXD1_SELECTOR RXD1_IS_PIO0_8 +#define LPC122x_SERIAL_TXD1_SELECTOR TXD1_IS_PIO0_9 + +/* + * SPI driver system settings. + */ +#define LPC122x_SPI_USE_SSP0 TRUE +#define LPC122x_SPI_SSP0CLKDIV 1 +#define LPC122x_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC122x_SPI_SSP_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/LPC122x/IRQ_STORM/readme.txt b/testhal/LPC122x/IRQ_STORM/readme.txt new file mode 100644 index 000000000..58f143f05 --- /dev/null +++ b/testhal/LPC122x/IRQ_STORM/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ-STORM demo for LPC122x. ** +***************************************************************************** + +** TARGET ** + +The demo will on an LPCXpresso LPC1114 board. + +** The Demo ** + +The application demonstrates the use of the LPC11xx GPT, PAL and Serial drivers +in order to implement a system stress demo. + +** Build Procedure ** + +The demo has been tested using the free LPCXpresso toolchain but also with +Codesourcery and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +NXP and are licensed under a different license. + + http://www.nxp.com diff --git a/testhal/LPC122x/PWM/Makefile b/testhal/LPC122x/PWM/Makefile new file mode 100644 index 000000000..16eff2811 --- /dev/null +++ b/testhal/LPC122x/PWM/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_LPC-P1227/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC122x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1227.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1227 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC122x/PWM/chconf.h b/testhal/LPC122x/PWM/chconf.h new file mode 100644 index 000000000..b5126732f --- /dev/null +++ b/testhal/LPC122x/PWM/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/PWM/halconf.h b/testhal/LPC122x/PWM/halconf.h new file mode 100644 index 000000000..945da9669 --- /dev/null +++ b/testhal/LPC122x/PWM/halconf.h @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/PWM/main.c b/testhal/LPC122x/PWM/main.c new file mode 100644 index 000000000..eb8abb951 --- /dev/null +++ b/testhal/LPC122x/PWM/main.c @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwm2pcb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIO1, GPIO1_LED2); +} + +static void pwm2c0cb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIO1, GPIO1_LED2); +} + +static PWMConfig pwmcfg = { + 10000, /* 100kHz PWM clock frequency. */ + 1000, /* PWM 10 Hz */ + pwm2pcb, + { + {PWM_OUTPUT_ACTIVE_LOW, pwm2c0cb}, + {PWM_OUTPUT_ACTIVE_LOW, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2. + */ + pwmStart(&PWMD2, &pwmcfg); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 1 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 250); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 1 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 500); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, 250); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 500); + chThdSleepMilliseconds(5000); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/LPC122x/PWM/mcuconf.h b/testhal/LPC122x/PWM/mcuconf.h new file mode 100644 index 000000000..b4a308c7a --- /dev/null +++ b/testhal/LPC122x/PWM/mcuconf.h @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1227 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC122x_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC122x_SYSPLL_MUL 3 +#define LPC122x_SYSPLL_DIV 8 +#define LPC122x_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC122x_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC122x_GPT_USE_CT16B0 TRUE +#define LPC122x_GPT_USE_CT16B1 TRUE +#define LPC122x_GPT_USE_CT32B0 TRUE +#define LPC122x_GPT_USE_CT32B1 TRUE +#define LPC122x_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC122x_SERIAL_USE_UART0 TRUE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART0CLKDIV 1 +#define LPC122x_SERIAL_UART0_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_TXD0_SELECTOR TXD0_IS_PIO0_2 +#define LPC122x_SERIAL_RXD0_SELECTOR RXD0_IS_PIO0_1 + +#define LPC122x_SERIAL_USE_UART1 FALSE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART1CLKDIV 1 +#define LPC122x_SERIAL_UART1_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_RXD1_SELECTOR RXD1_IS_PIO0_8 +#define LPC122x_SERIAL_TXD1_SELECTOR TXD1_IS_PIO0_9 + +/* + * SPI driver system settings. + */ +#define LPC122x_SPI_USE_SSP0 TRUE +#define LPC122x_SPI_SSP0CLKDIV 1 +#define LPC122x_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC122x_SPI_SSP_ERROR_HOOK(spip) chSysHalt() + +/* + * EXT driver system settings. + */ +#define LPC122x_EXT_USE_EXT0 FALSE +#define LPC122x_EXT_USE_EXT1 FALSE +#define LPC122x_EXT_USE_EXT2 TRUE +#define LPC122x_EXT_EXTI0_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI1_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI2_IRQ_PRIORITY 3 + +/* + * RTC driver system settings. + */ +#define LPC122x_RTCCLK SYSCFG_RTCCLK_1Hz +#define LPC122x_RTC_CLKDIV 0 +#define LPC122x_RTC_USE_ALARM TRUE +#define LPC122x_RTC_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define LPC122x_PWM_USE_CT16B0 FALSE +#define LPC122x_PWM_USE_CT16B1 TRUE +#define LPC122x_PWM_USE_CT32B0 FALSE +#define LPC122x_PWM_USE_CT32B1 FALSE +#define LPC122x_PWM_USE_CT16B0_CH0 FALSE +#define LPC122x_PWM_USE_CT16B0_CH1 FALSE +#define LPC122x_PWM_USE_CT16B1_CH0 TRUE +#define LPC122x_PWM_USE_CT16B1_CH1 TRUE +#define LPC122x_PWM_USE_CT32B0_CH0 FALSE +#define LPC122x_PWM_USE_CT32B0_CH1 FALSE +#define LPC122x_PWM_USE_CT32B1_CH0 FALSE +#define LPC122x_PWM_USE_CT32B1_CH1 FALSE +#define LPC122x_PWM_CT16B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B0_CH0_SELECTOR PWM_CT16B0_CH0_IS_PIO0_28 +#define LPC122x_PWM_CT16B0_CH1_SELECTOR PWM_CT16B0_CH1_IS_PIO0_29 +#define LPC122x_PWM_CT16B1_CH0_SELECTOR PWM_CT16B1_CH0_IS_PIO2_2 +#define LPC122x_PWM_CT16B1_CH1_SELECTOR PWM_CT16B1_CH1_IS_PIO1_6 +#define LPC122x_PWM_CT32B0_CH0_SELECTOR PWM_CT32B0_CH0_IS_PIO2_4 +#define LPC122x_PWM_CT32B0_CH1_SELECTOR PWM_CT32B0_CH1_IS_PIO0_2 +#define LPC122x_PWM_CT32B1_CH0_SELECTOR PWM_CT32B1_CH0_IS_PIO0_6 +#define LPC122x_PWM_CT32B1_CH1_SELECTOR PWM_CT32B1_CH1_IS_PIO0_7 + +/* + * I2C driver system settings. + */ +#define LPC122x_I2C_IRQ_PRIORITY 3 diff --git a/testhal/LPC122x/RTC/Makefile b/testhal/LPC122x/RTC/Makefile new file mode 100644 index 000000000..7b0b90b17 --- /dev/null +++ b/testhal/LPC122x/RTC/Makefile @@ -0,0 +1,199 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_LPC-P1227/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC122x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1227.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/chrtclib.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC122X -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC122x/RTC/chconf.h b/testhal/LPC122x/RTC/chconf.h new file mode 100644 index 000000000..120d2b7d5 --- /dev/null +++ b/testhal/LPC122x/RTC/chconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/RTC/halconf.h b/testhal/LPC122x/RTC/halconf.h new file mode 100644 index 000000000..b9195a6dc --- /dev/null +++ b/testhal/LPC122x/RTC/halconf.h @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC122x/RTC/main.c b/testhal/LPC122x/RTC/main.c new file mode 100644 index 000000000..c9cf9dab0 --- /dev/null +++ b/testhal/LPC122x/RTC/main.c @@ -0,0 +1,286 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* +This structure is used to hold the values representing a calendar time. +It contains the following members, with the meanings as shown. + +int tm_sec seconds after minute [0-61] (61 allows for 2 leap-seconds) +int tm_min minutes after hour [0-59] +int tm_hour hours after midnight [0-23] +int tm_mday day of the month [1-31] +int tm_mon month of year [0-11] +int tm_year current year-1900 +int tm_wday days since Sunday [0-6] +int tm_yday days since January 1st [0-365] +int tm_isdst daylight savings indicator (1 = yes, 0 = no, -1 = unknown) +*/ + +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" +#include "chrtclib.h" + +static RTCAlarm alarmspec; +static time_t unix_time; + +/* libc stub */ +int _getpid(void) {return 1;} +/* libc stub */ +void _exit(int i) {(void)i;} +/* libc stub */ +#include +#undef errno +extern int errno; +int _kill(int pid, int sig) { + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + + +/* sleep indicator thread */ +static WORKING_AREA(blinkWA, 128); +static msg_t blink_thd(void *arg){ + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(100); + palTogglePad(GPIO1, GPIO1_LED1); + } + return 0; +} + +static void wakeup_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + if (event == RTC_EVENT_ALARM) { + palTogglePad(GPIO1, GPIO1_LED2); + } +} + +/* Wake-up from Deep-sleep mode with rtc alarm (must be set first) */ +static void func_sleep(void) { + + chSysLock(); + + /* Deep sleep-mode configuration */ + LPC_PMU->PCON = 0; /* DPDEN bit set to 0 */ + LPC_SYSCON->PDSLEEPCFG = 0x0000FFBF; /* BOD off, wdt osc on */ + LPC_SYSCON->PDAWAKECFG &= ~(1 << 6); /* WDT osc powered after woke */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep mode */ + + /* WDT osc config and run */ + LPC_SYSCON->PDRUNCFG |= (1 << 6); /* WDT oscillator power-down */ + LPC_SYSCON->WDTOSCCTRL = (0x01 << 5 ) | 0; /* wdt_osc_clk = Fclkana/(2 * (1 + DIVSEL)) */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* WDT oscillator power-up */ + __NOP(); + + /* Set WDT osc as Main Clock*/ + LPC_SYSCON->MAINCLKSEL = SYSMAINCLKSEL_WDGOSC; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* Set RTC start logic */ + LPC_SYSCON->STARTAPRP1 = (1UL << 18); /* Rising edge */ + LPC_SYSCON->STARTERP1 = (1UL << 18); /* Enable Start Logic for RTC interrupt */ + + __WFI(); + + NVIC_SystemReset(); +} + +/* Wake-up from Deep power-down with wake-up pin or rtc alarm (must be set first) */ +static void func_pwrdown(void) { + + chSysLock(); + + LPC_PMU->PCON |= (1UL << 1); /* DPDEN bit set to 1. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep mode. */ + LPC_SYSCON->PDRUNCFG &= ~((1UL << 1) | 1UL); /* IRC osc powered. */ + + __WFI(); +} + +static void cmd_pwrdown(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argv; + + if (argc > 0) { + chprintf(chp, "Usage: pwrdown\r\n"); + return; + } + chprintf(chp, "Going to power down.\r\n"); + + chThdSleepMilliseconds(200); + + func_pwrdown(); + +} + +static void cmd_sleep(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: sleep\r\n"); + return; + } + chprintf(chp, "Going to sleep.\r\n"); + + chThdSleepMilliseconds(200); + + /* going to anabiosis */ + func_sleep(); +} + +/* + * + */ +static void cmd_alarm(BaseSequentialStream *chp, int argc, char *argv[]){ + + (void)argv; + if (argc < 1) { + goto ERROR; + } + + if ((argc == 1) && (strcmp(argv[0], "get") == 0)){ + rtcGetAlarm(&RTCD1, 0, &alarmspec); + chprintf(chp, "%D%s",alarmspec.tv_sec," - alarm in seconds\r\n"); + return; + } + + if ((argc == 2) && (strcmp(argv[0], "set") == 0)){ + alarmspec.tv_sec = (uint32_t)atol(argv[1]); + rtcSetAlarm(&RTCD1, 0, &alarmspec); + rtcSetCallback(&RTCD1, wakeup_cb); + return; + } + else{ + goto ERROR; + } + +ERROR: + chprintf(chp, "Usage: alarm get\r\n"); + chprintf(chp, " alarm set N\r\n"); + chprintf(chp, "where N is alarm time in seconds\r\n"); +} + +/* + * + */ +static void cmd_date(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argv; + struct tm timp; + + if (argc == 0) { + goto ERROR; + } + + if ((argc == 1) && (strcmp(argv[0], "get") == 0)){ + unix_time = rtcGetTimeUnixSec(&RTCD1); + + if (unix_time == -1){ + chprintf(chp, "incorrect time in RTC cell\r\n"); + } + else{ + chprintf(chp, "%D%s",unix_time," - unix time\r\n"); + rtcGetTimeTm(&RTCD1, &timp); + chprintf(chp, "%s%s",asctime(&timp)," - formatted time string\r\n"); + } + return; + } + + if ((argc == 2) && (strcmp(argv[0], "set") == 0)){ + unix_time = atol(argv[1]); + if (unix_time > 0){ + rtcSetTimeUnixSec(&RTCD1, unix_time); + return; + } + else{ + goto ERROR; + } + } + else{ + goto ERROR; + } + +ERROR: + chprintf(chp, "Usage: date get\r\n"); + chprintf(chp, " date set N\r\n"); + chprintf(chp, "where N is time in seconds sins Unix epoch\r\n"); + chprintf(chp, "you can get current N value from unix console by the command\r\n"); + chprintf(chp, "%s", "date +\%s\r\n"); + return; +} + +static const ShellCommand commands[] = { + {"alarm", cmd_alarm}, + {"date", cmd_date}, + {"sleep", cmd_sleep}, + {"pwrdown", cmd_pwrdown}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +BaseSequentialStream * chp1 = (BaseSequentialStream *)&SD1; + +/** + * Main function. + */ +int main(void){ + + halInit(); + chSysInit(); + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + + if (LPC_PMU->PCON & (1UL << 11)) { + chprintf(chp1, "Woke from Deep power-down\r\n"); + LPC_PMU->PCON |= (1 << 11); + } + + if (LPC_PMU->PCON & (1UL << 8)) { + chprintf(chp1, "Woke from Deep-sleep mode\r\n"); + LPC_PMU->PCON |= (1 << 8); + } + + /* Shell initialization.*/ + shellInit(); + static WORKING_AREA(waShell, 1024); + shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); + + /* wait until user do not want to test wakeup */ + while (TRUE){ + chThdSleepMilliseconds(200); + } + return 0; +} + + diff --git a/testhal/LPC122x/RTC/mcuconf.h b/testhal/LPC122x/RTC/mcuconf.h new file mode 100644 index 000000000..16519cb51 --- /dev/null +++ b/testhal/LPC122x/RTC/mcuconf.h @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC1227 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC122x_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC122x_SYSPLL_MUL 3 +#define LPC122x_SYSPLL_DIV 8 +#define LPC122x_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC122x_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC122x_GPT_USE_CT16B0 TRUE +#define LPC122x_GPT_USE_CT16B1 TRUE +#define LPC122x_GPT_USE_CT32B0 TRUE +#define LPC122x_GPT_USE_CT32B1 TRUE +#define LPC122x_GPT_CT16B0_IRQ_PRIORITY 1 +#define LPC122x_GPT_CT16B1_IRQ_PRIORITY 3 +#define LPC122x_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC122x_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC122x_SERIAL_USE_UART0 TRUE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART0CLKDIV 1 +#define LPC122x_SERIAL_UART0_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_TXD0_SELECTOR TXD0_IS_PIO0_2 +#define LPC122x_SERIAL_RXD0_SELECTOR RXD0_IS_PIO0_1 + +#define LPC122x_SERIAL_USE_UART1 FALSE +#define LPC122x_SERIAL_FIFO_PRELOAD 16 +#define LPC122x_SERIAL_UART1CLKDIV 1 +#define LPC122x_SERIAL_UART1_IRQ_PRIORITY 3 +#define LPC122x_SERIAL_RXD1_SELECTOR RXD1_IS_PIO0_8 +#define LPC122x_SERIAL_TXD1_SELECTOR TXD1_IS_PIO0_9 + +/* + * SPI driver system settings. + */ +#define LPC122x_SPI_USE_SSP0 TRUE +#define LPC122x_SPI_SSP0CLKDIV 1 +#define LPC122x_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC122x_SPI_SSP_ERROR_HOOK(spip) chSysHalt() + +/* + * EXT driver system settings. + */ +#define LPC122x_EXT_USE_EXT0 FALSE +#define LPC122x_EXT_USE_EXT1 FALSE +#define LPC122x_EXT_USE_EXT2 TRUE +#define LPC122x_EXT_EXTI0_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI1_IRQ_PRIORITY 3 +#define LPC122x_EXT_EXTI2_IRQ_PRIORITY 3 + +/* + * RTC driver system settings. + */ +#define LPC122x_RTCCLK SYSCFG_RTCCLK_1Hz +#define LPC122x_RTC_CLKDIV 0 +#define LPC122x_RTC_USE_ALARM TRUE +#define LPC122x_RTC_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define LPC122x_PWM_USE_CT16B0 FALSE +#define LPC122x_PWM_USE_CT16B1 TRUE +#define LPC122x_PWM_USE_CT32B0 FALSE +#define LPC122x_PWM_USE_CT32B1 FALSE +#define LPC122x_PWM_USE_CT16B0_CH0 FALSE +#define LPC122x_PWM_USE_CT16B0_CH1 FALSE +#define LPC122x_PWM_USE_CT16B1_CH0 TRUE +#define LPC122x_PWM_USE_CT16B1_CH1 TRUE +#define LPC122x_PWM_USE_CT32B0_CH0 FALSE +#define LPC122x_PWM_USE_CT32B0_CH1 FALSE +#define LPC122x_PWM_USE_CT32B1_CH0 FALSE +#define LPC122x_PWM_USE_CT32B1_CH1 FALSE +#define LPC122x_PWM_CT16B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B0_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT32B1_IRQ_PRIORITY 3 +#define LPC122x_PWM_CT16B0_CH0_SELECTOR PWM_CT16B0_CH0_IS_PIO0_28 +#define LPC122x_PWM_CT16B0_CH1_SELECTOR PWM_CT16B0_CH1_IS_PIO0_29 +#define LPC122x_PWM_CT16B1_CH0_SELECTOR PWM_CT16B1_CH0_IS_PIO1_5 +#define LPC122x_PWM_CT16B1_CH1_SELECTOR PWM_CT16B1_CH1_IS_PIO1_6 +#define LPC122x_PWM_CT32B0_CH0_SELECTOR PWM_CT32B0_CH0_IS_PIO2_4 +#define LPC122x_PWM_CT32B0_CH1_SELECTOR PWM_CT32B0_CH1_IS_PIO0_2 +#define LPC122x_PWM_CT32B1_CH0_SELECTOR PWM_CT32B1_CH0_IS_PIO0_6 +#define LPC122x_PWM_CT32B1_CH1_SELECTOR PWM_CT32B1_CH1_IS_PIO0_7 + +/* + * I2C driver system settings. + */ +#define LPC122x_I2C_IRQ_PRIORITY 3 diff --git a/testhal/LPC13xx/IRQ_STORM/Makefile b/testhal/LPC13xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..081579754 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1343/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC13xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC1343.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1348 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/LPC13xx/IRQ_STORM/chconf.h b/testhal/LPC13xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC13xx/IRQ_STORM/halconf.h b/testhal/LPC13xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..d91a792b4 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/LPC13xx/IRQ_STORM/main.c b/testhal/LPC13xx/IRQ_STORM/main.c new file mode 100644 index 000000000..b9c2f0274 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/main.c @@ -0,0 +1,324 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIO0, GPIO0_LED2); + } + } + } +} + +/* + * GPT1 callback. + */ +static void gpt1cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT1 configuration. + */ +static const GPTConfig gpt1cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt1cb /* Timer callback.*/ +}; + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 1 and 2. + */ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + gptStart(&GPTD1, &gpt1cfg); + gptStart(&GPTD2, &gpt2cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(LPC13xx_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD2, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/LPC13xx/IRQ_STORM/mcuconf.h b/testhal/LPC13xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..98da38735 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,76 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * LPC13xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC13xx_SYSPLL_MUL 6 +#define LPC13xx_SYSPLL_DIV 4 +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC13xx_SYSABHCLK_DIV 1 + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * GPT driver system settings. + */ +#define LPC13xx_GPT_USE_CT16B0 TRUE +#define LPC13xx_GPT_USE_CT16B1 TRUE +#define LPC13xx_GPT_USE_CT32B0 TRUE +#define LPC13xx_GPT_USE_CT32B1 TRUE +#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 6 +#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define LPC13xx_SERIAL_USE_UART0 TRUE +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC13xx_SPI_USE_SSP0 TRUE +#define LPC13xx_SPI_SSP0CLKDIV 1 +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 diff --git a/testhal/LPC13xx/IRQ_STORM/readme.txt b/testhal/LPC13xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..85a4cee82 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ-STORM demo for LPC13xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an LPCXpresso LPC1114 board. + +** The Demo ** + +The application demonstrates the use of the LPC13xx GPT, PAL and Serial drivers +in order to implement a system stress demo. + +** Build Procedure ** + +The demo has been tested using the free LPCXpresso toolchain but also with +Codesourcery and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +NXP and are licensed under a different license. + + http://www.nxp.com diff --git a/testhal/SPC560BCxx/CAN/Makefile b/testhal/SPC560BCxx/CAN/Makefile new file mode 100644 index 000000000..97618eebb --- /dev/null +++ b/testhal/SPC560BCxx/CAN/Makefile @@ -0,0 +1,140 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC560B50L5 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560bcxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC560BCxx/CAN/chconf.h b/testhal/SPC560BCxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/CAN/halconf.h b/testhal/SPC560BCxx/CAN/halconf.h new file mode 100644 index 000000000..c316bb385 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/CAN/main.c b/testhal/SPC560BCxx/CAN/main.c new file mode 100644 index 000000000..8525d7ddd --- /dev/null +++ b/testhal/SPC560BCxx/CAN/main.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND5, PE_LED1}; + +/* + * Internal loopback mode, 500kBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_E, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_E, cip->led); + } +#endif + } + chEvtUnregister(&CAND5.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND5, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_E, PE_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND5, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} + diff --git a/testhal/SPC560BCxx/CAN/mcuconf.h b/testhal/SPC560BCxx/CAN/mcuconf.h new file mode 100644 index 000000000..dc667bb74 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/mcuconf.h @@ -0,0 +1,223 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560BCxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 FALSE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#define SPC5_CAN_FLEXCAN1_PRIORITY 11 +#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN2 FALSE +#define SPC5_CAN_FLEXCAN2_PRIORITY 11 +#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN3 FALSE +#define SPC5_CAN_FLEXCAN3_PRIORITY 11 +#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN4 TRUE +#define SPC5_CAN_FLEXCAN4_PRIORITY 11 +#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN5 FALSE +#define SPC5_CAN_FLEXCAN5_PRIORITY 11 +#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560BCxx/CAN/readme.txt b/testhal/SPC560BCxx/CAN/readme.txt new file mode 100644 index 000000000..78f7e7cd5 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC560BCxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560BCxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560BCxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560BCxx/ICU-PWM/Makefile b/testhal/SPC560BCxx/ICU-PWM/Makefile new file mode 100644 index 000000000..9e39b8301 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/Makefile @@ -0,0 +1,121 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560bcxx_1.0.0.201305101230/component/lib/rsc/rules.mk diff --git a/testhal/SPC560BCxx/ICU-PWM/chconf.h b/testhal/SPC560BCxx/ICU-PWM/chconf.h new file mode 100644 index 000000000..db0d97427 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/chconf.h @@ -0,0 +1,536 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES FALSE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/ICU-PWM/halconf.h b/testhal/SPC560BCxx/ICU-PWM/halconf.h new file mode 100644 index 000000000..24462dafd --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/ICU-PWM/main.c b/testhal/SPC560BCxx/ICU-PWM/main.c new file mode 100644 index 000000000..11b4a8a23 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/main.c @@ -0,0 +1,151 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT_E, PE_LED1); + +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT_E, PE_LED1); +} + +static PWMConfig pwmcfg = { + 40000, /* 40kHz PWM clock frequency.*/ + 20000, /* Initial PWM period 0.5s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_LOW, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT_E, PE_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT_E, PE_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_LOW, + 40000, /* 40kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palClearPad(PORT_E, PE_LED4); + + /* + * Initializes the PWM driver 1 and ICU driver 1. + * GPIOA9 is the PWM channel 0 output. + * GPIOA0 is the ICU input. + * The two pins have to be externally connected together. + */ + icuStart(&ICUD1, &icucfg); + icuEnable(&ICUD1); + + /* Sets A0 alternative function.*/ + SIU.PCR[0].R = 0b0000010100000100; + + /* Sets A9 alternative function.*/ + SIU.PCR[9U].R = 0b0000011000000100; + + pwmStart(&PWMD1, &pwmcfg); + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD1, 30000); + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + + icuDisable(&ICUD1); + icuStop(&ICUD1); + + palClearPad(PORT_E, PE_LED3); + palClearPad(PORT_E, PE_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC560BCxx/ICU-PWM/mcuconf.h b/testhal/SPC560BCxx/ICU-PWM/mcuconf.h new file mode 100644 index 000000000..010a16b16 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/mcuconf.h @@ -0,0 +1,242 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560BCxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 FALSE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU-PWM driver system settings. + */ +#define SPC5_EMIOS0_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/ + +#define SPC5_ICU_USE_EMIOS0_CH0 TRUE +#define SPC5_ICU_USE_EMIOS0_CH1 TRUE +#define SPC5_ICU_USE_EMIOS0_CH2 TRUE +#define SPC5_ICU_USE_EMIOS0_CH3 TRUE +#define SPC5_ICU_USE_EMIOS0_CH4 TRUE +#define SPC5_ICU_USE_EMIOS0_CH5 TRUE +#define SPC5_ICU_USE_EMIOS0_CH6 TRUE +#define SPC5_ICU_USE_EMIOS0_CH7 TRUE +#define SPC5_ICU_USE_EMIOS0_CH24 TRUE + +#define SPC5_PWM_USE_EMIOS0_GROUP0 TRUE +#define SPC5_PWM_USE_EMIOS0_GROUP1 TRUE + +#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7 +#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7 + +#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_EMIOS1_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/ + +#define SPC5_ICU_USE_EMIOS1_CH24 TRUE + +#define SPC5_PWM_USE_EMIOS1_GROUP0 TRUE +#define SPC5_PWM_USE_EMIOS1_GROUP1 TRUE +#define SPC5_PWM_USE_EMIOS1_GROUP2 TRUE + +#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7 +#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7 + +#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560BCxx/ICU-PWM/readme.txt b/testhal/SPC560BCxx/ICU-PWM/readme.txt new file mode 100644 index 000000000..6c64a8d21 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - ICU-PWM driver demo for SPC560BCxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560BCxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560BCxx ICU and PWM drivers. + +** Board Setup ** + +Connect PINA0 and PINA9 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Dxx/SPI/.cproject b/testhal/SPC560Dxx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC560Dxx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Dxx/SPI/.project b/testhal/SPC560Dxx/SPI/.project new file mode 100644 index 000000000..7000648ab --- /dev/null +++ b/testhal/SPC560Dxx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC560Dxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560D + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Dxx/SPI/Makefile b/testhal/SPC560Dxx/SPI/Makefile new file mode 100644 index 000000000..833d3878a --- /dev/null +++ b/testhal/SPC560Dxx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560D/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Dxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Dxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560D40.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC560Dxx/SPI/UDE/debug .wsx b/testhal/SPC560Dxx/SPI/UDE/debug .wsx new file mode 100644 index 000000000..8a1dc048c --- /dev/null +++ b/testhal/SPC560Dxx/SPI/UDE/debug .wsx @@ -0,0 +1,273 @@ + + + debug .wsx002vQTv/gAAAQAXAAIA6AkIAAAABAAAAAAAPwAAAAAAAAAEAAAAAgAAAAAAAAAAAAAAAAAAAA==4.019.11.2012 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Window Bar 00-1FalseUDEDesktop Standard BarsTab Window Bar 0UDEDesktop0015019100False00True000004-214748364803889FalseFalse100000030018030018015018006144014948CUdeProjectWspBarProject Workspace Bar0-1FalseUDEDesktop Standard BarsProject Workspace BarUDEDesktop0001TrueTrueFalse21.11.2012 14:43:52:278487782411WorkspaceManager11019.11.2012 16:28:52:057MgAAAA==AQAAAA==ZAAAAA==AQAAAA==lgAAAA==AQAAAA==6AMAAA==AQAAAA==139011201WorkspaceManager110000110010\\napnt002.nap.st.com\NAPPRT0001000WorkspaceManagerWorkspaceManager01Core1Target0.Controller0.CoreTarget0.Controller0.Core102200701438312957781279740NormalfalseTop1271falseBottom0000falsefalse00DockPaneltrue417falseLeft0000falsefalse00DockPaneltrue417falseLeft0000falsefalse10DockPanelfalse0falseTop0000falsefalse0-1TabbedDocumenttrue417falseLeft0000falsefalse20DockPanelfalse417falseLeft0000falsefalse30DockPanelfalsetrue556false200false200true200true100truetrue0012797400127924Platform Main Menufalsetrue4249525Edit ToolbarfalsetrueUDE_Workspace_0x1779trueCutImagetrueUDE_Workspace_0x177AtrueCopyImagetrueUDE_Workspace_0x177BtruePasteImagetrue992427625Macro ToolbarfalsetrueUDE_0x3B_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueRun MacroImagetrueUDE_0x40_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueDebug MacroImagetrueUDE_0x3_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueBreak MacroImagetrueUDE_0x3C_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueReload MacroImagetrueUDE_Ctrl_{4D5190CD-077D-4F92-B890-4545242BF32A}_UDEWorkspacetrueImageAndTextfalse3752421025File ToolbarfalsetrueUDE_Workspace_0x1770trueNew WorkspaceImagetrueUDE_Workspace_0x1771trueOpen workspaceImagetrueUDE_Workspace_0x1772trueSave workspace asImagetrueUDE_Workspace_0x1773trueSave workspaceImagetrueUDE_Workspace_0x1774trueClose workspaceImagetrueUDE_Workspace_0x177FtrueExport view contentImagetrueUDE_Workspace_0x1778truePrintImagetrueUDE_0x1_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueLoad ProgramImagetrue5852444025Views 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HTMLImagetrueUDE_0x19_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueArray ChartImagetrueUDE_0x1B_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueTime Traced Signal ChartImagetrueUDE_0x50_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueIP Trace ProfilingImagetrueUDE_0x28_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueMemoryImagetrueUDE_0x46_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueCall StackImagetrue34950925Debug ToolbarfalsetrueUDE_0x18_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow IPImagetrueUDE_0x5E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow program codeImagetrueUDE_0x7_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStart ProgramImagetrueUDE_0x9_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OverImagetrueUDE_0xA_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep IntoImagetrueUDE_0xB_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OutImagetrueUDE_0x8_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRun CursorImagetrueUDE_0x321_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreak ProgramImagetrueUDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueResetImagetrueUDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRestart ProgramImagetrueUDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreakpointsImagetrueUDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueToggle BreakImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_CoretrueImageAndTextfalseUDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueTrigger setupImagetrue5124914125Config ToolbarfalsetrueUDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget ConfigurationImagetrueUDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueConnect TargetImagetrueUDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueDisconnect TargetImagetrueUDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueSetup Target InterfaceImagetrueUDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueMCU Run ControlImagetrue6534915125Tools ToolbarfalsetrueUDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_CoretrueImageAndTextfalseUDE_0xE1_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueExecution Time SetupImagetrue01002625Show Toolbarfalsefalse02002625Window Toolbarfalsefalse02252625Workspace Toolbarfalsefalse02752625Help Toolbarfalsefalse071712792300127923Platform Status Barfalsetrue07406431279740643..\..\..\..\..\Program Files\pls\UDE 4.0\StdLibrary.mso{866f82d3-fac5-43cd-8a82-0af01e46e2c5}669,1006,350,6610..\..\..\..\..\Documents and Settings\disiriog\My Documents\pls\UDE 4.0The script contains a collection of macros to save memory content into different file formats +and fill target memory rangesV:\UDE\AddOns\Macro\MacroLibrary\StdMacros1.dsm' +' $Header: /Ude/AddOns/Macro/MacroLibrary/StdMacros.dsm 3 30.04.04 9:34 Weisses $ +'_______________________________________________________ +' +' universal debug engine +' +' Standard command line macros - part 1 +' +' pls Development Tools 1999-2004 +' +' 28.04.04 SW correction for UDE 1.10 +' 03.06.03 SW initial version +'_______________________________________________________ + +'_______________________________________________________ +' +' UnAss command line function +' +' generates disassembly file +' +' command line UnAss output-file range1 [range2] [range3] ..... +' range description: +' C:<startaddress>,<length> or - code +' DB:<startaddress>,<length> or - data byte +' DW:<startaddress>,<length> or - data word +' DD:<startaddress>,<length> or - data dword +'_______________________________________________________ + +Sub UnAss(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE Disassembler output of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + KindOfRange = CStr(ParameterObj.Parameter(ParamIndex)) + KindOfRange = UCase(KindOfRange) + Address = CLng(ParameterObj.Parameter(ParamIndex +1)) + Length = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + If IsNumeric(KindOfRange) Then + If KindOfRange = 12 Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = 219 Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = 221 Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + Else + If KindOfRange = "C" Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = "DB" Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = "DW" Then + DisASMObj.AddRange Address,Length,3 + ElseIf KindOfRange = "DD" Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + End If + Next + DisASMObj.HexFileModeFlag = False + DisASMObj.ListModeFlag = False + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' SaveHEX command line function +' +' generates intel-HEX file +' +' command line SaveHex output-file range1 [range2] [range3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub SaveHEX(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE generated intel-Hex file of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 2 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/2 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + ParamIndex = ParamIndex +2 + DisASMObj.AddRange Address,Length,0 + Next + DisASMObj.HexFileModeFlag = True + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' FillByte command line function +' +' fills memory range with byte pattern +' +' command line FillByte range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillByte(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.ByteArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillWord command line function +' +' fills memory range with word pattern +' +' command line FillWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.WordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/2) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillDWord command line function +' +' fills memory range with dword pattern +' +' command line FillDWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillDWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.DWordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/4) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub63VBScript24.11.2006 14:43:20:0001WS_CORE_DUOMacro_14_06_13_14_48_10_010Execute UnAss ..Macro UnAssExecute macro UnAss0210Execute SaveHEX ..Macro SaveHEXExecute macro SaveHEX0210Execute FillByte ..Macro FillByteExecute macro FillByte0110Execute FillWord ..Macro FillWordExecute macro FillWord0110Execute FillDWord ..Macro FillDWordExecute macro FillDWord0150121.11.2012 14:17:23:6457782750Target0.Controller0.Core1020.11.2012 16:19:48:3447782640Target0.Controller0.Core11021.11.2012 12:22:49:573..\main.c1,0,0,353,10940017372830Target0.Controller0.Core1114.06.2013 14:25:28:960..\..\..\os\hal\src\hal.c1,49,63,402,11570017372860Target0.Controller0.Core110214.06.2013 14:27:53:872..\..\..\os\hal\platforms\SPC5xx\SIUL_v1\pal_lld.c7372880Target0.Controller0.Core1121.11.2012 14:44:22:506..\..\..\os\kernel\src\chsys.c7372860Target0.Controller0.Core13121.11.2012 14:14:46:537AwAAAA==AQAAAA==kAAAAA==YAAAAA==TgAAAA==jQAAAA==TgAAAA==jQAAAA==TgAAAA==jgAAAA==AAAAAA==AAAAAA==AAAAAA==AAAAAA==7782520Target0.Controller0.Core10021.11.2012 14:10:10:4245380360007372850Target0.Controller0.Core10000000013.06.2013 16:10:26:035000013.06.2013 16:20:21:757<_ExtentX type="bin" size="8">UEoAAA==<_ExtentY type="bin" size="8">gysAAA==<_StockProps type="bin" size="8">AAAAAA==AgAAAA==UABDAAAAUABDAAAAAAAAAA==YAAAAA==RgB1AG4AYwB0AGkAbwBuAAAARgB1AG4AYwB0AGkAbwBuAAAAAAAAAA==QAYAAA==7372890Target0.Controller0.Core1OFF0..\build11..\build\ch.elf<Section>C:\ChibiStudio\chibios\os\kernel\src\chevents.c1Software;enabled;0;disabled;'main {C:\ChibiStudio\chibios\demos\PPC-SPC560D-GCC\main.c} .164';main.c;1;0;;$disabled; ;disabled; ;100111100verify.txt0000000004..\..\..\..\os\ports\GCC\PPC\chcore.c..\..\..\..\os\kernel\src\chsys.c..\..\..\..\os\hal\platforms\SPC5xx\DSPI_v1\spi_lld.c..\main.cstm_xpc560b_spc560d40_minimodule_debug_jtag.cfg14.06.2013 14:48:09:999 diff --git a/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg b/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg new file mode 100644 index 000000000..ca4a75aa0 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg @@ -0,0 +1,160 @@ +[Main] +Signature=UDE_TARGINFO_2.0 +Description=STM XPC560B Mini Module with SPC560D40 (Jtag) +Description1=PLL set for 48MHz +Description2=FLASH programming prepared but not enabled +Description3=Write Filter for BAM Module +MCUs=Controller0 +Architecture=PowerPC +Vendor=STM +Board=XPC560B Mini Module + +[Controller0] +Family=PowerPC +Type=SPC560D40 +Enabled=1 +IntClock=48000 +MemDevs=BAMWriteFilter +ExtClock=8000 + +[Controller0.Core] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.Core.LoadedAddOn] +UDEMemtool=1 + +[Controller0.Core.PpcJtagTargIntf] +PortType=FTDI +ResetWaitTime=50 +MaxJtagClk=2500 +DoSramInit=1 +UseNexus=1 +AdaptiveJtagPhaseShift=1 +ConnOption=Default +ChangeJtagClk=10000 +HaltAfterReset=1 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=0 +InvalidateCache=0 +ForceCacheFlush=0 +IgnoreLockedLines=0 +ExecInitCmds=1 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 + +SimioAddr=g_JtagSimioAccess + +FlushCache=0 +AllowMmuSetup=1 +UseExtReset=1 +HandleWdtBug=0 +ForceEndOfReset=0 +JtagViaPod=0 +AllowResetOnCheck=0 +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +TargetPort=Default +EnableProgramTimeMeasurement=0 +UseHwResetMode=0 +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +CommDevSel=PortType=USB,Type=FTDI +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF +JtagIoType=Jtag +ExecOnHaltCmdsWhileHalted=0 +TimerForPTM=Default +AllowBreakOnUpdateBreakpoints=0 +ClearDebugStatusOnHalt=1 +HwResetMode=Simulate +UseMasterNexusIfResetState=1 +UseLocalAddressTranslation=1 +Use64BitNexus=0 +InitSramOnlyWhenNotInitialized=0 +AllowHarrForUpdateDebugRegs=0 +DisableE2EECC=0 +UseCore0ForNexusMemoryAccessWhileRunning=0 + +[Controller0.Core.PpcJtagTargIntf.InitScript] +// setup IVOPR +// points to internal memory at 0x40000000 +SETSPR 0x3F 0x40000000 0xFFFFFFFF + +// disable watchdog +SET SWT_SR 0xC520 +SET SWT_SR 0xD928 +SET SWT_CR 0xFF00000A + +// Oscillator select +SET CGM_OCDS_SC 0x1000000 +SET CGM_OC_EN 0x1 + +// enable all modes +SET ME_MER 0x5FF + +// run mode +SET ME_DRUN_MC 0x1F0032 +SET ME_RUN_PC0 0xFE + +// enable peripherals in run and low power modes +SET ME_LP_PC0 0x500 + +// enable clocks +SET8 CGM_SC_DC0 0x80 +SET8 CGM_SC_DC1 0x80 +SET8 CGM_SC_DC2 0x80 + +// setup clock monitor +SET CMU_CSR 0x6 +SET CMU_LFREFR 0x1 +SET CMU_HFREFR 0xFFE + +// Make DRUN configuration active +SET ME_MCTL 0x30005AF0 +SET ME_MCTL 0x3000A50F +WAIT 0x5 + +// setup pll to 48MHz +SET FMPLL_CR 0x5300041 0xFFFFFFFF +// run mode +SET ME_DRUN_MC 0x1F00F4 + +// Make DRUN configuration active +SET ME_MCTL 0x30005AF0 +SET ME_MCTL 0x3000A50F +WAIT 0x5 + +// setup SSCM erro cfg for debug +SET16 SSCM_ERROR 0x3 0x3 + +[Controller0.BAMWriteFilter] +Description=BAM WriteAccess Filter +Range0Start=0xFFFFC000 +Range0Size=0x4000 +Enabled=1 +Handler=AccessFilter +Mode=ReadOnly + +[Controller0.PFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.DFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.Core.PpcJtagTargIntf.OnStartScript] + +[Controller0.Core.PpcJtagTargIntf.OnHaltScript] diff --git a/testhal/SPC560Dxx/SPI/chconf.h b/testhal/SPC560Dxx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Dxx/SPI/halconf.h b/testhal/SPC560Dxx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC560Dxx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Dxx/SPI/main.c b/testhal/SPC560Dxx/SPI/main.c new file mode 100644 index 000000000..f6aa96abe --- /dev/null +++ b/testhal/SPC560Dxx/SPI/main.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration. + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(PORT_E, PE_LED1); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(PORT_E, PE_LED1); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_1 I/O pins setup.*/ + spiStart(&SPID1, &ls_spicfg); + SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */ + SIU.PCR[28].R = PAL_MODE_OUTPUT_ALTERNATE(3); /* CS[1] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID1, 4, txbuf, rxbuf); + spiExchange(&SPID1, 32, txbuf, rxbuf); + spiExchange(&SPID1, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID1, 4); + spiIgnore(&SPID1, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID1, 4, txbuf); + spiSend(&SPID1, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID1, 4, rxbuf); + spiReceive(&SPID1, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID1); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT_E, PE_LED2); + } + return 0; +} diff --git a/testhal/SPC560Dxx/SPI/mcuconf.h b/testhal/SPC560Dxx/SPI/mcuconf.h new file mode 100644 index 000000000..166be874b --- /dev/null +++ b/testhal/SPC560Dxx/SPI/mcuconf.h @@ -0,0 +1,230 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Dxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 48 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_USE_LINFLEX2 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX2_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Dxx/SPI/readme.txt b/testhal/SPC560Dxx/SPI/readme.txt new file mode 100644 index 000000000..baa32f272 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC560Dxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Dxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Dxx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Pxx/CAN/.cproject b/testhal/SPC560Pxx/CAN/.cproject new file mode 100644 index 000000000..18c26cafe --- /dev/null +++ b/testhal/SPC560Pxx/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Pxx/CAN/.project b/testhal/SPC560Pxx/CAN/.project new file mode 100644 index 000000000..4c2d806c5 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/.project @@ -0,0 +1,38 @@ + + + SPC560Pxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560P + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Pxx/CAN/Makefile b/testhal/SPC560Pxx/CAN/Makefile new file mode 100644 index 000000000..33ab47686 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/Makefile @@ -0,0 +1,140 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC560P50L5 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560pxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC560Pxx/CAN/chconf.h b/testhal/SPC560Pxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/CAN/halconf.h b/testhal/SPC560Pxx/CAN/halconf.h new file mode 100644 index 000000000..c316bb385 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/CAN/main.c b/testhal/SPC560Pxx/CAN/main.c new file mode 100644 index 000000000..b60729765 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/main.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND1, PD_LED1}; + +/* + * Internal loopback mode, 500kBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#endif + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} + diff --git a/testhal/SPC560Pxx/CAN/mcuconf.h b/testhal/SPC560Pxx/CAN/mcuconf.h new file mode 100644 index 000000000..bdd11f6ae --- /dev/null +++ b/testhal/SPC560Pxx/CAN/mcuconf.h @@ -0,0 +1,190 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 TRUE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Pxx/CAN/readme.txt b/testhal/SPC560Pxx/CAN/readme.txt new file mode 100644 index 000000000..b5587dd29 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC560Pxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Pxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Pxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Pxx/PWM-ICU/.cproject b/testhal/SPC560Pxx/PWM-ICU/.cproject new file mode 100644 index 000000000..18c26cafe --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Pxx/PWM-ICU/.project b/testhal/SPC560Pxx/PWM-ICU/.project new file mode 100644 index 000000000..4c2d806c5 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + SPC560Pxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560P + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Pxx/PWM-ICU/Makefile b/testhal/SPC560Pxx/PWM-ICU/Makefile new file mode 100644 index 000000000..1bdaed928 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/Makefile @@ -0,0 +1,167 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560P/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Pxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Pxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560P50.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC560Pxx/PWM-ICU/chconf.h b/testhal/SPC560Pxx/PWM-ICU/chconf.h new file mode 100644 index 000000000..c132ac014 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/chconf.h @@ -0,0 +1,525 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/PWM-ICU/halconf.h b/testhal/SPC560Pxx/PWM-ICU/halconf.h new file mode 100644 index 000000000..09022b9e7 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/PWM-ICU/main.c b/testhal/SPC560Pxx/PWM-ICU/main.c new file mode 100644 index 000000000..31ef444ee --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/main.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT_D, PD_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT_D, PD_LED1); +} + +static PWMConfig pwmcfg = { + 250000, /* 250kHz PWM clock frequency.*/ + 50000, /* Initial PWM period 0.2s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT_D, PD_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT_D, PD_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 250000, /* 250kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 1 and ICU driver 1. + * GPIOD10 is the PWM output. + * GPIOA0 is the ICU input. + * The two pins have to be externally connected together. + */ + icuStart(&ICUD1, &icucfg); + icuEnable(&ICUD1); + + /* Sets A0 alternative function.*/ + SIU.PCR[0].R = 0b0100010100000100; + + pwmStart(&PWMD1, &pwmcfg); + /* Sets D10 alternative function.*/ + SIU.PCR[58].R = 0b0100010100000100; + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD1, 25000); + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + icuDisable(&ICUD1); + icuStop(&ICUD1); + palClearPad(PORT_D, PD_LED3); + palClearPad(PORT_D, PD_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..ae770ef86 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h @@ -0,0 +1,298 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * Serial driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_USE_DSPI3 FALSE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Pxx/PWM-ICU/readme.txt b/testhal/SPC560Pxx/PWM-ICU/readme.txt new file mode 100644 index 000000000..025e73c87 --- /dev/null +++ b/testhal/SPC560Pxx/PWM-ICU/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM/ICU drivers demo for SPC560Pxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Pxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Pxx PWM-ICU drivers. + +** Board Setup ** + +- Connect D10 and A0 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Pxx/SPI/.cproject b/testhal/SPC560Pxx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC560Pxx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Pxx/SPI/.project b/testhal/SPC560Pxx/SPI/.project new file mode 100644 index 000000000..c0c005e49 --- /dev/null +++ b/testhal/SPC560Pxx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC560Pxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560P + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Pxx/SPI/Makefile b/testhal/SPC560Pxx/SPI/Makefile new file mode 100644 index 000000000..c5e4bde95 --- /dev/null +++ b/testhal/SPC560Pxx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560P/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Pxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Pxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560P50.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC560Pxx/SPI/chconf.h b/testhal/SPC560Pxx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC560Pxx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/SPI/halconf.h b/testhal/SPC560Pxx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC560Pxx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/SPI/main.c b/testhal/SPC560Pxx/SPI/main.c new file mode 100644 index 000000000..83ee0bbb1 --- /dev/null +++ b/testhal/SPC560Pxx/SPI/main.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(PORT_D, PD_LED1); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(PORT_D, PD_LED1); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_1 I/O pins setup.*/ + spiStart(&SPID1, &ls_spicfg); + SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[36].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */ + SIU.PCR[35].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[1] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID1, 4, txbuf, rxbuf); + spiExchange(&SPID1, 32, txbuf, rxbuf); + spiExchange(&SPID1, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID1, 4); + spiIgnore(&SPID1, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID1, 4, txbuf); + spiSend(&SPID1, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID1, 4, rxbuf); + spiReceive(&SPID1, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID1); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT_D, PD_LED2); + } + return 0; +} diff --git a/testhal/SPC560Pxx/SPI/mcuconf.h b/testhal/SPC560Pxx/SPI/mcuconf.h new file mode 100644 index 000000000..ba5720366 --- /dev/null +++ b/testhal/SPC560Pxx/SPI/mcuconf.h @@ -0,0 +1,298 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * Serial driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 FALSE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 FALSE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Pxx/SPI/readme.txt b/testhal/SPC560Pxx/SPI/readme.txt new file mode 100644 index 000000000..302b4a23b --- /dev/null +++ b/testhal/SPC560Pxx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC560Pxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Pxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Pxx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC563Mxx/ADC/.cproject b/testhal/SPC563Mxx/ADC/.cproject new file mode 100644 index 000000000..57b44e9a8 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC563Mxx/ADC/.project b/testhal/SPC563Mxx/ADC/.project new file mode 100644 index 000000000..ff4e5ffca --- /dev/null +++ b/testhal/SPC563Mxx/ADC/.project @@ -0,0 +1,38 @@ + + + SPC563Mxx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC563M + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile new file mode 100644 index 000000000..644898587 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC563M64.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + adc_cfg.c main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.c b/testhal/SPC563Mxx/ADC/adc_cfg.c new file mode 100644 index 000000000..7bb5bbbe6 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/adc_cfg.c @@ -0,0 +1,743 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "adc_cfg.h" + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 5 channels, SW triggered. + * Channels: ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50, + * ADC_CHN_VREF75, ADC_CHN_VRH. + * + * NOTE: The configuration of a sequence is very complex in this ADC + * implementation. Configurations are meant to be generated by the + * SPC5 Studio visual configuration tool and not be written manually. + * Writing complex sequences manually requires ad deep knowledge of both + * the EQADC peripheral and the driver implementation. + */ +static const adccommand_t adcgrpcfg1_commands[ADC_GRP1_NUM_CHANNELS * + ADC_GRP1_BUF_DEPTH] = { + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH) +}; + +const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + EQADC_CFCR_MODE_SWCS, + 0, 0, /* ISEL, EISEL.*/ + ADC_GRP1_BUF_DEPTH, + adcgrpcfg1_commands +}; + +/* + * ADC conversion group. + * Mode: Circular buffer, 16 samples of 5 channels, SW triggered. + * Channels: ADC_CHN_VRL, ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50, + * ADC_CHN_VREF50, ADC_CHN_VREF75, ADC_CHN_VRH, ADC_CHN_VRH. + * + * NOTE: The configuration of a sequence is very complex in this ADC + * implementation. Configurations are meant to be generated by the + * SPC5 Studio visual configuration tool and not be written manually. + * Writing complex sequences manually requires ad deep knowledge of both + * the EQADC peripheral and the driver implementation. + */ +static const adccommand_t adcgrpcfg2_commands[ADC_GRP2_NUM_CHANNELS * + ADC_GRP2_BUF_DEPTH] = { + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRL), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF25), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF50), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VREF75), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), + + EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL | + EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) | + EQADC_CONV_CHANNEL(ADC_CHN_VRH), +}; + +const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + EQADC_CFCR_MODE_SWCS, + 0, 0, /* ISEL, EISEL.*/ + ADC_GRP2_BUF_DEPTH, + adcgrpcfg2_commands +}; diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.h b/testhal/SPC563Mxx/ADC/adc_cfg.h new file mode 100644 index 000000000..cf0f411a3 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/adc_cfg.h @@ -0,0 +1,38 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _ADC_CFG_H_ +#define _ADC_CFG_H_ + +#define ADC_GRP1_NUM_CHANNELS 5 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +extern const ADCConversionGroup adcgrpcfg1; +extern const ADCConversionGroup adcgrpcfg2; + +#ifdef __cplusplus +extern "C" { +#endif + void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n); + void adcerrorcallback(ADCDriver *adcp, adcerror_t err); +#ifdef __cplusplus +} +#endif + +#endif /* _ADC_CFG_H_ */ diff --git a/testhal/SPC563Mxx/ADC/chconf.h b/testhal/SPC563Mxx/ADC/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ADC/halconf.h b/testhal/SPC563Mxx/ADC/halconf.h new file mode 100644 index 000000000..a719ec40a --- /dev/null +++ b/testhal/SPC563Mxx/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c new file mode 100644 index 000000000..6ec736309 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/main.c @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "adc_cfg.h" + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +/* + * ADC error callback. + */ +void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; + + palSetPad(PORT11, P11_LED4); + chSysHalt(); +} + +/* + * LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(PORT11, P11_LED1); + chThdSleepMilliseconds(500); + palClearPad(PORT11, P11_LED1); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1, ADC3 drivers. + */ + adcStart(&ADCD1, NULL); + adcStart(&ADCD3, NULL); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD3, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, once the button is pressed the ADC + * conversion is stopped. + */ + while (TRUE) { + if (palReadPad(PORT11, P11_BUTTON1)) { + adcStopConversion(&ADCD3); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h new file mode 100644 index 000000000..18cc088ac --- /dev/null +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -0,0 +1,122 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC563Mxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 80 +#define SPC5_CLK_RFD SPC5_RFD_DIV4 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 TRUE +#define SPC5_ADC_USE_ADC0_Q1 TRUE +#define SPC5_ADC_USE_ADC0_Q2 TRUE +#define SPC5_ADC_USE_ADC1_Q3 TRUE +#define SPC5_ADC_USE_ADC1_Q4 TRUE +#define SPC5_ADC_USE_ADC1_Q5 TRUE +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB TRUE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/SPC563Mxx/ADC/readme.txt b/testhal/SPC563Mxx/ADC/readme.txt new file mode 100644 index 000000000..ebe5c0a37 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for SPC563Mxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC563Mxx ADC driver. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC563Mxx/ICU-PWM/.cproject b/testhal/SPC563Mxx/ICU-PWM/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC563Mxx/ICU-PWM/.project b/testhal/SPC563Mxx/ICU-PWM/.project new file mode 100644 index 000000000..31139adbb --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/.project @@ -0,0 +1,38 @@ + + + SPC563Mxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC563M + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC563Mxx/ICU-PWM/Makefile b/testhal/SPC563Mxx/ICU-PWM/Makefile new file mode 100644 index 000000000..911a39668 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC563M64.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC563Mxx/ICU-PWM/chconf.h b/testhal/SPC563Mxx/ICU-PWM/chconf.h new file mode 100644 index 000000000..b4c46c7f6 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/chconf.h @@ -0,0 +1,536 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES FALSE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ICU-PWM/halconf.h b/testhal/SPC563Mxx/ICU-PWM/halconf.h new file mode 100644 index 000000000..3a6d72910 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/ICU-PWM/main.c b/testhal/SPC563Mxx/ICU-PWM/main.c new file mode 100644 index 000000000..51edb64c8 --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/main.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT11, P11_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT11, P11_LED1); +} + +static PWMConfig pwmcfg = { + 100000, /* 100kHz PWM clock frequency.*/ + 20000, /* Initial PWM period 0.2s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT11, P11_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT11, P11_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 100000, /* 100kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* Initialization of all the imported components in the order specified in + the application wizard. The function is generated automatically.*/ + componentsInit(); + + palClearPad(PORT11, P11_LED4); + + /* + * Initializes the PWM driver 8 and ICU driver 1. + * PIN80 is the PWM output. + * PIN63 is the ICU input. + * The two pins have to be externally connected together. + */ + + /* Sets PIN63 alternative function.*/ + SIU.PCR[179].R = 0b0000010100001100; + + /* Sets PIN80 alternative function.*/ + SIU.PCR[202].R = 0b0000011000001100; + + icuStart(&ICUD1, &icucfg); + icuEnable(&ICUD1); + pwmStart(&PWMD8, &pwmcfg); + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD8, 25000); + pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables PWM channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD8, 0); + pwmStop(&PWMD8); + + /* + * Disables and stops the ICU drivers. + */ + + icuDisable(&ICUD1); + icuStop(&ICUD1); + + palClearPad(PORT11, P11_LED3); + palClearPad(PORT11, P11_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC563Mxx/ICU-PWM/mcuconf.h b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h new file mode 100644 index 000000000..be3ee85cf --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h @@ -0,0 +1,100 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC563Mxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 80 +#define SPC5_CLK_RFD SPC5_RFD_DIV4 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_PRIO 12 +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB FALSE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * ICU - PWM driver system settings. + */ +#define SPC5_ICU_USE_EMIOS_CH0 TRUE +#define SPC5_ICU_USE_EMIOS_CH1 TRUE +#define SPC5_ICU_USE_EMIOS_CH2 TRUE +#define SPC5_ICU_USE_EMIOS_CH3 TRUE +#define SPC5_ICU_USE_EMIOS_CH4 TRUE +#define SPC5_ICU_USE_EMIOS_CH5 TRUE +#define SPC5_ICU_USE_EMIOS_CH6 TRUE +#define SPC5_ICU_USE_EMIOS_CH8 TRUE + +#define SPC5_PWM_USE_EMIOS_CH9 TRUE +#define SPC5_PWM_USE_EMIOS_CH10 TRUE +#define SPC5_PWM_USE_EMIOS_CH11 TRUE +#define SPC5_PWM_USE_EMIOS_CH12 TRUE +#define SPC5_PWM_USE_EMIOS_CH13 TRUE +#define SPC5_PWM_USE_EMIOS_CH14 TRUE +#define SPC5_PWM_USE_EMIOS_CH15 TRUE +#define SPC5_PWM_USE_EMIOS_CH23 TRUE + +#define SPC5_EMIOS_GLOBAL_PRESCALER 200 diff --git a/testhal/SPC563Mxx/ICU-PWM/readme.txt b/testhal/SPC563Mxx/ICU-PWM/readme.txt new file mode 100644 index 000000000..90fcf6d5c --- /dev/null +++ b/testhal/SPC563Mxx/ICU-PWM/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - ICU_PWM driver demo for SPC563Mxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC563Mxx ICU and PWM drivers. + +** Board Setup ** + +Connect PIN63 and PIN80 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC563Mxx/SPI/.cproject b/testhal/SPC563Mxx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC563Mxx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC563Mxx/SPI/.project b/testhal/SPC563Mxx/SPI/.project new file mode 100644 index 000000000..31139adbb --- /dev/null +++ b/testhal/SPC563Mxx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC563Mxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC563M + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC563Mxx/SPI/Makefile b/testhal/SPC563Mxx/SPI/Makefile new file mode 100644 index 000000000..911a39668 --- /dev/null +++ b/testhal/SPC563Mxx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC563M64.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC563Mxx/SPI/chconf.h b/testhal/SPC563Mxx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC563Mxx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/SPI/halconf.h b/testhal/SPC563Mxx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC563Mxx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c new file mode 100644 index 000000000..46378a5f8 --- /dev/null +++ b/testhal/SPC563Mxx/SPI/main.c @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(PORT11, P11_LED1); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(PORT11, P11_LED1); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_B I/O pins setup.*/ + spiStart(&SPID2, &ls_spicfg); + SIU.PCR[102].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SIN */ + SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[0] */ + SIU.PCR[106].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[1] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID2, 4, txbuf, rxbuf); + spiExchange(&SPID2, 32, txbuf, rxbuf); + spiExchange(&SPID2, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID2, 4); + spiIgnore(&SPID2, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID2, 4, txbuf); + spiSend(&SPID2, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID2, 4, rxbuf); + spiReceive(&SPID2, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID2); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT11, P11_LED2); + } + return 0; +} diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h new file mode 100644 index 000000000..6affa7878 --- /dev/null +++ b/testhal/SPC563Mxx/SPI/mcuconf.h @@ -0,0 +1,122 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC563Mxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 80 +#define SPC5_CLK_RFD SPC5_RFD_DIV4 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB TRUE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/SPC563Mxx/SPI/readme.txt b/testhal/SPC563Mxx/SPI/readme.txt new file mode 100644 index 000000000..1e0b7fcc0 --- /dev/null +++ b/testhal/SPC563Mxx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC563Mxx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC564Axx/ICU-PWM/Makefile b/testhal/SPC564Axx/ICU-PWM/Makefile new file mode 100644 index 000000000..bdd72d6ac --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/Makefile @@ -0,0 +1,121 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc564axx_1.0.0.201305101230/component/lib/rsc/rules.mk diff --git a/testhal/SPC564Axx/ICU-PWM/chconf.h b/testhal/SPC564Axx/ICU-PWM/chconf.h new file mode 100644 index 000000000..b4c46c7f6 --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/chconf.h @@ -0,0 +1,536 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES FALSE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/ICU-PWM/halconf.h b/testhal/SPC564Axx/ICU-PWM/halconf.h new file mode 100644 index 000000000..24462dafd --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/ICU-PWM/main.c b/testhal/SPC564Axx/ICU-PWM/main.c new file mode 100644 index 000000000..9f175890c --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/main.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT11, P11_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT11, P11_LED1); +} + +static PWMConfig pwmcfg = { + 187500, /* 187500Hz PWM clock frequency.*/ + 19500, /* Initial PWM period 0.1040s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT11, P11_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT11, P11_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 187500, /* 187500Hz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* Initialization of all the imported components in the order specified in + the application wizard. The function is generated automatically.*/ + componentsInit(); + + palClearPad(PORT11, P11_LED4); + + /* + * Initializes the PWM driver 6 and ICU driver 3. + * PIN78 is the PWM output. + * PIN65 is the ICU input. + * The two pins have to be externally connected together. + */ + + /* Sets PIN65 alternative function.*/ + SIU.PCR[181].R = 0b0000010100001100; + + /* Sets PIN78 alternative function.*/ + SIU.PCR[193].R = 0b0000011000001100; + + icuStart(&ICUD3, &icucfg); + icuEnable(&ICUD3); + pwmStart(&PWMD6, &pwmcfg); + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD6, 25000); + pwmEnableChannel(&PWMD6, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD6, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables PWM channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD6, 0); + pwmStop(&PWMD6); + + /* + * Disables and stops the ICU drivers. + */ + + icuDisable(&ICUD3); + icuStop(&ICUD3); + + palClearPad(PORT11, P11_LED3); + palClearPad(PORT11, P11_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC564Axx/ICU-PWM/mcuconf.h b/testhal/SPC564Axx/ICU-PWM/mcuconf.h new file mode 100644 index 000000000..a2e46cd16 --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/mcuconf.h @@ -0,0 +1,108 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC564Axx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC564Axx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 75 +#define SPC5_CLK_RFD SPC5_RFD_DIV2 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_PRIO 12 +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB FALSE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 + +/* + * ICU - PWM driver system settings. + */ +#define SPC5_ICU_USE_EMIOS_CH0 TRUE +#define SPC5_ICU_USE_EMIOS_CH1 TRUE +#define SPC5_ICU_USE_EMIOS_CH2 TRUE +#define SPC5_ICU_USE_EMIOS_CH3 TRUE +#define SPC5_ICU_USE_EMIOS_CH4 TRUE +#define SPC5_ICU_USE_EMIOS_CH5 TRUE +#define SPC5_ICU_USE_EMIOS_CH6 TRUE +#define SPC5_ICU_USE_EMIOS_CH7 TRUE +#define SPC5_ICU_USE_EMIOS_CH8 TRUE +#define SPC5_ICU_USE_EMIOS_CH16 TRUE +#define SPC5_ICU_USE_EMIOS_CH17 TRUE +#define SPC5_ICU_USE_EMIOS_CH18 TRUE + +#define SPC5_PWM_USE_EMIOS_CH9 TRUE +#define SPC5_PWM_USE_EMIOS_CH10 TRUE +#define SPC5_PWM_USE_EMIOS_CH11 TRUE +#define SPC5_PWM_USE_EMIOS_CH12 TRUE +#define SPC5_PWM_USE_EMIOS_CH13 TRUE +#define SPC5_PWM_USE_EMIOS_CH14 TRUE +#define SPC5_PWM_USE_EMIOS_CH15 TRUE +#define SPC5_PWM_USE_EMIOS_CH19 TRUE +#define SPC5_PWM_USE_EMIOS_CH20 TRUE +#define SPC5_PWM_USE_EMIOS_CH21 TRUE +#define SPC5_PWM_USE_EMIOS_CH22 TRUE +#define SPC5_PWM_USE_EMIOS_CH23 TRUE + +#define SPC5_EMIOS_GLOBAL_PRESCALER 200 diff --git a/testhal/SPC564Axx/ICU-PWM/readme.txt b/testhal/SPC564Axx/ICU-PWM/readme.txt new file mode 100644 index 000000000..01668f205 --- /dev/null +++ b/testhal/SPC564Axx/ICU-PWM/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - ICU-PWM driver demo for SPC564Axx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC564Axx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC564Axx ICU and PWM drivers. + +** Board Setup ** + +Connect PIN65 and PIN78 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC564Axx/SPI/.cproject b/testhal/SPC564Axx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC564Axx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC564Axx/SPI/.project b/testhal/SPC564Axx/SPI/.project new file mode 100644 index 000000000..bb29d6206 --- /dev/null +++ b/testhal/SPC564Axx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC564Axx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC564A + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC564Axx/SPI/Makefile b/testhal/SPC564Axx/SPI/Makefile new file mode 100644 index 000000000..200b9191d --- /dev/null +++ b/testhal/SPC564Axx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC564A/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC564Axx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC564Axx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC564A70.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC564A70L7_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC564Axx/SPI/chconf.h b/testhal/SPC564Axx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC564Axx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/SPI/halconf.h b/testhal/SPC564Axx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC564Axx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC564Axx/SPI/main.c b/testhal/SPC564Axx/SPI/main.c new file mode 100644 index 000000000..46378a5f8 --- /dev/null +++ b/testhal/SPC564Axx/SPI/main.c @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(PORT11, P11_LED1); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(PORT11, P11_LED1); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_B I/O pins setup.*/ + spiStart(&SPID2, &ls_spicfg); + SIU.PCR[102].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SIN */ + SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[0] */ + SIU.PCR[106].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[1] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID2, 4, txbuf, rxbuf); + spiExchange(&SPID2, 32, txbuf, rxbuf); + spiExchange(&SPID2, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID2, 4); + spiIgnore(&SPID2, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID2, 4, txbuf); + spiSend(&SPID2, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID2, 4, rxbuf); + spiReceive(&SPID2, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID2); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT11, P11_LED2); + } + return 0; +} diff --git a/testhal/SPC564Axx/SPI/mcuconf.h b/testhal/SPC564Axx/SPI/mcuconf.h new file mode 100644 index 000000000..2fccca076 --- /dev/null +++ b/testhal/SPC564Axx/SPI/mcuconf.h @@ -0,0 +1,139 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC563Mxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC564Axx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_CLK_BYPASS FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_CLK_PREDIV_VALUE 2 +#define SPC5_CLK_MFD_VALUE 75 +#define SPC5_CLK_RFD SPC5_RFD_DIV2 +#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * ADC driver settings. + */ +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(10) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} + +/* + * SERIAL driver system settings. + */ +#define SPC5_USE_ESCIA TRUE +#define SPC5_USE_ESCIB TRUE +#define SPC5_USE_ESCIC TRUE +#define SPC5_ESCIA_PRIORITY 8 +#define SPC5_ESCIB_PRIORITY 8 +#define SPC5_ESCIC_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/SPC564Axx/SPI/readme.txt b/testhal/SPC564Axx/SPI/readme.txt new file mode 100644 index 000000000..cd9368fb1 --- /dev/null +++ b/testhal/SPC564Axx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC564Axx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC564Axx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC564Axx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC56ELxx/CAN/.cproject b/testhal/SPC56ELxx/CAN/.cproject new file mode 100644 index 000000000..dd958292f --- /dev/null +++ b/testhal/SPC56ELxx/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC56ELxx/CAN/.project b/testhal/SPC56ELxx/CAN/.project new file mode 100644 index 000000000..80fb08c6f --- /dev/null +++ b/testhal/SPC56ELxx/CAN/.project @@ -0,0 +1,38 @@ + + + SPC56ELxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC56EL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC56ELxx/CAN/Makefile b/testhal/SPC56ELxx/CAN/Makefile new file mode 100644 index 000000000..79d8dd648 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/Makefile @@ -0,0 +1,139 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti -fno-exceptions +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC56EL60L3 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc56elxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC56ELxx/CAN/chconf.h b/testhal/SPC56ELxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/CAN/halconf.h b/testhal/SPC56ELxx/CAN/halconf.h new file mode 100644 index 000000000..7c9fe78a8 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/CAN/main.c b/testhal/SPC56ELxx/CAN/main.c new file mode 100644 index 000000000..a0750898a --- /dev/null +++ b/testhal/SPC56ELxx/CAN/main.c @@ -0,0 +1,148 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND1, PD_LED1}; + +/* + * Internal loopback mode, 1MBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#endif + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC56ELxx/CAN/mcuconf.h b/testhal/SPC56ELxx/CAN/mcuconf.h new file mode 100644 index 000000000..212082fc9 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/mcuconf.h @@ -0,0 +1,236 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC56ELxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC56ELxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_SWG_DIVIDER_VALUE 2 +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 TRUE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 TRUE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#define SPC5_CAN_FLEXCAN1_PRIORITY 11 +#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC56ELxx/CAN/readme.txt b/testhal/SPC56ELxx/CAN/readme.txt new file mode 100644 index 000000000..036a5502e --- /dev/null +++ b/testhal/SPC56ELxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC56ELxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC56ELxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC56ELxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC56ELxx/PWM-ICU/.cproject b/testhal/SPC56ELxx/PWM-ICU/.cproject new file mode 100644 index 000000000..dd958292f --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC56ELxx/PWM-ICU/.project b/testhal/SPC56ELxx/PWM-ICU/.project new file mode 100644 index 000000000..80fb08c6f --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + SPC56ELxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC56EL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC56ELxx/PWM-ICU/Makefile b/testhal/SPC56ELxx/PWM-ICU/Makefile new file mode 100644 index 000000000..a6f7718ca --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/Makefile @@ -0,0 +1,167 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC56EL/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC56ELxx/PWM-ICU/chconf.h b/testhal/SPC56ELxx/PWM-ICU/chconf.h new file mode 100644 index 000000000..50d8024a1 --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/chconf.h @@ -0,0 +1,525 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/PWM-ICU/halconf.h b/testhal/SPC56ELxx/PWM-ICU/halconf.h new file mode 100644 index 000000000..09022b9e7 --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/halconf.h @@ -0,0 +1,367 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/PWM-ICU/main.c b/testhal/SPC56ELxx/PWM-ICU/main.c new file mode 100644 index 000000000..e6ac6281f --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/main.c @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(PORT_D, PD_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(PORT_D, PD_LED1); +} + +static PWMConfig pwmcfg = { + 250000, /* 250kHz PWM clock frequency.*/ + 50000, /* Initial PWM period 0.2s.*/ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL} + }, + PWM_ALIGN_EDGE +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(PORT_D, PD_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(PORT_D, PD_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 250000, /* 250kHz ICU clock frequency.*/ + icuwidthcb, + icuperiodcb, + NULL +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* + * Initializes the PWM driver 1 and ICU driver 1. + * GPIOD10 is the PWM output. + * GPIOA0 is the ICU input. + * The two pins have to be externally connected together. + */ + icuStart(&ICUD1, &icucfg); + icuEnable(&ICUD1); + + /* Sets A0 alternative function.*/ + SIU.PCR[0].R = 0b0100010100000100; + + pwmStart(&PWMD1, &pwmcfg); + /* Sets D10 alternative function.*/ + SIU.PCR[58].R = 0b0100010100000100; + + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period and the PWM channel 0 to 50% duty cycle. + */ + pwmChangePeriod(&PWMD1, 25000); + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + icuDisable(&ICUD1); + icuStop(&ICUD1); + palClearPad(PORT_D, PD_LED3); + palClearPad(PORT_D, PD_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..221ad245e --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h @@ -0,0 +1,280 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC56ELxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC56ELxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 60 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 15 +#define SPC5_SWG_DIVIDER_VALUE 2 +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 TRUE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC56ELxx/PWM-ICU/readme.txt b/testhal/SPC56ELxx/PWM-ICU/readme.txt new file mode 100644 index 000000000..b17dba82f --- /dev/null +++ b/testhal/SPC56ELxx/PWM-ICU/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM/ICU drivers demo for SPC56ELxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC56ELxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC56ELxx PWM-ICU drivers. + +** Board Setup ** + +- Connect D10 and A0 together. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC56ELxx/SPI/.cproject b/testhal/SPC56ELxx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC56ELxx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC56ELxx/SPI/.project b/testhal/SPC56ELxx/SPI/.project new file mode 100644 index 000000000..c5157f21e --- /dev/null +++ b/testhal/SPC56ELxx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC56ELxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC56EL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC56ELxx/SPI/Makefile b/testhal/SPC56ELxx/SPI/Makefile new file mode 100644 index 000000000..afc709b93 --- /dev/null +++ b/testhal/SPC56ELxx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC56EL/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC56ELxx/SPI/chconf.h b/testhal/SPC56ELxx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC56ELxx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/SPI/halconf.h b/testhal/SPC56ELxx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC56ELxx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/SPI/main.c b/testhal/SPC56ELxx/SPI/main.c new file mode 100644 index 000000000..ef283f656 --- /dev/null +++ b/testhal/SPC56ELxx/SPI/main.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration. + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(PORT_D, PD_LED1); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(PORT_D, PD_LED1); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_0 I/O pins setup.*/ + spiStart(&SPID1, &ls_spicfg); + SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[36].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */ + SIU.PCR[54].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[2] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID1, 4, txbuf, rxbuf); + spiExchange(&SPID1, 32, txbuf, rxbuf); + spiExchange(&SPID1, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID1, 4); + spiIgnore(&SPID1, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID1, 4, txbuf); + spiSend(&SPID1, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID1, 4, rxbuf); + spiReceive(&SPID1, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID1); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT_D, PD_LED2); + } + return 0; +} diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h new file mode 100644 index 000000000..322a9be56 --- /dev/null +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -0,0 +1,280 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC56ELxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC56ELxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 60 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 15 +#define SPC5_SWG_DIVIDER_VALUE 2 +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 FALSE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 FALSE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 TRUE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC56ELxx/SPI/readme.txt b/testhal/SPC56ELxx/SPI/readme.txt new file mode 100644 index 000000000..96da3df24 --- /dev/null +++ b/testhal/SPC56ELxx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC56ELxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC56ELxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC56ELxx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/STM32F0xx/ADC/.cproject b/testhal/STM32F0xx/ADC/.cproject new file mode 100644 index 000000000..a3fb831a8 --- /dev/null +++ b/testhal/STM32F0xx/ADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/ADC/.project b/testhal/STM32F0xx/ADC/.project new file mode 100644 index 000000000..4aa2b6463 --- /dev/null +++ b/testhal/STM32F0xx/ADC/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/ADC/Makefile b/testhal/STM32F0xx/ADC/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/ADC/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/ADC/chconf.h b/testhal/STM32F0xx/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F0xx/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/ADC/halconf.h b/testhal/STM32F0xx/ADC/halconf.h new file mode 100644 index 000000000..a719ec40a --- /dev/null +++ b/testhal/STM32F0xx/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/ADC/main.c b/testhal/STM32F0xx/ADC/main.c new file mode 100644 index 000000000..90b05df1a --- /dev/null +++ b/testhal/STM32F0xx/ADC/main.c @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 4 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN10. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + ADC_CFGR1_RES_12BIT, /* CFGRR1 */ + ADC_TR(0, 0), /* TR */ + ADC_SMPR_SMP_1P5, /* SMPR */ + ADC_CHSELR_CHSEL10 /* CHSELR */ +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + ADC_CFGR1_RES_12BIT, /* CFGRR1 */ + ADC_TR(0, 0), /* TR */ + ADC_SMPR_SMP_28P5, /* SMPR */ + ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 | + ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17 /* CHSELR */ +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + adcSTM32SetCCR(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + adcSTM32SetCCR(0); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F0xx/ADC/mcuconf.h b/testhal/STM32F0xx/ADC/mcuconf.h new file mode 100644 index 000000000..cca199b9c --- /dev/null +++ b/testhal/STM32F0xx/ADC/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/ADC/readme.txt b/testhal/STM32F0xx/ADC/readme.txt new file mode 100644 index 000000000..704ffb1a6 --- /dev/null +++ b/testhal/STM32F0xx/ADC/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx ADC driver. + +** Board Setup ** + +- Remove the LCD module. +- Connect PC0 to 3.3V and PC1 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/EXT/.cproject b/testhal/STM32F0xx/EXT/.cproject new file mode 100644 index 000000000..818c355d4 --- /dev/null +++ b/testhal/STM32F0xx/EXT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/EXT/.project b/testhal/STM32F0xx/EXT/.project new file mode 100644 index 000000000..301651983 --- /dev/null +++ b/testhal/STM32F0xx/EXT/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/EXT/Makefile b/testhal/STM32F0xx/EXT/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/EXT/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/EXT/chconf.h b/testhal/STM32F0xx/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F0xx/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/EXT/halconf.h b/testhal/STM32F0xx/EXT/halconf.h new file mode 100644 index 000000000..1069ba5c1 --- /dev/null +++ b/testhal/STM32F0xx/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/EXT/main.c b/testhal/STM32F0xx/EXT/main.c new file mode 100644 index 000000000..cdba37eff --- /dev/null +++ b/testhal/STM32F0xx/EXT/main.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led4off(void *arg) { + + (void)arg; + palClearPad(GPIOC, GPIOC_LED4); +} + +/* Triggered when the button is pressed or released. The LED4 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + palSetPad(GPIOC, GPIOC_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led4off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F0xx/EXT/mcuconf.h b/testhal/STM32F0xx/EXT/mcuconf.h new file mode 100644 index 000000000..ea61b3dec --- /dev/null +++ b/testhal/STM32F0xx/EXT/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/EXT/readme.txt b/testhal/STM32F0xx/EXT/readme.txt new file mode 100644 index 000000000..542fc577e --- /dev/null +++ b/testhal/STM32F0xx/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/IRQ_STORM/.cproject b/testhal/STM32F0xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..aea7bcbae --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/IRQ_STORM/.project b/testhal/STM32F0xx/IRQ_STORM/.project new file mode 100644 index 000000000..a3027689a --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/IRQ_STORM/Makefile b/testhal/STM32F0xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/IRQ_STORM/chconf.h b/testhal/STM32F0xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/IRQ_STORM/halconf.h b/testhal/STM32F0xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..d91a792b4 --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/IRQ_STORM/main.c b/testhal/STM32F0xx/IRQ_STORM/main.c new file mode 100644 index 000000000..fd74a54c1 --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/main.c @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOC, GPIOC_LED4); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 1 and GPT drivers 2 and 3. + */ + sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */ + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/STM32F0xx/IRQ_STORM/mcuconf.h b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..1a719e0ce --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/IRQ_STORM/readme.txt b/testhal/STM32F0xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..e56547a46 --- /dev/null +++ b/testhal/STM32F0xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/PWM-ICU/.cproject b/testhal/STM32F0xx/PWM-ICU/.cproject new file mode 100644 index 000000000..b8b1e0f2b --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/PWM-ICU/.project b/testhal/STM32F0xx/PWM-ICU/.project new file mode 100644 index 000000000..60ef1bb65 --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/PWM-ICU/Makefile b/testhal/STM32F0xx/PWM-ICU/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/PWM-ICU/chconf.h b/testhal/STM32F0xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/PWM-ICU/halconf.h b/testhal/STM32F0xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..501792854 --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/PWM-ICU/main.c b/testhal/STM32F0xx/PWM-ICU/main.c new file mode 100644 index 000000000..de6191c01 --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/main.c @@ -0,0 +1,143 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOC, GPIOC_LED4); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOC, GPIOC_LED4); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOC, GPIOC_LED3); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOC, GPIOC_LED3); + last_period = icuGetPeriod(icup); +} + +static void icuoverflowcb(ICUDriver *icup) { + + (void)icup; +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + icuoverflowcb, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA6 is the ICU input (CH1). + * GPIOA15 is the PWM output (CH1). + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(2)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(1)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOC, GPIOC_LED3); + palClearPad(GPIOC, GPIOC_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F0xx/PWM-ICU/mcuconf.h b/testhal/STM32F0xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..8e7779960 --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/PWM-ICU/readme.txt b/testhal/STM32F0xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..eccb291d3 --- /dev/null +++ b/testhal/STM32F0xx/PWM-ICU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx PWM-ICU drivers. + +** Board Setup ** + +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/SPI/.cproject b/testhal/STM32F0xx/SPI/.cproject new file mode 100644 index 000000000..d5cace391 --- /dev/null +++ b/testhal/STM32F0xx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/SPI/.project b/testhal/STM32F0xx/SPI/.project new file mode 100644 index 000000000..be544ce50 --- /dev/null +++ b/testhal/STM32F0xx/SPI/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/SPI/Makefile b/testhal/STM32F0xx/SPI/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/SPI/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/SPI/chconf.h b/testhal/STM32F0xx/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F0xx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/SPI/halconf.h b/testhal/STM32F0xx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/STM32F0xx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/SPI/main.c b/testhal/STM32F0xx/SPI/main.c new file mode 100644 index 000000000..0f6313022 --- /dev/null +++ b/testhal/STM32F0xx/SPI/main.c @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOC, GPIOC_LED4); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOC, GPIOC_LED4); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(0) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F0xx/SPI/mcuconf.h b/testhal/STM32F0xx/SPI/mcuconf.h new file mode 100644 index 000000000..cf60d78be --- /dev/null +++ b/testhal/STM32F0xx/SPI/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/SPI/readme.txt b/testhal/STM32F0xx/SPI/readme.txt new file mode 100644 index 000000000..636a7c248 --- /dev/null +++ b/testhal/STM32F0xx/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F0xx/UART/.cproject b/testhal/STM32F0xx/UART/.cproject new file mode 100644 index 000000000..9dc8b7121 --- /dev/null +++ b/testhal/STM32F0xx/UART/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F0xx/UART/.project b/testhal/STM32F0xx/UART/.project new file mode 100644 index 000000000..d05252ac5 --- /dev/null +++ b/testhal/STM32F0xx/UART/.project @@ -0,0 +1,38 @@ + + + STM32F0xx-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F0_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F0xx/UART/Makefile b/testhal/STM32F0xx/UART/Makefile new file mode 100644 index 000000000..0b2d556fb --- /dev/null +++ b/testhal/STM32F0xx/UART/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F051x8.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F0xx/UART/chconf.h b/testhal/STM32F0xx/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F0xx/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/UART/halconf.h b/testhal/STM32F0xx/UART/halconf.h new file mode 100644 index 000000000..a4fc70926 --- /dev/null +++ b/testhal/STM32F0xx/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F0xx/UART/main.c b/testhal/STM32F0xx/UART/main.c new file mode 100644 index 000000000..aa52aeb77 --- /dev/null +++ b/testhal/STM32F0xx/UART/main.c @@ -0,0 +1,144 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromIsr(); + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); + chSysUnlockFromIsr(); +} + +static void ledoff(void *p) { + + (void)p; + palClearPad(GPIOC, GPIOC_LED4); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOC, GPIOC_LED4); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palClearPad(GPIOC, GPIOC_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOC, GPIOC_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1, PA9 and PA10 are routed to USART1. + */ + uartStart(&UARTD1, &uart_cfg_1); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */ + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F0xx/UART/mcuconf.h b/testhal/STM32F0xx/UART/mcuconf.h new file mode 100644 index 000000000..fb5ea8f3d --- /dev/null +++ b/testhal/STM32F0xx/UART/mcuconf.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F0xx/UART/readme.txt b/testhal/STM32F0xx/UART/readme.txt new file mode 100644 index 000000000..921f1bc8e --- /dev/null +++ b/testhal/STM32F0xx/UART/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F0xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F0-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F0xx UART driver. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/ADC/Makefile b/testhal/STM32F1xx/ADC/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/ADC/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/ADC/chconf.h b/testhal/STM32F1xx/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/ADC/halconf.h b/testhal/STM32F1xx/ADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F1xx/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/ADC/main.c b/testhal/STM32F1xx/ADC/main.c new file mode 100644 index 000000000..43ae179ee --- /dev/null +++ b/testhal/STM32F1xx/ADC/main.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN10. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, 0, /* CR1, CR2 */ + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, ADC_CR2_TSVREFE, /* CR1, CR2 */ + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_239P5), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), + ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + adcStopConversion(&ADCD1); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/ADC/mcuconf.h b/testhal/STM32F1xx/ADC/mcuconf.h new file mode 100644 index 000000000..1b3927677 --- /dev/null +++ b/testhal/STM32F1xx/ADC/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/ADC/readme.txt b/testhal/STM32F1xx/ADC/readme.txt new file mode 100644 index 000000000..1502425f4 --- /dev/null +++ b/testhal/STM32F1xx/ADC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 ADC driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/CAN/Makefile b/testhal/STM32F1xx/CAN/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/CAN/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/CAN/chconf.h b/testhal/STM32F1xx/CAN/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F1xx/CAN/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/CAN/halconf.h b/testhal/STM32F1xx/CAN/halconf.h new file mode 100644 index 000000000..5b6535967 --- /dev/null +++ b/testhal/STM32F1xx/CAN/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/CAN/main.c b/testhal/STM32F1xx/CAN/main.c new file mode 100644 index 000000000..43164e1ce --- /dev/null +++ b/testhal/STM32F1xx/CAN/main.c @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Internal loopback mode, 500KBaud, automatic wakeup, automatic recover + * from abort mode. + * See section 22.7.7 on the STM32 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + CAN_BTR_LBKM | CAN_BTR_SJW(0) | CAN_BTR_TS2(1) | + CAN_BTR_TS1(8) | CAN_BTR_BRP(6) +}; + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + EventListener el; + CANRxFrame rxmsg; + + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&CAND1.rxfull_event, &el, 0); + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; + while (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(IOPORT3, GPIOC_LED); + } + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.DLC = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, can_rx, NULL); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, can_tx, NULL); + + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/CAN/mcuconf.h b/testhal/STM32F1xx/CAN/mcuconf.h new file mode 100644 index 000000000..06bc8c715 --- /dev/null +++ b/testhal/STM32F1xx/CAN/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/CAN/readme.txt b/testhal/STM32F1xx/CAN/readme.txt new file mode 100644 index 000000000..b78112885 --- /dev/null +++ b/testhal/STM32F1xx/CAN/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 CAN driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/EXT/Makefile b/testhal/STM32F1xx/EXT/Makefile new file mode 100644 index 000000000..e9b6719d7 --- /dev/null +++ b/testhal/STM32F1xx/EXT/Makefile @@ -0,0 +1,208 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/EXT/chconf.h b/testhal/STM32F1xx/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h new file mode 100644 index 000000000..e0e0c38ff --- /dev/null +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT/main.c b/testhal/STM32F1xx/EXT/main.c new file mode 100644 index 000000000..e0fcd896c --- /dev/null +++ b/testhal/STM32F1xx/EXT/main.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt; + +/* LED set to OFF after 200mS.*/ +static void ledoff(void *arg) { + + (void)arg; + palSetPad(GPIOC, GPIOC_LED); +} + +/* Triggered when the button is pressed or released. The LED is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + palClearPad(GPIOC, GPIOC_LED); + chSysLockFromIsr(); + if (!chVTIsArmedI(&vt)) + chVTSetI(&vt, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* Triggered when the LED goes OFF.*/ +static void extcb2(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOC, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h new file mode 100644 index 000000000..d7d712736 --- /dev/null +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/EXT/readme.txt b/testhal/STM32F1xx/EXT/readme.txt new file mode 100644 index 000000000..48288c565 --- /dev/null +++ b/testhal/STM32F1xx/EXT/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 EXT driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/GPT/Makefile b/testhal/STM32F1xx/GPT/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/GPT/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/GPT/chconf.h b/testhal/STM32F1xx/GPT/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F1xx/GPT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/GPT/halconf.h b/testhal/STM32F1xx/GPT/halconf.h new file mode 100644 index 000000000..554b4e9ca --- /dev/null +++ b/testhal/STM32F1xx/GPT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/GPT/main.c b/testhal/STM32F1xx/GPT/main.c new file mode 100644 index 000000000..f14ffd941 --- /dev/null +++ b/testhal/STM32F1xx/GPT/main.c @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * GPT1 callback. + */ +static void gpt1cb(GPTDriver *gptp) { + + (void)gptp; + palClearPad(IOPORT3, GPIOC_LED); + chSysLockFromIsr(); + gptStartOneShotI(&GPTD2, 200); /* 0.02 second pulse.*/ + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + + (void)gptp; + palSetPad(IOPORT3, GPIOC_LED); +} + +/* + * GPT1 configuration. + */ +static const GPTConfig gpt1cfg = { + 10000, /* 10kHz timer clock.*/ + gpt1cb /* Timer callback.*/ +}; + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 10000, /* 10kHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the GPT drivers 1 and 2. + */ + gptStart(&GPTD1, &gpt1cfg); + gptPolledDelay(&GPTD1, 10); /* Small delay.*/ + gptStart(&GPTD2, &gpt2cfg); + gptPolledDelay(&GPTD2, 10); /* Small delay.*/ + + /* + * Normal main() thread activity, it changes the GPT1 period every + * five seconds. + */ + while (TRUE) { + gptStartContinuous(&GPTD1, 5000); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD1); + gptStartContinuous(&GPTD1, 2500); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD1); + } + return 0; +} diff --git a/testhal/STM32F1xx/GPT/mcuconf.h b/testhal/STM32F1xx/GPT/mcuconf.h new file mode 100644 index 000000000..e987d18f5 --- /dev/null +++ b/testhal/STM32F1xx/GPT/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/GPT/readme.txt b/testhal/STM32F1xx/GPT/readme.txt new file mode 100644 index 000000000..2355ef173 --- /dev/null +++ b/testhal/STM32F1xx/GPT/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - GPT driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo will on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 GPT driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/I2C/Makefile b/testhal/STM32F1xx/I2C/Makefile new file mode 100644 index 000000000..24cebda3b --- /dev/null +++ b/testhal/STM32F1xx/I2C/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra + #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_103STK/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c \ + i2c_pns.c \ + tmp75.c \ + fake.c \ + lis3.c + + + + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. + +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk + + diff --git a/testhal/STM32F1xx/I2C/chconf.h b/testhal/STM32F1xx/I2C/chconf.h new file mode 100644 index 000000000..c1dec4b48 --- /dev/null +++ b/testhal/STM32F1xx/I2C/chconf.h @@ -0,0 +1,505 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 0//20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/I2C/fake.c b/testhal/STM32F1xx/I2C/fake.c new file mode 100644 index 000000000..74fc44539 --- /dev/null +++ b/testhal/STM32F1xx/I2C/fake.c @@ -0,0 +1,61 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * Not responding slave test + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "fake.h" + + +/* input buffer */ +static uint8_t rx_data[2]; + +/* temperature value */ +static int16_t temperature = 0; + +static i2cflags_t errors = 0; + +#define addr 0b1001100 + +/* This is main function. */ +void request_fake(void){ + msg_t status = RDY_OK; + systime_t tmo = MS2ST(4); + + i2cAcquireBus(&I2CD1); + status = i2cMasterReceiveTimeout(&I2CD1, addr, rx_data, 2, tmo); + i2cReleaseBus(&I2CD1); + + if (status == RDY_RESET){ + errors = i2cGetErrors(&I2CD1); + if (errors == I2CD_ACK_FAILURE){ + /* there is no slave with given address on the bus, or it was die */ + return; + } + } + + else{ + temperature = (rx_data[0] << 8) + rx_data[1]; + } +} + + diff --git a/testhal/STM32F1xx/I2C/fake.h b/testhal/STM32F1xx/I2C/fake.h new file mode 100644 index 000000000..2869b0c93 --- /dev/null +++ b/testhal/STM32F1xx/I2C/fake.h @@ -0,0 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef FAKE_H_ +#define FAKE_H_ + +void request_fake(void); + +#endif /* FAKE_H_ */ diff --git a/testhal/STM32F1xx/I2C/halconf.h b/testhal/STM32F1xx/I2C/halconf.h new file mode 100644 index 000000000..3ac5de5ba --- /dev/null +++ b/testhal/STM32F1xx/I2C/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/I2C/i2c_pns.c b/testhal/STM32F1xx/I2C/i2c_pns.c new file mode 100644 index 000000000..3cb568ce8 --- /dev/null +++ b/testhal/STM32F1xx/I2C/i2c_pns.c @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "i2c_pns.h" +#include "lis3.h" + + +/* I2C1 */ +static const I2CConfig i2cfg1 = { + OPMODE_I2C, + 400000, + FAST_DUTY_CYCLE_2, +}; + + + +void I2CInit_pns(void){ + i2cInit(); + + i2cStart(&I2CD1, &i2cfg1); + + /* tune ports for I2C1*/ + palSetPadMode(IOPORT2, 6, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + palSetPadMode(IOPORT2, 7, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + + chThdSleepMilliseconds(100); /* Just to be safe. */ + + init_lis3(); /* accelerometer init */ +} + + diff --git a/testhal/STM32F1xx/I2C/i2c_pns.h b/testhal/STM32F1xx/I2C/i2c_pns.h new file mode 100644 index 000000000..b01c85b7e --- /dev/null +++ b/testhal/STM32F1xx/I2C/i2c_pns.h @@ -0,0 +1,24 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef I2C_PNS_H_ +#define I2C_PNS_H_ + + +void I2CInit_pns(void); + + +#endif /* I2C_PNS_H_ */ diff --git a/testhal/STM32F1xx/I2C/lis3.c b/testhal/STM32F1xx/I2C/lis3.c new file mode 100644 index 000000000..e55d1180e --- /dev/null +++ b/testhal/STM32F1xx/I2C/lis3.c @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * This is device realize "read through write" paradigm. This is not + * standard, but most of I2C devices use this paradigm. + * You must write to device reading address, send restart to bus, + * and then begin reading process. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "lis3.h" + + +#define lis3_addr 0b0011101 + + +/* buffers */ +static uint8_t accel_rx_data[ACCEL_RX_DEPTH]; +static uint8_t accel_tx_data[ACCEL_TX_DEPTH]; + +static i2cflags_t errors = 0; + +static int16_t acceleration_x = 0; +static int16_t acceleration_y = 0; +static int16_t acceleration_z = 0; + + +/** + * Init function. Here we will also start personal serving thread. + */ +int init_lis3(void){ + msg_t status = RDY_OK; + systime_t tmo = MS2ST(4); + + /* configure accelerometer */ + accel_tx_data[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; /* register address */ + accel_tx_data[1] = 0b11100111; + accel_tx_data[2] = 0b01000001; + accel_tx_data[3] = 0b00000000; + + /* sending */ + i2cAcquireBus(&I2CD1); + status = i2cMasterTransmitTimeout(&I2CD1, lis3_addr, accel_tx_data, 4, accel_rx_data, 0, tmo); + i2cReleaseBus(&I2CD1); + + if (status != RDY_OK){ + errors = i2cGetErrors(&I2CD1); + } + + return 0; +} + +/** + * + */ +void request_acceleration_data(void){ + msg_t status = RDY_OK; + systime_t tmo = MS2ST(4); + + accel_tx_data[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; /* register address */ + i2cAcquireBus(&I2CD1); + status = i2cMasterTransmitTimeout(&I2CD1, lis3_addr, accel_tx_data, 1, accel_rx_data, 6, tmo); + i2cReleaseBus(&I2CD1); + + if (status != RDY_OK){ + errors = i2cGetErrors(&I2CD1); + } + + acceleration_x = accel_rx_data[0] + (accel_rx_data[1] << 8); + acceleration_y = accel_rx_data[2] + (accel_rx_data[3] << 8); + acceleration_z = accel_rx_data[4] + (accel_rx_data[5] << 8); +} + diff --git a/testhal/STM32F1xx/I2C/lis3.h b/testhal/STM32F1xx/I2C/lis3.h new file mode 100644 index 000000000..f48b7cd20 --- /dev/null +++ b/testhal/STM32F1xx/I2C/lis3.h @@ -0,0 +1,44 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "ch.h" + +#ifndef LIS3_H_ +#define LIS3_H_ + + + +/* buffers depth */ +#define ACCEL_RX_DEPTH 8 +#define ACCEL_TX_DEPTH 8 + +/* autoincrement bit position. This bit needs to perform reading of + * multiple bytes at one request */ +#define AUTO_INCREMENT_BIT (1<<7) + +/* slave specific addresses */ +#define ACCEL_STATUS_REG 0x27 +#define ACCEL_CTRL_REG1 0x20 +#define ACCEL_OUT_DATA 0x28 + + + +inline int init_lis3(void); +inline void request_acceleration_data(void); + + +#endif /* LIS3_H_ */ diff --git a/testhal/STM32F1xx/I2C/main.c b/testhal/STM32F1xx/I2C/main.c new file mode 100644 index 000000000..cba3dad3a --- /dev/null +++ b/testhal/STM32F1xx/I2C/main.c @@ -0,0 +1,135 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "i2c_pns.h" +#include "lis3.h" +#include "tmp75.h" +#include "fake.h" + + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(BlinkWA, 64); +static msg_t Blink(void *arg) { + chRegSetThreadName("Blink"); + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Accelerometer thread + */ +static WORKING_AREA(PollAccelThreadWA, 256); +static msg_t PollAccelThread(void *arg) { + chRegSetThreadName("PollAccel"); + (void)arg; + while (TRUE) { + /*chThdSleepMilliseconds(rand() & 31);*/ + chThdSleepMilliseconds(32); + request_acceleration_data(); + } + return 0; +} + + +/* Temperature polling thread */ +static WORKING_AREA(PollTmp75ThreadWA, 256); +static msg_t PollTmp75Thread(void *arg) { + chRegSetThreadName("PollTmp75"); + (void)arg; + while (TRUE) { + /*chThdSleepMilliseconds(rand() & 31);*/ + chThdSleepMilliseconds(15); + /* Call reading function */ + request_temperature(); + } + return 0; +} + + +/* Temperature polling thread */ +static WORKING_AREA(PollFakeThreadWA, 256); +static msg_t PollFakeThread(void *arg) { + chRegSetThreadName("PollFake"); + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(16); + /* Call reading function */ + request_fake(); + } + return 0; +} + + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(void) { + + halInit(); + chSysInit(); + + chThdSleepMilliseconds(200); + I2CInit_pns(); + + /* Create accelerometer thread */ + chThdCreateStatic(PollAccelThreadWA, + sizeof(PollAccelThreadWA), + NORMALPRIO, + PollAccelThread, + NULL); + + /* Create temperature thread */ + chThdCreateStatic(PollTmp75ThreadWA, + sizeof(PollTmp75ThreadWA), + NORMALPRIO, + PollTmp75Thread, + NULL); + + /* Create not responding thread */ + chThdCreateStatic(PollFakeThreadWA, + sizeof(PollFakeThreadWA), + NORMALPRIO, + PollFakeThread, + NULL); + + /* Creates the blinker thread. */ + chThdCreateStatic(BlinkWA, sizeof(BlinkWA), HIGHPRIO, Blink, NULL); + + /* main loop that do nothing */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + + return 0; +} diff --git a/testhal/STM32F1xx/I2C/mcuconf.h b/testhal/STM32F1xx/I2C/mcuconf.h new file mode 100644 index 000000000..a5748e0e8 --- /dev/null +++ b/testhal/STM32F1xx/I2C/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/I2C/tmp75.c b/testhal/STM32F1xx/I2C/tmp75.c new file mode 100644 index 000000000..478c322fa --- /dev/null +++ b/testhal/STM32F1xx/I2C/tmp75.c @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * TMP75 is most simple I2C device in our case. It is already useful with + * default settings after powerup. + * You only must read 2 sequential bytes from it. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "tmp75.h" + + +/* input buffer */ +static uint8_t tmp75_rx_data[TMP75_RX_DEPTH]; + +/* temperature value */ +static int16_t temperature = 0; + +static i2cflags_t errors = 0; + +#define tmp75_addr 0b1001000 + +/* This is main function. */ +void request_temperature(void){ + int16_t t_int = 0, t_frac = 0; + msg_t status = RDY_OK; + systime_t tmo = MS2ST(4); + + i2cAcquireBus(&I2CD1); + status = i2cMasterReceiveTimeout(&I2CD1, tmp75_addr, tmp75_rx_data, 2, tmo); + i2cReleaseBus(&I2CD1); + + if (status != RDY_OK){ + errors = i2cGetErrors(&I2CD1); + } + + t_int = tmp75_rx_data[0] * 100; + t_frac = (tmp75_rx_data[1] * 100) >> 8; + temperature = t_int + t_frac; +} + + diff --git a/testhal/STM32F1xx/I2C/tmp75.h b/testhal/STM32F1xx/I2C/tmp75.h new file mode 100644 index 000000000..57729b9db --- /dev/null +++ b/testhal/STM32F1xx/I2C/tmp75.h @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef TMP75_H_ +#define TMP75_H_ + + + +/* buffers depth */ +#define TMP75_RX_DEPTH 2 +#define TMP75_TX_DEPTH 2 + +void init_tmp75(void); +void request_temperature(void); + +#endif /* TMP75_H_ */ diff --git a/testhal/STM32F1xx/IRQ_STORM/Makefile b/testhal/STM32F1xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/IRQ_STORM/chconf.h b/testhal/STM32F1xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/IRQ_STORM/halconf.h b/testhal/STM32F1xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/IRQ_STORM/main.c b/testhal/STM32F1xx/IRQ_STORM/main.c new file mode 100644 index 000000000..8961668b0 --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/main.c @@ -0,0 +1,326 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOC, GPIOC_LED); + } + } + } +} + +/* + * GPT1 callback. + */ +static void gpt1cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT1 configuration. + */ +static const GPTConfig gpt1cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt1cb /* Timer callback.*/ +}; + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } + chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 1 and 2. + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + gptStart(&GPTD1, &gpt1cfg); + gptStart(&GPTD2, &gpt2cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD2, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD1); + gptStopTimer(&GPTD2); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..e607b235c --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 6 +#define STM32_GPT_TIM2_IRQ_PRIORITY 10 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/IRQ_STORM/readme.txt b/testhal/STM32F1xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..32f5a3781 --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ-STORM demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32F1xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/PWM-ICU/Makefile b/testhal/STM32F1xx/PWM-ICU/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/PWM-ICU/chconf.h b/testhal/STM32F1xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/PWM-ICU/halconf.h b/testhal/STM32F1xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..2f74c82c8 --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/PWM-ICU/main.c b/testhal/STM32F1xx/PWM-ICU/main.c new file mode 100644 index 000000000..a2ba2a12d --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/main.c @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(IOPORT3, GPIOC_LED); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(IOPORT3, GPIOC_LED); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +#if STM32_PWM_USE_ADVANCED + 0 +#endif +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * LED initially off. + */ + palSetPad(IOPORT3, GPIOC_LED); + + /* + * Initializes the PWM driver 1 and ICU driver 4. + */ + pwmStart(&PWMD1, &pwmcfg); + palSetPadMode(IOPORT1, 8, PAL_MODE_STM32_ALTERNATE_PUSHPULL); + icuStart(&ICUD4, &icucfg); + icuEnable(&ICUD4); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD1, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + icuDisable(&ICUD4); + icuStop(&ICUD4); + palSetPad(IOPORT3, GPIOC_LED); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/PWM-ICU/mcuconf.h b/testhal/STM32F1xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..de845bbbe --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/PWM-ICU/readme.txt b/testhal/STM32F1xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..55ffef2cf --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM/ICU driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 PWM and ICU drivers. Pins +PA8 and PB6 must be connected in order to trigger the ICU input with the +PWM output. The ICU unit will measure the generated PWM. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/RTC/Makefile b/testhal/STM32F1xx/RTC/Makefile new file mode 100644 index 000000000..3d28124f2 --- /dev/null +++ b/testhal/STM32F1xx/RTC/Makefile @@ -0,0 +1,211 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/chrtclib.c \ + main.c \ + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. + +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/RTC/chconf.h b/testhal/STM32F1xx/RTC/chconf.h new file mode 100644 index 000000000..c1dec4b48 --- /dev/null +++ b/testhal/STM32F1xx/RTC/chconf.h @@ -0,0 +1,505 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 0//20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h new file mode 100644 index 000000000..388e9a080 --- /dev/null +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c new file mode 100644 index 000000000..1d43b33ad --- /dev/null +++ b/testhal/STM32F1xx/RTC/main.c @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "chrtclib.h" + +RTCTime timespec; +RTCAlarm alarmspec; + +#define TEST_ALARM_WAKEUP FALSE + + +#if TEST_ALARM_WAKEUP + +/* sleep indicator thread */ +static WORKING_AREA(blinkWA, 128); +static msg_t blink_thd(void *arg){ + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(100); + palTogglePad(GPIOC, GPIOC_LED); + } + return 0; +} + +int main(void) { + halInit(); + chSysInit(); + + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + /* set alarm in near future */ + rtcGetTime(&RTCD1, ×pec); + alarmspec.tv_sec = timespec.tv_sec + 30; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + + while (TRUE){ + chThdSleepSeconds(10); + chSysLock(); + + /* going to anabiosis*/ + PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + } + return 0; +} + +#else /* TEST_ALARM_WAKEUP */ + +/* Manually reloaded test alarm period.*/ +#define RTC_ALARMPERIOD 10 + +BinarySemaphore alarm_sem; + +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + switch (event) { + case RTC_EVENT_OVERFLOW: + palTogglePad(GPIOC, GPIOC_LED); + break; + case RTC_EVENT_SECOND: + /* palTogglePad(GPIOC, GPIOC_LED); */ + break; + case RTC_EVENT_ALARM: + palTogglePad(GPIOC, GPIOC_LED); + chSysLockFromIsr(); + chBSemSignalI(&alarm_sem); + chSysUnlockFromIsr(); + break; + } +} + +int main(void) { + msg_t status = RDY_TIMEOUT; + + halInit(); + chSysInit(); + chBSemInit(&alarm_sem, TRUE); + + rtcGetTime(&RTCD1, ×pec); + alarmspec.tv_sec = timespec.tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + + rtcSetCallback(&RTCD1, my_cb); + while (TRUE){ + + /* Wait until alarm callback signaled semaphore.*/ + status = chBSemWaitTimeout(&alarm_sem, S2ST(RTC_ALARMPERIOD + 5)); + + if (status == RDY_TIMEOUT){ + chSysHalt(); + } + else{ + rtcGetTime(&RTCD1, ×pec); + alarmspec.tv_sec = timespec.tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + } + } + return 0; +} +#endif /* TEST_ALARM_WAKEUP */ diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h new file mode 100644 index 000000000..589b599d4 --- /dev/null +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/RTC_FATTIME/Makefile b/testhal/STM32F1xx/RTC_FATTIME/Makefile new file mode 100644 index 000000000..347169ba9 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/Makefile @@ -0,0 +1,213 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_103STK/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/chrtclib.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various $(FATFSINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/RTC_FATTIME/chconf.h b/testhal/STM32F1xx/RTC_FATTIME/chconf.h new file mode 100644 index 000000000..f29e139f7 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC_FATTIME/ffconf.h b/testhal/STM32F1xx/RTC_FATTIME/ffconf.h new file mode 100644 index 000000000..a4816e845 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1251 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 1 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/testhal/STM32F1xx/RTC_FATTIME/halconf.h b/testhal/STM32F1xx/RTC_FATTIME/halconf.h new file mode 100644 index 000000000..54be7f5e8 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC_FATTIME/main.c b/testhal/STM32F1xx/RTC_FATTIME/main.c new file mode 100644 index 000000000..c229830d0 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/main.c @@ -0,0 +1,570 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "usb_cdc.h" +#include "shell.h" +#include "chprintf.h" +#include "chrtclib.h" +#include "ff.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USB_CDC_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USB_CDC_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USB_CDC_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 1, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USB_CDC_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USB_CDC_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0}; + +/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, + SPI_CR1_BR_2 | SPI_CR1_BR_1}; + +/* MMC/SD over SPI driver configuration.*/ +static MMCConfig mmccfg = {&SPID2, &ls_spicfg, &hs_spicfg}; + +/** + * + */ +bool_t mmc_lld_is_write_protected(MMCDriver *sdcp) { + (void)sdcp; + return FALSE; +} + +/** + * + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *sdcp) { + (void)sdcp; + return !palReadPad(GPIOC, GPIOC_MMCCP); +} + +/** + * + */ +void cmd_sdiotest(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argc; + (void)argv; + FRESULT err; + uint32_t clusters; + FATFS *fsp; + FIL FileObject; + //FILINFO FileInfo; + size_t bytes_written; + struct tm timp; + + // set time to 2011-03-13 07:06:40 + //rtcSetTimeUnixSec(&RTCD1, 1300000000); + +#if !HAL_USE_RTC + chprintf(chp, "ERROR! Chibios compiled without RTC support."); + chprintf(chp, "Enable HAL_USE_RCT in you halconf.h"); + chThdSleepMilliseconds(100); + return; +#endif + + chprintf(chp, "Trying to connect SDIO... "); + chThdSleepMilliseconds(100); + + if (!mmcConnect(&MMCD1)) { + chprintf(chp, "OK\r\n"); + chprintf(chp, "Register working area for filesystem... "); + chThdSleepMilliseconds(100); + err = f_mount(0, &MMC_FS); + if (err != FR_OK){ + chSysHalt(); + } + else{ + fs_ready = TRUE; + chprintf(chp, "OK\r\n"); + } + + chprintf(chp, "Mounting filesystem... "); + chThdSleepMilliseconds(100); + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + + rtcGetTimeTm(&RTCD1, &timp); + chprintf(chp, "Current RTC time is: "); + chprintf(chp, "%u-%u-%u %u:%u:%u\r\n", + timp.tm_year+1900, timp.tm_mon+1, timp.tm_mday, timp.tm_hour, timp.tm_min, + timp.tm_sec); + + chprintf(chp, "Creating empty file 'tmstmp.tst'... "); + chThdSleepMilliseconds(100); + err = f_open(&FileObject, "0:tmstmp.tst", FA_WRITE | FA_OPEN_ALWAYS); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Write some data in it... "); + chThdSleepMilliseconds(100); + err = f_write(&FileObject, "tst", sizeof("tst"), (void *)&bytes_written); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Closing file 'tmstmp.tst'... "); + chThdSleepMilliseconds(100); + err = f_close(&FileObject); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + +// chprintf(chp, "Obtaining file info ... "); +// chThdSleepMilliseconds(100); +// err = f_stat("0:tmstmp.tst", &FileInfo); +// if (err != FR_OK) { +// chSysHalt(); +// } +// else{ +// chprintf(chp, "OK\r\n"); +// chprintf(chp, " Timestamp: %u-%u-%u %u:%u:%u\r\n", +// ((FileInfo.fdate >> 9) & 127) + 1980, +// (FileInfo.fdate >> 5) & 15, +// FileInfo.fdate & 31, +// (FileInfo.ftime >> 11) & 31, +// (FileInfo.ftime >> 5) & 63, +// (FileInfo.ftime & 31) * 2); +// } + + chprintf(chp, "Umounting filesystem... "); + f_mount(0, NULL); + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Disconnecting from SDIO..."); + chThdSleepMilliseconds(100); + if (mmcDisconnect(&MMCD1)) + chSysHalt(); + chprintf(chp, " OK\r\n"); + chprintf(chp, "------------------------------------------------------\r\n"); + chprintf(chp, "Now you can remove memory card and check timestamp on PC.\r\n"); + chThdSleepMilliseconds(100); + } + else{ + chSysHalt(); + } +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) + +static const ShellCommand commands[] = { + {"sdiotest", cmd_sdiotest}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(100); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the SDIO drivers. + */ + mmcObjectInit(&MMCD1); + mmcStart(&MMCD1, &mmccfg); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); +} + +} diff --git a/testhal/STM32F1xx/RTC_FATTIME/mcuconf.h b/testhal/STM32F1xx/RTC_FATTIME/mcuconf.h new file mode 100644 index 000000000..6c437d356 --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/RTC_FATTIME/readme.txt b/testhal/STM32F1xx/RTC_FATTIME/readme.txt new file mode 100644 index 000000000..0d7b112ee --- /dev/null +++ b/testhal/STM32F1xx/RTC_FATTIME/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates checks timestamp correctness on FAT. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/SDC/Makefile b/testhal/STM32F1xx/SDC/Makefile new file mode 100644 index 000000000..4e25ee845 --- /dev/null +++ b/testhal/STM32F1xx/SDC/Makefile @@ -0,0 +1,212 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM3210E_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xE.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SDC/chconf.h b/testhal/STM32F1xx/SDC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/SDC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SDC/halconf.h b/testhal/STM32F1xx/SDC/halconf.h new file mode 100644 index 000000000..3f22f8d9c --- /dev/null +++ b/testhal/STM32F1xx/SDC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SDC/main.c b/testhal/STM32F1xx/SDC/main.c new file mode 100644 index 000000000..24a8d4346 --- /dev/null +++ b/testhal/STM32F1xx/SDC/main.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * SDIO configuration. + */ +static const SDCConfig sdccfg = { + 0 +}; + +static uint8_t blkbuf[MMCSD_BLOCK_SIZE * 4 + 1]; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the SDIO drivers. + */ + sdcStart(&SDCD1, &sdccfg); + if (!sdcConnect(&SDCD1)) { + int i; + + /* Single aligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf, 1)) + chSysHalt(); + + /* Single unaligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf + 1, 1)) + chSysHalt(); + + /* Multiple aligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf, 4)) + chSysHalt(); + + /* Multiple unaligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) + chSysHalt(); + + /* Repeated multiple aligned reads.*/ + for (i = 0; i < 1000; i++) { + if (sdcRead(&SDCD1, 0, blkbuf, 4)) + chSysHalt(); + } + + /* Repeated multiple unaligned reads.*/ + for (i = 0; i < 1000; i++) { + if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) + chSysHalt(); + } + + /* Repeated multiple aligned writes.*/ + for (i = 0; i < 100; i++) { + if (sdcRead(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + } + + /* Repeated multiple unaligned writes.*/ + for (i = 0; i < 100; i++) { + if (sdcRead(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + } + + if (sdcDisconnect(&SDCD1)) + chSysHalt(); + } + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F1xx/SDC/mcuconf.h b/testhal/STM32F1xx/SDC/mcuconf.h new file mode 100644 index 000000000..b506af317 --- /dev/null +++ b/testhal/STM32F1xx/SDC/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/SDC/readme.txt b/testhal/STM32F1xx/SDC/readme.txt new file mode 100644 index 000000000..b897676af --- /dev/null +++ b/testhal/STM32F1xx/SDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex ST_STM3210E_EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32 SDC driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/SPI/Makefile b/testhal/STM32F1xx/SPI/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/SPI/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SPI/chconf.h b/testhal/STM32F1xx/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SPI/halconf.h b/testhal/STM32F1xx/SPI/halconf.h new file mode 100644 index 000000000..3e1cafbbf --- /dev/null +++ b/testhal/STM32F1xx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SPI/main.c b/testhal/STM32F1xx/SPI/main.c new file mode 100644 index 000000000..35b7c3b42 --- /dev/null +++ b/testhal/STM32F1xx/SPI/main.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOA, + GPIOA_SPI1NSS, + 0 +}; + +/* + * Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOA, + GPIOA_SPI1NSS, + SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(IOPORT3, GPIOC_LED); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(IOPORT3, GPIOC_LED); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI1 I/O pins setup. + */ + palSetPadMode(IOPORT1, 5, PAL_MODE_STM32_ALTERNATE_PUSHPULL); /* SCK. */ + palSetPadMode(IOPORT1, 6, PAL_MODE_STM32_ALTERNATE_PUSHPULL); /* MISO.*/ + palSetPadMode(IOPORT1, 7, PAL_MODE_STM32_ALTERNATE_PUSHPULL); /* MOSI.*/ + palSetPadMode(IOPORT1, GPIOA_SPI1NSS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, GPIOA_SPI1NSS); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/SPI/mcuconf.h b/testhal/STM32F1xx/SPI/mcuconf.h new file mode 100644 index 000000000..c74814336 --- /dev/null +++ b/testhal/STM32F1xx/SPI/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/SPI/readme.txt b/testhal/STM32F1xx/SPI/readme.txt new file mode 100644 index 000000000..1a9c90b47 --- /dev/null +++ b/testhal/STM32F1xx/SPI/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 SPI driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/UART/Makefile b/testhal/STM32F1xx/UART/Makefile new file mode 100644 index 000000000..0f7e20317 --- /dev/null +++ b/testhal/STM32F1xx/UART/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/UART/chconf.h b/testhal/STM32F1xx/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/UART/halconf.h b/testhal/STM32F1xx/UART/halconf.h new file mode 100644 index 000000000..520e71b0a --- /dev/null +++ b/testhal/STM32F1xx/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/UART/main.c b/testhal/STM32F1xx/UART/main.c new file mode 100644 index 000000000..5682b8029 --- /dev/null +++ b/testhal/STM32F1xx/UART/main.c @@ -0,0 +1,143 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromIsr(); + uartStartSendI(&UARTD2, 14, "Hello World!\r\n"); + chSysUnlockFromIsr(); +} + +static void ledoff(void *p) { + + (void)p; + palSetPad(IOPORT3, GPIOC_LED); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palClearPad(IOPORT3, GPIOC_LED); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palSetPad(IOPORT3, GPIOC_LED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palClearPad(IOPORT3, GPIOC_LED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + uartStart(&UARTD2, &uart_cfg_1); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD2, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/UART/mcuconf.h b/testhal/STM32F1xx/UART/mcuconf.h new file mode 100644 index 000000000..05ad2de0d --- /dev/null +++ b/testhal/STM32F1xx/UART/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/UART/readme.txt b/testhal/STM32F1xx/UART/readme.txt new file mode 100644 index 000000000..e24a2c568 --- /dev/null +++ b/testhal/STM32F1xx/UART/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 UART driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/USB_CDC/Makefile b/testhal/STM32F1xx/USB_CDC/Makefile new file mode 100644 index 000000000..0c781d14c --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/USB_CDC/chconf.h b/testhal/STM32F1xx/USB_CDC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_CDC/halconf.h b/testhal/STM32F1xx/USB_CDC/halconf.h new file mode 100644 index 000000000..cd76b0cfe --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_CDC/main.c b/testhal/STM32F1xx/USB_CDC/main.c new file mode 100644 index 000000000..8b11e7ed4 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/main.c @@ -0,0 +1,509 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "shell.h" +#include "chprintf.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 1, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chSequentialStreamWrite(&SDU1, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(time); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F1xx/USB_CDC/mcuconf.h b/testhal/STM32F1xx/USB_CDC/mcuconf.h new file mode 100644 index 000000000..ba73e46b0 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F1xx/USB_CDC/readme.txt b/testhal/STM32F1xx/USB_CDC/readme.txt new file mode 100644 index 000000000..2d71df64f --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 USB driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/USB_CDC_F107/.cproject b/testhal/STM32F1xx/USB_CDC_F107/.cproject new file mode 100644 index 000000000..e5f35ee12 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/USB_CDC_F107/.project b/testhal/STM32F1xx/USB_CDC_F107/.project new file mode 100644 index 000000000..cdd1937af --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/.project @@ -0,0 +1,95 @@ + + + TEST-STM32F1xx-USB_CDC_F107 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_P107 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/testhal/STM32F1xx/USB_CDC_F107/Makefile b/testhal/STM32F1xx/USB_CDC_F107/Makefile new file mode 100644 index 000000000..9b861f6d3 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform_f105_f107.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F107xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/USB_CDC_F107/chconf.h b/testhal/STM32F1xx/USB_CDC_F107/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_CDC_F107/halconf.h b/testhal/STM32F1xx/USB_CDC_F107/halconf.h new file mode 100644 index 000000000..cd76b0cfe --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_CDC_F107/main.c b/testhal/STM32F1xx/USB_CDC_F107/main.c new file mode 100644 index 000000000..8dda559c0 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/main.c @@ -0,0 +1,509 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "shell.h" +#include "chprintf.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 1, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chSequentialStreamWrite(&SDU1, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(IOPORT3, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(time); + palSetPad(IOPORT3, GPIOC_LED_STATUS1); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F1xx/USB_CDC_F107/mcuconf.h b/testhal/STM32F1xx/USB_CDC_F107/mcuconf.h new file mode 100644 index 000000000..5b6ba6683 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/mcuconf.h @@ -0,0 +1,207 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F107 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F107_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_PLL3MUL_VALUE 10 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_OTG_CLOCK_REQUIRED TRUE +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#define STM32_I2S_CLOCK_REQUIRED FALSE +#define STM32_MCOSEL STM32_MCOSEL_PLL3 +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F1xx/USB_CDC_F107/readme.txt b/testhal/STM32F1xx/USB_CDC_F107/readme.txt new file mode 100644 index 000000000..43098d8ac --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC_F107/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P107 board. + +** The Demo ** + +The application demonstrates the use of the STM32 USB (OTG) driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/USB_MSC/Makefile b/testhal/STM32F1xx/USB_MSC/Makefile new file mode 100644 index 000000000..1f76375fe --- /dev/null +++ b/testhal/STM32F1xx/USB_MSC/Makefile @@ -0,0 +1,210 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/usb_msc.c \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/USB_MSC/chconf.h b/testhal/STM32F1xx/USB_MSC/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F1xx/USB_MSC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_MSC/halconf.h b/testhal/STM32F1xx/USB_MSC/halconf.h new file mode 100644 index 000000000..2d8f40004 --- /dev/null +++ b/testhal/STM32F1xx/USB_MSC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/USB_MSC/main.c b/testhal/STM32F1xx/USB_MSC/main.c new file mode 100644 index 000000000..c8e350596 --- /dev/null +++ b/testhal/STM32F1xx/USB_MSC/main.c @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "usb_msc.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * USB Device Descriptor. + */ +static const uint8_t msc_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x00, /* bDeviceClass (in interface). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x2004, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor msc_device_descriptor = { + sizeof msc_device_descriptor_data, + msc_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t msc_configuration_descriptor_data[32] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(32, /* wTotalLength. */ + 0x01, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x08, /* bInterfaceClass (Mass Stprage). */ + 0x06, /* bInterfaceSubClass (SCSI + transparent command set, MSCO + chapter 2). */ + 0x50, /* bInterfaceProtocol (Bulk-Only + Mass Storage, MSCO chapter 3). */ + 4), /* iInterface. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (MSC_DATA_IN_EP|0x80, /* bEndpointAddress. */ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval (ignored for bulk). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (MSC_DATA_OUT_EP, /* bEndpointAddress. */ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval (ignored for bulk). */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor msc_configuration_descriptor = { + sizeof msc_configuration_descriptor_data, + msc_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t msc_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t msc_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t msc_string2[] = { + USB_DESC_BYTE(50), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0, ' ', 0, + 'S', 0, 't', 0, 'o', 0, 'r', 0, 'a', 0, 'g', 0, 'e', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t msc_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Interface string. + */ +static const uint8_t msc_string4[] = { + 16, /* bLength. */ + USB_DESCRIPTOR_STRING, /* bDescriptorType. */ + 'S', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor msc_strings[] = { + {sizeof msc_string0, msc_string0}, + {sizeof msc_string1, msc_string1}, + {sizeof msc_string2, msc_string2}, + {sizeof msc_string3, msc_string3}, + {sizeof msc_string4, msc_string4} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &msc_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &msc_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 5) + return &msc_strings[dindex]; + } + return NULL; +} + +/* + * IN EP1 state. + */ +USBInEndpointState ep1state; + +/* + * OUT EP2 state. + */ +USBOutEndpointState ep2state; + +/* + * EP1 initialization structure (IN only). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK | USB_EP_MODE_TRANSACTION, + mscDataTransmitted, + NULL, + 0x0040, + 0x0000, + &ep1state, + NULL +}; + +/* + * EP2 initialization structure (OUT only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_BULK | USB_EP_MODE_TRANSACTION, + NULL, + mscDataReceived, + 0x0000, + 0x0040, + NULL, + &ep2state +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + chSysLockFromIsr(); + usbInitEndpointI(usbp, MSC_DATA_IN_EP, &ep1config); + usbInitEndpointI(usbp, MSC_DATA_OUT_EP, &ep2config); + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Serial over USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + mscRequestsHook, + NULL +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + */ + usbStart(&USBD1, &usbcfg); + palClearPad(GPIOC, GPIOC_USB_DISC); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F1xx/USB_MSC/mcuconf.h b/testhal/STM32F1xx/USB_MSC/mcuconf.h new file mode 100644 index 000000000..157bbda32 --- /dev/null +++ b/testhal/STM32F1xx/USB_MSC/mcuconf.h @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define STM32F103_MCUCONF + +/* + * STM32F103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + diff --git a/testhal/STM32F30x/ADC/.cproject b/testhal/STM32F30x/ADC/.cproject new file mode 100644 index 000000000..18ecf6a9c --- /dev/null +++ b/testhal/STM32F30x/ADC/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/ADC/.project b/testhal/STM32F30x/ADC/.project new file mode 100644 index 000000000..723f89815 --- /dev/null +++ b/testhal/STM32F30x/ADC/.project @@ -0,0 +1,90 @@ + + + STM32F30x-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/ADC/Makefile b/testhal/STM32F30x/ADC/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/ADC/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/ADC/chconf.h b/testhal/STM32F30x/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/ADC/halconf.h b/testhal/STM32F30x/ADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F30x/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/ADC/main.c b/testhal/STM32F30x/ADC/main.c new file mode 100644 index 000000000..8489f1bef --- /dev/null +++ b/testhal/STM32F30x/ADC/main.c @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 2 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 2 channels, SW triggered. + * Channels: IN7, IN8. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, /* CFGR */ + ADC_TR(0, 4095), /* TR1 */ + 0, /* CCR */ + { /* SMPR[2] */ + 0, + 0 + }, + { /* SQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8), + 0, + 0, + 0 + } +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CFGR */ + ADC_TR(0, 4095), /* TR1 */ + ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */ + { /* SMPR[2] */ + ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) + | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), + ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) + | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), + }, + { /* SQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) | + ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8), + ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) | + ADC_SQR2_SQ7_N(ADC_CHANNEL_IN16) | ADC_SQR2_SQ8_N(ADC_CHANNEL_IN17), + 0, + 0 + } +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOE, GPIOE_LED10_RED); + chThdSleepMilliseconds(500); + palClearPad(GPIOE, GPIOE_LED10_RED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F30x/ADC/mcuconf.h b/testhal/STM32F30x/ADC/mcuconf.h new file mode 100644 index 000000000..3f9c9b5fa --- /dev/null +++ b/testhal/STM32F30x/ADC/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/ADC/readme.txt b/testhal/STM32F30x/ADC/readme.txt new file mode 100644 index 000000000..bc0a30424 --- /dev/null +++ b/testhal/STM32F30x/ADC/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x ADC driver. + +** Board Setup ** + +- Connect PC1 to 3.3V and PC2 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/ADC_DUAL/.cproject b/testhal/STM32F30x/ADC_DUAL/.cproject new file mode 100644 index 000000000..151e30397 --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/ADC_DUAL/.project b/testhal/STM32F30x/ADC_DUAL/.project new file mode 100644 index 000000000..216f76c48 --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/.project @@ -0,0 +1,90 @@ + + + STM32F30x-ADC_DUAL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/ADC_DUAL/Makefile b/testhal/STM32F30x/ADC_DUAL/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/ADC_DUAL/chconf.h b/testhal/STM32F30x/ADC_DUAL/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/ADC_DUAL/halconf.h b/testhal/STM32F30x/ADC_DUAL/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/ADC_DUAL/main.c b/testhal/STM32F30x/ADC_DUAL/main.c new file mode 100644 index 000000000..c4fa35c5c --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/main.c @@ -0,0 +1,196 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 4 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 16 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 2 channels, SW triggered. + * Channels: IN7, IN8. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, /* CFGR */ + ADC_TR(0, 4095), /* TR1 */ + ADC_CCR_DUAL(1), /* CCR */ + { /* SMPR[2] */ + 0, + 0 + }, + { /* SQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8), + 0, + 0, + 0 + }, + { /* SSMPR[2] */ + 0, + 0 + }, + { /* SSQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7), + 0, + 0, + 0 + } +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CFGR */ + ADC_TR(0, 4095), /* TR1 */ + ADC_CCR_DUAL(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */ + { /* SMPR[2] */ + ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) + | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), + ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) + | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), + }, + { /* SQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) | + ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8), + ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) | + ADC_SQR2_SQ7_N(ADC_CHANNEL_IN16) | ADC_SQR2_SQ8_N(ADC_CHANNEL_IN17), + 0, + 0 + }, + { /* SSMPR[2] */ + ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) + | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), + ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) + | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), + }, + { /* SSQR[4] */ + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7) | + ADC_SQR1_SQ3_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN7), + ADC_SQR2_SQ5_N(ADC_CHANNEL_IN8) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN7) | + ADC_SQR2_SQ7_N(ADC_CHANNEL_IN17) | ADC_SQR2_SQ8_N(ADC_CHANNEL_IN16), + 0, + 0 + } +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOE, GPIOE_LED10_RED); + chThdSleepMilliseconds(500); + palClearPad(GPIOE, GPIOE_LED10_RED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F30x/ADC_DUAL/mcuconf.h b/testhal/STM32F30x/ADC_DUAL/mcuconf.h new file mode 100644 index 000000000..4b69ad89d --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE TRUE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/ADC_DUAL/readme.txt b/testhal/STM32F30x/ADC_DUAL/readme.txt new file mode 100644 index 000000000..bc0a30424 --- /dev/null +++ b/testhal/STM32F30x/ADC_DUAL/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x ADC driver. + +** Board Setup ** + +- Connect PC1 to 3.3V and PC2 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/CAN/.cproject b/testhal/STM32F30x/CAN/.cproject new file mode 100644 index 000000000..7cdad62bb --- /dev/null +++ b/testhal/STM32F30x/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/CAN/.project b/testhal/STM32F30x/CAN/.project new file mode 100644 index 000000000..a01f8a133 --- /dev/null +++ b/testhal/STM32F30x/CAN/.project @@ -0,0 +1,90 @@ + + + STM32F30x-CAN + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/CAN/Makefile b/testhal/STM32F30x/CAN/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/CAN/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/CAN/chconf.h b/testhal/STM32F30x/CAN/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F30x/CAN/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/CAN/halconf.h b/testhal/STM32F30x/CAN/halconf.h new file mode 100644 index 000000000..5b6535967 --- /dev/null +++ b/testhal/STM32F30x/CAN/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/CAN/main.c b/testhal/STM32F30x/CAN/main.c new file mode 100644 index 000000000..c44acf566 --- /dev/null +++ b/testhal/STM32F30x/CAN/main.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Internal loopback mode, 500KBaud, automatic wakeup, automatic recover + * from abort mode. + */ +static const CANConfig cancfg = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + CAN_BTR_LBKM | CAN_BTR_SJW(0) | CAN_BTR_TS2(1) | + CAN_BTR_TS1(8) | CAN_BTR_BRP(6) +}; + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + EventListener el; + CANRxFrame rxmsg; + + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&CAND1.rxfull_event, &el, 0); + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; + while (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(GPIOE, GPIOE_LED3_RED); + } + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.DLC = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, can_rx, NULL); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F30x/CAN/mcuconf.h b/testhal/STM32F30x/CAN/mcuconf.h new file mode 100644 index 000000000..42fc2ed25 --- /dev/null +++ b/testhal/STM32F30x/CAN/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/CAN/readme.txt b/testhal/STM32F30x/CAN/readme.txt new file mode 100644 index 000000000..983b34d1d --- /dev/null +++ b/testhal/STM32F30x/CAN/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x CAN driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/EXT/.cproject b/testhal/STM32F30x/EXT/.cproject new file mode 100644 index 000000000..81789e942 --- /dev/null +++ b/testhal/STM32F30x/EXT/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/EXT/.project b/testhal/STM32F30x/EXT/.project new file mode 100644 index 000000000..7c6f467a6 --- /dev/null +++ b/testhal/STM32F30x/EXT/.project @@ -0,0 +1,90 @@ + + + STM32F30x-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/EXT/Makefile b/testhal/STM32F30x/EXT/Makefile new file mode 100644 index 000000000..8e7cec92d --- /dev/null +++ b/testhal/STM32F30x/EXT/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/EXT/chconf.h b/testhal/STM32F30x/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/EXT/halconf.h b/testhal/STM32F30x/EXT/halconf.h new file mode 100644 index 000000000..e0e0c38ff --- /dev/null +++ b/testhal/STM32F30x/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/EXT/main.c b/testhal/STM32F30x/EXT/main.c new file mode 100644 index 000000000..9ef548d87 --- /dev/null +++ b/testhal/STM32F30x/EXT/main.c @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led5off(void *arg) { + + (void)arg; + palClearPad(GPIOE, GPIOE_LED10_RED); +} + +/* Triggered when the button is pressed or released. The LED5 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palSetPad(GPIOE, GPIOE_LED10_RED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led5off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F30x/EXT/mcuconf.h b/testhal/STM32F30x/EXT/mcuconf.h new file mode 100644 index 000000000..42fc2ed25 --- /dev/null +++ b/testhal/STM32F30x/EXT/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/EXT/readme.txt b/testhal/STM32F30x/EXT/readme.txt new file mode 100644 index 000000000..39255526b --- /dev/null +++ b/testhal/STM32F30x/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/IRQ_STORM/.cproject b/testhal/STM32F30x/IRQ_STORM/.cproject new file mode 100644 index 000000000..ed2858c43 --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/IRQ_STORM/.project b/testhal/STM32F30x/IRQ_STORM/.project new file mode 100644 index 000000000..a7a6d0b2e --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/.project @@ -0,0 +1,38 @@ + + + STM32F30x-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/IRQ_STORM/Makefile b/testhal/STM32F30x/IRQ_STORM/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/IRQ_STORM/chconf.h b/testhal/STM32F30x/IRQ_STORM/chconf.h new file mode 100644 index 000000000..38242d75d --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/chconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_USE_FPU FALSE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/IRQ_STORM/halconf.h b/testhal/STM32F30x/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/IRQ_STORM/main.c b/testhal/STM32F30x/IRQ_STORM/main.c new file mode 100644 index 000000000..2487373ca --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/main.c @@ -0,0 +1,331 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOE, GPIOE_LED10_RED); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1, PA9 and PA10 are routed to USART1. + */ + sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); /* USART1 RX. */ + + /* + * Activates GPTs. + */ + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 10; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/STM32F30x/IRQ_STORM/mcuconf.h b/testhal/STM32F30x/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..c660fc3f9 --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_USE_TIM7 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/IRQ_STORM/readme.txt b/testhal/STM32F30x/IRQ_STORM/readme.txt new file mode 100644 index 000000000..5193c5f89 --- /dev/null +++ b/testhal/STM32F30x/IRQ_STORM/readme.txt @@ -0,0 +1,32 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/PWM-ICU/.cproject b/testhal/STM32F30x/PWM-ICU/.cproject new file mode 100644 index 000000000..0bb5b2f00 --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/PWM-ICU/.project b/testhal/STM32F30x/PWM-ICU/.project new file mode 100644 index 000000000..6d36832e8 --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + STM32F30x-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/PWM-ICU/Makefile b/testhal/STM32F30x/PWM-ICU/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/PWM-ICU/chconf.h b/testhal/STM32F30x/PWM-ICU/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/PWM-ICU/halconf.h b/testhal/STM32F30x/PWM-ICU/halconf.h new file mode 100644 index 000000000..2f74c82c8 --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/PWM-ICU/main.c b/testhal/STM32F30x/PWM-ICU/main.c new file mode 100644 index 000000000..01215fdda --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/main.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOE, GPIOE_LED4_BLUE); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOE, GPIOE_LED4_BLUE); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOE, GPIOE_LED9_BLUE); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOE, GPIOE_LED9_BLUE); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA15 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOE, GPIOE_LED4_BLUE); + palClearPad(GPIOE, GPIOE_LED9_BLUE); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F30x/PWM-ICU/mcuconf.h b/testhal/STM32F30x/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..ca40cb887 --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 TRUE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM8 TRUE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/PWM-ICU/readme.txt b/testhal/STM32F30x/PWM-ICU/readme.txt new file mode 100644 index 000000000..cfb53f76a --- /dev/null +++ b/testhal/STM32F30x/PWM-ICU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x PWM-ICU drivers. + +** Board Setup ** + +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/SPI/.cproject b/testhal/STM32F30x/SPI/.cproject new file mode 100644 index 000000000..104d73e64 --- /dev/null +++ b/testhal/STM32F30x/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/SPI/.project b/testhal/STM32F30x/SPI/.project new file mode 100644 index 000000000..61b728dcf --- /dev/null +++ b/testhal/STM32F30x/SPI/.project @@ -0,0 +1,90 @@ + + + STM32F30x-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/SPI/Makefile b/testhal/STM32F30x/SPI/Makefile new file mode 100644 index 000000000..455c2e5da --- /dev/null +++ b/testhal/STM32F30x/SPI/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/SPI/chconf.h b/testhal/STM32F30x/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/SPI/halconf.h b/testhal/STM32F30x/SPI/halconf.h new file mode 100644 index 000000000..3e1cafbbf --- /dev/null +++ b/testhal/STM32F30x/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/SPI/main.c b/testhal/STM32F30x/SPI/main.c new file mode 100644 index 000000000..aedae794a --- /dev/null +++ b/testhal/STM32F30x/SPI/main.c @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOE, GPIOE_LED10_RED); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOE, GPIOE_LED10_RED);/* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(500); + palClearPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F30x/SPI/mcuconf.h b/testhal/STM32F30x/SPI/mcuconf.h new file mode 100644 index 000000000..1768aa8db --- /dev/null +++ b/testhal/STM32F30x/SPI/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/SPI/readme.txt b/testhal/STM32F30x/SPI/readme.txt new file mode 100644 index 000000000..9275c06ee --- /dev/null +++ b/testhal/STM32F30x/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/UART/.cproject b/testhal/STM32F30x/UART/.cproject new file mode 100644 index 000000000..661d548d0 --- /dev/null +++ b/testhal/STM32F30x/UART/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/UART/.project b/testhal/STM32F30x/UART/.project new file mode 100644 index 000000000..24b9d53ce --- /dev/null +++ b/testhal/STM32F30x/UART/.project @@ -0,0 +1,90 @@ + + + STM32F30x-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F30x/UART/Makefile b/testhal/STM32F30x/UART/Makefile new file mode 100644 index 000000000..8e7cec92d --- /dev/null +++ b/testhal/STM32F30x/UART/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/UART/chconf.h b/testhal/STM32F30x/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/UART/halconf.h b/testhal/STM32F30x/UART/halconf.h new file mode 100644 index 000000000..a4fc70926 --- /dev/null +++ b/testhal/STM32F30x/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/UART/main.c b/testhal/STM32F30x/UART/main.c new file mode 100644 index 000000000..9d0bea53c --- /dev/null +++ b/testhal/STM32F30x/UART/main.c @@ -0,0 +1,144 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromIsr(); + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); + chSysUnlockFromIsr(); +} + +static void ledoff(void *p) { + + (void)p; + palClearPad(GPIOE, GPIOE_LED3_RED); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOE, GPIOE_LED3_RED); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palClearPad(GPIOE, GPIOE_LED3_RED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOE, GPIOE_LED3_RED); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1, PA9 and PA10 are routed to USART1. + */ + uartStart(&UARTD1, &uart_cfg_1); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); /* USART1 TX. */ + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); /* USART1 RX. */ + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F30x/UART/mcuconf.h b/testhal/STM32F30x/UART/mcuconf.h new file mode 100644 index 000000000..0eaddf96a --- /dev/null +++ b/testhal/STM32F30x/UART/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/UART/readme.txt b/testhal/STM32F30x/UART/readme.txt new file mode 100644 index 000000000..3f55599a8 --- /dev/null +++ b/testhal/STM32F30x/UART/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x UART driver. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F30x/USB_CDC/.cproject b/testhal/STM32F30x/USB_CDC/.cproject new file mode 100644 index 000000000..839c40d30 --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F30x/USB_CDC/.project b/testhal/STM32F30x/USB_CDC/.project new file mode 100644 index 000000000..a1dcbcd63 --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/.project @@ -0,0 +1,43 @@ + + + STM32F30x-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F3_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/testhal/STM32F30x/USB_CDC/Makefile b/testhal/STM32F30x/USB_CDC/Makefile new file mode 100644 index 000000000..1f03d2992 --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F303xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F30x/USB_CDC/chconf.h b/testhal/STM32F30x/USB_CDC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/USB_CDC/halconf.h b/testhal/STM32F30x/USB_CDC/halconf.h new file mode 100644 index 000000000..cd76b0cfe --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F30x/USB_CDC/main.c b/testhal/STM32F30x/USB_CDC/main.c new file mode 100644 index 000000000..6555da8d3 --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/main.c @@ -0,0 +1,516 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "shell.h" +#include "chprintf.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * DP resistor control is not possible on the STM32F3-Discovery, using stubs + * for the connection macros. + */ +#define usb_lld_connect_bus(usbp) +#define usb_lld_disconnect_bus(usbp) + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 1, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chSequentialStreamWrite(&SDU1, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(time); + palSetPad(GPIOE, GPIOE_LED3_RED); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F30x/USB_CDC/mcuconf.h b/testhal/STM32F30x/USB_CDC/mcuconf.h new file mode 100644 index 000000000..c0a1aaa0f --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/mcuconf.h @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F30x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_UART4SW STM32_UART4SW_PCLK +#define STM32_UART5SW STM32_UART5SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F30x/USB_CDC/readme.txt b/testhal/STM32F30x/USB_CDC/readme.txt new file mode 100644 index 000000000..39055f999 --- /dev/null +++ b/testhal/STM32F30x/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32F30x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F3-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F30x USB driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/ADC/.cproject b/testhal/STM32F37x/ADC/.cproject new file mode 100644 index 000000000..2230bab81 --- /dev/null +++ b/testhal/STM32F37x/ADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/ADC/.project b/testhal/STM32F37x/ADC/.project new file mode 100644 index 000000000..cf24ffaeb --- /dev/null +++ b/testhal/STM32F37x/ADC/.project @@ -0,0 +1,38 @@ + + + STM32F37x-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/ADC/Makefile b/testhal/STM32F37x/ADC/Makefile new file mode 100644 index 000000000..684302ce4 --- /dev/null +++ b/testhal/STM32F37x/ADC/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/ADC/chconf.h b/testhal/STM32F37x/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/ADC/halconf.h b/testhal/STM32F37x/ADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F37x/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/ADC/main.c b/testhal/STM32F37x/ADC/main.c new file mode 100644 index 000000000..b9a481825 --- /dev/null +++ b/testhal/STM32F37x/ADC/main.c @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 2 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 2 channels, SW triggered. + * Channels: IN1, IN9. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + .u.adc = { + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* LTR */ + 0, /* HTR */ + { /* SMPR[2] */ + 0, + ADC_SMPR2_SMP_AN9(ADC_SAMPLE_41P5) | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_41P5), + }, + { /* SQR[3] */ + 0, + 0, + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1) + } + } +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN1, IN9, IN1, IN9, IN1, IN9, VBat, Sensor. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + .u.adc = { + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* LTR */ + 0, /* HTR */ + { /* SMPR[2] */ + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_239P5), + ADC_SMPR2_SMP_AN9(ADC_SAMPLE_41P5) | ADC_SMPR2_SMP_AN1(ADC_SAMPLE_41P5) + }, + { /* SQR[3] */ + 0, + ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VBAT), + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN9) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN1) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN9) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN1) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1) + } + } +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver, the temperature sensor and the VBat + * measurement. + */ + adcStart(&ADCD1, NULL); + adcSTM32Calibrate(&ADCD1); + adcSTM32EnableTSVREFE(); + adcSTM32EnableVBATE(); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) { + adcStopConversion(&ADCD1); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F37x/ADC/mcuconf.h b/testhal/STM32F37x/ADC/mcuconf.h new file mode 100644 index 000000000..7cdc9bf4a --- /dev/null +++ b/testhal/STM32F37x/ADC/mcuconf.h @@ -0,0 +1,209 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_SDADC_SLOW_MODE FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/ADC/readme.txt b/testhal/STM32F37x/ADC/readme.txt new file mode 100644 index 000000000..8cb97fdc2 --- /dev/null +++ b/testhal/STM32F37x/ADC/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x ADC driver on the +ADC peripheral. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/CAN/.cproject b/testhal/STM32F37x/CAN/.cproject new file mode 100644 index 000000000..a6eeccae8 --- /dev/null +++ b/testhal/STM32F37x/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/CAN/.project b/testhal/STM32F37x/CAN/.project new file mode 100644 index 000000000..d26e9f35e --- /dev/null +++ b/testhal/STM32F37x/CAN/.project @@ -0,0 +1,38 @@ + + + STM32F37x-CAN + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/CAN/Makefile b/testhal/STM32F37x/CAN/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/CAN/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/CAN/chconf.h b/testhal/STM32F37x/CAN/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F37x/CAN/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/CAN/halconf.h b/testhal/STM32F37x/CAN/halconf.h new file mode 100644 index 000000000..5b6535967 --- /dev/null +++ b/testhal/STM32F37x/CAN/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/CAN/main.c b/testhal/STM32F37x/CAN/main.c new file mode 100644 index 000000000..12e0c4650 --- /dev/null +++ b/testhal/STM32F37x/CAN/main.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Internal loopback mode, 500KBaud, automatic wakeup, automatic recover + * from abort mode. + */ +static const CANConfig cancfg = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + CAN_BTR_LBKM | CAN_BTR_SJW(0) | CAN_BTR_TS2(1) | + CAN_BTR_TS1(8) | CAN_BTR_BRP(6) +}; + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + EventListener el; + CANRxFrame rxmsg; + + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&CAND1.rxfull_event, &el, 0); + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; + while (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(GPIOC, GPIOC_LED1); + } + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.DLC = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, can_rx, NULL); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F37x/CAN/mcuconf.h b/testhal/STM32F37x/CAN/mcuconf.h new file mode 100644 index 000000000..1434b2fae --- /dev/null +++ b/testhal/STM32F37x/CAN/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/CAN/readme.txt b/testhal/STM32F37x/CAN/readme.txt new file mode 100644 index 000000000..9acc1deee --- /dev/null +++ b/testhal/STM32F37x/CAN/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x CAN driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/EXT/.cproject b/testhal/STM32F37x/EXT/.cproject new file mode 100644 index 000000000..420df3639 --- /dev/null +++ b/testhal/STM32F37x/EXT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/EXT/.project b/testhal/STM32F37x/EXT/.project new file mode 100644 index 000000000..e64b8406f --- /dev/null +++ b/testhal/STM32F37x/EXT/.project @@ -0,0 +1,38 @@ + + + STM32F37x-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/EXT/Makefile b/testhal/STM32F37x/EXT/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/EXT/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/EXT/chconf.h b/testhal/STM32F37x/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/EXT/halconf.h b/testhal/STM32F37x/EXT/halconf.h new file mode 100644 index 000000000..e0e0c38ff --- /dev/null +++ b/testhal/STM32F37x/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/EXT/main.c b/testhal/STM32F37x/EXT/main.c new file mode 100644 index 000000000..7c158e306 --- /dev/null +++ b/testhal/STM32F37x/EXT/main.c @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led5off(void *arg) { + + (void)arg; + palClearPad(GPIOC, GPIOC_LED1); +} + +/* Triggered when the button is pressed or released. The LED5 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palSetPad(GPIOC, GPIOC_LED1); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led5off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F37x/EXT/mcuconf.h b/testhal/STM32F37x/EXT/mcuconf.h new file mode 100644 index 000000000..1434b2fae --- /dev/null +++ b/testhal/STM32F37x/EXT/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/EXT/readme.txt b/testhal/STM32F37x/EXT/readme.txt new file mode 100644 index 000000000..e5a0e21fb --- /dev/null +++ b/testhal/STM32F37x/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/I2C/.cproject b/testhal/STM32F37x/I2C/.cproject new file mode 100644 index 000000000..367316a03 --- /dev/null +++ b/testhal/STM32F37x/I2C/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/I2C/.project b/testhal/STM32F37x/I2C/.project new file mode 100644 index 000000000..03945c10e --- /dev/null +++ b/testhal/STM32F37x/I2C/.project @@ -0,0 +1,38 @@ + + + STM32F37x-I2C + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/I2C/Makefile b/testhal/STM32F37x/I2C/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/I2C/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/I2C/chconf.h b/testhal/STM32F37x/I2C/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/I2C/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/I2C/halconf.h b/testhal/STM32F37x/I2C/halconf.h new file mode 100644 index 000000000..3ac5de5ba --- /dev/null +++ b/testhal/STM32F37x/I2C/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/I2C/main.c b/testhal/STM32F37x/I2C/main.c new file mode 100644 index 000000000..fc0e4e2ab --- /dev/null +++ b/testhal/STM32F37x/I2C/main.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Timing values are taken from the RM except the PRESC set to 9 because + * the input clock is 72MHz. + * The timings are critical, please always refer to the STM32 Reference + * Manual before attempting changes. + */ +#if 0 +static const I2CConfig i2cconfig = { + STM32_TIMINGR_PRESC(8U) | /* 72MHz/9 = 8MHz I2CCLK. */ + STM32_TIMINGR_SCLDEL(3U) | STM32_TIMINGR_SDADEL(3U) | + STM32_TIMINGR_SCLH(3U) | STM32_TIMINGR_SCLL(9U), + 0, + 0 +}; +#endif +static const I2CConfig i2cconfig = { + STM32_TIMINGR_PRESC(15U) | + STM32_TIMINGR_SCLDEL(4U) | STM32_TIMINGR_SDADEL(2U) | + STM32_TIMINGR_SCLH(15U) | STM32_TIMINGR_SCLL(21U), + 0, + 0 +}; + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Starting the I2C driver 2. + */ + i2cStart(&I2CD2, &i2cconfig); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + unsigned i; + msg_t msg; + static const uint8_t cmd[] = {0, 0}; + uint8_t data[16]; + + msg = i2cMasterTransmitTimeout(&I2CD2, 0x52, cmd, sizeof(cmd), + data, sizeof(data), TIME_INFINITE); + if (msg != RDY_OK) + palTogglePad(GPIOC, GPIOC_LED3); + for (i = 0; i < 256; i++) { + msg = i2cMasterReceiveTimeout(&I2CD2, 0x52, + data, sizeof(data), TIME_INFINITE); + if (msg != RDY_OK) + palTogglePad(GPIOC, GPIOC_LED3); + } + chThdSleepMilliseconds(500); + palTogglePad(GPIOC, GPIOC_LED2); + } + return 0; +} diff --git a/testhal/STM32F37x/I2C/mcuconf.h b/testhal/STM32F37x/I2C/mcuconf.h new file mode 100644 index 000000000..c18448c10 --- /dev/null +++ b/testhal/STM32F37x/I2C/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/I2C/readme.txt b/testhal/STM32F37x/I2C/readme.txt new file mode 100644 index 000000000..f7d032869 --- /dev/null +++ b/testhal/STM32F37x/I2C/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - I2C driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x I2C driver. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/IRQ_STORM/.cproject b/testhal/STM32F37x/IRQ_STORM/.cproject new file mode 100644 index 000000000..bf0ac2f78 --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/IRQ_STORM/.project b/testhal/STM32F37x/IRQ_STORM/.project new file mode 100644 index 000000000..da09bb566 --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/.project @@ -0,0 +1,38 @@ + + + STM32F37x-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/IRQ_STORM/Makefile b/testhal/STM32F37x/IRQ_STORM/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/IRQ_STORM/chconf.h b/testhal/STM32F37x/IRQ_STORM/chconf.h new file mode 100644 index 000000000..38242d75d --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/chconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_USE_FPU FALSE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/IRQ_STORM/halconf.h b/testhal/STM32F37x/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/IRQ_STORM/main.c b/testhal/STM32F37x/IRQ_STORM/main.c new file mode 100644 index 000000000..7a630450b --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/main.c @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOC, GPIOC_LED1); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } + chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the default configuration, pins + * are pre-configured in board.h. + */ + sdStart(&SD2, NULL); + + /* + * Activates GPTs. + */ + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 10; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/STM32F37x/IRQ_STORM/mcuconf.h b/testhal/STM32F37x/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..1434b2fae --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/IRQ_STORM/readme.txt b/testhal/STM32F37x/IRQ_STORM/readme.txt new file mode 100644 index 000000000..740cf3c20 --- /dev/null +++ b/testhal/STM32F37x/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +- Connect a terminal emulator to serial port connector (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/PWM-ICU/.cproject b/testhal/STM32F37x/PWM-ICU/.cproject new file mode 100644 index 000000000..42e9f611b --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/PWM-ICU/.project b/testhal/STM32F37x/PWM-ICU/.project new file mode 100644 index 000000000..958fa1637 --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + STM32F37x-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/PWM-ICU/Makefile b/testhal/STM32F37x/PWM-ICU/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/PWM-ICU/chconf.h b/testhal/STM32F37x/PWM-ICU/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/PWM-ICU/halconf.h b/testhal/STM32F37x/PWM-ICU/halconf.h new file mode 100644 index 000000000..2f74c82c8 --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/PWM-ICU/main.c b/testhal/STM32F37x/PWM-ICU/main.c new file mode 100644 index 000000000..603b891f8 --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/main.c @@ -0,0 +1,136 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOC, GPIOC_LED1); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOC, GPIOC_LED1); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_LOW, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOC, GPIOC_LED2); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOC, GPIOC_LED2); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_LOW, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 5 and ICU driver 3. + * GPIOC0 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD5, &pwmcfg); + palSetPadMode(GPIOC, 0, PAL_MODE_ALTERNATE(2)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD5, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD5, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD5, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD5, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD5, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD5, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD5, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD5, 0); + pwmStop(&PWMD5); + icuDisable(&ICUD3); + icuStop(&ICUD3); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F37x/PWM-ICU/mcuconf.h b/testhal/STM32F37x/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..36b5c84a5 --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/PWM-ICU/readme.txt b/testhal/STM32F37x/PWM-ICU/readme.txt new file mode 100644 index 000000000..b1acb879a --- /dev/null +++ b/testhal/STM32F37x/PWM-ICU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x PWM and ICU drivers. + +** Board Setup ** + +- Connect PC0 and PC6 together. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/SDADC/.cproject b/testhal/STM32F37x/SDADC/.cproject new file mode 100644 index 000000000..e3d709437 --- /dev/null +++ b/testhal/STM32F37x/SDADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/SDADC/.project b/testhal/STM32F37x/SDADC/.project new file mode 100644 index 000000000..83a87eb03 --- /dev/null +++ b/testhal/STM32F37x/SDADC/.project @@ -0,0 +1,38 @@ + + + STM32F37x-SDADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/SDADC/Makefile b/testhal/STM32F37x/SDADC/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/SDADC/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/SDADC/chconf.h b/testhal/STM32F37x/SDADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/SDADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SDADC/halconf.h b/testhal/STM32F37x/SDADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F37x/SDADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SDADC/main.c b/testhal/STM32F37x/SDADC/main.c new file mode 100644 index 000000000..1d700a3a5 --- /dev/null +++ b/testhal/STM32F37x/SDADC/main.c @@ -0,0 +1,164 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 1 +#define ADC_GRP2_BUF_DEPTH 32 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * SDADC configuration. + */ +static const ADCConfig sdadc_config = { + 0, + { + SDADC_CONFR_GAIN_1X | SDADC_CONFR_SE_ZERO_VOLT | SDADC_CONFR_COMMON_VSSSD, + 0, + 0 + } +}; + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: ADC_IN5P. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + .u.sdadc = { + SDADC_CR2_JSWSTART, /* CR2 */ + SDADC_JCHGR_CH(5), /* JCHGR */ + { /* CONFCHR[2]*/ + SDADC_CONFCHR1_CH5(0), + 0 + } + } +}; + +/* + * ADC conversion group. + * Mode: Continuous, 32 samples of 1 channel, SW triggered. + * Channels: ADC_IN5P. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + .u.sdadc = { + SDADC_CR2_JSWSTART, /* CR2 */ + SDADC_JCHGR_CH(5), /* JCHGR */ + { /* CONFCHR[2]*/ + SDADC_CONFCHR1_CH5(0), + 0 + } + } +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the SDADC1 driver. + */ + adcStart(&SDADCD1, &sdadc_config); + adcSTM32Calibrate(&SDADCD1); + + /* + * Linear conversion. + */ + adcConvert(&SDADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&SDADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) { + adcStopConversion(&SDADCD1); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F37x/SDADC/mcuconf.h b/testhal/STM32F37x/SDADC/mcuconf.h new file mode 100644 index 000000000..8a4e68ba8 --- /dev/null +++ b/testhal/STM32F37x/SDADC/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_SDADC1 TRUE +#define STM32_ADC_USE_SDADC2 TRUE +#define STM32_ADC_USE_SDADC3 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/SDADC/readme.txt b/testhal/STM32F37x/SDADC/readme.txt new file mode 100644 index 000000000..0e5191419 --- /dev/null +++ b/testhal/STM32F37x/SDADC/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x ADC driver on the +SDADC peripheral. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/SPI/.cproject b/testhal/STM32F37x/SPI/.cproject new file mode 100644 index 000000000..5aaba7ac7 --- /dev/null +++ b/testhal/STM32F37x/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/SPI/.project b/testhal/STM32F37x/SPI/.project new file mode 100644 index 000000000..c3985659c --- /dev/null +++ b/testhal/STM32F37x/SPI/.project @@ -0,0 +1,38 @@ + + + STM32F37x-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/SPI/Makefile b/testhal/STM32F37x/SPI/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/SPI/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/SPI/chconf.h b/testhal/STM32F37x/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SPI/halconf.h b/testhal/STM32F37x/SPI/halconf.h new file mode 100644 index 000000000..3e1cafbbf --- /dev/null +++ b/testhal/STM32F37x/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/SPI/main.c b/testhal/STM32F37x/SPI/main.c new file mode 100644 index 000000000..3a828f3a9 --- /dev/null +++ b/testhal/STM32F37x/SPI/main.c @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 10, + 0, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 10, + SPI_CR1_BR_2 | SPI_CR1_BR_1, + SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOC, GPIOC_LED2); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOC, GPIOC_LED2); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(blinker_wa, 128); +static msg_t blinker(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(blinker_wa, sizeof(blinker_wa), + NORMALPRIO-1, blinker, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F37x/SPI/mcuconf.h b/testhal/STM32F37x/SPI/mcuconf.h new file mode 100644 index 000000000..5326570a9 --- /dev/null +++ b/testhal/STM32F37x/SPI/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/SPI/readme.txt b/testhal/STM32F37x/SPI/readme.txt new file mode 100644 index 000000000..ebf5f3563 --- /dev/null +++ b/testhal/STM32F37x/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/UART/.cproject b/testhal/STM32F37x/UART/.cproject new file mode 100644 index 000000000..be46a014d --- /dev/null +++ b/testhal/STM32F37x/UART/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/UART/.project b/testhal/STM32F37x/UART/.project new file mode 100644 index 000000000..dfdbbc5df --- /dev/null +++ b/testhal/STM32F37x/UART/.project @@ -0,0 +1,38 @@ + + + STM32F37x-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F37x/UART/Makefile b/testhal/STM32F37x/UART/Makefile new file mode 100644 index 000000000..782a3b3d7 --- /dev/null +++ b/testhal/STM32F37x/UART/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/UART/chconf.h b/testhal/STM32F37x/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/UART/halconf.h b/testhal/STM32F37x/UART/halconf.h new file mode 100644 index 000000000..a4fc70926 --- /dev/null +++ b/testhal/STM32F37x/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/UART/main.c b/testhal/STM32F37x/UART/main.c new file mode 100644 index 000000000..7b9577f8a --- /dev/null +++ b/testhal/STM32F37x/UART/main.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromIsr(); + uartStartSendI(&UARTD2, 14, "Hello World!\r\n"); + chSysUnlockFromIsr(); +} + +static void ledoff(void *p) { + + (void)p; + palSetPad(GPIOC, GPIOC_LED1); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOC, GPIOC_LED1); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOC, GPIOC_LED1); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palClearPad(GPIOC, GPIOC_LED1); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1, PA9 and PA10 are routed to USART2. + */ + uartStart(&UARTD2, &uart_cfg_1); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD2, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F37x/UART/mcuconf.h b/testhal/STM32F37x/UART/mcuconf.h new file mode 100644 index 000000000..1421ff9f3 --- /dev/null +++ b/testhal/STM32F37x/UART/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/UART/readme.txt b/testhal/STM32F37x/UART/readme.txt new file mode 100644 index 000000000..27b6bfefd --- /dev/null +++ b/testhal/STM32F37x/UART/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x UART driver. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F37x/USB_CDC/.cproject b/testhal/STM32F37x/USB_CDC/.cproject new file mode 100644 index 000000000..66a97f931 --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F37x/USB_CDC/.project b/testhal/STM32F37x/USB_CDC/.project new file mode 100644 index 000000000..4e173140c --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/.project @@ -0,0 +1,43 @@ + + + STM32F37x-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32373C_EVAL + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/testhal/STM32F37x/USB_CDC/Makefile b/testhal/STM32F37x/USB_CDC/Makefile new file mode 100644 index 000000000..60e76cc62 --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/Makefile @@ -0,0 +1,223 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F373xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F37x/USB_CDC/chconf.h b/testhal/STM32F37x/USB_CDC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/USB_CDC/halconf.h b/testhal/STM32F37x/USB_CDC/halconf.h new file mode 100644 index 000000000..cd76b0cfe --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F37x/USB_CDC/main.c b/testhal/STM32F37x/USB_CDC/main.c new file mode 100644 index 000000000..200a0f3d5 --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/main.c @@ -0,0 +1,515 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "shell.h" +#include "chprintf.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * DP resistor control. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISCONNECT) +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISCONNECT) + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU1; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 1, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chSequentialStreamWrite(&SDU1, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(time); + palSetPad(GPIOC, GPIOC_LED1); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F37x/USB_CDC/mcuconf.h b/testhal/STM32F37x/USB_CDC/mcuconf.h new file mode 100644 index 000000000..4d4320200 --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F30x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F37x_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_SDPRE STM32_SDPRE_DIV12 +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_USART2SW STM32_USART2SW_PCLK +#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_SDADC1 FALSE +#define STM32_ADC_USE_SDADC2 FALSE +#define STM32_ADC_USE_SDADC3 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F37x/USB_CDC/readme.txt b/testhal/STM32F37x/USB_CDC/readme.txt new file mode 100644 index 000000000..1c0755213 --- /dev/null +++ b/testhal/STM32F37x/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32F37x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32373C-EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32F37x USB driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/ADC/.cproject b/testhal/STM32F4xx/ADC/.cproject new file mode 100644 index 000000000..b279459f3 --- /dev/null +++ b/testhal/STM32F4xx/ADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/ADC/.project b/testhal/STM32F4xx/ADC/.project new file mode 100644 index 000000000..eafa4d503 --- /dev/null +++ b/testhal/STM32F4xx/ADC/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/ADC/Makefile b/testhal/STM32F4xx/ADC/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/ADC/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/ADC/chconf.h b/testhal/STM32F4xx/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/ADC/halconf.h b/testhal/STM32F4xx/ADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32F4xx/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/ADC/main.c b/testhal/STM32F4xx/ADC/main.c new file mode 100644 index 000000000..650347f76 --- /dev/null +++ b/testhal/STM32F4xx/ADC/main.c @@ -0,0 +1,160 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN11. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_3), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN11, IN12, IN11, IN12, IN11, IN12, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN12(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), + ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + palClearPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + adcSTM32DisableTSVREFE(); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F4xx/ADC/mcuconf.h b/testhal/STM32F4xx/ADC/mcuconf.h new file mode 100644 index 000000000..10e1fae6c --- /dev/null +++ b/testhal/STM32F4xx/ADC/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/ADC/readme.txt b/testhal/STM32F4xx/ADC/readme.txt new file mode 100644 index 000000000..af029649b --- /dev/null +++ b/testhal/STM32F4xx/ADC/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx ADC driver. + +** Board Setup ** + +- Connect PC1 to 3.3V and PC2 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/CAN/.cproject b/testhal/STM32F4xx/CAN/.cproject new file mode 100644 index 000000000..41abe3d02 --- /dev/null +++ b/testhal/STM32F4xx/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/CAN/.project b/testhal/STM32F4xx/CAN/.project new file mode 100644 index 000000000..3c1df9502 --- /dev/null +++ b/testhal/STM32F4xx/CAN/.project @@ -0,0 +1,90 @@ + + + STM32F4xx-CAN + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/CAN/Makefile b/testhal/STM32F4xx/CAN/Makefile new file mode 100644 index 000000000..62d0516f0 --- /dev/null +++ b/testhal/STM32F4xx/CAN/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/CAN/chconf.h b/testhal/STM32F4xx/CAN/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F4xx/CAN/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/CAN/halconf.h b/testhal/STM32F4xx/CAN/halconf.h new file mode 100644 index 000000000..5b6535967 --- /dev/null +++ b/testhal/STM32F4xx/CAN/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/CAN/main.c b/testhal/STM32F4xx/CAN/main.c new file mode 100644 index 000000000..8202afe1e --- /dev/null +++ b/testhal/STM32F4xx/CAN/main.c @@ -0,0 +1,127 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND1, GPIOD_LED5}; +static const struct can_instance can2 = {&CAND2, GPIOD_LED3}; + +/* + * Internal loopback mode, 500KBaud, automatic wakeup, automatic recover + * from abort mode. + * See section 22.7.7 on the STM32 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + CAN_BTR_LBKM | CAN_BTR_SJW(0) | CAN_BTR_TS2(1) | + CAN_BTR_TS1(8) | CAN_BTR_BRP(6) +}; + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx1_wa, 256); +static WORKING_AREA(can_rx2_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(GPIOD, cip->led); + } + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.DLC = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); + canTransmit(&CAND2, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN drivers 1 and 2. + */ + canStart(&CAND1, &cancfg); + canStart(&CAND2, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx1_wa, sizeof(can_rx1_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_rx2_wa, sizeof(can_rx2_wa), NORMALPRIO + 7, + can_rx, (void *)&can2); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F4xx/CAN/mcuconf.h b/testhal/STM32F4xx/CAN/mcuconf.h new file mode 100644 index 000000000..e0dffb5de --- /dev/null +++ b/testhal/STM32F4xx/CAN/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/CAN/readme.txt b/testhal/STM32F4xx/CAN/readme.txt new file mode 100644 index 000000000..5884567ac --- /dev/null +++ b/testhal/STM32F4xx/CAN/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32 CAN driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/DMA_STORM/.cproject b/testhal/STM32F4xx/DMA_STORM/.cproject new file mode 100644 index 000000000..4b78ef53c --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/DMA_STORM/.project b/testhal/STM32F4xx/DMA_STORM/.project new file mode 100644 index 000000000..fdacc2794 --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-DMA_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/DMA_STORM/Makefile b/testhal/STM32F4xx/DMA_STORM/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/DMA_STORM/chconf.h b/testhal/STM32F4xx/DMA_STORM/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/DMA_STORM/halconf.h b/testhal/STM32F4xx/DMA_STORM/halconf.h new file mode 100644 index 000000000..e2b440694 --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/DMA_STORM/main.c b/testhal/STM32F4xx/DMA_STORM/main.c new file mode 100644 index 000000000..a3193fcc1 --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/main.c @@ -0,0 +1,229 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + (void)buffer; + (void)n; +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; + chSysHalt(); +} + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN11, IN12, IN11, IN12, IN11, IN12, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN12(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), + ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) +}; + +/* + * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0 +}; + +static void tmo(void *p) { + + (void)p; + chSysHalt(); +} + +/* + * SPI thread. + */ +static WORKING_AREA(waSPI1, 1024); +static WORKING_AREA(waSPI2, 1024); +static WORKING_AREA(waSPI3, 1024); +static msg_t spi_thread(void *p) { + unsigned i; + SPIDriver *spip = (SPIDriver *)p; + VirtualTimer vt; + uint8_t txbuf[256]; + uint8_t rxbuf[256]; + + /* Prepare transmit pattern.*/ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Continuous transmission.*/ + while (TRUE) { + /* Starts a VT working as watchdog to catch a malfunction in the SPI + driver.*/ + chSysLock(); + chVTSetI(&vt, MS2ST(10), tmo, NULL); + chSysUnlock(); + + spiExchange(spip, sizeof(txbuf), txbuf, rxbuf); + + /* Stops the watchdog.*/ + chSysLock(); + if (chVTIsArmedI(&vt)) + chVTResetI(&vt); + chSysUnlock(); + } +} + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED3); /* Orange. */ + chThdSleepMilliseconds(500); + palClearPad(GPIOD, GPIOD_LED3); /* Orange. */ + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + static uint8_t patterns1[4096], patterns2[4096], buf1[4096], buf2[4096]; + + /* System initializations. + - HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations. + - Kernel initialization, the main() function becomes a thread and the + RTOS is active.*/ + halInit(); + chSysInit(); + + /* Creates the blinker thread.*/ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO + 10, + Thread1, NULL); + + /* Activates the ADC1 driver and the temperature sensor.*/ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + + /* Starts an ADC continuous conversion.*/ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* Activating SPI drivers.*/ + spiStart(&SPID1, &hs_spicfg); + spiStart(&SPID2, &hs_spicfg); + spiStart(&SPID3, &hs_spicfg); + + /* Starting SPI threads instances.*/ + chThdCreateStatic(waSPI1, sizeof(waSPI1), NORMALPRIO + 1, spi_thread, &SPID1); + chThdCreateStatic(waSPI2, sizeof(waSPI2), NORMALPRIO + 1, spi_thread, &SPID2); + chThdCreateStatic(waSPI3, sizeof(waSPI3), NORMALPRIO + 1, spi_thread, &SPID3); + + /* Allocating two DMA2 streams for memory copy operations.*/ + if (dmaStreamAllocate(STM32_DMA2_STREAM6, 0, NULL, NULL)) + chSysHalt(); + if (dmaStreamAllocate(STM32_DMA2_STREAM7, 0, NULL, NULL)) + chSysHalt(); + for (i = 0; i < sizeof (patterns1); i++) + patterns1[i] = (uint8_t)i; + for (i = 0; i < sizeof (patterns2); i++) + patterns2[i] = (uint8_t)(i ^ 0xAA); + + /* Normal main() thread activity, it does continues memory copy operations + using 2 DMA streams at the lowest priority.*/ + while (TRUE) { + VirtualTimer vt; + + /* Starts a VT working as watchdog to catch a malfunction in the DMA + driver.*/ + chSysLock(); + chVTSetI(&vt, MS2ST(10), tmo, NULL); + chSysUnlock(); + + /* Copy pattern 1.*/ + dmaStartMemCopy(STM32_DMA2_STREAM6, + STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE, + patterns1, buf1, sizeof (patterns1)); + dmaStartMemCopy(STM32_DMA2_STREAM7, + STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE, + patterns1, buf2, sizeof (patterns1)); + dmaWaitCompletion(STM32_DMA2_STREAM6); + dmaWaitCompletion(STM32_DMA2_STREAM7); + if (memcmp(patterns1, buf1, sizeof (patterns1))) + chSysHalt(); + if (memcmp(patterns1, buf2, sizeof (patterns1))) + chSysHalt(); + + /* Copy pattern 2.*/ + dmaStartMemCopy(STM32_DMA2_STREAM6, + STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE, + patterns2, buf1, sizeof (patterns2)); + dmaStartMemCopy(STM32_DMA2_STREAM7, + STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE, + patterns2, buf2, sizeof (patterns2)); + dmaWaitCompletion(STM32_DMA2_STREAM6); + dmaWaitCompletion(STM32_DMA2_STREAM7); + if (memcmp(patterns2, buf1, sizeof (patterns2))) + chSysHalt(); + if (memcmp(patterns2, buf2, sizeof (patterns2))) + chSysHalt(); + + /* Stops the watchdog.*/ + chSysLock(); + if (chVTIsArmedI(&vt)) + chVTResetI(&vt); + chSysUnlock(); + + chThdSleepMilliseconds(2); + } + return 0; +} diff --git a/testhal/STM32F4xx/DMA_STORM/mcuconf.h b/testhal/STM32F4xx/DMA_STORM/mcuconf.h new file mode 100644 index 000000000..84cd9a0f1 --- /dev/null +++ b/testhal/STM32F4xx/DMA_STORM/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/EXT/.cproject b/testhal/STM32F4xx/EXT/.cproject new file mode 100644 index 000000000..59e262be9 --- /dev/null +++ b/testhal/STM32F4xx/EXT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/EXT/.project b/testhal/STM32F4xx/EXT/.project new file mode 100644 index 000000000..b4ae995c3 --- /dev/null +++ b/testhal/STM32F4xx/EXT/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/EXT/Makefile b/testhal/STM32F4xx/EXT/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/EXT/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/EXT/chconf.h b/testhal/STM32F4xx/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/EXT/halconf.h b/testhal/STM32F4xx/EXT/halconf.h new file mode 100644 index 000000000..e0e0c38ff --- /dev/null +++ b/testhal/STM32F4xx/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/EXT/main.c b/testhal/STM32F4xx/EXT/main.c new file mode 100644 index 000000000..1bdce5a09 --- /dev/null +++ b/testhal/STM32F4xx/EXT/main.c @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led5off(void *arg) { + + (void)arg; + palClearPad(GPIOD, GPIOD_LED5); +} + +/* Triggered when the button is pressed or released. The LED5 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palSetPad(GPIOD, GPIOD_LED5); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led5off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F4xx/EXT/mcuconf.h b/testhal/STM32F4xx/EXT/mcuconf.h new file mode 100644 index 000000000..172f90b30 --- /dev/null +++ b/testhal/STM32F4xx/EXT/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/EXT/readme.txt b/testhal/STM32F4xx/EXT/readme.txt new file mode 100644 index 000000000..1105f431e --- /dev/null +++ b/testhal/STM32F4xx/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/GPT/.cproject b/testhal/STM32F4xx/GPT/.cproject new file mode 100644 index 000000000..4933adfbb --- /dev/null +++ b/testhal/STM32F4xx/GPT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/GPT/.project b/testhal/STM32F4xx/GPT/.project new file mode 100644 index 000000000..90014959c --- /dev/null +++ b/testhal/STM32F4xx/GPT/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-GPT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/GPT/Makefile b/testhal/STM32F4xx/GPT/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/GPT/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/GPT/chconf.h b/testhal/STM32F4xx/GPT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/GPT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/GPT/halconf.h b/testhal/STM32F4xx/GPT/halconf.h new file mode 100644 index 000000000..554b4e9ca --- /dev/null +++ b/testhal/STM32F4xx/GPT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/GPT/main.c b/testhal/STM32F4xx/GPT/main.c new file mode 100644 index 000000000..4b0031dc3 --- /dev/null +++ b/testhal/STM32F4xx/GPT/main.c @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + + (void)gptp; + palSetPad(GPIOD, GPIOD_LED5); + chSysLockFromIsr(); + gptStartOneShotI(&GPTD3, 1000); /* 0.1 second pulse.*/ + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + + (void)gptp; + palClearPad(GPIOD, GPIOD_LED5); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 10000, /* 10kHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 10000, /* 10kHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the GPT drivers 2 and 3. + */ + gptStart(&GPTD2, &gpt2cfg); + gptPolledDelay(&GPTD2, 10); /* Small delay.*/ + gptStart(&GPTD3, &gpt3cfg); + gptPolledDelay(&GPTD3, 10); /* Small delay.*/ + + /* + * Normal main() thread activity, it changes the GPT1 period every + * five seconds. + */ + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED4); + gptStartContinuous(&GPTD2, 5000); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD2); + palClearPad(GPIOD, GPIOD_LED4); + gptStartContinuous(&GPTD2, 2500); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD2); + } +} diff --git a/testhal/STM32F4xx/GPT/mcuconf.h b/testhal/STM32F4xx/GPT/mcuconf.h new file mode 100644 index 000000000..ffc39aa31 --- /dev/null +++ b/testhal/STM32F4xx/GPT/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_USE_TIM7 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_USE_TIM9 TRUE +#define STM32_GPT_USE_TIM11 TRUE +#define STM32_GPT_USE_TIM12 TRUE +#define STM32_GPT_USE_TIM14 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/GPT/readme.txt b/testhal/STM32F4xx/GPT/readme.txt new file mode 100644 index 000000000..1508a8233 --- /dev/null +++ b/testhal/STM32F4xx/GPT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - GPT driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/I2C/.cproject b/testhal/STM32F4xx/I2C/.cproject new file mode 100644 index 000000000..5effe9a53 --- /dev/null +++ b/testhal/STM32F4xx/I2C/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/I2C/.project b/testhal/STM32F4xx/I2C/.project new file mode 100644 index 000000000..c506abb10 --- /dev/null +++ b/testhal/STM32F4xx/I2C/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-I2C + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/NONSTANDARD_STM32F4_BARTHESS1 + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/I2C/Makefile b/testhal/STM32F4xx/I2C/Makefile new file mode 100644 index 000000000..d52f5d4e8 --- /dev/null +++ b/testhal/STM32F4xx/I2C/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/I2C/chconf.h b/testhal/STM32F4xx/I2C/chconf.h new file mode 100644 index 000000000..9357b698c --- /dev/null +++ b/testhal/STM32F4xx/I2C/chconf.h @@ -0,0 +1,508 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +//#define CORTEX_VTOR_INIT 0x000E0000 +#define CORTEX_VTOR_INIT 0x00000000 + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 0//20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/I2C/halconf.h b/testhal/STM32F4xx/I2C/halconf.h new file mode 100644 index 000000000..8f77e1d4a --- /dev/null +++ b/testhal/STM32F4xx/I2C/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/I2C/main.c b/testhal/STM32F4xx/I2C/main.c new file mode 100644 index 000000000..e83a98ffd --- /dev/null +++ b/testhal/STM32F4xx/I2C/main.c @@ -0,0 +1,181 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * This demo acquire data from accelerometer and prints it in shell. + */ + +#include + +#include "ch.h" +#include "hal.h" + +/* buffers depth */ +#define ACCEL_RX_DEPTH 6 +#define ACCEL_TX_DEPTH 4 + +/* mma8451q specific addresses */ +#define ACCEL_OUT_DATA 0x01 +#define ACCEL_CTRL_REG1 0x2A + +static uint8_t rxbuf[ACCEL_RX_DEPTH]; +static uint8_t txbuf[ACCEL_TX_DEPTH]; +static i2cflags_t errors = 0; +static int16_t acceleration_x, acceleration_y, acceleration_z; +#define mma8451_addr 0b0011100 + +/** + * + */ +static void print(char *p) { + + while (*p) { + sdPut(&SD2, *p++); + } +} + +/** + * + */ +static void println(char *p) { + + while (*p) { + sdPut(&SD2, *p++); + } + sdWriteTimeout(&SD2, (uint8_t *)"\r\n", 2, TIME_INFINITE); +} + +/** + * + */ +static void printn(int16_t n) { + char buf[16], *p; + + if (n > 0) + sdPut(&SD2, '+'); + else{ + sdPut(&SD2, '-'); + n = abs(n); + } + + if (!n) + sdPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + sdPut(&SD2, *--p); + } +} + +/** + * Converts data from 2complemented representation to signed integer + */ +int16_t complement2signed(uint8_t msb, uint8_t lsb){ + uint16_t word = 0; + word = (msb << 8) + lsb; + if (msb > 0x7F){ + return -1 * ((int16_t)((~word) + 1)); + } + return (int16_t)word; +} + +/* I2C interface #2 */ +static const I2CConfig i2cfg2 = { + OPMODE_I2C, + 400000, + FAST_DUTY_CYCLE_2, +}; + +/* + * Application entry point. + */ +int main(void) { + msg_t status = RDY_OK; + systime_t tmo = MS2ST(4); + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Starts I2C + */ + i2cStart(&I2CD2, &i2cfg2); + + /* + * Prepares the Serial driver 2 + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /** + * Prepares the accelerometer + */ + txbuf[0] = ACCEL_CTRL_REG1; /* register address */ + txbuf[1] = 0x1; + i2cAcquireBus(&I2CD2); + status = i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 2, rxbuf, 0, tmo); + i2cReleaseBus(&I2CD2); + + if (status != RDY_OK){ + errors = i2cGetErrors(&I2CD2); + } + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + palTogglePad(GPIOB, GPIOB_LED_B); + chThdSleepMilliseconds(100); + + txbuf[0] = ACCEL_OUT_DATA; /* register address */ + i2cAcquireBus(&I2CD2); + status = i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 1, rxbuf, 6, tmo); + i2cReleaseBus(&I2CD2); + + if (status != RDY_OK){ + errors = i2cGetErrors(&I2CD2); + } + + acceleration_x = complement2signed(rxbuf[0], rxbuf[1]); + acceleration_y = complement2signed(rxbuf[2], rxbuf[3]); + acceleration_z = complement2signed(rxbuf[4], rxbuf[5]); + + print("x: "); + printn(acceleration_x); + print(" y: "); + printn(acceleration_y); + print(" z: "); + printn(acceleration_z); + println(""); + } +} + + + diff --git a/testhal/STM32F4xx/I2C/mcuconf.h b/testhal/STM32F4xx/I2C/mcuconf.h new file mode 100644 index 000000000..da3dba336 --- /dev/null +++ b/testhal/STM32F4xx/I2C/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/IRQ_STORM/.cproject b/testhal/STM32F4xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..1e9c4518b --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM/.project b/testhal/STM32F4xx/IRQ_STORM/.project new file mode 100644 index 000000000..6f3b0385f --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/IRQ_STORM/Makefile b/testhal/STM32F4xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/IRQ_STORM/chconf.h b/testhal/STM32F4xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..38242d75d --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/chconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_USE_FPU FALSE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM/halconf.h b/testhal/STM32F4xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp b/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp new file mode 100644 index 000000000..ffd2532c1 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp @@ -0,0 +1,2289 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww b/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf b/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj b/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj new file mode 100644 index 000000000..b5e042b8a --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj @@ -0,0 +1,945 @@ + + + + 1.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\..\os\kernel\include;..\..\..\..\os\ports\common\ARMCMx;..\..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\..\os\ports\RVCT\ARMCMx;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\..\os\hal\include;..\..\..\..\os\hal\platforms\STM32;..\..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\..\os\hal\platforms\STM32F4xx;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + cmparams.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h + + + vectors.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s + + + nvic.c + 1 + ..\..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\..\os\kernel\include\chvt.h + + + + + hal + + + hal.c + 1 + ..\..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\..\os\hal\src\pal.c + + + serial.c + 1 + ..\..\..\..\os\hal\src\serial.c + + + hal.h + 5 + ..\..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\..\os\hal\include\pal.h + + + serial.h + 5 + ..\..\..\..\os\hal\include\serial.h + + + gpt.h + 5 + ..\..\..\..\os\hal\include\gpt.h + + + gpt.c + 1 + ..\..\..\..\os\hal\src\gpt.c + + + tm.c + 1 + ..\..\..\..\os\hal\src\tm.c + + + + + platform + + + gpt_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\gpt_lld.h + + + gpt_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\gpt_lld.c + + + hal_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + serial_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + serial_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + stm32l1xx.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32l1xx.h + + + + + test + + + test.c + 1 + ..\..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + +     diff --git a/testhal/STM32F4xx/IRQ_STORM/main.c b/testhal/STM32F4xx/IRQ_STORM/main.c new file mode 100644 index 000000000..905af44fe --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/main.c @@ -0,0 +1,327 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOD, GPIOD_LED5); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } + chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 2 and 3. + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 10; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..dc10c0604 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/IRQ_STORM/readme.txt b/testhal/STM32F4xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..2b9f076f5 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/.cproject b/testhal/STM32F4xx/IRQ_STORM_FPU/.cproject new file mode 100644 index 000000000..22b5f4d43 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/.project b/testhal/STM32F4xx/IRQ_STORM_FPU/.project new file mode 100644 index 000000000..46cb19671 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-IRQ_STORM_FPU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile b/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile new file mode 100644 index 000000000..8391b78dc --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = yes +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + extfunc.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h b/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/extfunc.c b/testhal/STM32F4xx/IRQ_STORM_FPU/extfunc.c new file mode 100644 index 000000000..0418e3124 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/extfunc.c @@ -0,0 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +float ff1(float par) { + return par; +} + +float ff2(float par1, float par2, float par3, float par4) { + return (par1 + par2) * (par3 + par4); +} diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h b/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h new file mode 100644 index 000000000..d91a792b4 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp new file mode 100644 index 000000000..186319a4c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp @@ -0,0 +1,2292 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\tm.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\extfunc.c + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj b/testhal/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj new file mode 100644 index 000000000..0f02f5523 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj @@ -0,0 +1,945 @@ + + + + 1.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\..\os\kernel\include;..\..\..\..\os\ports\common\ARMCMx;..\..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\..\os\ports\RVCT\ARMCMx;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\..\os\hal\include;..\..\..\..\os\hal\platforms\STM32;..\..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\..\os\hal\platforms\STM32F4xx;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + cmparams.h + 5 + ..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h + + + vectors.s + 2 + ..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s + + + nvic.c + 1 + ..\..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\..\os\kernel\include\chvt.h + + + + + hal + + + hal.c + 1 + ..\..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\..\os\hal\src\pal.c + + + serial.c + 1 + ..\..\..\..\os\hal\src\serial.c + + + hal.h + 5 + ..\..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\..\os\hal\include\pal.h + + + serial.h + 5 + ..\..\..\..\os\hal\include\serial.h + + + gpt.h + 5 + ..\..\..\..\os\hal\include\gpt.h + + + gpt.c + 1 + ..\..\..\..\os\hal\src\gpt.c + + + + + platform + + + gpt_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\gpt_lld.h + + + gpt_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\gpt_lld.c + + + hal_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + serial_lld.c + 1 + ..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + serial_lld.h + 5 + ..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + stm32l1xx.h + 5 + ..\..\..\..\os\hal\platforms\STM32F4xx\stm32l1xx.h + + + + + test + + + test.c + 1 + ..\..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + extfunc.c + 1 + ..\extfunc.c + + + + + + + +     diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/main.c b/testhal/STM32F4xx/IRQ_STORM_FPU/main.c new file mode 100644 index 000000000..ad72cc0b9 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/main.c @@ -0,0 +1,300 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +float ff1(float par); + +float ff2(float par1, float par2, float par3, float par4); + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +static bool_t saturated; + +/* + * Test worker thread. + */ +static WORKING_AREA(waWorkerThread, 128); +static msg_t WorkerThread(void *arg) { + + (void)arg; + + while(1) { + float f1, f2, f3, f4, f5; + + f1 = ff1(3.0f); + f2 = ff1(4.0f); + f3 = ff1(5.0f); + f5 = f1 + f2 + f3; + f4 = ff1(6.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 324.0f) + chSysHalt(); + } +} + +/* + * Test periodic thread. + */ +static WORKING_AREA(waPeriodicThread, 128); +static msg_t PeriodicThread(void *arg) { + + (void)arg; + + while(1) { + float f1, f2, f3, f4, f5; + + f1 = ff1(4.0f); + f2 = ff1(5.0f); + f3 = ff1(6.0f); + f5 = f1 + f2 + f3; + f4 = ff1(7.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 484.0f) + chSysHalt(); + chThdSleepSeconds(1); + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + float f1, f2, f3, f4, f5; + + (void)gptp; + + f1 = ff1(2.0f); + f2 = ff1(3.0f); + f3 = ff1(4.0f); + f5 = f1 + f2 + f3; + f4 = ff1(5.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 196.0f) + chSysHalt(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + float f1, f2, f3, f4, f5; + + (void)gptp; + + f1 = ff1(1.0f); + f2 = ff1(2.0f); + f3 = ff1(3.0f); + f5 = f1 + f2 + f3; + f4 = ff1(4.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 100.0f) + chSysHalt(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } + chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 2 and 3. + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the worker threads. + */ + chThdCreateStatic(waWorkerThread, sizeof waWorkerThread, + NORMALPRIO - 20, WorkerThread, NULL); + chThdCreateStatic(waPeriodicThread, sizeof waPeriodicThread, + NORMALPRIO - 10, PeriodicThread, NULL); + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM-FPU long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 10; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h new file mode 100644 index 000000000..dc10c0604 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/readme.txt b/testhal/STM32F4xx/IRQ_STORM_FPU/readme.txt new file mode 100644 index 000000000..cb043261f --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM_FPU stress test demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT, PAL and Serial +drivers in order to implement a system stress demo involving the FPU. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using YAGARTO 4.6.2. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/PWM-ICU/.cproject b/testhal/STM32F4xx/PWM-ICU/.cproject new file mode 100644 index 000000000..940a1c9d5 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/PWM-ICU/.project b/testhal/STM32F4xx/PWM-ICU/.project new file mode 100644 index 000000000..ebfbb62af --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/PWM-ICU/Makefile b/testhal/STM32F4xx/PWM-ICU/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/PWM-ICU/chconf.h b/testhal/STM32F4xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/PWM-ICU/halconf.h b/testhal/STM32F4xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..2f74c82c8 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/PWM-ICU/main.c b/testhal/STM32F4xx/PWM-ICU/main.c new file mode 100644 index 000000000..dc6287209 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/main.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOD, GPIOD_LED5); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOD, GPIOD_LED5); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOD, GPIOD_LED4); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOD, GPIOD_LED4); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA15 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOD, GPIOD_LED4); + palClearPad(GPIOD, GPIOD_LED5); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F4xx/PWM-ICU/mcuconf.h b/testhal/STM32F4xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..e1e2badda --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/PWM-ICU/readme.txt b/testhal/STM32F4xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..bd908948f --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx PWM-ICU drivers. + +** Board Setup ** + +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/RTC/.cproject b/testhal/STM32F4xx/RTC/.cproject new file mode 100644 index 000000000..685ffe5f1 --- /dev/null +++ b/testhal/STM32F4xx/RTC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/RTC/.project b/testhal/STM32F4xx/RTC/.project new file mode 100644 index 000000000..b281eb7d2 --- /dev/null +++ b/testhal/STM32F4xx/RTC/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-RTC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/RTC/Makefile b/testhal/STM32F4xx/RTC/Makefile new file mode 100644 index 000000000..e383fef85 --- /dev/null +++ b/testhal/STM32F4xx/RTC/Makefile @@ -0,0 +1,226 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/chrtclib.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/RTC/chconf.h b/testhal/STM32F4xx/RTC/chconf.h new file mode 100644 index 000000000..0a00640e2 --- /dev/null +++ b/testhal/STM32F4xx/RTC/chconf.h @@ -0,0 +1,508 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define PORT_IDLE_THREAD_STACK_SIZE 32 +#define CORTEX_USE_FPU FALSE + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 0//20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/RTC/halconf.h b/testhal/STM32F4xx/RTC/halconf.h new file mode 100644 index 000000000..f0040635d --- /dev/null +++ b/testhal/STM32F4xx/RTC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/RTC/main.c b/testhal/STM32F4xx/RTC/main.c new file mode 100644 index 000000000..6b25d371a --- /dev/null +++ b/testhal/STM32F4xx/RTC/main.c @@ -0,0 +1,239 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* +This structure is used to hold the values representing a calendar time. +It contains the following members, with the meanings as shown. + +int tm_sec seconds after minute [0-61] (61 allows for 2 leap-seconds) +int tm_min minutes after hour [0-59] +int tm_hour hours after midnight [0-23] +int tm_mday day of the month [1-31] +int tm_mon month of year [0-11] +int tm_year current year-1900 +int tm_wday days since Sunday [0-6] +int tm_yday days since January 1st [0-365] +int tm_isdst daylight savings indicator (1 = yes, 0 = no, -1 = unknown) +*/ +#define WAKEUP_TEST FALSE + +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" +#include "chrtclib.h" + +#if WAKEUP_TEST +static RTCWakeup wakeupspec; +#endif +static RTCAlarm alarmspec; +static time_t unix_time; + +/* libc stub */ +int _getpid(void) {return 1;} +/* libc stub */ +void _exit(int i) {(void)i;} +/* libc stub */ +#include +#undef errno +extern int errno; +int _kill(int pid, int sig) { + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + + +/* sleep indicator thread */ +static WORKING_AREA(blinkWA, 128); +static msg_t blink_thd(void *arg){ + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(100); + palTogglePad(GPIOB, GPIOB_LED_R); + } + return 0; +} + +static void func_sleep(void){ + chSysLock(); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); + RTC->ISR &= ~(RTC_ISR_ALRBF | RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TAMP1F | + RTC_ISR_TSOVF | RTC_ISR_TSF); + __WFI(); +} + +static void cmd_sleep(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: sleep\r\n"); + return; + } + chprintf(chp, "Going to sleep.\r\n"); + + chThdSleepMilliseconds(200); + + /* going to anabiosis */ + func_sleep(); +} + +/* + * + */ +static void cmd_alarm(BaseSequentialStream *chp, int argc, char *argv[]){ + int i = 0; + + (void)argv; + if (argc < 1) { + goto ERROR; + } + + if ((argc == 1) && (strcmp(argv[0], "get") == 0)){ + rtcGetAlarm(&RTCD1, 0, &alarmspec); + chprintf(chp, "%D%s",alarmspec," - alarm in STM internal format\r\n"); + return; + } + + if ((argc == 2) && (strcmp(argv[0], "set") == 0)){ + i = atol(argv[1]); + alarmspec.tv_datetime = ((i / 10) & 7 << 4) | (i % 10) | RTC_ALRMAR_MSK4 | + RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + return; + } + else{ + goto ERROR; + } + +ERROR: + chprintf(chp, "Usage: alarm get\r\n"); + chprintf(chp, " alarm set N\r\n"); + chprintf(chp, "where N is alarm time in seconds\r\n"); +} + +/* + * + */ +static void cmd_date(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argv; + struct tm timp; + + if (argc == 0) { + goto ERROR; + } + + if ((argc == 1) && (strcmp(argv[0], "get") == 0)){ + unix_time = rtcGetTimeUnixSec(&RTCD1); + + if (unix_time == -1){ + chprintf(chp, "incorrect time in RTC cell\r\n"); + } + else{ + chprintf(chp, "%D%s",unix_time," - unix time\r\n"); + rtcGetTimeTm(&RTCD1, &timp); + chprintf(chp, "%s%s",asctime(&timp)," - formatted time string\r\n"); + } + return; + } + + if ((argc == 2) && (strcmp(argv[0], "set") == 0)){ + unix_time = atol(argv[1]); + if (unix_time > 0){ + rtcSetTimeUnixSec(&RTCD1, unix_time); + return; + } + else{ + goto ERROR; + } + } + else{ + goto ERROR; + } + +ERROR: + chprintf(chp, "Usage: date get\r\n"); + chprintf(chp, " date set N\r\n"); + chprintf(chp, "where N is time in seconds sins Unix epoch\r\n"); + chprintf(chp, "you can get current N value from unix console by the command\r\n"); + chprintf(chp, "%s", "date +\%s\r\n"); + return; +} + +static SerialConfig ser_cfg = { + 115200, + 0, + 0, + 0, +}; + +static const ShellCommand commands[] = { + {"alarm", cmd_alarm}, + {"date", cmd_date}, + {"sleep", cmd_sleep}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + + +/** + * Main function. + */ +int main(void){ + + halInit(); + chSysInit(); + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + +#if !WAKEUP_TEST + /* switch off wakeup */ + rtcSetPeriodicWakeup_v2(&RTCD1, NULL); + + /* Shell initialization.*/ + sdStart(&SD2, &ser_cfg); + shellInit(); + static WORKING_AREA(waShell, 1024); + shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); + + /* wait until user do not want to test wakeup */ + while (TRUE){ + chThdSleepMilliseconds(200); + } + +#else + /* set wakeup */ + wakeupspec.wakeup = ((uint32_t)4) << 16; /* select 1 Hz clock source */ + wakeupspec.wakeup |= 9; /* set counter value to 9. Period will be 9+1 seconds. */ + rtcSetPeriodicWakeup_v2(&RTCD1, &wakeupspec); + + chThdSleepSeconds(3); + func_sleep(); +#endif /* !WAKEUP_TEST */ + + return 0; +} + + diff --git a/testhal/STM32F4xx/RTC/mcuconf.h b/testhal/STM32F4xx/RTC/mcuconf.h new file mode 100644 index 000000000..5feae3259 --- /dev/null +++ b/testhal/STM32F4xx/RTC/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/RTC_FATTIME/Makefile b/testhal/STM32F4xx/RTC_FATTIME/Makefile new file mode 100644 index 000000000..ffd36e3d2 --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 #-mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/chrtclib.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various $(FATFSINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/RTC_FATTIME/chconf.h b/testhal/STM32F4xx/RTC_FATTIME/chconf.h new file mode 100644 index 000000000..868377751 --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/chconf.h @@ -0,0 +1,534 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define PORT_IDLE_THREAD_STACK_SIZE 32 +#define CORTEX_USE_FPU FALSE + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/RTC_FATTIME/ffconf.h b/testhal/STM32F4xx/RTC_FATTIME/ffconf.h new file mode 100644 index 000000000..a4816e845 --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1251 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 1 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/testhal/STM32F4xx/RTC_FATTIME/halconf.h b/testhal/STM32F4xx/RTC_FATTIME/halconf.h new file mode 100644 index 000000000..f33c18c27 --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/halconf.h @@ -0,0 +1,319 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_WRITE_TIMEOUT_MS 250 +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_READ_TIMEOUT_MS 5 +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/RTC_FATTIME/main.c b/testhal/STM32F4xx/RTC_FATTIME/main.c new file mode 100644 index 000000000..3c031ade0 --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/main.c @@ -0,0 +1,218 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" +#include "chrtclib.h" + +#include "ff.h" + +/* FS object.*/ +static FATFS SDC_FS; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/** + * + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + (void)sdcp; + return FALSE; +} + +/** + * + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + (void)sdcp; + return !palReadPad(GPIOE, GPIOE_SDIO_DETECT); +} + +/** + * + */ +void cmd_sdiotest(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argc; + (void)argv; + FRESULT err; + uint32_t clusters; + FATFS *fsp; + FIL FileObject; + //FILINFO FileInfo; + size_t bytes_written; + struct tm timp; + +#if !HAL_USE_RTC + chprintf(chp, "ERROR! Chibios compiled without RTC support."); + chprintf(chp, "Enable HAL_USE_RCT in you halconf.h"); + chThdSleepMilliseconds(100); + return; +#endif + + chprintf(chp, "Trying to connect SDIO... "); + chThdSleepMilliseconds(100); + + if (!sdcConnect(&SDCD1)) { + chprintf(chp, "OK\r\n"); + chprintf(chp, "Register working area for filesystem... "); + chThdSleepMilliseconds(100); + err = f_mount(0, &SDC_FS); + if (err != FR_OK){ + chSysHalt(); + } + else{ + fs_ready = TRUE; + chprintf(chp, "OK\r\n"); + } + + chprintf(chp, "Mounting filesystem... "); + chThdSleepMilliseconds(100); + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)SDC_FS.csize, + clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + + rtcGetTimeTm(&RTCD1, &timp); + chprintf(chp, "Current RTC time is: "); + chprintf(chp, "%u-%u-%u %u:%u:%u\r\n", + timp.tm_year+1900, timp.tm_mon+1, timp.tm_mday, timp.tm_hour, timp.tm_min, + timp.tm_sec); + + chprintf(chp, "Creating empty file 'tmstmp.tst'... "); + chThdSleepMilliseconds(100); + err = f_open(&FileObject, "0:tmstmp.tst", FA_WRITE | FA_OPEN_ALWAYS); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Write some data in it... "); + chThdSleepMilliseconds(100); + err = f_write(&FileObject, "tst", sizeof("tst"), (void *)&bytes_written); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Closing file 'tmstmp.tst'... "); + chThdSleepMilliseconds(100); + err = f_close(&FileObject); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + +// chprintf(chp, "Obtaining file info ... "); +// chThdSleepMilliseconds(100); +// err = f_stat("0:tmstmp.tst", &FileInfo); +// if (err != FR_OK) { +// chSysHalt(); +// } +// else{ +// chprintf(chp, "OK\r\n"); +// chprintf(chp, " Timestamp: %u-%u-%u %u:%u:%u\r\n", +// ((FileInfo.fdate >> 9) & 127) + 1980, +// (FileInfo.fdate >> 5) & 15, +// FileInfo.fdate & 31, +// (FileInfo.ftime >> 11) & 31, +// (FileInfo.ftime >> 5) & 63, +// (FileInfo.ftime & 31) * 2); +// } + + chprintf(chp, "Umounting filesystem... "); + f_mount(0, NULL); + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Disconnecting from SDIO..."); + chThdSleepMilliseconds(100); + if (sdcDisconnect(&SDCD1)) + chSysHalt(); + chprintf(chp, " OK\r\n"); + chprintf(chp, "------------------------------------------------------\r\n"); + chprintf(chp, "Now you can remove memory card and check timestamp on PC.\r\n"); + chThdSleepMilliseconds(100); + } + else{ + chSysHalt(); + } +} + +/* + * SDIO configuration. + */ +static const SDCConfig sdccfg = { + 0 +}; + +/** + * + */ +static SerialConfig ser_cfg = { + 115200, + 0, + 0, + 0, +}; +static const ShellCommand commands[] = { + {"sdiotest", cmd_sdiotest}, + {NULL, NULL} +}; +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/* + * Application entry point. + */ +int main(void) { + halInit(); + chSysInit(); + + /* start debugging serial link */ + sdStart(&SD2, &ser_cfg); + shellInit(); + static WORKING_AREA(waShell, 4096); + shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); + + /* + * Initializes the SDIO drivers. + */ + sdcStart(&SDCD1, &sdccfg); + + /* + * Normal main() thread activity. + * Blinking signaling about successful passing. + */ + while (TRUE) { + palTogglePad(GPIOB, GPIOB_LED_R); + chThdSleepMilliseconds(100); + } +} diff --git a/testhal/STM32F4xx/RTC_FATTIME/mcuconf.h b/testhal/STM32F4xx/RTC_FATTIME/mcuconf.h new file mode 100644 index 000000000..a8d51babe --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/RTC_FATTIME/readme.txt b/testhal/STM32F4xx/RTC_FATTIME/readme.txt new file mode 100644 index 000000000..b5036cd2c --- /dev/null +++ b/testhal/STM32F4xx/RTC_FATTIME/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - SDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex ST_STM3210E_EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32 RTC driver for timestamping +files on FAT. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/SDC/.cproject b/testhal/STM32F4xx/SDC/.cproject new file mode 100644 index 000000000..5315ed60f --- /dev/null +++ b/testhal/STM32F4xx/SDC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/SDC/.project b/testhal/STM32F4xx/SDC/.project new file mode 100644 index 000000000..630877d95 --- /dev/null +++ b/testhal/STM32F4xx/SDC/.project @@ -0,0 +1,43 @@ + + + STM32F4xx-SDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + fatfs + 2 + CHIBIOS/ext/fatfs + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/SDC/Makefile b/testhal/STM32F4xx/SDC/Makefile new file mode 100644 index 000000000..b22e616e5 --- /dev/null +++ b/testhal/STM32F4xx/SDC/Makefile @@ -0,0 +1,230 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various $(FATFSINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/SDC/chconf.h b/testhal/STM32F4xx/SDC/chconf.h new file mode 100644 index 000000000..868377751 --- /dev/null +++ b/testhal/STM32F4xx/SDC/chconf.h @@ -0,0 +1,534 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define PORT_IDLE_THREAD_STACK_SIZE 32 +#define CORTEX_USE_FPU FALSE + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SDC/csd.txt b/testhal/STM32F4xx/SDC/csd.txt new file mode 100644 index 000000000..eefe5274c --- /dev/null +++ b/testhal/STM32F4xx/SDC/csd.txt @@ -0,0 +1,7 @@ +127 ... ... 0 + +00000000 00101110 00000000 00110010 - 01011011 01011010 10100011 10100000 - 11111111111111111111111110000000 - 00001010100000000000000010001110 kingmax 2 GB +00000000 00101110 00000000 00110010 - 01011011 01011010 10000011 10101001 - 11111111111111111111111110000000 - 00010110100000000000000010010000 kingstone 2 GB +01000000 00001110 00000000 00110010 - 01011011 01011001 00000000 00000000 - 00111011010010110111111110000000 - 00001010010000000100000001000000 samsung sdhc 8 GB +00000000 00100110 00000000 00110010 - 01011111 01011010 10000011 10101110 - 11111110111110111100111111111111 - 10010010100000000100000011011110 noname 2 GB + diff --git a/testhal/STM32F4xx/SDC/ffconf.h b/testhal/STM32F4xx/SDC/ffconf.h new file mode 100644 index 000000000..9073f2286 --- /dev/null +++ b/testhal/STM32F4xx/SDC/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1251 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/testhal/STM32F4xx/SDC/halconf.h b/testhal/STM32F4xx/SDC/halconf.h new file mode 100644 index 000000000..7c79feea0 --- /dev/null +++ b/testhal/STM32F4xx/SDC/halconf.h @@ -0,0 +1,319 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_WRITE_TIMEOUT_MS 250 +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) +#define SDC_READ_TIMEOUT_MS 5 +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SDC/main.c b/testhal/STM32F4xx/SDC/main.c new file mode 100644 index 000000000..721eac66b --- /dev/null +++ b/testhal/STM32F4xx/SDC/main.c @@ -0,0 +1,382 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + +#include "ff.h" + +#define SDC_DATA_DESTRUCTIVE_TEST FALSE + +#define SDC_BURST_SIZE 8 /* how many sectors reads at once */ +static uint8_t outbuf[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE + 1]; +static uint8_t inbuf[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE + 1]; + +/* FS object.*/ +static FATFS SDC_FS; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/** + * @brief Parody of UNIX badblocks program. + * + * @param[in] start first block to check + * @param[in] end last block to check + * @param[in] blockatonce number of blocks to check at once + * @param[in] pattern check pattern + * + * @return The operation status. + * @retval SDC_SUCCESS operation succeeded, the requested blocks have been + * read. + * @retval SDC_FAILED operation failed, the state of the buffer is uncertain. + */ +bool_t badblocks(uint32_t start, uint32_t end, uint32_t blockatonce, uint8_t pattern){ + uint32_t position = 0; + uint32_t i = 0; + + chDbgCheck(blockatonce <= SDC_BURST_SIZE, "badblocks"); + + /* fill control buffer */ + for (i=0; i < MMCSD_BLOCK_SIZE * blockatonce; i++) + outbuf[i] = pattern; + + /* fill SD card with pattern. */ + position = start; + while (position < end){ + if (sdcWrite(&SDCD1, position, outbuf, blockatonce)) + goto ERROR; + position += blockatonce; + } + + /* read and compare. */ + position = start; + while (position < end){ + if (sdcRead(&SDCD1, position, inbuf, blockatonce)) + goto ERROR; + if (memcmp(inbuf, outbuf, blockatonce * MMCSD_BLOCK_SIZE) != 0) + goto ERROR; + position += blockatonce; + } + return FALSE; + +ERROR: + return TRUE; +} + +/** + * + */ +void fillbuffer(uint8_t pattern, uint8_t *b){ + uint32_t i = 0; + for (i=0; i < MMCSD_BLOCK_SIZE * SDC_BURST_SIZE; i++) + b[i] = pattern; +} + +/** + * + */ +void fillbuffers(uint8_t pattern){ + fillbuffer(pattern, inbuf); + fillbuffer(pattern, outbuf); +} + +/** + * + */ +void cmd_sdiotest(BaseSequentialStream *chp, int argc, char *argv[]){ + (void)argc; + (void)argv; + uint32_t i = 0; + + chprintf(chp, "Trying to connect SDIO... "); + chThdSleepMilliseconds(100); + + if (!sdcConnect(&SDCD1)) { + + chprintf(chp, "OK\r\n"); + chprintf(chp, "*** Card CSD content is: "); + chprintf(chp, "%X %X %X %X \r\n", (&SDCD1)->csd[3], (&SDCD1)->csd[2], + (&SDCD1)->csd[1], (&SDCD1)->csd[0]); + + chprintf(chp, "Single aligned read..."); + chThdSleepMilliseconds(100); + if (sdcRead(&SDCD1, 0, inbuf, 1)) + chSysHalt(); + chprintf(chp, " OK\r\n"); + chThdSleepMilliseconds(100); + + + chprintf(chp, "Single unaligned read..."); + chThdSleepMilliseconds(100); + if (sdcRead(&SDCD1, 0, inbuf + 1, 1)) + chSysHalt(); + if (sdcRead(&SDCD1, 0, inbuf + 2, 1)) + chSysHalt(); + if (sdcRead(&SDCD1, 0, inbuf + 3, 1)) + chSysHalt(); + chprintf(chp, " OK\r\n"); + chThdSleepMilliseconds(100); + + + chprintf(chp, "Multiple aligned reads..."); + chThdSleepMilliseconds(100); + fillbuffers(0x55); + /* fill reference buffer from SD card */ + if (sdcRead(&SDCD1, 0, inbuf, SDC_BURST_SIZE)) + chSysHalt(); + for (i=0; i<1000; i++){ + if (sdcRead(&SDCD1, 0, outbuf, SDC_BURST_SIZE)) + chSysHalt(); + if (memcmp(inbuf, outbuf, SDC_BURST_SIZE * MMCSD_BLOCK_SIZE) != 0) + chSysHalt(); + } + chprintf(chp, " OK\r\n"); + chThdSleepMilliseconds(100); + + + chprintf(chp, "Multiple unaligned reads..."); + chThdSleepMilliseconds(100); + fillbuffers(0x55); + /* fill reference buffer from SD card */ + if (sdcRead(&SDCD1, 0, inbuf + 1, SDC_BURST_SIZE)) + chSysHalt(); + for (i=0; i<1000; i++){ + if (sdcRead(&SDCD1, 0, outbuf + 1, SDC_BURST_SIZE)) + chSysHalt(); + if (memcmp(inbuf, outbuf, SDC_BURST_SIZE * MMCSD_BLOCK_SIZE) != 0) + chSysHalt(); + } + chprintf(chp, " OK\r\n"); + chThdSleepMilliseconds(100); + +#if SDC_DATA_DESTRUCTIVE_TEST + + chprintf(chp, "Single aligned write..."); + chThdSleepMilliseconds(100); + fillbuffer(0xAA, inbuf); + if (sdcWrite(&SDCD1, 0, inbuf, 1)) + chSysHalt(); + fillbuffer(0, outbuf); + if (sdcRead(&SDCD1, 0, outbuf, 1)) + chSysHalt(); + if (memcmp(inbuf, outbuf, MMCSD_BLOCK_SIZE) != 0) + chSysHalt(); + chprintf(chp, " OK\r\n"); + + chprintf(chp, "Single unaligned write..."); + chThdSleepMilliseconds(100); + fillbuffer(0xFF, inbuf); + if (sdcWrite(&SDCD1, 0, inbuf+1, 1)) + chSysHalt(); + fillbuffer(0, outbuf); + if (sdcRead(&SDCD1, 0, outbuf+1, 1)) + chSysHalt(); + if (memcmp(inbuf+1, outbuf+1, MMCSD_BLOCK_SIZE) != 0) + chSysHalt(); + chprintf(chp, " OK\r\n"); + + chprintf(chp, "Running badblocks at 0x10000 offset..."); + chThdSleepMilliseconds(100); + if(badblocks(0x10000, 0x11000, SDC_BURST_SIZE, 0xAA)) + chSysHalt(); + chprintf(chp, " OK\r\n"); +#endif /* !SDC_DATA_DESTRUCTIVE_TEST */ + + + /** + * Now perform some FS tests. + */ + + FRESULT err; + uint32_t clusters; + FATFS *fsp; + FIL FileObject; + uint32_t bytes_written; + uint32_t bytes_read; + FILINFO filinfo; + uint8_t teststring[] = {"This is test file\r\n"}; + + chprintf(chp, "Register working area for filesystem... "); + chThdSleepMilliseconds(100); + err = f_mount(0, &SDC_FS); + if (err != FR_OK){ + chSysHalt(); + } + else{ + fs_ready = TRUE; + chprintf(chp, "OK\r\n"); + } + + +#if SDC_DATA_DESTRUCTIVE_TEST + chprintf(chp, "Formatting... "); + chThdSleepMilliseconds(100); + err = f_mkfs (0,0,0); + if (err != FR_OK){ + chSysHalt(); + } + else{ + chprintf(chp, "OK\r\n"); + } +#endif /* SDC_DATA_DESTRUCTIVE_TEST */ + + + chprintf(chp, "Mount filesystem... "); + chThdSleepMilliseconds(100); + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + chprintf(chp, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n", + clusters, (uint32_t)SDC_FS.csize, + clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE); + + + chprintf(chp, "Create file \"chtest.txt\"... "); + chThdSleepMilliseconds(100); + err = f_open(&FileObject, "0:chtest.txt", FA_WRITE | FA_OPEN_ALWAYS); + if (err != FR_OK) { + chSysHalt(); + } + chprintf(chp, "OK\r\n"); + chprintf(chp, "Write some data in it... "); + chThdSleepMilliseconds(100); + err = f_write(&FileObject, teststring, sizeof(teststring), (void *)&bytes_written); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Close file \"chtest.txt\"... "); + err = f_close(&FileObject); + if (err != FR_OK) { + chSysHalt(); + } + else + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Check file size \"chtest.txt\"... "); + err = f_stat("0:chtest.txt", &filinfo); + chThdSleepMilliseconds(100); + if (err != FR_OK) { + chSysHalt(); + } + else{ + if (filinfo.fsize == sizeof(teststring)) + chprintf(chp, "OK\r\n"); + else + chSysHalt(); + } + + chprintf(chp, "Check file content \"chtest.txt\"... "); + err = f_open(&FileObject, "0:chtest.txt", FA_READ | FA_OPEN_EXISTING); + chThdSleepMilliseconds(100); + if (err != FR_OK) { + chSysHalt(); + } + uint8_t buf[sizeof(teststring)]; + err = f_read(&FileObject, buf, sizeof(teststring), (void *)&bytes_read); + if (err != FR_OK) { + chSysHalt(); + } + else{ + if (memcmp(teststring, buf, sizeof(teststring)) != 0){ + chSysHalt(); + } + else{ + chprintf(chp, "OK\r\n"); + } + } + + chprintf(chp, "Umount filesystem... "); + f_mount(0, NULL); + chprintf(chp, "OK\r\n"); + + chprintf(chp, "Disconnecting from SDIO..."); + chThdSleepMilliseconds(100); + if (sdcDisconnect(&SDCD1)) + chSysHalt(); + chprintf(chp, " OK\r\n"); + chprintf(chp, "------------------------------------------------------\r\n"); + chprintf(chp, "All tests passed successfully.\r\n"); + chThdSleepMilliseconds(100); + } + else{ + chSysHalt(); + } +} + + +/* + * SDIO configuration. + */ +static const SDCConfig sdccfg = { + 0 +}; + +/** + * + */ +static SerialConfig ser_cfg = { + 115200, + 0, + 0, + 0, +}; +static const ShellCommand commands[] = { + {"sdiotest", cmd_sdiotest}, + {NULL, NULL} +}; +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/* + * Application entry point. + */ +int main(void) { + halInit(); + chSysInit(); + + /* start debugging serial link */ + sdStart(&SD2, &ser_cfg); + shellInit(); + static WORKING_AREA(waShell, 2048); + shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); + + /* + * Initializes the SDIO drivers. + */ + sdcStart(&SDCD1, &sdccfg); + + /* + * Normal main() thread activity. + * Blinking signaling about successful passing. + */ + while (TRUE) { + palTogglePad(GPIOB, GPIOB_LED_R); + chThdSleepMilliseconds(100); + } +} diff --git a/testhal/STM32F4xx/SDC/mcuconf.h b/testhal/STM32F4xx/SDC/mcuconf.h new file mode 100644 index 000000000..a8d51babe --- /dev/null +++ b/testhal/STM32F4xx/SDC/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/SDC/readme.txt b/testhal/STM32F4xx/SDC/readme.txt new file mode 100644 index 000000000..b897676af --- /dev/null +++ b/testhal/STM32F4xx/SDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex ST_STM3210E_EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32 SDC driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/SPI/.cproject b/testhal/STM32F4xx/SPI/.cproject new file mode 100644 index 000000000..6b2c42453 --- /dev/null +++ b/testhal/STM32F4xx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/SPI/.project b/testhal/STM32F4xx/SPI/.project new file mode 100644 index 000000000..effebe09e --- /dev/null +++ b/testhal/STM32F4xx/SPI/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/SPI/Makefile b/testhal/STM32F4xx/SPI/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/SPI/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/SPI/chconf.h b/testhal/STM32F4xx/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SPI/halconf.h b/testhal/STM32F4xx/SPI/halconf.h new file mode 100644 index 000000000..3e1cafbbf --- /dev/null +++ b/testhal/STM32F4xx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SPI/main.c b/testhal/STM32F4xx/SPI/main.c new file mode 100644 index 000000000..04999434b --- /dev/null +++ b/testhal/STM32F4xx/SPI/main.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0 +}; + +/* + * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOD, GPIOD_LED5); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOD, GPIOD_LED5); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI2 I/O pins setup. + */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F4xx/SPI/mcuconf.h b/testhal/STM32F4xx/SPI/mcuconf.h new file mode 100644 index 000000000..21f5e5dcc --- /dev/null +++ b/testhal/STM32F4xx/SPI/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/SPI/readme.txt b/testhal/STM32F4xx/SPI/readme.txt new file mode 100644 index 000000000..d3d78bc8c --- /dev/null +++ b/testhal/STM32F4xx/SPI/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/UART/.cproject b/testhal/STM32F4xx/UART/.cproject new file mode 100644 index 000000000..7bb8c14a7 --- /dev/null +++ b/testhal/STM32F4xx/UART/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/UART/.project b/testhal/STM32F4xx/UART/.project new file mode 100644 index 000000000..06e8b52e8 --- /dev/null +++ b/testhal/STM32F4xx/UART/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32F4xx/UART/Makefile b/testhal/STM32F4xx/UART/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/UART/Makefile @@ -0,0 +1,222 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/UART/chconf.h b/testhal/STM32F4xx/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/UART/halconf.h b/testhal/STM32F4xx/UART/halconf.h new file mode 100644 index 000000000..520e71b0a --- /dev/null +++ b/testhal/STM32F4xx/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/UART/main.c b/testhal/STM32F4xx/UART/main.c new file mode 100644 index 000000000..fcd6fa965 --- /dev/null +++ b/testhal/STM32F4xx/UART/main.c @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt3, vt4, vt5; + +static const uint8_t message[] = "0123456789ABCDEF"; +static uint8_t buffer[16]; + +static void led3off(void *p) { + + (void)p; + palClearPad(GPIOD, GPIOD_LED3); +} + +static void led4off(void *p) { + + (void)p; + palClearPad(GPIOD, GPIOD_LED4); +} + +static void led5off(void *p) { + + (void)p; + palClearPad(GPIOD, GPIOD_LED5); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOD, GPIOD_LED5); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt5)) + chVTResetI(&vt5); + chVTSetI(&vt5, MS2ST(200), led5off, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOD, GPIOD_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + chVTSetI(&vt4, MS2ST(200), led4off, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; + + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOD, GPIOD_LED3); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt3)) + chVTResetI(&vt3); + chVTSetI(&vt3, MS2ST(200), led3off, NULL); + chSysUnlockFromIsr(); +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the UART driver 2, PA2(TX) and PA3(RX) are routed to USART2. + */ + uartStart(&UARTD2, &uart_cfg_1); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + /* + * Starts both a transmission and a receive operations, both will be + * handled entirely in background. + */ + uartStopReceive(&UARTD2); + uartStopSend(&UARTD2); + uartStartReceive(&UARTD2, 16, buffer); + uartStartSend(&UARTD2, 16, message); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F4xx/UART/mcuconf.h b/testhal/STM32F4xx/UART/mcuconf.h new file mode 100644 index 000000000..102c44dd7 --- /dev/null +++ b/testhal/STM32F4xx/UART/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/UART/readme.txt b/testhal/STM32F4xx/UART/readme.txt new file mode 100644 index 000000000..19a8e26da --- /dev/null +++ b/testhal/STM32F4xx/UART/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx UART driver. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA2(TX) and PA3(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/USB_CDC/.cproject b/testhal/STM32F4xx/USB_CDC/.cproject new file mode 100644 index 000000000..16a94a05d --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F4xx/USB_CDC/.project b/testhal/STM32F4xx/USB_CDC/.project new file mode 100644 index 000000000..135abc544 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/.project @@ -0,0 +1,43 @@ + + + STM32F4xx-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/OLIMEX_STM32_E407 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/testhal/STM32F4xx/USB_CDC/Makefile b/testhal/STM32F4xx/USB_CDC/Makefile new file mode 100644 index 000000000..8c329e2d7 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/Makefile @@ -0,0 +1,223 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_E407/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/USB_CDC/chconf.h b/testhal/STM32F4xx/USB_CDC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/USB_CDC/halconf.h b/testhal/STM32F4xx/USB_CDC/halconf.h new file mode 100644 index 000000000..cd76b0cfe --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/USB_CDC/main.c b/testhal/STM32F4xx/USB_CDC/main.c new file mode 100644 index 000000000..8bdf3c0ba --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/main.c @@ -0,0 +1,522 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "shell.h" +#include "chprintf.h" + +/*===========================================================================*/ +/* USB related stuff. */ +/*===========================================================================*/ + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +/* + * Serial over USB Driver structure. + */ +static SerialUSBDriver SDU2; + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU2); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +static const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +static const SerialUSBConfig serusbcfg = { + &USBD2, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chSequentialStreamWrite(&SDU2, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU2, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + systime_t time; + + time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(time); + palSetPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + Thread *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU2); + sduStart(&SDU2, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Stopping and restarting the USB in order to test the stop procedure. The + * following lines are not usually required. + */ + chThdSleepMilliseconds(3000); + usbDisconnectBus(serusbcfg.usbp); + usbStop(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!shelltp && (SDU2.config->usbp->state == USB_ACTIVE)) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/STM32F4xx/USB_CDC/mcuconf.h b/testhal/STM32F4xx/USB_CDC/mcuconf.h new file mode 100644 index 000000000..34138a27d --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_VOS STM32_VOS_HIGH +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/testhal/STM32F4xx/USB_CDC/readme.txt b/testhal/STM32F4xx/USB_CDC/readme.txt new file mode 100644 index 000000000..a619a3ec1 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - USB-CDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-E407 board. + +** The Demo ** + +The application demonstrates the use of the STM32 USB (OTG) driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/ADC/.cproject b/testhal/STM32L1xx/ADC/.cproject new file mode 100644 index 000000000..dd444dc30 --- /dev/null +++ b/testhal/STM32L1xx/ADC/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/ADC/.project b/testhal/STM32L1xx/ADC/.project new file mode 100644 index 000000000..170610f4f --- /dev/null +++ b/testhal/STM32L1xx/ADC/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/ADC/Makefile b/testhal/STM32L1xx/ADC/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/ADC/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/ADC/chconf.h b/testhal/STM32L1xx/ADC/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32L1xx/ADC/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/ADC/halconf.h b/testhal/STM32L1xx/ADC/halconf.h new file mode 100644 index 000000000..85a5dbd3b --- /dev/null +++ b/testhal/STM32L1xx/ADC/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c new file mode 100644 index 000000000..9ca4b541f --- /dev/null +++ b/testhal/STM32L1xx/ADC/main.c @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN10. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_4), + 0, /* SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, 0, 0, /* SQR2, SQR3, SQR4 */ + ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN11(ADC_SAMPLE_48) | ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | + ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), + 0, /* SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), + 0, 0, /* SQR2, SQR3 */ + ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + palClearPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + 0, PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the temperature sensor. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + adcSTM32DisableTSVREFE(); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32L1xx/ADC/mcuconf.h b/testhal/STM32L1xx/ADC/mcuconf.h new file mode 100644 index 000000000..f0bf4a0cc --- /dev/null +++ b/testhal/STM32L1xx/ADC/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/ADC/readme.txt b/testhal/STM32L1xx/ADC/readme.txt new file mode 100644 index 000000000..91e9574b3 --- /dev/null +++ b/testhal/STM32L1xx/ADC/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx ADC driver. + +** Board Setup ** + +- Remove the LCD module. +- Connect PC0 to 3.3V and PC1 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/EXT/.cproject b/testhal/STM32L1xx/EXT/.cproject new file mode 100644 index 000000000..2148e6575 --- /dev/null +++ b/testhal/STM32L1xx/EXT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/EXT/.project b/testhal/STM32L1xx/EXT/.project new file mode 100644 index 000000000..c24be83e5 --- /dev/null +++ b/testhal/STM32L1xx/EXT/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/EXT/Makefile b/testhal/STM32L1xx/EXT/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/EXT/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/EXT/chconf.h b/testhal/STM32L1xx/EXT/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32L1xx/EXT/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/EXT/halconf.h b/testhal/STM32L1xx/EXT/halconf.h new file mode 100644 index 000000000..e0e0c38ff --- /dev/null +++ b/testhal/STM32L1xx/EXT/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/EXT/main.c b/testhal/STM32L1xx/EXT/main.c new file mode 100644 index 000000000..c0820d139 --- /dev/null +++ b/testhal/STM32L1xx/EXT/main.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void led4off(void *arg) { + + (void)arg; + palClearPad(GPIOB, GPIOB_LED4); +} + +/* Triggered when the button is pressed or released. The LED4 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + palSetPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led4off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32L1xx/EXT/mcuconf.h b/testhal/STM32L1xx/EXT/mcuconf.h new file mode 100644 index 000000000..753e83df3 --- /dev/null +++ b/testhal/STM32L1xx/EXT/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/EXT/readme.txt b/testhal/STM32L1xx/EXT/readme.txt new file mode 100644 index 000000000..16953a3c9 --- /dev/null +++ b/testhal/STM32L1xx/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/IRQ_STORM/.cproject b/testhal/STM32L1xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..5b23e9f4d --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/IRQ_STORM/.project b/testhal/STM32L1xx/IRQ_STORM/.project new file mode 100644 index 000000000..5cc197397 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/IRQ_STORM/Makefile b/testhal/STM32L1xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/IRQ_STORM/chconf.h b/testhal/STM32L1xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/IRQ_STORM/halconf.h b/testhal/STM32L1xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/IRQ_STORM/main.c b/testhal/STM32L1xx/IRQ_STORM/main.c new file mode 100644 index 000000000..88d575b18 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/main.c @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOB, GPIOB_LED4); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD1, *p++); + } + chSequentialStreamWrite(&SD1, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 1 and GPT drivers 2 and 3. + */ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..e73375db2 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/IRQ_STORM/readme.txt b/testhal/STM32L1xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..9483b1f02 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/PWM-ICU/.cproject b/testhal/STM32L1xx/PWM-ICU/.cproject new file mode 100644 index 000000000..b96ec18ee --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/PWM-ICU/.project b/testhal/STM32L1xx/PWM-ICU/.project new file mode 100644 index 000000000..393dbac2d --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/PWM-ICU/Makefile b/testhal/STM32L1xx/PWM-ICU/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/PWM-ICU/chconf.h b/testhal/STM32L1xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/PWM-ICU/halconf.h b/testhal/STM32L1xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..2f74c82c8 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/PWM-ICU/main.c b/testhal/STM32L1xx/PWM-ICU/main.c new file mode 100644 index 000000000..3ef877831 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/main.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOB, GPIOB_LED4); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOB, GPIOB_LED4); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOB, GPIOB_LED3); + last_width = icuGetWidth(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOB, GPIOB_LED3); + last_period = icuGetPeriod(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA15 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOB, GPIOB_LED3); + palClearPad(GPIOB, GPIOB_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/PWM-ICU/mcuconf.h b/testhal/STM32L1xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..961a41c01 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/PWM-ICU/readme.txt b/testhal/STM32L1xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..52a2dd2ad --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx PWM-ICU drivers. + +** Board Setup ** + +- Remove the LCD module. +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/SPI/.cproject b/testhal/STM32L1xx/SPI/.cproject new file mode 100644 index 000000000..b2bc5eb2d --- /dev/null +++ b/testhal/STM32L1xx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/SPI/.project b/testhal/STM32L1xx/SPI/.project new file mode 100644 index 000000000..aef073cf3 --- /dev/null +++ b/testhal/STM32L1xx/SPI/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/SPI/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/SPI/chconf.h b/testhal/STM32L1xx/SPI/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32L1xx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/SPI/halconf.h b/testhal/STM32L1xx/SPI/halconf.h new file mode 100644 index 000000000..3e1cafbbf --- /dev/null +++ b/testhal/STM32L1xx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c new file mode 100644 index 000000000..da394e97b --- /dev/null +++ b/testhal/STM32L1xx/SPI/main.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (16MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0 +}; + +/* + * Low speed SPI configuration (256kHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palSetPad(GPIOB, GPIOB_LED4); /* LED ON. */ + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ + palClearPad(GPIOB, GPIOB_LED4); /* LED OFF. */ + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI1 I/O pins setup. + */ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/SPI/mcuconf.h b/testhal/STM32L1xx/SPI/mcuconf.h new file mode 100644 index 000000000..a992d3419 --- /dev/null +++ b/testhal/STM32L1xx/SPI/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/SPI/readme.txt b/testhal/STM32L1xx/SPI/readme.txt new file mode 100644 index 000000000..2ce870851 --- /dev/null +++ b/testhal/STM32L1xx/SPI/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx SPI driver. + +** Board Setup ** + +- Remove the LCD module. +- Connect PB14 and PB15 together for SPI loop-back. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/UART/.cproject b/testhal/STM32L1xx/UART/.cproject new file mode 100644 index 000000000..dc7b9ec94 --- /dev/null +++ b/testhal/STM32L1xx/UART/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/UART/.project b/testhal/STM32L1xx/UART/.project new file mode 100644 index 000000000..ac58d7107 --- /dev/null +++ b/testhal/STM32L1xx/UART/.project @@ -0,0 +1,38 @@ + + + STM32L1xx-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32L_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32L1xx/UART/Makefile b/testhal/STM32L1xx/UART/Makefile new file mode 100644 index 000000000..0d3a8e2b2 --- /dev/null +++ b/testhal/STM32L1xx/UART/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/UART/chconf.h b/testhal/STM32L1xx/UART/chconf.h new file mode 100644 index 000000000..2e6fcc6ee --- /dev/null +++ b/testhal/STM32L1xx/UART/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/UART/halconf.h b/testhal/STM32L1xx/UART/halconf.h new file mode 100644 index 000000000..520e71b0a --- /dev/null +++ b/testhal/STM32L1xx/UART/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/UART/main.c b/testhal/STM32L1xx/UART/main.c new file mode 100644 index 000000000..01a8c8cd9 --- /dev/null +++ b/testhal/STM32L1xx/UART/main.c @@ -0,0 +1,144 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromIsr(); + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); + chSysUnlockFromIsr(); +} + +static void ledoff(void *p) { + + (void)p; + palClearPad(GPIOB, GPIOB_LED4); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOB, GPIOB_LED4); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palClearPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1, PA9 and PA10 are routed to USART1. + */ + uartStart(&UARTD1, &uart_cfg_1); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32L1xx/UART/mcuconf.h b/testhal/STM32L1xx/UART/mcuconf.h new file mode 100644 index 000000000..ee338ce96 --- /dev/null +++ b/testhal/STM32L1xx/UART/mcuconf.h @@ -0,0 +1,171 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L1xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/UART/readme.txt b/testhal/STM32L1xx/UART/readme.txt new file mode 100644 index 000000000..5f3edb851 --- /dev/null +++ b/testhal/STM32L1xx/UART/readme.txt @@ -0,0 +1,32 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx UART driver. + +** Board Setup ** + +- Remove the LCD module. +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM8S/SPI/ChibiOS-RT.stw b/testhal/STM8S/SPI/ChibiOS-RT.stw new file mode 100644 index 000000000..a6630271a --- /dev/null +++ b/testhal/STM8S/SPI/ChibiOS-RT.stw @@ -0,0 +1,16 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=cosmic\cosmic.stp +Dependencies= + +[Project1] +Filename=raisonance\raisonance.stp +Dependencies= +[Options] +ActiveProject=cosmic +ActiveConfig=Release +AddSortedElements=0 diff --git a/testhal/STM8S/SPI/cosmic/cosmic.stp b/testhal/STM8S/SPI/cosmic/cosmic.stp new file mode 100644 index 000000000..f45146b03 --- /dev/null +++ b/testhal/STM8S/SPI/cosmic/cosmic.stp @@ -0,0 +1,1947 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=cosmic +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\..\os\kernel\src;..\..\..\..\os\kernel\include;..\..\..\..\os\ports\cosmic\stm8;..\..\..\..\boards\st_stm8s_discovery;..\..\..\..\os\hal\platforms\stm8s;..\..\..\..\os\hal\include;..\..\..\..\os\hal\src;..\..\..\test;..\demo; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,5,25,14,45,56 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,26,17,30,51 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0= +String.6.0=2010,6,4,10,29,4 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg .text -a .const -n .text +String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct +String.102.4=+seg .ubsct -a .bsct -n .ubsct +String.102.5=+seg .bit -a .ubsct -n .bit -id +String.102.6=+seg .share -a .bit -n .share -is +String.102.7=+seg .data -b 0x100 -m 0x700 -n .data +String.102.8=+seg .bss -a .data -n .bss +String.103.0=Code,Constants[0x8080-0xffff]=.const,.text +String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x100-0x7ff]=.data,.bss +String.104.0=0x7ff +String.105.0=libisl0.sm8;libm0.sm8 +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8 +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,5,25,14,45,56 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\..\os\kernel\src;..\..\..\..\os\kernel\include;..\..\..\..\os\ports\cosmic\stm8;..\..\..\..\boards\st_stm8s_discovery;..\..\..\..\os\hal\platforms\stm8s;..\..\..\..\os\hal\include;..\..\..\..\os\hal\src;..\..\..\test;..\demo; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,5,25,14,45,56 +String.100.0=STM8S105C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0= +String.6.0=2010,6,5,11,53,48 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg .text -a .const -n .text +String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct +String.102.4=+seg .ubsct -a .bsct -n .ubsct +String.102.5=+seg .bit -a .ubsct -n .bit -id +String.102.6=+seg .share -a .bit -n .share -is +String.102.7=+seg .data -b 0x100 -m 0x700 -n .data +String.102.8=+seg .bss -a .data -n .bss +String.103.0=Code,Constants[0x8080-0xffff]=.const,.text +String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x100-0x7ff]=.data,.bss +String.104.0=0x7ff +String.105.0=libisl0.sm8;libm0.sm8 +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8 +String.6.0=2010,5,25,14,45,56 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,5,25,14,45,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,5,25,14,45,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Source Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files...\demo\main.c] +ElemType=File +PathName=..\demo\main.c +Next=Root.Source Files.vectors.c + +[Root.Source Files.vectors.c] +ElemType=File +PathName=vectors.c +Next=Root.Source Files.Source Files\board + +[Root.Source Files.Source Files\board] +ElemType=Folder +PathName=Source Files\board +Child=Root.Source Files.Source Files\board...\..\..\..\boards\st_stm8s_discovery\board.c +Next=Root.Source Files.Source Files\os +Config.0=Root.Source Files.Source Files\board.Config.0 +Config.1=Root.Source Files.Source Files\board.Config.1 + +[Root.Source Files.Source Files\board.Config.0] +Settings.0.0=Root.Source Files.Source Files\board.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\board.Config.0.Settings.3 + +[Root.Source Files.Source Files\board.Config.1] +Settings.1.0=Root.Source Files.Source Files\board.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 + +[Root.Source Files.Source Files\board.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Source Files.Source Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\board.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Source Files.Source Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Source Files.Source Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\board...\..\..\..\boards\st_stm8s_discovery\board.c] +ElemType=File +PathName=..\..\..\..\boards\st_stm8s_discovery\board.c + +[Root.Source Files.Source Files\os] +ElemType=Folder +PathName=Source Files\os +Child=Root.Source Files.Source Files\os.Source Files\os\hal + +[Root.Source Files.Source Files\os.Source Files\os\hal] +ElemType=Folder +PathName=Source Files\os\hal +Child=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\..\os\hal\src\adc.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\..\os\hal\include -i..\..\..\..\os\hal\platforms\stm8s -i..\..\..\..\boards\st_stm8s_discovery -i..\..\..\..\os\ports\cosmic\stm8 -i..\..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls 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+PathName=..\..\..\..\os\ports\cosmic\stm8\chcore.h +Next=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\cosmic\stm8\chtypes.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\cosmic\stm8\chtypes.h] +ElemType=File +PathName=..\..\..\..\os\ports\cosmic\stm8\chtypes.h + +[Root.Include Files.Include Files\test] +ElemType=Folder +PathName=Include Files\test \ No newline at end of file diff --git a/testhal/STM8S/SPI/cosmic/vectors.c b/testhal/STM8S/SPI/cosmic/vectors.c new file mode 100644 index 000000000..b6b57dc1d --- /dev/null +++ b/testhal/STM8S/SPI/cosmic/vectors.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Exception handler type. + */ +typedef void @far @interrupt (*interrupt_handler_t)(void); + +/* + * Various external symbols. + */ +void _stext(void); +@far @interrupt void vector10(void); +@far @interrupt void vector13(void); +@far @interrupt void vector17(void); +@far @interrupt void vector18(void); +@far @interrupt void vector20(void); +@far @interrupt void vector21(void); + +/** + * @brief Exception vector type. + */ +typedef struct { + uint8_t ev_instruction; + interrupt_handler_t ev_handler; +} exception_vector_t; + +/** + * @brief Undefined interrupt handler. + * @note It should never be invoked. + */ +@far @interrupt static void vector (void) +{ + return; +} + +/** + * @brief Exceptions table. + */ +exception_vector_t const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, vector}, /* trap */ + {0x82, vector}, /* vector0 */ + {0x82, vector}, /* vector1 */ + {0x82, vector}, /* vector2 */ + {0x82, vector}, /* vector3 */ + {0x82, vector}, /* vector4 */ + {0x82, vector}, /* vector5 */ + {0x82, vector}, /* vector6 */ + {0x82, vector}, /* vector7 */ + {0x82, vector}, /* vector8 */ + {0x82, vector}, /* vector9 */ +#if HAL_USE_SPI && STM8S_SPI_USE_SPI + {0x82, vector10}, +#else + {0x82, vector}, /* vector10 */ +#endif + {0x82, vector}, /* vector11 */ + {0x82, vector}, /* vector12 */ + {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector14 */ + {0x82, vector}, /* vector15 */ + {0x82, vector}, /* vector16 */ +#if HAL_USE_SERIAL && STM8S_SERIAL_USE_UART1 + {0x82, vector17}, /* vector17 */ + {0x82, vector18}, /* vector18 */ +#else + {0x82, vector}, /* vector17 */ + {0x82, vector}, /* vector18 */ +#endif + {0x82, vector}, /* vector19 */ +#if HAL_USE_SERIAL && (STM8S_SERIAL_USE_UART2 || STM8S_SERIAL_USE_UART3) + {0x82, vector20}, /* vector20 */ + {0x82, vector21}, /* vector21 */ +#else + {0x82, vector}, /* vector20 */ + {0x82, vector}, /* vector21 */ +#endif + {0x82, vector}, /* vector22 */ + {0x82, vector}, /* vector23 */ + {0x82, vector}, /* vector24 */ + {0x82, vector}, /* vector25 */ + {0x82, vector}, /* vector26 */ + {0x82, vector}, /* vector27 */ + {0x82, vector}, /* vector28 */ + {0x82, vector}, /* vector29 */ +}; diff --git a/testhal/STM8S/SPI/demo/chconf.h b/testhal/STM8S/SPI/demo/chconf.h new file mode 100644 index 000000000..f943ea80c --- /dev/null +++ b/testhal/STM8S/SPI/demo/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM8S/SPI/demo/halconf.h b/testhal/STM8S/SPI/demo/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/STM8S/SPI/demo/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM8S/SPI/demo/main.c b/testhal/STM8S/SPI/demo/main.c new file mode 100644 index 000000000..b1e8b6ed1 --- /dev/null +++ b/testhal/STM8S/SPI/demo/main.c @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * SPI configuration (8MHz, CPHA=0, CPOL=0, MSb first). + */ +static ROMCONST SPIConfig spicfg = { + NULL, + GPIOD, + PD_LD10, + 0 +}; + +/* + * Transmit data. + */ +static ROMCONST uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +/* + * Receive buffer. + */ +static uint8_t buffer[32]; + +/* + * Application entry point. + */ +void main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * OS initialization. + */ + chSysInit(); + + /* + * Activates the SPI driver 1 using the driver default configuration. + */ + spiStart(&SPID1, &spicfg); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + volatile uint8_t b; + + chThdSleepMilliseconds(1000); + /* Exchanging data, if the pins MISO and MOSI are connected then the + transmitted data is received back into the buffer. On the + STM8S-Discovery board the pins are CN2-9 and CN2-10.*/ + spiSelect(&SPID1); + spiExchange(&SPID1, sizeof(digits), digits, buffer); + /* Polled transfers test.*/ + b = spiPolledExchange(&SPID1, 0x55); + b = spiPolledExchange(&SPID1, 0xAA); + spiUnselect(&SPID1); + } +} diff --git a/testhal/STM8S/SPI/demo/mcuconf.h b/testhal/STM8S/SPI/demo/mcuconf.h new file mode 100644 index 000000000..c09874c9b --- /dev/null +++ b/testhal/STM8S/SPI/demo/mcuconf.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED FALSE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED TRUE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8S_SERIAL_USE_UART1 FALSE +#define STM8S_SERIAL_USE_UART2 TRUE +#define STM8S_SERIAL_USE_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/STM8S/SPI/raisonance/raisonance.stp b/testhal/STM8S/SPI/raisonance/raisonance.stp new file mode 100644 index 000000000..d9e65a4e0 --- /dev/null +++ b/testhal/STM8S/SPI/raisonance/raisonance.stp @@ -0,0 +1,1963 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=raisonance +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,4,10,30,46 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\..\boards\st_stm8s_discovery;..\..\..\..\os\kernel\src;..\..\..\..\os\kernel\include;..\..\..\..\os\hal\include;..\..\..\..\os\hal\platforms\stm8s;..\..\..\..\os\hal\src;..\..\..\test;..\..\..\..\os\ports\rc\stm8; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,4,11,25,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= 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PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,31 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chthreads.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chthreads.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chthreads.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chthreads.c.Config.1 + +[Root.Source Files.Source Files\os.Source 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PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chsys.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source 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Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chsem.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chschd.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source 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Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source 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Files\os\kernel...\..\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chqueues.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source 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Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmsg.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source 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STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmsg.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chmsg.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source 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LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chmempools.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chmemcore.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.1 + 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+[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chmboxes.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chlists.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + 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Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdynamic.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + 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Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c] +ElemType=File +PathName=..\..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\..\os\ports\rc\stm8\chcore.c + +[Root.Include Files] +ElemType=Folder +PathName=Include Files +Child=Root.Include Files...\demo\halconf.h +Config.0=Root.Include Files.Config.0 +Config.1=Root.Include Files.Config.1 + +[Root.Include Files.Config.0] +Settings.0.0=Root.Include Files.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Config.0.Settings.3 + +[Root.Include Files.Config.1] +Settings.1.0=Root.Include Files.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Config.1.Settings.3 + +[Root.Include Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\..\os\ports\RC\stm8) PIN(..\..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\..\os\kernel\include) PIN(..\..\..\..\os\hal\include) PIN(..\..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files...\demo\halconf.h] +ElemType=File +PathName=..\demo\halconf.h +Next=Root.Include Files...\demo\chconf.h + +[Root.Include Files...\demo\chconf.h] +ElemType=File +PathName=..\demo\chconf.h +Next=Root.Include Files...\demo\mcuconf.h + +[Root.Include Files...\demo\mcuconf.h] +ElemType=File +PathName=..\demo\mcuconf.h +Next=Root.Include Files.Include Files\board + +[Root.Include Files.Include Files\board] +ElemType=Folder +PathName=Include Files\board +Child=Root.Include Files.Include Files\board...\..\..\..\boards\st_stm8s_discovery\board.h +Next=Root.Include Files.Include Files\os + +[Root.Include Files.Include Files\board...\..\..\..\boards\st_stm8s_discovery\board.h] +ElemType=File +PathName=..\..\..\..\boards\st_stm8s_discovery\board.h + +[Root.Include Files.Include Files\os] +ElemType=Folder +PathName=Include Files\os +Child=Root.Include Files.Include Files\os.Include Files\os\hal + +[Root.Include Files.Include Files\os.Include Files\os\hal] +ElemType=Folder +PathName=Include Files\os\hal +Child=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\spi.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\serial.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\serial.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\serial.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\pwm.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\pwm.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\pwm.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\pal.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\pal.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\pal.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mmc_spi.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mmc_spi.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\mmc_spi.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mii.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mii.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\mii.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mac.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\mac.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\mac.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\hal.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\hal.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\hal.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\can.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\can.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\can.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\adc.h + +[Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\..\os\hal\include\adc.h] +ElemType=File +PathName=..\..\..\..\os\hal\include\adc.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s] +ElemType=Folder +PathName=Include Files\os\hal\stm8s +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\..\os\hal\platforms\stm8s\spi_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\..\os\hal\platforms\stm8s\spi_lld.h] +ElemType=File +PathName=..\..\..\..\os\hal\platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\..\os\hal\platforms\stm8s\stm8s_type.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include 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+ElemType=Folder +PathName=Include Files\os\port +Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\rc\stm8\chtypes.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\rc\stm8\chtypes.h] +ElemType=File +PathName=..\..\..\..\os\ports\rc\stm8\chtypes.h +Next=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\..\os\ports\rc\stm8\chcore.h] +ElemType=File +PathName=..\..\..\..\os\ports\rc\stm8\chcore.h \ No newline at end of file diff --git a/testhal/common/testbuild/.cproject b/testhal/common/testbuild/.cproject new file mode 100644 index 000000000..1ce473e74 --- /dev/null +++ b/testhal/common/testbuild/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/common/testbuild/.project b/testhal/common/testbuild/.project new file mode 100644 index 000000000..2fd707444 --- /dev/null +++ b/testhal/common/testbuild/.project @@ -0,0 +1,33 @@ + + + HAL-BUILD_TEST + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/common/testbuild/Makefile b/testhal/common/testbuild/Makefile new file mode 100644 index 000000000..280c5f3e3 --- /dev/null +++ b/testhal/common/testbuild/Makefile @@ -0,0 +1,221 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4. +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +#include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/templates/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FPU),yes) + USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE +endif + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/common/testbuild/board.h b/testhal/common/testbuild/board.h new file mode 100644 index 000000000..328950186 --- /dev/null +++ b/testhal/common/testbuild/board.h @@ -0,0 +1,40 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic board. + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC +#define BOARD_NAME "Generic Board" + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/testhal/common/testbuild/chconf.h b/testhal/common/testbuild/chconf.h new file mode 100644 index 000000000..9ba7b1772 --- /dev/null +++ b/testhal/common/testbuild/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/common/testbuild/main.c b/testhal/common/testbuild/main.c new file mode 100644 index 000000000..e295c1e84 --- /dev/null +++ b/testhal/common/testbuild/main.c @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Simulator main. + */ +int main(int argc, char *argv[]) { + + (void)argc; + (void)argv; + + return 0; +} diff --git a/todo.txt b/todo.txt new file mode 100644 index 000000000..2af67c22f --- /dev/null +++ b/todo.txt @@ -0,0 +1,91 @@ +Status: +- = Planned. +X = In progress, some work done. +* = Done. +? = Not sure if worth the effort or useful at all. +N = Decided against. + +Version 2.5.2 +* STM32 CAN2 support. +* Support for ATSAM4L devices. +* Improve support for STM32F3xx devices. +* Update C++ wrapper. +* Support for STM32F37x devices. +X Restructure and improve documentation. +X Improve support for SPC560BC devices. +X Improve support for SPC560P devices. +X Improve support for SPC563M devices. +X Improve support for SPC56EL devices. +- Support for SPC564A devices. +- Support for SPC560D devices. +- Support for STM32L1xx MD and HD devices. +- Support for STM32F427 and STM32F437 devices. +- Support for STM32F429 and STM32F439 devices. + +Within 2.5.x: +X File System infrastructure. + X FatFs wrapper. +- Recursive mutexes. +X Revision of the RTCv2 driver implementation. +X Streaming DAC/I2S driver model and STM32 implementation. +- Specific I2C driver for STM32F0 and newer devices. +- Unified LPC1xxx HAL. + - LPC11xx and LPC13xx HALs merged in the unified one. + - LPC17xx support. +- NUC140 support. +- Create a null device driver implementing a stream interface. +- Add USARTs support to the STM32 SPI driver. +- Add option to use another counter instead of the systick counter into the + trace buffer. +- Add a chSysIntegrityCheck() API to the kernel. +- Add guard pages as extra stack checking mechanism. Guard pages should be + of the same type of the stack alignment type. +- Add a CH_THREAD macro for threads declaration in order to hide + compiler-specific optimizations for thread functions. All demos will have + to be updated. +- Runtime errors manager in HAL. +- Critical errors manager in HAL (to replace or complement assertions). +- Add ADC3 support to the STM32F1xx ADC driver. +? Add the RTC service inside the kernel and port, remove from HAL. + +Within 2.x.x +- Software I2C implementation using a GPT instance for timings. +- Static memory allocation hook macros in kernel code. +X Implement the "transmission end" serial driver event on those platforms + supporting the feature, so far only done in STM32 driver. +- Test suite overhaul, the API should be more generic in order to be used + with different subsystems and not just the kernel. +- Reduce number of demos globally, add demos to a repository or on web site. + Required in order to reduce support effort. +- New device driver models: Clock, Systick, WDG. +- Add UART4 support to the STM32 UART driver (CL line only, HD has a nasty + shared interrupt). +- Shared DMA channels support in the STM8L HAL. +- Device drivers for STM8/STM8L (ADC, PWM, bring them on par with STM32). +- Device drivers for LPC1xxx (ADC, PWM, bring them on par with STM32). +- Implement USB Mass Storage Class support. +- Batch testing of the ARM7/ARMCMx port using OpenOCD, with reports. +X Transactional flash file system implementation. +- Serial over UART complex driver driver, evaluate from the performance + results if to make obsolete the current dedicated Serial driver. +- Official segmented interrupts support and abstraction in CMx port. +- MAC driver revision in order to support copy-less operations, this will + require changes to lwIP or a new TCP/IP stack however. +- Threads Pools manager in the library. +- Dedicated TCP/IP stack. +? Evaluate if change thread functions to return void is worthwhile. +? Add a *very simple* ADC API for single one shot sampling (implement it as + an injected conversion on the STM32). +? Add a switch to enable/disable the priority inheritance algorithm in mutexes. +? ISO7816 driver over UART driver, both reader and card side. +? Merge the Coldfire branch in mainline (hardware missing). +? Merge the H8S branch in mainline (hardware missing). + +Ideas for 3.x.x: +- MMU/MPU support. +- High resolution timers and tickless kernel. +- Multicore support. + +Side projects: +X ChibiOS Wizard, UML modeling and ChibiOS applications code and + documentation generator. diff --git a/tools/gencfg/.externalToolBuilders/FMPP Builder (Linux).launch b/tools/gencfg/.externalToolBuilders/FMPP Builder (Linux).launch new file mode 100644 index 000000000..0a4fc898b --- /dev/null +++ b/tools/gencfg/.externalToolBuilders/FMPP Builder (Linux).launch @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/tools/gencfg/.externalToolBuilders/FMPP Builder (Windows).launch b/tools/gencfg/.externalToolBuilders/FMPP Builder (Windows).launch new file mode 100644 index 000000000..abf46ff08 --- /dev/null +++ b/tools/gencfg/.externalToolBuilders/FMPP Builder (Windows).launch @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/tools/gencfg/.project b/tools/gencfg/.project new file mode 100644 index 000000000..9872c4eef --- /dev/null +++ b/tools/gencfg/.project @@ -0,0 +1,39 @@ + + + _Configuration Tool + + + + + + org.eclipse.ui.externaltools.ExternalToolBuilder + full,incremental, + + + LaunchConfigHandle + <project>/.externalToolBuilders/FMPP Builder (Windows).launch + + + incclean + true + + + + + org.eclipse.ui.externaltools.ExternalToolBuilder + full,incremental, + + + LaunchConfigHandle + <project>/.externalToolBuilders/FMPP Builder (Linux).launch + + + incclean + true + + + + + + + diff --git a/tools/gencfg/config.fmpp b/tools/gencfg/config.fmpp new file mode 100644 index 000000000..0f34b0a03 --- /dev/null +++ b/tools/gencfg/config.fmpp @@ -0,0 +1,10 @@ +# Change the next line to point to the processor you want to use. Processors +# are identified by a file named "config.fmpp" under the "processors" root +# directory. +inheritConfiguration: processors/boards/stm32f4xx/config.fmpp + +# Settings common to all processors. Do not change the following lines. +freemarkerLinks: { + lib: ./lib +} +logFile: ./log.fmpp diff --git a/tools/gencfg/fmpp.sh b/tools/gencfg/fmpp.sh new file mode 100644 index 000000000..b98398702 --- /dev/null +++ b/tools/gencfg/fmpp.sh @@ -0,0 +1,7 @@ +#!/bin/bash +JAVA_HOME=/usr/lib/jvm/java-6-sun +export JAVA_HOME +PATH=$PATH:$JAVA_HOME/bin +export PATH +fmpp -C config.fmpp + diff --git a/tools/gencfg/lib/libcode.ftl b/tools/gencfg/lib/libcode.ftl new file mode 100644 index 000000000..45b94a320 --- /dev/null +++ b/tools/gencfg/lib/libcode.ftl @@ -0,0 +1,316 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] + +<#-- + -- Coding style global settings. + --> +[#assign indentation = " " /] +[#assign fields_align = 24 /] +[#assign define_value_align = 36 /] +[#assign comments_align = 48 /] +[#assign boundary = 80 /] + +[#-- + -- This macro generates a brief description in DoxyGen format. + --] +[#macro EmitDoxygenBrief object=[]] + [#if object.brief[0]??] +[@utils.FormatStringAsText " * @brief " + " * " + utils.WithDot(object.brief[0]?cap_first) + boundary /] + [/#if] +[/#macro] + +[#-- + -- This macro generates a detailed description in DoxyGen format. + --] +[#macro EmitDoxygenDetails object=[]] + [#if object.details[0]??] +[@utils.FormatStringAsText " * @details " + " * " + utils.WithDot(object.details[0]?cap_first) + boundary /] + [/#if] +[/#macro] + +[#-- + -- This macro generates a notes list in DoxyGen format. + --] +[#macro EmitDoxygenNotes object=[]] + [#list object.* as note] + [#if note?node_name == "note"] + [@utils.FormatStringAsText " * @note " + " * " + utils.WithDot(note[0]?cap_first) + boundary /] + [/#if] + [/#list] +[/#macro] + +[#-- + -- This macro generates a pre-requisites list in DoxyGen format. + --] +[#macro EmitDoxygenPrerequisites object=[]] + [#list object.* as pre] + [#if pre?node_name == "pre"] + [@utils.FormatStringAsText " * @pre " + " * " + utils.WithDot(pre[0]?cap_first) + boundary /] + [/#if] + [/#list] +[/#macro] + +[#-- + -- This macro generates a post-requisites list in DoxyGen format. + --] +[#macro EmitDoxygenPostrequisites object=[]] + [#list object.* as post] + [#if post?node_name == "post"] + [@utils.FormatStringAsText " * @post " + " * " + utils.WithDot(post[0]?cap_first) + boundary /] + [/#if] + [/#list] +[/#macro] + +[#-- + -- This macro generates a complete Doxygen documentation comment. + --] +[#macro EmitDoxygenDocumentationComment object=[]] +/** + [@code.EmitDoxygenBrief object /] + [@code.EmitDoxygenDetails object /] + [@code.EmitDoxygenPrerequisites object /] + [@code.EmitDoxygenPostrequisites object /] + [@code.EmitDoxygenNotes object /] + */ +[/#macro] + +[#-- + -- This macro generates the parameters description in DoxyGen format. + --] +[#macro EmitDoxygenParams params=[]] + [#list params as param] + [#local name = (param.@name[0]!"no-name")?trim /] + [#local brief = (param.@brief[0]!"")?trim /] + [#local dir = (param.@dir[0]!"boh")?trim?lower_case /] + [#if dir == "in"] +[@utils.FormatStringAsText " * @param[in] " + " * " + utils.IntelligentDot(name + " " + brief?uncap_first) + boundary /] + [#elseif dir == "out"] +[@utils.FormatStringAsText " * @param[out] " + " * " + utils.IntelligentDot(name + " " + brief?uncap_first) + boundary /] + [#elseif dir == "both"] +[@utils.FormatStringAsText " * @param[in,out] " + " * " + utils.IntelligentDot(name + " " + brief?uncap_first) + boundary /] + [#elseif dir == "boh"] +[@utils.FormatStringAsText " * @param " + " * " + utils.IntelligentDot(name + " " + brief?uncap_first) + boundary /] + [/#if] + [/#list] +[/#macro] + +[#-- + -- This macro generates a return description followed by a retval list + -- in DoxyGen format. + --] +[#macro EmitDoxygenReturn return=[]] + [#if return[0]?? && ((return[0].@type[0]!"void")?trim != "void")] + [#local brief = (return[0].@brief[0]!"")?trim /] + [#if brief != ""] +[@utils.FormatStringAsText " * @return " + " * " + utils.WithDot(brief?cap_first) + boundary /] + [/#if] + [#list return[0].value as value] + [#local label = (value.@name[0]!"no-val")?trim /] + [#local brief = (value.@brief[0]!"")?trim /] +[@utils.FormatStringAsText " * @retval " + " * " + utils.WithDot(label + " " + brief?uncap_first) + boundary /] + [/#list] + [/#if] +[/#macro] + +[#-- + -- This macro generates the inner function code (if present). + --] +[#macro EmitCode code=[]] + [#if function.code[0]?? && (function.code[0]?trim != "")] +${indentation}${function.code[0]?trim} + [/#if] +[/#macro] + +[#-- + -- Returns true if the module exports some functions. + --] +[#function HasPublicFunctions module=[]] + [#local flag = false /] + [#list module.function as function] + [#if (function.@visibility[0]!"private") == "public"] + [#local flag = true /] + [/#if] + [/#list] + [#return flag /] +[/#function] + +[#-- + -- Returns true if the module has static functions. + --] +[#function HasPrivateFunctions module=[]] + [#local flag = false /] + [#list module.function as function] + [#if (function.@visibility[0]!"private") == "private"] + [#local flag = true /] + [/#if] + [/#list] + [#return flag /] +[/#function] + +[#-- + -- This macro generates a function prototype from an XML "function" + -- node passed as parameter. + -- @note Does not generate the final EOL. + --] +[#macro GeneratePrototype function={}] + [#if function.return?? && function.return[0]??] + [#local rettype = (function.return[0].@type[0]!"void")?trim /] + [#else] + [#local rettype = "void" /] + [/#if] + [#local name = (function.@name[0]!"no-name")?trim /] + [#local visibility = (function.@visibility[0]!"private")?trim /] + [#if function.param?? && function.param[0]??] + [#-- If the function has parameters then generates the parameters list --] + [#local l1 = rettype + " " + name + "(" /] + [#if visibility == "private"] + [#local l1 = "static " + l1 /] + [/#if] + [#local ln = ""?right_pad(l1?length) /] + [#list function.param as param] + [#local type = (param.@type[0]!"no-type")?trim /] + [#if type?contains("$")] + [#local pstring = type?replace("$", (param.@name[0]!"no-name")?trim) /] + [#else] + [#local pstring = type + " " + (param.@name[0]!"no-name")?trim /] + [/#if] + [#local dir = (param.@dir[0]!"boh")?trim?lower_case /] + [#if dir == "in"] + [#local pstring = "const " + pstring /] + [/#if] + [#if param_index == 0] + [#local line = l1 + pstring /] + [#else] + [#if (line + ", " + pstring + " ")?length > boundary] +${line + ","} + [#local line = ln + pstring /] + [#else] + [#local line = line + ", " + pstring /] + [/#if] + [/#if] + [/#list] +${line + ")"}[#rt] + [#else] +${rettype + " " + name}(void)[#rt] + [/#if] +[/#macro] + +[#-- + -- This macro generates a function (and its Doxygen documentation) + -- from an XML "function" node passed as parameter. + --] +[#macro GenerateFunction function={}] +/** +[@EmitDoxygenBrief function.@brief /] +[@EmitDoxygenDetails function.details /] +[@EmitDoxygenParams function.param /] +[@EmitDoxygenReturn function.return /] + * + * @note --Implementer notes here (or remove the tag)-- + * @bug --Known problems please here (or remove the tag)-- + * @todo --Implement this function (then remove the tag)-- + */ +[@GeneratePrototype function /] { + [#if function.code[0]??] + [#-- Makes sure to undef the do_code macro --] + [#assign inline = "[#ftl][#macro do_code function][/#macro]"?interpret /] +[@inline /] + [#-- Interprets the code within the code element --] + [#assign inline = function.code[0]?interpret /] +[@inline /] +[@do_code function /] + [#else] + +${indentation}/* ${function.@name[0]!"no-name"}() Implementation here! */ + [/#if] +} +[/#macro] + +[#-- + -- Generates the implementations for the private functions in the specified + -- module. + --] +[#macro GeneratePrivateFunctionsImplementations module] + [#list module.function as function] + [#if (function.@visibility[0]!"private") == "private"] +[@code.GenerateFunction function /] + + [/#if] + [/#list] +[/#macro] + +[#-- + -- Generates the prototypes of the public functions in the specified + -- module. + --] +[#macro GeneratePublicFunctionsPrototypes indentation module] + [#list module.function as function] + [#if (function.@visibility[0]!"private")?trim == "public"] +${indentation}[@code.GeneratePrototype function /]; + [/#if] + [/#list] +[/#macro] + +[#-- + -- Generates the implementations for the public functions in the specified + -- module. + --] +[#macro GeneratePublicFunctionsImplementations module] + [#list module.function as function] + [#if (function.@visibility[0]!"private") == "public"] +[@code.GenerateFunction function /] + + [/#if] + [/#list] +[/#macro] diff --git a/tools/gencfg/lib/liblicense.ftl b/tools/gencfg/lib/liblicense.ftl new file mode 100644 index 000000000..18581ee29 --- /dev/null +++ b/tools/gencfg/lib/liblicense.ftl @@ -0,0 +1,58 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] + +[#-- + -- Emits the ChibiOS/RT standard license exception text. + -- The license exception text is indented by 4 spaces. + --] +[#macro EmitLicenseExceptionAsText] + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +[/#macro] + +[#-- + -- Emits the ChibiOS/RT standard license text. + -- The license text is indented by 4 spaces. + --] +[#macro EmitLicenseAsText] + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +[/#macro] diff --git a/tools/gencfg/lib/libstm32f4xx.ftl b/tools/gencfg/lib/libstm32f4xx.ftl new file mode 100644 index 000000000..81b8f987c --- /dev/null +++ b/tools/gencfg/lib/libstm32f4xx.ftl @@ -0,0 +1,144 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] + +[#-- + -- Emits the STM32F4xx ADC driver constant configuration structures. + --] +[#macro EmitADCConfig config] + [#local cfg_name = config.name[0]?string /] + [@code.EmitDoxygenDocumentationComment config /] +const ADCConfig ${cfg_name} = {0}; + + [#list config.groups.group as group] + [#local grpcfg_name = group.name[0]?string /] + [@code.EmitDoxygenDocumentationComment group /] +const ADCGroupConfig ${grpcfg_name} = { + /* Circular conversion flag.*/ + ${group.circular[0]?string?upper_case}, + /* Number of channels sampled in the conversion group.*/ + ${group.channels_sequence.channel?size}, + /* End of conversion callback or NULL.*/ + [#if group.conv_callback[0]?string?trim == ""] + NULL, + [#else] + ${group.conv_callback[0]?string?trim}, + [/#if] + /* Error callback or NULL.*/ + [#if group.error_callback[0]?string?trim == ""] + NULL, + [#else] + ${group.error_callback[0]?string?trim}, + [/#if] + /* CR1 register initialization value.*/ + [#local resolution = group.resolution[0]?word_list[0]?number /] + [#local cr1 = "ADC_CR1_RESOLUTION_N(" + resolution?string + ")" /] + [#local disc = group.discontinuous[0]?word_list[0]?number /] + [#if disc > 0] + [#local cr1 = cr1 + " | ADC_CR1_DISCEN" /] + [#local cr1 = cr1 + " | ADC_CR1_DISCNUM_N(" + (disc - 1)?string + ")" /] + [/#if] + ${cr1}, + /* CR2 register initialization value.*/ + [#local exten = group.trigger_mode[0]?word_list[0]?number /] + [#local cr2 = "ADC_CR1_EXTEN_N(" + exten?string + ")" /] + [#local extsel = group.trigger_source[0]?word_list[0]?number /] + [#local cr2 = cr2 + " | ADC_CR1_EXSEL_N(" + extsel?string + ")" /] + [#if group.alignment[0]?word_list[0]?number != 0] + [#local cr2 = cr2 + " | ADC_CR2_ALIGN" /] + [/#if] + ${cr2}, + /* Channels sample time settings.*/ + [#local smpr1 = "" /] + [#local smpr2 = "" /] + [#list group.sample_time.* as input] + [#local sinput = input?node_name] + [#if input_index < 9] + [#local smpr2 = smpr2 + "ADC_SMPR2_SMP_" + input?node_name + + "(" + input?string + ") | " /] + [#elseif input_index == 9] + [#local smpr2 = smpr2 + "ADC_SMPR2_SMP_" + input?node_name + + "(" + input?string + ")," /] + [#elseif input_index < 18] + [#local smpr1 = smpr1 + "ADC_SMPR1_SMP_" + input?node_name + + "(" + input?string + ") | " /] + [#else] + [#local smpr1 = smpr1 + "ADC_SMPR1_SMP_" + input?node_name + + "(" + input?string + ")," /] + [/#if] + [/#list] + [@utils.FormatStringAsText " " " " smpr1 80 /] + [@utils.FormatStringAsText " " " " smpr2 80 /] + /* Channels sequence.*/ + [#local sqr1 = "ADC_SQR1_NUM_CH(" + group.channels_sequence?size + ")" /] + [#local sqr2 = "" /] + [#local sqr3 = "" /] + [#list group.channels_sequence.channel as channel] + [#if channel_index <= 5] + [#local sqr3 = sqr3 + "ADC_SQR3_SQ" + (channel_index + 1) + + "_N(" + channel + ")" /] + [#if channel_has_next && channel_index < 5] + [#local sqr3 = sqr3 + " | " /] + [/#if] + [#elseif channel_index <= 11] + [#local sqr2 = sqr2 + "ADC_SQR2_SQ" + (channel_index + 1) + + "_N(" + channel + ")" /] + [#if channel_has_next && channel_index < 11] + [#local sqr2 = sqr2 + " | " /] + [/#if] + [#else] + [#local sqr1 = sqr1 + " | ADC_SQR2_SQ" + (channel_index + 1) + + "_N(" + channel + ")" /] + [/#if] + [/#list] + [#-- SQR2 could be empty.--] + [#if sqr2 == ""] + [#local sqr2 = "0" /] + [/#if] + [#local sqr1 = sqr1 + "," /] + [#local sqr2 = sqr2 + "," /] + [@utils.FormatStringAsText " " " " sqr1 80 /] + [@utils.FormatStringAsText " " " " sqr2 80 /] + [@utils.FormatStringAsText " " " " sqr3 80 /] +}; + [/#list] +[/#macro] + +[#-- + -- Emits the STM32F4xx ADC driver configuration external declarations. + --] +[#macro EmitADCConfigExtern config] + [#local cfg_name = config.name[0]?string /] + [#list config.groups.group as group] + [#local grpcfg_name = group.name[0]?string /] + [#-- Only emits the comment if there is at least a callback defined.--] + /* ADC configuration "${cfg_name}".*/ + extern const ADCConfig ${cfg_name}; + /* ADC conversion group "${grpcfg_name}".*/ + extern const ADCGroupConfig ${grpcfg_name}; + [#if group.conv_callback[0]?string?trim != ""] + void ${group.conv_callback[0]?string?trim}(ADCDriver *, adcsample_t *, size_t); + [/#if] + [#if group.error_callback[0]?string?trim != ""] + void ${group.error_callback[0]?string?trim}(ADCDriver *, adcerror_t); + [/#if] + + [/#list] +[/#macro] diff --git a/tools/gencfg/lib/libutils.ftl b/tools/gencfg/lib/libutils.ftl new file mode 100644 index 000000000..03b0622a3 --- /dev/null +++ b/tools/gencfg/lib/libutils.ftl @@ -0,0 +1,109 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] + +[#-- + -- Returns the trimmed text "s" making sure it is terminated by a dot. + -- The empty string is always returned as an empty string, the dot is not + -- added. + --] +[#function WithDot s] + [#local s = s?trim /] + [#if s == ""] + [#return s /] + [/#if] + [#if s?ends_with(".")] + [#return s /] + [/#if] + [#return s + "." /] +[/#function] + +[#-- + -- Returns the trimmed text "s" making sure it is not terminated by a dot. + --] +[#function WithoutDot s] + [#local s = s?trim /] + [#if s?ends_with(".")] + [#return s?substring(0, s?length - 2) /] + [/#if] + [#return s /] +[/#function] + +[#-- + -- Returns the trimmed text "s" making sure it is terminated by a dot if the + -- text is composed of multiple phrases, if the text is composed of a single + -- phrase then makes sure it is *not* terminated by a dot. + -- A phrase is recognized by the pattern ". " into the text. + -- The empty string is always returned as an empty string, the dot is never + -- added. + --] +[#function IntelligentDot s] + [#local s = s?trim /] + [#if s?contains(". ")] + [#return WithDot(s) /] + [/#if] + [#return WithoutDot(s) /] +[/#function] + +[#-- + -- Formats a text string in a sequence of strings no longer than "len" (first + -- line) or "lenn" (subsequent lines). + -- White spaces are normalized between words, sequences of white spaces become + -- a single space. + --] +[#function StringToText len1 lenn s] + [#local words=s?word_list /] + [#local line="" /] + [#local lines=[] /] + [#list words as word] + [#if lines?size == 0] + [#local len = len1 /] + [#else] + [#local len = lenn /] + [/#if] + [#if (line?length + word?length + 1 > len)] + [#local lines = lines + [line?trim] /] + [#local line = word + " " /] + [#else] + [#local line = line + word + " " /] + [/#if] + [/#list] + [#if line != ""] + [#local lines = lines + [line?trim] /] + [/#if] + [#return lines /] +[/#function] + +[#-- + -- Emits a string "s" as a formatted text, the first line is prefixed by the + -- "p1" parameter, subsequent lines are prefixed by the "pn" paramenter. + -- Emitted lines are no longer than the "len" parameter. + -- White spaces are normalized between words. + --] +[#macro FormatStringAsText p1 pn s len] + [#local lines = StringToText(len - p1?length, len - pn?length, s) /] + [#list lines as line] + [#if line_index == 0] +${p1}${line} + [#else] +${pn}${line} + [/#if] + [/#list] +[/#macro] diff --git a/tools/gencfg/processors/boards/stm32f4xx/config.fmpp b/tools/gencfg/processors/boards/stm32f4xx/config.fmpp new file mode 100644 index 000000000..970d936ca --- /dev/null +++ b/tools/gencfg/processors/boards/stm32f4xx/config.fmpp @@ -0,0 +1,5 @@ +sourceRoot: templates +outputRoot: output +data: { + doc1: xml(../input/stm32f4board.xml) +} diff --git a/tools/gencfg/processors/boards/stm32f4xx/templates/board.c.ftl b/tools/gencfg/processors/boards/stm32f4xx/templates/board.c.ftl new file mode 100644 index 000000000..f38fd106a --- /dev/null +++ b/tools/gencfg/processors/boards/stm32f4xx/templates/board.c.ftl @@ -0,0 +1,139 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[@pp.changeOutputFile name="board.c" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +[#if doc1.board.board_functions.__early_init[0]??] + ${doc1.board.board_functions.__early_init[0]} +[/#if] +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??] +${doc1.board.board_functions.sdc_lld_is_card_inserted[0]} +[#else] + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +[/#if] +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??] +${doc1.board.board_functions.sdc_lld_is_write_protected[0]} +[#else] + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +[/#if] +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??] +${doc1.board.board_functions.mmc_lld_is_card_inserted[0]} +[#else] + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +[/#if] +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??] +${doc1.board.board_functions.mmc_lld_is_write_protected[0]} +[#else] + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +[/#if] +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/tools/gencfg/processors/boards/stm32f4xx/templates/board.h.ftl b/tools/gencfg/processors/boards/stm32f4xx/templates/board.h.ftl new file mode 100644 index 000000000..c24c0a355 --- /dev/null +++ b/tools/gencfg/processors/boards/stm32f4xx/templates/board.h.ftl @@ -0,0 +1,327 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[@pp.changeOutputFile name="board.h" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for ${doc1.board.board_name[0]} board. + */ + +/* + * Board identifier. + */ +#define BOARD_${doc1.board.board_id[0]} +#define BOARD_NAME "${doc1.board.board_name[0]}" + +[#if doc1.board.ethernet_phy[0]??] +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]} +[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"] +#define BOARD_PHY_RMII +[/#if] +[/#if] + +/* + * Board oscillators-related settings. +[#if doc1.board.clocks.@LSEFrequency[0]?number == 0] + * NOTE: LSE not fitted. +[/#if] +[#if doc1.board.clocks.@HSEFrequency[0]?number == 0] + * NOTE: HSE not fitted. +[/#if] + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]} +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]} +#endif + +[#if doc1.board.clocks.@HSEBypass[0]?string == "true"] +#define STM32_HSE_BYPASS +[/#if] + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD ${doc1.board.clocks.@VDD[0]} + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +[#list doc1.board.ports.* as port] + [#assign port_name = port?node_name?upper_case /] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] +#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string} + [/#list] + +[/#list] +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +[#list doc1.board.ports.* as port] + [#assign port_name = port?node_name?upper_case /] +/* + * ${port_name} setup: + * + [#-- Generating pin descriptions inside the comment.--] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign mode = pin.@Mode[0] /] + [#assign type = pin.@Type[0] /] + [#assign resistor = pin.@Resistor[0] /] + [#assign speed = pin.@Speed[0] /] + [#assign alternate = pin.@Alternate[0] /] + [#if mode == "Input"] + [#assign desc = mode + " " + resistor /] + [#elseif mode == "Output"] + [#assign desc = mode + " " + type + " " + speed /] + [#elseif mode == "Alternate"] + [#assign desc = mode + " " + alternate /] + [#else] + [#assign desc = "Analog" /] + [/#if] + * P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}). + [/#list] + */ + [#-- + -- Generating MODER register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign mode = pin.@Mode[0] /] + [#if mode == "Input"] + [#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /] + [#elseif mode == "Output"] + [#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /] + [#elseif mode == "Alternate"] + [#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_MODER (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating OTYPER register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign type = pin.@Type[0] /] + [#if type == "PushPull"] + [#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating SPEEDR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign speed = pin.@Speed[0] /] + [#if speed == "Minimum"] + [#assign out = "PIN_OSPEED_2M(" + port_name + "_" + name + ")" /] + [#elseif speed == "Low"] + [#assign out = "PIN_OSPEED_25M(" + port_name + "_" + name + ")" /] + [#elseif speed == "High"] + [#assign out = "PIN_OSPEED_50M(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_OSPEED_100M(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating PUPDR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign resistor = pin.@Resistor[0] /] + [#if resistor == "Floating"] + [#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /] + [#elseif resistor == "PullUp"] + [#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating ODR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign level = pin.@Level[0] /] + [#if level == "Low"] + [#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_ODR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating AFRx registers values. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign alternate = pin.@Alternate[0]?trim /] + [#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + ")" /] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_AFRL (" + out /] + [#elseif pin_index == 8] + [#assign line = "#define VAL_" + port_name + "_AFRH (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if (pin_index == 7) || (pin_index == 15)] +${line + ")"} + [#else] +${(line + " |")?right_pad(76, " ") + "\\"} + [/#if] + [/#list] + +[/#list] + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/tools/gencfg/processors/boards/stm32f4xx/templates/board.mk.ftl b/tools/gencfg/processors/boards/stm32f4xx/templates/board.mk.ftl new file mode 100644 index 000000000..c88471ac3 --- /dev/null +++ b/tools/gencfg/processors/boards/stm32f4xx/templates/board.mk.ftl @@ -0,0 +1,28 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[@pp.changeOutputFile name="board.mk" /] +# List of all the board related files. +BOARDSRC = ${'$'}{CHIBIOS}/boards/${doc1.board.board_id[0]}/board.c + +# Required include directories +BOARDINC = ${'$'}{CHIBIOS}/boards/${doc1.board.board_id[0]} diff --git a/tools/gencfg/processors/hal/stm32f4xx/config.fmpp b/tools/gencfg/processors/hal/stm32f4xx/config.fmpp new file mode 100644 index 000000000..307a6f61c --- /dev/null +++ b/tools/gencfg/processors/hal/stm32f4xx/config.fmpp @@ -0,0 +1,5 @@ +sourceRoot: templates +outputRoot: output +data: { + doc1: xml(../input/stm32f4xx_cfg.xml) +} diff --git a/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.c.ftl b/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.c.ftl new file mode 100644 index 000000000..eeea09d99 --- /dev/null +++ b/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.c.ftl @@ -0,0 +1,66 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[#import "/@lib/libcode.ftl" as code /] +[#import "/@lib/libstm32f4xx.ftl" as stm32f4xx /] +[#assign fname = doc1.configuration.name[0] /] +[@pp.changeOutputFile name = fname + ".c" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#include "ch.h" +#include "hal.h" + +#include "${fname + ".h"}" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +[#list doc1.configuration.configs.* as config] + [#assign config_type = config?node_name /] + [#if config_type == "adc_config"] + [@stm32f4xx.EmitADCConfig config /] + [/#if] + +[/#list] +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ diff --git a/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.h.ftl b/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.h.ftl new file mode 100644 index 000000000..47ea70f7c --- /dev/null +++ b/tools/gencfg/processors/hal/stm32f4xx/templates/hal_cfg.h.ftl @@ -0,0 +1,72 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[#import "/@lib/libcode.ftl" as code /] +[#import "/@lib/libstm32f4xx.ftl" as stm32f4xx /] +[#assign fname = doc1.configuration.name[0] /] +[@pp.changeOutputFile name = fname + ".h" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#ifndef _${fname?upper_case}_H_ +#define _${fname?upper_case}_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +[#list doc1.configuration.configs.* as config] + [#assign config_type = config?node_name /] + [#if config_type == "adc_config"] + [@stm32f4xx.EmitADCConfigExtern config /] + [/#if] +[/#list] +#ifdef __cplusplus +} +#endif + +#endif /* _${fname?upper_case}_H_ */ diff --git a/tools/gencfg/processors/processors.xml b/tools/gencfg/processors/processors.xml new file mode 100644 index 000000000..cac95cc23 --- /dev/null +++ b/tools/gencfg/processors/processors.xml @@ -0,0 +1,14 @@ + + + STM32F4xx Board Configuration + resources/gencfg/processors/boards/stm32f4xx/templates + resources/gencfg/xml/stm32f4board.xml + board + + + STM32F0xx Board Configuration + resources/gencfg/processors/boards/stm32f0xx/templates + resources/gencfg/xml/stm32f0board.xml + board + + diff --git a/tools/gencfg/readme.txt b/tools/gencfg/readme.txt new file mode 100644 index 000000000..5b2b58ba4 --- /dev/null +++ b/tools/gencfg/readme.txt @@ -0,0 +1,14 @@ +***************************************************************************** +*** Files Organization *** +***************************************************************************** + +--{root} - Configuration Generator tool. + +--readme.txt - This file. + +--config.fmpp - Tool configuration file, tool setup is done here. + +--run.bat - Tool runner batch file. + +--lib/ - FTL library files. + +--processors/ - Various configuration generators. + +--schema/ - Schema files used to validate XML configurations. + +--xml/ - Templates of configuration files. + +Write requirements and setup documentation here. diff --git a/tools/gencfg/run.bat b/tools/gencfg/run.bat new file mode 100644 index 000000000..460783f39 --- /dev/null +++ b/tools/gencfg/run.bat @@ -0,0 +1 @@ +fmpp -C config.fmpp diff --git a/tools/gencfg/schema/boards/abstract_board.xsd b/tools/gencfg/schema/boards/abstract_board.xsd new file mode 100644 index 000000000..c4c953240 --- /dev/null +++ b/tools/gencfg/schema/boards/abstract_board.xsd @@ -0,0 +1,68 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/boards/stm32f4xx_board.xsd b/tools/gencfg/schema/boards/stm32f4xx_board.xsd new file mode 100644 index 000000000..ace3b5acb --- /dev/null +++ b/tools/gencfg/schema/boards/stm32f4xx_board.xsd @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/common/doc.xsd b/tools/gencfg/schema/common/doc.xsd new file mode 100644 index 000000000..e5be361d5 --- /dev/null +++ b/tools/gencfg/schema/common/doc.xsd @@ -0,0 +1,108 @@ + + + + + + + >Generic item with optional name and brief + description + + + + + + Name of the object. + + + + + + + + + + + + + + + + >Something that can have a detailed description + attached + + + + + + + + + Brief description of the object. + + + + + + + + + + + + + + Object documentation as text, does not preserve + formatting. + + + + + + + + + + + + Object pre-requisites as text, does not preserve + formatting. + + + + + + + + + + + + Object post-requisites as text, does not preserve + formatting. + + + + + + + + + + + + Object note as text, does not preserve formatting. + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/common/stm32/stm32_gpiov2_port.xsd b/tools/gencfg/schema/common/stm32/stm32_gpiov2_port.xsd new file mode 100644 index 000000000..c3ac59487 --- /dev/null +++ b/tools/gencfg/schema/common/stm32/stm32_gpiov2_port.xsd @@ -0,0 +1,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Object representing an STM32 pin for the GPIOv2 + peripheral. + + + + + Pin identifier, used to generate a #define with the + pin name. + + + + + + + + + + + + + + + + Pin mode, as defined for MODER register. + + + + + + + + + + + + + + Logic level for the ODR register. + + + + + + + + + + + + Pin speed as defined in SPEEDR register. + + + + + + + + + + + + + + + Pin type as defined in TYPER register. + + + + + + + + + + + + + Pin pull-up/down resistor as defined in PUDR register. + + + + + + + + + + + + + + Pin alternate function number, only valid if + "Alternate" is selected + in the Mode attribute. + + + + + + + + + + + + diff --git a/tools/gencfg/schema/hal/abstract_adc_cfg.xsd b/tools/gencfg/schema/hal/abstract_adc_cfg.xsd new file mode 100644 index 000000000..52a6c9096 --- /dev/null +++ b/tools/gencfg/schema/hal/abstract_adc_cfg.xsd @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/hal/abstract_cfg.xsd b/tools/gencfg/schema/hal/abstract_cfg.xsd new file mode 100644 index 000000000..72491eea9 --- /dev/null +++ b/tools/gencfg/schema/hal/abstract_cfg.xsd @@ -0,0 +1,344 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/hal/abstract_driver_cfg.xsd b/tools/gencfg/schema/hal/abstract_driver_cfg.xsd new file mode 100644 index 000000000..d6501ff2a --- /dev/null +++ b/tools/gencfg/schema/hal/abstract_driver_cfg.xsd @@ -0,0 +1,12 @@ + + + + + + + + + + + diff --git a/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_adc_cfg.xsd b/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_adc_cfg.xsd new file mode 100644 index 000000000..331933109 --- /dev/null +++ b/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_adc_cfg.xsd @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_cfg.xsd b/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_cfg.xsd new file mode 100644 index 000000000..f846403f3 --- /dev/null +++ b/tools/gencfg/schema/hal/stm32f4xx/stm32f4xx_cfg.xsd @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/xml/stm32f0board.xml b/tools/gencfg/xml/stm32f0board.xml new file mode 100644 index 000000000..64420371f --- /dev/null +++ b/tools/gencfg/xml/stm32f0board.xml @@ -0,0 +1,665 @@ + + + + -----human readable board name----- + BOARD_IDENTIFIER + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/xml/stm32f4board.xml b/tools/gencfg/xml/stm32f4board.xml new file mode 100644 index 000000000..0c6b42106 --- /dev/null +++ b/tools/gencfg/xml/stm32f4board.xml @@ -0,0 +1,1190 @@ + + + + -----human readable board name----- + BOARD_IDENTIFIER + + + MII_KS8721_ID + RMII + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/gencfg/xml/stm32f4xx_cfg.xml b/tools/gencfg/xml/stm32f4xx_cfg.xml new file mode 100644 index 000000000..896cc2614 --- /dev/null +++ b/tools/gencfg/xml/stm32f4xx_cfg.xml @@ -0,0 +1,52 @@ + + + + hal_configs + Application HAL-related settings. + + + adccfg1 + Example ADC configuration. + + + adcgrpcfg1 + Example ADC conversion group configuration. + true + conv_callback + error_callback + 0 Samples are Right Aligned + 0 12 bits + 0 Software + 0 Timer 1 CC1 event + 2 Two discontinous conversions + + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + ADC_SAMPLE_3 + + + ADC_CHANNEL_IN0 + ADC_CHANNEL_IN8 + + + + + +